1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/Constants.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Instructions.h"
20 #include "llvm/Intrinsics.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
39 ViewDAGs("view-isel-dags", cl::Hidden,
40 cl::desc("Pop up a window to show isel dags as they are selected"));
42 static const bool ViewDAGS = 0;
46 //===--------------------------------------------------------------------===//
47 /// FunctionLoweringInfo - This contains information that is global to a
48 /// function that is used when lowering a region of the function.
49 class FunctionLoweringInfo {
56 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
58 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
59 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
61 /// ValueMap - Since we emit code for the function a basic block at a time,
62 /// we must remember which virtual registers hold the values for
63 /// cross-basic-block values.
64 std::map<const Value*, unsigned> ValueMap;
66 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
67 /// the entry block. This allows the allocas to be efficiently referenced
68 /// anywhere in the function.
69 std::map<const AllocaInst*, int> StaticAllocaMap;
71 /// BlockLocalArguments - If any arguments are only used in a single basic
72 /// block, and if the target can access the arguments without side-effects,
73 /// avoid emitting CopyToReg nodes for those arguments. This map keeps
74 /// track of which arguments are local to each BB.
75 std::multimap<BasicBlock*, std::pair<Argument*,
76 unsigned> > BlockLocalArguments;
79 unsigned MakeReg(MVT::ValueType VT) {
80 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
83 unsigned CreateRegForValue(const Value *V) {
84 MVT::ValueType VT = TLI.getValueType(V->getType());
85 // The common case is that we will only create one register for this
86 // value. If we have that case, create and return the virtual register.
87 unsigned NV = TLI.getNumElements(VT);
89 // If we are promoting this value, pick the next largest supported type.
90 return MakeReg(TLI.getTypeToTransformTo(VT));
93 // If this value is represented with multiple target registers, make sure
94 // to create enough consequtive registers of the right (smaller) type.
95 unsigned NT = VT-1; // Find the type to use.
96 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
99 unsigned R = MakeReg((MVT::ValueType)NT);
100 for (unsigned i = 1; i != NV; ++i)
101 MakeReg((MVT::ValueType)NT);
105 unsigned InitializeRegForValue(const Value *V) {
106 unsigned &R = ValueMap[V];
107 assert(R == 0 && "Already initialized this value register!");
108 return R = CreateRegForValue(V);
113 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
114 /// PHI nodes or outside of the basic block that defines it.
115 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
116 if (isa<PHINode>(I)) return true;
117 BasicBlock *BB = I->getParent();
118 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
119 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
124 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
125 Function &fn, MachineFunction &mf)
126 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
128 // Initialize the mapping of values to registers. This is only set up for
129 // instruction values that are used outside of the block that defines
131 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); AI != E; ++AI)
132 InitializeRegForValue(AI);
134 Function::iterator BB = Fn.begin(), E = Fn.end();
135 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
136 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
137 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
138 const Type *Ty = AI->getAllocatedType();
139 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
140 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
141 TySize *= CUI->getValue(); // Get total allocated size.
142 StaticAllocaMap[AI] =
143 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
146 for (; BB != E; ++BB)
147 for (BasicBlock::iterator I = BB->begin(), e = BB->end(); I != e; ++I)
148 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
149 if (!isa<AllocaInst>(I) ||
150 !StaticAllocaMap.count(cast<AllocaInst>(I)))
151 InitializeRegForValue(I);
153 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
154 // also creates the initial PHI MachineInstrs, though none of the input
155 // operands are populated.
156 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
157 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
159 MF.getBasicBlockList().push_back(MBB);
161 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
164 for (BasicBlock::iterator I = BB->begin();
165 (PN = dyn_cast<PHINode>(I)); ++I)
166 if (!PN->use_empty()) {
167 unsigned NumElements =
168 TLI.getNumElements(TLI.getValueType(PN->getType()));
169 unsigned PHIReg = ValueMap[PN];
170 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
171 for (unsigned i = 0; i != NumElements; ++i)
172 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
179 //===----------------------------------------------------------------------===//
180 /// SelectionDAGLowering - This is the common target-independent lowering
181 /// implementation that is parameterized by a TargetLowering object.
182 /// Also, targets can overload any lowering method.
185 class SelectionDAGLowering {
186 MachineBasicBlock *CurMBB;
188 std::map<const Value*, SDOperand> NodeMap;
190 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
191 /// them up and then emit token factor nodes when possible. This allows us to
192 /// get simple disambiguation between loads without worrying about alias
194 std::vector<SDOperand> PendingLoads;
197 // TLI - This is information that describes the available target features we
198 // need for lowering. This indicates when operations are unavailable,
199 // implemented with a libcall, etc.
202 const TargetData &TD;
204 /// FuncInfo - Information about the function as a whole.
206 FunctionLoweringInfo &FuncInfo;
208 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
209 FunctionLoweringInfo &funcinfo)
210 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
214 /// getRoot - Return the current virtual root of the Selection DAG.
216 SDOperand getRoot() {
217 if (PendingLoads.empty())
218 return DAG.getRoot();
220 if (PendingLoads.size() == 1) {
221 SDOperand Root = PendingLoads[0];
223 PendingLoads.clear();
227 // Otherwise, we have to make a token factor node.
228 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
229 PendingLoads.clear();
234 void visit(Instruction &I) { visit(I.getOpcode(), I); }
236 void visit(unsigned Opcode, User &I) {
238 default: assert(0 && "Unknown instruction type encountered!");
240 // Build the switch statement using the Instruction.def file.
241 #define HANDLE_INST(NUM, OPCODE, CLASS) \
242 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
243 #include "llvm/Instruction.def"
247 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
250 SDOperand getIntPtrConstant(uint64_t Val) {
251 return DAG.getConstant(Val, TLI.getPointerTy());
254 SDOperand getValue(const Value *V) {
255 SDOperand &N = NodeMap[V];
258 MVT::ValueType VT = TLI.getValueType(V->getType());
259 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V)))
260 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
261 visit(CE->getOpcode(), *CE);
262 assert(N.Val && "visit didn't populate the ValueMap!");
264 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
265 return N = DAG.getGlobalAddress(GV, VT);
266 } else if (isa<ConstantPointerNull>(C)) {
267 return N = DAG.getConstant(0, TLI.getPointerTy());
268 } else if (isa<UndefValue>(C)) {
269 return N = DAG.getNode(ISD::UNDEF, VT);
270 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
271 return N = DAG.getConstantFP(CFP->getValue(), VT);
273 // Canonicalize all constant ints to be unsigned.
274 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
277 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
278 std::map<const AllocaInst*, int>::iterator SI =
279 FuncInfo.StaticAllocaMap.find(AI);
280 if (SI != FuncInfo.StaticAllocaMap.end())
281 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
284 std::map<const Value*, unsigned>::const_iterator VMI =
285 FuncInfo.ValueMap.find(V);
286 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
288 return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode());
291 const SDOperand &setValue(const Value *V, SDOperand NewN) {
292 SDOperand &N = NodeMap[V];
293 assert(N.Val == 0 && "Already set a value for this node!");
297 // Terminator instructions.
298 void visitRet(ReturnInst &I);
299 void visitBr(BranchInst &I);
300 void visitUnreachable(UnreachableInst &I) { /* noop */ }
302 // These all get lowered before this pass.
303 void visitSwitch(SwitchInst &I) { assert(0 && "TODO"); }
304 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
305 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
308 void visitBinary(User &I, unsigned Opcode);
309 void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
310 void visitSub(User &I);
311 void visitMul(User &I) { visitBinary(I, ISD::MUL); }
312 void visitDiv(User &I) {
313 visitBinary(I, I.getType()->isUnsigned() ? ISD::UDIV : ISD::SDIV);
315 void visitRem(User &I) {
316 visitBinary(I, I.getType()->isUnsigned() ? ISD::UREM : ISD::SREM);
318 void visitAnd(User &I) { visitBinary(I, ISD::AND); }
319 void visitOr (User &I) { visitBinary(I, ISD::OR); }
320 void visitXor(User &I) { visitBinary(I, ISD::XOR); }
321 void visitShl(User &I) { visitBinary(I, ISD::SHL); }
322 void visitShr(User &I) {
323 visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
326 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
327 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ); }
328 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE); }
329 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE); }
330 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE); }
331 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
332 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
334 void visitGetElementPtr(User &I);
335 void visitCast(User &I);
336 void visitSelect(User &I);
339 void visitMalloc(MallocInst &I);
340 void visitFree(FreeInst &I);
341 void visitAlloca(AllocaInst &I);
342 void visitLoad(LoadInst &I);
343 void visitStore(StoreInst &I);
344 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
345 void visitCall(CallInst &I);
347 void visitVAStart(CallInst &I);
348 void visitVANext(VANextInst &I);
349 void visitVAArg(VAArgInst &I);
350 void visitVAEnd(CallInst &I);
351 void visitVACopy(CallInst &I);
352 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
354 void visitMemIntrinsic(CallInst &I, unsigned Op);
356 void visitUserOp1(Instruction &I) {
357 assert(0 && "UserOp1 should not exist at instruction selection time!");
360 void visitUserOp2(Instruction &I) {
361 assert(0 && "UserOp2 should not exist at instruction selection time!");
365 } // end namespace llvm
367 void SelectionDAGLowering::visitRet(ReturnInst &I) {
368 if (I.getNumOperands() == 0) {
369 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
373 SDOperand Op1 = getValue(I.getOperand(0));
374 MVT::ValueType TmpVT;
376 switch (Op1.getValueType()) {
377 default: assert(0 && "Unknown value type!");
382 // If this is a machine where 32-bits is legal or expanded, promote to
383 // 32-bits, otherwise, promote to 64-bits.
384 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
385 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
389 // Extend integer types to result type.
390 if (I.getOperand(0)->getType()->isSigned())
391 Op1 = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, Op1);
393 Op1 = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, Op1);
396 // Extend float to double.
397 Op1 = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op1);
401 break; // No extension needed!
404 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot(), Op1));
407 void SelectionDAGLowering::visitBr(BranchInst &I) {
408 // Update machine-CFG edges.
409 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
411 // Figure out which block is immediately after the current one.
412 MachineBasicBlock *NextBlock = 0;
413 MachineFunction::iterator BBI = CurMBB;
414 if (++BBI != CurMBB->getParent()->end())
417 if (I.isUnconditional()) {
418 // If this is not a fall-through branch, emit the branch.
419 if (Succ0MBB != NextBlock)
420 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
421 DAG.getBasicBlock(Succ0MBB)));
423 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
425 SDOperand Cond = getValue(I.getCondition());
426 if (Succ1MBB == NextBlock) {
427 // If the condition is false, fall through. This means we should branch
428 // if the condition is true to Succ #0.
429 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
430 Cond, DAG.getBasicBlock(Succ0MBB)));
431 } else if (Succ0MBB == NextBlock) {
432 // If the condition is true, fall through. This means we should branch if
433 // the condition is false to Succ #1. Invert the condition first.
434 SDOperand True = DAG.getConstant(1, Cond.getValueType());
435 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
436 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
437 Cond, DAG.getBasicBlock(Succ1MBB)));
439 std::vector<SDOperand> Ops;
440 Ops.push_back(getRoot());
442 Ops.push_back(DAG.getBasicBlock(Succ0MBB));
443 Ops.push_back(DAG.getBasicBlock(Succ1MBB));
444 DAG.setRoot(DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops));
449 void SelectionDAGLowering::visitSub(User &I) {
451 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
452 if (CFP->isExactlyValue(-0.0)) {
453 SDOperand Op2 = getValue(I.getOperand(1));
454 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
458 visitBinary(I, ISD::SUB);
461 void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode) {
462 SDOperand Op1 = getValue(I.getOperand(0));
463 SDOperand Op2 = getValue(I.getOperand(1));
465 if (isa<ShiftInst>(I))
466 Op2 = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), Op2);
468 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
471 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
472 ISD::CondCode UnsignedOpcode) {
473 SDOperand Op1 = getValue(I.getOperand(0));
474 SDOperand Op2 = getValue(I.getOperand(1));
475 ISD::CondCode Opcode = SignedOpcode;
476 if (I.getOperand(0)->getType()->isUnsigned())
477 Opcode = UnsignedOpcode;
478 setValue(&I, DAG.getSetCC(Opcode, MVT::i1, Op1, Op2));
481 void SelectionDAGLowering::visitSelect(User &I) {
482 SDOperand Cond = getValue(I.getOperand(0));
483 SDOperand TrueVal = getValue(I.getOperand(1));
484 SDOperand FalseVal = getValue(I.getOperand(2));
485 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
489 void SelectionDAGLowering::visitCast(User &I) {
490 SDOperand N = getValue(I.getOperand(0));
491 MVT::ValueType SrcTy = TLI.getValueType(I.getOperand(0)->getType());
492 MVT::ValueType DestTy = TLI.getValueType(I.getType());
494 if (N.getValueType() == DestTy) {
495 setValue(&I, N); // noop cast.
496 } else if (isInteger(SrcTy)) {
497 if (isInteger(DestTy)) { // Int -> Int cast
498 if (DestTy < SrcTy) // Truncating cast?
499 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestTy, N));
500 else if (I.getOperand(0)->getType()->isSigned())
501 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestTy, N));
503 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestTy, N));
504 } else { // Int -> FP cast
505 if (I.getOperand(0)->getType()->isSigned())
506 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestTy, N));
508 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestTy, N));
511 assert(isFloatingPoint(SrcTy) && "Unknown value type!");
512 if (isFloatingPoint(DestTy)) { // FP -> FP cast
513 if (DestTy < SrcTy) // Rounding cast?
514 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestTy, N));
516 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestTy, N));
517 } else { // FP -> Int cast.
518 if (I.getType()->isSigned())
519 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestTy, N));
521 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestTy, N));
526 void SelectionDAGLowering::visitGetElementPtr(User &I) {
527 SDOperand N = getValue(I.getOperand(0));
528 const Type *Ty = I.getOperand(0)->getType();
529 const Type *UIntPtrTy = TD.getIntPtrType();
531 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
534 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
535 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
538 uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field];
539 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
540 getIntPtrConstant(Offset));
542 Ty = StTy->getElementType(Field);
544 Ty = cast<SequentialType>(Ty)->getElementType();
545 if (!isa<Constant>(Idx) || !cast<Constant>(Idx)->isNullValue()) {
546 // N = N + Idx * ElementSize;
547 uint64_t ElementSize = TD.getTypeSize(Ty);
548 SDOperand IdxN = getValue(Idx), Scale = getIntPtrConstant(ElementSize);
550 // If the index is smaller or larger than intptr_t, truncate or extend
552 if (IdxN.getValueType() < Scale.getValueType()) {
553 if (Idx->getType()->isSigned())
554 IdxN = DAG.getNode(ISD::SIGN_EXTEND, Scale.getValueType(), IdxN);
556 IdxN = DAG.getNode(ISD::ZERO_EXTEND, Scale.getValueType(), IdxN);
557 } else if (IdxN.getValueType() > Scale.getValueType())
558 IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN);
560 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
561 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
568 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
569 // If this is a fixed sized alloca in the entry block of the function,
570 // allocate it statically on the stack.
571 if (FuncInfo.StaticAllocaMap.count(&I))
572 return; // getValue will auto-populate this.
574 const Type *Ty = I.getAllocatedType();
575 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
576 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
578 SDOperand AllocSize = getValue(I.getArraySize());
579 MVT::ValueType IntPtr = TLI.getPointerTy();
580 if (IntPtr < AllocSize.getValueType())
581 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
582 else if (IntPtr > AllocSize.getValueType())
583 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
585 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
586 getIntPtrConstant(TySize));
588 // Handle alignment. If the requested alignment is less than or equal to the
589 // stack alignment, ignore it and round the size of the allocation up to the
590 // stack alignment size. If the size is greater than the stack alignment, we
591 // note this in the DYNAMIC_STACKALLOC node.
592 unsigned StackAlign =
593 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
594 if (Align <= StackAlign) {
596 // Add SA-1 to the size.
597 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
598 getIntPtrConstant(StackAlign-1));
599 // Mask out the low bits for alignment purposes.
600 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
601 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
604 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, AllocSize.getValueType(),
605 getRoot(), AllocSize,
606 getIntPtrConstant(Align));
607 DAG.setRoot(setValue(&I, DSA).getValue(1));
609 // Inform the Frame Information that we have just allocated a variable-sized
611 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
615 void SelectionDAGLowering::visitLoad(LoadInst &I) {
616 SDOperand Ptr = getValue(I.getOperand(0));
622 // Do not serialize non-volatile loads against each other.
623 Root = DAG.getRoot();
626 SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr, DAG.getSrcValue(&I));
630 DAG.setRoot(L.getValue(1));
632 PendingLoads.push_back(L.getValue(1));
636 void SelectionDAGLowering::visitStore(StoreInst &I) {
637 Value *SrcV = I.getOperand(0);
638 SDOperand Src = getValue(SrcV);
639 SDOperand Ptr = getValue(I.getOperand(1));
640 // DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr));
641 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr, DAG.getSrcValue(&I)));
644 void SelectionDAGLowering::visitCall(CallInst &I) {
645 const char *RenameFn = 0;
646 if (Function *F = I.getCalledFunction())
648 switch (F->getIntrinsicID()) {
649 case 0: // Not an LLVM intrinsic.
650 if (F->getName() == "fabs" || F->getName() == "fabsf") {
651 if (I.getNumOperands() == 2 && // Basic sanity checks.
652 I.getOperand(1)->getType()->isFloatingPoint() &&
653 I.getType() == I.getOperand(1)->getType()) {
654 SDOperand Tmp = getValue(I.getOperand(1));
655 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
659 else if (F->getName() == "sin" || F->getName() == "sinf") {
660 if (I.getNumOperands() == 2 && // Basic sanity checks.
661 I.getOperand(1)->getType()->isFloatingPoint() &&
662 I.getType() == I.getOperand(1)->getType()) {
663 SDOperand Tmp = getValue(I.getOperand(1));
664 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
668 else if (F->getName() == "cos" || F->getName() == "cosf") {
669 if (I.getNumOperands() == 2 && // Basic sanity checks.
670 I.getOperand(1)->getType()->isFloatingPoint() &&
671 I.getType() == I.getOperand(1)->getType()) {
672 SDOperand Tmp = getValue(I.getOperand(1));
673 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
678 case Intrinsic::vastart: visitVAStart(I); return;
679 case Intrinsic::vaend: visitVAEnd(I); return;
680 case Intrinsic::vacopy: visitVACopy(I); return;
681 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return;
682 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return;
684 // FIXME: IMPLEMENT THESE.
685 // readport, writeport, readio, writeio
687 assert(0 && "This intrinsic is not implemented yet!");
689 case Intrinsic::setjmp: RenameFn = "setjmp"; break;
690 case Intrinsic::longjmp: RenameFn = "longjmp"; break;
691 case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return;
692 case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return;
693 case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
695 case Intrinsic::dbg_stoppoint:
696 case Intrinsic::dbg_region_start:
697 case Intrinsic::dbg_region_end:
698 case Intrinsic::dbg_func_start:
699 case Intrinsic::dbg_declare:
700 if (I.getType() != Type::VoidTy)
701 setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
704 case Intrinsic::isunordered:
705 setValue(&I, DAG.getSetCC(ISD::SETUO, MVT::i1,getValue(I.getOperand(1)),
706 getValue(I.getOperand(2))));
709 case Intrinsic::sqrt:
710 setValue(&I, DAG.getNode(ISD::FSQRT,
711 getValue(I.getOperand(1)).getValueType(),
712 getValue(I.getOperand(1))));
715 case Intrinsic::pcmarker: {
716 SDOperand Num = getValue(I.getOperand(1));
717 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Num));
720 case Intrinsic::cttz:
721 setValue(&I, DAG.getNode(ISD::CTTZ,
722 getValue(I.getOperand(1)).getValueType(),
723 getValue(I.getOperand(1))));
725 case Intrinsic::ctlz:
726 setValue(&I, DAG.getNode(ISD::CTLZ,
727 getValue(I.getOperand(1)).getValueType(),
728 getValue(I.getOperand(1))));
730 case Intrinsic::ctpop:
731 setValue(&I, DAG.getNode(ISD::CTPOP,
732 getValue(I.getOperand(1)).getValueType(),
733 getValue(I.getOperand(1))));
739 Callee = getValue(I.getOperand(0));
741 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
742 std::vector<std::pair<SDOperand, const Type*> > Args;
744 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
745 Value *Arg = I.getOperand(i);
746 SDOperand ArgNode = getValue(Arg);
747 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
750 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
751 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
753 std::pair<SDOperand,SDOperand> Result =
754 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), Callee, Args, DAG);
755 if (I.getType() != Type::VoidTy)
756 setValue(&I, Result.first);
757 DAG.setRoot(Result.second);
760 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
761 SDOperand Src = getValue(I.getOperand(0));
763 MVT::ValueType IntPtr = TLI.getPointerTy();
765 if (IntPtr < Src.getValueType())
766 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
767 else if (IntPtr > Src.getValueType())
768 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
770 // Scale the source by the type size.
771 uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType());
772 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
773 Src, getIntPtrConstant(ElementSize));
775 std::vector<std::pair<SDOperand, const Type*> > Args;
776 Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
778 std::pair<SDOperand,SDOperand> Result =
779 TLI.LowerCallTo(getRoot(), I.getType(), false,
780 DAG.getExternalSymbol("malloc", IntPtr),
782 setValue(&I, Result.first); // Pointers always fit in registers
783 DAG.setRoot(Result.second);
786 void SelectionDAGLowering::visitFree(FreeInst &I) {
787 std::vector<std::pair<SDOperand, const Type*> > Args;
788 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
789 TLI.getTargetData().getIntPtrType()));
790 MVT::ValueType IntPtr = TLI.getPointerTy();
791 std::pair<SDOperand,SDOperand> Result =
792 TLI.LowerCallTo(getRoot(), Type::VoidTy, false,
793 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
794 DAG.setRoot(Result.second);
797 std::pair<SDOperand, SDOperand>
798 TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
799 // We have no sane default behavior, just emit a useful error message and bail
801 std::cerr << "Variable arguments handling not implemented on this target!\n";
803 return std::make_pair(SDOperand(), SDOperand());
806 SDOperand TargetLowering::LowerVAEnd(SDOperand Chain, SDOperand L,
808 // Default to a noop.
812 std::pair<SDOperand,SDOperand>
813 TargetLowering::LowerVACopy(SDOperand Chain, SDOperand L, SelectionDAG &DAG) {
814 // Default to returning the input list.
815 return std::make_pair(L, Chain);
818 std::pair<SDOperand,SDOperand>
819 TargetLowering::LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
820 const Type *ArgTy, SelectionDAG &DAG) {
821 // We have no sane default behavior, just emit a useful error message and bail
823 std::cerr << "Variable arguments handling not implemented on this target!\n";
825 return std::make_pair(SDOperand(), SDOperand());
829 void SelectionDAGLowering::visitVAStart(CallInst &I) {
830 std::pair<SDOperand,SDOperand> Result = TLI.LowerVAStart(getRoot(), DAG);
831 setValue(&I, Result.first);
832 DAG.setRoot(Result.second);
835 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
836 std::pair<SDOperand,SDOperand> Result =
837 TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)),
839 setValue(&I, Result.first);
840 DAG.setRoot(Result.second);
843 void SelectionDAGLowering::visitVANext(VANextInst &I) {
844 std::pair<SDOperand,SDOperand> Result =
845 TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)),
846 I.getArgType(), DAG);
847 setValue(&I, Result.first);
848 DAG.setRoot(Result.second);
851 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
852 DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)), DAG));
855 void SelectionDAGLowering::visitVACopy(CallInst &I) {
856 std::pair<SDOperand,SDOperand> Result =
857 TLI.LowerVACopy(getRoot(), getValue(I.getOperand(1)), DAG);
858 setValue(&I, Result.first);
859 DAG.setRoot(Result.second);
863 // It is always conservatively correct for llvm.returnaddress and
864 // llvm.frameaddress to return 0.
865 std::pair<SDOperand, SDOperand>
866 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
867 unsigned Depth, SelectionDAG &DAG) {
868 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
871 SDOperand TargetLowering::LowerOperation(SDOperand Op) {
872 assert(0 && "LowerOperation not implemented for this target!");
877 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
878 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
879 std::pair<SDOperand,SDOperand> Result =
880 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
881 setValue(&I, Result.first);
882 DAG.setRoot(Result.second);
885 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
886 std::vector<SDOperand> Ops;
887 Ops.push_back(getRoot());
888 Ops.push_back(getValue(I.getOperand(1)));
889 Ops.push_back(getValue(I.getOperand(2)));
890 Ops.push_back(getValue(I.getOperand(3)));
891 Ops.push_back(getValue(I.getOperand(4)));
892 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
895 //===----------------------------------------------------------------------===//
896 // SelectionDAGISel code
897 //===----------------------------------------------------------------------===//
899 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
900 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
905 bool SelectionDAGISel::runOnFunction(Function &Fn) {
906 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
907 RegMap = MF.getSSARegMap();
908 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
910 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
912 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
913 SelectBasicBlock(I, MF, FuncInfo);
919 SDOperand SelectionDAGISel::
920 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
921 SelectionDAG &DAG = SDL.DAG;
922 SDOperand Op = SDL.getValue(V);
923 assert((Op.getOpcode() != ISD::CopyFromReg ||
924 cast<RegSDNode>(Op)->getReg() != Reg) &&
925 "Copy from a reg to the same reg!");
926 return DAG.getCopyToReg(SDL.getRoot(), Op, Reg);
929 /// IsOnlyUsedInOneBasicBlock - If the specified argument is only used in a
930 /// single basic block, return that block. Otherwise, return a null pointer.
931 static BasicBlock *IsOnlyUsedInOneBasicBlock(Argument *A) {
932 if (A->use_empty()) return 0;
933 BasicBlock *BB = cast<Instruction>(A->use_back())->getParent();
934 for (Argument::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E;
936 if (isa<PHINode>(*UI) || cast<Instruction>(*UI)->getParent() != BB)
937 return 0; // Disagreement among the users?
939 // Okay, there is a single BB user. Only permit this optimization if this is
940 // the entry block, otherwise, we might sink argument loads into loops and
941 // stuff. Later, when we have global instruction selection, this won't be an
943 if (BB == BB->getParent()->begin())
948 void SelectionDAGISel::
949 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
950 std::vector<SDOperand> &UnorderedChains) {
951 // If this is the entry block, emit arguments.
952 Function &F = *BB->getParent();
953 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
955 if (BB == &F.front()) {
956 SDOperand OldRoot = SDL.DAG.getRoot();
958 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
960 // If there were side effects accessing the argument list, do not do
962 if (OldRoot != SDL.DAG.getRoot()) {
964 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
966 if (!AI->use_empty()) {
967 SDL.setValue(AI, Args[a]);
969 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
970 UnorderedChains.push_back(Copy);
973 // Otherwise, if any argument is only accessed in a single basic block,
974 // emit that argument only to that basic block.
976 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
978 if (!AI->use_empty()) {
979 if (BasicBlock *BBU = IsOnlyUsedInOneBasicBlock(AI)) {
980 FuncInfo.BlockLocalArguments.insert(std::make_pair(BBU,
981 std::make_pair(AI, a)));
983 SDL.setValue(AI, Args[a]);
985 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
986 UnorderedChains.push_back(Copy);
992 // See if there are any block-local arguments that need to be emitted in this
995 if (!FuncInfo.BlockLocalArguments.empty()) {
996 std::multimap<BasicBlock*, std::pair<Argument*, unsigned> >::iterator BLAI =
997 FuncInfo.BlockLocalArguments.lower_bound(BB);
998 if (BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB) {
999 // Lower the arguments into this block.
1000 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
1002 // Set up the value mapping for the local arguments.
1003 for (; BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB;
1005 SDL.setValue(BLAI->second.first, Args[BLAI->second.second]);
1007 // Any dead arguments will just be ignored here.
1013 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
1014 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
1015 FunctionLoweringInfo &FuncInfo) {
1016 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
1018 std::vector<SDOperand> UnorderedChains;
1020 // Lower any arguments needed in this block.
1021 LowerArguments(LLVMBB, SDL, UnorderedChains);
1023 BB = FuncInfo.MBBMap[LLVMBB];
1024 SDL.setCurrentBasicBlock(BB);
1026 // Lower all of the non-terminator instructions.
1027 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
1031 // Ensure that all instructions which are used outside of their defining
1032 // blocks are available as virtual registers.
1033 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
1034 if (!I->use_empty() && !isa<PHINode>(I)) {
1035 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
1036 if (VMI != FuncInfo.ValueMap.end())
1037 UnorderedChains.push_back(
1038 CopyValueToVirtualRegister(SDL, I, VMI->second));
1041 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
1042 // ensure constants are generated when needed. Remember the virtual registers
1043 // that need to be added to the Machine PHI nodes as input. We cannot just
1044 // directly add them, because expansion might result in multiple MBB's for one
1045 // BB. As such, the start of the BB might correspond to a different MBB than
1049 // Emit constants only once even if used by multiple PHI nodes.
1050 std::map<Constant*, unsigned> ConstantsOut;
1052 // Check successor nodes PHI nodes that expect a constant to be available from
1054 TerminatorInst *TI = LLVMBB->getTerminator();
1055 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1056 BasicBlock *SuccBB = TI->getSuccessor(succ);
1057 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
1060 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1061 // nodes and Machine PHI nodes, but the incoming operands have not been
1063 for (BasicBlock::iterator I = SuccBB->begin();
1064 (PN = dyn_cast<PHINode>(I)); ++I)
1065 if (!PN->use_empty()) {
1067 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
1068 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
1069 unsigned &RegOut = ConstantsOut[C];
1071 RegOut = FuncInfo.CreateRegForValue(C);
1072 UnorderedChains.push_back(
1073 CopyValueToVirtualRegister(SDL, C, RegOut));
1077 Reg = FuncInfo.ValueMap[PHIOp];
1079 assert(isa<AllocaInst>(PHIOp) &&
1080 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
1081 "Didn't codegen value into a register!??");
1082 Reg = FuncInfo.CreateRegForValue(PHIOp);
1083 UnorderedChains.push_back(
1084 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
1088 // Remember that this register needs to added to the machine PHI node as
1089 // the input for this MBB.
1090 unsigned NumElements =
1091 TLI.getNumElements(TLI.getValueType(PN->getType()));
1092 for (unsigned i = 0, e = NumElements; i != e; ++i)
1093 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
1096 ConstantsOut.clear();
1098 // Turn all of the unordered chains into one factored node.
1099 if (!UnorderedChains.empty()) {
1100 UnorderedChains.push_back(SDL.getRoot());
1101 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
1104 // Lower the terminator after the copies are emitted.
1105 SDL.visit(*LLVMBB->getTerminator());
1107 // Make sure the root of the DAG is up-to-date.
1108 DAG.setRoot(SDL.getRoot());
1111 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
1112 FunctionLoweringInfo &FuncInfo) {
1113 SelectionDAG DAG(TLI, MF);
1115 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
1117 // First step, lower LLVM code to some DAG. This DAG may use operations and
1118 // types that are not supported by the target.
1119 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
1121 DEBUG(std::cerr << "Lowered selection DAG:\n");
1124 // Second step, hack on the DAG until it only uses operations and types that
1125 // the target supports.
1128 DEBUG(std::cerr << "Legalized selection DAG:\n");
1131 // Third, instruction select all of the operations to machine code, adding the
1132 // code to the MachineBasicBlock.
1133 InstructionSelectBasicBlock(DAG);
1135 if (ViewDAGs) DAG.viewGraph();
1137 DEBUG(std::cerr << "Selected machine code:\n");
1140 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1141 // PHI nodes in successors.
1142 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
1143 MachineInstr *PHI = PHINodesToUpdate[i].first;
1144 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
1145 "This is not a machine PHI node that we are updating!");
1146 PHI->addRegOperand(PHINodesToUpdate[i].second);
1147 PHI->addMachineBasicBlockOperand(BB);
1150 // Finally, add the CFG edges from the last selected MBB to the successor
1152 TerminatorInst *TI = LLVMBB->getTerminator();
1153 for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
1154 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[TI->getSuccessor(i)];
1155 BB->addSuccessor(Succ0MBB);