1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/CodeGen/DwarfWriter.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetIntrinsicInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetMachine.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/Timer.h"
58 #include "llvm/Support/raw_ostream.h"
63 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
64 cl::desc("Enable verbose messages in the \"fast\" "
65 "instruction selector"));
67 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
68 cl::desc("Enable abort calls when \"fast\" instruction fails"));
70 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
71 cl::desc("Schedule copies of livein registers"),
76 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the first "
80 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before legalize types"));
83 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize"));
86 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before the second "
90 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
91 cl::desc("Pop up a window to show dags before the post legalize types"
92 " dag combine pass"));
94 ViewISelDAGs("view-isel-dags", cl::Hidden,
95 cl::desc("Pop up a window to show isel dags as they are selected"));
97 ViewSchedDAGs("view-sched-dags", cl::Hidden,
98 cl::desc("Pop up a window to show sched dags as they are processed"));
100 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
101 cl::desc("Pop up a window to show SUnit dags after they are processed"));
103 static const bool ViewDAGCombine1 = false,
104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
105 ViewDAGCombine2 = false,
106 ViewDAGCombineLT = false,
107 ViewISelDAGs = false, ViewSchedDAGs = false,
108 ViewSUnitDAGs = false;
111 //===---------------------------------------------------------------------===//
113 /// RegisterScheduler class - Track the registration of instruction schedulers.
115 //===---------------------------------------------------------------------===//
116 MachinePassRegistry RegisterScheduler::Registry;
118 //===---------------------------------------------------------------------===//
120 /// ISHeuristic command line option for instruction schedulers.
122 //===---------------------------------------------------------------------===//
123 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
124 RegisterPassParser<RegisterScheduler> >
125 ISHeuristic("pre-RA-sched",
126 cl::init(&createDefaultScheduler),
127 cl::desc("Instruction schedulers available (before register"
130 static RegisterScheduler
131 defaultListDAGScheduler("default", "Best scheduler for the target",
132 createDefaultScheduler);
135 //===--------------------------------------------------------------------===//
136 /// createDefaultScheduler - This creates an instruction scheduler appropriate
138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
139 CodeGenOpt::Level OptLevel) {
140 const TargetLowering &TLI = IS->getTargetLowering();
142 if (OptLevel == CodeGenOpt::None)
143 return createFastDAGScheduler(IS, OptLevel);
144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
145 return createTDListDAGScheduler(IS, OptLevel);
146 assert(TLI.getSchedulingPreference() ==
147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
148 return createBURRListDAGScheduler(IS, OptLevel);
152 // EmitInstrWithCustomInserter - This method should be implemented by targets
153 // that mark instructions with the 'usesCustomInserter' flag. These
154 // instructions are special in various ways, which require special support to
155 // insert. The specified MachineInstr is created but not inserted into any
156 // basic blocks, and this method is called to expand it into a sequence of
157 // instructions, potentially also creating new basic blocks and control flow.
158 // When new basic blocks are inserted and the edges from MBB to its successors
159 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
161 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
162 MachineBasicBlock *MBB,
163 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
165 dbgs() << "If a target marks an instruction with "
166 "'usesCustomInserter', it must implement "
167 "TargetLowering::EmitInstrWithCustomInserter!";
173 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
174 /// physical register has only a single copy use, then coalesced the copy
176 static void EmitLiveInCopy(MachineBasicBlock *MBB,
177 MachineBasicBlock::iterator &InsertPos,
178 unsigned VirtReg, unsigned PhysReg,
179 const TargetRegisterClass *RC,
180 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
181 const MachineRegisterInfo &MRI,
182 const TargetRegisterInfo &TRI,
183 const TargetInstrInfo &TII) {
184 unsigned NumUses = 0;
185 MachineInstr *UseMI = NULL;
186 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
187 UE = MRI.use_end(); UI != UE; ++UI) {
193 // If the number of uses is not one, or the use is not a move instruction,
194 // don't coalesce. Also, only coalesce away a virtual register to virtual
196 bool Coalesced = false;
197 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
199 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
200 TargetRegisterInfo::isVirtualRegister(DstReg)) {
205 // Now find an ideal location to insert the copy.
206 MachineBasicBlock::iterator Pos = InsertPos;
207 while (Pos != MBB->begin()) {
208 MachineInstr *PrevMI = prior(Pos);
209 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
210 // copyRegToReg might emit multiple instructions to do a copy.
211 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
212 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
213 // This is what the BB looks like right now:
218 // We want to insert "r1025 = mov r1". Inserting this copy below the
219 // move to r1024 makes it impossible for that move to be coalesced.
226 break; // Woot! Found a good location.
230 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
231 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
234 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
236 if (&*InsertPos == UseMI) ++InsertPos;
241 /// EmitLiveInCopies - If this is the first basic block in the function,
242 /// and if it has live ins that need to be copied into vregs, emit the
243 /// copies into the block.
244 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
245 const MachineRegisterInfo &MRI,
246 const TargetRegisterInfo &TRI,
247 const TargetInstrInfo &TII) {
248 if (SchedLiveInCopies) {
249 // Emit the copies at a heuristically-determined location in the block.
250 DenseMap<MachineInstr*, unsigned> CopyRegMap;
251 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
252 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
253 E = MRI.livein_end(); LI != E; ++LI)
255 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
256 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
257 RC, CopyRegMap, MRI, TRI, TII);
260 // Emit the copies into the top of the block.
261 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
262 E = MRI.livein_end(); LI != E; ++LI)
264 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
265 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
266 LI->second, LI->first, RC, RC);
267 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
273 //===----------------------------------------------------------------------===//
274 // SelectionDAGISel code
275 //===----------------------------------------------------------------------===//
277 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
278 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
279 FuncInfo(new FunctionLoweringInfo(TLI)),
280 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
281 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
287 SelectionDAGISel::~SelectionDAGISel() {
293 unsigned SelectionDAGISel::MakeReg(EVT VT) {
294 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
297 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
298 AU.addRequired<AliasAnalysis>();
299 AU.addPreserved<AliasAnalysis>();
300 AU.addRequired<GCModuleInfo>();
301 AU.addPreserved<GCModuleInfo>();
302 AU.addRequired<DwarfWriter>();
303 AU.addPreserved<DwarfWriter>();
304 MachineFunctionPass::getAnalysisUsage(AU);
307 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
308 Function &Fn = *mf.getFunction();
310 // Do some sanity-checking on the command-line options.
311 assert((!EnableFastISelVerbose || EnableFastISel) &&
312 "-fast-isel-verbose requires -fast-isel");
313 assert((!EnableFastISelAbort || EnableFastISel) &&
314 "-fast-isel-abort requires -fast-isel");
316 // Get alias analysis for load/store combining.
317 AA = &getAnalysis<AliasAnalysis>();
320 const TargetInstrInfo &TII = *TM.getInstrInfo();
321 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
324 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
327 RegInfo = &MF->getRegInfo();
328 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
330 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
331 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
332 CurDAG->init(*MF, MMI, DW);
333 FuncInfo->set(Fn, *MF, EnableFastISel);
336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
339 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
341 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
343 // If the first basic block in the function has live ins that need to be
344 // copied into vregs, emit the copies into the top of the block before
345 // emitting the code for the block.
346 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
348 // Add function live-ins to entry block live-in set.
349 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
350 E = RegInfo->livein_end(); I != E; ++I)
351 MF->begin()->addLiveIn(I->first);
354 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
355 "Not all catch info was assigned to a landing pad!");
363 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
364 /// attached with this instruction.
365 static void SetDebugLoc(unsigned MDDbgKind, Instruction *I,
366 SelectionDAGBuilder *SDB,
367 FastISel *FastIS, MachineFunction *MF) {
368 if (isa<DbgInfoIntrinsic>(I)) return;
370 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) {
371 DILocation DILoc(Dbg);
372 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
374 SDB->setCurDebugLoc(Loc);
377 FastIS->setCurDebugLoc(Loc);
379 // If the function doesn't have a default debug location yet, set
380 // it. This is kind of a hack.
381 if (MF->getDefaultDebugLoc().isUnknown())
382 MF->setDefaultDebugLoc(Loc);
386 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
387 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
388 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc());
390 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc());
393 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
394 BasicBlock::iterator Begin,
395 BasicBlock::iterator End,
397 SDB->setCurrentBasicBlock(BB);
398 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg");
400 // Lower all of the non-terminator instructions. If a call is emitted
401 // as a tail call, cease emitting nodes for this block.
402 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
403 SetDebugLoc(MDDbgKind, I, SDB, 0, MF);
405 if (!isa<TerminatorInst>(I)) {
408 // Set the current debug location back to "unknown" so that it doesn't
409 // spuriously apply to subsequent instructions.
410 ResetDebugLoc(SDB, 0);
414 if (!SDB->HasTailCall) {
415 // Ensure that all instructions which are used outside of their defining
416 // blocks are available as virtual registers. Invoke is handled elsewhere.
417 for (BasicBlock::iterator I = Begin; I != End; ++I)
418 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
419 SDB->CopyToExportRegsIfNeeded(I);
421 // Handle PHI nodes in successor blocks.
422 if (End == LLVMBB->end()) {
423 HandlePHINodesInSuccessorBlocks(LLVMBB);
425 // Lower the terminator after the copies are emitted.
426 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF);
427 SDB->visit(*LLVMBB->getTerminator());
428 ResetDebugLoc(SDB, 0);
432 // Make sure the root of the DAG is up-to-date.
433 CurDAG->setRoot(SDB->getControlRoot());
435 // Final step, emit the lowered DAG as machine code.
437 HadTailCall = SDB->HasTailCall;
442 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
443 /// nodes from the worklist.
444 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
445 SmallVector<SDNode*, 128> &Worklist;
447 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl) : Worklist(wl) {}
449 virtual void NodeDeleted(SDNode *N, SDNode *E) {
450 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N),
454 virtual void NodeUpdated(SDNode *N) {
460 /// TrivialTruncElim - Eliminate some trivial nops that can result from
461 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
462 static bool TrivialTruncElim(SDValue Op,
463 TargetLowering::TargetLoweringOpt &TLO) {
464 SDValue N0 = Op.getOperand(0);
465 EVT VT = Op.getValueType();
466 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
467 N0.getOpcode() == ISD::SIGN_EXTEND ||
468 N0.getOpcode() == ISD::ANY_EXTEND) &&
469 N0.getOperand(0).getValueType() == VT) {
470 return TLO.CombineTo(Op, N0.getOperand(0));
475 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
476 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
477 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
478 void SelectionDAGISel::ShrinkDemandedOps() {
479 SmallVector<SDNode*, 128> Worklist;
481 // Add all the dag nodes to the worklist.
482 Worklist.reserve(CurDAG->allnodes_size());
483 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
484 E = CurDAG->allnodes_end(); I != E; ++I)
485 Worklist.push_back(I);
491 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
492 while (!Worklist.empty()) {
493 SDNode *N = Worklist.pop_back_val();
495 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
496 CurDAG->DeleteNode(N);
500 // Run ShrinkDemandedOp on scalar binary operations.
501 if (N->getNumValues() == 1 &&
502 N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) {
503 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
504 APInt Demanded = APInt::getAllOnesValue(BitWidth);
505 APInt KnownZero, KnownOne;
506 if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
507 KnownZero, KnownOne, TLO) ||
508 (N->getOpcode() == ISD::TRUNCATE &&
509 TrivialTruncElim(SDValue(N, 0), TLO))) {
511 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N),
513 Worklist.push_back(N);
515 // Replace the old value with the new one.
516 DEBUG(errs() << "\nReplacing ";
517 TLO.Old.getNode()->dump(CurDAG);
518 errs() << "\nWith: ";
519 TLO.New.getNode()->dump(CurDAG);
522 Worklist.push_back(TLO.New.getNode());
524 SDOPsWorkListRemover DeadNodes(Worklist);
525 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
527 if (TLO.Old.getNode()->use_empty()) {
528 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
530 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
531 if (OpNode->hasOneUse()) {
532 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(),
533 OpNode), Worklist.end());
534 Worklist.push_back(OpNode);
538 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(),
539 TLO.Old.getNode()), Worklist.end());
540 CurDAG->DeleteNode(TLO.Old.getNode());
547 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
548 SmallPtrSet<SDNode*, 128> VisitedNodes;
549 SmallVector<SDNode*, 128> Worklist;
551 Worklist.push_back(CurDAG->getRoot().getNode());
558 SDNode *N = Worklist.pop_back_val();
560 // If we've already seen this node, ignore it.
561 if (!VisitedNodes.insert(N))
564 // Otherwise, add all chain operands to the worklist.
565 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
566 if (N->getOperand(i).getValueType() == MVT::Other)
567 Worklist.push_back(N->getOperand(i).getNode());
569 // If this is a CopyToReg with a vreg dest, process it.
570 if (N->getOpcode() != ISD::CopyToReg)
573 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
574 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
577 // Ignore non-scalar or non-integer values.
578 SDValue Src = N->getOperand(2);
579 EVT SrcVT = Src.getValueType();
580 if (!SrcVT.isInteger() || SrcVT.isVector())
583 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
584 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
585 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
587 // Only install this information if it tells us something.
588 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
589 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
590 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
591 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
592 FunctionLoweringInfo::LiveOutInfo &LOI =
593 FuncInfo->LiveOutRegInfo[DestReg];
594 LOI.NumSignBits = NumSignBits;
595 LOI.KnownOne = KnownOne;
596 LOI.KnownZero = KnownZero;
598 } while (!Worklist.empty());
601 void SelectionDAGISel::CodeGenAndEmitDAG() {
602 std::string GroupName;
603 if (TimePassesIsEnabled)
604 GroupName = "Instruction Selection and Scheduling";
605 std::string BlockName;
606 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
607 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
609 BlockName = MF->getFunction()->getNameStr() + ":" +
610 BB->getBasicBlock()->getNameStr();
612 DEBUG(dbgs() << "Initial selection DAG:\n");
613 DEBUG(CurDAG->dump());
615 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
617 // Run the DAG combiner in pre-legalize mode.
618 if (TimePassesIsEnabled) {
619 NamedRegionTimer T("DAG Combining 1", GroupName);
620 CurDAG->Combine(Unrestricted, *AA, OptLevel);
622 CurDAG->Combine(Unrestricted, *AA, OptLevel);
625 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
626 DEBUG(CurDAG->dump());
628 // Second step, hack on the DAG until it only uses operations and types that
629 // the target supports.
630 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
634 if (TimePassesIsEnabled) {
635 NamedRegionTimer T("Type Legalization", GroupName);
636 Changed = CurDAG->LegalizeTypes();
638 Changed = CurDAG->LegalizeTypes();
641 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
642 DEBUG(CurDAG->dump());
645 if (ViewDAGCombineLT)
646 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
648 // Run the DAG combiner in post-type-legalize mode.
649 if (TimePassesIsEnabled) {
650 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
651 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
653 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
656 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
657 DEBUG(CurDAG->dump());
660 if (TimePassesIsEnabled) {
661 NamedRegionTimer T("Vector Legalization", GroupName);
662 Changed = CurDAG->LegalizeVectors();
664 Changed = CurDAG->LegalizeVectors();
668 if (TimePassesIsEnabled) {
669 NamedRegionTimer T("Type Legalization 2", GroupName);
670 CurDAG->LegalizeTypes();
672 CurDAG->LegalizeTypes();
675 if (ViewDAGCombineLT)
676 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
678 // Run the DAG combiner in post-type-legalize mode.
679 if (TimePassesIsEnabled) {
680 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
681 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
683 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
686 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
687 DEBUG(CurDAG->dump());
690 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
692 if (TimePassesIsEnabled) {
693 NamedRegionTimer T("DAG Legalization", GroupName);
694 CurDAG->Legalize(OptLevel);
696 CurDAG->Legalize(OptLevel);
699 DEBUG(dbgs() << "Legalized selection DAG:\n");
700 DEBUG(CurDAG->dump());
702 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
704 // Run the DAG combiner in post-legalize mode.
705 if (TimePassesIsEnabled) {
706 NamedRegionTimer T("DAG Combining 2", GroupName);
707 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
709 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
712 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
713 DEBUG(CurDAG->dump());
715 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
717 if (OptLevel != CodeGenOpt::None) {
719 ComputeLiveOutVRegInfo();
722 // Third, instruction select all of the operations to machine code, adding the
723 // code to the MachineBasicBlock.
724 if (TimePassesIsEnabled) {
725 NamedRegionTimer T("Instruction Selection", GroupName);
731 DEBUG(dbgs() << "Selected selection DAG:\n");
732 DEBUG(CurDAG->dump());
734 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
736 // Schedule machine code.
737 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
738 if (TimePassesIsEnabled) {
739 NamedRegionTimer T("Instruction Scheduling", GroupName);
740 Scheduler->Run(CurDAG, BB, BB->end());
742 Scheduler->Run(CurDAG, BB, BB->end());
745 if (ViewSUnitDAGs) Scheduler->viewGraph();
747 // Emit machine code to BB. This can change 'BB' to the last block being
749 if (TimePassesIsEnabled) {
750 NamedRegionTimer T("Instruction Creation", GroupName);
751 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
753 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
756 // Free the scheduler state.
757 if (TimePassesIsEnabled) {
758 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
764 DEBUG(dbgs() << "Selected machine code:\n");
768 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
770 MachineModuleInfo *MMI,
772 const TargetInstrInfo &TII) {
773 // Initialize the Fast-ISel state, if needed.
774 FastISel *FastIS = 0;
776 FastIS = TLI.createFastISel(MF, MMI, DW,
779 FuncInfo->StaticAllocaMap
781 , FuncInfo->CatchInfoLost
785 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg");
787 // Iterate over all basic blocks in the function.
788 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
789 BasicBlock *LLVMBB = &*I;
790 BB = FuncInfo->MBBMap[LLVMBB];
792 BasicBlock::iterator const Begin = LLVMBB->begin();
793 BasicBlock::iterator const End = LLVMBB->end();
794 BasicBlock::iterator BI = Begin;
796 // Lower any arguments needed in this block if this is the entry block.
797 bool SuppressFastISel = false;
798 if (LLVMBB == &Fn.getEntryBlock()) {
799 LowerArguments(LLVMBB);
801 // If any of the arguments has the byval attribute, forgo
802 // fast-isel in the entry block.
805 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
807 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
808 if (EnableFastISelVerbose || EnableFastISelAbort)
809 dbgs() << "FastISel skips entry block due to byval argument\n";
810 SuppressFastISel = true;
816 if (MMI && BB->isLandingPad()) {
817 // Add a label to mark the beginning of the landing pad. Deletion of the
818 // landing pad can thus be detected via the MachineModuleInfo.
819 unsigned LabelID = MMI->addLandingPad(BB);
821 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
822 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID);
824 // Mark exception register as live in.
825 unsigned Reg = TLI.getExceptionAddressRegister();
826 if (Reg) BB->addLiveIn(Reg);
828 // Mark exception selector register as live in.
829 Reg = TLI.getExceptionSelectorRegister();
830 if (Reg) BB->addLiveIn(Reg);
832 // FIXME: Hack around an exception handling flaw (PR1508): the personality
833 // function and list of typeids logically belong to the invoke (or, if you
834 // like, the basic block containing the invoke), and need to be associated
835 // with it in the dwarf exception handling tables. Currently however the
836 // information is provided by an intrinsic (eh.selector) that can be moved
837 // to unexpected places by the optimizers: if the unwind edge is critical,
838 // then breaking it can result in the intrinsics being in the successor of
839 // the landing pad, not the landing pad itself. This results
840 // in exceptions not being caught because no typeids are associated with
841 // the invoke. This may not be the only way things can go wrong, but it
842 // is the only way we try to work around for the moment.
843 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
845 if (Br && Br->isUnconditional()) { // Critical edge?
846 BasicBlock::iterator I, E;
847 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
848 if (isa<EHSelectorInst>(I))
852 // No catch info found - try to extract some from the successor.
853 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
857 // Before doing SelectionDAG ISel, see if FastISel has been requested.
858 if (FastIS && !SuppressFastISel) {
859 // Emit code for any incoming arguments. This must happen before
860 // beginning FastISel on the entry block.
861 if (LLVMBB == &Fn.getEntryBlock()) {
862 CurDAG->setRoot(SDB->getControlRoot());
866 FastIS->startNewBlock(BB);
867 // Do FastISel on as many instructions as possible.
868 for (; BI != End; ++BI) {
869 // Just before the terminator instruction, insert instructions to
870 // feed PHI nodes in successor blocks.
871 if (isa<TerminatorInst>(BI))
872 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
873 ResetDebugLoc(SDB, FastIS);
874 if (EnableFastISelVerbose || EnableFastISelAbort) {
875 dbgs() << "FastISel miss: ";
878 assert(!EnableFastISelAbort &&
879 "FastISel didn't handle a PHI in a successor");
883 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF);
885 // Try to select the instruction with FastISel.
886 if (FastIS->SelectInstruction(BI)) {
887 ResetDebugLoc(SDB, FastIS);
891 // Clear out the debug location so that it doesn't carry over to
892 // unrelated instructions.
893 ResetDebugLoc(SDB, FastIS);
895 // Then handle certain instructions as single-LLVM-Instruction blocks.
896 if (isa<CallInst>(BI)) {
897 if (EnableFastISelVerbose || EnableFastISelAbort) {
898 dbgs() << "FastISel missed call: ";
902 if (!BI->getType()->isVoidTy()) {
903 unsigned &R = FuncInfo->ValueMap[BI];
905 R = FuncInfo->CreateRegForValue(BI);
908 bool HadTailCall = false;
909 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
911 // If the call was emitted as a tail call, we're done with the block.
917 // If the instruction was codegen'd with multiple blocks,
918 // inform the FastISel object where to resume inserting.
919 FastIS->setCurrentBlock(BB);
923 // Otherwise, give up on FastISel for the rest of the block.
924 // For now, be a little lenient about non-branch terminators.
925 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
926 if (EnableFastISelVerbose || EnableFastISelAbort) {
927 dbgs() << "FastISel miss: ";
930 if (EnableFastISelAbort)
931 // The "fast" selector couldn't handle something and bailed.
932 // For the purpose of debugging, just abort.
933 llvm_unreachable("FastISel didn't select the entire block");
939 // Run SelectionDAG instruction selection on the remainder of the block
940 // not handled by FastISel. If FastISel is not run, this is the entire
944 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
954 SelectionDAGISel::FinishBasicBlock() {
956 DEBUG(dbgs() << "Target-post-processed machine code:\n");
959 DEBUG(dbgs() << "Total amount of phi nodes to update: "
960 << SDB->PHINodesToUpdate.size() << "\n");
961 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
962 dbgs() << "Node " << i << " : ("
963 << SDB->PHINodesToUpdate[i].first
964 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
966 // Next, now that we know what the last MBB the LLVM BB expanded is, update
967 // PHI nodes in successors.
968 if (SDB->SwitchCases.empty() &&
969 SDB->JTCases.empty() &&
970 SDB->BitTestCases.empty()) {
971 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
972 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
973 assert(PHI->isPHI() &&
974 "This is not a machine PHI node that we are updating!");
975 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
977 PHI->addOperand(MachineOperand::CreateMBB(BB));
979 SDB->PHINodesToUpdate.clear();
983 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
984 // Lower header first, if it wasn't already lowered
985 if (!SDB->BitTestCases[i].Emitted) {
986 // Set the current basic block to the mbb we wish to insert the code into
987 BB = SDB->BitTestCases[i].Parent;
988 SDB->setCurrentBasicBlock(BB);
990 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
991 CurDAG->setRoot(SDB->getRoot());
996 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
997 // Set the current basic block to the mbb we wish to insert the code into
998 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
999 SDB->setCurrentBasicBlock(BB);
1002 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1003 SDB->BitTestCases[i].Reg,
1004 SDB->BitTestCases[i].Cases[j]);
1006 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1007 SDB->BitTestCases[i].Reg,
1008 SDB->BitTestCases[i].Cases[j]);
1011 CurDAG->setRoot(SDB->getRoot());
1012 CodeGenAndEmitDAG();
1017 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1018 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1019 MachineBasicBlock *PHIBB = PHI->getParent();
1020 assert(PHI->isPHI() &&
1021 "This is not a machine PHI node that we are updating!");
1022 // This is "default" BB. We have two jumps to it. From "header" BB and
1023 // from last "case" BB.
1024 if (PHIBB == SDB->BitTestCases[i].Default) {
1025 PHI->addOperand(MachineOperand::
1026 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1027 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1028 PHI->addOperand(MachineOperand::
1029 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1030 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1033 // One of "cases" BB.
1034 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1036 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1037 if (cBB->isSuccessor(PHIBB)) {
1038 PHI->addOperand(MachineOperand::
1039 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1040 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1045 SDB->BitTestCases.clear();
1047 // If the JumpTable record is filled in, then we need to emit a jump table.
1048 // Updating the PHI nodes is tricky in this case, since we need to determine
1049 // whether the PHI is a successor of the range check MBB or the jump table MBB
1050 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1051 // Lower header first, if it wasn't already lowered
1052 if (!SDB->JTCases[i].first.Emitted) {
1053 // Set the current basic block to the mbb we wish to insert the code into
1054 BB = SDB->JTCases[i].first.HeaderBB;
1055 SDB->setCurrentBasicBlock(BB);
1057 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1058 CurDAG->setRoot(SDB->getRoot());
1059 CodeGenAndEmitDAG();
1063 // Set the current basic block to the mbb we wish to insert the code into
1064 BB = SDB->JTCases[i].second.MBB;
1065 SDB->setCurrentBasicBlock(BB);
1067 SDB->visitJumpTable(SDB->JTCases[i].second);
1068 CurDAG->setRoot(SDB->getRoot());
1069 CodeGenAndEmitDAG();
1073 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1074 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1075 MachineBasicBlock *PHIBB = PHI->getParent();
1076 assert(PHI->isPHI() &&
1077 "This is not a machine PHI node that we are updating!");
1078 // "default" BB. We can go there only from header BB.
1079 if (PHIBB == SDB->JTCases[i].second.Default) {
1081 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1083 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1085 // JT BB. Just iterate over successors here
1086 if (BB->isSuccessor(PHIBB)) {
1088 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1089 PHI->addOperand(MachineOperand::CreateMBB(BB));
1093 SDB->JTCases.clear();
1095 // If the switch block involved a branch to one of the actual successors, we
1096 // need to update PHI nodes in that block.
1097 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1098 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1099 assert(PHI->isPHI() &&
1100 "This is not a machine PHI node that we are updating!");
1101 if (BB->isSuccessor(PHI->getParent())) {
1102 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1104 PHI->addOperand(MachineOperand::CreateMBB(BB));
1108 // If we generated any switch lowering information, build and codegen any
1109 // additional DAGs necessary.
1110 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1111 // Set the current basic block to the mbb we wish to insert the code into
1112 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1113 SDB->setCurrentBasicBlock(BB);
1116 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1117 CurDAG->setRoot(SDB->getRoot());
1118 CodeGenAndEmitDAG();
1120 // Handle any PHI nodes in successors of this chunk, as if we were coming
1121 // from the original BB before switch expansion. Note that PHI nodes can
1122 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1123 // handle them the right number of times.
1124 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1125 // If new BB's are created during scheduling, the edges may have been
1126 // updated. That is, the edge from ThisBB to BB may have been split and
1127 // BB's predecessor is now another block.
1128 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1129 SDB->EdgeMapping.find(BB);
1130 if (EI != SDB->EdgeMapping.end())
1131 ThisBB = EI->second;
1133 // BB may have been removed from the CFG if a branch was constant folded.
1134 if (ThisBB->isSuccessor(BB)) {
1135 for (MachineBasicBlock::iterator Phi = BB->begin();
1136 Phi != BB->end() && Phi->isPHI();
1138 // This value for this PHI node is recorded in PHINodesToUpdate.
1139 for (unsigned pn = 0; ; ++pn) {
1140 assert(pn != SDB->PHINodesToUpdate.size() &&
1141 "Didn't find PHI entry!");
1142 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1143 Phi->addOperand(MachineOperand::
1144 CreateReg(SDB->PHINodesToUpdate[pn].second,
1146 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1153 // Don't process RHS if same block as LHS.
1154 if (BB == SDB->SwitchCases[i].FalseBB)
1155 SDB->SwitchCases[i].FalseBB = 0;
1157 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1158 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1159 SDB->SwitchCases[i].FalseBB = 0;
1161 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1164 SDB->SwitchCases.clear();
1166 SDB->PHINodesToUpdate.clear();
1170 /// Create the scheduler. If a specific scheduler was specified
1171 /// via the SchedulerRegistry, use it, otherwise select the
1172 /// one preferred by the target.
1174 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1175 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1179 RegisterScheduler::setDefault(Ctor);
1182 return Ctor(this, OptLevel);
1185 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1186 return new ScheduleHazardRecognizer();
1189 //===----------------------------------------------------------------------===//
1190 // Helper functions used by the generated instruction selector.
1191 //===----------------------------------------------------------------------===//
1192 // Calls to these methods are generated by tblgen.
1194 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1195 /// the dag combiner simplified the 255, we still want to match. RHS is the
1196 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1197 /// specified in the .td file (e.g. 255).
1198 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1199 int64_t DesiredMaskS) const {
1200 const APInt &ActualMask = RHS->getAPIntValue();
1201 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1203 // If the actual mask exactly matches, success!
1204 if (ActualMask == DesiredMask)
1207 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1208 if (ActualMask.intersects(~DesiredMask))
1211 // Otherwise, the DAG Combiner may have proven that the value coming in is
1212 // either already zero or is not demanded. Check for known zero input bits.
1213 APInt NeededMask = DesiredMask & ~ActualMask;
1214 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1217 // TODO: check to see if missing bits are just not demanded.
1219 // Otherwise, this pattern doesn't match.
1223 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1224 /// the dag combiner simplified the 255, we still want to match. RHS is the
1225 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1226 /// specified in the .td file (e.g. 255).
1227 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1228 int64_t DesiredMaskS) const {
1229 const APInt &ActualMask = RHS->getAPIntValue();
1230 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1232 // If the actual mask exactly matches, success!
1233 if (ActualMask == DesiredMask)
1236 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1237 if (ActualMask.intersects(~DesiredMask))
1240 // Otherwise, the DAG Combiner may have proven that the value coming in is
1241 // either already zero or is not demanded. Check for known zero input bits.
1242 APInt NeededMask = DesiredMask & ~ActualMask;
1244 APInt KnownZero, KnownOne;
1245 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1247 // If all the missing bits in the or are already known to be set, match!
1248 if ((NeededMask & KnownOne) == NeededMask)
1251 // TODO: check to see if missing bits are just not demanded.
1253 // Otherwise, this pattern doesn't match.
1258 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1259 /// by tblgen. Others should not call it.
1260 void SelectionDAGISel::
1261 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1262 std::vector<SDValue> InOps;
1263 std::swap(InOps, Ops);
1265 Ops.push_back(InOps[0]); // input chain.
1266 Ops.push_back(InOps[1]); // input asm string.
1268 unsigned i = 2, e = InOps.size();
1269 if (InOps[e-1].getValueType() == MVT::Flag)
1270 --e; // Don't process a flag operand if it is here.
1273 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1274 if ((Flags & 7) != 4 /*MEM*/) {
1275 // Just skip over this operand, copying the operands verbatim.
1276 Ops.insert(Ops.end(), InOps.begin()+i,
1277 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1278 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1280 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1281 "Memory operand with multiple values?");
1282 // Otherwise, this is a memory operand. Ask the target to select it.
1283 std::vector<SDValue> SelOps;
1284 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1285 llvm_report_error("Could not match memory address. Inline asm"
1289 // Add this to the output node.
1290 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1292 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1297 // Add the flag input back if present.
1298 if (e != InOps.size())
1299 Ops.push_back(InOps.back());
1302 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1305 static SDNode *findFlagUse(SDNode *N) {
1306 unsigned FlagResNo = N->getNumValues()-1;
1307 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1308 SDUse &Use = I.getUse();
1309 if (Use.getResNo() == FlagResNo)
1310 return Use.getUser();
1315 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1316 /// This function recursively traverses up the operand chain, ignoring
1318 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1320 SmallPtrSet<SDNode*, 16> &Visited) {
1321 if (Use->getNodeId() < Def->getNodeId() ||
1322 !Visited.insert(Use))
1325 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1326 SDNode *N = Use->getOperand(i).getNode();
1328 if (Use == ImmedUse || Use == Root)
1329 continue; // We are not looking for immediate use.
1334 // Traverse up the operand chain.
1335 if (findNonImmUse(N, Def, ImmedUse, Root, Visited))
1341 /// isNonImmUse - Start searching from Root up the DAG to check is Def can
1342 /// be reached. Return true if that's the case. However, ignore direct uses
1343 /// by ImmedUse (which would be U in the example illustrated in
1344 /// IsLegalAndProfitableToFold) and by Root (which can happen in the store
1346 /// FIXME: to be really generic, we should allow direct use by any node
1347 /// that is being folded. But realisticly since we only fold loads which
1348 /// have one non-chain use, we only need to watch out for load/op/store
1349 /// and load/op/cmp case where the root (store / cmp) may reach the load via
1350 /// its chain operand.
1351 static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
1352 SmallPtrSet<SDNode*, 16> Visited;
1353 return findNonImmUse(Root, Def, ImmedUse, Root, Visited);
1356 /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
1357 /// U can be folded during instruction selection that starts at Root and
1358 /// folding N is profitable.
1359 bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
1360 SDNode *Root) const {
1361 if (OptLevel == CodeGenOpt::None) return false;
1363 // If Root use can somehow reach N through a path that that doesn't contain
1364 // U then folding N would create a cycle. e.g. In the following
1365 // diagram, Root can reach N through X. If N is folded into into Root, then
1366 // X is both a predecessor and a successor of U.
1377 // * indicates nodes to be folded together.
1379 // If Root produces a flag, then it gets (even more) interesting. Since it
1380 // will be "glued" together with its flag use in the scheduler, we need to
1381 // check if it might reach N.
1400 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1401 // (call it Fold), then X is a predecessor of FU and a successor of
1402 // Fold. But since Fold and FU are flagged together, this will create
1403 // a cycle in the scheduling graph.
1405 EVT VT = Root->getValueType(Root->getNumValues()-1);
1406 while (VT == MVT::Flag) {
1407 SDNode *FU = findFlagUse(Root);
1411 VT = Root->getValueType(Root->getNumValues()-1);
1414 return !isNonImmUse(Root, N, U);
1417 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1418 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1419 SelectInlineAsmMemoryOperands(Ops);
1421 std::vector<EVT> VTs;
1422 VTs.push_back(MVT::Other);
1423 VTs.push_back(MVT::Flag);
1424 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1425 VTs, &Ops[0], Ops.size());
1426 return New.getNode();
1429 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1430 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1433 SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) {
1434 SDValue Chain = N->getOperand(0);
1435 unsigned C = cast<LabelSDNode>(N)->getLabelID();
1436 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);
1437 return CurDAG->SelectNodeTo(N, TargetOpcode::EH_LABEL,
1438 MVT::Other, Tmp, Chain);
1441 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
1443 raw_string_ostream Msg(msg);
1444 Msg << "Cannot yet select: ";
1445 N->printrFull(Msg, CurDAG);
1446 llvm_report_error(Msg.str());
1449 void SelectionDAGISel::CannotYetSelectIntrinsic(SDNode *N) {
1450 dbgs() << "Cannot yet select: ";
1452 cast<ConstantSDNode>(N->getOperand(N->getOperand(0).getValueType() ==
1453 MVT::Other))->getZExtValue();
1454 if (iid < Intrinsic::num_intrinsics)
1455 llvm_report_error("Cannot yet select: intrinsic %" +
1456 Intrinsic::getName((Intrinsic::ID)iid));
1457 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo())
1458 llvm_report_error(Twine("Cannot yet select: target intrinsic %") +
1462 char SelectionDAGISel::ID = 0;