1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/MRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register allocation):"));
84 static RegisterScheduler
85 defaultListDAGScheduler("default", " Best scheduler for the target",
86 createDefaultScheduler);
89 namespace { struct AsmOperandInfo; }
92 /// RegsForValue - This struct represents the physical registers that a
93 /// particular value is assigned and the type information about the value.
94 /// This is needed because values can be promoted into larger registers and
95 /// expanded into multiple smaller registers than the value.
96 struct VISIBILITY_HIDDEN RegsForValue {
97 /// Regs - This list holds the register (for legal and promoted values)
98 /// or register set (for expanded values) that the value should be assigned
100 std::vector<unsigned> Regs;
102 /// RegVT - The value type of each register.
104 MVT::ValueType RegVT;
106 /// ValueVT - The value type of the LLVM value, which may be promoted from
107 /// RegVT or made from merging the two expanded parts.
108 MVT::ValueType ValueVT;
110 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
112 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
113 : RegVT(regvt), ValueVT(valuevt) {
116 RegsForValue(const std::vector<unsigned> ®s,
117 MVT::ValueType regvt, MVT::ValueType valuevt)
118 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
121 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
122 /// this value and returns the result as a ValueVT value. This uses
123 /// Chain/Flag as the input and updates them for the output Chain/Flag.
124 /// If the Flag pointer is NULL, no flag is used.
125 SDOperand getCopyFromRegs(SelectionDAG &DAG,
126 SDOperand &Chain, SDOperand *Flag) const;
128 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
129 /// specified value into the registers specified by this object. This uses
130 /// Chain/Flag as the input and updates them for the output Chain/Flag.
131 /// If the Flag pointer is NULL, no flag is used.
132 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
133 SDOperand &Chain, SDOperand *Flag) const;
135 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
136 /// operand list. This adds the code marker and includes the number of
137 /// values added into it.
138 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
139 std::vector<SDOperand> &Ops) const;
144 //===--------------------------------------------------------------------===//
145 /// createDefaultScheduler - This creates an instruction scheduler appropriate
147 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
149 MachineBasicBlock *BB) {
150 TargetLowering &TLI = IS->getTargetLowering();
152 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
153 return createTDListDAGScheduler(IS, DAG, BB);
155 assert(TLI.getSchedulingPreference() ==
156 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
157 return createBURRListDAGScheduler(IS, DAG, BB);
162 //===--------------------------------------------------------------------===//
163 /// FunctionLoweringInfo - This contains information that is global to a
164 /// function that is used when lowering a region of the function.
165 class FunctionLoweringInfo {
170 MachineRegisterInfo &RegInfo;
172 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
174 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
175 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
177 /// ValueMap - Since we emit code for the function a basic block at a time,
178 /// we must remember which virtual registers hold the values for
179 /// cross-basic-block values.
180 DenseMap<const Value*, unsigned> ValueMap;
182 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
183 /// the entry block. This allows the allocas to be efficiently referenced
184 /// anywhere in the function.
185 std::map<const AllocaInst*, int> StaticAllocaMap;
188 SmallSet<Instruction*, 8> CatchInfoLost;
189 SmallSet<Instruction*, 8> CatchInfoFound;
192 unsigned MakeReg(MVT::ValueType VT) {
193 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
196 /// isExportedInst - Return true if the specified value is an instruction
197 /// exported from its block.
198 bool isExportedInst(const Value *V) {
199 return ValueMap.count(V);
202 unsigned CreateRegForValue(const Value *V);
204 unsigned InitializeRegForValue(const Value *V) {
205 unsigned &R = ValueMap[V];
206 assert(R == 0 && "Already initialized this value register!");
207 return R = CreateRegForValue(V);
212 /// isSelector - Return true if this instruction is a call to the
213 /// eh.selector intrinsic.
214 static bool isSelector(Instruction *I) {
215 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
216 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
217 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
221 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
222 /// PHI nodes or outside of the basic block that defines it, or used by a
223 /// switch instruction, which may expand to multiple basic blocks.
224 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
225 if (isa<PHINode>(I)) return true;
226 BasicBlock *BB = I->getParent();
227 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
228 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
229 // FIXME: Remove switchinst special case.
230 isa<SwitchInst>(*UI))
235 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
236 /// entry block, return true. This includes arguments used by switches, since
237 /// the switch may expand into multiple basic blocks.
238 static bool isOnlyUsedInEntryBlock(Argument *A) {
239 BasicBlock *Entry = A->getParent()->begin();
240 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
241 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
242 return false; // Use not in entry block.
246 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
247 Function &fn, MachineFunction &mf)
248 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
250 // Create a vreg for each argument register that is not dead and is used
251 // outside of the entry block for the function.
252 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
254 if (!isOnlyUsedInEntryBlock(AI))
255 InitializeRegForValue(AI);
257 // Initialize the mapping of values to registers. This is only set up for
258 // instruction values that are used outside of the block that defines
260 Function::iterator BB = Fn.begin(), EB = Fn.end();
261 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
262 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
263 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
264 const Type *Ty = AI->getAllocatedType();
265 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
267 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
270 TySize *= CUI->getZExtValue(); // Get total allocated size.
271 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
272 StaticAllocaMap[AI] =
273 MF.getFrameInfo()->CreateStackObject(TySize, Align);
276 for (; BB != EB; ++BB)
277 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
278 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
279 if (!isa<AllocaInst>(I) ||
280 !StaticAllocaMap.count(cast<AllocaInst>(I)))
281 InitializeRegForValue(I);
283 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
284 // also creates the initial PHI MachineInstrs, though none of the input
285 // operands are populated.
286 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
287 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
289 MF.getBasicBlockList().push_back(MBB);
291 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
294 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
295 if (PN->use_empty()) continue;
297 MVT::ValueType VT = TLI.getValueType(PN->getType());
298 unsigned NumRegisters = TLI.getNumRegisters(VT);
299 unsigned PHIReg = ValueMap[PN];
300 assert(PHIReg && "PHI node does not have an assigned virtual register!");
301 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
302 for (unsigned i = 0; i != NumRegisters; ++i)
303 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
308 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
309 /// the correctly promoted or expanded types. Assign these registers
310 /// consecutive vreg numbers and return the first assigned number.
311 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
312 MVT::ValueType VT = TLI.getValueType(V->getType());
314 unsigned NumRegisters = TLI.getNumRegisters(VT);
315 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
317 unsigned R = MakeReg(RegisterVT);
318 for (unsigned i = 1; i != NumRegisters; ++i)
324 //===----------------------------------------------------------------------===//
325 /// SelectionDAGLowering - This is the common target-independent lowering
326 /// implementation that is parameterized by a TargetLowering object.
327 /// Also, targets can overload any lowering method.
330 class SelectionDAGLowering {
331 MachineBasicBlock *CurMBB;
333 DenseMap<const Value*, SDOperand> NodeMap;
335 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
336 /// them up and then emit token factor nodes when possible. This allows us to
337 /// get simple disambiguation between loads without worrying about alias
339 std::vector<SDOperand> PendingLoads;
341 /// Case - A struct to record the Value for a switch case, and the
342 /// case's target basic block.
346 MachineBasicBlock* BB;
348 Case() : Low(0), High(0), BB(0) { }
349 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
350 Low(low), High(high), BB(bb) { }
351 uint64_t size() const {
352 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
353 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
354 return (rHigh - rLow + 1ULL);
360 MachineBasicBlock* BB;
363 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
364 Mask(mask), BB(bb), Bits(bits) { }
367 typedef std::vector<Case> CaseVector;
368 typedef std::vector<CaseBits> CaseBitsVector;
369 typedef CaseVector::iterator CaseItr;
370 typedef std::pair<CaseItr, CaseItr> CaseRange;
372 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
373 /// of conditional branches.
375 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
376 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
378 /// CaseBB - The MBB in which to emit the compare and branch
379 MachineBasicBlock *CaseBB;
380 /// LT, GE - If nonzero, we know the current case value must be less-than or
381 /// greater-than-or-equal-to these Constants.
384 /// Range - A pair of iterators representing the range of case values to be
385 /// processed at this point in the binary search tree.
389 typedef std::vector<CaseRec> CaseRecVector;
391 /// The comparison function for sorting the switch case values in the vector.
392 /// WARNING: Case ranges should be disjoint!
394 bool operator () (const Case& C1, const Case& C2) {
395 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
396 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
397 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
398 return CI1->getValue().slt(CI2->getValue());
403 bool operator () (const CaseBits& C1, const CaseBits& C2) {
404 return C1.Bits > C2.Bits;
408 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
411 // TLI - This is information that describes the available target features we
412 // need for lowering. This indicates when operations are unavailable,
413 // implemented with a libcall, etc.
416 const TargetData *TD;
419 /// SwitchCases - Vector of CaseBlock structures used to communicate
420 /// SwitchInst code generation information.
421 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
422 /// JTCases - Vector of JumpTable structures used to communicate
423 /// SwitchInst code generation information.
424 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
425 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
427 /// FuncInfo - Information about the function as a whole.
429 FunctionLoweringInfo &FuncInfo;
431 /// GCI - Garbage collection metadata for the function.
432 CollectorMetadata *GCI;
434 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
436 FunctionLoweringInfo &funcinfo,
437 CollectorMetadata *gci)
438 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
439 FuncInfo(funcinfo), GCI(gci) {
442 /// getRoot - Return the current virtual root of the Selection DAG.
444 SDOperand getRoot() {
445 if (PendingLoads.empty())
446 return DAG.getRoot();
448 if (PendingLoads.size() == 1) {
449 SDOperand Root = PendingLoads[0];
451 PendingLoads.clear();
455 // Otherwise, we have to make a token factor node.
456 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
457 &PendingLoads[0], PendingLoads.size());
458 PendingLoads.clear();
463 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
465 void visit(Instruction &I) { visit(I.getOpcode(), I); }
467 void visit(unsigned Opcode, User &I) {
468 // Note: this doesn't use InstVisitor, because it has to work with
469 // ConstantExpr's in addition to instructions.
471 default: assert(0 && "Unknown instruction type encountered!");
473 // Build the switch statement using the Instruction.def file.
474 #define HANDLE_INST(NUM, OPCODE, CLASS) \
475 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
476 #include "llvm/Instruction.def"
480 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
482 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
483 const Value *SV, SDOperand Root,
484 bool isVolatile, unsigned Alignment);
486 SDOperand getValue(const Value *V);
488 void setValue(const Value *V, SDOperand NewN) {
489 SDOperand &N = NodeMap[V];
490 assert(N.Val == 0 && "Already set a value for this node!");
494 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
495 std::set<unsigned> &OutputRegs,
496 std::set<unsigned> &InputRegs);
498 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
499 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
501 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
502 void ExportFromCurrentBlock(Value *V);
503 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
504 MachineBasicBlock *LandingPad = NULL);
506 // Terminator instructions.
507 void visitRet(ReturnInst &I);
508 void visitBr(BranchInst &I);
509 void visitSwitch(SwitchInst &I);
510 void visitUnreachable(UnreachableInst &I) { /* noop */ }
512 // Helpers for visitSwitch
513 bool handleSmallSwitchRange(CaseRec& CR,
514 CaseRecVector& WorkList,
516 MachineBasicBlock* Default);
517 bool handleJTSwitchCase(CaseRec& CR,
518 CaseRecVector& WorkList,
520 MachineBasicBlock* Default);
521 bool handleBTSplitSwitchCase(CaseRec& CR,
522 CaseRecVector& WorkList,
524 MachineBasicBlock* Default);
525 bool handleBitTestsSwitchCase(CaseRec& CR,
526 CaseRecVector& WorkList,
528 MachineBasicBlock* Default);
529 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
530 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
531 void visitBitTestCase(MachineBasicBlock* NextMBB,
533 SelectionDAGISel::BitTestCase &B);
534 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
535 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
536 SelectionDAGISel::JumpTableHeader &JTH);
538 // These all get lowered before this pass.
539 void visitInvoke(InvokeInst &I);
540 void visitUnwind(UnwindInst &I);
542 void visitBinary(User &I, unsigned OpCode);
543 void visitShift(User &I, unsigned Opcode);
544 void visitAdd(User &I) {
545 if (I.getType()->isFPOrFPVector())
546 visitBinary(I, ISD::FADD);
548 visitBinary(I, ISD::ADD);
550 void visitSub(User &I);
551 void visitMul(User &I) {
552 if (I.getType()->isFPOrFPVector())
553 visitBinary(I, ISD::FMUL);
555 visitBinary(I, ISD::MUL);
557 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
558 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
559 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
560 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
561 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
562 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
563 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
564 void visitOr (User &I) { visitBinary(I, ISD::OR); }
565 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
566 void visitShl (User &I) { visitShift(I, ISD::SHL); }
567 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
568 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
569 void visitICmp(User &I);
570 void visitFCmp(User &I);
571 // Visit the conversion instructions
572 void visitTrunc(User &I);
573 void visitZExt(User &I);
574 void visitSExt(User &I);
575 void visitFPTrunc(User &I);
576 void visitFPExt(User &I);
577 void visitFPToUI(User &I);
578 void visitFPToSI(User &I);
579 void visitUIToFP(User &I);
580 void visitSIToFP(User &I);
581 void visitPtrToInt(User &I);
582 void visitIntToPtr(User &I);
583 void visitBitCast(User &I);
585 void visitExtractElement(User &I);
586 void visitInsertElement(User &I);
587 void visitShuffleVector(User &I);
589 void visitGetElementPtr(User &I);
590 void visitSelect(User &I);
592 void visitMalloc(MallocInst &I);
593 void visitFree(FreeInst &I);
594 void visitAlloca(AllocaInst &I);
595 void visitLoad(LoadInst &I);
596 void visitStore(StoreInst &I);
597 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
598 void visitCall(CallInst &I);
599 void visitInlineAsm(CallSite CS);
600 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
601 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
603 void visitVAStart(CallInst &I);
604 void visitVAArg(VAArgInst &I);
605 void visitVAEnd(CallInst &I);
606 void visitVACopy(CallInst &I);
608 void visitMemIntrinsic(CallInst &I, unsigned Op);
610 void visitUserOp1(Instruction &I) {
611 assert(0 && "UserOp1 should not exist at instruction selection time!");
614 void visitUserOp2(Instruction &I) {
615 assert(0 && "UserOp2 should not exist at instruction selection time!");
619 } // end namespace llvm
622 /// getCopyFromParts - Create a value that contains the
623 /// specified legal parts combined into the value they represent.
624 static SDOperand getCopyFromParts(SelectionDAG &DAG,
625 const SDOperand *Parts,
627 MVT::ValueType PartVT,
628 MVT::ValueType ValueVT,
629 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
630 if (!MVT::isVector(ValueVT) || NumParts == 1) {
631 SDOperand Val = Parts[0];
633 // If the value was expanded, copy from the top part.
635 assert(NumParts == 2 &&
636 "Cannot expand to more than 2 elts yet!");
637 SDOperand Hi = Parts[1];
638 if (!DAG.getTargetLoweringInfo().isLittleEndian())
640 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
643 // Otherwise, if the value was promoted or extended, truncate it to the
645 if (PartVT == ValueVT)
648 if (MVT::isVector(PartVT)) {
649 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
650 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
653 if (MVT::isVector(ValueVT)) {
654 assert(NumParts == 1 &&
655 MVT::getVectorElementType(ValueVT) == PartVT &&
656 MVT::getVectorNumElements(ValueVT) == 1 &&
657 "Only trivial scalar-to-vector conversions should get here!");
658 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
661 if (MVT::isInteger(PartVT) &&
662 MVT::isInteger(ValueVT)) {
663 if (ValueVT < PartVT) {
664 // For a truncate, see if we have any information to
665 // indicate whether the truncated bits will always be
666 // zero or sign-extension.
667 if (AssertOp != ISD::DELETED_NODE)
668 Val = DAG.getNode(AssertOp, PartVT, Val,
669 DAG.getValueType(ValueVT));
670 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
672 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
676 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
677 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, DAG.getIntPtrConstant(0));
679 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
680 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
682 assert(0 && "Unknown mismatch!");
685 // Handle a multi-element vector.
686 MVT::ValueType IntermediateVT, RegisterVT;
687 unsigned NumIntermediates;
689 DAG.getTargetLoweringInfo()
690 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
693 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
694 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
695 assert(RegisterVT == Parts[0].getValueType() &&
696 "Part type doesn't match part!");
698 // Assemble the parts into intermediate operands.
699 SmallVector<SDOperand, 8> Ops(NumIntermediates);
700 if (NumIntermediates == NumParts) {
701 // If the register was not expanded, truncate or copy the value,
703 for (unsigned i = 0; i != NumParts; ++i)
704 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
705 PartVT, IntermediateVT);
706 } else if (NumParts > 0) {
707 // If the intermediate type was expanded, build the intermediate operands
709 assert(NumParts % NumIntermediates == 0 &&
710 "Must expand into a divisible number of parts!");
711 unsigned Factor = NumParts / NumIntermediates;
712 for (unsigned i = 0; i != NumIntermediates; ++i)
713 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
714 PartVT, IntermediateVT);
717 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
719 return DAG.getNode(MVT::isVector(IntermediateVT) ?
720 ISD::CONCAT_VECTORS :
722 ValueVT, &Ops[0], NumIntermediates);
725 /// getCopyToParts - Create a series of nodes that contain the
726 /// specified value split into legal parts.
727 static void getCopyToParts(SelectionDAG &DAG,
731 MVT::ValueType PartVT) {
732 TargetLowering &TLI = DAG.getTargetLoweringInfo();
733 MVT::ValueType PtrVT = TLI.getPointerTy();
734 MVT::ValueType ValueVT = Val.getValueType();
736 if (!MVT::isVector(ValueVT) || NumParts == 1) {
737 // If the value was expanded, copy from the parts.
739 for (unsigned i = 0; i != NumParts; ++i)
740 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
741 DAG.getConstant(i, PtrVT));
742 if (!DAG.getTargetLoweringInfo().isLittleEndian())
743 std::reverse(Parts, Parts + NumParts);
747 // If there is a single part and the types differ, this must be
749 if (PartVT != ValueVT) {
750 if (MVT::isVector(PartVT)) {
751 assert(MVT::isVector(ValueVT) &&
752 "Not a vector-vector cast?");
753 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
754 } else if (MVT::isVector(ValueVT)) {
755 assert(NumParts == 1 &&
756 MVT::getVectorElementType(ValueVT) == PartVT &&
757 MVT::getVectorNumElements(ValueVT) == 1 &&
758 "Only trivial vector-to-scalar conversions should get here!");
759 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
760 DAG.getConstant(0, PtrVT));
761 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
762 if (PartVT < ValueVT)
763 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
765 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
766 } else if (MVT::isFloatingPoint(PartVT) &&
767 MVT::isFloatingPoint(ValueVT)) {
768 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
769 } else if (MVT::getSizeInBits(PartVT) ==
770 MVT::getSizeInBits(ValueVT)) {
771 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
773 assert(0 && "Unknown mismatch!");
780 // Handle a multi-element vector.
781 MVT::ValueType IntermediateVT, RegisterVT;
782 unsigned NumIntermediates;
784 DAG.getTargetLoweringInfo()
785 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
787 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
789 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
790 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
792 // Split the vector into intermediate operands.
793 SmallVector<SDOperand, 8> Ops(NumIntermediates);
794 for (unsigned i = 0; i != NumIntermediates; ++i)
795 if (MVT::isVector(IntermediateVT))
796 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
798 DAG.getConstant(i * (NumElements / NumIntermediates),
801 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
803 DAG.getConstant(i, PtrVT));
805 // Split the intermediate operands into legal parts.
806 if (NumParts == NumIntermediates) {
807 // If the register was not expanded, promote or copy the value,
809 for (unsigned i = 0; i != NumParts; ++i)
810 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
811 } else if (NumParts > 0) {
812 // If the intermediate type was expanded, split each the value into
814 assert(NumParts % NumIntermediates == 0 &&
815 "Must expand into a divisible number of parts!");
816 unsigned Factor = NumParts / NumIntermediates;
817 for (unsigned i = 0; i != NumIntermediates; ++i)
818 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
823 SDOperand SelectionDAGLowering::getValue(const Value *V) {
824 SDOperand &N = NodeMap[V];
827 const Type *VTy = V->getType();
828 MVT::ValueType VT = TLI.getValueType(VTy);
829 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
830 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
831 visit(CE->getOpcode(), *CE);
832 SDOperand N1 = NodeMap[V];
833 assert(N1.Val && "visit didn't populate the ValueMap!");
835 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
836 return N = DAG.getGlobalAddress(GV, VT);
837 } else if (isa<ConstantPointerNull>(C)) {
838 return N = DAG.getConstant(0, TLI.getPointerTy());
839 } else if (isa<UndefValue>(C)) {
840 if (!isa<VectorType>(VTy))
841 return N = DAG.getNode(ISD::UNDEF, VT);
843 // Create a BUILD_VECTOR of undef nodes.
844 const VectorType *PTy = cast<VectorType>(VTy);
845 unsigned NumElements = PTy->getNumElements();
846 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
848 SmallVector<SDOperand, 8> Ops;
849 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
851 // Create a VConstant node with generic Vector type.
852 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
853 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
854 &Ops[0], Ops.size());
855 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
856 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
857 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
858 unsigned NumElements = PTy->getNumElements();
859 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
861 // Now that we know the number and type of the elements, push a
862 // Constant or ConstantFP node onto the ops list for each element of
863 // the vector constant.
864 SmallVector<SDOperand, 8> Ops;
865 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
866 for (unsigned i = 0; i != NumElements; ++i)
867 Ops.push_back(getValue(CP->getOperand(i)));
869 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
871 if (MVT::isFloatingPoint(PVT))
872 Op = DAG.getConstantFP(0, PVT);
874 Op = DAG.getConstant(0, PVT);
875 Ops.assign(NumElements, Op);
878 // Create a BUILD_VECTOR node.
879 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
880 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
883 // Canonicalize all constant ints to be unsigned.
884 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
888 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
889 std::map<const AllocaInst*, int>::iterator SI =
890 FuncInfo.StaticAllocaMap.find(AI);
891 if (SI != FuncInfo.StaticAllocaMap.end())
892 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
895 unsigned InReg = FuncInfo.ValueMap[V];
896 assert(InReg && "Value not in map!");
898 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
899 unsigned NumRegs = TLI.getNumRegisters(VT);
901 std::vector<unsigned> Regs(NumRegs);
902 for (unsigned i = 0; i != NumRegs; ++i)
905 RegsForValue RFV(Regs, RegisterVT, VT);
906 SDOperand Chain = DAG.getEntryNode();
908 return RFV.getCopyFromRegs(DAG, Chain, NULL);
912 void SelectionDAGLowering::visitRet(ReturnInst &I) {
913 if (I.getNumOperands() == 0) {
914 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
917 SmallVector<SDOperand, 8> NewValues;
918 NewValues.push_back(getRoot());
919 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
920 SDOperand RetOp = getValue(I.getOperand(i));
922 // If this is an integer return value, we need to promote it ourselves to
923 // the full width of a register, since getCopyToParts and Legalize will use
924 // ANY_EXTEND rather than sign/zero.
925 // FIXME: C calling convention requires the return type to be promoted to
926 // at least 32-bit. But this is not necessary for non-C calling conventions.
927 if (MVT::isInteger(RetOp.getValueType()) &&
928 RetOp.getValueType() < MVT::i64) {
929 MVT::ValueType TmpVT;
930 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
931 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
934 const Function *F = I.getParent()->getParent();
935 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
936 if (F->paramHasAttr(0, ParamAttr::SExt))
937 ExtendKind = ISD::SIGN_EXTEND;
938 if (F->paramHasAttr(0, ParamAttr::ZExt))
939 ExtendKind = ISD::ZERO_EXTEND;
940 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
941 NewValues.push_back(RetOp);
942 NewValues.push_back(DAG.getConstant(false, MVT::i32));
944 MVT::ValueType VT = RetOp.getValueType();
945 unsigned NumParts = TLI.getNumRegisters(VT);
946 MVT::ValueType PartVT = TLI.getRegisterType(VT);
947 SmallVector<SDOperand, 4> Parts(NumParts);
948 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
949 for (unsigned i = 0; i < NumParts; ++i) {
950 NewValues.push_back(Parts[i]);
951 NewValues.push_back(DAG.getConstant(false, MVT::i32));
955 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
956 &NewValues[0], NewValues.size()));
959 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
960 /// the current basic block, add it to ValueMap now so that we'll get a
962 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
963 // No need to export constants.
964 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
967 if (FuncInfo.isExportedInst(V)) return;
969 unsigned Reg = FuncInfo.InitializeRegForValue(V);
970 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
973 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
974 const BasicBlock *FromBB) {
975 // The operands of the setcc have to be in this block. We don't know
976 // how to export them from some other block.
977 if (Instruction *VI = dyn_cast<Instruction>(V)) {
978 // Can export from current BB.
979 if (VI->getParent() == FromBB)
982 // Is already exported, noop.
983 return FuncInfo.isExportedInst(V);
986 // If this is an argument, we can export it if the BB is the entry block or
987 // if it is already exported.
988 if (isa<Argument>(V)) {
989 if (FromBB == &FromBB->getParent()->getEntryBlock())
992 // Otherwise, can only export this if it is already exported.
993 return FuncInfo.isExportedInst(V);
996 // Otherwise, constants can always be exported.
1000 static bool InBlock(const Value *V, const BasicBlock *BB) {
1001 if (const Instruction *I = dyn_cast<Instruction>(V))
1002 return I->getParent() == BB;
1006 /// FindMergedConditions - If Cond is an expression like
1007 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1008 MachineBasicBlock *TBB,
1009 MachineBasicBlock *FBB,
1010 MachineBasicBlock *CurBB,
1012 // If this node is not part of the or/and tree, emit it as a branch.
1013 Instruction *BOp = dyn_cast<Instruction>(Cond);
1015 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1016 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1017 BOp->getParent() != CurBB->getBasicBlock() ||
1018 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1019 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1020 const BasicBlock *BB = CurBB->getBasicBlock();
1022 // If the leaf of the tree is a comparison, merge the condition into
1024 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1025 // The operands of the cmp have to be in this block. We don't know
1026 // how to export them from some other block. If this is the first block
1027 // of the sequence, no exporting is needed.
1029 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1030 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1031 BOp = cast<Instruction>(Cond);
1032 ISD::CondCode Condition;
1033 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1034 switch (IC->getPredicate()) {
1035 default: assert(0 && "Unknown icmp predicate opcode!");
1036 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1037 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1038 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1039 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1040 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1041 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1042 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1043 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1044 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1045 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1047 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1048 ISD::CondCode FPC, FOC;
1049 switch (FC->getPredicate()) {
1050 default: assert(0 && "Unknown fcmp predicate opcode!");
1051 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1052 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1053 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1054 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1055 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1056 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1057 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1058 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1059 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1060 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1061 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1062 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1063 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1064 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1065 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1066 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1068 if (FiniteOnlyFPMath())
1073 Condition = ISD::SETEQ; // silence warning.
1074 assert(0 && "Unknown compare instruction");
1077 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1078 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1079 SwitchCases.push_back(CB);
1083 // Create a CaseBlock record representing this branch.
1084 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1085 NULL, TBB, FBB, CurBB);
1086 SwitchCases.push_back(CB);
1091 // Create TmpBB after CurBB.
1092 MachineFunction::iterator BBI = CurBB;
1093 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1094 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1096 if (Opc == Instruction::Or) {
1097 // Codegen X | Y as:
1105 // Emit the LHS condition.
1106 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1108 // Emit the RHS condition into TmpBB.
1109 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1111 assert(Opc == Instruction::And && "Unknown merge op!");
1112 // Codegen X & Y as:
1119 // This requires creation of TmpBB after CurBB.
1121 // Emit the LHS condition.
1122 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1124 // Emit the RHS condition into TmpBB.
1125 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1129 /// If the set of cases should be emitted as a series of branches, return true.
1130 /// If we should emit this as a bunch of and/or'd together conditions, return
1133 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1134 if (Cases.size() != 2) return true;
1136 // If this is two comparisons of the same values or'd or and'd together, they
1137 // will get folded into a single comparison, so don't emit two blocks.
1138 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1139 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1140 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1141 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1148 void SelectionDAGLowering::visitBr(BranchInst &I) {
1149 // Update machine-CFG edges.
1150 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1152 // Figure out which block is immediately after the current one.
1153 MachineBasicBlock *NextBlock = 0;
1154 MachineFunction::iterator BBI = CurMBB;
1155 if (++BBI != CurMBB->getParent()->end())
1158 if (I.isUnconditional()) {
1159 // If this is not a fall-through branch, emit the branch.
1160 if (Succ0MBB != NextBlock)
1161 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1162 DAG.getBasicBlock(Succ0MBB)));
1164 // Update machine-CFG edges.
1165 CurMBB->addSuccessor(Succ0MBB);
1169 // If this condition is one of the special cases we handle, do special stuff
1171 Value *CondVal = I.getCondition();
1172 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1174 // If this is a series of conditions that are or'd or and'd together, emit
1175 // this as a sequence of branches instead of setcc's with and/or operations.
1176 // For example, instead of something like:
1189 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1190 if (BOp->hasOneUse() &&
1191 (BOp->getOpcode() == Instruction::And ||
1192 BOp->getOpcode() == Instruction::Or)) {
1193 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1194 // If the compares in later blocks need to use values not currently
1195 // exported from this block, export them now. This block should always
1196 // be the first entry.
1197 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1199 // Allow some cases to be rejected.
1200 if (ShouldEmitAsBranches(SwitchCases)) {
1201 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1202 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1203 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1206 // Emit the branch for this block.
1207 visitSwitchCase(SwitchCases[0]);
1208 SwitchCases.erase(SwitchCases.begin());
1212 // Okay, we decided not to do this, remove any inserted MBB's and clear
1214 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1215 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1217 SwitchCases.clear();
1221 // Create a CaseBlock record representing this branch.
1222 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1223 NULL, Succ0MBB, Succ1MBB, CurMBB);
1224 // Use visitSwitchCase to actually insert the fast branch sequence for this
1226 visitSwitchCase(CB);
1229 /// visitSwitchCase - Emits the necessary code to represent a single node in
1230 /// the binary search tree resulting from lowering a switch instruction.
1231 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1233 SDOperand CondLHS = getValue(CB.CmpLHS);
1235 // Build the setcc now.
1236 if (CB.CmpMHS == NULL) {
1237 // Fold "(X == true)" to X and "(X == false)" to !X to
1238 // handle common cases produced by branch lowering.
1239 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1241 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1242 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1243 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1245 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1247 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1249 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1250 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1252 SDOperand CmpOp = getValue(CB.CmpMHS);
1253 MVT::ValueType VT = CmpOp.getValueType();
1255 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1256 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1258 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1259 Cond = DAG.getSetCC(MVT::i1, SUB,
1260 DAG.getConstant(High-Low, VT), ISD::SETULE);
1265 // Set NextBlock to be the MBB immediately after the current one, if any.
1266 // This is used to avoid emitting unnecessary branches to the next block.
1267 MachineBasicBlock *NextBlock = 0;
1268 MachineFunction::iterator BBI = CurMBB;
1269 if (++BBI != CurMBB->getParent()->end())
1272 // If the lhs block is the next block, invert the condition so that we can
1273 // fall through to the lhs instead of the rhs block.
1274 if (CB.TrueBB == NextBlock) {
1275 std::swap(CB.TrueBB, CB.FalseBB);
1276 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1277 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1279 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1280 DAG.getBasicBlock(CB.TrueBB));
1281 if (CB.FalseBB == NextBlock)
1282 DAG.setRoot(BrCond);
1284 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1285 DAG.getBasicBlock(CB.FalseBB)));
1286 // Update successor info
1287 CurMBB->addSuccessor(CB.TrueBB);
1288 CurMBB->addSuccessor(CB.FalseBB);
1291 /// visitJumpTable - Emit JumpTable node in the current MBB
1292 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1293 // Emit the code for the jump table
1294 assert(JT.Reg != -1U && "Should lower JT Header first!");
1295 MVT::ValueType PTy = TLI.getPointerTy();
1296 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1297 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1298 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1303 /// visitJumpTableHeader - This function emits necessary code to produce index
1304 /// in the JumpTable from switch case.
1305 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1306 SelectionDAGISel::JumpTableHeader &JTH) {
1307 // Subtract the lowest switch case value from the value being switched on
1308 // and conditional branch to default mbb if the result is greater than the
1309 // difference between smallest and largest cases.
1310 SDOperand SwitchOp = getValue(JTH.SValue);
1311 MVT::ValueType VT = SwitchOp.getValueType();
1312 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1313 DAG.getConstant(JTH.First, VT));
1315 // The SDNode we just created, which holds the value being switched on
1316 // minus the the smallest case value, needs to be copied to a virtual
1317 // register so it can be used as an index into the jump table in a
1318 // subsequent basic block. This value may be smaller or larger than the
1319 // target's pointer type, and therefore require extension or truncating.
1320 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1321 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1323 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1325 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1326 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1327 JT.Reg = JumpTableReg;
1329 // Emit the range check for the jump table, and branch to the default
1330 // block for the switch statement if the value being switched on exceeds
1331 // the largest case in the switch.
1332 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1333 DAG.getConstant(JTH.Last-JTH.First,VT),
1336 // Set NextBlock to be the MBB immediately after the current one, if any.
1337 // This is used to avoid emitting unnecessary branches to the next block.
1338 MachineBasicBlock *NextBlock = 0;
1339 MachineFunction::iterator BBI = CurMBB;
1340 if (++BBI != CurMBB->getParent()->end())
1343 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1344 DAG.getBasicBlock(JT.Default));
1346 if (JT.MBB == NextBlock)
1347 DAG.setRoot(BrCond);
1349 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1350 DAG.getBasicBlock(JT.MBB)));
1355 /// visitBitTestHeader - This function emits necessary code to produce value
1356 /// suitable for "bit tests"
1357 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1358 // Subtract the minimum value
1359 SDOperand SwitchOp = getValue(B.SValue);
1360 MVT::ValueType VT = SwitchOp.getValueType();
1361 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1362 DAG.getConstant(B.First, VT));
1365 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1366 DAG.getConstant(B.Range, VT),
1370 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1371 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1373 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1375 // Make desired shift
1376 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1377 DAG.getConstant(1, TLI.getPointerTy()),
1380 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1381 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1384 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1385 DAG.getBasicBlock(B.Default));
1387 // Set NextBlock to be the MBB immediately after the current one, if any.
1388 // This is used to avoid emitting unnecessary branches to the next block.
1389 MachineBasicBlock *NextBlock = 0;
1390 MachineFunction::iterator BBI = CurMBB;
1391 if (++BBI != CurMBB->getParent()->end())
1394 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1395 if (MBB == NextBlock)
1396 DAG.setRoot(BrRange);
1398 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1399 DAG.getBasicBlock(MBB)));
1401 CurMBB->addSuccessor(B.Default);
1402 CurMBB->addSuccessor(MBB);
1407 /// visitBitTestCase - this function produces one "bit test"
1408 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1410 SelectionDAGISel::BitTestCase &B) {
1411 // Emit bit tests and jumps
1412 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1414 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1416 DAG.getConstant(B.Mask,
1417 TLI.getPointerTy()));
1418 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1419 DAG.getConstant(0, TLI.getPointerTy()),
1421 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1422 AndCmp, DAG.getBasicBlock(B.TargetBB));
1424 // Set NextBlock to be the MBB immediately after the current one, if any.
1425 // This is used to avoid emitting unnecessary branches to the next block.
1426 MachineBasicBlock *NextBlock = 0;
1427 MachineFunction::iterator BBI = CurMBB;
1428 if (++BBI != CurMBB->getParent()->end())
1431 if (NextMBB == NextBlock)
1434 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1435 DAG.getBasicBlock(NextMBB)));
1437 CurMBB->addSuccessor(B.TargetBB);
1438 CurMBB->addSuccessor(NextMBB);
1443 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1444 // Retrieve successors.
1445 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1446 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1448 if (isa<InlineAsm>(I.getCalledValue()))
1451 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1453 // If the value of the invoke is used outside of its defining block, make it
1454 // available as a virtual register.
1455 if (!I.use_empty()) {
1456 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1457 if (VMI != FuncInfo.ValueMap.end())
1458 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1461 // Drop into normal successor.
1462 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1463 DAG.getBasicBlock(Return)));
1465 // Update successor info
1466 CurMBB->addSuccessor(Return);
1467 CurMBB->addSuccessor(LandingPad);
1470 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1473 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1474 /// small case ranges).
1475 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1476 CaseRecVector& WorkList,
1478 MachineBasicBlock* Default) {
1479 Case& BackCase = *(CR.Range.second-1);
1481 // Size is the number of Cases represented by this range.
1482 unsigned Size = CR.Range.second - CR.Range.first;
1486 // Get the MachineFunction which holds the current MBB. This is used when
1487 // inserting any additional MBBs necessary to represent the switch.
1488 MachineFunction *CurMF = CurMBB->getParent();
1490 // Figure out which block is immediately after the current one.
1491 MachineBasicBlock *NextBlock = 0;
1492 MachineFunction::iterator BBI = CR.CaseBB;
1494 if (++BBI != CurMBB->getParent()->end())
1497 // TODO: If any two of the cases has the same destination, and if one value
1498 // is the same as the other, but has one bit unset that the other has set,
1499 // use bit manipulation to do two compares at once. For example:
1500 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1502 // Rearrange the case blocks so that the last one falls through if possible.
1503 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1504 // The last case block won't fall through into 'NextBlock' if we emit the
1505 // branches in this order. See if rearranging a case value would help.
1506 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1507 if (I->BB == NextBlock) {
1508 std::swap(*I, BackCase);
1514 // Create a CaseBlock record representing a conditional branch to
1515 // the Case's target mbb if the value being switched on SV is equal
1517 MachineBasicBlock *CurBlock = CR.CaseBB;
1518 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1519 MachineBasicBlock *FallThrough;
1521 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1522 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1524 // If the last case doesn't match, go to the default block.
1525 FallThrough = Default;
1528 Value *RHS, *LHS, *MHS;
1530 if (I->High == I->Low) {
1531 // This is just small small case range :) containing exactly 1 case
1533 LHS = SV; RHS = I->High; MHS = NULL;
1536 LHS = I->Low; MHS = SV; RHS = I->High;
1538 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1539 I->BB, FallThrough, CurBlock);
1541 // If emitting the first comparison, just call visitSwitchCase to emit the
1542 // code into the current block. Otherwise, push the CaseBlock onto the
1543 // vector to be later processed by SDISel, and insert the node's MBB
1544 // before the next MBB.
1545 if (CurBlock == CurMBB)
1546 visitSwitchCase(CB);
1548 SwitchCases.push_back(CB);
1550 CurBlock = FallThrough;
1556 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1557 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1558 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1561 /// handleJTSwitchCase - Emit jumptable for current switch case range
1562 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1563 CaseRecVector& WorkList,
1565 MachineBasicBlock* Default) {
1566 Case& FrontCase = *CR.Range.first;
1567 Case& BackCase = *(CR.Range.second-1);
1569 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1570 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1573 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1577 if (!areJTsAllowed(TLI) || TSize <= 3)
1580 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1584 DOUT << "Lowering jump table\n"
1585 << "First entry: " << First << ". Last entry: " << Last << "\n"
1586 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1588 // Get the MachineFunction which holds the current MBB. This is used when
1589 // inserting any additional MBBs necessary to represent the switch.
1590 MachineFunction *CurMF = CurMBB->getParent();
1592 // Figure out which block is immediately after the current one.
1593 MachineBasicBlock *NextBlock = 0;
1594 MachineFunction::iterator BBI = CR.CaseBB;
1596 if (++BBI != CurMBB->getParent()->end())
1599 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1601 // Create a new basic block to hold the code for loading the address
1602 // of the jump table, and jumping to it. Update successor information;
1603 // we will either branch to the default case for the switch, or the jump
1605 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1606 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1607 CR.CaseBB->addSuccessor(Default);
1608 CR.CaseBB->addSuccessor(JumpTableBB);
1610 // Build a vector of destination BBs, corresponding to each target
1611 // of the jump table. If the value of the jump table slot corresponds to
1612 // a case statement, push the case's BB onto the vector, otherwise, push
1614 std::vector<MachineBasicBlock*> DestBBs;
1615 int64_t TEI = First;
1616 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1617 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1618 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1620 if ((Low <= TEI) && (TEI <= High)) {
1621 DestBBs.push_back(I->BB);
1625 DestBBs.push_back(Default);
1629 // Update successor info. Add one edge to each unique successor.
1630 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1631 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1632 E = DestBBs.end(); I != E; ++I) {
1633 if (!SuccsHandled[(*I)->getNumber()]) {
1634 SuccsHandled[(*I)->getNumber()] = true;
1635 JumpTableBB->addSuccessor(*I);
1639 // Create a jump table index for this jump table, or return an existing
1641 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1643 // Set the jump table information so that we can codegen it as a second
1644 // MachineBasicBlock
1645 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1646 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1647 (CR.CaseBB == CurMBB));
1648 if (CR.CaseBB == CurMBB)
1649 visitJumpTableHeader(JT, JTH);
1651 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1656 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1658 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1659 CaseRecVector& WorkList,
1661 MachineBasicBlock* Default) {
1662 // Get the MachineFunction which holds the current MBB. This is used when
1663 // inserting any additional MBBs necessary to represent the switch.
1664 MachineFunction *CurMF = CurMBB->getParent();
1666 // Figure out which block is immediately after the current one.
1667 MachineBasicBlock *NextBlock = 0;
1668 MachineFunction::iterator BBI = CR.CaseBB;
1670 if (++BBI != CurMBB->getParent()->end())
1673 Case& FrontCase = *CR.Range.first;
1674 Case& BackCase = *(CR.Range.second-1);
1675 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1677 // Size is the number of Cases represented by this range.
1678 unsigned Size = CR.Range.second - CR.Range.first;
1680 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1681 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1683 CaseItr Pivot = CR.Range.first + Size/2;
1685 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1686 // (heuristically) allow us to emit JumpTable's later.
1688 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1692 uint64_t LSize = FrontCase.size();
1693 uint64_t RSize = TSize-LSize;
1694 DOUT << "Selecting best pivot: \n"
1695 << "First: " << First << ", Last: " << Last <<"\n"
1696 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1697 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1699 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1700 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1701 assert((RBegin-LEnd>=1) && "Invalid case distance");
1702 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1703 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1704 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1705 // Should always split in some non-trivial place
1707 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1708 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1709 << "Metric: " << Metric << "\n";
1710 if (FMetric < Metric) {
1713 DOUT << "Current metric set to: " << FMetric << "\n";
1719 if (areJTsAllowed(TLI)) {
1720 // If our case is dense we *really* should handle it earlier!
1721 assert((FMetric > 0) && "Should handle dense range earlier!");
1723 Pivot = CR.Range.first + Size/2;
1726 CaseRange LHSR(CR.Range.first, Pivot);
1727 CaseRange RHSR(Pivot, CR.Range.second);
1728 Constant *C = Pivot->Low;
1729 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1731 // We know that we branch to the LHS if the Value being switched on is
1732 // less than the Pivot value, C. We use this to optimize our binary
1733 // tree a bit, by recognizing that if SV is greater than or equal to the
1734 // LHS's Case Value, and that Case Value is exactly one less than the
1735 // Pivot's Value, then we can branch directly to the LHS's Target,
1736 // rather than creating a leaf node for it.
1737 if ((LHSR.second - LHSR.first) == 1 &&
1738 LHSR.first->High == CR.GE &&
1739 cast<ConstantInt>(C)->getSExtValue() ==
1740 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1741 TrueBB = LHSR.first->BB;
1743 TrueBB = new MachineBasicBlock(LLVMBB);
1744 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1745 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1748 // Similar to the optimization above, if the Value being switched on is
1749 // known to be less than the Constant CR.LT, and the current Case Value
1750 // is CR.LT - 1, then we can branch directly to the target block for
1751 // the current Case Value, rather than emitting a RHS leaf node for it.
1752 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1753 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1754 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1755 FalseBB = RHSR.first->BB;
1757 FalseBB = new MachineBasicBlock(LLVMBB);
1758 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1759 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1762 // Create a CaseBlock record representing a conditional branch to
1763 // the LHS node if the value being switched on SV is less than C.
1764 // Otherwise, branch to LHS.
1765 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1766 TrueBB, FalseBB, CR.CaseBB);
1768 if (CR.CaseBB == CurMBB)
1769 visitSwitchCase(CB);
1771 SwitchCases.push_back(CB);
1776 /// handleBitTestsSwitchCase - if current case range has few destination and
1777 /// range span less, than machine word bitwidth, encode case range into series
1778 /// of masks and emit bit tests with these masks.
1779 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1780 CaseRecVector& WorkList,
1782 MachineBasicBlock* Default){
1783 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1785 Case& FrontCase = *CR.Range.first;
1786 Case& BackCase = *(CR.Range.second-1);
1788 // Get the MachineFunction which holds the current MBB. This is used when
1789 // inserting any additional MBBs necessary to represent the switch.
1790 MachineFunction *CurMF = CurMBB->getParent();
1792 unsigned numCmps = 0;
1793 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1795 // Single case counts one, case range - two.
1796 if (I->Low == I->High)
1802 // Count unique destinations
1803 SmallSet<MachineBasicBlock*, 4> Dests;
1804 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1805 Dests.insert(I->BB);
1806 if (Dests.size() > 3)
1807 // Don't bother the code below, if there are too much unique destinations
1810 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1811 << "Total number of comparisons: " << numCmps << "\n";
1813 // Compute span of values.
1814 Constant* minValue = FrontCase.Low;
1815 Constant* maxValue = BackCase.High;
1816 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1817 cast<ConstantInt>(minValue)->getSExtValue();
1818 DOUT << "Compare range: " << range << "\n"
1819 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1820 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1822 if (range>=IntPtrBits ||
1823 (!(Dests.size() == 1 && numCmps >= 3) &&
1824 !(Dests.size() == 2 && numCmps >= 5) &&
1825 !(Dests.size() >= 3 && numCmps >= 6)))
1828 DOUT << "Emitting bit tests\n";
1829 int64_t lowBound = 0;
1831 // Optimize the case where all the case values fit in a
1832 // word without having to subtract minValue. In this case,
1833 // we can optimize away the subtraction.
1834 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1835 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1836 range = cast<ConstantInt>(maxValue)->getSExtValue();
1838 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1841 CaseBitsVector CasesBits;
1842 unsigned i, count = 0;
1844 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1845 MachineBasicBlock* Dest = I->BB;
1846 for (i = 0; i < count; ++i)
1847 if (Dest == CasesBits[i].BB)
1851 assert((count < 3) && "Too much destinations to test!");
1852 CasesBits.push_back(CaseBits(0, Dest, 0));
1856 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1857 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1859 for (uint64_t j = lo; j <= hi; j++) {
1860 CasesBits[i].Mask |= 1ULL << j;
1861 CasesBits[i].Bits++;
1865 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1867 SelectionDAGISel::BitTestInfo BTC;
1869 // Figure out which block is immediately after the current one.
1870 MachineFunction::iterator BBI = CR.CaseBB;
1873 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1876 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1877 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1878 << ", BB: " << CasesBits[i].BB << "\n";
1880 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1881 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1882 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1887 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1888 -1U, (CR.CaseBB == CurMBB),
1889 CR.CaseBB, Default, BTC);
1891 if (CR.CaseBB == CurMBB)
1892 visitBitTestHeader(BTB);
1894 BitTestCases.push_back(BTB);
1900 // Clusterify - Transform simple list of Cases into list of CaseRange's
1901 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1902 const SwitchInst& SI) {
1903 unsigned numCmps = 0;
1905 // Start with "simple" cases
1906 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1907 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1908 Cases.push_back(Case(SI.getSuccessorValue(i),
1909 SI.getSuccessorValue(i),
1912 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1914 // Merge case into clusters
1915 if (Cases.size()>=2)
1916 // Must recompute end() each iteration because it may be
1917 // invalidated by erase if we hold on to it
1918 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1919 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1920 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1921 MachineBasicBlock* nextBB = J->BB;
1922 MachineBasicBlock* currentBB = I->BB;
1924 // If the two neighboring cases go to the same destination, merge them
1925 // into a single case.
1926 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1934 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1935 if (I->Low != I->High)
1936 // A range counts double, since it requires two compares.
1943 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1944 // Figure out which block is immediately after the current one.
1945 MachineBasicBlock *NextBlock = 0;
1946 MachineFunction::iterator BBI = CurMBB;
1948 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1950 // If there is only the default destination, branch to it if it is not the
1951 // next basic block. Otherwise, just fall through.
1952 if (SI.getNumOperands() == 2) {
1953 // Update machine-CFG edges.
1955 // If this is not a fall-through branch, emit the branch.
1956 if (Default != NextBlock)
1957 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1958 DAG.getBasicBlock(Default)));
1960 CurMBB->addSuccessor(Default);
1964 // If there are any non-default case statements, create a vector of Cases
1965 // representing each one, and sort the vector so that we can efficiently
1966 // create a binary search tree from them.
1968 unsigned numCmps = Clusterify(Cases, SI);
1969 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1970 << ". Total compares: " << numCmps << "\n";
1972 // Get the Value to be switched on and default basic blocks, which will be
1973 // inserted into CaseBlock records, representing basic blocks in the binary
1975 Value *SV = SI.getOperand(0);
1977 // Push the initial CaseRec onto the worklist
1978 CaseRecVector WorkList;
1979 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1981 while (!WorkList.empty()) {
1982 // Grab a record representing a case range to process off the worklist
1983 CaseRec CR = WorkList.back();
1984 WorkList.pop_back();
1986 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1989 // If the range has few cases (two or less) emit a series of specific
1991 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1994 // If the switch has more than 5 blocks, and at least 40% dense, and the
1995 // target supports indirect branches, then emit a jump table rather than
1996 // lowering the switch to a binary tree of conditional branches.
1997 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2000 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2001 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2002 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2007 void SelectionDAGLowering::visitSub(User &I) {
2008 // -0.0 - X --> fneg
2009 const Type *Ty = I.getType();
2010 if (isa<VectorType>(Ty)) {
2011 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2012 const VectorType *DestTy = cast<VectorType>(I.getType());
2013 const Type *ElTy = DestTy->getElementType();
2014 if (ElTy->isFloatingPoint()) {
2015 unsigned VL = DestTy->getNumElements();
2016 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2017 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2019 SDOperand Op2 = getValue(I.getOperand(1));
2020 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2026 if (Ty->isFloatingPoint()) {
2027 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2028 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2029 SDOperand Op2 = getValue(I.getOperand(1));
2030 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2035 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2038 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2039 SDOperand Op1 = getValue(I.getOperand(0));
2040 SDOperand Op2 = getValue(I.getOperand(1));
2042 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2045 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2046 SDOperand Op1 = getValue(I.getOperand(0));
2047 SDOperand Op2 = getValue(I.getOperand(1));
2049 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2050 MVT::getSizeInBits(Op2.getValueType()))
2051 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2052 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2053 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2055 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2058 void SelectionDAGLowering::visitICmp(User &I) {
2059 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2060 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2061 predicate = IC->getPredicate();
2062 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2063 predicate = ICmpInst::Predicate(IC->getPredicate());
2064 SDOperand Op1 = getValue(I.getOperand(0));
2065 SDOperand Op2 = getValue(I.getOperand(1));
2066 ISD::CondCode Opcode;
2067 switch (predicate) {
2068 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2069 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2070 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2071 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2072 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2073 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2074 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2075 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2076 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2077 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2079 assert(!"Invalid ICmp predicate value");
2080 Opcode = ISD::SETEQ;
2083 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2086 void SelectionDAGLowering::visitFCmp(User &I) {
2087 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2088 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2089 predicate = FC->getPredicate();
2090 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2091 predicate = FCmpInst::Predicate(FC->getPredicate());
2092 SDOperand Op1 = getValue(I.getOperand(0));
2093 SDOperand Op2 = getValue(I.getOperand(1));
2094 ISD::CondCode Condition, FOC, FPC;
2095 switch (predicate) {
2096 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2097 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2098 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2099 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2100 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2101 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2102 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2103 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2104 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2105 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2106 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2107 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2108 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2109 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2110 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2111 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2113 assert(!"Invalid FCmp predicate value");
2114 FOC = FPC = ISD::SETFALSE;
2117 if (FiniteOnlyFPMath())
2121 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2124 void SelectionDAGLowering::visitSelect(User &I) {
2125 SDOperand Cond = getValue(I.getOperand(0));
2126 SDOperand TrueVal = getValue(I.getOperand(1));
2127 SDOperand FalseVal = getValue(I.getOperand(2));
2128 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2129 TrueVal, FalseVal));
2133 void SelectionDAGLowering::visitTrunc(User &I) {
2134 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2135 SDOperand N = getValue(I.getOperand(0));
2136 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2137 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2140 void SelectionDAGLowering::visitZExt(User &I) {
2141 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2142 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2143 SDOperand N = getValue(I.getOperand(0));
2144 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2145 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2148 void SelectionDAGLowering::visitSExt(User &I) {
2149 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2150 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2151 SDOperand N = getValue(I.getOperand(0));
2152 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2153 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2156 void SelectionDAGLowering::visitFPTrunc(User &I) {
2157 // FPTrunc is never a no-op cast, no need to check
2158 SDOperand N = getValue(I.getOperand(0));
2159 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2160 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2163 void SelectionDAGLowering::visitFPExt(User &I){
2164 // FPTrunc is never a no-op cast, no need to check
2165 SDOperand N = getValue(I.getOperand(0));
2166 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2167 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2170 void SelectionDAGLowering::visitFPToUI(User &I) {
2171 // FPToUI is never a no-op cast, no need to check
2172 SDOperand N = getValue(I.getOperand(0));
2173 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2174 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2177 void SelectionDAGLowering::visitFPToSI(User &I) {
2178 // FPToSI is never a no-op cast, no need to check
2179 SDOperand N = getValue(I.getOperand(0));
2180 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2181 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2184 void SelectionDAGLowering::visitUIToFP(User &I) {
2185 // UIToFP is never a no-op cast, no need to check
2186 SDOperand N = getValue(I.getOperand(0));
2187 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2188 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2191 void SelectionDAGLowering::visitSIToFP(User &I){
2192 // UIToFP is never a no-op cast, no need to check
2193 SDOperand N = getValue(I.getOperand(0));
2194 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2195 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2198 void SelectionDAGLowering::visitPtrToInt(User &I) {
2199 // What to do depends on the size of the integer and the size of the pointer.
2200 // We can either truncate, zero extend, or no-op, accordingly.
2201 SDOperand N = getValue(I.getOperand(0));
2202 MVT::ValueType SrcVT = N.getValueType();
2203 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2205 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2206 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2208 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2209 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2210 setValue(&I, Result);
2213 void SelectionDAGLowering::visitIntToPtr(User &I) {
2214 // What to do depends on the size of the integer and the size of the pointer.
2215 // We can either truncate, zero extend, or no-op, accordingly.
2216 SDOperand N = getValue(I.getOperand(0));
2217 MVT::ValueType SrcVT = N.getValueType();
2218 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2219 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2220 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2222 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2223 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2226 void SelectionDAGLowering::visitBitCast(User &I) {
2227 SDOperand N = getValue(I.getOperand(0));
2228 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2230 // BitCast assures us that source and destination are the same size so this
2231 // is either a BIT_CONVERT or a no-op.
2232 if (DestVT != N.getValueType())
2233 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2235 setValue(&I, N); // noop cast.
2238 void SelectionDAGLowering::visitInsertElement(User &I) {
2239 SDOperand InVec = getValue(I.getOperand(0));
2240 SDOperand InVal = getValue(I.getOperand(1));
2241 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2242 getValue(I.getOperand(2)));
2244 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2245 TLI.getValueType(I.getType()),
2246 InVec, InVal, InIdx));
2249 void SelectionDAGLowering::visitExtractElement(User &I) {
2250 SDOperand InVec = getValue(I.getOperand(0));
2251 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2252 getValue(I.getOperand(1)));
2253 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2254 TLI.getValueType(I.getType()), InVec, InIdx));
2257 void SelectionDAGLowering::visitShuffleVector(User &I) {
2258 SDOperand V1 = getValue(I.getOperand(0));
2259 SDOperand V2 = getValue(I.getOperand(1));
2260 SDOperand Mask = getValue(I.getOperand(2));
2262 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2263 TLI.getValueType(I.getType()),
2268 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2269 SDOperand N = getValue(I.getOperand(0));
2270 const Type *Ty = I.getOperand(0)->getType();
2272 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2275 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2276 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2279 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2280 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2281 DAG.getIntPtrConstant(Offset));
2283 Ty = StTy->getElementType(Field);
2285 Ty = cast<SequentialType>(Ty)->getElementType();
2287 // If this is a constant subscript, handle it quickly.
2288 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2289 if (CI->getZExtValue() == 0) continue;
2291 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2292 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2293 DAG.getIntPtrConstant(Offs));
2297 // N = N + Idx * ElementSize;
2298 uint64_t ElementSize = TD->getABITypeSize(Ty);
2299 SDOperand IdxN = getValue(Idx);
2301 // If the index is smaller or larger than intptr_t, truncate or extend
2303 if (IdxN.getValueType() < N.getValueType()) {
2304 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2305 } else if (IdxN.getValueType() > N.getValueType())
2306 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2308 // If this is a multiply by a power of two, turn it into a shl
2309 // immediately. This is a very common case.
2310 if (isPowerOf2_64(ElementSize)) {
2311 unsigned Amt = Log2_64(ElementSize);
2312 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2313 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2314 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2318 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2319 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2320 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2326 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2327 // If this is a fixed sized alloca in the entry block of the function,
2328 // allocate it statically on the stack.
2329 if (FuncInfo.StaticAllocaMap.count(&I))
2330 return; // getValue will auto-populate this.
2332 const Type *Ty = I.getAllocatedType();
2333 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2335 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2338 SDOperand AllocSize = getValue(I.getArraySize());
2339 MVT::ValueType IntPtr = TLI.getPointerTy();
2340 if (IntPtr < AllocSize.getValueType())
2341 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2342 else if (IntPtr > AllocSize.getValueType())
2343 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2345 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2346 DAG.getIntPtrConstant(TySize));
2348 // Handle alignment. If the requested alignment is less than or equal to
2349 // the stack alignment, ignore it. If the size is greater than or equal to
2350 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2351 unsigned StackAlign =
2352 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2353 if (Align <= StackAlign)
2356 // Round the size of the allocation up to the stack alignment size
2357 // by add SA-1 to the size.
2358 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2359 DAG.getIntPtrConstant(StackAlign-1));
2360 // Mask out the low bits for alignment purposes.
2361 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2362 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2364 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2365 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2367 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2369 DAG.setRoot(DSA.getValue(1));
2371 // Inform the Frame Information that we have just allocated a variable-sized
2373 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2376 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2377 SDOperand Ptr = getValue(I.getOperand(0));
2383 // Do not serialize non-volatile loads against each other.
2384 Root = DAG.getRoot();
2387 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2388 Root, I.isVolatile(), I.getAlignment()));
2391 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2392 const Value *SV, SDOperand Root,
2394 unsigned Alignment) {
2396 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2397 isVolatile, Alignment);
2400 DAG.setRoot(L.getValue(1));
2402 PendingLoads.push_back(L.getValue(1));
2408 void SelectionDAGLowering::visitStore(StoreInst &I) {
2409 Value *SrcV = I.getOperand(0);
2410 SDOperand Src = getValue(SrcV);
2411 SDOperand Ptr = getValue(I.getOperand(1));
2412 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2413 I.isVolatile(), I.getAlignment()));
2416 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2418 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2419 unsigned Intrinsic) {
2420 bool HasChain = !I.doesNotAccessMemory();
2421 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2423 // Build the operand list.
2424 SmallVector<SDOperand, 8> Ops;
2425 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2427 // We don't need to serialize loads against other loads.
2428 Ops.push_back(DAG.getRoot());
2430 Ops.push_back(getRoot());
2434 // Add the intrinsic ID as an integer operand.
2435 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2437 // Add all operands of the call to the operand list.
2438 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2439 SDOperand Op = getValue(I.getOperand(i));
2440 assert(TLI.isTypeLegal(Op.getValueType()) &&
2441 "Intrinsic uses a non-legal type?");
2445 std::vector<MVT::ValueType> VTs;
2446 if (I.getType() != Type::VoidTy) {
2447 MVT::ValueType VT = TLI.getValueType(I.getType());
2448 if (MVT::isVector(VT)) {
2449 const VectorType *DestTy = cast<VectorType>(I.getType());
2450 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2452 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2453 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2456 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2460 VTs.push_back(MVT::Other);
2462 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2467 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2468 &Ops[0], Ops.size());
2469 else if (I.getType() != Type::VoidTy)
2470 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2471 &Ops[0], Ops.size());
2473 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2474 &Ops[0], Ops.size());
2477 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2479 PendingLoads.push_back(Chain);
2483 if (I.getType() != Type::VoidTy) {
2484 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2485 MVT::ValueType VT = TLI.getValueType(PTy);
2486 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2488 setValue(&I, Result);
2492 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2493 static GlobalVariable *ExtractTypeInfo (Value *V) {
2494 V = IntrinsicInst::StripPointerCasts(V);
2495 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2496 assert (GV || isa<ConstantPointerNull>(V) &&
2497 "TypeInfo must be a global variable or NULL");
2501 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2502 /// call, and add them to the specified machine basic block.
2503 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2504 MachineBasicBlock *MBB) {
2505 // Inform the MachineModuleInfo of the personality for this landing pad.
2506 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2507 assert(CE->getOpcode() == Instruction::BitCast &&
2508 isa<Function>(CE->getOperand(0)) &&
2509 "Personality should be a function");
2510 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2512 // Gather all the type infos for this landing pad and pass them along to
2513 // MachineModuleInfo.
2514 std::vector<GlobalVariable *> TyInfo;
2515 unsigned N = I.getNumOperands();
2517 for (unsigned i = N - 1; i > 2; --i) {
2518 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2519 unsigned FilterLength = CI->getZExtValue();
2520 unsigned FirstCatch = i + FilterLength + !FilterLength;
2521 assert (FirstCatch <= N && "Invalid filter length");
2523 if (FirstCatch < N) {
2524 TyInfo.reserve(N - FirstCatch);
2525 for (unsigned j = FirstCatch; j < N; ++j)
2526 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2527 MMI->addCatchTypeInfo(MBB, TyInfo);
2531 if (!FilterLength) {
2533 MMI->addCleanup(MBB);
2536 TyInfo.reserve(FilterLength - 1);
2537 for (unsigned j = i + 1; j < FirstCatch; ++j)
2538 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2539 MMI->addFilterTypeInfo(MBB, TyInfo);
2548 TyInfo.reserve(N - 3);
2549 for (unsigned j = 3; j < N; ++j)
2550 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2551 MMI->addCatchTypeInfo(MBB, TyInfo);
2555 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2556 /// we want to emit this as a call to a named external function, return the name
2557 /// otherwise lower it and return null.
2559 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2560 switch (Intrinsic) {
2562 // By default, turn this into a target intrinsic node.
2563 visitTargetIntrinsic(I, Intrinsic);
2565 case Intrinsic::vastart: visitVAStart(I); return 0;
2566 case Intrinsic::vaend: visitVAEnd(I); return 0;
2567 case Intrinsic::vacopy: visitVACopy(I); return 0;
2568 case Intrinsic::returnaddress:
2569 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2570 getValue(I.getOperand(1))));
2572 case Intrinsic::frameaddress:
2573 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2574 getValue(I.getOperand(1))));
2576 case Intrinsic::setjmp:
2577 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2579 case Intrinsic::longjmp:
2580 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2582 case Intrinsic::memcpy_i32:
2583 case Intrinsic::memcpy_i64:
2584 visitMemIntrinsic(I, ISD::MEMCPY);
2586 case Intrinsic::memset_i32:
2587 case Intrinsic::memset_i64:
2588 visitMemIntrinsic(I, ISD::MEMSET);
2590 case Intrinsic::memmove_i32:
2591 case Intrinsic::memmove_i64:
2592 visitMemIntrinsic(I, ISD::MEMMOVE);
2595 case Intrinsic::dbg_stoppoint: {
2596 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2597 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2598 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2602 Ops[1] = getValue(SPI.getLineValue());
2603 Ops[2] = getValue(SPI.getColumnValue());
2605 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2606 assert(DD && "Not a debug information descriptor");
2607 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2609 Ops[3] = DAG.getString(CompileUnit->getFileName());
2610 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2612 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2617 case Intrinsic::dbg_region_start: {
2618 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2619 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2620 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2621 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2622 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2623 DAG.getConstant(LabelID, MVT::i32)));
2628 case Intrinsic::dbg_region_end: {
2629 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2630 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2631 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2632 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2633 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2634 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2639 case Intrinsic::dbg_func_start: {
2640 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2641 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2642 if (MMI && FSI.getSubprogram() &&
2643 MMI->Verify(FSI.getSubprogram())) {
2644 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
2645 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2646 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2651 case Intrinsic::dbg_declare: {
2652 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2653 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2654 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
2655 SDOperand AddressOp = getValue(DI.getAddress());
2656 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2657 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
2663 case Intrinsic::eh_exception: {
2664 if (ExceptionHandling) {
2665 if (!CurMBB->isLandingPad()) {
2666 // FIXME: Mark exception register as live in. Hack for PR1508.
2667 unsigned Reg = TLI.getExceptionAddressRegister();
2668 if (Reg) CurMBB->addLiveIn(Reg);
2670 // Insert the EXCEPTIONADDR instruction.
2671 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2673 Ops[0] = DAG.getRoot();
2674 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2676 DAG.setRoot(Op.getValue(1));
2678 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2683 case Intrinsic::eh_selector_i32:
2684 case Intrinsic::eh_selector_i64: {
2685 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2686 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2687 MVT::i32 : MVT::i64);
2689 if (ExceptionHandling && MMI) {
2690 if (CurMBB->isLandingPad())
2691 addCatchInfo(I, MMI, CurMBB);
2694 FuncInfo.CatchInfoLost.insert(&I);
2696 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2697 unsigned Reg = TLI.getExceptionSelectorRegister();
2698 if (Reg) CurMBB->addLiveIn(Reg);
2701 // Insert the EHSELECTION instruction.
2702 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2704 Ops[0] = getValue(I.getOperand(1));
2706 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2708 DAG.setRoot(Op.getValue(1));
2710 setValue(&I, DAG.getConstant(0, VT));
2716 case Intrinsic::eh_typeid_for_i32:
2717 case Intrinsic::eh_typeid_for_i64: {
2718 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2719 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2720 MVT::i32 : MVT::i64);
2723 // Find the type id for the given typeinfo.
2724 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2726 unsigned TypeID = MMI->getTypeIDFor(GV);
2727 setValue(&I, DAG.getConstant(TypeID, VT));
2729 // Return something different to eh_selector.
2730 setValue(&I, DAG.getConstant(1, VT));
2736 case Intrinsic::eh_return: {
2737 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2739 if (MMI && ExceptionHandling) {
2740 MMI->setCallsEHReturn(true);
2741 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2744 getValue(I.getOperand(1)),
2745 getValue(I.getOperand(2))));
2747 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2753 case Intrinsic::eh_unwind_init: {
2754 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2755 MMI->setCallsUnwindInit(true);
2761 case Intrinsic::eh_dwarf_cfa: {
2762 if (ExceptionHandling) {
2763 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2765 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2766 CfaArg = DAG.getNode(ISD::TRUNCATE,
2767 TLI.getPointerTy(), getValue(I.getOperand(1)));
2769 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2770 TLI.getPointerTy(), getValue(I.getOperand(1)));
2772 SDOperand Offset = DAG.getNode(ISD::ADD,
2774 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2775 TLI.getPointerTy()),
2777 setValue(&I, DAG.getNode(ISD::ADD,
2779 DAG.getNode(ISD::FRAMEADDR,
2782 TLI.getPointerTy())),
2785 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2791 case Intrinsic::sqrt:
2792 setValue(&I, DAG.getNode(ISD::FSQRT,
2793 getValue(I.getOperand(1)).getValueType(),
2794 getValue(I.getOperand(1))));
2796 case Intrinsic::powi:
2797 setValue(&I, DAG.getNode(ISD::FPOWI,
2798 getValue(I.getOperand(1)).getValueType(),
2799 getValue(I.getOperand(1)),
2800 getValue(I.getOperand(2))));
2802 case Intrinsic::sin:
2803 setValue(&I, DAG.getNode(ISD::FSIN,
2804 getValue(I.getOperand(1)).getValueType(),
2805 getValue(I.getOperand(1))));
2807 case Intrinsic::cos:
2808 setValue(&I, DAG.getNode(ISD::FCOS,
2809 getValue(I.getOperand(1)).getValueType(),
2810 getValue(I.getOperand(1))));
2812 case Intrinsic::pow:
2813 setValue(&I, DAG.getNode(ISD::FPOW,
2814 getValue(I.getOperand(1)).getValueType(),
2815 getValue(I.getOperand(1)),
2816 getValue(I.getOperand(2))));
2818 case Intrinsic::pcmarker: {
2819 SDOperand Tmp = getValue(I.getOperand(1));
2820 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2823 case Intrinsic::readcyclecounter: {
2824 SDOperand Op = getRoot();
2825 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2826 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2829 DAG.setRoot(Tmp.getValue(1));
2832 case Intrinsic::part_select: {
2833 // Currently not implemented: just abort
2834 assert(0 && "part_select intrinsic not implemented");
2837 case Intrinsic::part_set: {
2838 // Currently not implemented: just abort
2839 assert(0 && "part_set intrinsic not implemented");
2842 case Intrinsic::bswap:
2843 setValue(&I, DAG.getNode(ISD::BSWAP,
2844 getValue(I.getOperand(1)).getValueType(),
2845 getValue(I.getOperand(1))));
2847 case Intrinsic::cttz: {
2848 SDOperand Arg = getValue(I.getOperand(1));
2849 MVT::ValueType Ty = Arg.getValueType();
2850 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2851 setValue(&I, result);
2854 case Intrinsic::ctlz: {
2855 SDOperand Arg = getValue(I.getOperand(1));
2856 MVT::ValueType Ty = Arg.getValueType();
2857 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2858 setValue(&I, result);
2861 case Intrinsic::ctpop: {
2862 SDOperand Arg = getValue(I.getOperand(1));
2863 MVT::ValueType Ty = Arg.getValueType();
2864 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2865 setValue(&I, result);
2868 case Intrinsic::stacksave: {
2869 SDOperand Op = getRoot();
2870 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2871 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2873 DAG.setRoot(Tmp.getValue(1));
2876 case Intrinsic::stackrestore: {
2877 SDOperand Tmp = getValue(I.getOperand(1));
2878 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2881 case Intrinsic::prefetch:
2882 // FIXME: Currently discarding prefetches.
2885 case Intrinsic::var_annotation:
2886 // Discard annotate attributes
2889 case Intrinsic::init_trampoline: {
2891 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
2895 Ops[1] = getValue(I.getOperand(1));
2896 Ops[2] = getValue(I.getOperand(2));
2897 Ops[3] = getValue(I.getOperand(3));
2898 Ops[4] = DAG.getSrcValue(I.getOperand(1));
2899 Ops[5] = DAG.getSrcValue(F);
2901 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
2902 DAG.getNodeValueTypes(TLI.getPointerTy(),
2907 DAG.setRoot(Tmp.getValue(1));
2911 case Intrinsic::gcroot:
2913 Value *Alloca = I.getOperand(1);
2914 Constant *TypeMap = cast<Constant>(I.getOperand(2));
2916 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
2917 GCI->addStackRoot(FI->getIndex(), TypeMap);
2921 case Intrinsic::gcread:
2922 case Intrinsic::gcwrite:
2923 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
2926 case Intrinsic::flt_rounds: {
2927 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32));
2931 case Intrinsic::trap: {
2932 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
2939 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
2941 MachineBasicBlock *LandingPad) {
2942 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2943 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2944 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2945 unsigned BeginLabel = 0, EndLabel = 0;
2947 TargetLowering::ArgListTy Args;
2948 TargetLowering::ArgListEntry Entry;
2949 Args.reserve(CS.arg_size());
2950 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2952 SDOperand ArgNode = getValue(*i);
2953 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
2955 unsigned attrInd = i - CS.arg_begin() + 1;
2956 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
2957 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
2958 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
2959 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
2960 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
2961 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
2962 Args.push_back(Entry);
2965 bool MarkTryRange = LandingPad ||
2966 // C++ requires special handling of 'nounwind' calls.
2967 (CS.doesNotThrow());
2969 if (MarkTryRange && ExceptionHandling && MMI) {
2970 // Insert a label before the invoke call to mark the try range. This can be
2971 // used to detect deletion of the invoke via the MachineModuleInfo.
2972 BeginLabel = MMI->NextLabelID();
2973 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2974 DAG.getConstant(BeginLabel, MVT::i32)));
2977 std::pair<SDOperand,SDOperand> Result =
2978 TLI.LowerCallTo(getRoot(), CS.getType(),
2979 CS.paramHasAttr(0, ParamAttr::SExt),
2980 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
2982 if (CS.getType() != Type::VoidTy)
2983 setValue(CS.getInstruction(), Result.first);
2984 DAG.setRoot(Result.second);
2986 if (MarkTryRange && ExceptionHandling && MMI) {
2987 // Insert a label at the end of the invoke call to mark the try range. This
2988 // can be used to detect deletion of the invoke via the MachineModuleInfo.
2989 EndLabel = MMI->NextLabelID();
2990 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2991 DAG.getConstant(EndLabel, MVT::i32)));
2993 // Inform MachineModuleInfo of range.
2994 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
2999 void SelectionDAGLowering::visitCall(CallInst &I) {
3000 const char *RenameFn = 0;
3001 if (Function *F = I.getCalledFunction()) {
3002 if (F->isDeclaration()) {
3003 if (unsigned IID = F->getIntrinsicID()) {
3004 RenameFn = visitIntrinsicCall(I, IID);
3010 // Check for well-known libc/libm calls. If the function is internal, it
3011 // can't be a library call.
3012 unsigned NameLen = F->getNameLen();
3013 if (!F->hasInternalLinkage() && NameLen) {
3014 const char *NameStr = F->getNameStart();
3015 if (NameStr[0] == 'c' &&
3016 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3017 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3018 if (I.getNumOperands() == 3 && // Basic sanity checks.
3019 I.getOperand(1)->getType()->isFloatingPoint() &&
3020 I.getType() == I.getOperand(1)->getType() &&
3021 I.getType() == I.getOperand(2)->getType()) {
3022 SDOperand LHS = getValue(I.getOperand(1));
3023 SDOperand RHS = getValue(I.getOperand(2));
3024 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3028 } else if (NameStr[0] == 'f' &&
3029 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3030 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3031 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3032 if (I.getNumOperands() == 2 && // Basic sanity checks.
3033 I.getOperand(1)->getType()->isFloatingPoint() &&
3034 I.getType() == I.getOperand(1)->getType()) {
3035 SDOperand Tmp = getValue(I.getOperand(1));
3036 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3039 } else if (NameStr[0] == 's' &&
3040 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3041 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3042 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3043 if (I.getNumOperands() == 2 && // Basic sanity checks.
3044 I.getOperand(1)->getType()->isFloatingPoint() &&
3045 I.getType() == I.getOperand(1)->getType()) {
3046 SDOperand Tmp = getValue(I.getOperand(1));
3047 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3050 } else if (NameStr[0] == 'c' &&
3051 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3052 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3053 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3054 if (I.getNumOperands() == 2 && // Basic sanity checks.
3055 I.getOperand(1)->getType()->isFloatingPoint() &&
3056 I.getType() == I.getOperand(1)->getType()) {
3057 SDOperand Tmp = getValue(I.getOperand(1));
3058 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3063 } else if (isa<InlineAsm>(I.getOperand(0))) {
3070 Callee = getValue(I.getOperand(0));
3072 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3074 LowerCallTo(&I, Callee, I.isTailCall());
3078 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3079 /// this value and returns the result as a ValueVT value. This uses
3080 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3081 /// If the Flag pointer is NULL, no flag is used.
3082 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3083 SDOperand &Chain, SDOperand *Flag)const{
3084 // Copy the legal parts from the registers.
3085 unsigned NumParts = Regs.size();
3086 SmallVector<SDOperand, 8> Parts(NumParts);
3087 for (unsigned i = 0; i != NumParts; ++i) {
3088 SDOperand Part = Flag ?
3089 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3090 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3091 Chain = Part.getValue(1);
3093 *Flag = Part.getValue(2);
3097 // Assemble the legal parts into the final value.
3098 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3101 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3102 /// specified value into the registers specified by this object. This uses
3103 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3104 /// If the Flag pointer is NULL, no flag is used.
3105 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3106 SDOperand &Chain, SDOperand *Flag) const {
3107 // Get the list of the values's legal parts.
3108 unsigned NumParts = Regs.size();
3109 SmallVector<SDOperand, 8> Parts(NumParts);
3110 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3112 // Copy the parts into the registers.
3113 for (unsigned i = 0; i != NumParts; ++i) {
3114 SDOperand Part = Flag ?
3115 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3116 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3117 Chain = Part.getValue(0);
3119 *Flag = Part.getValue(1);
3123 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3124 /// operand list. This adds the code marker and includes the number of
3125 /// values added into it.
3126 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3127 std::vector<SDOperand> &Ops) const {
3128 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3129 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3130 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3131 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3134 /// isAllocatableRegister - If the specified register is safe to allocate,
3135 /// i.e. it isn't a stack pointer or some other special register, return the
3136 /// register class for the register. Otherwise, return null.
3137 static const TargetRegisterClass *
3138 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3139 const TargetLowering &TLI, const MRegisterInfo *MRI) {
3140 MVT::ValueType FoundVT = MVT::Other;
3141 const TargetRegisterClass *FoundRC = 0;
3142 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
3143 E = MRI->regclass_end(); RCI != E; ++RCI) {
3144 MVT::ValueType ThisVT = MVT::Other;
3146 const TargetRegisterClass *RC = *RCI;
3147 // If none of the the value types for this register class are valid, we
3148 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3149 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3151 if (TLI.isTypeLegal(*I)) {
3152 // If we have already found this register in a different register class,
3153 // choose the one with the largest VT specified. For example, on
3154 // PowerPC, we favor f64 register classes over f32.
3155 if (FoundVT == MVT::Other ||
3156 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3163 if (ThisVT == MVT::Other) continue;
3165 // NOTE: This isn't ideal. In particular, this might allocate the
3166 // frame pointer in functions that need it (due to them not being taken
3167 // out of allocation, because a variable sized allocation hasn't been seen
3168 // yet). This is a slight code pessimization, but should still work.
3169 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3170 E = RC->allocation_order_end(MF); I != E; ++I)
3172 // We found a matching register class. Keep looking at others in case
3173 // we find one with larger registers that this physreg is also in.
3184 /// AsmOperandInfo - This contains information for each constraint that we are
3186 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3187 /// ConstraintCode - This contains the actual string for the code, like "m".
3188 std::string ConstraintCode;
3190 /// ConstraintType - Information about the constraint code, e.g. Register,
3191 /// RegisterClass, Memory, Other, Unknown.
3192 TargetLowering::ConstraintType ConstraintType;
3194 /// CallOperand/CallOperandval - If this is the result output operand or a
3195 /// clobber, this is null, otherwise it is the incoming operand to the
3196 /// CallInst. This gets modified as the asm is processed.
3197 SDOperand CallOperand;
3198 Value *CallOperandVal;
3200 /// ConstraintVT - The ValueType for the operand value.
3201 MVT::ValueType ConstraintVT;
3203 /// AssignedRegs - If this is a register or register class operand, this
3204 /// contains the set of register corresponding to the operand.
3205 RegsForValue AssignedRegs;
3207 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3208 : InlineAsm::ConstraintInfo(info),
3209 ConstraintType(TargetLowering::C_Unknown),
3210 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3213 void ComputeConstraintToUse(const TargetLowering &TLI);
3215 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3216 /// busy in OutputRegs/InputRegs.
3217 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3218 std::set<unsigned> &OutputRegs,
3219 std::set<unsigned> &InputRegs) const {
3221 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3223 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3226 } // end anon namespace.
3228 /// getConstraintGenerality - Return an integer indicating how general CT is.
3229 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3231 default: assert(0 && "Unknown constraint type!");
3232 case TargetLowering::C_Other:
3233 case TargetLowering::C_Unknown:
3235 case TargetLowering::C_Register:
3237 case TargetLowering::C_RegisterClass:
3239 case TargetLowering::C_Memory:
3244 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3245 assert(!Codes.empty() && "Must have at least one constraint");
3247 std::string *Current = &Codes[0];
3248 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3249 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3250 ConstraintCode = *Current;
3251 ConstraintType = CurType;
3255 unsigned CurGenerality = getConstraintGenerality(CurType);
3257 // If we have multiple constraints, try to pick the most general one ahead
3258 // of time. This isn't a wonderful solution, but handles common cases.
3259 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3260 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3261 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3262 if (ThisGenerality > CurGenerality) {
3263 // This constraint letter is more general than the previous one,
3266 Current = &Codes[j];
3267 CurGenerality = ThisGenerality;
3271 ConstraintCode = *Current;
3272 ConstraintType = CurType;
3276 void SelectionDAGLowering::
3277 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3278 std::set<unsigned> &OutputRegs,
3279 std::set<unsigned> &InputRegs) {
3280 // Compute whether this value requires an input register, an output register,
3282 bool isOutReg = false;
3283 bool isInReg = false;
3284 switch (OpInfo.Type) {
3285 case InlineAsm::isOutput:
3288 // If this is an early-clobber output, or if there is an input
3289 // constraint that matches this, we need to reserve the input register
3290 // so no other inputs allocate to it.
3291 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3293 case InlineAsm::isInput:
3297 case InlineAsm::isClobber:
3304 MachineFunction &MF = DAG.getMachineFunction();
3305 std::vector<unsigned> Regs;
3307 // If this is a constraint for a single physreg, or a constraint for a
3308 // register class, find it.
3309 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3310 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3311 OpInfo.ConstraintVT);
3313 unsigned NumRegs = 1;
3314 if (OpInfo.ConstraintVT != MVT::Other)
3315 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3316 MVT::ValueType RegVT;
3317 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3320 // If this is a constraint for a specific physical register, like {r17},
3322 if (PhysReg.first) {
3323 if (OpInfo.ConstraintVT == MVT::Other)
3324 ValueVT = *PhysReg.second->vt_begin();
3326 // Get the actual register value type. This is important, because the user
3327 // may have asked for (e.g.) the AX register in i32 type. We need to
3328 // remember that AX is actually i16 to get the right extension.
3329 RegVT = *PhysReg.second->vt_begin();
3331 // This is a explicit reference to a physical register.
3332 Regs.push_back(PhysReg.first);
3334 // If this is an expanded reference, add the rest of the regs to Regs.
3336 TargetRegisterClass::iterator I = PhysReg.second->begin();
3337 TargetRegisterClass::iterator E = PhysReg.second->end();
3338 for (; *I != PhysReg.first; ++I)
3339 assert(I != E && "Didn't find reg!");
3341 // Already added the first reg.
3343 for (; NumRegs; --NumRegs, ++I) {
3344 assert(I != E && "Ran out of registers to allocate!");
3348 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3349 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3353 // Otherwise, if this was a reference to an LLVM register class, create vregs
3354 // for this reference.
3355 std::vector<unsigned> RegClassRegs;
3356 const TargetRegisterClass *RC = PhysReg.second;
3358 // If this is an early clobber or tied register, our regalloc doesn't know
3359 // how to maintain the constraint. If it isn't, go ahead and create vreg
3360 // and let the regalloc do the right thing.
3361 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3362 // If there is some other early clobber and this is an input register,
3363 // then we are forced to pre-allocate the input reg so it doesn't
3364 // conflict with the earlyclobber.
3365 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3366 RegVT = *PhysReg.second->vt_begin();
3368 if (OpInfo.ConstraintVT == MVT::Other)
3371 // Create the appropriate number of virtual registers.
3372 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3373 for (; NumRegs; --NumRegs)
3374 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3376 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3377 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3381 // Otherwise, we can't allocate it. Let the code below figure out how to
3382 // maintain these constraints.
3383 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3386 // This is a reference to a register class that doesn't directly correspond
3387 // to an LLVM register class. Allocate NumRegs consecutive, available,
3388 // registers from the class.
3389 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3390 OpInfo.ConstraintVT);
3393 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3394 unsigned NumAllocated = 0;
3395 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3396 unsigned Reg = RegClassRegs[i];
3397 // See if this register is available.
3398 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3399 (isInReg && InputRegs.count(Reg))) { // Already used.
3400 // Make sure we find consecutive registers.
3405 // Check to see if this register is allocatable (i.e. don't give out the
3408 RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3409 if (!RC) { // Couldn't allocate this register.
3410 // Reset NumAllocated to make sure we return consecutive registers.
3416 // Okay, this register is good, we can use it.
3419 // If we allocated enough consecutive registers, succeed.
3420 if (NumAllocated == NumRegs) {
3421 unsigned RegStart = (i-NumAllocated)+1;
3422 unsigned RegEnd = i+1;
3423 // Mark all of the allocated registers used.
3424 for (unsigned i = RegStart; i != RegEnd; ++i)
3425 Regs.push_back(RegClassRegs[i]);
3427 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3428 OpInfo.ConstraintVT);
3429 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3434 // Otherwise, we couldn't allocate enough registers for this.
3439 /// visitInlineAsm - Handle a call to an InlineAsm object.
3441 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3442 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3444 /// ConstraintOperands - Information about all of the constraints.
3445 std::vector<AsmOperandInfo> ConstraintOperands;
3447 SDOperand Chain = getRoot();
3450 std::set<unsigned> OutputRegs, InputRegs;
3452 // Do a prepass over the constraints, canonicalizing them, and building up the
3453 // ConstraintOperands list.
3454 std::vector<InlineAsm::ConstraintInfo>
3455 ConstraintInfos = IA->ParseConstraints();
3457 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3458 // constraint. If so, we can't let the register allocator allocate any input
3459 // registers, because it will not know to avoid the earlyclobbered output reg.
3460 bool SawEarlyClobber = false;
3462 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3463 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3464 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3465 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3467 MVT::ValueType OpVT = MVT::Other;
3469 // Compute the value type for each operand.
3470 switch (OpInfo.Type) {
3471 case InlineAsm::isOutput:
3472 if (!OpInfo.isIndirect) {
3473 // The return value of the call is this value. As such, there is no
3474 // corresponding argument.
3475 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3476 OpVT = TLI.getValueType(CS.getType());
3478 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3481 case InlineAsm::isInput:
3482 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3484 case InlineAsm::isClobber:
3489 // If this is an input or an indirect output, process the call argument.
3490 // BasicBlocks are labels, currently appearing only in asm's.
3491 if (OpInfo.CallOperandVal) {
3492 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3493 OpInfo.CallOperand =
3494 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(OpInfo.CallOperandVal)]);
3496 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3497 const Type *OpTy = OpInfo.CallOperandVal->getType();
3498 // If this is an indirect operand, the operand is a pointer to the
3500 if (OpInfo.isIndirect)
3501 OpTy = cast<PointerType>(OpTy)->getElementType();
3503 // If OpTy is not a first-class value, it may be a struct/union that we
3504 // can tile with integers.
3505 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3506 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3514 OpTy = IntegerType::get(BitSize);
3519 OpVT = TLI.getValueType(OpTy, true);
3523 OpInfo.ConstraintVT = OpVT;
3525 // Compute the constraint code and ConstraintType to use.
3526 OpInfo.ComputeConstraintToUse(TLI);
3528 // Keep track of whether we see an earlyclobber.
3529 SawEarlyClobber |= OpInfo.isEarlyClobber;
3531 // If this is a memory input, and if the operand is not indirect, do what we
3532 // need to to provide an address for the memory input.
3533 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3534 !OpInfo.isIndirect) {
3535 assert(OpInfo.Type == InlineAsm::isInput &&
3536 "Can only indirectify direct input operands!");
3538 // Memory operands really want the address of the value. If we don't have
3539 // an indirect input, put it in the constpool if we can, otherwise spill
3540 // it to a stack slot.
3542 // If the operand is a float, integer, or vector constant, spill to a
3543 // constant pool entry to get its address.
3544 Value *OpVal = OpInfo.CallOperandVal;
3545 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3546 isa<ConstantVector>(OpVal)) {
3547 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3548 TLI.getPointerTy());
3550 // Otherwise, create a stack slot and emit a store to it before the
3552 const Type *Ty = OpVal->getType();
3553 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3554 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3555 MachineFunction &MF = DAG.getMachineFunction();
3556 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3557 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3558 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3559 OpInfo.CallOperand = StackSlot;
3562 // There is no longer a Value* corresponding to this operand.
3563 OpInfo.CallOperandVal = 0;
3564 // It is now an indirect operand.
3565 OpInfo.isIndirect = true;
3568 // If this constraint is for a specific register, allocate it before
3570 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3571 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3573 ConstraintInfos.clear();
3576 // Second pass - Loop over all of the operands, assigning virtual or physregs
3577 // to registerclass operands.
3578 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3579 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3581 // C_Register operands have already been allocated, Other/Memory don't need
3583 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3584 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3587 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3588 std::vector<SDOperand> AsmNodeOperands;
3589 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3590 AsmNodeOperands.push_back(
3591 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3594 // Loop over all of the inputs, copying the operand values into the
3595 // appropriate registers and processing the output regs.
3596 RegsForValue RetValRegs;
3598 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3599 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3601 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3602 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3604 switch (OpInfo.Type) {
3605 case InlineAsm::isOutput: {
3606 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3607 OpInfo.ConstraintType != TargetLowering::C_Register) {
3608 // Memory output, or 'other' output (e.g. 'X' constraint).
3609 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3611 // Add information to the INLINEASM node to know about this output.
3612 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3613 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3614 TLI.getPointerTy()));
3615 AsmNodeOperands.push_back(OpInfo.CallOperand);
3619 // Otherwise, this is a register or register class output.
3621 // Copy the output from the appropriate register. Find a register that
3623 if (OpInfo.AssignedRegs.Regs.empty()) {
3624 cerr << "Couldn't allocate output reg for contraint '"
3625 << OpInfo.ConstraintCode << "'!\n";
3629 if (!OpInfo.isIndirect) {
3630 // This is the result value of the call.
3631 assert(RetValRegs.Regs.empty() &&
3632 "Cannot have multiple output constraints yet!");
3633 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3634 RetValRegs = OpInfo.AssignedRegs;
3636 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3637 OpInfo.CallOperandVal));
3640 // Add information to the INLINEASM node to know that this register is
3642 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3646 case InlineAsm::isInput: {
3647 SDOperand InOperandVal = OpInfo.CallOperand;
3649 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3650 // If this is required to match an output register we have already set,
3651 // just use its register.
3652 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3654 // Scan until we find the definition we already emitted of this operand.
3655 // When we find it, create a RegsForValue operand.
3656 unsigned CurOp = 2; // The first operand.
3657 for (; OperandNo; --OperandNo) {
3658 // Advance to the next operand.
3660 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3661 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3662 (NumOps & 7) == 4 /*MEM*/) &&
3663 "Skipped past definitions?");
3664 CurOp += (NumOps>>3)+1;
3668 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3669 if ((NumOps & 7) == 2 /*REGDEF*/) {
3670 // Add NumOps>>3 registers to MatchedRegs.
3671 RegsForValue MatchedRegs;
3672 MatchedRegs.ValueVT = InOperandVal.getValueType();
3673 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3674 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3676 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3677 MatchedRegs.Regs.push_back(Reg);
3680 // Use the produced MatchedRegs object to
3681 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3682 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3685 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3686 assert(0 && "matching constraints for memory operands unimp");
3690 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3691 assert(!OpInfo.isIndirect &&
3692 "Don't know how to handle indirect other inputs yet!");
3694 std::vector<SDOperand> Ops;
3695 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3698 cerr << "Invalid operand for inline asm constraint '"
3699 << OpInfo.ConstraintCode << "'!\n";
3703 // Add information to the INLINEASM node to know about this input.
3704 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3705 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3706 TLI.getPointerTy()));
3707 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3709 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3710 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3711 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3712 "Memory operands expect pointer values");
3714 // Add information to the INLINEASM node to know about this input.
3715 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3716 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3717 TLI.getPointerTy()));
3718 AsmNodeOperands.push_back(InOperandVal);
3722 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3723 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3724 "Unknown constraint type!");
3725 assert(!OpInfo.isIndirect &&
3726 "Don't know how to handle indirect register inputs yet!");
3728 // Copy the input into the appropriate registers.
3729 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3730 "Couldn't allocate input reg!");
3732 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3734 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3738 case InlineAsm::isClobber: {
3739 // Add the clobbered value to the operand list, so that the register
3740 // allocator is aware that the physreg got clobbered.
3741 if (!OpInfo.AssignedRegs.Regs.empty())
3742 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3749 // Finish up input operands.
3750 AsmNodeOperands[0] = Chain;
3751 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3753 Chain = DAG.getNode(ISD::INLINEASM,
3754 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3755 &AsmNodeOperands[0], AsmNodeOperands.size());
3756 Flag = Chain.getValue(1);
3758 // If this asm returns a register value, copy the result from that register
3759 // and set it as the value of the call.
3760 if (!RetValRegs.Regs.empty()) {
3761 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3763 // If the result of the inline asm is a vector, it may have the wrong
3764 // width/num elts. Make sure to convert it to the right type with
3766 if (MVT::isVector(Val.getValueType())) {
3767 const VectorType *VTy = cast<VectorType>(CS.getType());
3768 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3770 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3773 setValue(CS.getInstruction(), Val);
3776 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3778 // Process indirect outputs, first output all of the flagged copies out of
3780 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3781 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3782 Value *Ptr = IndirectStoresToEmit[i].second;
3783 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3784 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3787 // Emit the non-flagged stores from the physregs.
3788 SmallVector<SDOperand, 8> OutChains;
3789 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3790 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3791 getValue(StoresToEmit[i].second),
3792 StoresToEmit[i].second, 0));
3793 if (!OutChains.empty())
3794 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3795 &OutChains[0], OutChains.size());
3800 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3801 SDOperand Src = getValue(I.getOperand(0));
3803 MVT::ValueType IntPtr = TLI.getPointerTy();
3805 if (IntPtr < Src.getValueType())
3806 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3807 else if (IntPtr > Src.getValueType())
3808 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3810 // Scale the source by the type size.
3811 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
3812 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3813 Src, DAG.getIntPtrConstant(ElementSize));
3815 TargetLowering::ArgListTy Args;
3816 TargetLowering::ArgListEntry Entry;
3818 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3819 Args.push_back(Entry);
3821 std::pair<SDOperand,SDOperand> Result =
3822 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
3823 DAG.getExternalSymbol("malloc", IntPtr),
3825 setValue(&I, Result.first); // Pointers always fit in registers
3826 DAG.setRoot(Result.second);
3829 void SelectionDAGLowering::visitFree(FreeInst &I) {
3830 TargetLowering::ArgListTy Args;
3831 TargetLowering::ArgListEntry Entry;
3832 Entry.Node = getValue(I.getOperand(0));
3833 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3834 Args.push_back(Entry);
3835 MVT::ValueType IntPtr = TLI.getPointerTy();
3836 std::pair<SDOperand,SDOperand> Result =
3837 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
3838 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3839 DAG.setRoot(Result.second);
3842 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
3843 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3844 // instructions are special in various ways, which require special support to
3845 // insert. The specified MachineInstr is created but not inserted into any
3846 // basic blocks, and the scheduler passes ownership of it to this method.
3847 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
3848 MachineBasicBlock *MBB) {
3849 cerr << "If a target marks an instruction with "
3850 << "'usesCustomDAGSchedInserter', it must implement "
3851 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
3856 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3857 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3858 getValue(I.getOperand(1)),
3859 DAG.getSrcValue(I.getOperand(1))));
3862 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3863 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3864 getValue(I.getOperand(0)),
3865 DAG.getSrcValue(I.getOperand(0)));
3867 DAG.setRoot(V.getValue(1));
3870 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3871 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3872 getValue(I.getOperand(1)),
3873 DAG.getSrcValue(I.getOperand(1))));
3876 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3877 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3878 getValue(I.getOperand(1)),
3879 getValue(I.getOperand(2)),
3880 DAG.getSrcValue(I.getOperand(1)),
3881 DAG.getSrcValue(I.getOperand(2))));
3884 /// TargetLowering::LowerArguments - This is the default LowerArguments
3885 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3886 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3887 /// integrated into SDISel.
3888 std::vector<SDOperand>
3889 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3890 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3891 std::vector<SDOperand> Ops;
3892 Ops.push_back(DAG.getRoot());
3893 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3894 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3896 // Add one result value for each formal argument.
3897 std::vector<MVT::ValueType> RetVals;
3899 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3901 MVT::ValueType VT = getValueType(I->getType());
3902 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3903 unsigned OriginalAlignment =
3904 getTargetData()->getABITypeAlignment(I->getType());
3906 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3907 // that is zero extended!
3908 if (F.paramHasAttr(j, ParamAttr::ZExt))
3909 Flags &= ~(ISD::ParamFlags::SExt);
3910 if (F.paramHasAttr(j, ParamAttr::SExt))
3911 Flags |= ISD::ParamFlags::SExt;
3912 if (F.paramHasAttr(j, ParamAttr::InReg))
3913 Flags |= ISD::ParamFlags::InReg;
3914 if (F.paramHasAttr(j, ParamAttr::StructRet))
3915 Flags |= ISD::ParamFlags::StructReturn;
3916 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
3917 Flags |= ISD::ParamFlags::ByVal;
3918 const PointerType *Ty = cast<PointerType>(I->getType());
3919 const Type *ElementTy = Ty->getElementType();
3920 unsigned FrameAlign =
3921 Log2_32(getTargetData()->getCallFrameTypeAlignment(ElementTy));
3922 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
3923 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
3924 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
3926 if (F.paramHasAttr(j, ParamAttr::Nest))
3927 Flags |= ISD::ParamFlags::Nest;
3928 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
3930 switch (getTypeAction(VT)) {
3931 default: assert(0 && "Unknown type action!");
3933 RetVals.push_back(VT);
3934 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3937 RetVals.push_back(getTypeToTransformTo(VT));
3938 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3941 // If this is an illegal type, it needs to be broken up to fit into
3943 MVT::ValueType RegisterVT = getRegisterType(VT);
3944 unsigned NumRegs = getNumRegisters(VT);
3945 for (unsigned i = 0; i != NumRegs; ++i) {
3946 RetVals.push_back(RegisterVT);
3947 // if it isn't first piece, alignment must be 1
3949 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3950 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3951 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3958 RetVals.push_back(MVT::Other);
3961 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3962 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3963 &Ops[0], Ops.size()).Val;
3964 unsigned NumArgRegs = Result->getNumValues() - 1;
3965 DAG.setRoot(SDOperand(Result, NumArgRegs));
3967 // Set up the return result vector.
3971 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3973 MVT::ValueType VT = getValueType(I->getType());
3975 switch (getTypeAction(VT)) {
3976 default: assert(0 && "Unknown type action!");
3978 Ops.push_back(SDOperand(Result, i++));
3981 SDOperand Op(Result, i++);
3982 if (MVT::isInteger(VT)) {
3983 if (F.paramHasAttr(Idx, ParamAttr::SExt))
3984 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
3985 DAG.getValueType(VT));
3986 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
3987 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
3988 DAG.getValueType(VT));
3989 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
3991 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3992 Op = DAG.getNode(ISD::FP_ROUND, VT, Op, DAG.getIntPtrConstant(1));
3998 MVT::ValueType PartVT = getRegisterType(VT);
3999 unsigned NumParts = getNumRegisters(VT);
4000 SmallVector<SDOperand, 4> Parts(NumParts);
4001 for (unsigned j = 0; j != NumParts; ++j)
4002 Parts[j] = SDOperand(Result, i++);
4003 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
4008 assert(i == NumArgRegs && "Argument register count mismatch!");
4013 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4014 /// implementation, which just inserts an ISD::CALL node, which is later custom
4015 /// lowered by the target to something concrete. FIXME: When all targets are
4016 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4017 std::pair<SDOperand, SDOperand>
4018 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4019 bool RetTyIsSigned, bool isVarArg,
4020 unsigned CallingConv, bool isTailCall,
4022 ArgListTy &Args, SelectionDAG &DAG) {
4023 SmallVector<SDOperand, 32> Ops;
4024 Ops.push_back(Chain); // Op#0 - Chain
4025 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4026 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4027 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4028 Ops.push_back(Callee);
4030 // Handle all of the outgoing arguments.
4031 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4032 MVT::ValueType VT = getValueType(Args[i].Ty);
4033 SDOperand Op = Args[i].Node;
4034 unsigned Flags = ISD::ParamFlags::NoFlagSet;
4035 unsigned OriginalAlignment =
4036 getTargetData()->getABITypeAlignment(Args[i].Ty);
4039 Flags |= ISD::ParamFlags::SExt;
4041 Flags |= ISD::ParamFlags::ZExt;
4042 if (Args[i].isInReg)
4043 Flags |= ISD::ParamFlags::InReg;
4045 Flags |= ISD::ParamFlags::StructReturn;
4046 if (Args[i].isByVal) {
4047 Flags |= ISD::ParamFlags::ByVal;
4048 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4049 const Type *ElementTy = Ty->getElementType();
4050 unsigned FrameAlign =
4051 Log2_32(getTargetData()->getCallFrameTypeAlignment(ElementTy));
4052 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4053 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
4054 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
4057 Flags |= ISD::ParamFlags::Nest;
4058 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
4060 switch (getTypeAction(VT)) {
4061 default: assert(0 && "Unknown type action!");
4064 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4067 if (MVT::isInteger(VT)) {
4070 ExtOp = ISD::SIGN_EXTEND;
4071 else if (Args[i].isZExt)
4072 ExtOp = ISD::ZERO_EXTEND;
4074 ExtOp = ISD::ANY_EXTEND;
4075 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
4077 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
4078 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
4081 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4084 MVT::ValueType PartVT = getRegisterType(VT);
4085 unsigned NumParts = getNumRegisters(VT);
4086 SmallVector<SDOperand, 4> Parts(NumParts);
4087 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
4088 for (unsigned i = 0; i != NumParts; ++i) {
4089 // if it isn't first piece, alignment must be 1
4090 unsigned MyFlags = Flags;
4092 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4093 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4095 Ops.push_back(Parts[i]);
4096 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
4103 // Figure out the result value types.
4104 MVT::ValueType VT = getValueType(RetTy);
4105 MVT::ValueType RegisterVT = getRegisterType(VT);
4106 unsigned NumRegs = getNumRegisters(VT);
4107 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4108 for (unsigned i = 0; i != NumRegs; ++i)
4109 RetTys[i] = RegisterVT;
4111 RetTys.push_back(MVT::Other); // Always has a chain.
4113 // Create the CALL node.
4114 SDOperand Res = DAG.getNode(ISD::CALL,
4115 DAG.getVTList(&RetTys[0], NumRegs + 1),
4116 &Ops[0], Ops.size());
4117 Chain = Res.getValue(NumRegs);
4119 // Gather up the call result into a single value.
4120 if (RetTy != Type::VoidTy) {
4121 ISD::NodeType AssertOp = ISD::AssertSext;
4123 AssertOp = ISD::AssertZext;
4124 SmallVector<SDOperand, 4> Results(NumRegs);
4125 for (unsigned i = 0; i != NumRegs; ++i)
4126 Results[i] = Res.getValue(i);
4127 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
4130 return std::make_pair(Res, Chain);
4133 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4134 assert(0 && "LowerOperation not implemented for this target!");
4139 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4140 SelectionDAG &DAG) {
4141 assert(0 && "CustomPromoteOperation not implemented for this target!");
4146 /// getMemsetValue - Vectorized representation of the memset value
4148 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4149 SelectionDAG &DAG) {
4150 MVT::ValueType CurVT = VT;
4151 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4152 uint64_t Val = C->getValue() & 255;
4154 while (CurVT != MVT::i8) {
4155 Val = (Val << Shift) | Val;
4157 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4159 return DAG.getConstant(Val, VT);
4161 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4163 while (CurVT != MVT::i8) {
4165 DAG.getNode(ISD::OR, VT,
4166 DAG.getNode(ISD::SHL, VT, Value,
4167 DAG.getConstant(Shift, MVT::i8)), Value);
4169 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4176 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4177 /// used when a memcpy is turned into a memset when the source is a constant
4179 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4180 SelectionDAG &DAG, TargetLowering &TLI,
4181 std::string &Str, unsigned Offset) {
4183 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4184 if (TLI.isLittleEndian())
4185 Offset = Offset + MSB - 1;
4186 for (unsigned i = 0; i != MSB; ++i) {
4187 Val = (Val << 8) | (unsigned char)Str[Offset];
4188 Offset += TLI.isLittleEndian() ? -1 : 1;
4190 return DAG.getConstant(Val, VT);
4193 /// getMemBasePlusOffset - Returns base and offset node for the
4194 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4195 SelectionDAG &DAG, TargetLowering &TLI) {
4196 MVT::ValueType VT = Base.getValueType();
4197 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4200 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4201 /// to replace the memset / memcpy is below the threshold. It also returns the
4202 /// types of the sequence of memory ops to perform memset / memcpy.
4203 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4204 unsigned Limit, uint64_t Size,
4205 unsigned Align, TargetLowering &TLI) {
4208 if (TLI.allowsUnalignedMemoryAccesses()) {
4211 switch (Align & 7) {
4227 MVT::ValueType LVT = MVT::i64;
4228 while (!TLI.isTypeLegal(LVT))
4229 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4230 assert(MVT::isInteger(LVT));
4235 unsigned NumMemOps = 0;
4237 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4238 while (VTSize > Size) {
4239 VT = (MVT::ValueType)((unsigned)VT - 1);
4242 assert(MVT::isInteger(VT));
4244 if (++NumMemOps > Limit)
4246 MemOps.push_back(VT);
4253 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4254 SDOperand Op1 = getValue(I.getOperand(1));
4255 SDOperand Op2 = getValue(I.getOperand(2));
4256 SDOperand Op3 = getValue(I.getOperand(3));
4257 SDOperand Op4 = getValue(I.getOperand(4));
4258 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4259 if (Align == 0) Align = 1;
4261 // If the source and destination are known to not be aliases, we can
4262 // lower memmove as memcpy.
4263 if (Op == ISD::MEMMOVE) {
4264 uint64_t Size = -1ULL;
4265 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4266 Size = C->getValue();
4267 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4268 AliasAnalysis::NoAlias)
4272 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4273 std::vector<MVT::ValueType> MemOps;
4275 // Expand memset / memcpy to a series of load / store ops
4276 // if the size operand falls below a certain threshold.
4277 SmallVector<SDOperand, 8> OutChains;
4279 default: break; // Do nothing for now.
4281 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4282 Size->getValue(), Align, TLI)) {
4283 unsigned NumMemOps = MemOps.size();
4284 unsigned Offset = 0;
4285 for (unsigned i = 0; i < NumMemOps; i++) {
4286 MVT::ValueType VT = MemOps[i];
4287 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4288 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4289 SDOperand Store = DAG.getStore(getRoot(), Value,
4290 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4291 I.getOperand(1), Offset);
4292 OutChains.push_back(Store);
4299 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4300 Size->getValue(), Align, TLI)) {
4301 unsigned NumMemOps = MemOps.size();
4302 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4303 GlobalAddressSDNode *G = NULL;
4305 bool CopyFromStr = false;
4307 if (Op2.getOpcode() == ISD::GlobalAddress)
4308 G = cast<GlobalAddressSDNode>(Op2);
4309 else if (Op2.getOpcode() == ISD::ADD &&
4310 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4311 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4312 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4313 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4316 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4317 if (GV && GV->isConstant()) {
4318 Str = GV->getStringValue(false);
4326 for (unsigned i = 0; i < NumMemOps; i++) {
4327 MVT::ValueType VT = MemOps[i];
4328 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4329 SDOperand Value, Chain, Store;
4332 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4335 DAG.getStore(Chain, Value,
4336 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4337 I.getOperand(1), DstOff);
4339 Value = DAG.getLoad(VT, getRoot(),
4340 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4341 I.getOperand(2), SrcOff, false, Align);
4342 Chain = Value.getValue(1);
4344 DAG.getStore(Chain, Value,
4345 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4346 I.getOperand(1), DstOff, false, Align);
4348 OutChains.push_back(Store);
4357 if (!OutChains.empty()) {
4358 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4359 &OutChains[0], OutChains.size()));
4364 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4368 assert(0 && "Unknown Op");
4370 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4373 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4376 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4382 //===----------------------------------------------------------------------===//
4383 // SelectionDAGISel code
4384 //===----------------------------------------------------------------------===//
4386 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4387 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4390 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4391 AU.addRequired<AliasAnalysis>();
4392 AU.addRequired<CollectorModuleMetadata>();
4393 AU.setPreservesAll();
4398 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4399 // Get alias analysis for load/store combining.
4400 AA = &getAnalysis<AliasAnalysis>();
4402 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4403 if (MF.getFunction()->hasCollector())
4404 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4407 RegInfo = &MF.getRegInfo();
4408 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4410 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4412 if (ExceptionHandling)
4413 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4414 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4415 // Mark landing pad.
4416 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4418 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4419 SelectBasicBlock(I, MF, FuncInfo);
4421 // Add function live-ins to entry block live-in set.
4422 BasicBlock *EntryBB = &Fn.getEntryBlock();
4423 BB = FuncInfo.MBBMap[EntryBB];
4424 if (!RegInfo->livein_empty())
4425 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4426 E = RegInfo->livein_end(); I != E; ++I)
4427 BB->addLiveIn(I->first);
4430 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4431 "Not all catch info was assigned to a landing pad!");
4437 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4439 SDOperand Op = getValue(V);
4440 assert((Op.getOpcode() != ISD::CopyFromReg ||
4441 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4442 "Copy from a reg to the same reg!");
4444 MVT::ValueType SrcVT = Op.getValueType();
4445 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4446 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4447 SmallVector<SDOperand, 8> Regs(NumRegs);
4448 SmallVector<SDOperand, 8> Chains(NumRegs);
4450 // Copy the value by legal parts into sequential virtual registers.
4451 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4452 for (unsigned i = 0; i != NumRegs; ++i)
4453 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4454 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4457 void SelectionDAGISel::
4458 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4459 std::vector<SDOperand> &UnorderedChains) {
4460 // If this is the entry block, emit arguments.
4461 Function &F = *LLVMBB->getParent();
4462 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4463 SDOperand OldRoot = SDL.DAG.getRoot();
4464 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4467 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4469 if (!AI->use_empty()) {
4470 SDL.setValue(AI, Args[a]);
4472 // If this argument is live outside of the entry block, insert a copy from
4473 // whereever we got it to the vreg that other BB's will reference it as.
4474 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4475 if (VMI != FuncInfo.ValueMap.end()) {
4476 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4477 UnorderedChains.push_back(Copy);
4481 // Finally, if the target has anything special to do, allow it to do so.
4482 // FIXME: this should insert code into the DAG!
4483 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4486 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4487 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4488 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4489 if (isSelector(I)) {
4490 // Apply the catch info to DestBB.
4491 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4493 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4494 FLI.CatchInfoFound.insert(I);
4499 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4500 /// DAG and fixes their tailcall attribute operand.
4501 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4502 TargetLowering& TLI) {
4503 SDNode * Ret = NULL;
4504 SDOperand Terminator = DAG.getRoot();
4507 if (Terminator.getOpcode() == ISD::RET) {
4508 Ret = Terminator.Val;
4511 // Fix tail call attribute of CALL nodes.
4512 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4513 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4514 if (BI->getOpcode() == ISD::CALL) {
4515 SDOperand OpRet(Ret, 0);
4516 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4517 bool isMarkedTailCall =
4518 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4519 // If CALL node has tail call attribute set to true and the call is not
4520 // eligible (no RET or the target rejects) the attribute is fixed to
4521 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4522 // must correctly identify tail call optimizable calls.
4523 if (isMarkedTailCall &&
4525 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4526 SmallVector<SDOperand, 32> Ops;
4528 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4529 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4533 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4535 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4541 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4542 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4543 FunctionLoweringInfo &FuncInfo) {
4544 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4546 std::vector<SDOperand> UnorderedChains;
4548 // Lower any arguments needed in this block if this is the entry block.
4549 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4550 LowerArguments(LLVMBB, SDL, UnorderedChains);
4552 BB = FuncInfo.MBBMap[LLVMBB];
4553 SDL.setCurrentBasicBlock(BB);
4555 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4557 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4558 // Add a label to mark the beginning of the landing pad. Deletion of the
4559 // landing pad can thus be detected via the MachineModuleInfo.
4560 unsigned LabelID = MMI->addLandingPad(BB);
4561 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4562 DAG.getConstant(LabelID, MVT::i32)));
4564 // Mark exception register as live in.
4565 unsigned Reg = TLI.getExceptionAddressRegister();
4566 if (Reg) BB->addLiveIn(Reg);
4568 // Mark exception selector register as live in.
4569 Reg = TLI.getExceptionSelectorRegister();
4570 if (Reg) BB->addLiveIn(Reg);
4572 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4573 // function and list of typeids logically belong to the invoke (or, if you
4574 // like, the basic block containing the invoke), and need to be associated
4575 // with it in the dwarf exception handling tables. Currently however the
4576 // information is provided by an intrinsic (eh.selector) that can be moved
4577 // to unexpected places by the optimizers: if the unwind edge is critical,
4578 // then breaking it can result in the intrinsics being in the successor of
4579 // the landing pad, not the landing pad itself. This results in exceptions
4580 // not being caught because no typeids are associated with the invoke.
4581 // This may not be the only way things can go wrong, but it is the only way
4582 // we try to work around for the moment.
4583 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4585 if (Br && Br->isUnconditional()) { // Critical edge?
4586 BasicBlock::iterator I, E;
4587 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4592 // No catch info found - try to extract some from the successor.
4593 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4597 // Lower all of the non-terminator instructions.
4598 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4602 // Ensure that all instructions which are used outside of their defining
4603 // blocks are available as virtual registers. Invoke is handled elsewhere.
4604 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4605 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4606 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4607 if (VMI != FuncInfo.ValueMap.end())
4608 UnorderedChains.push_back(
4609 SDL.CopyValueToVirtualRegister(I, VMI->second));
4612 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4613 // ensure constants are generated when needed. Remember the virtual registers
4614 // that need to be added to the Machine PHI nodes as input. We cannot just
4615 // directly add them, because expansion might result in multiple MBB's for one
4616 // BB. As such, the start of the BB might correspond to a different MBB than
4619 TerminatorInst *TI = LLVMBB->getTerminator();
4621 // Emit constants only once even if used by multiple PHI nodes.
4622 std::map<Constant*, unsigned> ConstantsOut;
4624 // Vector bool would be better, but vector<bool> is really slow.
4625 std::vector<unsigned char> SuccsHandled;
4626 if (TI->getNumSuccessors())
4627 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4629 // Check successor nodes' PHI nodes that expect a constant to be available
4631 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4632 BasicBlock *SuccBB = TI->getSuccessor(succ);
4633 if (!isa<PHINode>(SuccBB->begin())) continue;
4634 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4636 // If this terminator has multiple identical successors (common for
4637 // switches), only handle each succ once.
4638 unsigned SuccMBBNo = SuccMBB->getNumber();
4639 if (SuccsHandled[SuccMBBNo]) continue;
4640 SuccsHandled[SuccMBBNo] = true;
4642 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4645 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4646 // nodes and Machine PHI nodes, but the incoming operands have not been
4648 for (BasicBlock::iterator I = SuccBB->begin();
4649 (PN = dyn_cast<PHINode>(I)); ++I) {
4650 // Ignore dead phi's.
4651 if (PN->use_empty()) continue;
4654 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4656 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4657 unsigned &RegOut = ConstantsOut[C];
4659 RegOut = FuncInfo.CreateRegForValue(C);
4660 UnorderedChains.push_back(
4661 SDL.CopyValueToVirtualRegister(C, RegOut));
4665 Reg = FuncInfo.ValueMap[PHIOp];
4667 assert(isa<AllocaInst>(PHIOp) &&
4668 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4669 "Didn't codegen value into a register!??");
4670 Reg = FuncInfo.CreateRegForValue(PHIOp);
4671 UnorderedChains.push_back(
4672 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4676 // Remember that this register needs to added to the machine PHI node as
4677 // the input for this MBB.
4678 MVT::ValueType VT = TLI.getValueType(PN->getType());
4679 unsigned NumRegisters = TLI.getNumRegisters(VT);
4680 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4681 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4684 ConstantsOut.clear();
4686 // Turn all of the unordered chains into one factored node.
4687 if (!UnorderedChains.empty()) {
4688 SDOperand Root = SDL.getRoot();
4689 if (Root.getOpcode() != ISD::EntryToken) {
4690 unsigned i = 0, e = UnorderedChains.size();
4691 for (; i != e; ++i) {
4692 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4693 if (UnorderedChains[i].Val->getOperand(0) == Root)
4694 break; // Don't add the root if we already indirectly depend on it.
4698 UnorderedChains.push_back(Root);
4700 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4701 &UnorderedChains[0], UnorderedChains.size()));
4704 // Lower the terminator after the copies are emitted.
4705 SDL.visit(*LLVMBB->getTerminator());
4707 // Copy over any CaseBlock records that may now exist due to SwitchInst
4708 // lowering, as well as any jump table information.
4709 SwitchCases.clear();
4710 SwitchCases = SDL.SwitchCases;
4712 JTCases = SDL.JTCases;
4713 BitTestCases.clear();
4714 BitTestCases = SDL.BitTestCases;
4716 // Make sure the root of the DAG is up-to-date.
4717 DAG.setRoot(SDL.getRoot());
4719 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4720 // with correct tailcall attribute so that the target can rely on the tailcall
4721 // attribute indicating whether the call is really eligible for tail call
4723 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4726 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4727 DOUT << "Lowered selection DAG:\n";
4730 // Run the DAG combiner in pre-legalize mode.
4731 DAG.Combine(false, *AA);
4733 DOUT << "Optimized lowered selection DAG:\n";
4736 // Second step, hack on the DAG until it only uses operations and types that
4737 // the target supports.
4738 #if 0 // Enable this some day.
4739 DAG.LegalizeTypes();
4740 // Someday even later, enable a dag combine pass here.
4744 DOUT << "Legalized selection DAG:\n";
4747 // Run the DAG combiner in post-legalize mode.
4748 DAG.Combine(true, *AA);
4750 DOUT << "Optimized legalized selection DAG:\n";
4753 if (ViewISelDAGs) DAG.viewGraph();
4755 // Third, instruction select all of the operations to machine code, adding the
4756 // code to the MachineBasicBlock.
4757 InstructionSelectBasicBlock(DAG);
4759 DOUT << "Selected machine code:\n";
4763 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4764 FunctionLoweringInfo &FuncInfo) {
4765 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4767 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4770 // First step, lower LLVM code to some DAG. This DAG may use operations and
4771 // types that are not supported by the target.
4772 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4774 // Second step, emit the lowered DAG as machine code.
4775 CodeGenAndEmitDAG(DAG);
4778 DOUT << "Total amount of phi nodes to update: "
4779 << PHINodesToUpdate.size() << "\n";
4780 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4781 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4782 << ", " << PHINodesToUpdate[i].second << ")\n";);
4784 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4785 // PHI nodes in successors.
4786 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4787 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4788 MachineInstr *PHI = PHINodesToUpdate[i].first;
4789 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4790 "This is not a machine PHI node that we are updating!");
4791 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4793 PHI->addOperand(MachineOperand::CreateMBB(BB));
4798 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4799 // Lower header first, if it wasn't already lowered
4800 if (!BitTestCases[i].Emitted) {
4801 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4803 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4804 // Set the current basic block to the mbb we wish to insert the code into
4805 BB = BitTestCases[i].Parent;
4806 HSDL.setCurrentBasicBlock(BB);
4808 HSDL.visitBitTestHeader(BitTestCases[i]);
4809 HSDAG.setRoot(HSDL.getRoot());
4810 CodeGenAndEmitDAG(HSDAG);
4813 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4814 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4816 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
4817 // Set the current basic block to the mbb we wish to insert the code into
4818 BB = BitTestCases[i].Cases[j].ThisBB;
4819 BSDL.setCurrentBasicBlock(BB);
4822 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4823 BitTestCases[i].Reg,
4824 BitTestCases[i].Cases[j]);
4826 BSDL.visitBitTestCase(BitTestCases[i].Default,
4827 BitTestCases[i].Reg,
4828 BitTestCases[i].Cases[j]);
4831 BSDAG.setRoot(BSDL.getRoot());
4832 CodeGenAndEmitDAG(BSDAG);
4836 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4837 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4838 MachineBasicBlock *PHIBB = PHI->getParent();
4839 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4840 "This is not a machine PHI node that we are updating!");
4841 // This is "default" BB. We have two jumps to it. From "header" BB and
4842 // from last "case" BB.
4843 if (PHIBB == BitTestCases[i].Default) {
4844 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4846 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
4847 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4849 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
4852 // One of "cases" BB.
4853 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4854 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4855 if (cBB->succ_end() !=
4856 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4857 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4859 PHI->addOperand(MachineOperand::CreateMBB(cBB));
4865 // If the JumpTable record is filled in, then we need to emit a jump table.
4866 // Updating the PHI nodes is tricky in this case, since we need to determine
4867 // whether the PHI is a successor of the range check MBB or the jump table MBB
4868 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4869 // Lower header first, if it wasn't already lowered
4870 if (!JTCases[i].first.Emitted) {
4871 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4873 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4874 // Set the current basic block to the mbb we wish to insert the code into
4875 BB = JTCases[i].first.HeaderBB;
4876 HSDL.setCurrentBasicBlock(BB);
4878 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4879 HSDAG.setRoot(HSDL.getRoot());
4880 CodeGenAndEmitDAG(HSDAG);
4883 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4885 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
4886 // Set the current basic block to the mbb we wish to insert the code into
4887 BB = JTCases[i].second.MBB;
4888 JSDL.setCurrentBasicBlock(BB);
4890 JSDL.visitJumpTable(JTCases[i].second);
4891 JSDAG.setRoot(JSDL.getRoot());
4892 CodeGenAndEmitDAG(JSDAG);
4895 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4896 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4897 MachineBasicBlock *PHIBB = PHI->getParent();
4898 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4899 "This is not a machine PHI node that we are updating!");
4900 // "default" BB. We can go there only from header BB.
4901 if (PHIBB == JTCases[i].second.Default) {
4902 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4904 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
4906 // JT BB. Just iterate over successors here
4907 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4908 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4910 PHI->addOperand(MachineOperand::CreateMBB(BB));
4915 // If the switch block involved a branch to one of the actual successors, we
4916 // need to update PHI nodes in that block.
4917 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4918 MachineInstr *PHI = PHINodesToUpdate[i].first;
4919 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4920 "This is not a machine PHI node that we are updating!");
4921 if (BB->isSuccessor(PHI->getParent())) {
4922 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4924 PHI->addOperand(MachineOperand::CreateMBB(BB));
4928 // If we generated any switch lowering information, build and codegen any
4929 // additional DAGs necessary.
4930 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4931 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4933 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
4935 // Set the current basic block to the mbb we wish to insert the code into
4936 BB = SwitchCases[i].ThisBB;
4937 SDL.setCurrentBasicBlock(BB);
4940 SDL.visitSwitchCase(SwitchCases[i]);
4941 SDAG.setRoot(SDL.getRoot());
4942 CodeGenAndEmitDAG(SDAG);
4944 // Handle any PHI nodes in successors of this chunk, as if we were coming
4945 // from the original BB before switch expansion. Note that PHI nodes can
4946 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4947 // handle them the right number of times.
4948 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4949 for (MachineBasicBlock::iterator Phi = BB->begin();
4950 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4951 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4952 for (unsigned pn = 0; ; ++pn) {
4953 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4954 if (PHINodesToUpdate[pn].first == Phi) {
4955 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
4957 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
4963 // Don't process RHS if same block as LHS.
4964 if (BB == SwitchCases[i].FalseBB)
4965 SwitchCases[i].FalseBB = 0;
4967 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4968 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4969 SwitchCases[i].FalseBB = 0;
4971 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4976 //===----------------------------------------------------------------------===//
4977 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4978 /// target node in the graph.
4979 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4980 if (ViewSchedDAGs) DAG.viewGraph();
4982 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4986 RegisterScheduler::setDefault(Ctor);
4989 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4992 if (ViewSUnitDAGs) SL->viewGraph();
4998 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4999 return new HazardRecognizer();
5002 //===----------------------------------------------------------------------===//
5003 // Helper functions used by the generated instruction selector.
5004 //===----------------------------------------------------------------------===//
5005 // Calls to these methods are generated by tblgen.
5007 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5008 /// the dag combiner simplified the 255, we still want to match. RHS is the
5009 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5010 /// specified in the .td file (e.g. 255).
5011 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5012 int64_t DesiredMaskS) const {
5013 uint64_t ActualMask = RHS->getValue();
5014 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5016 // If the actual mask exactly matches, success!
5017 if (ActualMask == DesiredMask)
5020 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5021 if (ActualMask & ~DesiredMask)
5024 // Otherwise, the DAG Combiner may have proven that the value coming in is
5025 // either already zero or is not demanded. Check for known zero input bits.
5026 uint64_t NeededMask = DesiredMask & ~ActualMask;
5027 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5030 // TODO: check to see if missing bits are just not demanded.
5032 // Otherwise, this pattern doesn't match.
5036 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5037 /// the dag combiner simplified the 255, we still want to match. RHS is the
5038 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5039 /// specified in the .td file (e.g. 255).
5040 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5041 int64_t DesiredMaskS) const {
5042 uint64_t ActualMask = RHS->getValue();
5043 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5045 // If the actual mask exactly matches, success!
5046 if (ActualMask == DesiredMask)
5049 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5050 if (ActualMask & ~DesiredMask)
5053 // Otherwise, the DAG Combiner may have proven that the value coming in is
5054 // either already zero or is not demanded. Check for known zero input bits.
5055 uint64_t NeededMask = DesiredMask & ~ActualMask;
5057 uint64_t KnownZero, KnownOne;
5058 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5060 // If all the missing bits in the or are already known to be set, match!
5061 if ((NeededMask & KnownOne) == NeededMask)
5064 // TODO: check to see if missing bits are just not demanded.
5066 // Otherwise, this pattern doesn't match.
5071 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5072 /// by tblgen. Others should not call it.
5073 void SelectionDAGISel::
5074 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5075 std::vector<SDOperand> InOps;
5076 std::swap(InOps, Ops);
5078 Ops.push_back(InOps[0]); // input chain.
5079 Ops.push_back(InOps[1]); // input asm string.
5081 unsigned i = 2, e = InOps.size();
5082 if (InOps[e-1].getValueType() == MVT::Flag)
5083 --e; // Don't process a flag operand if it is here.
5086 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5087 if ((Flags & 7) != 4 /*MEM*/) {
5088 // Just skip over this operand, copying the operands verbatim.
5089 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5090 i += (Flags >> 3) + 1;
5092 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5093 // Otherwise, this is a memory operand. Ask the target to select it.
5094 std::vector<SDOperand> SelOps;
5095 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5096 cerr << "Could not match memory address. Inline asm failure!\n";
5100 // Add this to the output node.
5101 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5102 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5104 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5109 // Add the flag input back if present.
5110 if (e != InOps.size())
5111 Ops.push_back(InOps.back());
5114 char SelectionDAGISel::ID = 0;