1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLibraryInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/Timer.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/ADT/PostOrderIterator.h"
55 #include "llvm/ADT/Statistic.h"
59 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
60 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
61 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
62 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
63 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
68 cl::desc("Enable extra verbose messages in the \"fast\" "
69 "instruction selector"));
71 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
72 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
73 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
74 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
75 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
76 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
77 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
79 // Standard binary operators...
80 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
81 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
82 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
83 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
84 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
85 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
86 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
87 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
88 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
89 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
90 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
91 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
93 // Logical operators...
94 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
95 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
96 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
98 // Memory instructions...
99 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
100 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
101 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
102 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
103 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
104 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
105 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
107 // Convert instructions...
108 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
109 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
110 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
111 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
112 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
113 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
114 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
115 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
116 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
117 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
118 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
119 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
121 // Other instructions...
122 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
123 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
124 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
125 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
126 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
127 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
128 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
129 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
130 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
131 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
132 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
133 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
134 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
135 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
136 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
140 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
141 cl::desc("Enable verbose messages in the \"fast\" "
142 "instruction selector"));
144 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
145 cl::desc("Enable abort calls when \"fast\" instruction fails"));
149 cl::desc("use Machine Branch Probability Info"),
150 cl::init(true), cl::Hidden);
154 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
155 cl::desc("Pop up a window to show dags before the first "
156 "dag combine pass"));
158 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
159 cl::desc("Pop up a window to show dags before legalize types"));
161 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
162 cl::desc("Pop up a window to show dags before legalize"));
164 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
165 cl::desc("Pop up a window to show dags before the second "
166 "dag combine pass"));
168 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
169 cl::desc("Pop up a window to show dags before the post legalize types"
170 " dag combine pass"));
172 ViewISelDAGs("view-isel-dags", cl::Hidden,
173 cl::desc("Pop up a window to show isel dags as they are selected"));
175 ViewSchedDAGs("view-sched-dags", cl::Hidden,
176 cl::desc("Pop up a window to show sched dags as they are processed"));
178 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
179 cl::desc("Pop up a window to show SUnit dags after they are processed"));
181 static const bool ViewDAGCombine1 = false,
182 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
183 ViewDAGCombine2 = false,
184 ViewDAGCombineLT = false,
185 ViewISelDAGs = false, ViewSchedDAGs = false,
186 ViewSUnitDAGs = false;
189 //===---------------------------------------------------------------------===//
191 /// RegisterScheduler class - Track the registration of instruction schedulers.
193 //===---------------------------------------------------------------------===//
194 MachinePassRegistry RegisterScheduler::Registry;
196 //===---------------------------------------------------------------------===//
198 /// ISHeuristic command line option for instruction schedulers.
200 //===---------------------------------------------------------------------===//
201 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
202 RegisterPassParser<RegisterScheduler> >
203 ISHeuristic("pre-RA-sched",
204 cl::init(&createDefaultScheduler),
205 cl::desc("Instruction schedulers available (before register"
208 static RegisterScheduler
209 defaultListDAGScheduler("default", "Best scheduler for the target",
210 createDefaultScheduler);
213 //===--------------------------------------------------------------------===//
214 /// createDefaultScheduler - This creates an instruction scheduler appropriate
216 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
217 CodeGenOpt::Level OptLevel) {
218 const TargetLowering &TLI = IS->getTargetLowering();
220 if (OptLevel == CodeGenOpt::None ||
221 TLI.getSchedulingPreference() == Sched::Source)
222 return createSourceListDAGScheduler(IS, OptLevel);
223 if (TLI.getSchedulingPreference() == Sched::RegPressure)
224 return createBURRListDAGScheduler(IS, OptLevel);
225 if (TLI.getSchedulingPreference() == Sched::Hybrid)
226 return createHybridListDAGScheduler(IS, OptLevel);
227 if (TLI.getSchedulingPreference() == Sched::VLIW)
228 return createVLIWDAGScheduler(IS, OptLevel);
229 assert(TLI.getSchedulingPreference() == Sched::ILP &&
230 "Unknown sched type!");
231 return createILPListDAGScheduler(IS, OptLevel);
235 // EmitInstrWithCustomInserter - This method should be implemented by targets
236 // that mark instructions with the 'usesCustomInserter' flag. These
237 // instructions are special in various ways, which require special support to
238 // insert. The specified MachineInstr is created but not inserted into any
239 // basic blocks, and this method is called to expand it into a sequence of
240 // instructions, potentially also creating new basic blocks and control flow.
241 // When new basic blocks are inserted and the edges from MBB to its successors
242 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
245 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
246 MachineBasicBlock *MBB) const {
248 dbgs() << "If a target marks an instruction with "
249 "'usesCustomInserter', it must implement "
250 "TargetLowering::EmitInstrWithCustomInserter!";
255 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
256 SDNode *Node) const {
257 assert(!MI->hasPostISelHook() &&
258 "If a target marks an instruction with 'hasPostISelHook', "
259 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
262 //===----------------------------------------------------------------------===//
263 // SelectionDAGISel code
264 //===----------------------------------------------------------------------===//
266 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
267 CodeGenOpt::Level OL) :
268 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
269 FuncInfo(new FunctionLoweringInfo(TLI)),
270 CurDAG(new SelectionDAG(tm, OL)),
271 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
275 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
276 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
277 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
278 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
281 SelectionDAGISel::~SelectionDAGISel() {
287 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
288 AU.addRequired<AliasAnalysis>();
289 AU.addPreserved<AliasAnalysis>();
290 AU.addRequired<GCModuleInfo>();
291 AU.addPreserved<GCModuleInfo>();
292 AU.addRequired<TargetLibraryInfo>();
293 if (UseMBPI && OptLevel != CodeGenOpt::None)
294 AU.addRequired<BranchProbabilityInfo>();
295 MachineFunctionPass::getAnalysisUsage(AU);
298 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
299 /// may trap on it. In this case we have to split the edge so that the path
300 /// through the predecessor block that doesn't go to the phi block doesn't
301 /// execute the possibly trapping instruction.
303 /// This is required for correctness, so it must be done at -O0.
305 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
306 // Loop for blocks with phi nodes.
307 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
308 PHINode *PN = dyn_cast<PHINode>(BB->begin());
309 if (PN == 0) continue;
312 // For each block with a PHI node, check to see if any of the input values
313 // are potentially trapping constant expressions. Constant expressions are
314 // the only potentially trapping value that can occur as the argument to a
316 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
317 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
318 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
319 if (CE == 0 || !CE->canTrap()) continue;
321 // The only case we have to worry about is when the edge is critical.
322 // Since this block has a PHI Node, we assume it has multiple input
323 // edges: check to see if the pred has multiple successors.
324 BasicBlock *Pred = PN->getIncomingBlock(i);
325 if (Pred->getTerminator()->getNumSuccessors() == 1)
328 // Okay, we have to split this edge.
329 SplitCriticalEdge(Pred->getTerminator(),
330 GetSuccessorNumber(Pred, BB), SDISel, true);
336 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
337 // Do some sanity-checking on the command-line options.
338 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
339 "-fast-isel-verbose requires -fast-isel");
340 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
341 "-fast-isel-abort requires -fast-isel");
343 const Function &Fn = *mf.getFunction();
344 const TargetInstrInfo &TII = *TM.getInstrInfo();
345 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
348 RegInfo = &MF->getRegInfo();
349 AA = &getAnalysis<AliasAnalysis>();
350 LibInfo = &getAnalysis<TargetLibraryInfo>();
351 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
353 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
355 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
358 FuncInfo->set(Fn, *MF);
360 if (UseMBPI && OptLevel != CodeGenOpt::None)
361 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
365 SDB->init(GFI, *AA, LibInfo);
367 SelectAllBasicBlocks(Fn);
369 // If the first basic block in the function has live ins that need to be
370 // copied into vregs, emit the copies into the top of the block before
371 // emitting the code for the block.
372 MachineBasicBlock *EntryMBB = MF->begin();
373 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
375 DenseMap<unsigned, unsigned> LiveInMap;
376 if (!FuncInfo->ArgDbgValues.empty())
377 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
378 E = RegInfo->livein_end(); LI != E; ++LI)
380 LiveInMap.insert(std::make_pair(LI->first, LI->second));
382 // Insert DBG_VALUE instructions for function arguments to the entry block.
383 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
384 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
385 unsigned Reg = MI->getOperand(0).getReg();
386 if (TargetRegisterInfo::isPhysicalRegister(Reg))
387 EntryMBB->insert(EntryMBB->begin(), MI);
389 MachineInstr *Def = RegInfo->getVRegDef(Reg);
390 MachineBasicBlock::iterator InsertPos = Def;
391 // FIXME: VR def may not be in entry block.
392 Def->getParent()->insert(llvm::next(InsertPos), MI);
395 // If Reg is live-in then update debug info to track its copy in a vreg.
396 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
397 if (LDI != LiveInMap.end()) {
398 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
399 MachineBasicBlock::iterator InsertPos = Def;
400 const MDNode *Variable =
401 MI->getOperand(MI->getNumOperands()-1).getMetadata();
402 unsigned Offset = MI->getOperand(1).getImm();
403 // Def is never a terminator here, so it is ok to increment InsertPos.
404 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
405 TII.get(TargetOpcode::DBG_VALUE))
406 .addReg(LDI->second, RegState::Debug)
407 .addImm(Offset).addMetadata(Variable);
409 // If this vreg is directly copied into an exported register then
410 // that COPY instructions also need DBG_VALUE, if it is the only
411 // user of LDI->second.
412 MachineInstr *CopyUseMI = NULL;
413 for (MachineRegisterInfo::use_iterator
414 UI = RegInfo->use_begin(LDI->second);
415 MachineInstr *UseMI = UI.skipInstruction();) {
416 if (UseMI->isDebugValue()) continue;
417 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
418 CopyUseMI = UseMI; continue;
420 // Otherwise this is another use or second copy use.
421 CopyUseMI = NULL; break;
424 MachineInstr *NewMI =
425 BuildMI(*MF, CopyUseMI->getDebugLoc(),
426 TII.get(TargetOpcode::DBG_VALUE))
427 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
428 .addImm(Offset).addMetadata(Variable);
429 MachineBasicBlock::iterator Pos = CopyUseMI;
430 EntryMBB->insertAfter(Pos, NewMI);
435 // Determine if there are any calls in this machine function.
436 MachineFrameInfo *MFI = MF->getFrameInfo();
437 if (!MFI->hasCalls()) {
438 for (MachineFunction::const_iterator
439 I = MF->begin(), E = MF->end(); I != E; ++I) {
440 const MachineBasicBlock *MBB = I;
441 for (MachineBasicBlock::const_iterator
442 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
443 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
445 if ((MCID.isCall() && !MCID.isReturn()) ||
446 II->isStackAligningInlineAsm()) {
447 MFI->setHasCalls(true);
455 // Determine if there is a call to setjmp in the machine function.
456 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
458 // Replace forward-declared registers with the registers containing
459 // the desired value.
460 MachineRegisterInfo &MRI = MF->getRegInfo();
461 for (DenseMap<unsigned, unsigned>::iterator
462 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
464 unsigned From = I->first;
465 unsigned To = I->second;
466 // If To is also scheduled to be replaced, find what its ultimate
469 DenseMap<unsigned, unsigned>::iterator J =
470 FuncInfo->RegFixups.find(To);
475 MRI.replaceRegWith(From, To);
478 // Release function-specific state. SDB and CurDAG are already cleared
485 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
486 BasicBlock::const_iterator End,
488 // Lower all of the non-terminator instructions. If a call is emitted
489 // as a tail call, cease emitting nodes for this block. Terminators
490 // are handled below.
491 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
494 // Make sure the root of the DAG is up-to-date.
495 CurDAG->setRoot(SDB->getControlRoot());
496 HadTailCall = SDB->HasTailCall;
499 // Final step, emit the lowered DAG as machine code.
503 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
504 SmallPtrSet<SDNode*, 128> VisitedNodes;
505 SmallVector<SDNode*, 128> Worklist;
507 Worklist.push_back(CurDAG->getRoot().getNode());
513 SDNode *N = Worklist.pop_back_val();
515 // If we've already seen this node, ignore it.
516 if (!VisitedNodes.insert(N))
519 // Otherwise, add all chain operands to the worklist.
520 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
521 if (N->getOperand(i).getValueType() == MVT::Other)
522 Worklist.push_back(N->getOperand(i).getNode());
524 // If this is a CopyToReg with a vreg dest, process it.
525 if (N->getOpcode() != ISD::CopyToReg)
528 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
529 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
532 // Ignore non-scalar or non-integer values.
533 SDValue Src = N->getOperand(2);
534 EVT SrcVT = Src.getValueType();
535 if (!SrcVT.isInteger() || SrcVT.isVector())
538 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
539 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
540 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
541 } while (!Worklist.empty());
544 void SelectionDAGISel::CodeGenAndEmitDAG() {
545 std::string GroupName;
546 if (TimePassesIsEnabled)
547 GroupName = "Instruction Selection and Scheduling";
548 std::string BlockName;
549 int BlockNumber = -1;
552 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
553 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
557 BlockNumber = FuncInfo->MBB->getNumber();
558 BlockName = MF->getFunction()->getName().str() + ":" +
559 FuncInfo->MBB->getBasicBlock()->getName().str();
561 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
562 << " '" << BlockName << "'\n"; CurDAG->dump());
564 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
566 // Run the DAG combiner in pre-legalize mode.
568 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
569 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
572 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
573 << " '" << BlockName << "'\n"; CurDAG->dump());
575 // Second step, hack on the DAG until it only uses operations and types that
576 // the target supports.
577 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
582 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
583 Changed = CurDAG->LegalizeTypes();
586 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
587 << " '" << BlockName << "'\n"; CurDAG->dump());
590 if (ViewDAGCombineLT)
591 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
593 // Run the DAG combiner in post-type-legalize mode.
595 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
596 TimePassesIsEnabled);
597 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
600 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
601 << " '" << BlockName << "'\n"; CurDAG->dump());
605 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
606 Changed = CurDAG->LegalizeVectors();
611 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
612 CurDAG->LegalizeTypes();
615 if (ViewDAGCombineLT)
616 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
618 // Run the DAG combiner in post-type-legalize mode.
620 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
621 TimePassesIsEnabled);
622 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
625 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
626 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
629 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
632 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
636 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
637 << " '" << BlockName << "'\n"; CurDAG->dump());
639 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
641 // Run the DAG combiner in post-legalize mode.
643 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
644 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
647 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
648 << " '" << BlockName << "'\n"; CurDAG->dump());
650 if (OptLevel != CodeGenOpt::None)
651 ComputeLiveOutVRegInfo();
653 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
655 // Third, instruction select all of the operations to machine code, adding the
656 // code to the MachineBasicBlock.
658 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
659 DoInstructionSelection();
662 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
663 << " '" << BlockName << "'\n"; CurDAG->dump());
665 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
667 // Schedule machine code.
668 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
670 NamedRegionTimer T("Instruction Scheduling", GroupName,
671 TimePassesIsEnabled);
672 Scheduler->Run(CurDAG, FuncInfo->MBB);
675 if (ViewSUnitDAGs) Scheduler->viewGraph();
677 // Emit machine code to BB. This can change 'BB' to the last block being
679 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
681 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
683 // FuncInfo->InsertPt is passed by reference and set to the end of the
684 // scheduled instructions.
685 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
688 // If the block was split, make sure we update any references that are used to
689 // update PHI nodes later on.
690 if (FirstMBB != LastMBB)
691 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
693 // Free the scheduler state.
695 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
696 TimePassesIsEnabled);
700 // Free the SelectionDAG state, now that we're finished with it.
705 /// ISelUpdater - helper class to handle updates of the instruction selection
707 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
708 SelectionDAG::allnodes_iterator &ISelPosition;
710 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
711 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
713 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
714 /// deleted is the current ISelPosition node, update ISelPosition.
716 virtual void NodeDeleted(SDNode *N, SDNode *E) {
717 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
721 } // end anonymous namespace
723 void SelectionDAGISel::DoInstructionSelection() {
724 DEBUG(errs() << "===== Instruction selection begins: BB#"
725 << FuncInfo->MBB->getNumber()
726 << " '" << FuncInfo->MBB->getName() << "'\n");
730 // Select target instructions for the DAG.
732 // Number all nodes with a topological order and set DAGSize.
733 DAGSize = CurDAG->AssignTopologicalOrder();
735 // Create a dummy node (which is not added to allnodes), that adds
736 // a reference to the root node, preventing it from being deleted,
737 // and tracking any changes of the root.
738 HandleSDNode Dummy(CurDAG->getRoot());
739 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
742 // Make sure that ISelPosition gets properly updated when nodes are deleted
743 // in calls made from this function.
744 ISelUpdater ISU(*CurDAG, ISelPosition);
746 // The AllNodes list is now topological-sorted. Visit the
747 // nodes by starting at the end of the list (the root of the
748 // graph) and preceding back toward the beginning (the entry
750 while (ISelPosition != CurDAG->allnodes_begin()) {
751 SDNode *Node = --ISelPosition;
752 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
753 // but there are currently some corner cases that it misses. Also, this
754 // makes it theoretically possible to disable the DAGCombiner.
755 if (Node->use_empty())
758 SDNode *ResNode = Select(Node);
760 // FIXME: This is pretty gross. 'Select' should be changed to not return
761 // anything at all and this code should be nuked with a tactical strike.
763 // If node should not be replaced, continue with the next one.
764 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
768 ReplaceUses(Node, ResNode);
770 // If after the replacement this node is not used any more,
771 // remove this dead node.
772 if (Node->use_empty()) // Don't delete EntryToken, etc.
773 CurDAG->RemoveDeadNode(Node);
776 CurDAG->setRoot(Dummy.getValue());
779 DEBUG(errs() << "===== Instruction selection ends:\n");
781 PostprocessISelDAG();
784 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
785 /// do other setup for EH landing-pad blocks.
786 void SelectionDAGISel::PrepareEHLandingPad() {
787 MachineBasicBlock *MBB = FuncInfo->MBB;
789 // Add a label to mark the beginning of the landing pad. Deletion of the
790 // landing pad can thus be detected via the MachineModuleInfo.
791 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
793 // Assign the call site to the landing pad's begin label.
794 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
796 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
797 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
800 // Mark exception register as live in.
801 unsigned Reg = TLI.getExceptionPointerRegister();
802 if (Reg) MBB->addLiveIn(Reg);
804 // Mark exception selector register as live in.
805 Reg = TLI.getExceptionSelectorRegister();
806 if (Reg) MBB->addLiveIn(Reg);
809 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
810 /// load into the specified FoldInst. Note that we could have a sequence where
811 /// multiple LLVM IR instructions are folded into the same machineinstr. For
812 /// example we could have:
813 /// A: x = load i32 *P
814 /// B: y = icmp A, 42
817 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
818 /// any other folded instructions) because it is between A and C.
820 /// If we succeed in folding the load into the operation, return true.
822 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
823 const Instruction *FoldInst,
825 // We know that the load has a single use, but don't know what it is. If it
826 // isn't one of the folded instructions, then we can't succeed here. Handle
827 // this by scanning the single-use users of the load until we get to FoldInst.
828 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
830 const Instruction *TheUser = LI->use_back();
831 while (TheUser != FoldInst && // Scan up until we find FoldInst.
832 // Stay in the right block.
833 TheUser->getParent() == FoldInst->getParent() &&
834 --MaxUsers) { // Don't scan too far.
835 // If there are multiple or no uses of this instruction, then bail out.
836 if (!TheUser->hasOneUse())
839 TheUser = TheUser->use_back();
842 // If we didn't find the fold instruction, then we failed to collapse the
844 if (TheUser != FoldInst)
847 // Don't try to fold volatile loads. Target has to deal with alignment
849 if (LI->isVolatile()) return false;
851 // Figure out which vreg this is going into. If there is no assigned vreg yet
852 // then there actually was no reference to it. Perhaps the load is referenced
853 // by a dead instruction.
854 unsigned LoadReg = FastIS->getRegForValue(LI);
858 // Check to see what the uses of this vreg are. If it has no uses, or more
859 // than one use (at the machine instr level) then we can't fold it.
860 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
861 if (RI == RegInfo->reg_end())
864 // See if there is exactly one use of the vreg. If there are multiple uses,
865 // then the instruction got lowered to multiple machine instructions or the
866 // use of the loaded value ended up being multiple operands of the result, in
867 // either case, we can't fold this.
868 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
869 if (PostRI != RegInfo->reg_end())
872 assert(RI.getOperand().isUse() &&
873 "The only use of the vreg must be a use, we haven't emitted the def!");
875 MachineInstr *User = &*RI;
877 // Set the insertion point properly. Folding the load can cause generation of
878 // other random instructions (like sign extends) for addressing modes, make
879 // sure they get inserted in a logical place before the new instruction.
880 FuncInfo->InsertPt = User;
881 FuncInfo->MBB = User->getParent();
883 // Ask the target to try folding the load.
884 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
887 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
888 /// side-effect free and is either dead or folded into a generated instruction.
889 /// Return false if it needs to be emitted.
890 static bool isFoldedOrDeadInstruction(const Instruction *I,
891 FunctionLoweringInfo *FuncInfo) {
892 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
893 !isa<TerminatorInst>(I) && // Terminators aren't folded.
894 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
895 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
896 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
900 // Collect per Instruction statistics for fast-isel misses. Only those
901 // instructions that cause the bail are accounted for. It does not account for
902 // instructions higher in the block. Thus, summing the per instructions stats
903 // will not add up to what is reported by NumFastIselFailures.
904 static void collectFailStats(const Instruction *I) {
905 switch (I->getOpcode()) {
906 default: assert (0 && "<Invalid operator> ");
909 case Instruction::Ret: NumFastIselFailRet++; return;
910 case Instruction::Br: NumFastIselFailBr++; return;
911 case Instruction::Switch: NumFastIselFailSwitch++; return;
912 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
913 case Instruction::Invoke: NumFastIselFailInvoke++; return;
914 case Instruction::Resume: NumFastIselFailResume++; return;
915 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
917 // Standard binary operators...
918 case Instruction::Add: NumFastIselFailAdd++; return;
919 case Instruction::FAdd: NumFastIselFailFAdd++; return;
920 case Instruction::Sub: NumFastIselFailSub++; return;
921 case Instruction::FSub: NumFastIselFailFSub++; return;
922 case Instruction::Mul: NumFastIselFailMul++; return;
923 case Instruction::FMul: NumFastIselFailFMul++; return;
924 case Instruction::UDiv: NumFastIselFailUDiv++; return;
925 case Instruction::SDiv: NumFastIselFailSDiv++; return;
926 case Instruction::FDiv: NumFastIselFailFDiv++; return;
927 case Instruction::URem: NumFastIselFailURem++; return;
928 case Instruction::SRem: NumFastIselFailSRem++; return;
929 case Instruction::FRem: NumFastIselFailFRem++; return;
931 // Logical operators...
932 case Instruction::And: NumFastIselFailAnd++; return;
933 case Instruction::Or: NumFastIselFailOr++; return;
934 case Instruction::Xor: NumFastIselFailXor++; return;
936 // Memory instructions...
937 case Instruction::Alloca: NumFastIselFailAlloca++; return;
938 case Instruction::Load: NumFastIselFailLoad++; return;
939 case Instruction::Store: NumFastIselFailStore++; return;
940 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
941 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
942 case Instruction::Fence: NumFastIselFailFence++; return;
943 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
945 // Convert instructions...
946 case Instruction::Trunc: NumFastIselFailTrunc++; return;
947 case Instruction::ZExt: NumFastIselFailZExt++; return;
948 case Instruction::SExt: NumFastIselFailSExt++; return;
949 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
950 case Instruction::FPExt: NumFastIselFailFPExt++; return;
951 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
952 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
953 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
954 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
955 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
956 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
957 case Instruction::BitCast: NumFastIselFailBitCast++; return;
959 // Other instructions...
960 case Instruction::ICmp: NumFastIselFailICmp++; return;
961 case Instruction::FCmp: NumFastIselFailFCmp++; return;
962 case Instruction::PHI: NumFastIselFailPHI++; return;
963 case Instruction::Select: NumFastIselFailSelect++; return;
964 case Instruction::Call: NumFastIselFailCall++; return;
965 case Instruction::Shl: NumFastIselFailShl++; return;
966 case Instruction::LShr: NumFastIselFailLShr++; return;
967 case Instruction::AShr: NumFastIselFailAShr++; return;
968 case Instruction::VAArg: NumFastIselFailVAArg++; return;
969 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
970 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
971 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
972 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
973 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
974 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
979 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
980 // Initialize the Fast-ISel state, if needed.
981 FastISel *FastIS = 0;
982 if (TM.Options.EnableFastISel)
983 FastIS = TLI.createFastISel(*FuncInfo);
985 // Iterate over all basic blocks in the function.
986 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
987 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
988 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
989 const BasicBlock *LLVMBB = *I;
991 if (OptLevel != CodeGenOpt::None) {
992 bool AllPredsVisited = true;
993 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
995 if (!FuncInfo->VisitedBBs.count(*PI)) {
996 AllPredsVisited = false;
1001 if (AllPredsVisited) {
1002 for (BasicBlock::const_iterator I = LLVMBB->begin();
1003 isa<PHINode>(I); ++I)
1004 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
1006 for (BasicBlock::const_iterator I = LLVMBB->begin();
1007 isa<PHINode>(I); ++I)
1008 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
1011 FuncInfo->VisitedBBs.insert(LLVMBB);
1014 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1015 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1017 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1018 BasicBlock::const_iterator const End = LLVMBB->end();
1019 BasicBlock::const_iterator BI = End;
1021 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1023 // Setup an EH landing-pad block.
1024 if (FuncInfo->MBB->isLandingPad())
1025 PrepareEHLandingPad();
1027 // Lower any arguments needed in this block if this is the entry block.
1028 if (LLVMBB == &Fn.getEntryBlock())
1029 LowerArguments(LLVMBB);
1031 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1033 FastIS->startNewBlock();
1035 // Emit code for any incoming arguments. This must happen before
1036 // beginning FastISel on the entry block.
1037 if (LLVMBB == &Fn.getEntryBlock()) {
1038 CurDAG->setRoot(SDB->getControlRoot());
1040 CodeGenAndEmitDAG();
1042 // If we inserted any instructions at the beginning, make a note of
1043 // where they are, so we can be sure to emit subsequent instructions
1045 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1046 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1048 FastIS->setLastLocalValue(0);
1051 unsigned NumFastIselRemaining = std::distance(Begin, End);
1052 // Do FastISel on as many instructions as possible.
1053 for (; BI != Begin; --BI) {
1054 const Instruction *Inst = llvm::prior(BI);
1056 // If we no longer require this instruction, skip it.
1057 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1058 --NumFastIselRemaining;
1062 // Bottom-up: reset the insert pos at the top, after any local-value
1064 FastIS->recomputeInsertPt();
1066 // Try to select the instruction with FastISel.
1067 if (FastIS->SelectInstruction(Inst)) {
1068 --NumFastIselRemaining;
1069 ++NumFastIselSuccess;
1070 // If fast isel succeeded, skip over all the folded instructions, and
1071 // then see if there is a load right before the selected instructions.
1072 // Try to fold the load if so.
1073 const Instruction *BeforeInst = Inst;
1074 while (BeforeInst != Begin) {
1075 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1076 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1079 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1080 BeforeInst->hasOneUse() &&
1081 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1082 // If we succeeded, don't re-select the load.
1083 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1084 --NumFastIselRemaining;
1085 ++NumFastIselSuccess;
1091 if (EnableFastISelVerbose2)
1092 collectFailStats(Inst);
1095 // Then handle certain instructions as single-LLVM-Instruction blocks.
1096 if (isa<CallInst>(Inst)) {
1098 if (EnableFastISelVerbose || EnableFastISelAbort) {
1099 dbgs() << "FastISel missed call: ";
1103 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1104 unsigned &R = FuncInfo->ValueMap[Inst];
1106 R = FuncInfo->CreateRegs(Inst->getType());
1109 bool HadTailCall = false;
1110 SelectBasicBlock(Inst, BI, HadTailCall);
1112 // Recompute NumFastIselRemaining as Selection DAG instruction
1113 // selection may have handled the call, input args, etc.
1114 unsigned RemainingNow = std::distance(Begin, BI);
1115 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1117 // If the call was emitted as a tail call, we're done with the block.
1123 NumFastIselRemaining = RemainingNow;
1127 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1128 // Don't abort, and use a different message for terminator misses.
1129 NumFastIselFailures += NumFastIselRemaining;
1130 if (EnableFastISelVerbose || EnableFastISelAbort) {
1131 dbgs() << "FastISel missed terminator: ";
1135 NumFastIselFailures += NumFastIselRemaining;
1136 if (EnableFastISelVerbose || EnableFastISelAbort) {
1137 dbgs() << "FastISel miss: ";
1140 if (EnableFastISelAbort)
1141 // The "fast" selector couldn't handle something and bailed.
1142 // For the purpose of debugging, just abort.
1143 llvm_unreachable("FastISel didn't select the entire block");
1148 FastIS->recomputeInsertPt();
1154 ++NumFastIselBlocks;
1157 // Run SelectionDAG instruction selection on the remainder of the block
1158 // not handled by FastISel. If FastISel is not run, this is the entire
1161 SelectBasicBlock(Begin, BI, HadTailCall);
1165 FuncInfo->PHINodesToUpdate.clear();
1169 SDB->clearDanglingDebugInfo();
1173 SelectionDAGISel::FinishBasicBlock() {
1175 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1176 << FuncInfo->PHINodesToUpdate.size() << "\n";
1177 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1178 dbgs() << "Node " << i << " : ("
1179 << FuncInfo->PHINodesToUpdate[i].first
1180 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1182 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1183 // PHI nodes in successors.
1184 if (SDB->SwitchCases.empty() &&
1185 SDB->JTCases.empty() &&
1186 SDB->BitTestCases.empty()) {
1187 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1188 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1189 assert(PHI->isPHI() &&
1190 "This is not a machine PHI node that we are updating!");
1191 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1194 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1195 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1200 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1201 // Lower header first, if it wasn't already lowered
1202 if (!SDB->BitTestCases[i].Emitted) {
1203 // Set the current basic block to the mbb we wish to insert the code into
1204 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1205 FuncInfo->InsertPt = FuncInfo->MBB->end();
1207 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1208 CurDAG->setRoot(SDB->getRoot());
1210 CodeGenAndEmitDAG();
1213 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1214 // Set the current basic block to the mbb we wish to insert the code into
1215 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1216 FuncInfo->InsertPt = FuncInfo->MBB->end();
1219 SDB->visitBitTestCase(SDB->BitTestCases[i],
1220 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1221 SDB->BitTestCases[i].Reg,
1222 SDB->BitTestCases[i].Cases[j],
1225 SDB->visitBitTestCase(SDB->BitTestCases[i],
1226 SDB->BitTestCases[i].Default,
1227 SDB->BitTestCases[i].Reg,
1228 SDB->BitTestCases[i].Cases[j],
1232 CurDAG->setRoot(SDB->getRoot());
1234 CodeGenAndEmitDAG();
1238 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1240 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1241 MachineBasicBlock *PHIBB = PHI->getParent();
1242 assert(PHI->isPHI() &&
1243 "This is not a machine PHI node that we are updating!");
1244 // This is "default" BB. We have two jumps to it. From "header" BB and
1245 // from last "case" BB.
1246 if (PHIBB == SDB->BitTestCases[i].Default) {
1247 PHI->addOperand(MachineOperand::
1248 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1250 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1251 PHI->addOperand(MachineOperand::
1252 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1254 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1257 // One of "cases" BB.
1258 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1260 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1261 if (cBB->isSuccessor(PHIBB)) {
1262 PHI->addOperand(MachineOperand::
1263 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1265 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1270 SDB->BitTestCases.clear();
1272 // If the JumpTable record is filled in, then we need to emit a jump table.
1273 // Updating the PHI nodes is tricky in this case, since we need to determine
1274 // whether the PHI is a successor of the range check MBB or the jump table MBB
1275 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1276 // Lower header first, if it wasn't already lowered
1277 if (!SDB->JTCases[i].first.Emitted) {
1278 // Set the current basic block to the mbb we wish to insert the code into
1279 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1280 FuncInfo->InsertPt = FuncInfo->MBB->end();
1282 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1284 CurDAG->setRoot(SDB->getRoot());
1286 CodeGenAndEmitDAG();
1289 // Set the current basic block to the mbb we wish to insert the code into
1290 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1291 FuncInfo->InsertPt = FuncInfo->MBB->end();
1293 SDB->visitJumpTable(SDB->JTCases[i].second);
1294 CurDAG->setRoot(SDB->getRoot());
1296 CodeGenAndEmitDAG();
1299 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1301 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1302 MachineBasicBlock *PHIBB = PHI->getParent();
1303 assert(PHI->isPHI() &&
1304 "This is not a machine PHI node that we are updating!");
1305 // "default" BB. We can go there only from header BB.
1306 if (PHIBB == SDB->JTCases[i].second.Default) {
1308 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1311 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1313 // JT BB. Just iterate over successors here
1314 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1316 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1318 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1322 SDB->JTCases.clear();
1324 // If the switch block involved a branch to one of the actual successors, we
1325 // need to update PHI nodes in that block.
1326 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1327 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1328 assert(PHI->isPHI() &&
1329 "This is not a machine PHI node that we are updating!");
1330 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1332 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1333 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1337 // If we generated any switch lowering information, build and codegen any
1338 // additional DAGs necessary.
1339 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1340 // Set the current basic block to the mbb we wish to insert the code into
1341 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1342 FuncInfo->InsertPt = FuncInfo->MBB->end();
1344 // Determine the unique successors.
1345 SmallVector<MachineBasicBlock *, 2> Succs;
1346 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1347 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1348 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1350 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1351 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1352 CurDAG->setRoot(SDB->getRoot());
1354 CodeGenAndEmitDAG();
1356 // Remember the last block, now that any splitting is done, for use in
1357 // populating PHI nodes in successors.
1358 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1360 // Handle any PHI nodes in successors of this chunk, as if we were coming
1361 // from the original BB before switch expansion. Note that PHI nodes can
1362 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1363 // handle them the right number of times.
1364 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1365 FuncInfo->MBB = Succs[i];
1366 FuncInfo->InsertPt = FuncInfo->MBB->end();
1367 // FuncInfo->MBB may have been removed from the CFG if a branch was
1369 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1370 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1371 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1373 // This value for this PHI node is recorded in PHINodesToUpdate.
1374 for (unsigned pn = 0; ; ++pn) {
1375 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1376 "Didn't find PHI entry!");
1377 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1378 Phi->addOperand(MachineOperand::
1379 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1381 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1389 SDB->SwitchCases.clear();
1393 /// Create the scheduler. If a specific scheduler was specified
1394 /// via the SchedulerRegistry, use it, otherwise select the
1395 /// one preferred by the target.
1397 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1398 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1402 RegisterScheduler::setDefault(Ctor);
1405 return Ctor(this, OptLevel);
1408 //===----------------------------------------------------------------------===//
1409 // Helper functions used by the generated instruction selector.
1410 //===----------------------------------------------------------------------===//
1411 // Calls to these methods are generated by tblgen.
1413 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1414 /// the dag combiner simplified the 255, we still want to match. RHS is the
1415 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1416 /// specified in the .td file (e.g. 255).
1417 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1418 int64_t DesiredMaskS) const {
1419 const APInt &ActualMask = RHS->getAPIntValue();
1420 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1422 // If the actual mask exactly matches, success!
1423 if (ActualMask == DesiredMask)
1426 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1427 if (ActualMask.intersects(~DesiredMask))
1430 // Otherwise, the DAG Combiner may have proven that the value coming in is
1431 // either already zero or is not demanded. Check for known zero input bits.
1432 APInt NeededMask = DesiredMask & ~ActualMask;
1433 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1436 // TODO: check to see if missing bits are just not demanded.
1438 // Otherwise, this pattern doesn't match.
1442 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1443 /// the dag combiner simplified the 255, we still want to match. RHS is the
1444 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1445 /// specified in the .td file (e.g. 255).
1446 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1447 int64_t DesiredMaskS) const {
1448 const APInt &ActualMask = RHS->getAPIntValue();
1449 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1451 // If the actual mask exactly matches, success!
1452 if (ActualMask == DesiredMask)
1455 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1456 if (ActualMask.intersects(~DesiredMask))
1459 // Otherwise, the DAG Combiner may have proven that the value coming in is
1460 // either already zero or is not demanded. Check for known zero input bits.
1461 APInt NeededMask = DesiredMask & ~ActualMask;
1463 APInt KnownZero, KnownOne;
1464 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1466 // If all the missing bits in the or are already known to be set, match!
1467 if ((NeededMask & KnownOne) == NeededMask)
1470 // TODO: check to see if missing bits are just not demanded.
1472 // Otherwise, this pattern doesn't match.
1477 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1478 /// by tblgen. Others should not call it.
1479 void SelectionDAGISel::
1480 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1481 std::vector<SDValue> InOps;
1482 std::swap(InOps, Ops);
1484 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1485 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1486 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1487 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1489 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1490 if (InOps[e-1].getValueType() == MVT::Glue)
1491 --e; // Don't process a glue operand if it is here.
1494 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1495 if (!InlineAsm::isMemKind(Flags)) {
1496 // Just skip over this operand, copying the operands verbatim.
1497 Ops.insert(Ops.end(), InOps.begin()+i,
1498 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1499 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1501 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1502 "Memory operand with multiple values?");
1503 // Otherwise, this is a memory operand. Ask the target to select it.
1504 std::vector<SDValue> SelOps;
1505 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1506 report_fatal_error("Could not match memory address. Inline asm"
1509 // Add this to the output node.
1511 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1512 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1513 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1518 // Add the glue input back if present.
1519 if (e != InOps.size())
1520 Ops.push_back(InOps.back());
1523 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1526 static SDNode *findGlueUse(SDNode *N) {
1527 unsigned FlagResNo = N->getNumValues()-1;
1528 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1529 SDUse &Use = I.getUse();
1530 if (Use.getResNo() == FlagResNo)
1531 return Use.getUser();
1536 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1537 /// This function recursively traverses up the operand chain, ignoring
1539 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1540 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1541 bool IgnoreChains) {
1542 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1543 // greater than all of its (recursive) operands. If we scan to a point where
1544 // 'use' is smaller than the node we're scanning for, then we know we will
1547 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1548 // happen because we scan down to newly selected nodes in the case of glue
1550 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1553 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1554 // won't fail if we scan it again.
1555 if (!Visited.insert(Use))
1558 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1559 // Ignore chain uses, they are validated by HandleMergeInputChains.
1560 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1563 SDNode *N = Use->getOperand(i).getNode();
1565 if (Use == ImmedUse || Use == Root)
1566 continue; // We are not looking for immediate use.
1571 // Traverse up the operand chain.
1572 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1578 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1579 /// operand node N of U during instruction selection that starts at Root.
1580 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1581 SDNode *Root) const {
1582 if (OptLevel == CodeGenOpt::None) return false;
1583 return N.hasOneUse();
1586 /// IsLegalToFold - Returns true if the specific operand node N of
1587 /// U can be folded during instruction selection that starts at Root.
1588 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1589 CodeGenOpt::Level OptLevel,
1590 bool IgnoreChains) {
1591 if (OptLevel == CodeGenOpt::None) return false;
1593 // If Root use can somehow reach N through a path that that doesn't contain
1594 // U then folding N would create a cycle. e.g. In the following
1595 // diagram, Root can reach N through X. If N is folded into into Root, then
1596 // X is both a predecessor and a successor of U.
1607 // * indicates nodes to be folded together.
1609 // If Root produces glue, then it gets (even more) interesting. Since it
1610 // will be "glued" together with its glue use in the scheduler, we need to
1611 // check if it might reach N.
1630 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1631 // (call it Fold), then X is a predecessor of GU and a successor of
1632 // Fold. But since Fold and GU are glued together, this will create
1633 // a cycle in the scheduling graph.
1635 // If the node has glue, walk down the graph to the "lowest" node in the
1637 EVT VT = Root->getValueType(Root->getNumValues()-1);
1638 while (VT == MVT::Glue) {
1639 SDNode *GU = findGlueUse(Root);
1643 VT = Root->getValueType(Root->getNumValues()-1);
1645 // If our query node has a glue result with a use, we've walked up it. If
1646 // the user (which has already been selected) has a chain or indirectly uses
1647 // the chain, our WalkChainUsers predicate will not consider it. Because of
1648 // this, we cannot ignore chains in this predicate.
1649 IgnoreChains = false;
1653 SmallPtrSet<SDNode*, 16> Visited;
1654 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1657 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1658 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1659 SelectInlineAsmMemoryOperands(Ops);
1661 std::vector<EVT> VTs;
1662 VTs.push_back(MVT::Other);
1663 VTs.push_back(MVT::Glue);
1664 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1665 VTs, &Ops[0], Ops.size());
1667 return New.getNode();
1670 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1671 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1674 /// GetVBR - decode a vbr encoding whose top bit is set.
1675 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1676 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1677 assert(Val >= 128 && "Not a VBR");
1678 Val &= 127; // Remove first vbr bit.
1683 NextBits = MatcherTable[Idx++];
1684 Val |= (NextBits&127) << Shift;
1686 } while (NextBits & 128);
1692 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1693 /// interior glue and chain results to use the new glue and chain results.
1694 void SelectionDAGISel::
1695 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1696 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1698 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1699 bool isMorphNodeTo) {
1700 SmallVector<SDNode*, 4> NowDeadNodes;
1702 // Now that all the normal results are replaced, we replace the chain and
1703 // glue results if present.
1704 if (!ChainNodesMatched.empty()) {
1705 assert(InputChain.getNode() != 0 &&
1706 "Matched input chains but didn't produce a chain");
1707 // Loop over all of the nodes we matched that produced a chain result.
1708 // Replace all the chain results with the final chain we ended up with.
1709 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1710 SDNode *ChainNode = ChainNodesMatched[i];
1712 // If this node was already deleted, don't look at it.
1713 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1716 // Don't replace the results of the root node if we're doing a
1718 if (ChainNode == NodeToMatch && isMorphNodeTo)
1721 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1722 if (ChainVal.getValueType() == MVT::Glue)
1723 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1724 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1725 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1727 // If the node became dead and we haven't already seen it, delete it.
1728 if (ChainNode->use_empty() &&
1729 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1730 NowDeadNodes.push_back(ChainNode);
1734 // If the result produces glue, update any glue results in the matched
1735 // pattern with the glue result.
1736 if (InputGlue.getNode() != 0) {
1737 // Handle any interior nodes explicitly marked.
1738 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1739 SDNode *FRN = GlueResultNodesMatched[i];
1741 // If this node was already deleted, don't look at it.
1742 if (FRN->getOpcode() == ISD::DELETED_NODE)
1745 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1746 "Doesn't have a glue result");
1747 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1750 // If the node became dead and we haven't already seen it, delete it.
1751 if (FRN->use_empty() &&
1752 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1753 NowDeadNodes.push_back(FRN);
1757 if (!NowDeadNodes.empty())
1758 CurDAG->RemoveDeadNodes(NowDeadNodes);
1760 DEBUG(errs() << "ISEL: Match complete!\n");
1766 CR_LeadsToInteriorNode
1769 /// WalkChainUsers - Walk down the users of the specified chained node that is
1770 /// part of the pattern we're matching, looking at all of the users we find.
1771 /// This determines whether something is an interior node, whether we have a
1772 /// non-pattern node in between two pattern nodes (which prevent folding because
1773 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1774 /// between pattern nodes (in which case the TF becomes part of the pattern).
1776 /// The walk we do here is guaranteed to be small because we quickly get down to
1777 /// already selected nodes "below" us.
1779 WalkChainUsers(SDNode *ChainedNode,
1780 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1781 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1782 ChainResult Result = CR_Simple;
1784 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1785 E = ChainedNode->use_end(); UI != E; ++UI) {
1786 // Make sure the use is of the chain, not some other value we produce.
1787 if (UI.getUse().getValueType() != MVT::Other) continue;
1791 // If we see an already-selected machine node, then we've gone beyond the
1792 // pattern that we're selecting down into the already selected chunk of the
1794 if (User->isMachineOpcode() ||
1795 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1798 if (User->getOpcode() == ISD::CopyToReg ||
1799 User->getOpcode() == ISD::CopyFromReg ||
1800 User->getOpcode() == ISD::INLINEASM ||
1801 User->getOpcode() == ISD::EH_LABEL) {
1802 // If their node ID got reset to -1 then they've already been selected.
1803 // Treat them like a MachineOpcode.
1804 if (User->getNodeId() == -1)
1808 // If we have a TokenFactor, we handle it specially.
1809 if (User->getOpcode() != ISD::TokenFactor) {
1810 // If the node isn't a token factor and isn't part of our pattern, then it
1811 // must be a random chained node in between two nodes we're selecting.
1812 // This happens when we have something like:
1817 // Because we structurally match the load/store as a read/modify/write,
1818 // but the call is chained between them. We cannot fold in this case
1819 // because it would induce a cycle in the graph.
1820 if (!std::count(ChainedNodesInPattern.begin(),
1821 ChainedNodesInPattern.end(), User))
1822 return CR_InducesCycle;
1824 // Otherwise we found a node that is part of our pattern. For example in:
1828 // This would happen when we're scanning down from the load and see the
1829 // store as a user. Record that there is a use of ChainedNode that is
1830 // part of the pattern and keep scanning uses.
1831 Result = CR_LeadsToInteriorNode;
1832 InteriorChainedNodes.push_back(User);
1836 // If we found a TokenFactor, there are two cases to consider: first if the
1837 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1838 // uses of the TF are in our pattern) we just want to ignore it. Second,
1839 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1845 // | \ DAG's like cheese
1848 // [TokenFactor] [Op]
1855 // In this case, the TokenFactor becomes part of our match and we rewrite it
1856 // as a new TokenFactor.
1858 // To distinguish these two cases, do a recursive walk down the uses.
1859 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1861 // If the uses of the TokenFactor are just already-selected nodes, ignore
1862 // it, it is "below" our pattern.
1864 case CR_InducesCycle:
1865 // If the uses of the TokenFactor lead to nodes that are not part of our
1866 // pattern that are not selected, folding would turn this into a cycle,
1868 return CR_InducesCycle;
1869 case CR_LeadsToInteriorNode:
1870 break; // Otherwise, keep processing.
1873 // Okay, we know we're in the interesting interior case. The TokenFactor
1874 // is now going to be considered part of the pattern so that we rewrite its
1875 // uses (it may have uses that are not part of the pattern) with the
1876 // ultimate chain result of the generated code. We will also add its chain
1877 // inputs as inputs to the ultimate TokenFactor we create.
1878 Result = CR_LeadsToInteriorNode;
1879 ChainedNodesInPattern.push_back(User);
1880 InteriorChainedNodes.push_back(User);
1887 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1888 /// operation for when the pattern matched at least one node with a chains. The
1889 /// input vector contains a list of all of the chained nodes that we match. We
1890 /// must determine if this is a valid thing to cover (i.e. matching it won't
1891 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1892 /// be used as the input node chain for the generated nodes.
1894 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1895 SelectionDAG *CurDAG) {
1896 // Walk all of the chained nodes we've matched, recursively scanning down the
1897 // users of the chain result. This adds any TokenFactor nodes that are caught
1898 // in between chained nodes to the chained and interior nodes list.
1899 SmallVector<SDNode*, 3> InteriorChainedNodes;
1900 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1901 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1902 InteriorChainedNodes) == CR_InducesCycle)
1903 return SDValue(); // Would induce a cycle.
1906 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1907 // that we are interested in. Form our input TokenFactor node.
1908 SmallVector<SDValue, 3> InputChains;
1909 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1910 // Add the input chain of this node to the InputChains list (which will be
1911 // the operands of the generated TokenFactor) if it's not an interior node.
1912 SDNode *N = ChainNodesMatched[i];
1913 if (N->getOpcode() != ISD::TokenFactor) {
1914 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1917 // Otherwise, add the input chain.
1918 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1919 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1920 InputChains.push_back(InChain);
1924 // If we have a token factor, we want to add all inputs of the token factor
1925 // that are not part of the pattern we're matching.
1926 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1927 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1928 N->getOperand(op).getNode()))
1929 InputChains.push_back(N->getOperand(op));
1934 if (InputChains.size() == 1)
1935 return InputChains[0];
1936 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1937 MVT::Other, &InputChains[0], InputChains.size());
1940 /// MorphNode - Handle morphing a node in place for the selector.
1941 SDNode *SelectionDAGISel::
1942 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1943 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1944 // It is possible we're using MorphNodeTo to replace a node with no
1945 // normal results with one that has a normal result (or we could be
1946 // adding a chain) and the input could have glue and chains as well.
1947 // In this case we need to shift the operands down.
1948 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1949 // than the old isel though.
1950 int OldGlueResultNo = -1, OldChainResultNo = -1;
1952 unsigned NTMNumResults = Node->getNumValues();
1953 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1954 OldGlueResultNo = NTMNumResults-1;
1955 if (NTMNumResults != 1 &&
1956 Node->getValueType(NTMNumResults-2) == MVT::Other)
1957 OldChainResultNo = NTMNumResults-2;
1958 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1959 OldChainResultNo = NTMNumResults-1;
1961 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1962 // that this deletes operands of the old node that become dead.
1963 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1965 // MorphNodeTo can operate in two ways: if an existing node with the
1966 // specified operands exists, it can just return it. Otherwise, it
1967 // updates the node in place to have the requested operands.
1969 // If we updated the node in place, reset the node ID. To the isel,
1970 // this should be just like a newly allocated machine node.
1974 unsigned ResNumResults = Res->getNumValues();
1975 // Move the glue if needed.
1976 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1977 (unsigned)OldGlueResultNo != ResNumResults-1)
1978 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1979 SDValue(Res, ResNumResults-1));
1981 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1984 // Move the chain reference if needed.
1985 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1986 (unsigned)OldChainResultNo != ResNumResults-1)
1987 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1988 SDValue(Res, ResNumResults-1));
1990 // Otherwise, no replacement happened because the node already exists. Replace
1991 // Uses of the old node with the new one.
1993 CurDAG->ReplaceAllUsesWith(Node, Res);
1998 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1999 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2000 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2002 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2003 // Accept if it is exactly the same as a previously recorded node.
2004 unsigned RecNo = MatcherTable[MatcherIndex++];
2005 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2006 return N == RecordedNodes[RecNo].first;
2009 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2010 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2011 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2012 SelectionDAGISel &SDISel) {
2013 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2016 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2017 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2018 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2019 SelectionDAGISel &SDISel, SDNode *N) {
2020 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2023 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2024 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2026 uint16_t Opc = MatcherTable[MatcherIndex++];
2027 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2028 return N->getOpcode() == Opc;
2031 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2032 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2033 SDValue N, const TargetLowering &TLI) {
2034 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2035 if (N.getValueType() == VT) return true;
2037 // Handle the case when VT is iPTR.
2038 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2041 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2042 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2043 SDValue N, const TargetLowering &TLI,
2045 if (ChildNo >= N.getNumOperands())
2046 return false; // Match fails if out of range child #.
2047 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2051 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2052 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2054 return cast<CondCodeSDNode>(N)->get() ==
2055 (ISD::CondCode)MatcherTable[MatcherIndex++];
2058 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2059 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2060 SDValue N, const TargetLowering &TLI) {
2061 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2062 if (cast<VTSDNode>(N)->getVT() == VT)
2065 // Handle the case when VT is iPTR.
2066 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2069 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2070 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2072 int64_t Val = MatcherTable[MatcherIndex++];
2074 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2076 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2077 return C != 0 && C->getSExtValue() == Val;
2080 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2081 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2082 SDValue N, SelectionDAGISel &SDISel) {
2083 int64_t Val = MatcherTable[MatcherIndex++];
2085 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2087 if (N->getOpcode() != ISD::AND) return false;
2089 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2090 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2093 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2094 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2095 SDValue N, SelectionDAGISel &SDISel) {
2096 int64_t Val = MatcherTable[MatcherIndex++];
2098 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2100 if (N->getOpcode() != ISD::OR) return false;
2102 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2103 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2106 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2107 /// scope, evaluate the current node. If the current predicate is known to
2108 /// fail, set Result=true and return anything. If the current predicate is
2109 /// known to pass, set Result=false and return the MatcherIndex to continue
2110 /// with. If the current predicate is unknown, set Result=false and return the
2111 /// MatcherIndex to continue with.
2112 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2113 unsigned Index, SDValue N,
2114 bool &Result, SelectionDAGISel &SDISel,
2115 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2116 switch (Table[Index++]) {
2119 return Index-1; // Could not evaluate this predicate.
2120 case SelectionDAGISel::OPC_CheckSame:
2121 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2123 case SelectionDAGISel::OPC_CheckPatternPredicate:
2124 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2126 case SelectionDAGISel::OPC_CheckPredicate:
2127 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2129 case SelectionDAGISel::OPC_CheckOpcode:
2130 Result = !::CheckOpcode(Table, Index, N.getNode());
2132 case SelectionDAGISel::OPC_CheckType:
2133 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2135 case SelectionDAGISel::OPC_CheckChild0Type:
2136 case SelectionDAGISel::OPC_CheckChild1Type:
2137 case SelectionDAGISel::OPC_CheckChild2Type:
2138 case SelectionDAGISel::OPC_CheckChild3Type:
2139 case SelectionDAGISel::OPC_CheckChild4Type:
2140 case SelectionDAGISel::OPC_CheckChild5Type:
2141 case SelectionDAGISel::OPC_CheckChild6Type:
2142 case SelectionDAGISel::OPC_CheckChild7Type:
2143 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2144 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2146 case SelectionDAGISel::OPC_CheckCondCode:
2147 Result = !::CheckCondCode(Table, Index, N);
2149 case SelectionDAGISel::OPC_CheckValueType:
2150 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2152 case SelectionDAGISel::OPC_CheckInteger:
2153 Result = !::CheckInteger(Table, Index, N);
2155 case SelectionDAGISel::OPC_CheckAndImm:
2156 Result = !::CheckAndImm(Table, Index, N, SDISel);
2158 case SelectionDAGISel::OPC_CheckOrImm:
2159 Result = !::CheckOrImm(Table, Index, N, SDISel);
2167 /// FailIndex - If this match fails, this is the index to continue with.
2170 /// NodeStack - The node stack when the scope was formed.
2171 SmallVector<SDValue, 4> NodeStack;
2173 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2174 unsigned NumRecordedNodes;
2176 /// NumMatchedMemRefs - The number of matched memref entries.
2177 unsigned NumMatchedMemRefs;
2179 /// InputChain/InputGlue - The current chain/glue
2180 SDValue InputChain, InputGlue;
2182 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2183 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2188 SDNode *SelectionDAGISel::
2189 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2190 unsigned TableSize) {
2191 // FIXME: Should these even be selected? Handle these cases in the caller?
2192 switch (NodeToMatch->getOpcode()) {
2195 case ISD::EntryToken: // These nodes remain the same.
2196 case ISD::BasicBlock:
2198 case ISD::RegisterMask:
2199 //case ISD::VALUETYPE:
2200 //case ISD::CONDCODE:
2201 case ISD::HANDLENODE:
2202 case ISD::MDNODE_SDNODE:
2203 case ISD::TargetConstant:
2204 case ISD::TargetConstantFP:
2205 case ISD::TargetConstantPool:
2206 case ISD::TargetFrameIndex:
2207 case ISD::TargetExternalSymbol:
2208 case ISD::TargetBlockAddress:
2209 case ISD::TargetJumpTable:
2210 case ISD::TargetGlobalTLSAddress:
2211 case ISD::TargetGlobalAddress:
2212 case ISD::TokenFactor:
2213 case ISD::CopyFromReg:
2214 case ISD::CopyToReg:
2216 NodeToMatch->setNodeId(-1); // Mark selected.
2218 case ISD::AssertSext:
2219 case ISD::AssertZext:
2220 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2221 NodeToMatch->getOperand(0));
2223 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2224 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2227 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2229 // Set up the node stack with NodeToMatch as the only node on the stack.
2230 SmallVector<SDValue, 8> NodeStack;
2231 SDValue N = SDValue(NodeToMatch, 0);
2232 NodeStack.push_back(N);
2234 // MatchScopes - Scopes used when matching, if a match failure happens, this
2235 // indicates where to continue checking.
2236 SmallVector<MatchScope, 8> MatchScopes;
2238 // RecordedNodes - This is the set of nodes that have been recorded by the
2239 // state machine. The second value is the parent of the node, or null if the
2240 // root is recorded.
2241 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2243 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2245 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2247 // These are the current input chain and glue for use when generating nodes.
2248 // Various Emit operations change these. For example, emitting a copytoreg
2249 // uses and updates these.
2250 SDValue InputChain, InputGlue;
2252 // ChainNodesMatched - If a pattern matches nodes that have input/output
2253 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2254 // which ones they are. The result is captured into this list so that we can
2255 // update the chain results when the pattern is complete.
2256 SmallVector<SDNode*, 3> ChainNodesMatched;
2257 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2259 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2260 NodeToMatch->dump(CurDAG);
2263 // Determine where to start the interpreter. Normally we start at opcode #0,
2264 // but if the state machine starts with an OPC_SwitchOpcode, then we
2265 // accelerate the first lookup (which is guaranteed to be hot) with the
2266 // OpcodeOffset table.
2267 unsigned MatcherIndex = 0;
2269 if (!OpcodeOffset.empty()) {
2270 // Already computed the OpcodeOffset table, just index into it.
2271 if (N.getOpcode() < OpcodeOffset.size())
2272 MatcherIndex = OpcodeOffset[N.getOpcode()];
2273 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2275 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2276 // Otherwise, the table isn't computed, but the state machine does start
2277 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2278 // is the first time we're selecting an instruction.
2281 // Get the size of this case.
2282 unsigned CaseSize = MatcherTable[Idx++];
2284 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2285 if (CaseSize == 0) break;
2287 // Get the opcode, add the index to the table.
2288 uint16_t Opc = MatcherTable[Idx++];
2289 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2290 if (Opc >= OpcodeOffset.size())
2291 OpcodeOffset.resize((Opc+1)*2);
2292 OpcodeOffset[Opc] = Idx;
2296 // Okay, do the lookup for the first opcode.
2297 if (N.getOpcode() < OpcodeOffset.size())
2298 MatcherIndex = OpcodeOffset[N.getOpcode()];
2302 assert(MatcherIndex < TableSize && "Invalid index");
2304 unsigned CurrentOpcodeIndex = MatcherIndex;
2306 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2309 // Okay, the semantics of this operation are that we should push a scope
2310 // then evaluate the first child. However, pushing a scope only to have
2311 // the first check fail (which then pops it) is inefficient. If we can
2312 // determine immediately that the first check (or first several) will
2313 // immediately fail, don't even bother pushing a scope for them.
2317 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2318 if (NumToSkip & 128)
2319 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2320 // Found the end of the scope with no match.
2321 if (NumToSkip == 0) {
2326 FailIndex = MatcherIndex+NumToSkip;
2328 unsigned MatcherIndexOfPredicate = MatcherIndex;
2329 (void)MatcherIndexOfPredicate; // silence warning.
2331 // If we can't evaluate this predicate without pushing a scope (e.g. if
2332 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2333 // push the scope and evaluate the full predicate chain.
2335 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2336 Result, *this, RecordedNodes);
2340 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2341 << "index " << MatcherIndexOfPredicate
2342 << ", continuing at " << FailIndex << "\n");
2343 ++NumDAGIselRetries;
2345 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2346 // move to the next case.
2347 MatcherIndex = FailIndex;
2350 // If the whole scope failed to match, bail.
2351 if (FailIndex == 0) break;
2353 // Push a MatchScope which indicates where to go if the first child fails
2355 MatchScope NewEntry;
2356 NewEntry.FailIndex = FailIndex;
2357 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2358 NewEntry.NumRecordedNodes = RecordedNodes.size();
2359 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2360 NewEntry.InputChain = InputChain;
2361 NewEntry.InputGlue = InputGlue;
2362 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2363 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2364 MatchScopes.push_back(NewEntry);
2367 case OPC_RecordNode: {
2368 // Remember this node, it may end up being an operand in the pattern.
2370 if (NodeStack.size() > 1)
2371 Parent = NodeStack[NodeStack.size()-2].getNode();
2372 RecordedNodes.push_back(std::make_pair(N, Parent));
2376 case OPC_RecordChild0: case OPC_RecordChild1:
2377 case OPC_RecordChild2: case OPC_RecordChild3:
2378 case OPC_RecordChild4: case OPC_RecordChild5:
2379 case OPC_RecordChild6: case OPC_RecordChild7: {
2380 unsigned ChildNo = Opcode-OPC_RecordChild0;
2381 if (ChildNo >= N.getNumOperands())
2382 break; // Match fails if out of range child #.
2384 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2388 case OPC_RecordMemRef:
2389 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2392 case OPC_CaptureGlueInput:
2393 // If the current node has an input glue, capture it in InputGlue.
2394 if (N->getNumOperands() != 0 &&
2395 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2396 InputGlue = N->getOperand(N->getNumOperands()-1);
2399 case OPC_MoveChild: {
2400 unsigned ChildNo = MatcherTable[MatcherIndex++];
2401 if (ChildNo >= N.getNumOperands())
2402 break; // Match fails if out of range child #.
2403 N = N.getOperand(ChildNo);
2404 NodeStack.push_back(N);
2408 case OPC_MoveParent:
2409 // Pop the current node off the NodeStack.
2410 NodeStack.pop_back();
2411 assert(!NodeStack.empty() && "Node stack imbalance!");
2412 N = NodeStack.back();
2416 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2418 case OPC_CheckPatternPredicate:
2419 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2421 case OPC_CheckPredicate:
2422 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2426 case OPC_CheckComplexPat: {
2427 unsigned CPNum = MatcherTable[MatcherIndex++];
2428 unsigned RecNo = MatcherTable[MatcherIndex++];
2429 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2430 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2431 RecordedNodes[RecNo].first, CPNum,
2436 case OPC_CheckOpcode:
2437 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2441 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2444 case OPC_SwitchOpcode: {
2445 unsigned CurNodeOpcode = N.getOpcode();
2446 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2449 // Get the size of this case.
2450 CaseSize = MatcherTable[MatcherIndex++];
2452 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2453 if (CaseSize == 0) break;
2455 uint16_t Opc = MatcherTable[MatcherIndex++];
2456 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2458 // If the opcode matches, then we will execute this case.
2459 if (CurNodeOpcode == Opc)
2462 // Otherwise, skip over this case.
2463 MatcherIndex += CaseSize;
2466 // If no cases matched, bail out.
2467 if (CaseSize == 0) break;
2469 // Otherwise, execute the case we found.
2470 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2471 << " to " << MatcherIndex << "\n");
2475 case OPC_SwitchType: {
2476 MVT CurNodeVT = N.getValueType().getSimpleVT();
2477 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2480 // Get the size of this case.
2481 CaseSize = MatcherTable[MatcherIndex++];
2483 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2484 if (CaseSize == 0) break;
2486 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2487 if (CaseVT == MVT::iPTR)
2488 CaseVT = TLI.getPointerTy();
2490 // If the VT matches, then we will execute this case.
2491 if (CurNodeVT == CaseVT)
2494 // Otherwise, skip over this case.
2495 MatcherIndex += CaseSize;
2498 // If no cases matched, bail out.
2499 if (CaseSize == 0) break;
2501 // Otherwise, execute the case we found.
2502 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2503 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2506 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2507 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2508 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2509 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2510 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2511 Opcode-OPC_CheckChild0Type))
2514 case OPC_CheckCondCode:
2515 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2517 case OPC_CheckValueType:
2518 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2520 case OPC_CheckInteger:
2521 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2523 case OPC_CheckAndImm:
2524 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2526 case OPC_CheckOrImm:
2527 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2530 case OPC_CheckFoldableChainNode: {
2531 assert(NodeStack.size() != 1 && "No parent node");
2532 // Verify that all intermediate nodes between the root and this one have
2534 bool HasMultipleUses = false;
2535 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2536 if (!NodeStack[i].hasOneUse()) {
2537 HasMultipleUses = true;
2540 if (HasMultipleUses) break;
2542 // Check to see that the target thinks this is profitable to fold and that
2543 // we can fold it without inducing cycles in the graph.
2544 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2546 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2547 NodeToMatch, OptLevel,
2548 true/*We validate our own chains*/))
2553 case OPC_EmitInteger: {
2554 MVT::SimpleValueType VT =
2555 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2556 int64_t Val = MatcherTable[MatcherIndex++];
2558 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2559 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2560 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2563 case OPC_EmitRegister: {
2564 MVT::SimpleValueType VT =
2565 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2566 unsigned RegNo = MatcherTable[MatcherIndex++];
2567 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2568 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2571 case OPC_EmitRegister2: {
2572 // For targets w/ more than 256 register names, the register enum
2573 // values are stored in two bytes in the matcher table (just like
2575 MVT::SimpleValueType VT =
2576 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2577 unsigned RegNo = MatcherTable[MatcherIndex++];
2578 RegNo |= MatcherTable[MatcherIndex++] << 8;
2579 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2580 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2584 case OPC_EmitConvertToTarget: {
2585 // Convert from IMM/FPIMM to target version.
2586 unsigned RecNo = MatcherTable[MatcherIndex++];
2587 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2588 SDValue Imm = RecordedNodes[RecNo].first;
2590 if (Imm->getOpcode() == ISD::Constant) {
2591 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2592 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2593 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2594 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2595 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2598 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2602 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2603 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2604 // These are space-optimized forms of OPC_EmitMergeInputChains.
2605 assert(InputChain.getNode() == 0 &&
2606 "EmitMergeInputChains should be the first chain producing node");
2607 assert(ChainNodesMatched.empty() &&
2608 "Should only have one EmitMergeInputChains per match");
2610 // Read all of the chained nodes.
2611 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2612 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2613 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2615 // FIXME: What if other value results of the node have uses not matched
2617 if (ChainNodesMatched.back() != NodeToMatch &&
2618 !RecordedNodes[RecNo].first.hasOneUse()) {
2619 ChainNodesMatched.clear();
2623 // Merge the input chains if they are not intra-pattern references.
2624 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2626 if (InputChain.getNode() == 0)
2627 break; // Failed to merge.
2631 case OPC_EmitMergeInputChains: {
2632 assert(InputChain.getNode() == 0 &&
2633 "EmitMergeInputChains should be the first chain producing node");
2634 // This node gets a list of nodes we matched in the input that have
2635 // chains. We want to token factor all of the input chains to these nodes
2636 // together. However, if any of the input chains is actually one of the
2637 // nodes matched in this pattern, then we have an intra-match reference.
2638 // Ignore these because the newly token factored chain should not refer to
2640 unsigned NumChains = MatcherTable[MatcherIndex++];
2641 assert(NumChains != 0 && "Can't TF zero chains");
2643 assert(ChainNodesMatched.empty() &&
2644 "Should only have one EmitMergeInputChains per match");
2646 // Read all of the chained nodes.
2647 for (unsigned i = 0; i != NumChains; ++i) {
2648 unsigned RecNo = MatcherTable[MatcherIndex++];
2649 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2650 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2652 // FIXME: What if other value results of the node have uses not matched
2654 if (ChainNodesMatched.back() != NodeToMatch &&
2655 !RecordedNodes[RecNo].first.hasOneUse()) {
2656 ChainNodesMatched.clear();
2661 // If the inner loop broke out, the match fails.
2662 if (ChainNodesMatched.empty())
2665 // Merge the input chains if they are not intra-pattern references.
2666 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2668 if (InputChain.getNode() == 0)
2669 break; // Failed to merge.
2674 case OPC_EmitCopyToReg: {
2675 unsigned RecNo = MatcherTable[MatcherIndex++];
2676 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2677 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2679 if (InputChain.getNode() == 0)
2680 InputChain = CurDAG->getEntryNode();
2682 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2683 DestPhysReg, RecordedNodes[RecNo].first,
2686 InputGlue = InputChain.getValue(1);
2690 case OPC_EmitNodeXForm: {
2691 unsigned XFormNo = MatcherTable[MatcherIndex++];
2692 unsigned RecNo = MatcherTable[MatcherIndex++];
2693 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2694 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2695 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2700 case OPC_MorphNodeTo: {
2701 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2702 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2703 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2704 // Get the result VT list.
2705 unsigned NumVTs = MatcherTable[MatcherIndex++];
2706 SmallVector<EVT, 4> VTs;
2707 for (unsigned i = 0; i != NumVTs; ++i) {
2708 MVT::SimpleValueType VT =
2709 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2710 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2714 if (EmitNodeInfo & OPFL_Chain)
2715 VTs.push_back(MVT::Other);
2716 if (EmitNodeInfo & OPFL_GlueOutput)
2717 VTs.push_back(MVT::Glue);
2719 // This is hot code, so optimize the two most common cases of 1 and 2
2722 if (VTs.size() == 1)
2723 VTList = CurDAG->getVTList(VTs[0]);
2724 else if (VTs.size() == 2)
2725 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2727 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2729 // Get the operand list.
2730 unsigned NumOps = MatcherTable[MatcherIndex++];
2731 SmallVector<SDValue, 8> Ops;
2732 for (unsigned i = 0; i != NumOps; ++i) {
2733 unsigned RecNo = MatcherTable[MatcherIndex++];
2735 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2737 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2738 Ops.push_back(RecordedNodes[RecNo].first);
2741 // If there are variadic operands to add, handle them now.
2742 if (EmitNodeInfo & OPFL_VariadicInfo) {
2743 // Determine the start index to copy from.
2744 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2745 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2746 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2747 "Invalid variadic node");
2748 // Copy all of the variadic operands, not including a potential glue
2750 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2752 SDValue V = NodeToMatch->getOperand(i);
2753 if (V.getValueType() == MVT::Glue) break;
2758 // If this has chain/glue inputs, add them.
2759 if (EmitNodeInfo & OPFL_Chain)
2760 Ops.push_back(InputChain);
2761 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2762 Ops.push_back(InputGlue);
2766 if (Opcode != OPC_MorphNodeTo) {
2767 // If this is a normal EmitNode command, just create the new node and
2768 // add the results to the RecordedNodes list.
2769 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2770 VTList, Ops.data(), Ops.size());
2772 // Add all the non-glue/non-chain results to the RecordedNodes list.
2773 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2774 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2775 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2780 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2784 // If the node had chain/glue results, update our notion of the current
2786 if (EmitNodeInfo & OPFL_GlueOutput) {
2787 InputGlue = SDValue(Res, VTs.size()-1);
2788 if (EmitNodeInfo & OPFL_Chain)
2789 InputChain = SDValue(Res, VTs.size()-2);
2790 } else if (EmitNodeInfo & OPFL_Chain)
2791 InputChain = SDValue(Res, VTs.size()-1);
2793 // If the OPFL_MemRefs glue is set on this node, slap all of the
2794 // accumulated memrefs onto it.
2796 // FIXME: This is vastly incorrect for patterns with multiple outputs
2797 // instructions that access memory and for ComplexPatterns that match
2799 if (EmitNodeInfo & OPFL_MemRefs) {
2800 // Only attach load or store memory operands if the generated
2801 // instruction may load or store.
2802 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2803 bool mayLoad = MCID.mayLoad();
2804 bool mayStore = MCID.mayStore();
2806 unsigned NumMemRefs = 0;
2807 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2808 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2809 if ((*I)->isLoad()) {
2812 } else if ((*I)->isStore()) {
2820 MachineSDNode::mmo_iterator MemRefs =
2821 MF->allocateMemRefsArray(NumMemRefs);
2823 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2824 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2825 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2826 if ((*I)->isLoad()) {
2829 } else if ((*I)->isStore()) {
2837 cast<MachineSDNode>(Res)
2838 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2842 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2843 << " node: "; Res->dump(CurDAG); errs() << "\n");
2845 // If this was a MorphNodeTo then we're completely done!
2846 if (Opcode == OPC_MorphNodeTo) {
2847 // Update chain and glue uses.
2848 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2849 InputGlue, GlueResultNodesMatched, true);
2856 case OPC_MarkGlueResults: {
2857 unsigned NumNodes = MatcherTable[MatcherIndex++];
2859 // Read and remember all the glue-result nodes.
2860 for (unsigned i = 0; i != NumNodes; ++i) {
2861 unsigned RecNo = MatcherTable[MatcherIndex++];
2863 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2865 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2866 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2871 case OPC_CompleteMatch: {
2872 // The match has been completed, and any new nodes (if any) have been
2873 // created. Patch up references to the matched dag to use the newly
2875 unsigned NumResults = MatcherTable[MatcherIndex++];
2877 for (unsigned i = 0; i != NumResults; ++i) {
2878 unsigned ResSlot = MatcherTable[MatcherIndex++];
2880 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2882 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2883 SDValue Res = RecordedNodes[ResSlot].first;
2885 assert(i < NodeToMatch->getNumValues() &&
2886 NodeToMatch->getValueType(i) != MVT::Other &&
2887 NodeToMatch->getValueType(i) != MVT::Glue &&
2888 "Invalid number of results to complete!");
2889 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2890 NodeToMatch->getValueType(i) == MVT::iPTR ||
2891 Res.getValueType() == MVT::iPTR ||
2892 NodeToMatch->getValueType(i).getSizeInBits() ==
2893 Res.getValueType().getSizeInBits()) &&
2894 "invalid replacement");
2895 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2898 // If the root node defines glue, add it to the glue nodes to update list.
2899 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2900 GlueResultNodesMatched.push_back(NodeToMatch);
2902 // Update chain and glue uses.
2903 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2904 InputGlue, GlueResultNodesMatched, false);
2906 assert(NodeToMatch->use_empty() &&
2907 "Didn't replace all uses of the node?");
2909 // FIXME: We just return here, which interacts correctly with SelectRoot
2910 // above. We should fix this to not return an SDNode* anymore.
2915 // If the code reached this point, then the match failed. See if there is
2916 // another child to try in the current 'Scope', otherwise pop it until we
2917 // find a case to check.
2918 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2919 ++NumDAGIselRetries;
2921 if (MatchScopes.empty()) {
2922 CannotYetSelect(NodeToMatch);
2926 // Restore the interpreter state back to the point where the scope was
2928 MatchScope &LastScope = MatchScopes.back();
2929 RecordedNodes.resize(LastScope.NumRecordedNodes);
2931 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2932 N = NodeStack.back();
2934 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2935 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2936 MatcherIndex = LastScope.FailIndex;
2938 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2940 InputChain = LastScope.InputChain;
2941 InputGlue = LastScope.InputGlue;
2942 if (!LastScope.HasChainNodesMatched)
2943 ChainNodesMatched.clear();
2944 if (!LastScope.HasGlueResultNodesMatched)
2945 GlueResultNodesMatched.clear();
2947 // Check to see what the offset is at the new MatcherIndex. If it is zero
2948 // we have reached the end of this scope, otherwise we have another child
2949 // in the current scope to try.
2950 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2951 if (NumToSkip & 128)
2952 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2954 // If we have another child in this scope to match, update FailIndex and
2956 if (NumToSkip != 0) {
2957 LastScope.FailIndex = MatcherIndex+NumToSkip;
2961 // End of this scope, pop it and try the next child in the containing
2963 MatchScopes.pop_back();
2970 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2972 raw_string_ostream Msg(msg);
2973 Msg << "Cannot select: ";
2975 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2976 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2977 N->getOpcode() != ISD::INTRINSIC_VOID) {
2978 N->printrFull(Msg, CurDAG);
2980 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2982 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2983 if (iid < Intrinsic::num_intrinsics)
2984 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2985 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2986 Msg << "target intrinsic %" << TII->getName(iid);
2988 Msg << "unknown intrinsic #" << iid;
2990 report_fatal_error(Msg.str());
2993 char SelectionDAGISel::ID = 0;