1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/Constants.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Instructions.h"
20 #include "llvm/Intrinsics.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
39 ViewDAGs("view-isel-dags", cl::Hidden,
40 cl::desc("Pop up a window to show isel dags as they are selected"));
42 static const bool ViewDAGS = 0;
46 //===--------------------------------------------------------------------===//
47 /// FunctionLoweringInfo - This contains information that is global to a
48 /// function that is used when lowering a region of the function.
49 class FunctionLoweringInfo {
56 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
58 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
59 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
61 /// ValueMap - Since we emit code for the function a basic block at a time,
62 /// we must remember which virtual registers hold the values for
63 /// cross-basic-block values.
64 std::map<const Value*, unsigned> ValueMap;
66 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
67 /// the entry block. This allows the allocas to be efficiently referenced
68 /// anywhere in the function.
69 std::map<const AllocaInst*, int> StaticAllocaMap;
71 /// BlockLocalArguments - If any arguments are only used in a single basic
72 /// block, and if the target can access the arguments without side-effects,
73 /// avoid emitting CopyToReg nodes for those arguments. This map keeps
74 /// track of which arguments are local to each BB.
75 std::multimap<BasicBlock*, std::pair<Argument*,
76 unsigned> > BlockLocalArguments;
79 unsigned MakeReg(MVT::ValueType VT) {
80 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
83 unsigned CreateRegForValue(const Value *V) {
84 MVT::ValueType VT = TLI.getValueType(V->getType());
85 // The common case is that we will only create one register for this
86 // value. If we have that case, create and return the virtual register.
87 unsigned NV = TLI.getNumElements(VT);
89 // If we are promoting this value, pick the next largest supported type.
90 return MakeReg(TLI.getTypeToTransformTo(VT));
93 // If this value is represented with multiple target registers, make sure
94 // to create enough consequtive registers of the right (smaller) type.
95 unsigned NT = VT-1; // Find the type to use.
96 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
99 unsigned R = MakeReg((MVT::ValueType)NT);
100 for (unsigned i = 1; i != NV; ++i)
101 MakeReg((MVT::ValueType)NT);
105 unsigned InitializeRegForValue(const Value *V) {
106 unsigned &R = ValueMap[V];
107 assert(R == 0 && "Already initialized this value register!");
108 return R = CreateRegForValue(V);
113 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
114 /// PHI nodes or outside of the basic block that defines it.
115 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
116 if (isa<PHINode>(I)) return true;
117 BasicBlock *BB = I->getParent();
118 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
119 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
124 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
125 Function &fn, MachineFunction &mf)
126 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
128 // Initialize the mapping of values to registers. This is only set up for
129 // instruction values that are used outside of the block that defines
131 for (Function::aiterator AI = Fn.abegin(), E = Fn.aend(); AI != E; ++AI)
132 InitializeRegForValue(AI);
134 Function::iterator BB = Fn.begin(), E = Fn.end();
135 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
136 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
137 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
138 const Type *Ty = AI->getAllocatedType();
139 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
140 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
141 TySize *= CUI->getValue(); // Get total allocated size.
142 StaticAllocaMap[AI] =
143 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
146 for (; BB != E; ++BB)
147 for (BasicBlock::iterator I = BB->begin(), e = BB->end(); I != e; ++I)
148 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
149 if (!isa<AllocaInst>(I) ||
150 !StaticAllocaMap.count(cast<AllocaInst>(I)))
151 InitializeRegForValue(I);
153 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
154 // also creates the initial PHI MachineInstrs, though none of the input
155 // operands are populated.
156 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
157 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
159 MF.getBasicBlockList().push_back(MBB);
161 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
164 for (BasicBlock::iterator I = BB->begin();
165 (PN = dyn_cast<PHINode>(I)); ++I)
166 if (!PN->use_empty()) {
167 unsigned NumElements =
168 TLI.getNumElements(TLI.getValueType(PN->getType()));
169 unsigned PHIReg = ValueMap[PN];
170 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
171 for (unsigned i = 0; i != NumElements; ++i)
172 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
179 //===----------------------------------------------------------------------===//
180 /// SelectionDAGLowering - This is the common target-independent lowering
181 /// implementation that is parameterized by a TargetLowering object.
182 /// Also, targets can overload any lowering method.
185 class SelectionDAGLowering {
186 MachineBasicBlock *CurMBB;
188 std::map<const Value*, SDOperand> NodeMap;
190 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
191 /// them up and then emit token factor nodes when possible. This allows us to
192 /// get simple disambiguation between loads without worrying about alias
194 std::vector<SDOperand> PendingLoads;
197 // TLI - This is information that describes the available target features we
198 // need for lowering. This indicates when operations are unavailable,
199 // implemented with a libcall, etc.
202 const TargetData &TD;
204 /// FuncInfo - Information about the function as a whole.
206 FunctionLoweringInfo &FuncInfo;
208 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
209 FunctionLoweringInfo &funcinfo)
210 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
214 /// getRoot - Return the current virtual root of the Selection DAG.
216 SDOperand getRoot() {
217 if (PendingLoads.empty())
218 return DAG.getRoot();
220 if (PendingLoads.size() == 1) {
221 SDOperand Root = PendingLoads[0];
223 PendingLoads.clear();
227 // Otherwise, we have to make a token factor node.
228 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
229 PendingLoads.clear();
234 void visit(Instruction &I) { visit(I.getOpcode(), I); }
236 void visit(unsigned Opcode, User &I) {
238 default: assert(0 && "Unknown instruction type encountered!");
240 // Build the switch statement using the Instruction.def file.
241 #define HANDLE_INST(NUM, OPCODE, CLASS) \
242 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
243 #include "llvm/Instruction.def"
247 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
250 SDOperand getIntPtrConstant(uint64_t Val) {
251 return DAG.getConstant(Val, TLI.getPointerTy());
254 SDOperand getValue(const Value *V) {
255 SDOperand &N = NodeMap[V];
258 MVT::ValueType VT = TLI.getValueType(V->getType());
259 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V)))
260 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
261 visit(CE->getOpcode(), *CE);
262 assert(N.Val && "visit didn't populate the ValueMap!");
264 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
265 return N = DAG.getGlobalAddress(GV, VT);
266 } else if (isa<ConstantPointerNull>(C)) {
267 return N = DAG.getConstant(0, TLI.getPointerTy());
268 } else if (isa<UndefValue>(C)) {
269 /// FIXME: Implement UNDEFVALUE better.
270 if (MVT::isInteger(VT))
271 return N = DAG.getConstant(0, VT);
272 else if (MVT::isFloatingPoint(VT))
273 return N = DAG.getConstantFP(0, VT);
275 assert(0 && "Unknown value type!");
277 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
278 return N = DAG.getConstantFP(CFP->getValue(), VT);
280 // Canonicalize all constant ints to be unsigned.
281 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
284 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
285 std::map<const AllocaInst*, int>::iterator SI =
286 FuncInfo.StaticAllocaMap.find(AI);
287 if (SI != FuncInfo.StaticAllocaMap.end())
288 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
291 std::map<const Value*, unsigned>::const_iterator VMI =
292 FuncInfo.ValueMap.find(V);
293 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
295 return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode());
298 const SDOperand &setValue(const Value *V, SDOperand NewN) {
299 SDOperand &N = NodeMap[V];
300 assert(N.Val == 0 && "Already set a value for this node!");
304 // Terminator instructions.
305 void visitRet(ReturnInst &I);
306 void visitBr(BranchInst &I);
307 void visitUnreachable(UnreachableInst &I) { /* noop */ }
309 // These all get lowered before this pass.
310 void visitSwitch(SwitchInst &I) { assert(0 && "TODO"); }
311 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
312 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
315 void visitBinary(User &I, unsigned Opcode);
316 void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
317 void visitSub(User &I) { visitBinary(I, ISD::SUB); }
318 void visitMul(User &I) { visitBinary(I, ISD::MUL); }
319 void visitDiv(User &I) {
320 visitBinary(I, I.getType()->isUnsigned() ? ISD::UDIV : ISD::SDIV);
322 void visitRem(User &I) {
323 visitBinary(I, I.getType()->isUnsigned() ? ISD::UREM : ISD::SREM);
325 void visitAnd(User &I) { visitBinary(I, ISD::AND); }
326 void visitOr (User &I) { visitBinary(I, ISD::OR); }
327 void visitXor(User &I) { visitBinary(I, ISD::XOR); }
328 void visitShl(User &I) { visitBinary(I, ISD::SHL); }
329 void visitShr(User &I) {
330 visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
333 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
334 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ); }
335 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE); }
336 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE); }
337 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE); }
338 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
339 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
341 void visitGetElementPtr(User &I);
342 void visitCast(User &I);
343 void visitSelect(User &I);
346 void visitMalloc(MallocInst &I);
347 void visitFree(FreeInst &I);
348 void visitAlloca(AllocaInst &I);
349 void visitLoad(LoadInst &I);
350 void visitStore(StoreInst &I);
351 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
352 void visitCall(CallInst &I);
354 void visitVAStart(CallInst &I);
355 void visitVANext(VANextInst &I);
356 void visitVAArg(VAArgInst &I);
357 void visitVAEnd(CallInst &I);
358 void visitVACopy(CallInst &I);
359 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
361 void visitMemIntrinsic(CallInst &I, unsigned Op);
363 void visitUserOp1(Instruction &I) {
364 assert(0 && "UserOp1 should not exist at instruction selection time!");
367 void visitUserOp2(Instruction &I) {
368 assert(0 && "UserOp2 should not exist at instruction selection time!");
372 } // end namespace llvm
374 void SelectionDAGLowering::visitRet(ReturnInst &I) {
375 if (I.getNumOperands() == 0) {
376 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
380 SDOperand Op1 = getValue(I.getOperand(0));
381 switch (Op1.getValueType()) {
382 default: assert(0 && "Unknown value type!");
386 // Extend integer types to 32-bits.
387 if (I.getOperand(0)->getType()->isSigned())
388 Op1 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Op1);
390 Op1 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op1);
393 // Extend float to double.
394 Op1 = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op1);
399 break; // No extension needed!
402 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot(), Op1));
405 void SelectionDAGLowering::visitBr(BranchInst &I) {
406 // Update machine-CFG edges.
407 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
408 CurMBB->addSuccessor(Succ0MBB);
410 // Figure out which block is immediately after the current one.
411 MachineBasicBlock *NextBlock = 0;
412 MachineFunction::iterator BBI = CurMBB;
413 if (++BBI != CurMBB->getParent()->end())
416 if (I.isUnconditional()) {
417 // If this is not a fall-through branch, emit the branch.
418 if (Succ0MBB != NextBlock)
419 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
420 DAG.getBasicBlock(Succ0MBB)));
422 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
423 CurMBB->addSuccessor(Succ1MBB);
425 SDOperand Cond = getValue(I.getCondition());
427 if (Succ1MBB == NextBlock) {
428 // If the condition is false, fall through. This means we should branch
429 // if the condition is true to Succ #0.
430 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
431 Cond, DAG.getBasicBlock(Succ0MBB)));
432 } else if (Succ0MBB == NextBlock) {
433 // If the condition is true, fall through. This means we should branch if
434 // the condition is false to Succ #1. Invert the condition first.
435 SDOperand True = DAG.getConstant(1, Cond.getValueType());
436 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
437 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
438 Cond, DAG.getBasicBlock(Succ1MBB)));
440 // Neither edge is a fall through. If the comparison is true, jump to
441 // Succ#0, otherwise branch unconditionally to succ #1.
442 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
443 Cond, DAG.getBasicBlock(Succ0MBB)));
444 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
445 DAG.getBasicBlock(Succ1MBB)));
450 void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode) {
451 SDOperand Op1 = getValue(I.getOperand(0));
452 SDOperand Op2 = getValue(I.getOperand(1));
454 if (isa<ShiftInst>(I))
455 Op2 = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), Op2);
457 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
460 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
461 ISD::CondCode UnsignedOpcode) {
462 SDOperand Op1 = getValue(I.getOperand(0));
463 SDOperand Op2 = getValue(I.getOperand(1));
464 ISD::CondCode Opcode = SignedOpcode;
465 if (I.getOperand(0)->getType()->isUnsigned())
466 Opcode = UnsignedOpcode;
467 setValue(&I, DAG.getSetCC(Opcode, MVT::i1, Op1, Op2));
470 void SelectionDAGLowering::visitSelect(User &I) {
471 SDOperand Cond = getValue(I.getOperand(0));
472 SDOperand TrueVal = getValue(I.getOperand(1));
473 SDOperand FalseVal = getValue(I.getOperand(2));
474 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
478 void SelectionDAGLowering::visitCast(User &I) {
479 SDOperand N = getValue(I.getOperand(0));
480 MVT::ValueType SrcTy = TLI.getValueType(I.getOperand(0)->getType());
481 MVT::ValueType DestTy = TLI.getValueType(I.getType());
483 if (N.getValueType() == DestTy) {
484 setValue(&I, N); // noop cast.
485 } else if (isInteger(SrcTy)) {
486 if (isInteger(DestTy)) { // Int -> Int cast
487 if (DestTy < SrcTy) // Truncating cast?
488 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestTy, N));
489 else if (I.getOperand(0)->getType()->isSigned())
490 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestTy, N));
492 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestTy, N));
493 } else { // Int -> FP cast
494 if (I.getOperand(0)->getType()->isSigned())
495 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestTy, N));
497 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestTy, N));
500 assert(isFloatingPoint(SrcTy) && "Unknown value type!");
501 if (isFloatingPoint(DestTy)) { // FP -> FP cast
502 if (DestTy < SrcTy) // Rounding cast?
503 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestTy, N));
505 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestTy, N));
506 } else { // FP -> Int cast.
507 if (I.getType()->isSigned())
508 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestTy, N));
510 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestTy, N));
515 void SelectionDAGLowering::visitGetElementPtr(User &I) {
516 SDOperand N = getValue(I.getOperand(0));
517 const Type *Ty = I.getOperand(0)->getType();
518 const Type *UIntPtrTy = TD.getIntPtrType();
520 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
523 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
524 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
527 uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field];
528 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
529 getIntPtrConstant(Offset));
531 Ty = StTy->getElementType(Field);
533 Ty = cast<SequentialType>(Ty)->getElementType();
534 if (!isa<Constant>(Idx) || !cast<Constant>(Idx)->isNullValue()) {
535 // N = N + Idx * ElementSize;
536 uint64_t ElementSize = TD.getTypeSize(Ty);
537 SDOperand IdxN = getValue(Idx), Scale = getIntPtrConstant(ElementSize);
539 // If the index is smaller or larger than intptr_t, truncate or extend
541 if (IdxN.getValueType() < Scale.getValueType()) {
542 if (Idx->getType()->isSigned())
543 IdxN = DAG.getNode(ISD::SIGN_EXTEND, Scale.getValueType(), IdxN);
545 IdxN = DAG.getNode(ISD::ZERO_EXTEND, Scale.getValueType(), IdxN);
546 } else if (IdxN.getValueType() > Scale.getValueType())
547 IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN);
549 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
551 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
558 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
559 // If this is a fixed sized alloca in the entry block of the function,
560 // allocate it statically on the stack.
561 if (FuncInfo.StaticAllocaMap.count(&I))
562 return; // getValue will auto-populate this.
564 const Type *Ty = I.getAllocatedType();
565 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
566 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
568 SDOperand AllocSize = getValue(I.getArraySize());
569 MVT::ValueType IntPtr = TLI.getPointerTy();
570 if (IntPtr < AllocSize.getValueType())
571 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
572 else if (IntPtr > AllocSize.getValueType())
573 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
575 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
576 getIntPtrConstant(TySize));
578 // Handle alignment. If the requested alignment is less than or equal to the
579 // stack alignment, ignore it and round the size of the allocation up to the
580 // stack alignment size. If the size is greater than the stack alignment, we
581 // note this in the DYNAMIC_STACKALLOC node.
582 unsigned StackAlign =
583 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
584 if (Align <= StackAlign) {
586 // Add SA-1 to the size.
587 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
588 getIntPtrConstant(StackAlign-1));
589 // Mask out the low bits for alignment purposes.
590 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
591 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
594 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, AllocSize.getValueType(),
595 getRoot(), AllocSize,
596 getIntPtrConstant(Align));
597 DAG.setRoot(setValue(&I, DSA).getValue(1));
599 // Inform the Frame Information that we have just allocated a variable-sized
601 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
605 void SelectionDAGLowering::visitLoad(LoadInst &I) {
606 SDOperand Ptr = getValue(I.getOperand(0));
612 // Do not serialize non-volatile loads against each other.
613 Root = DAG.getRoot();
616 SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr);
620 DAG.setRoot(L.getValue(1));
622 PendingLoads.push_back(L.getValue(1));
626 void SelectionDAGLowering::visitStore(StoreInst &I) {
627 Value *SrcV = I.getOperand(0);
628 SDOperand Src = getValue(SrcV);
629 SDOperand Ptr = getValue(I.getOperand(1));
630 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr));
633 void SelectionDAGLowering::visitCall(CallInst &I) {
634 const char *RenameFn = 0;
635 if (Function *F = I.getCalledFunction())
636 switch (F->getIntrinsicID()) {
637 case 0: break; // Not an intrinsic.
638 case Intrinsic::vastart: visitVAStart(I); return;
639 case Intrinsic::vaend: visitVAEnd(I); return;
640 case Intrinsic::vacopy: visitVACopy(I); return;
641 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return;
642 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return;
644 // FIXME: IMPLEMENT THESE.
645 // readport, writeport, readio, writeio
646 assert(0 && "This intrinsic is not implemented yet!");
648 case Intrinsic::setjmp: RenameFn = "setjmp"; break;
649 case Intrinsic::longjmp: RenameFn = "longjmp"; break;
650 case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return;
651 case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return;
652 case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
654 case Intrinsic::isunordered:
655 setValue(&I, DAG.getSetCC(ISD::SETUO, MVT::i1, getValue(I.getOperand(1)),
656 getValue(I.getOperand(2))));
662 Callee = getValue(I.getOperand(0));
664 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
665 std::vector<std::pair<SDOperand, const Type*> > Args;
667 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
668 Value *Arg = I.getOperand(i);
669 SDOperand ArgNode = getValue(Arg);
670 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
673 std::pair<SDOperand,SDOperand> Result =
674 TLI.LowerCallTo(getRoot(), I.getType(), Callee, Args, DAG);
675 if (I.getType() != Type::VoidTy)
676 setValue(&I, Result.first);
677 DAG.setRoot(Result.second);
680 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
681 SDOperand Src = getValue(I.getOperand(0));
683 MVT::ValueType IntPtr = TLI.getPointerTy();
685 if (IntPtr < Src.getValueType())
686 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
687 else if (IntPtr > Src.getValueType())
688 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
690 // Scale the source by the type size.
691 uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType());
692 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
693 Src, getIntPtrConstant(ElementSize));
695 std::vector<std::pair<SDOperand, const Type*> > Args;
696 Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
698 std::pair<SDOperand,SDOperand> Result =
699 TLI.LowerCallTo(getRoot(), I.getType(),
700 DAG.getExternalSymbol("malloc", IntPtr),
702 setValue(&I, Result.first); // Pointers always fit in registers
703 DAG.setRoot(Result.second);
706 void SelectionDAGLowering::visitFree(FreeInst &I) {
707 std::vector<std::pair<SDOperand, const Type*> > Args;
708 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
709 TLI.getTargetData().getIntPtrType()));
710 MVT::ValueType IntPtr = TLI.getPointerTy();
711 std::pair<SDOperand,SDOperand> Result =
712 TLI.LowerCallTo(getRoot(), Type::VoidTy,
713 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
714 DAG.setRoot(Result.second);
717 std::pair<SDOperand, SDOperand>
718 TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
719 // We have no sane default behavior, just emit a useful error message and bail
721 std::cerr << "Variable arguments handling not implemented on this target!\n";
725 SDOperand TargetLowering::LowerVAEnd(SDOperand Chain, SDOperand L,
727 // Default to a noop.
731 std::pair<SDOperand,SDOperand>
732 TargetLowering::LowerVACopy(SDOperand Chain, SDOperand L, SelectionDAG &DAG) {
733 // Default to returning the input list.
734 return std::make_pair(L, Chain);
737 std::pair<SDOperand,SDOperand>
738 TargetLowering::LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
739 const Type *ArgTy, SelectionDAG &DAG) {
740 // We have no sane default behavior, just emit a useful error message and bail
742 std::cerr << "Variable arguments handling not implemented on this target!\n";
747 void SelectionDAGLowering::visitVAStart(CallInst &I) {
748 std::pair<SDOperand,SDOperand> Result = TLI.LowerVAStart(getRoot(), DAG);
749 setValue(&I, Result.first);
750 DAG.setRoot(Result.second);
753 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
754 std::pair<SDOperand,SDOperand> Result =
755 TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)),
757 setValue(&I, Result.first);
758 DAG.setRoot(Result.second);
761 void SelectionDAGLowering::visitVANext(VANextInst &I) {
762 std::pair<SDOperand,SDOperand> Result =
763 TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)),
764 I.getArgType(), DAG);
765 setValue(&I, Result.first);
766 DAG.setRoot(Result.second);
769 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
770 DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)), DAG));
773 void SelectionDAGLowering::visitVACopy(CallInst &I) {
774 std::pair<SDOperand,SDOperand> Result =
775 TLI.LowerVACopy(getRoot(), getValue(I.getOperand(1)), DAG);
776 setValue(&I, Result.first);
777 DAG.setRoot(Result.second);
781 // It is always conservatively correct for llvm.returnaddress and
782 // llvm.frameaddress to return 0.
783 std::pair<SDOperand, SDOperand>
784 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
785 unsigned Depth, SelectionDAG &DAG) {
786 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
789 SDOperand TargetLowering::LowerOperation(SDOperand Op) {
790 assert(0 && "LowerOperation not implemented for this target!");
794 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
795 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
796 std::pair<SDOperand,SDOperand> Result =
797 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
798 setValue(&I, Result.first);
799 DAG.setRoot(Result.second);
802 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
803 std::vector<SDOperand> Ops;
804 Ops.push_back(getRoot());
805 Ops.push_back(getValue(I.getOperand(1)));
806 Ops.push_back(getValue(I.getOperand(2)));
807 Ops.push_back(getValue(I.getOperand(3)));
808 Ops.push_back(getValue(I.getOperand(4)));
809 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
812 //===----------------------------------------------------------------------===//
813 // SelectionDAGISel code
814 //===----------------------------------------------------------------------===//
816 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
817 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
822 bool SelectionDAGISel::runOnFunction(Function &Fn) {
823 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
824 RegMap = MF.getSSARegMap();
825 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
827 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
829 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
830 SelectBasicBlock(I, MF, FuncInfo);
836 SDOperand SelectionDAGISel::
837 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
838 SelectionDAG &DAG = SDL.DAG;
839 SDOperand Op = SDL.getValue(V);
840 assert((Op.getOpcode() != ISD::CopyFromReg ||
841 cast<RegSDNode>(Op)->getReg() != Reg) &&
842 "Copy from a reg to the same reg!");
843 return DAG.getCopyToReg(SDL.getRoot(), Op, Reg);
846 /// IsOnlyUsedInOneBasicBlock - If the specified argument is only used in a
847 /// single basic block, return that block. Otherwise, return a null pointer.
848 static BasicBlock *IsOnlyUsedInOneBasicBlock(Argument *A) {
849 if (A->use_empty()) return 0;
850 BasicBlock *BB = cast<Instruction>(A->use_back())->getParent();
851 for (Argument::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E;
853 if (isa<PHINode>(*UI) || cast<Instruction>(*UI)->getParent() != BB)
854 return 0; // Disagreement among the users?
858 void SelectionDAGISel::
859 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
860 std::vector<SDOperand> &UnorderedChains) {
861 // If this is the entry block, emit arguments.
862 Function &F = *BB->getParent();
863 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
865 if (BB == &F.front()) {
866 SDOperand OldRoot = SDL.DAG.getRoot();
868 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
870 // If there were side effects accessing the argument list, do not do
872 if (OldRoot != SDL.DAG.getRoot()) {
874 for (Function::aiterator AI = F.abegin(), E = F.aend(); AI != E; ++AI,++a)
875 if (!AI->use_empty()) {
876 SDL.setValue(AI, Args[a]);
878 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
879 UnorderedChains.push_back(Copy);
882 // Otherwise, if any argument is only accessed in a single basic block,
883 // emit that argument only to that basic block.
885 for (Function::aiterator AI = F.abegin(), E = F.aend(); AI != E; ++AI,++a)
886 if (!AI->use_empty()) {
887 if (BasicBlock *BBU = IsOnlyUsedInOneBasicBlock(AI)) {
888 FuncInfo.BlockLocalArguments.insert(std::make_pair(BBU,
889 std::make_pair(AI, a)));
891 SDL.setValue(AI, Args[a]);
893 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
894 UnorderedChains.push_back(Copy);
900 // See if there are any block-local arguments that need to be emitted in this
903 if (!FuncInfo.BlockLocalArguments.empty()) {
904 std::multimap<BasicBlock*, std::pair<Argument*, unsigned> >::iterator BLAI =
905 FuncInfo.BlockLocalArguments.lower_bound(BB);
906 if (BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB) {
907 // Lower the arguments into this block.
908 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
910 // Set up the value mapping for the local arguments.
911 for (; BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB;
913 SDL.setValue(BLAI->second.first, Args[BLAI->second.second]);
915 // Any dead arguments will just be ignored here.
921 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
922 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
923 FunctionLoweringInfo &FuncInfo) {
924 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
926 std::vector<SDOperand> UnorderedChains;
928 // Lower any arguments needed in this block.
929 LowerArguments(LLVMBB, SDL, UnorderedChains);
931 BB = FuncInfo.MBBMap[LLVMBB];
932 SDL.setCurrentBasicBlock(BB);
934 // Lower all of the non-terminator instructions.
935 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
939 // Ensure that all instructions which are used outside of their defining
940 // blocks are available as virtual registers.
941 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
942 if (!I->use_empty() && !isa<PHINode>(I)) {
943 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
944 if (VMI != FuncInfo.ValueMap.end())
945 UnorderedChains.push_back(
946 CopyValueToVirtualRegister(SDL, I, VMI->second));
949 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
950 // ensure constants are generated when needed. Remember the virtual registers
951 // that need to be added to the Machine PHI nodes as input. We cannot just
952 // directly add them, because expansion might result in multiple MBB's for one
953 // BB. As such, the start of the BB might correspond to a different MBB than
957 // Emit constants only once even if used by multiple PHI nodes.
958 std::map<Constant*, unsigned> ConstantsOut;
960 // Check successor nodes PHI nodes that expect a constant to be available from
962 TerminatorInst *TI = LLVMBB->getTerminator();
963 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
964 BasicBlock *SuccBB = TI->getSuccessor(succ);
965 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
968 // At this point we know that there is a 1-1 correspondence between LLVM PHI
969 // nodes and Machine PHI nodes, but the incoming operands have not been
971 for (BasicBlock::iterator I = SuccBB->begin();
972 (PN = dyn_cast<PHINode>(I)); ++I)
973 if (!PN->use_empty()) {
975 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
976 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
977 unsigned &RegOut = ConstantsOut[C];
979 RegOut = FuncInfo.CreateRegForValue(C);
980 UnorderedChains.push_back(
981 CopyValueToVirtualRegister(SDL, C, RegOut));
985 Reg = FuncInfo.ValueMap[PHIOp];
987 assert(isa<AllocaInst>(PHIOp) &&
988 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
989 "Didn't codegen value into a register!??");
990 Reg = FuncInfo.CreateRegForValue(PHIOp);
991 UnorderedChains.push_back(
992 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
996 // Remember that this register needs to added to the machine PHI node as
997 // the input for this MBB.
998 unsigned NumElements =
999 TLI.getNumElements(TLI.getValueType(PN->getType()));
1000 for (unsigned i = 0, e = NumElements; i != e; ++i)
1001 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
1004 ConstantsOut.clear();
1006 // Turn all of the unordered chains into one factored node.
1007 if (!UnorderedChains.empty()) {
1008 UnorderedChains.push_back(SDL.getRoot());
1009 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
1012 // Lower the terminator after the copies are emitted.
1013 SDL.visit(*LLVMBB->getTerminator());
1015 // Make sure the root of the DAG is up-to-date.
1016 DAG.setRoot(SDL.getRoot());
1019 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
1020 FunctionLoweringInfo &FuncInfo) {
1021 SelectionDAG DAG(TLI, MF);
1023 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
1025 // First step, lower LLVM code to some DAG. This DAG may use operations and
1026 // types that are not supported by the target.
1027 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
1029 DEBUG(std::cerr << "Lowered selection DAG:\n");
1032 // Second step, hack on the DAG until it only uses operations and types that
1033 // the target supports.
1036 DEBUG(std::cerr << "Legalized selection DAG:\n");
1039 // Finally, instruction select all of the operations to machine code, adding
1040 // the code to the MachineBasicBlock.
1041 InstructionSelectBasicBlock(DAG);
1043 if (ViewDAGs) DAG.viewGraph();
1045 DEBUG(std::cerr << "Selected machine code:\n");
1048 // Finally, now that we know what the last MBB the LLVM BB expanded is, update
1049 // PHI nodes in successors.
1050 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
1051 MachineInstr *PHI = PHINodesToUpdate[i].first;
1052 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
1053 "This is not a machine PHI node that we are updating!");
1054 PHI->addRegOperand(PHINodesToUpdate[i].second);
1055 PHI->addMachineBasicBlockOperand(BB);