1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "SelectionDAGBuild.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Constants.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/GCMetadata.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/ScheduleDAGSDNodes.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetFrameInfo.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/Timer.h"
56 EnableValueProp("enable-value-prop", cl::Hidden);
58 DisableLegalizeTypes("disable-legalize-types", cl::Hidden);
61 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
62 cl::desc("Enable verbose messages in the \"fast\" "
63 "instruction selector"));
65 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
66 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 static const bool EnableFastISelVerbose = false,
69 EnableFastISelAbort = false;
72 SchedLiveInCopies("schedule-livein-copies",
73 cl::desc("Schedule copies of livein registers"),
78 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the first "
82 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before legalize types"));
85 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
86 cl::desc("Pop up a window to show dags before legalize"));
88 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
89 cl::desc("Pop up a window to show dags before the second "
92 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
93 cl::desc("Pop up a window to show dags before the post legalize types"
94 " dag combine pass"));
96 ViewISelDAGs("view-isel-dags", cl::Hidden,
97 cl::desc("Pop up a window to show isel dags as they are selected"));
99 ViewSchedDAGs("view-sched-dags", cl::Hidden,
100 cl::desc("Pop up a window to show sched dags as they are processed"));
102 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
103 cl::desc("Pop up a window to show SUnit dags after they are processed"));
105 static const bool ViewDAGCombine1 = false,
106 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
107 ViewDAGCombine2 = false,
108 ViewDAGCombineLT = false,
109 ViewISelDAGs = false, ViewSchedDAGs = false,
110 ViewSUnitDAGs = false;
113 //===---------------------------------------------------------------------===//
115 /// RegisterScheduler class - Track the registration of instruction schedulers.
117 //===---------------------------------------------------------------------===//
118 MachinePassRegistry RegisterScheduler::Registry;
120 //===---------------------------------------------------------------------===//
122 /// ISHeuristic command line option for instruction schedulers.
124 //===---------------------------------------------------------------------===//
125 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
126 RegisterPassParser<RegisterScheduler> >
127 ISHeuristic("pre-RA-sched",
128 cl::init(&createDefaultScheduler),
129 cl::desc("Instruction schedulers available (before register"
132 static RegisterScheduler
133 defaultListDAGScheduler("default", "Best scheduler for the target",
134 createDefaultScheduler);
137 //===--------------------------------------------------------------------===//
138 /// createDefaultScheduler - This creates an instruction scheduler appropriate
140 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
142 const TargetLowering &TLI = IS->getTargetLowering();
145 return createFastDAGScheduler(IS, Fast);
146 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
147 return createTDListDAGScheduler(IS, Fast);
148 assert(TLI.getSchedulingPreference() ==
149 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
150 return createBURRListDAGScheduler(IS, Fast);
154 // EmitInstrWithCustomInserter - This method should be implemented by targets
155 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
156 // instructions are special in various ways, which require special support to
157 // insert. The specified MachineInstr is created but not inserted into any
158 // basic blocks, and the scheduler passes ownership of it to this method.
159 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
160 MachineBasicBlock *MBB) {
161 cerr << "If a target marks an instruction with "
162 << "'usesCustomDAGSchedInserter', it must implement "
163 << "TargetLowering::EmitInstrWithCustomInserter!\n";
168 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
169 /// physical register has only a single copy use, then coalesced the copy
171 static void EmitLiveInCopy(MachineBasicBlock *MBB,
172 MachineBasicBlock::iterator &InsertPos,
173 unsigned VirtReg, unsigned PhysReg,
174 const TargetRegisterClass *RC,
175 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
176 const MachineRegisterInfo &MRI,
177 const TargetRegisterInfo &TRI,
178 const TargetInstrInfo &TII) {
179 unsigned NumUses = 0;
180 MachineInstr *UseMI = NULL;
181 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
182 UE = MRI.use_end(); UI != UE; ++UI) {
188 // If the number of uses is not one, or the use is not a move instruction,
189 // don't coalesce. Also, only coalesce away a virtual register to virtual
191 bool Coalesced = false;
192 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
194 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
195 TargetRegisterInfo::isVirtualRegister(DstReg)) {
200 // Now find an ideal location to insert the copy.
201 MachineBasicBlock::iterator Pos = InsertPos;
202 while (Pos != MBB->begin()) {
203 MachineInstr *PrevMI = prior(Pos);
204 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
205 // copyRegToReg might emit multiple instructions to do a copy.
206 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
207 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
208 // This is what the BB looks like right now:
213 // We want to insert "r1025 = mov r1". Inserting this copy below the
214 // move to r1024 makes it impossible for that move to be coalesced.
221 break; // Woot! Found a good location.
225 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
226 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
228 if (&*InsertPos == UseMI) ++InsertPos;
233 /// EmitLiveInCopies - If this is the first basic block in the function,
234 /// and if it has live ins that need to be copied into vregs, emit the
235 /// copies into the block.
236 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
237 const MachineRegisterInfo &MRI,
238 const TargetRegisterInfo &TRI,
239 const TargetInstrInfo &TII) {
240 if (SchedLiveInCopies) {
241 // Emit the copies at a heuristically-determined location in the block.
242 DenseMap<MachineInstr*, unsigned> CopyRegMap;
243 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
244 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
245 E = MRI.livein_end(); LI != E; ++LI)
247 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
248 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
249 RC, CopyRegMap, MRI, TRI, TII);
252 // Emit the copies into the top of the block.
253 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
254 E = MRI.livein_end(); LI != E; ++LI)
256 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
257 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
258 LI->second, LI->first, RC, RC);
263 //===----------------------------------------------------------------------===//
264 // SelectionDAGISel code
265 //===----------------------------------------------------------------------===//
267 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
268 FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
269 FuncInfo(new FunctionLoweringInfo(TLI)),
270 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
271 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
277 SelectionDAGISel::~SelectionDAGISel() {
283 unsigned SelectionDAGISel::MakeReg(MVT VT) {
284 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
287 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
288 AU.addRequired<AliasAnalysis>();
289 AU.addRequired<GCModuleInfo>();
290 AU.addRequired<DwarfWriter>();
291 AU.setPreservesAll();
294 bool SelectionDAGISel::runOnFunction(Function &Fn) {
295 // Do some sanity-checking on the command-line options.
296 assert((!EnableFastISelVerbose || EnableFastISel) &&
297 "-fast-isel-verbose requires -fast-isel");
298 assert((!EnableFastISelAbort || EnableFastISel) &&
299 "-fast-isel-abort requires -fast-isel");
301 // Get alias analysis for load/store combining.
302 AA = &getAnalysis<AliasAnalysis>();
304 TargetMachine &TM = TLI.getTargetMachine();
305 MF = &MachineFunction::construct(&Fn, TM);
306 const TargetInstrInfo &TII = *TM.getInstrInfo();
307 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
309 if (MF->getFunction()->hasGC())
310 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF->getFunction());
313 RegInfo = &MF->getRegInfo();
314 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
316 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
317 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
318 CurDAG->init(*MF, MMI, DW);
319 FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel);
322 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
323 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
325 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
327 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
329 // If the first basic block in the function has live ins that need to be
330 // copied into vregs, emit the copies into the top of the block before
331 // emitting the code for the block.
332 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
334 // Add function live-ins to entry block live-in set.
335 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
336 E = RegInfo->livein_end(); I != E; ++I)
337 MF->begin()->addLiveIn(I->first);
340 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
341 "Not all catch info was assigned to a landing pad!");
349 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
350 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
351 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
352 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) {
353 // Apply the catch info to DestBB.
354 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]);
356 if (!FLI.MBBMap[SrcBB]->isLandingPad())
357 FLI.CatchInfoFound.insert(EHSel);
362 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
363 /// whether object offset >= 0.
365 IsFixedFrameObjectWithPosOffset(MachineFrameInfo *MFI, SDValue Op) {
366 if (!isa<FrameIndexSDNode>(Op)) return false;
368 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
369 int FrameIdx = FrameIdxNode->getIndex();
370 return MFI->isFixedObjectIndex(FrameIdx) &&
371 MFI->getObjectOffset(FrameIdx) >= 0;
374 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
375 /// possibly be overwritten when lowering the outgoing arguments in a tail
376 /// call. Currently the implementation of this call is very conservative and
377 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
378 /// virtual registers would be overwritten by direct lowering.
379 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
380 MachineFrameInfo *MFI) {
381 RegisterSDNode * OpReg = NULL;
382 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
383 (Op.getOpcode()== ISD::CopyFromReg &&
384 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
385 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
386 (Op.getOpcode() == ISD::LOAD &&
387 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
388 (Op.getOpcode() == ISD::MERGE_VALUES &&
389 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
390 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
396 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
397 /// DAG and fixes their tailcall attribute operand.
398 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
399 const TargetLowering& TLI) {
401 SDValue Terminator = DAG.getRoot();
404 if (Terminator.getOpcode() == ISD::RET) {
405 Ret = Terminator.getNode();
408 // Fix tail call attribute of CALL nodes.
409 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
410 BI = DAG.allnodes_end(); BI != BE; ) {
412 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) {
413 SDValue OpRet(Ret, 0);
414 SDValue OpCall(BI, 0);
415 bool isMarkedTailCall = TheCall->isTailCall();
416 // If CALL node has tail call attribute set to true and the call is not
417 // eligible (no RET or the target rejects) the attribute is fixed to
418 // false. The TargetLowering::IsEligibleForTailCallOptimization function
419 // must correctly identify tail call optimizable calls.
420 if (!isMarkedTailCall) continue;
422 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) {
423 // Not eligible. Mark CALL node as non tail call. Note that we
424 // can modify the call node in place since calls are not CSE'd.
425 TheCall->setNotTailCall();
427 // Look for tail call clobbered arguments. Emit a series of
428 // copyto/copyfrom virtual register nodes to protect them.
429 SmallVector<SDValue, 32> Ops;
430 SDValue Chain = TheCall->getChain(), InFlag;
431 Ops.push_back(Chain);
432 Ops.push_back(TheCall->getCallee());
433 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
434 SDValue Arg = TheCall->getArg(i);
435 bool isByVal = TheCall->getArgFlags(i).isByVal();
436 MachineFunction &MF = DAG.getMachineFunction();
437 MachineFrameInfo *MFI = MF.getFrameInfo();
439 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
440 MVT VT = Arg.getValueType();
441 unsigned VReg = MF.getRegInfo().
442 createVirtualRegister(TLI.getRegClassFor(VT));
443 Chain = DAG.getCopyToReg(Chain, Arg.getNode()->getDebugLoc(),
445 InFlag = Chain.getValue(1);
446 Arg = DAG.getCopyFromReg(Chain, Arg.getNode()->getDebugLoc(),
448 Chain = Arg.getValue(1);
449 InFlag = Arg.getValue(2);
452 Ops.push_back(TheCall->getArgFlagsVal(i));
454 // Link in chain of CopyTo/CopyFromReg.
456 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
462 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
463 BasicBlock::iterator Begin,
464 BasicBlock::iterator End) {
465 SDL->setCurrentBasicBlock(BB);
467 // Lower all of the non-terminator instructions.
468 for (BasicBlock::iterator I = Begin; I != End; ++I)
469 if (!isa<TerminatorInst>(I))
472 // Ensure that all instructions which are used outside of their defining
473 // blocks are available as virtual registers. Invoke is handled elsewhere.
474 for (BasicBlock::iterator I = Begin; I != End; ++I)
475 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
476 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I);
477 if (VMI != FuncInfo->ValueMap.end())
478 SDL->CopyValueToVirtualRegister(I, VMI->second);
481 // Handle PHI nodes in successor blocks.
482 if (End == LLVMBB->end()) {
483 HandlePHINodesInSuccessorBlocks(LLVMBB);
485 // Lower the terminator after the copies are emitted.
486 SDL->visit(*LLVMBB->getTerminator());
489 // Make sure the root of the DAG is up-to-date.
490 CurDAG->setRoot(SDL->getControlRoot());
492 // Check whether calls in this block are real tail calls. Fix up CALL nodes
493 // with correct tailcall attribute so that the target can rely on the tailcall
494 // attribute indicating whether the call is really eligible for tail call
496 if (PerformTailCallOpt)
497 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
499 // Final step, emit the lowered DAG as machine code.
504 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
505 SmallPtrSet<SDNode*, 128> VisitedNodes;
506 SmallVector<SDNode*, 128> Worklist;
508 Worklist.push_back(CurDAG->getRoot().getNode());
514 while (!Worklist.empty()) {
515 SDNode *N = Worklist.back();
518 // If we've already seen this node, ignore it.
519 if (!VisitedNodes.insert(N))
522 // Otherwise, add all chain operands to the worklist.
523 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
524 if (N->getOperand(i).getValueType() == MVT::Other)
525 Worklist.push_back(N->getOperand(i).getNode());
527 // If this is a CopyToReg with a vreg dest, process it.
528 if (N->getOpcode() != ISD::CopyToReg)
531 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
532 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
535 // Ignore non-scalar or non-integer values.
536 SDValue Src = N->getOperand(2);
537 MVT SrcVT = Src.getValueType();
538 if (!SrcVT.isInteger() || SrcVT.isVector())
541 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
542 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
543 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
545 // Only install this information if it tells us something.
546 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
547 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
548 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
549 if (DestReg >= FLI.LiveOutRegInfo.size())
550 FLI.LiveOutRegInfo.resize(DestReg+1);
551 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
552 LOI.NumSignBits = NumSignBits;
553 LOI.KnownOne = NumSignBits;
554 LOI.KnownZero = NumSignBits;
559 void SelectionDAGISel::CodeGenAndEmitDAG() {
560 std::string GroupName;
561 if (TimePassesIsEnabled)
562 GroupName = "Instruction Selection and Scheduling";
563 std::string BlockName;
564 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
565 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
567 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' +
568 BB->getBasicBlock()->getName();
570 DOUT << "Initial selection DAG:\n";
571 DEBUG(CurDAG->dump());
573 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
575 // Run the DAG combiner in pre-legalize mode.
576 if (TimePassesIsEnabled) {
577 NamedRegionTimer T("DAG Combining 1", GroupName);
578 CurDAG->Combine(Unrestricted, *AA, Fast);
580 CurDAG->Combine(Unrestricted, *AA, Fast);
583 DOUT << "Optimized lowered selection DAG:\n";
584 DEBUG(CurDAG->dump());
586 // Second step, hack on the DAG until it only uses operations and types that
587 // the target supports.
588 if (!DisableLegalizeTypes) {
589 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
593 if (TimePassesIsEnabled) {
594 NamedRegionTimer T("Type Legalization", GroupName);
595 Changed = CurDAG->LegalizeTypes();
597 Changed = CurDAG->LegalizeTypes();
600 DOUT << "Type-legalized selection DAG:\n";
601 DEBUG(CurDAG->dump());
604 if (ViewDAGCombineLT)
605 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
607 // Run the DAG combiner in post-type-legalize mode.
608 if (TimePassesIsEnabled) {
609 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
610 CurDAG->Combine(NoIllegalTypes, *AA, Fast);
612 CurDAG->Combine(NoIllegalTypes, *AA, Fast);
615 DOUT << "Optimized type-legalized selection DAG:\n";
616 DEBUG(CurDAG->dump());
620 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
622 if (TimePassesIsEnabled) {
623 NamedRegionTimer T("DAG Legalization", GroupName);
624 CurDAG->Legalize(DisableLegalizeTypes);
626 CurDAG->Legalize(DisableLegalizeTypes);
629 DOUT << "Legalized selection DAG:\n";
630 DEBUG(CurDAG->dump());
632 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
634 // Run the DAG combiner in post-legalize mode.
635 if (TimePassesIsEnabled) {
636 NamedRegionTimer T("DAG Combining 2", GroupName);
637 CurDAG->Combine(NoIllegalOperations, *AA, Fast);
639 CurDAG->Combine(NoIllegalOperations, *AA, Fast);
642 DOUT << "Optimized legalized selection DAG:\n";
643 DEBUG(CurDAG->dump());
645 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
647 if (!Fast && EnableValueProp)
648 ComputeLiveOutVRegInfo();
650 // Third, instruction select all of the operations to machine code, adding the
651 // code to the MachineBasicBlock.
652 if (TimePassesIsEnabled) {
653 NamedRegionTimer T("Instruction Selection", GroupName);
659 DOUT << "Selected selection DAG:\n";
660 DEBUG(CurDAG->dump());
662 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
664 // Schedule machine code.
665 ScheduleDAG *Scheduler;
666 if (TimePassesIsEnabled) {
667 NamedRegionTimer T("Instruction Scheduling", GroupName);
668 Scheduler = Schedule();
670 Scheduler = Schedule();
673 if (ViewSUnitDAGs) Scheduler->viewGraph();
675 // Emit machine code to BB. This can change 'BB' to the last block being
677 if (TimePassesIsEnabled) {
678 NamedRegionTimer T("Instruction Creation", GroupName);
679 BB = Scheduler->EmitSchedule();
681 BB = Scheduler->EmitSchedule();
684 // Free the scheduler state.
685 if (TimePassesIsEnabled) {
686 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
692 DOUT << "Selected machine code:\n";
696 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
698 MachineModuleInfo *MMI,
700 const TargetInstrInfo &TII) {
701 // Initialize the Fast-ISel state, if needed.
702 FastISel *FastIS = 0;
704 FastIS = TLI.createFastISel(MF, MMI, DW,
707 FuncInfo->StaticAllocaMap
709 , FuncInfo->CatchInfoLost
713 // Iterate over all basic blocks in the function.
714 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
715 BasicBlock *LLVMBB = &*I;
716 BB = FuncInfo->MBBMap[LLVMBB];
718 BasicBlock::iterator const Begin = LLVMBB->begin();
719 BasicBlock::iterator const End = LLVMBB->end();
720 BasicBlock::iterator BI = Begin;
722 // Lower any arguments needed in this block if this is the entry block.
723 bool SuppressFastISel = false;
724 if (LLVMBB == &Fn.getEntryBlock()) {
725 LowerArguments(LLVMBB);
727 // If any of the arguments has the byval attribute, forgo
728 // fast-isel in the entry block.
731 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
733 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
734 if (EnableFastISelVerbose || EnableFastISelAbort)
735 cerr << "FastISel skips entry block due to byval argument\n";
736 SuppressFastISel = true;
742 if (MMI && BB->isLandingPad()) {
743 // Add a label to mark the beginning of the landing pad. Deletion of the
744 // landing pad can thus be detected via the MachineModuleInfo.
745 unsigned LabelID = MMI->addLandingPad(BB);
747 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL);
748 BuildMI(BB, SDL->getCurDebugLoc(), II).addImm(LabelID);
750 // Mark exception register as live in.
751 unsigned Reg = TLI.getExceptionAddressRegister();
752 if (Reg) BB->addLiveIn(Reg);
754 // Mark exception selector register as live in.
755 Reg = TLI.getExceptionSelectorRegister();
756 if (Reg) BB->addLiveIn(Reg);
758 // FIXME: Hack around an exception handling flaw (PR1508): the personality
759 // function and list of typeids logically belong to the invoke (or, if you
760 // like, the basic block containing the invoke), and need to be associated
761 // with it in the dwarf exception handling tables. Currently however the
762 // information is provided by an intrinsic (eh.selector) that can be moved
763 // to unexpected places by the optimizers: if the unwind edge is critical,
764 // then breaking it can result in the intrinsics being in the successor of
765 // the landing pad, not the landing pad itself. This results in exceptions
766 // not being caught because no typeids are associated with the invoke.
767 // This may not be the only way things can go wrong, but it is the only way
768 // we try to work around for the moment.
769 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
771 if (Br && Br->isUnconditional()) { // Critical edge?
772 BasicBlock::iterator I, E;
773 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
774 if (isa<EHSelectorInst>(I))
778 // No catch info found - try to extract some from the successor.
779 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
783 // Before doing SelectionDAG ISel, see if FastISel has been requested.
784 if (FastIS && !SuppressFastISel) {
785 // Emit code for any incoming arguments. This must happen before
786 // beginning FastISel on the entry block.
787 if (LLVMBB == &Fn.getEntryBlock()) {
788 CurDAG->setRoot(SDL->getControlRoot());
792 FastIS->startNewBlock(BB);
793 // Do FastISel on as many instructions as possible.
794 for (; BI != End; ++BI) {
795 // Just before the terminator instruction, insert instructions to
796 // feed PHI nodes in successor blocks.
797 if (isa<TerminatorInst>(BI))
798 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
799 if (EnableFastISelVerbose || EnableFastISelAbort) {
800 cerr << "FastISel miss: ";
803 if (EnableFastISelAbort)
804 assert(0 && "FastISel didn't handle a PHI in a successor");
808 // First try normal tablegen-generated "fast" selection.
809 if (FastIS->SelectInstruction(BI))
812 // Next, try calling the target to attempt to handle the instruction.
813 if (FastIS->TargetSelectInstruction(BI))
816 // Then handle certain instructions as single-LLVM-Instruction blocks.
817 if (isa<CallInst>(BI)) {
818 if (EnableFastISelVerbose || EnableFastISelAbort) {
819 cerr << "FastISel missed call: ";
823 if (BI->getType() != Type::VoidTy) {
824 unsigned &R = FuncInfo->ValueMap[BI];
826 R = FuncInfo->CreateRegForValue(BI);
829 SelectBasicBlock(LLVMBB, BI, next(BI));
830 // If the instruction was codegen'd with multiple blocks,
831 // inform the FastISel object where to resume inserting.
832 FastIS->setCurrentBlock(BB);
836 // Otherwise, give up on FastISel for the rest of the block.
837 // For now, be a little lenient about non-branch terminators.
838 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
839 if (EnableFastISelVerbose || EnableFastISelAbort) {
840 cerr << "FastISel miss: ";
843 if (EnableFastISelAbort)
844 // The "fast" selector couldn't handle something and bailed.
845 // For the purpose of debugging, just abort.
846 assert(0 && "FastISel didn't select the entire block");
852 // Run SelectionDAG instruction selection on the remainder of the block
853 // not handled by FastISel. If FastISel is not run, this is the entire
856 SelectBasicBlock(LLVMBB, BI, End);
865 SelectionDAGISel::FinishBasicBlock() {
867 DOUT << "Target-post-processed machine code:\n";
870 DOUT << "Total amount of phi nodes to update: "
871 << SDL->PHINodesToUpdate.size() << "\n";
872 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
873 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first
874 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";);
876 // Next, now that we know what the last MBB the LLVM BB expanded is, update
877 // PHI nodes in successors.
878 if (SDL->SwitchCases.empty() &&
879 SDL->JTCases.empty() &&
880 SDL->BitTestCases.empty()) {
881 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
882 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
883 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
884 "This is not a machine PHI node that we are updating!");
885 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
887 PHI->addOperand(MachineOperand::CreateMBB(BB));
889 SDL->PHINodesToUpdate.clear();
893 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
894 // Lower header first, if it wasn't already lowered
895 if (!SDL->BitTestCases[i].Emitted) {
896 // Set the current basic block to the mbb we wish to insert the code into
897 BB = SDL->BitTestCases[i].Parent;
898 SDL->setCurrentBasicBlock(BB);
900 SDL->visitBitTestHeader(SDL->BitTestCases[i]);
901 CurDAG->setRoot(SDL->getRoot());
906 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
907 // Set the current basic block to the mbb we wish to insert the code into
908 BB = SDL->BitTestCases[i].Cases[j].ThisBB;
909 SDL->setCurrentBasicBlock(BB);
912 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
913 SDL->BitTestCases[i].Reg,
914 SDL->BitTestCases[i].Cases[j]);
916 SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
917 SDL->BitTestCases[i].Reg,
918 SDL->BitTestCases[i].Cases[j]);
921 CurDAG->setRoot(SDL->getRoot());
927 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
928 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
929 MachineBasicBlock *PHIBB = PHI->getParent();
930 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
931 "This is not a machine PHI node that we are updating!");
932 // This is "default" BB. We have two jumps to it. From "header" BB and
933 // from last "case" BB.
934 if (PHIBB == SDL->BitTestCases[i].Default) {
935 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
937 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
938 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
940 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
943 // One of "cases" BB.
944 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
946 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
947 if (cBB->succ_end() !=
948 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
949 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
951 PHI->addOperand(MachineOperand::CreateMBB(cBB));
956 SDL->BitTestCases.clear();
958 // If the JumpTable record is filled in, then we need to emit a jump table.
959 // Updating the PHI nodes is tricky in this case, since we need to determine
960 // whether the PHI is a successor of the range check MBB or the jump table MBB
961 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
962 // Lower header first, if it wasn't already lowered
963 if (!SDL->JTCases[i].first.Emitted) {
964 // Set the current basic block to the mbb we wish to insert the code into
965 BB = SDL->JTCases[i].first.HeaderBB;
966 SDL->setCurrentBasicBlock(BB);
968 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
969 CurDAG->setRoot(SDL->getRoot());
974 // Set the current basic block to the mbb we wish to insert the code into
975 BB = SDL->JTCases[i].second.MBB;
976 SDL->setCurrentBasicBlock(BB);
978 SDL->visitJumpTable(SDL->JTCases[i].second);
979 CurDAG->setRoot(SDL->getRoot());
984 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
985 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
986 MachineBasicBlock *PHIBB = PHI->getParent();
987 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
988 "This is not a machine PHI node that we are updating!");
989 // "default" BB. We can go there only from header BB.
990 if (PHIBB == SDL->JTCases[i].second.Default) {
991 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
993 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
995 // JT BB. Just iterate over successors here
996 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
997 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
999 PHI->addOperand(MachineOperand::CreateMBB(BB));
1003 SDL->JTCases.clear();
1005 // If the switch block involved a branch to one of the actual successors, we
1006 // need to update PHI nodes in that block.
1007 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
1008 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
1009 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
1010 "This is not a machine PHI node that we are updating!");
1011 if (BB->isSuccessor(PHI->getParent())) {
1012 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
1014 PHI->addOperand(MachineOperand::CreateMBB(BB));
1018 // If we generated any switch lowering information, build and codegen any
1019 // additional DAGs necessary.
1020 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
1021 // Set the current basic block to the mbb we wish to insert the code into
1022 BB = SDL->SwitchCases[i].ThisBB;
1023 SDL->setCurrentBasicBlock(BB);
1026 SDL->visitSwitchCase(SDL->SwitchCases[i]);
1027 CurDAG->setRoot(SDL->getRoot());
1028 CodeGenAndEmitDAG();
1031 // Handle any PHI nodes in successors of this chunk, as if we were coming
1032 // from the original BB before switch expansion. Note that PHI nodes can
1033 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1034 // handle them the right number of times.
1035 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1036 for (MachineBasicBlock::iterator Phi = BB->begin();
1037 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
1038 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
1039 for (unsigned pn = 0; ; ++pn) {
1040 assert(pn != SDL->PHINodesToUpdate.size() &&
1041 "Didn't find PHI entry!");
1042 if (SDL->PHINodesToUpdate[pn].first == Phi) {
1043 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
1045 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
1051 // Don't process RHS if same block as LHS.
1052 if (BB == SDL->SwitchCases[i].FalseBB)
1053 SDL->SwitchCases[i].FalseBB = 0;
1055 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1056 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
1057 SDL->SwitchCases[i].FalseBB = 0;
1059 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
1061 SDL->SwitchCases.clear();
1063 SDL->PHINodesToUpdate.clear();
1067 /// Schedule - Pick a safe ordering for instructions for each
1068 /// target node in the graph.
1070 ScheduleDAG *SelectionDAGISel::Schedule() {
1071 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1075 RegisterScheduler::setDefault(Ctor);
1078 ScheduleDAG *Scheduler = Ctor(this, Fast);
1079 Scheduler->Run(CurDAG, BB, BB->end(), BB->end());
1085 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1086 return new ScheduleHazardRecognizer();
1089 //===----------------------------------------------------------------------===//
1090 // Helper functions used by the generated instruction selector.
1091 //===----------------------------------------------------------------------===//
1092 // Calls to these methods are generated by tblgen.
1094 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1095 /// the dag combiner simplified the 255, we still want to match. RHS is the
1096 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1097 /// specified in the .td file (e.g. 255).
1098 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1099 int64_t DesiredMaskS) const {
1100 const APInt &ActualMask = RHS->getAPIntValue();
1101 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1103 // If the actual mask exactly matches, success!
1104 if (ActualMask == DesiredMask)
1107 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1108 if (ActualMask.intersects(~DesiredMask))
1111 // Otherwise, the DAG Combiner may have proven that the value coming in is
1112 // either already zero or is not demanded. Check for known zero input bits.
1113 APInt NeededMask = DesiredMask & ~ActualMask;
1114 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1117 // TODO: check to see if missing bits are just not demanded.
1119 // Otherwise, this pattern doesn't match.
1123 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1124 /// the dag combiner simplified the 255, we still want to match. RHS is the
1125 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1126 /// specified in the .td file (e.g. 255).
1127 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1128 int64_t DesiredMaskS) const {
1129 const APInt &ActualMask = RHS->getAPIntValue();
1130 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1132 // If the actual mask exactly matches, success!
1133 if (ActualMask == DesiredMask)
1136 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1137 if (ActualMask.intersects(~DesiredMask))
1140 // Otherwise, the DAG Combiner may have proven that the value coming in is
1141 // either already zero or is not demanded. Check for known zero input bits.
1142 APInt NeededMask = DesiredMask & ~ActualMask;
1144 APInt KnownZero, KnownOne;
1145 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1147 // If all the missing bits in the or are already known to be set, match!
1148 if ((NeededMask & KnownOne) == NeededMask)
1151 // TODO: check to see if missing bits are just not demanded.
1153 // Otherwise, this pattern doesn't match.
1158 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1159 /// by tblgen. Others should not call it.
1160 void SelectionDAGISel::
1161 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1162 std::vector<SDValue> InOps;
1163 std::swap(InOps, Ops);
1165 Ops.push_back(InOps[0]); // input chain.
1166 Ops.push_back(InOps[1]); // input asm string.
1168 unsigned i = 2, e = InOps.size();
1169 if (InOps[e-1].getValueType() == MVT::Flag)
1170 --e; // Don't process a flag operand if it is here.
1173 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1174 if ((Flags & 7) != 4 /*MEM*/) {
1175 // Just skip over this operand, copying the operands verbatim.
1176 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
1177 i += (Flags >> 3) + 1;
1179 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
1180 // Otherwise, this is a memory operand. Ask the target to select it.
1181 std::vector<SDValue> SelOps;
1182 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1183 cerr << "Could not match memory address. Inline asm failure!\n";
1187 // Add this to the output node.
1188 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
1189 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1191 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1196 // Add the flag input back if present.
1197 if (e != InOps.size())
1198 Ops.push_back(InOps.back());
1201 char SelectionDAGISel::ID = 0;