1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register"
85 static RegisterScheduler
86 defaultListDAGScheduler("default", " Best scheduler for the target",
87 createDefaultScheduler);
90 namespace { struct SDISelAsmOperandInfo; }
93 /// RegsForValue - This struct represents the physical registers that a
94 /// particular value is assigned and the type information about the value.
95 /// This is needed because values can be promoted into larger registers and
96 /// expanded into multiple smaller registers than the value.
97 struct VISIBILITY_HIDDEN RegsForValue {
98 /// Regs - This list holds the register (for legal and promoted values)
99 /// or register set (for expanded values) that the value should be assigned
101 std::vector<unsigned> Regs;
103 /// RegVT - The value type of each register.
105 MVT::ValueType RegVT;
107 /// ValueVT - The value type of the LLVM value, which may be promoted from
108 /// RegVT or made from merging the two expanded parts.
109 MVT::ValueType ValueVT;
111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
114 : RegVT(regvt), ValueVT(valuevt) {
117 RegsForValue(const std::vector<unsigned> ®s,
118 MVT::ValueType regvt, MVT::ValueType valuevt)
119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
123 /// this value and returns the result as a ValueVT value. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
125 /// If the Flag pointer is NULL, no flag is used.
126 SDOperand getCopyFromRegs(SelectionDAG &DAG,
127 SDOperand &Chain, SDOperand *Flag) const;
129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
130 /// specified value into the registers specified by this object. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 /// If the Flag pointer is NULL, no flag is used.
133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
134 SDOperand &Chain, SDOperand *Flag) const;
136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
137 /// operand list. This adds the code marker and includes the number of
138 /// values added into it.
139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
140 std::vector<SDOperand> &Ops) const;
145 //===--------------------------------------------------------------------===//
146 /// createDefaultScheduler - This creates an instruction scheduler appropriate
148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
150 MachineBasicBlock *BB) {
151 TargetLowering &TLI = IS->getTargetLowering();
153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
154 return createTDListDAGScheduler(IS, DAG, BB);
156 assert(TLI.getSchedulingPreference() ==
157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
158 return createBURRListDAGScheduler(IS, DAG, BB);
163 //===--------------------------------------------------------------------===//
164 /// FunctionLoweringInfo - This contains information that is global to a
165 /// function that is used when lowering a region of the function.
166 class FunctionLoweringInfo {
171 MachineRegisterInfo &RegInfo;
173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
178 /// ValueMap - Since we emit code for the function a basic block at a time,
179 /// we must remember which virtual registers hold the values for
180 /// cross-basic-block values.
181 DenseMap<const Value*, unsigned> ValueMap;
183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
184 /// the entry block. This allows the allocas to be efficiently referenced
185 /// anywhere in the function.
186 std::map<const AllocaInst*, int> StaticAllocaMap;
189 SmallSet<Instruction*, 8> CatchInfoLost;
190 SmallSet<Instruction*, 8> CatchInfoFound;
193 unsigned MakeReg(MVT::ValueType VT) {
194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
197 /// isExportedInst - Return true if the specified value is an instruction
198 /// exported from its block.
199 bool isExportedInst(const Value *V) {
200 return ValueMap.count(V);
203 unsigned CreateRegForValue(const Value *V);
205 unsigned InitializeRegForValue(const Value *V) {
206 unsigned &R = ValueMap[V];
207 assert(R == 0 && "Already initialized this value register!");
208 return R = CreateRegForValue(V);
213 /// isSelector - Return true if this instruction is a call to the
214 /// eh.selector intrinsic.
215 static bool isSelector(Instruction *I) {
216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
218 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
222 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
223 /// PHI nodes or outside of the basic block that defines it, or used by a
224 /// switch or atomic instruction, which may expand to multiple basic blocks.
225 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
226 if (isa<PHINode>(I)) return true;
227 BasicBlock *BB = I->getParent();
228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
230 // FIXME: Remove switchinst special case.
231 isa<SwitchInst>(*UI))
236 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
237 /// entry block, return true. This includes arguments used by switches, since
238 /// the switch may expand into multiple basic blocks.
239 static bool isOnlyUsedInEntryBlock(Argument *A) {
240 BasicBlock *Entry = A->getParent()->begin();
241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
243 return false; // Use not in entry block.
247 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
248 Function &fn, MachineFunction &mf)
249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
251 // Create a vreg for each argument register that is not dead and is used
252 // outside of the entry block for the function.
253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
255 if (!isOnlyUsedInEntryBlock(AI))
256 InitializeRegForValue(AI);
258 // Initialize the mapping of values to registers. This is only set up for
259 // instruction values that are used outside of the block that defines
261 Function::iterator BB = Fn.begin(), EB = Fn.end();
262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
265 const Type *Ty = AI->getAllocatedType();
266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
271 TySize *= CUI->getZExtValue(); // Get total allocated size.
272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
273 StaticAllocaMap[AI] =
274 MF.getFrameInfo()->CreateStackObject(TySize, Align);
277 for (; BB != EB; ++BB)
278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
280 if (!isa<AllocaInst>(I) ||
281 !StaticAllocaMap.count(cast<AllocaInst>(I)))
282 InitializeRegForValue(I);
284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
285 // also creates the initial PHI MachineInstrs, though none of the input
286 // operands are populated.
287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
288 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
290 MF.getBasicBlockList().push_back(MBB);
292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
296 if (PN->use_empty()) continue;
298 MVT::ValueType VT = TLI.getValueType(PN->getType());
299 unsigned NumRegisters = TLI.getNumRegisters(VT);
300 unsigned PHIReg = ValueMap[PN];
301 assert(PHIReg && "PHI node does not have an assigned virtual register!");
302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
303 for (unsigned i = 0; i != NumRegisters; ++i)
304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
309 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
310 /// the correctly promoted or expanded types. Assign these registers
311 /// consecutive vreg numbers and return the first assigned number.
312 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
313 MVT::ValueType VT = TLI.getValueType(V->getType());
315 unsigned NumRegisters = TLI.getNumRegisters(VT);
316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
318 unsigned R = MakeReg(RegisterVT);
319 for (unsigned i = 1; i != NumRegisters; ++i)
325 //===----------------------------------------------------------------------===//
326 /// SelectionDAGLowering - This is the common target-independent lowering
327 /// implementation that is parameterized by a TargetLowering object.
328 /// Also, targets can overload any lowering method.
331 class SelectionDAGLowering {
332 MachineBasicBlock *CurMBB;
334 DenseMap<const Value*, SDOperand> NodeMap;
336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
337 /// them up and then emit token factor nodes when possible. This allows us to
338 /// get simple disambiguation between loads without worrying about alias
340 std::vector<SDOperand> PendingLoads;
342 /// PendingExports - CopyToReg nodes that copy values to virtual registers
343 /// for export to other blocks need to be emitted before any terminator
344 /// instruction, but they have no other ordering requirements. We bunch them
345 /// up and the emit a single tokenfactor for them just before terminator
347 std::vector<SDOperand> PendingExports;
349 /// Case - A struct to record the Value for a switch case, and the
350 /// case's target basic block.
354 MachineBasicBlock* BB;
356 Case() : Low(0), High(0), BB(0) { }
357 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
358 Low(low), High(high), BB(bb) { }
359 uint64_t size() const {
360 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
361 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
362 return (rHigh - rLow + 1ULL);
368 MachineBasicBlock* BB;
371 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
372 Mask(mask), BB(bb), Bits(bits) { }
375 typedef std::vector<Case> CaseVector;
376 typedef std::vector<CaseBits> CaseBitsVector;
377 typedef CaseVector::iterator CaseItr;
378 typedef std::pair<CaseItr, CaseItr> CaseRange;
380 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
381 /// of conditional branches.
383 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
384 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
386 /// CaseBB - The MBB in which to emit the compare and branch
387 MachineBasicBlock *CaseBB;
388 /// LT, GE - If nonzero, we know the current case value must be less-than or
389 /// greater-than-or-equal-to these Constants.
392 /// Range - A pair of iterators representing the range of case values to be
393 /// processed at this point in the binary search tree.
397 typedef std::vector<CaseRec> CaseRecVector;
399 /// The comparison function for sorting the switch case values in the vector.
400 /// WARNING: Case ranges should be disjoint!
402 bool operator () (const Case& C1, const Case& C2) {
403 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
404 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
405 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
406 return CI1->getValue().slt(CI2->getValue());
411 bool operator () (const CaseBits& C1, const CaseBits& C2) {
412 return C1.Bits > C2.Bits;
416 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
419 // TLI - This is information that describes the available target features we
420 // need for lowering. This indicates when operations are unavailable,
421 // implemented with a libcall, etc.
424 const TargetData *TD;
427 /// SwitchCases - Vector of CaseBlock structures used to communicate
428 /// SwitchInst code generation information.
429 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
430 /// JTCases - Vector of JumpTable structures used to communicate
431 /// SwitchInst code generation information.
432 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
433 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
435 /// FuncInfo - Information about the function as a whole.
437 FunctionLoweringInfo &FuncInfo;
439 /// GCI - Garbage collection metadata for the function.
440 CollectorMetadata *GCI;
442 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
444 FunctionLoweringInfo &funcinfo,
445 CollectorMetadata *gci)
446 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
447 FuncInfo(funcinfo), GCI(gci) {
450 /// getRoot - Return the current virtual root of the Selection DAG,
451 /// flushing any PendingLoad items. This must be done before emitting
452 /// a store or any other node that may need to be ordered after any
453 /// prior load instructions.
455 SDOperand getRoot() {
456 if (PendingLoads.empty())
457 return DAG.getRoot();
459 if (PendingLoads.size() == 1) {
460 SDOperand Root = PendingLoads[0];
462 PendingLoads.clear();
466 // Otherwise, we have to make a token factor node.
467 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
468 &PendingLoads[0], PendingLoads.size());
469 PendingLoads.clear();
474 /// getControlRoot - Similar to getRoot, but instead of flushing all the
475 /// PendingLoad items, flush all the PendingExports items. It is necessary
476 /// to do this before emitting a terminator instruction.
478 SDOperand getControlRoot() {
479 SDOperand Root = DAG.getRoot();
481 if (PendingExports.empty())
484 // Turn all of the CopyToReg chains into one factored node.
485 if (Root.getOpcode() != ISD::EntryToken) {
486 unsigned i = 0, e = PendingExports.size();
487 for (; i != e; ++i) {
488 assert(PendingExports[i].Val->getNumOperands() > 1);
489 if (PendingExports[i].Val->getOperand(0) == Root)
490 break; // Don't add the root if we already indirectly depend on it.
494 PendingExports.push_back(Root);
497 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
499 PendingExports.size());
500 PendingExports.clear();
505 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
507 void visit(Instruction &I) { visit(I.getOpcode(), I); }
509 void visit(unsigned Opcode, User &I) {
510 // Note: this doesn't use InstVisitor, because it has to work with
511 // ConstantExpr's in addition to instructions.
513 default: assert(0 && "Unknown instruction type encountered!");
515 // Build the switch statement using the Instruction.def file.
516 #define HANDLE_INST(NUM, OPCODE, CLASS) \
517 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
518 #include "llvm/Instruction.def"
522 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
524 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
525 const Value *SV, SDOperand Root,
526 bool isVolatile, unsigned Alignment);
528 SDOperand getValue(const Value *V);
530 void setValue(const Value *V, SDOperand NewN) {
531 SDOperand &N = NodeMap[V];
532 assert(N.Val == 0 && "Already set a value for this node!");
536 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
537 std::set<unsigned> &OutputRegs,
538 std::set<unsigned> &InputRegs);
540 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
541 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
543 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
544 void ExportFromCurrentBlock(Value *V);
545 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
546 MachineBasicBlock *LandingPad = NULL);
548 // Terminator instructions.
549 void visitRet(ReturnInst &I);
550 void visitBr(BranchInst &I);
551 void visitSwitch(SwitchInst &I);
552 void visitUnreachable(UnreachableInst &I) { /* noop */ }
554 // Helpers for visitSwitch
555 bool handleSmallSwitchRange(CaseRec& CR,
556 CaseRecVector& WorkList,
558 MachineBasicBlock* Default);
559 bool handleJTSwitchCase(CaseRec& CR,
560 CaseRecVector& WorkList,
562 MachineBasicBlock* Default);
563 bool handleBTSplitSwitchCase(CaseRec& CR,
564 CaseRecVector& WorkList,
566 MachineBasicBlock* Default);
567 bool handleBitTestsSwitchCase(CaseRec& CR,
568 CaseRecVector& WorkList,
570 MachineBasicBlock* Default);
571 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
572 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
573 void visitBitTestCase(MachineBasicBlock* NextMBB,
575 SelectionDAGISel::BitTestCase &B);
576 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
577 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
578 SelectionDAGISel::JumpTableHeader &JTH);
580 // These all get lowered before this pass.
581 void visitInvoke(InvokeInst &I);
582 void visitUnwind(UnwindInst &I);
584 void visitBinary(User &I, unsigned OpCode);
585 void visitShift(User &I, unsigned Opcode);
586 void visitAdd(User &I) {
587 if (I.getType()->isFPOrFPVector())
588 visitBinary(I, ISD::FADD);
590 visitBinary(I, ISD::ADD);
592 void visitSub(User &I);
593 void visitMul(User &I) {
594 if (I.getType()->isFPOrFPVector())
595 visitBinary(I, ISD::FMUL);
597 visitBinary(I, ISD::MUL);
599 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
600 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
601 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
602 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
603 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
604 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
605 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
606 void visitOr (User &I) { visitBinary(I, ISD::OR); }
607 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
608 void visitShl (User &I) { visitShift(I, ISD::SHL); }
609 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
610 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
611 void visitICmp(User &I);
612 void visitFCmp(User &I);
613 // Visit the conversion instructions
614 void visitTrunc(User &I);
615 void visitZExt(User &I);
616 void visitSExt(User &I);
617 void visitFPTrunc(User &I);
618 void visitFPExt(User &I);
619 void visitFPToUI(User &I);
620 void visitFPToSI(User &I);
621 void visitUIToFP(User &I);
622 void visitSIToFP(User &I);
623 void visitPtrToInt(User &I);
624 void visitIntToPtr(User &I);
625 void visitBitCast(User &I);
627 void visitExtractElement(User &I);
628 void visitInsertElement(User &I);
629 void visitShuffleVector(User &I);
631 void visitGetElementPtr(User &I);
632 void visitSelect(User &I);
634 void visitMalloc(MallocInst &I);
635 void visitFree(FreeInst &I);
636 void visitAlloca(AllocaInst &I);
637 void visitLoad(LoadInst &I);
638 void visitStore(StoreInst &I);
639 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
640 void visitCall(CallInst &I);
641 void visitInlineAsm(CallSite CS);
642 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
643 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
645 void visitVAStart(CallInst &I);
646 void visitVAArg(VAArgInst &I);
647 void visitVAEnd(CallInst &I);
648 void visitVACopy(CallInst &I);
650 void visitMemIntrinsic(CallInst &I, unsigned Op);
652 void visitGetResult(GetResultInst &I);
654 void visitUserOp1(Instruction &I) {
655 assert(0 && "UserOp1 should not exist at instruction selection time!");
658 void visitUserOp2(Instruction &I) {
659 assert(0 && "UserOp2 should not exist at instruction selection time!");
663 } // end namespace llvm
666 /// getCopyFromParts - Create a value that contains the specified legal parts
667 /// combined into the value they represent. If the parts combine to a type
668 /// larger then ValueVT then AssertOp can be used to specify whether the extra
669 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
670 /// (ISD::AssertSext).
671 static SDOperand getCopyFromParts(SelectionDAG &DAG,
672 const SDOperand *Parts,
674 MVT::ValueType PartVT,
675 MVT::ValueType ValueVT,
676 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
677 assert(NumParts > 0 && "No parts to assemble!");
678 TargetLowering &TLI = DAG.getTargetLoweringInfo();
679 SDOperand Val = Parts[0];
682 // Assemble the value from multiple parts.
683 if (!MVT::isVector(ValueVT)) {
684 unsigned PartBits = MVT::getSizeInBits(PartVT);
685 unsigned ValueBits = MVT::getSizeInBits(ValueVT);
687 // Assemble the power of 2 part.
688 unsigned RoundParts = NumParts & (NumParts - 1) ?
689 1 << Log2_32(NumParts) : NumParts;
690 unsigned RoundBits = PartBits * RoundParts;
691 MVT::ValueType RoundVT = RoundBits == ValueBits ?
692 ValueVT : MVT::getIntegerType(RoundBits);
695 if (RoundParts > 2) {
696 MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2);
697 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
698 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
704 if (TLI.isBigEndian())
706 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
708 if (RoundParts < NumParts) {
709 // Assemble the trailing non-power-of-2 part.
710 unsigned OddParts = NumParts - RoundParts;
711 MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits);
712 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
714 // Combine the round and odd parts.
716 if (TLI.isBigEndian())
718 MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits);
719 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
720 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
721 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
722 TLI.getShiftAmountTy()));
723 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
724 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
727 // Handle a multi-element vector.
728 MVT::ValueType IntermediateVT, RegisterVT;
729 unsigned NumIntermediates;
731 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
734 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
735 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
736 assert(RegisterVT == Parts[0].getValueType() &&
737 "Part type doesn't match part!");
739 // Assemble the parts into intermediate operands.
740 SmallVector<SDOperand, 8> Ops(NumIntermediates);
741 if (NumIntermediates == NumParts) {
742 // If the register was not expanded, truncate or copy the value,
744 for (unsigned i = 0; i != NumParts; ++i)
745 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
746 PartVT, IntermediateVT);
747 } else if (NumParts > 0) {
748 // If the intermediate type was expanded, build the intermediate operands
750 assert(NumParts % NumIntermediates == 0 &&
751 "Must expand into a divisible number of parts!");
752 unsigned Factor = NumParts / NumIntermediates;
753 for (unsigned i = 0; i != NumIntermediates; ++i)
754 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
755 PartVT, IntermediateVT);
758 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
760 Val = DAG.getNode(MVT::isVector(IntermediateVT) ?
761 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
762 ValueVT, &Ops[0], NumIntermediates);
766 // There is now one part, held in Val. Correct it to match ValueVT.
767 PartVT = Val.getValueType();
769 if (PartVT == ValueVT)
772 if (MVT::isVector(PartVT)) {
773 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
774 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
777 if (MVT::isVector(ValueVT)) {
778 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
779 MVT::getVectorNumElements(ValueVT) == 1 &&
780 "Only trivial scalar-to-vector conversions should get here!");
781 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
784 if (MVT::isInteger(PartVT) &&
785 MVT::isInteger(ValueVT)) {
786 if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) {
787 // For a truncate, see if we have any information to
788 // indicate whether the truncated bits will always be
789 // zero or sign-extension.
790 if (AssertOp != ISD::DELETED_NODE)
791 Val = DAG.getNode(AssertOp, PartVT, Val,
792 DAG.getValueType(ValueVT));
793 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
795 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
799 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
800 if (ValueVT < Val.getValueType())
801 // FP_ROUND's are always exact here.
802 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
803 DAG.getIntPtrConstant(1));
804 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
807 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
808 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
810 assert(0 && "Unknown mismatch!");
814 /// getCopyToParts - Create a series of nodes that contain the specified value
815 /// split into legal parts. If the parts contain more bits than Val, then, for
816 /// integers, ExtendKind can be used to specify how to generate the extra bits.
817 static void getCopyToParts(SelectionDAG &DAG,
821 MVT::ValueType PartVT,
822 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
823 TargetLowering &TLI = DAG.getTargetLoweringInfo();
824 MVT::ValueType PtrVT = TLI.getPointerTy();
825 MVT::ValueType ValueVT = Val.getValueType();
826 unsigned PartBits = MVT::getSizeInBits(PartVT);
827 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
832 if (!MVT::isVector(ValueVT)) {
833 if (PartVT == ValueVT) {
834 assert(NumParts == 1 && "No-op copy with multiple parts!");
839 if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) {
840 // If the parts cover more bits than the value has, promote the value.
841 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
842 assert(NumParts == 1 && "Do not know what to promote to!");
843 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
844 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
845 ValueVT = MVT::getIntegerType(NumParts * PartBits);
846 Val = DAG.getNode(ExtendKind, ValueVT, Val);
848 assert(0 && "Unknown mismatch!");
850 } else if (PartBits == MVT::getSizeInBits(ValueVT)) {
851 // Different types of the same size.
852 assert(NumParts == 1 && PartVT != ValueVT);
853 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
854 } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) {
855 // If the parts cover less bits than value has, truncate the value.
856 if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
857 ValueVT = MVT::getIntegerType(NumParts * PartBits);
858 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
860 assert(0 && "Unknown mismatch!");
864 // The value may have changed - recompute ValueVT.
865 ValueVT = Val.getValueType();
866 assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) &&
867 "Failed to tile the value with PartVT!");
870 assert(PartVT == ValueVT && "Type conversion failed!");
875 // Expand the value into multiple parts.
876 if (NumParts & (NumParts - 1)) {
877 // The number of parts is not a power of 2. Split off and copy the tail.
878 assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) &&
879 "Do not know what to expand to!");
880 unsigned RoundParts = 1 << Log2_32(NumParts);
881 unsigned RoundBits = RoundParts * PartBits;
882 unsigned OddParts = NumParts - RoundParts;
883 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
884 DAG.getConstant(RoundBits,
885 TLI.getShiftAmountTy()));
886 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
887 if (TLI.isBigEndian())
888 // The odd parts were reversed by getCopyToParts - unreverse them.
889 std::reverse(Parts + RoundParts, Parts + NumParts);
890 NumParts = RoundParts;
891 ValueVT = MVT::getIntegerType(NumParts * PartBits);
892 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
895 // The number of parts is a power of 2. Repeatedly bisect the value using
897 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
898 MVT::getIntegerType(MVT::getSizeInBits(ValueVT)),
900 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
901 for (unsigned i = 0; i < NumParts; i += StepSize) {
902 unsigned ThisBits = StepSize * PartBits / 2;
903 MVT::ValueType ThisVT = MVT::getIntegerType (ThisBits);
904 SDOperand &Part0 = Parts[i];
905 SDOperand &Part1 = Parts[i+StepSize/2];
907 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
908 DAG.getConstant(1, PtrVT));
909 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
910 DAG.getConstant(0, PtrVT));
912 if (ThisBits == PartBits && ThisVT != PartVT) {
913 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
914 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
919 if (TLI.isBigEndian())
920 std::reverse(Parts, Parts + NumParts);
927 if (PartVT != ValueVT) {
928 if (MVT::isVector(PartVT)) {
929 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
931 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
932 MVT::getVectorNumElements(ValueVT) == 1 &&
933 "Only trivial vector-to-scalar conversions should get here!");
934 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
935 DAG.getConstant(0, PtrVT));
943 // Handle a multi-element vector.
944 MVT::ValueType IntermediateVT, RegisterVT;
945 unsigned NumIntermediates;
947 DAG.getTargetLoweringInfo()
948 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
950 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
952 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
953 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
955 // Split the vector into intermediate operands.
956 SmallVector<SDOperand, 8> Ops(NumIntermediates);
957 for (unsigned i = 0; i != NumIntermediates; ++i)
958 if (MVT::isVector(IntermediateVT))
959 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
961 DAG.getConstant(i * (NumElements / NumIntermediates),
964 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
966 DAG.getConstant(i, PtrVT));
968 // Split the intermediate operands into legal parts.
969 if (NumParts == NumIntermediates) {
970 // If the register was not expanded, promote or copy the value,
972 for (unsigned i = 0; i != NumParts; ++i)
973 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
974 } else if (NumParts > 0) {
975 // If the intermediate type was expanded, split each the value into
977 assert(NumParts % NumIntermediates == 0 &&
978 "Must expand into a divisible number of parts!");
979 unsigned Factor = NumParts / NumIntermediates;
980 for (unsigned i = 0; i != NumIntermediates; ++i)
981 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
986 SDOperand SelectionDAGLowering::getValue(const Value *V) {
987 SDOperand &N = NodeMap[V];
990 const Type *VTy = V->getType();
991 MVT::ValueType VT = TLI.getValueType(VTy);
992 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
993 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
994 visit(CE->getOpcode(), *CE);
995 SDOperand N1 = NodeMap[V];
996 assert(N1.Val && "visit didn't populate the ValueMap!");
998 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
999 return N = DAG.getGlobalAddress(GV, VT);
1000 } else if (isa<ConstantPointerNull>(C)) {
1001 return N = DAG.getConstant(0, TLI.getPointerTy());
1002 } else if (isa<UndefValue>(C)) {
1003 if (!isa<VectorType>(VTy))
1004 return N = DAG.getNode(ISD::UNDEF, VT);
1006 // Create a BUILD_VECTOR of undef nodes.
1007 const VectorType *PTy = cast<VectorType>(VTy);
1008 unsigned NumElements = PTy->getNumElements();
1009 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1011 SmallVector<SDOperand, 8> Ops;
1012 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
1014 // Create a VConstant node with generic Vector type.
1015 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
1016 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
1017 &Ops[0], Ops.size());
1018 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
1019 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1020 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
1021 unsigned NumElements = PTy->getNumElements();
1022 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1024 // Now that we know the number and type of the elements, push a
1025 // Constant or ConstantFP node onto the ops list for each element of
1026 // the vector constant.
1027 SmallVector<SDOperand, 8> Ops;
1028 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1029 for (unsigned i = 0; i != NumElements; ++i)
1030 Ops.push_back(getValue(CP->getOperand(i)));
1032 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1034 if (MVT::isFloatingPoint(PVT))
1035 Op = DAG.getConstantFP(0, PVT);
1037 Op = DAG.getConstant(0, PVT);
1038 Ops.assign(NumElements, Op);
1041 // Create a BUILD_VECTOR node.
1042 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
1043 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
1046 // Canonicalize all constant ints to be unsigned.
1047 return N = DAG.getConstant(cast<ConstantInt>(C)->getValue(),VT);
1051 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1052 std::map<const AllocaInst*, int>::iterator SI =
1053 FuncInfo.StaticAllocaMap.find(AI);
1054 if (SI != FuncInfo.StaticAllocaMap.end())
1055 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1058 unsigned InReg = FuncInfo.ValueMap[V];
1059 assert(InReg && "Value not in map!");
1061 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
1062 unsigned NumRegs = TLI.getNumRegisters(VT);
1064 std::vector<unsigned> Regs(NumRegs);
1065 for (unsigned i = 0; i != NumRegs; ++i)
1066 Regs[i] = InReg + i;
1068 RegsForValue RFV(Regs, RegisterVT, VT);
1069 SDOperand Chain = DAG.getEntryNode();
1071 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1075 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1076 if (I.getNumOperands() == 0) {
1077 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1080 SmallVector<SDOperand, 8> NewValues;
1081 NewValues.push_back(getControlRoot());
1082 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1083 SDOperand RetOp = getValue(I.getOperand(i));
1084 MVT::ValueType VT = RetOp.getValueType();
1086 // FIXME: C calling convention requires the return type to be promoted to
1087 // at least 32-bit. But this is not necessary for non-C calling conventions.
1088 if (MVT::isInteger(VT)) {
1089 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32);
1090 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT))
1094 unsigned NumParts = TLI.getNumRegisters(VT);
1095 MVT::ValueType PartVT = TLI.getRegisterType(VT);
1096 SmallVector<SDOperand, 4> Parts(NumParts);
1097 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1099 const Function *F = I.getParent()->getParent();
1100 if (F->paramHasAttr(0, ParamAttr::SExt))
1101 ExtendKind = ISD::SIGN_EXTEND;
1102 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1103 ExtendKind = ISD::ZERO_EXTEND;
1105 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
1107 for (unsigned i = 0; i < NumParts; ++i) {
1108 NewValues.push_back(Parts[i]);
1109 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1112 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1113 &NewValues[0], NewValues.size()));
1116 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1117 /// the current basic block, add it to ValueMap now so that we'll get a
1119 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1120 // No need to export constants.
1121 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1123 // Already exported?
1124 if (FuncInfo.isExportedInst(V)) return;
1126 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1127 CopyValueToVirtualRegister(V, Reg);
1130 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1131 const BasicBlock *FromBB) {
1132 // The operands of the setcc have to be in this block. We don't know
1133 // how to export them from some other block.
1134 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1135 // Can export from current BB.
1136 if (VI->getParent() == FromBB)
1139 // Is already exported, noop.
1140 return FuncInfo.isExportedInst(V);
1143 // If this is an argument, we can export it if the BB is the entry block or
1144 // if it is already exported.
1145 if (isa<Argument>(V)) {
1146 if (FromBB == &FromBB->getParent()->getEntryBlock())
1149 // Otherwise, can only export this if it is already exported.
1150 return FuncInfo.isExportedInst(V);
1153 // Otherwise, constants can always be exported.
1157 static bool InBlock(const Value *V, const BasicBlock *BB) {
1158 if (const Instruction *I = dyn_cast<Instruction>(V))
1159 return I->getParent() == BB;
1163 /// FindMergedConditions - If Cond is an expression like
1164 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1165 MachineBasicBlock *TBB,
1166 MachineBasicBlock *FBB,
1167 MachineBasicBlock *CurBB,
1169 // If this node is not part of the or/and tree, emit it as a branch.
1170 Instruction *BOp = dyn_cast<Instruction>(Cond);
1172 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1173 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1174 BOp->getParent() != CurBB->getBasicBlock() ||
1175 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1176 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1177 const BasicBlock *BB = CurBB->getBasicBlock();
1179 // If the leaf of the tree is a comparison, merge the condition into
1181 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1182 // The operands of the cmp have to be in this block. We don't know
1183 // how to export them from some other block. If this is the first block
1184 // of the sequence, no exporting is needed.
1186 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1187 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1188 BOp = cast<Instruction>(Cond);
1189 ISD::CondCode Condition;
1190 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1191 switch (IC->getPredicate()) {
1192 default: assert(0 && "Unknown icmp predicate opcode!");
1193 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1194 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1195 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1196 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1197 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1198 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1199 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1200 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1201 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1202 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1204 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1205 ISD::CondCode FPC, FOC;
1206 switch (FC->getPredicate()) {
1207 default: assert(0 && "Unknown fcmp predicate opcode!");
1208 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1209 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1210 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1211 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1212 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1213 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1214 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1215 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1216 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1217 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1218 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1219 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1220 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1221 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1222 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1223 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1225 if (FiniteOnlyFPMath())
1230 Condition = ISD::SETEQ; // silence warning.
1231 assert(0 && "Unknown compare instruction");
1234 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1235 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1236 SwitchCases.push_back(CB);
1240 // Create a CaseBlock record representing this branch.
1241 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1242 NULL, TBB, FBB, CurBB);
1243 SwitchCases.push_back(CB);
1248 // Create TmpBB after CurBB.
1249 MachineFunction::iterator BBI = CurBB;
1250 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1251 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1253 if (Opc == Instruction::Or) {
1254 // Codegen X | Y as:
1262 // Emit the LHS condition.
1263 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1265 // Emit the RHS condition into TmpBB.
1266 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1268 assert(Opc == Instruction::And && "Unknown merge op!");
1269 // Codegen X & Y as:
1276 // This requires creation of TmpBB after CurBB.
1278 // Emit the LHS condition.
1279 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1281 // Emit the RHS condition into TmpBB.
1282 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1286 /// If the set of cases should be emitted as a series of branches, return true.
1287 /// If we should emit this as a bunch of and/or'd together conditions, return
1290 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1291 if (Cases.size() != 2) return true;
1293 // If this is two comparisons of the same values or'd or and'd together, they
1294 // will get folded into a single comparison, so don't emit two blocks.
1295 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1296 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1297 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1298 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1305 void SelectionDAGLowering::visitBr(BranchInst &I) {
1306 // Update machine-CFG edges.
1307 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1309 // Figure out which block is immediately after the current one.
1310 MachineBasicBlock *NextBlock = 0;
1311 MachineFunction::iterator BBI = CurMBB;
1312 if (++BBI != CurMBB->getParent()->end())
1315 if (I.isUnconditional()) {
1316 // If this is not a fall-through branch, emit the branch.
1317 if (Succ0MBB != NextBlock)
1318 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1319 DAG.getBasicBlock(Succ0MBB)));
1321 // Update machine-CFG edges.
1322 CurMBB->addSuccessor(Succ0MBB);
1326 // If this condition is one of the special cases we handle, do special stuff
1328 Value *CondVal = I.getCondition();
1329 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1331 // If this is a series of conditions that are or'd or and'd together, emit
1332 // this as a sequence of branches instead of setcc's with and/or operations.
1333 // For example, instead of something like:
1346 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1347 if (BOp->hasOneUse() &&
1348 (BOp->getOpcode() == Instruction::And ||
1349 BOp->getOpcode() == Instruction::Or)) {
1350 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1351 // If the compares in later blocks need to use values not currently
1352 // exported from this block, export them now. This block should always
1353 // be the first entry.
1354 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1356 // Allow some cases to be rejected.
1357 if (ShouldEmitAsBranches(SwitchCases)) {
1358 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1359 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1360 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1363 // Emit the branch for this block.
1364 visitSwitchCase(SwitchCases[0]);
1365 SwitchCases.erase(SwitchCases.begin());
1369 // Okay, we decided not to do this, remove any inserted MBB's and clear
1371 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1372 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1374 SwitchCases.clear();
1378 // Create a CaseBlock record representing this branch.
1379 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1380 NULL, Succ0MBB, Succ1MBB, CurMBB);
1381 // Use visitSwitchCase to actually insert the fast branch sequence for this
1383 visitSwitchCase(CB);
1386 /// visitSwitchCase - Emits the necessary code to represent a single node in
1387 /// the binary search tree resulting from lowering a switch instruction.
1388 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1390 SDOperand CondLHS = getValue(CB.CmpLHS);
1392 // Build the setcc now.
1393 if (CB.CmpMHS == NULL) {
1394 // Fold "(X == true)" to X and "(X == false)" to !X to
1395 // handle common cases produced by branch lowering.
1396 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1398 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1399 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1400 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1402 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1404 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1406 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1407 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1409 SDOperand CmpOp = getValue(CB.CmpMHS);
1410 MVT::ValueType VT = CmpOp.getValueType();
1412 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1413 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1415 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1416 Cond = DAG.getSetCC(MVT::i1, SUB,
1417 DAG.getConstant(High-Low, VT), ISD::SETULE);
1422 // Set NextBlock to be the MBB immediately after the current one, if any.
1423 // This is used to avoid emitting unnecessary branches to the next block.
1424 MachineBasicBlock *NextBlock = 0;
1425 MachineFunction::iterator BBI = CurMBB;
1426 if (++BBI != CurMBB->getParent()->end())
1429 // If the lhs block is the next block, invert the condition so that we can
1430 // fall through to the lhs instead of the rhs block.
1431 if (CB.TrueBB == NextBlock) {
1432 std::swap(CB.TrueBB, CB.FalseBB);
1433 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1434 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1436 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1437 DAG.getBasicBlock(CB.TrueBB));
1438 if (CB.FalseBB == NextBlock)
1439 DAG.setRoot(BrCond);
1441 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1442 DAG.getBasicBlock(CB.FalseBB)));
1443 // Update successor info
1444 CurMBB->addSuccessor(CB.TrueBB);
1445 CurMBB->addSuccessor(CB.FalseBB);
1448 /// visitJumpTable - Emit JumpTable node in the current MBB
1449 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1450 // Emit the code for the jump table
1451 assert(JT.Reg != -1U && "Should lower JT Header first!");
1452 MVT::ValueType PTy = TLI.getPointerTy();
1453 SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1454 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1455 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1460 /// visitJumpTableHeader - This function emits necessary code to produce index
1461 /// in the JumpTable from switch case.
1462 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1463 SelectionDAGISel::JumpTableHeader &JTH) {
1464 // Subtract the lowest switch case value from the value being switched on
1465 // and conditional branch to default mbb if the result is greater than the
1466 // difference between smallest and largest cases.
1467 SDOperand SwitchOp = getValue(JTH.SValue);
1468 MVT::ValueType VT = SwitchOp.getValueType();
1469 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1470 DAG.getConstant(JTH.First, VT));
1472 // The SDNode we just created, which holds the value being switched on
1473 // minus the the smallest case value, needs to be copied to a virtual
1474 // register so it can be used as an index into the jump table in a
1475 // subsequent basic block. This value may be smaller or larger than the
1476 // target's pointer type, and therefore require extension or truncating.
1477 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1478 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1480 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1482 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1483 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1484 JT.Reg = JumpTableReg;
1486 // Emit the range check for the jump table, and branch to the default
1487 // block for the switch statement if the value being switched on exceeds
1488 // the largest case in the switch.
1489 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1490 DAG.getConstant(JTH.Last-JTH.First,VT),
1493 // Set NextBlock to be the MBB immediately after the current one, if any.
1494 // This is used to avoid emitting unnecessary branches to the next block.
1495 MachineBasicBlock *NextBlock = 0;
1496 MachineFunction::iterator BBI = CurMBB;
1497 if (++BBI != CurMBB->getParent()->end())
1500 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1501 DAG.getBasicBlock(JT.Default));
1503 if (JT.MBB == NextBlock)
1504 DAG.setRoot(BrCond);
1506 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1507 DAG.getBasicBlock(JT.MBB)));
1512 /// visitBitTestHeader - This function emits necessary code to produce value
1513 /// suitable for "bit tests"
1514 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1515 // Subtract the minimum value
1516 SDOperand SwitchOp = getValue(B.SValue);
1517 MVT::ValueType VT = SwitchOp.getValueType();
1518 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1519 DAG.getConstant(B.First, VT));
1522 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1523 DAG.getConstant(B.Range, VT),
1527 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1528 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1530 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1532 // Make desired shift
1533 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1534 DAG.getConstant(1, TLI.getPointerTy()),
1537 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1538 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1541 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1542 DAG.getBasicBlock(B.Default));
1544 // Set NextBlock to be the MBB immediately after the current one, if any.
1545 // This is used to avoid emitting unnecessary branches to the next block.
1546 MachineBasicBlock *NextBlock = 0;
1547 MachineFunction::iterator BBI = CurMBB;
1548 if (++BBI != CurMBB->getParent()->end())
1551 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1552 if (MBB == NextBlock)
1553 DAG.setRoot(BrRange);
1555 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1556 DAG.getBasicBlock(MBB)));
1558 CurMBB->addSuccessor(B.Default);
1559 CurMBB->addSuccessor(MBB);
1564 /// visitBitTestCase - this function produces one "bit test"
1565 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1567 SelectionDAGISel::BitTestCase &B) {
1568 // Emit bit tests and jumps
1569 SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, TLI.getPointerTy());
1571 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1573 DAG.getConstant(B.Mask,
1574 TLI.getPointerTy()));
1575 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1576 DAG.getConstant(0, TLI.getPointerTy()),
1578 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1579 AndCmp, DAG.getBasicBlock(B.TargetBB));
1581 // Set NextBlock to be the MBB immediately after the current one, if any.
1582 // This is used to avoid emitting unnecessary branches to the next block.
1583 MachineBasicBlock *NextBlock = 0;
1584 MachineFunction::iterator BBI = CurMBB;
1585 if (++BBI != CurMBB->getParent()->end())
1588 if (NextMBB == NextBlock)
1591 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1592 DAG.getBasicBlock(NextMBB)));
1594 CurMBB->addSuccessor(B.TargetBB);
1595 CurMBB->addSuccessor(NextMBB);
1600 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1601 // Retrieve successors.
1602 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1603 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1605 if (isa<InlineAsm>(I.getCalledValue()))
1608 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1610 // If the value of the invoke is used outside of its defining block, make it
1611 // available as a virtual register.
1612 if (!I.use_empty()) {
1613 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1614 if (VMI != FuncInfo.ValueMap.end())
1615 CopyValueToVirtualRegister(&I, VMI->second);
1618 // Drop into normal successor.
1619 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1620 DAG.getBasicBlock(Return)));
1622 // Update successor info
1623 CurMBB->addSuccessor(Return);
1624 CurMBB->addSuccessor(LandingPad);
1627 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1630 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1631 /// small case ranges).
1632 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1633 CaseRecVector& WorkList,
1635 MachineBasicBlock* Default) {
1636 Case& BackCase = *(CR.Range.second-1);
1638 // Size is the number of Cases represented by this range.
1639 unsigned Size = CR.Range.second - CR.Range.first;
1643 // Get the MachineFunction which holds the current MBB. This is used when
1644 // inserting any additional MBBs necessary to represent the switch.
1645 MachineFunction *CurMF = CurMBB->getParent();
1647 // Figure out which block is immediately after the current one.
1648 MachineBasicBlock *NextBlock = 0;
1649 MachineFunction::iterator BBI = CR.CaseBB;
1651 if (++BBI != CurMBB->getParent()->end())
1654 // TODO: If any two of the cases has the same destination, and if one value
1655 // is the same as the other, but has one bit unset that the other has set,
1656 // use bit manipulation to do two compares at once. For example:
1657 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1659 // Rearrange the case blocks so that the last one falls through if possible.
1660 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1661 // The last case block won't fall through into 'NextBlock' if we emit the
1662 // branches in this order. See if rearranging a case value would help.
1663 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1664 if (I->BB == NextBlock) {
1665 std::swap(*I, BackCase);
1671 // Create a CaseBlock record representing a conditional branch to
1672 // the Case's target mbb if the value being switched on SV is equal
1674 MachineBasicBlock *CurBlock = CR.CaseBB;
1675 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1676 MachineBasicBlock *FallThrough;
1678 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1679 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1681 // If the last case doesn't match, go to the default block.
1682 FallThrough = Default;
1685 Value *RHS, *LHS, *MHS;
1687 if (I->High == I->Low) {
1688 // This is just small small case range :) containing exactly 1 case
1690 LHS = SV; RHS = I->High; MHS = NULL;
1693 LHS = I->Low; MHS = SV; RHS = I->High;
1695 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1696 I->BB, FallThrough, CurBlock);
1698 // If emitting the first comparison, just call visitSwitchCase to emit the
1699 // code into the current block. Otherwise, push the CaseBlock onto the
1700 // vector to be later processed by SDISel, and insert the node's MBB
1701 // before the next MBB.
1702 if (CurBlock == CurMBB)
1703 visitSwitchCase(CB);
1705 SwitchCases.push_back(CB);
1707 CurBlock = FallThrough;
1713 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1714 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1715 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1718 /// handleJTSwitchCase - Emit jumptable for current switch case range
1719 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1720 CaseRecVector& WorkList,
1722 MachineBasicBlock* Default) {
1723 Case& FrontCase = *CR.Range.first;
1724 Case& BackCase = *(CR.Range.second-1);
1726 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1727 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1730 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1734 if (!areJTsAllowed(TLI) || TSize <= 3)
1737 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1741 DOUT << "Lowering jump table\n"
1742 << "First entry: " << First << ". Last entry: " << Last << "\n"
1743 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1745 // Get the MachineFunction which holds the current MBB. This is used when
1746 // inserting any additional MBBs necessary to represent the switch.
1747 MachineFunction *CurMF = CurMBB->getParent();
1749 // Figure out which block is immediately after the current one.
1750 MachineBasicBlock *NextBlock = 0;
1751 MachineFunction::iterator BBI = CR.CaseBB;
1753 if (++BBI != CurMBB->getParent()->end())
1756 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1758 // Create a new basic block to hold the code for loading the address
1759 // of the jump table, and jumping to it. Update successor information;
1760 // we will either branch to the default case for the switch, or the jump
1762 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1763 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1764 CR.CaseBB->addSuccessor(Default);
1765 CR.CaseBB->addSuccessor(JumpTableBB);
1767 // Build a vector of destination BBs, corresponding to each target
1768 // of the jump table. If the value of the jump table slot corresponds to
1769 // a case statement, push the case's BB onto the vector, otherwise, push
1771 std::vector<MachineBasicBlock*> DestBBs;
1772 int64_t TEI = First;
1773 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1774 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1775 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1777 if ((Low <= TEI) && (TEI <= High)) {
1778 DestBBs.push_back(I->BB);
1782 DestBBs.push_back(Default);
1786 // Update successor info. Add one edge to each unique successor.
1787 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1788 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1789 E = DestBBs.end(); I != E; ++I) {
1790 if (!SuccsHandled[(*I)->getNumber()]) {
1791 SuccsHandled[(*I)->getNumber()] = true;
1792 JumpTableBB->addSuccessor(*I);
1796 // Create a jump table index for this jump table, or return an existing
1798 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1800 // Set the jump table information so that we can codegen it as a second
1801 // MachineBasicBlock
1802 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1803 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1804 (CR.CaseBB == CurMBB));
1805 if (CR.CaseBB == CurMBB)
1806 visitJumpTableHeader(JT, JTH);
1808 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1813 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1815 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1816 CaseRecVector& WorkList,
1818 MachineBasicBlock* Default) {
1819 // Get the MachineFunction which holds the current MBB. This is used when
1820 // inserting any additional MBBs necessary to represent the switch.
1821 MachineFunction *CurMF = CurMBB->getParent();
1823 // Figure out which block is immediately after the current one.
1824 MachineBasicBlock *NextBlock = 0;
1825 MachineFunction::iterator BBI = CR.CaseBB;
1827 if (++BBI != CurMBB->getParent()->end())
1830 Case& FrontCase = *CR.Range.first;
1831 Case& BackCase = *(CR.Range.second-1);
1832 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1834 // Size is the number of Cases represented by this range.
1835 unsigned Size = CR.Range.second - CR.Range.first;
1837 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1838 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1840 CaseItr Pivot = CR.Range.first + Size/2;
1842 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1843 // (heuristically) allow us to emit JumpTable's later.
1845 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1849 uint64_t LSize = FrontCase.size();
1850 uint64_t RSize = TSize-LSize;
1851 DOUT << "Selecting best pivot: \n"
1852 << "First: " << First << ", Last: " << Last <<"\n"
1853 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1854 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1856 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1857 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1858 assert((RBegin-LEnd>=1) && "Invalid case distance");
1859 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1860 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1861 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1862 // Should always split in some non-trivial place
1864 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1865 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1866 << "Metric: " << Metric << "\n";
1867 if (FMetric < Metric) {
1870 DOUT << "Current metric set to: " << FMetric << "\n";
1876 if (areJTsAllowed(TLI)) {
1877 // If our case is dense we *really* should handle it earlier!
1878 assert((FMetric > 0) && "Should handle dense range earlier!");
1880 Pivot = CR.Range.first + Size/2;
1883 CaseRange LHSR(CR.Range.first, Pivot);
1884 CaseRange RHSR(Pivot, CR.Range.second);
1885 Constant *C = Pivot->Low;
1886 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1888 // We know that we branch to the LHS if the Value being switched on is
1889 // less than the Pivot value, C. We use this to optimize our binary
1890 // tree a bit, by recognizing that if SV is greater than or equal to the
1891 // LHS's Case Value, and that Case Value is exactly one less than the
1892 // Pivot's Value, then we can branch directly to the LHS's Target,
1893 // rather than creating a leaf node for it.
1894 if ((LHSR.second - LHSR.first) == 1 &&
1895 LHSR.first->High == CR.GE &&
1896 cast<ConstantInt>(C)->getSExtValue() ==
1897 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1898 TrueBB = LHSR.first->BB;
1900 TrueBB = new MachineBasicBlock(LLVMBB);
1901 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1902 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1905 // Similar to the optimization above, if the Value being switched on is
1906 // known to be less than the Constant CR.LT, and the current Case Value
1907 // is CR.LT - 1, then we can branch directly to the target block for
1908 // the current Case Value, rather than emitting a RHS leaf node for it.
1909 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1910 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1911 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1912 FalseBB = RHSR.first->BB;
1914 FalseBB = new MachineBasicBlock(LLVMBB);
1915 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1916 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1919 // Create a CaseBlock record representing a conditional branch to
1920 // the LHS node if the value being switched on SV is less than C.
1921 // Otherwise, branch to LHS.
1922 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1923 TrueBB, FalseBB, CR.CaseBB);
1925 if (CR.CaseBB == CurMBB)
1926 visitSwitchCase(CB);
1928 SwitchCases.push_back(CB);
1933 /// handleBitTestsSwitchCase - if current case range has few destination and
1934 /// range span less, than machine word bitwidth, encode case range into series
1935 /// of masks and emit bit tests with these masks.
1936 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1937 CaseRecVector& WorkList,
1939 MachineBasicBlock* Default){
1940 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1942 Case& FrontCase = *CR.Range.first;
1943 Case& BackCase = *(CR.Range.second-1);
1945 // Get the MachineFunction which holds the current MBB. This is used when
1946 // inserting any additional MBBs necessary to represent the switch.
1947 MachineFunction *CurMF = CurMBB->getParent();
1949 unsigned numCmps = 0;
1950 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1952 // Single case counts one, case range - two.
1953 if (I->Low == I->High)
1959 // Count unique destinations
1960 SmallSet<MachineBasicBlock*, 4> Dests;
1961 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1962 Dests.insert(I->BB);
1963 if (Dests.size() > 3)
1964 // Don't bother the code below, if there are too much unique destinations
1967 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1968 << "Total number of comparisons: " << numCmps << "\n";
1970 // Compute span of values.
1971 Constant* minValue = FrontCase.Low;
1972 Constant* maxValue = BackCase.High;
1973 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1974 cast<ConstantInt>(minValue)->getSExtValue();
1975 DOUT << "Compare range: " << range << "\n"
1976 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1977 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1979 if (range>=IntPtrBits ||
1980 (!(Dests.size() == 1 && numCmps >= 3) &&
1981 !(Dests.size() == 2 && numCmps >= 5) &&
1982 !(Dests.size() >= 3 && numCmps >= 6)))
1985 DOUT << "Emitting bit tests\n";
1986 int64_t lowBound = 0;
1988 // Optimize the case where all the case values fit in a
1989 // word without having to subtract minValue. In this case,
1990 // we can optimize away the subtraction.
1991 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1992 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1993 range = cast<ConstantInt>(maxValue)->getSExtValue();
1995 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1998 CaseBitsVector CasesBits;
1999 unsigned i, count = 0;
2001 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2002 MachineBasicBlock* Dest = I->BB;
2003 for (i = 0; i < count; ++i)
2004 if (Dest == CasesBits[i].BB)
2008 assert((count < 3) && "Too much destinations to test!");
2009 CasesBits.push_back(CaseBits(0, Dest, 0));
2013 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2014 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2016 for (uint64_t j = lo; j <= hi; j++) {
2017 CasesBits[i].Mask |= 1ULL << j;
2018 CasesBits[i].Bits++;
2022 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2024 SelectionDAGISel::BitTestInfo BTC;
2026 // Figure out which block is immediately after the current one.
2027 MachineFunction::iterator BBI = CR.CaseBB;
2030 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2033 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2034 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2035 << ", BB: " << CasesBits[i].BB << "\n";
2037 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
2038 CurMF->getBasicBlockList().insert(BBI, CaseBB);
2039 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2044 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2045 -1U, (CR.CaseBB == CurMBB),
2046 CR.CaseBB, Default, BTC);
2048 if (CR.CaseBB == CurMBB)
2049 visitBitTestHeader(BTB);
2051 BitTestCases.push_back(BTB);
2057 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2058 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2059 const SwitchInst& SI) {
2060 unsigned numCmps = 0;
2062 // Start with "simple" cases
2063 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2064 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2065 Cases.push_back(Case(SI.getSuccessorValue(i),
2066 SI.getSuccessorValue(i),
2069 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2071 // Merge case into clusters
2072 if (Cases.size()>=2)
2073 // Must recompute end() each iteration because it may be
2074 // invalidated by erase if we hold on to it
2075 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2076 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2077 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2078 MachineBasicBlock* nextBB = J->BB;
2079 MachineBasicBlock* currentBB = I->BB;
2081 // If the two neighboring cases go to the same destination, merge them
2082 // into a single case.
2083 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2091 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2092 if (I->Low != I->High)
2093 // A range counts double, since it requires two compares.
2100 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2101 // Figure out which block is immediately after the current one.
2102 MachineBasicBlock *NextBlock = 0;
2103 MachineFunction::iterator BBI = CurMBB;
2105 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2107 // If there is only the default destination, branch to it if it is not the
2108 // next basic block. Otherwise, just fall through.
2109 if (SI.getNumOperands() == 2) {
2110 // Update machine-CFG edges.
2112 // If this is not a fall-through branch, emit the branch.
2113 if (Default != NextBlock)
2114 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2115 DAG.getBasicBlock(Default)));
2117 CurMBB->addSuccessor(Default);
2121 // If there are any non-default case statements, create a vector of Cases
2122 // representing each one, and sort the vector so that we can efficiently
2123 // create a binary search tree from them.
2125 unsigned numCmps = Clusterify(Cases, SI);
2126 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2127 << ". Total compares: " << numCmps << "\n";
2129 // Get the Value to be switched on and default basic blocks, which will be
2130 // inserted into CaseBlock records, representing basic blocks in the binary
2132 Value *SV = SI.getOperand(0);
2134 // Push the initial CaseRec onto the worklist
2135 CaseRecVector WorkList;
2136 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2138 while (!WorkList.empty()) {
2139 // Grab a record representing a case range to process off the worklist
2140 CaseRec CR = WorkList.back();
2141 WorkList.pop_back();
2143 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2146 // If the range has few cases (two or less) emit a series of specific
2148 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2151 // If the switch has more than 5 blocks, and at least 40% dense, and the
2152 // target supports indirect branches, then emit a jump table rather than
2153 // lowering the switch to a binary tree of conditional branches.
2154 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2157 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2158 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2159 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2164 void SelectionDAGLowering::visitSub(User &I) {
2165 // -0.0 - X --> fneg
2166 const Type *Ty = I.getType();
2167 if (isa<VectorType>(Ty)) {
2168 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2169 const VectorType *DestTy = cast<VectorType>(I.getType());
2170 const Type *ElTy = DestTy->getElementType();
2171 if (ElTy->isFloatingPoint()) {
2172 unsigned VL = DestTy->getNumElements();
2173 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2174 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2176 SDOperand Op2 = getValue(I.getOperand(1));
2177 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2183 if (Ty->isFloatingPoint()) {
2184 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2185 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2186 SDOperand Op2 = getValue(I.getOperand(1));
2187 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2192 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2195 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2196 SDOperand Op1 = getValue(I.getOperand(0));
2197 SDOperand Op2 = getValue(I.getOperand(1));
2199 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2202 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2203 SDOperand Op1 = getValue(I.getOperand(0));
2204 SDOperand Op2 = getValue(I.getOperand(1));
2206 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2207 MVT::getSizeInBits(Op2.getValueType()))
2208 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2209 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2210 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2212 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2215 void SelectionDAGLowering::visitICmp(User &I) {
2216 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2217 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2218 predicate = IC->getPredicate();
2219 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2220 predicate = ICmpInst::Predicate(IC->getPredicate());
2221 SDOperand Op1 = getValue(I.getOperand(0));
2222 SDOperand Op2 = getValue(I.getOperand(1));
2223 ISD::CondCode Opcode;
2224 switch (predicate) {
2225 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2226 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2227 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2228 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2229 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2230 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2231 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2232 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2233 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2234 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2236 assert(!"Invalid ICmp predicate value");
2237 Opcode = ISD::SETEQ;
2240 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2243 void SelectionDAGLowering::visitFCmp(User &I) {
2244 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2245 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2246 predicate = FC->getPredicate();
2247 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2248 predicate = FCmpInst::Predicate(FC->getPredicate());
2249 SDOperand Op1 = getValue(I.getOperand(0));
2250 SDOperand Op2 = getValue(I.getOperand(1));
2251 ISD::CondCode Condition, FOC, FPC;
2252 switch (predicate) {
2253 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2254 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2255 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2256 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2257 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2258 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2259 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2260 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2261 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2262 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2263 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2264 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2265 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2266 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2267 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2268 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2270 assert(!"Invalid FCmp predicate value");
2271 FOC = FPC = ISD::SETFALSE;
2274 if (FiniteOnlyFPMath())
2278 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2281 void SelectionDAGLowering::visitSelect(User &I) {
2282 SDOperand Cond = getValue(I.getOperand(0));
2283 SDOperand TrueVal = getValue(I.getOperand(1));
2284 SDOperand FalseVal = getValue(I.getOperand(2));
2285 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2286 TrueVal, FalseVal));
2290 void SelectionDAGLowering::visitTrunc(User &I) {
2291 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2292 SDOperand N = getValue(I.getOperand(0));
2293 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2294 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2297 void SelectionDAGLowering::visitZExt(User &I) {
2298 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2299 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2300 SDOperand N = getValue(I.getOperand(0));
2301 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2302 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2305 void SelectionDAGLowering::visitSExt(User &I) {
2306 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2307 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2308 SDOperand N = getValue(I.getOperand(0));
2309 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2310 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2313 void SelectionDAGLowering::visitFPTrunc(User &I) {
2314 // FPTrunc is never a no-op cast, no need to check
2315 SDOperand N = getValue(I.getOperand(0));
2316 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2317 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2320 void SelectionDAGLowering::visitFPExt(User &I){
2321 // FPTrunc is never a no-op cast, no need to check
2322 SDOperand N = getValue(I.getOperand(0));
2323 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2324 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2327 void SelectionDAGLowering::visitFPToUI(User &I) {
2328 // FPToUI is never a no-op cast, no need to check
2329 SDOperand N = getValue(I.getOperand(0));
2330 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2331 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2334 void SelectionDAGLowering::visitFPToSI(User &I) {
2335 // FPToSI is never a no-op cast, no need to check
2336 SDOperand N = getValue(I.getOperand(0));
2337 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2338 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2341 void SelectionDAGLowering::visitUIToFP(User &I) {
2342 // UIToFP is never a no-op cast, no need to check
2343 SDOperand N = getValue(I.getOperand(0));
2344 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2345 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2348 void SelectionDAGLowering::visitSIToFP(User &I){
2349 // UIToFP is never a no-op cast, no need to check
2350 SDOperand N = getValue(I.getOperand(0));
2351 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2352 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2355 void SelectionDAGLowering::visitPtrToInt(User &I) {
2356 // What to do depends on the size of the integer and the size of the pointer.
2357 // We can either truncate, zero extend, or no-op, accordingly.
2358 SDOperand N = getValue(I.getOperand(0));
2359 MVT::ValueType SrcVT = N.getValueType();
2360 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2362 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2363 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2365 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2366 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2367 setValue(&I, Result);
2370 void SelectionDAGLowering::visitIntToPtr(User &I) {
2371 // What to do depends on the size of the integer and the size of the pointer.
2372 // We can either truncate, zero extend, or no-op, accordingly.
2373 SDOperand N = getValue(I.getOperand(0));
2374 MVT::ValueType SrcVT = N.getValueType();
2375 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2376 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2377 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2379 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2380 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2383 void SelectionDAGLowering::visitBitCast(User &I) {
2384 SDOperand N = getValue(I.getOperand(0));
2385 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2387 // BitCast assures us that source and destination are the same size so this
2388 // is either a BIT_CONVERT or a no-op.
2389 if (DestVT != N.getValueType())
2390 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2392 setValue(&I, N); // noop cast.
2395 void SelectionDAGLowering::visitInsertElement(User &I) {
2396 SDOperand InVec = getValue(I.getOperand(0));
2397 SDOperand InVal = getValue(I.getOperand(1));
2398 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2399 getValue(I.getOperand(2)));
2401 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2402 TLI.getValueType(I.getType()),
2403 InVec, InVal, InIdx));
2406 void SelectionDAGLowering::visitExtractElement(User &I) {
2407 SDOperand InVec = getValue(I.getOperand(0));
2408 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2409 getValue(I.getOperand(1)));
2410 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2411 TLI.getValueType(I.getType()), InVec, InIdx));
2414 void SelectionDAGLowering::visitShuffleVector(User &I) {
2415 SDOperand V1 = getValue(I.getOperand(0));
2416 SDOperand V2 = getValue(I.getOperand(1));
2417 SDOperand Mask = getValue(I.getOperand(2));
2419 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2420 TLI.getValueType(I.getType()),
2425 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2426 SDOperand N = getValue(I.getOperand(0));
2427 const Type *Ty = I.getOperand(0)->getType();
2429 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2432 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2433 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2436 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2437 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2438 DAG.getIntPtrConstant(Offset));
2440 Ty = StTy->getElementType(Field);
2442 Ty = cast<SequentialType>(Ty)->getElementType();
2444 // If this is a constant subscript, handle it quickly.
2445 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2446 if (CI->getZExtValue() == 0) continue;
2448 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2449 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2450 DAG.getIntPtrConstant(Offs));
2454 // N = N + Idx * ElementSize;
2455 uint64_t ElementSize = TD->getABITypeSize(Ty);
2456 SDOperand IdxN = getValue(Idx);
2458 // If the index is smaller or larger than intptr_t, truncate or extend
2460 if (IdxN.getValueType() < N.getValueType()) {
2461 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2462 } else if (IdxN.getValueType() > N.getValueType())
2463 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2465 // If this is a multiply by a power of two, turn it into a shl
2466 // immediately. This is a very common case.
2467 if (isPowerOf2_64(ElementSize)) {
2468 unsigned Amt = Log2_64(ElementSize);
2469 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2470 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2471 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2475 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2476 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2477 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2483 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2484 // If this is a fixed sized alloca in the entry block of the function,
2485 // allocate it statically on the stack.
2486 if (FuncInfo.StaticAllocaMap.count(&I))
2487 return; // getValue will auto-populate this.
2489 const Type *Ty = I.getAllocatedType();
2490 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2492 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2495 SDOperand AllocSize = getValue(I.getArraySize());
2496 MVT::ValueType IntPtr = TLI.getPointerTy();
2497 if (IntPtr < AllocSize.getValueType())
2498 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2499 else if (IntPtr > AllocSize.getValueType())
2500 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2502 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2503 DAG.getIntPtrConstant(TySize));
2505 // Handle alignment. If the requested alignment is less than or equal to
2506 // the stack alignment, ignore it. If the size is greater than or equal to
2507 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2508 unsigned StackAlign =
2509 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2510 if (Align <= StackAlign)
2513 // Round the size of the allocation up to the stack alignment size
2514 // by add SA-1 to the size.
2515 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2516 DAG.getIntPtrConstant(StackAlign-1));
2517 // Mask out the low bits for alignment purposes.
2518 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2519 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2521 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2522 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2524 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2526 DAG.setRoot(DSA.getValue(1));
2528 // Inform the Frame Information that we have just allocated a variable-sized
2530 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2533 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2534 SDOperand Ptr = getValue(I.getOperand(0));
2540 // Do not serialize non-volatile loads against each other.
2541 Root = DAG.getRoot();
2544 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2545 Root, I.isVolatile(), I.getAlignment()));
2548 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2549 const Value *SV, SDOperand Root,
2551 unsigned Alignment) {
2553 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2554 isVolatile, Alignment);
2557 DAG.setRoot(L.getValue(1));
2559 PendingLoads.push_back(L.getValue(1));
2565 void SelectionDAGLowering::visitStore(StoreInst &I) {
2566 Value *SrcV = I.getOperand(0);
2567 SDOperand Src = getValue(SrcV);
2568 SDOperand Ptr = getValue(I.getOperand(1));
2569 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2570 I.isVolatile(), I.getAlignment()));
2573 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2575 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2576 unsigned Intrinsic) {
2577 bool HasChain = !I.doesNotAccessMemory();
2578 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2580 // Build the operand list.
2581 SmallVector<SDOperand, 8> Ops;
2582 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2584 // We don't need to serialize loads against other loads.
2585 Ops.push_back(DAG.getRoot());
2587 Ops.push_back(getRoot());
2591 // Add the intrinsic ID as an integer operand.
2592 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2594 // Add all operands of the call to the operand list.
2595 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2596 SDOperand Op = getValue(I.getOperand(i));
2597 assert(TLI.isTypeLegal(Op.getValueType()) &&
2598 "Intrinsic uses a non-legal type?");
2602 std::vector<MVT::ValueType> VTs;
2603 if (I.getType() != Type::VoidTy) {
2604 MVT::ValueType VT = TLI.getValueType(I.getType());
2605 if (MVT::isVector(VT)) {
2606 const VectorType *DestTy = cast<VectorType>(I.getType());
2607 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2609 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2610 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2613 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2617 VTs.push_back(MVT::Other);
2619 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2624 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2625 &Ops[0], Ops.size());
2626 else if (I.getType() != Type::VoidTy)
2627 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2628 &Ops[0], Ops.size());
2630 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2631 &Ops[0], Ops.size());
2634 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2636 PendingLoads.push_back(Chain);
2640 if (I.getType() != Type::VoidTy) {
2641 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2642 MVT::ValueType VT = TLI.getValueType(PTy);
2643 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2645 setValue(&I, Result);
2649 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2650 static GlobalVariable *ExtractTypeInfo (Value *V) {
2651 V = IntrinsicInst::StripPointerCasts(V);
2652 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2653 assert ((GV || isa<ConstantPointerNull>(V)) &&
2654 "TypeInfo must be a global variable or NULL");
2658 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2659 /// call, and add them to the specified machine basic block.
2660 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2661 MachineBasicBlock *MBB) {
2662 // Inform the MachineModuleInfo of the personality for this landing pad.
2663 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2664 assert(CE->getOpcode() == Instruction::BitCast &&
2665 isa<Function>(CE->getOperand(0)) &&
2666 "Personality should be a function");
2667 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2669 // Gather all the type infos for this landing pad and pass them along to
2670 // MachineModuleInfo.
2671 std::vector<GlobalVariable *> TyInfo;
2672 unsigned N = I.getNumOperands();
2674 for (unsigned i = N - 1; i > 2; --i) {
2675 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2676 unsigned FilterLength = CI->getZExtValue();
2677 unsigned FirstCatch = i + FilterLength + !FilterLength;
2678 assert (FirstCatch <= N && "Invalid filter length");
2680 if (FirstCatch < N) {
2681 TyInfo.reserve(N - FirstCatch);
2682 for (unsigned j = FirstCatch; j < N; ++j)
2683 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2684 MMI->addCatchTypeInfo(MBB, TyInfo);
2688 if (!FilterLength) {
2690 MMI->addCleanup(MBB);
2693 TyInfo.reserve(FilterLength - 1);
2694 for (unsigned j = i + 1; j < FirstCatch; ++j)
2695 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2696 MMI->addFilterTypeInfo(MBB, TyInfo);
2705 TyInfo.reserve(N - 3);
2706 for (unsigned j = 3; j < N; ++j)
2707 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2708 MMI->addCatchTypeInfo(MBB, TyInfo);
2712 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2713 /// we want to emit this as a call to a named external function, return the name
2714 /// otherwise lower it and return null.
2716 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2717 switch (Intrinsic) {
2719 // By default, turn this into a target intrinsic node.
2720 visitTargetIntrinsic(I, Intrinsic);
2722 case Intrinsic::vastart: visitVAStart(I); return 0;
2723 case Intrinsic::vaend: visitVAEnd(I); return 0;
2724 case Intrinsic::vacopy: visitVACopy(I); return 0;
2725 case Intrinsic::returnaddress:
2726 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2727 getValue(I.getOperand(1))));
2729 case Intrinsic::frameaddress:
2730 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2731 getValue(I.getOperand(1))));
2733 case Intrinsic::setjmp:
2734 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2736 case Intrinsic::longjmp:
2737 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2739 case Intrinsic::memcpy_i32:
2740 case Intrinsic::memcpy_i64:
2741 visitMemIntrinsic(I, ISD::MEMCPY);
2743 case Intrinsic::memset_i32:
2744 case Intrinsic::memset_i64:
2745 visitMemIntrinsic(I, ISD::MEMSET);
2747 case Intrinsic::memmove_i32:
2748 case Intrinsic::memmove_i64:
2749 visitMemIntrinsic(I, ISD::MEMMOVE);
2752 case Intrinsic::dbg_stoppoint: {
2753 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2754 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2755 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2759 Ops[1] = getValue(SPI.getLineValue());
2760 Ops[2] = getValue(SPI.getColumnValue());
2762 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2763 assert(DD && "Not a debug information descriptor");
2764 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2766 Ops[3] = DAG.getString(CompileUnit->getFileName());
2767 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2769 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2774 case Intrinsic::dbg_region_start: {
2775 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2776 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2777 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2778 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2779 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2780 DAG.getConstant(LabelID, MVT::i32),
2781 DAG.getConstant(0, MVT::i32)));
2786 case Intrinsic::dbg_region_end: {
2787 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2788 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2789 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2790 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2791 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2792 DAG.getConstant(LabelID, MVT::i32),
2793 DAG.getConstant(0, MVT::i32)));
2798 case Intrinsic::dbg_func_start: {
2799 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2801 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2802 Value *SP = FSI.getSubprogram();
2803 if (SP && MMI->Verify(SP)) {
2804 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
2805 // what (most?) gdb expects.
2806 DebugInfoDesc *DD = MMI->getDescFor(SP);
2807 assert(DD && "Not a debug information descriptor");
2808 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
2809 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
2810 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
2811 CompileUnit->getFileName());
2812 // Record the source line but does create a label. It will be emitted
2813 // at asm emission time.
2814 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
2819 case Intrinsic::dbg_declare: {
2820 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2821 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2822 Value *Variable = DI.getVariable();
2823 if (MMI && Variable && MMI->Verify(Variable))
2824 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
2825 getValue(DI.getAddress()), getValue(Variable)));
2829 case Intrinsic::eh_exception: {
2830 if (!CurMBB->isLandingPad()) {
2831 // FIXME: Mark exception register as live in. Hack for PR1508.
2832 unsigned Reg = TLI.getExceptionAddressRegister();
2833 if (Reg) CurMBB->addLiveIn(Reg);
2835 // Insert the EXCEPTIONADDR instruction.
2836 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2838 Ops[0] = DAG.getRoot();
2839 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2841 DAG.setRoot(Op.getValue(1));
2845 case Intrinsic::eh_selector_i32:
2846 case Intrinsic::eh_selector_i64: {
2847 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2848 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2849 MVT::i32 : MVT::i64);
2852 if (CurMBB->isLandingPad())
2853 addCatchInfo(I, MMI, CurMBB);
2856 FuncInfo.CatchInfoLost.insert(&I);
2858 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2859 unsigned Reg = TLI.getExceptionSelectorRegister();
2860 if (Reg) CurMBB->addLiveIn(Reg);
2863 // Insert the EHSELECTION instruction.
2864 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2866 Ops[0] = getValue(I.getOperand(1));
2868 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2870 DAG.setRoot(Op.getValue(1));
2872 setValue(&I, DAG.getConstant(0, VT));
2878 case Intrinsic::eh_typeid_for_i32:
2879 case Intrinsic::eh_typeid_for_i64: {
2880 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2881 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2882 MVT::i32 : MVT::i64);
2885 // Find the type id for the given typeinfo.
2886 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2888 unsigned TypeID = MMI->getTypeIDFor(GV);
2889 setValue(&I, DAG.getConstant(TypeID, VT));
2891 // Return something different to eh_selector.
2892 setValue(&I, DAG.getConstant(1, VT));
2898 case Intrinsic::eh_return: {
2899 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2902 MMI->setCallsEHReturn(true);
2903 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2906 getValue(I.getOperand(1)),
2907 getValue(I.getOperand(2))));
2909 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2915 case Intrinsic::eh_unwind_init: {
2916 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2917 MMI->setCallsUnwindInit(true);
2923 case Intrinsic::eh_dwarf_cfa: {
2924 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2926 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2927 CfaArg = DAG.getNode(ISD::TRUNCATE,
2928 TLI.getPointerTy(), getValue(I.getOperand(1)));
2930 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2931 TLI.getPointerTy(), getValue(I.getOperand(1)));
2933 SDOperand Offset = DAG.getNode(ISD::ADD,
2935 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2936 TLI.getPointerTy()),
2938 setValue(&I, DAG.getNode(ISD::ADD,
2940 DAG.getNode(ISD::FRAMEADDR,
2943 TLI.getPointerTy())),
2948 case Intrinsic::sqrt:
2949 setValue(&I, DAG.getNode(ISD::FSQRT,
2950 getValue(I.getOperand(1)).getValueType(),
2951 getValue(I.getOperand(1))));
2953 case Intrinsic::powi:
2954 setValue(&I, DAG.getNode(ISD::FPOWI,
2955 getValue(I.getOperand(1)).getValueType(),
2956 getValue(I.getOperand(1)),
2957 getValue(I.getOperand(2))));
2959 case Intrinsic::sin:
2960 setValue(&I, DAG.getNode(ISD::FSIN,
2961 getValue(I.getOperand(1)).getValueType(),
2962 getValue(I.getOperand(1))));
2964 case Intrinsic::cos:
2965 setValue(&I, DAG.getNode(ISD::FCOS,
2966 getValue(I.getOperand(1)).getValueType(),
2967 getValue(I.getOperand(1))));
2969 case Intrinsic::pow:
2970 setValue(&I, DAG.getNode(ISD::FPOW,
2971 getValue(I.getOperand(1)).getValueType(),
2972 getValue(I.getOperand(1)),
2973 getValue(I.getOperand(2))));
2975 case Intrinsic::pcmarker: {
2976 SDOperand Tmp = getValue(I.getOperand(1));
2977 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2980 case Intrinsic::readcyclecounter: {
2981 SDOperand Op = getRoot();
2982 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2983 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2986 DAG.setRoot(Tmp.getValue(1));
2989 case Intrinsic::part_select: {
2990 // Currently not implemented: just abort
2991 assert(0 && "part_select intrinsic not implemented");
2994 case Intrinsic::part_set: {
2995 // Currently not implemented: just abort
2996 assert(0 && "part_set intrinsic not implemented");
2999 case Intrinsic::bswap:
3000 setValue(&I, DAG.getNode(ISD::BSWAP,
3001 getValue(I.getOperand(1)).getValueType(),
3002 getValue(I.getOperand(1))));
3004 case Intrinsic::cttz: {
3005 SDOperand Arg = getValue(I.getOperand(1));
3006 MVT::ValueType Ty = Arg.getValueType();
3007 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3008 setValue(&I, result);
3011 case Intrinsic::ctlz: {
3012 SDOperand Arg = getValue(I.getOperand(1));
3013 MVT::ValueType Ty = Arg.getValueType();
3014 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3015 setValue(&I, result);
3018 case Intrinsic::ctpop: {
3019 SDOperand Arg = getValue(I.getOperand(1));
3020 MVT::ValueType Ty = Arg.getValueType();
3021 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3022 setValue(&I, result);
3025 case Intrinsic::stacksave: {
3026 SDOperand Op = getRoot();
3027 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
3028 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3030 DAG.setRoot(Tmp.getValue(1));
3033 case Intrinsic::stackrestore: {
3034 SDOperand Tmp = getValue(I.getOperand(1));
3035 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3038 case Intrinsic::var_annotation:
3039 // Discard annotate attributes
3042 case Intrinsic::init_trampoline: {
3044 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
3048 Ops[1] = getValue(I.getOperand(1));
3049 Ops[2] = getValue(I.getOperand(2));
3050 Ops[3] = getValue(I.getOperand(3));
3051 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3052 Ops[5] = DAG.getSrcValue(F);
3054 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3055 DAG.getNodeValueTypes(TLI.getPointerTy(),
3060 DAG.setRoot(Tmp.getValue(1));
3064 case Intrinsic::gcroot:
3066 Value *Alloca = I.getOperand(1);
3067 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3069 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3070 GCI->addStackRoot(FI->getIndex(), TypeMap);
3074 case Intrinsic::gcread:
3075 case Intrinsic::gcwrite:
3076 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3079 case Intrinsic::flt_rounds: {
3080 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3084 case Intrinsic::trap: {
3085 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3088 case Intrinsic::prefetch: {
3091 Ops[1] = getValue(I.getOperand(1));
3092 Ops[2] = getValue(I.getOperand(2));
3093 Ops[3] = getValue(I.getOperand(3));
3094 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3098 case Intrinsic::memory_barrier: {
3101 for (int x = 1; x < 6; ++x)
3102 Ops[x] = getValue(I.getOperand(x));
3104 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3107 case Intrinsic::atomic_lcs: {
3108 SDOperand Root = getRoot();
3109 SDOperand O3 = getValue(I.getOperand(3));
3110 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root,
3111 getValue(I.getOperand(1)),
3112 getValue(I.getOperand(2)),
3113 O3, O3.getValueType());
3115 DAG.setRoot(L.getValue(1));
3118 case Intrinsic::atomic_las: {
3119 SDOperand Root = getRoot();
3120 SDOperand O2 = getValue(I.getOperand(2));
3121 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LAS, Root,
3122 getValue(I.getOperand(1)),
3123 O2, O2.getValueType());
3125 DAG.setRoot(L.getValue(1));
3128 case Intrinsic::atomic_swap: {
3129 SDOperand Root = getRoot();
3130 SDOperand O2 = getValue(I.getOperand(2));
3131 SDOperand L = DAG.getAtomic(ISD::ATOMIC_SWAP, Root,
3132 getValue(I.getOperand(1)),
3133 O2, O2.getValueType());
3135 DAG.setRoot(L.getValue(1));
3143 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3145 MachineBasicBlock *LandingPad) {
3146 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3147 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3148 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3149 unsigned BeginLabel = 0, EndLabel = 0;
3151 TargetLowering::ArgListTy Args;
3152 TargetLowering::ArgListEntry Entry;
3153 Args.reserve(CS.arg_size());
3154 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3156 SDOperand ArgNode = getValue(*i);
3157 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3159 unsigned attrInd = i - CS.arg_begin() + 1;
3160 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3161 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3162 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3163 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3164 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3165 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3166 Entry.Alignment = CS.getParamAlignment(attrInd);
3167 Args.push_back(Entry);
3170 if (LandingPad && MMI) {
3171 // Insert a label before the invoke call to mark the try range. This can be
3172 // used to detect deletion of the invoke via the MachineModuleInfo.
3173 BeginLabel = MMI->NextLabelID();
3174 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3175 DAG.getConstant(BeginLabel, MVT::i32),
3176 DAG.getConstant(1, MVT::i32)));
3179 std::pair<SDOperand,SDOperand> Result =
3180 TLI.LowerCallTo(getRoot(), CS.getType(),
3181 CS.paramHasAttr(0, ParamAttr::SExt),
3182 CS.paramHasAttr(0, ParamAttr::ZExt),
3183 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3185 if (CS.getType() != Type::VoidTy)
3186 setValue(CS.getInstruction(), Result.first);
3187 DAG.setRoot(Result.second);
3189 if (LandingPad && MMI) {
3190 // Insert a label at the end of the invoke call to mark the try range. This
3191 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3192 EndLabel = MMI->NextLabelID();
3193 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3194 DAG.getConstant(EndLabel, MVT::i32),
3195 DAG.getConstant(1, MVT::i32)));
3197 // Inform MachineModuleInfo of range.
3198 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3203 void SelectionDAGLowering::visitCall(CallInst &I) {
3204 const char *RenameFn = 0;
3205 if (Function *F = I.getCalledFunction()) {
3206 if (F->isDeclaration()) {
3207 if (unsigned IID = F->getIntrinsicID()) {
3208 RenameFn = visitIntrinsicCall(I, IID);
3214 // Check for well-known libc/libm calls. If the function is internal, it
3215 // can't be a library call.
3216 unsigned NameLen = F->getNameLen();
3217 if (!F->hasInternalLinkage() && NameLen) {
3218 const char *NameStr = F->getNameStart();
3219 if (NameStr[0] == 'c' &&
3220 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3221 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3222 if (I.getNumOperands() == 3 && // Basic sanity checks.
3223 I.getOperand(1)->getType()->isFloatingPoint() &&
3224 I.getType() == I.getOperand(1)->getType() &&
3225 I.getType() == I.getOperand(2)->getType()) {
3226 SDOperand LHS = getValue(I.getOperand(1));
3227 SDOperand RHS = getValue(I.getOperand(2));
3228 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3232 } else if (NameStr[0] == 'f' &&
3233 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3234 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3235 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3236 if (I.getNumOperands() == 2 && // Basic sanity checks.
3237 I.getOperand(1)->getType()->isFloatingPoint() &&
3238 I.getType() == I.getOperand(1)->getType()) {
3239 SDOperand Tmp = getValue(I.getOperand(1));
3240 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3243 } else if (NameStr[0] == 's' &&
3244 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3245 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3246 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3247 if (I.getNumOperands() == 2 && // Basic sanity checks.
3248 I.getOperand(1)->getType()->isFloatingPoint() &&
3249 I.getType() == I.getOperand(1)->getType()) {
3250 SDOperand Tmp = getValue(I.getOperand(1));
3251 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3254 } else if (NameStr[0] == 'c' &&
3255 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3256 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3257 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3258 if (I.getNumOperands() == 2 && // Basic sanity checks.
3259 I.getOperand(1)->getType()->isFloatingPoint() &&
3260 I.getType() == I.getOperand(1)->getType()) {
3261 SDOperand Tmp = getValue(I.getOperand(1));
3262 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3267 } else if (isa<InlineAsm>(I.getOperand(0))) {
3274 Callee = getValue(I.getOperand(0));
3276 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3278 LowerCallTo(&I, Callee, I.isTailCall());
3282 void SelectionDAGLowering::visitGetResult(GetResultInst &I) {
3283 SDOperand Call = getValue(I.getOperand(0));
3284 setValue(&I, SDOperand(Call.Val, I.getIndex()));
3288 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3289 /// this value and returns the result as a ValueVT value. This uses
3290 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3291 /// If the Flag pointer is NULL, no flag is used.
3292 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3293 SDOperand &Chain, SDOperand *Flag)const{
3294 // Copy the legal parts from the registers.
3295 unsigned NumParts = Regs.size();
3296 SmallVector<SDOperand, 8> Parts(NumParts);
3297 for (unsigned i = 0; i != NumParts; ++i) {
3298 SDOperand Part = Flag ?
3299 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3300 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3301 Chain = Part.getValue(1);
3303 *Flag = Part.getValue(2);
3307 // Assemble the legal parts into the final value.
3308 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3311 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3312 /// specified value into the registers specified by this object. This uses
3313 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3314 /// If the Flag pointer is NULL, no flag is used.
3315 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3316 SDOperand &Chain, SDOperand *Flag) const {
3317 // Get the list of the values's legal parts.
3318 unsigned NumParts = Regs.size();
3319 SmallVector<SDOperand, 8> Parts(NumParts);
3320 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3322 // Copy the parts into the registers.
3323 for (unsigned i = 0; i != NumParts; ++i) {
3324 SDOperand Part = Flag ?
3325 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3326 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3327 Chain = Part.getValue(0);
3329 *Flag = Part.getValue(1);
3333 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3334 /// operand list. This adds the code marker and includes the number of
3335 /// values added into it.
3336 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3337 std::vector<SDOperand> &Ops) const {
3338 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3339 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3340 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3341 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3344 /// isAllocatableRegister - If the specified register is safe to allocate,
3345 /// i.e. it isn't a stack pointer or some other special register, return the
3346 /// register class for the register. Otherwise, return null.
3347 static const TargetRegisterClass *
3348 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3349 const TargetLowering &TLI,
3350 const TargetRegisterInfo *TRI) {
3351 MVT::ValueType FoundVT = MVT::Other;
3352 const TargetRegisterClass *FoundRC = 0;
3353 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3354 E = TRI->regclass_end(); RCI != E; ++RCI) {
3355 MVT::ValueType ThisVT = MVT::Other;
3357 const TargetRegisterClass *RC = *RCI;
3358 // If none of the the value types for this register class are valid, we
3359 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3360 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3362 if (TLI.isTypeLegal(*I)) {
3363 // If we have already found this register in a different register class,
3364 // choose the one with the largest VT specified. For example, on
3365 // PowerPC, we favor f64 register classes over f32.
3366 if (FoundVT == MVT::Other ||
3367 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3374 if (ThisVT == MVT::Other) continue;
3376 // NOTE: This isn't ideal. In particular, this might allocate the
3377 // frame pointer in functions that need it (due to them not being taken
3378 // out of allocation, because a variable sized allocation hasn't been seen
3379 // yet). This is a slight code pessimization, but should still work.
3380 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3381 E = RC->allocation_order_end(MF); I != E; ++I)
3383 // We found a matching register class. Keep looking at others in case
3384 // we find one with larger registers that this physreg is also in.
3395 /// AsmOperandInfo - This contains information for each constraint that we are
3397 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3398 /// CallOperand - If this is the result output operand or a clobber
3399 /// this is null, otherwise it is the incoming operand to the CallInst.
3400 /// This gets modified as the asm is processed.
3401 SDOperand CallOperand;
3403 /// AssignedRegs - If this is a register or register class operand, this
3404 /// contains the set of register corresponding to the operand.
3405 RegsForValue AssignedRegs;
3407 SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3408 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3411 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3412 /// busy in OutputRegs/InputRegs.
3413 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3414 std::set<unsigned> &OutputRegs,
3415 std::set<unsigned> &InputRegs,
3416 const TargetRegisterInfo &TRI) const {
3418 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3419 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3422 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3423 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3428 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3430 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3431 const TargetRegisterInfo &TRI) {
3432 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3434 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3435 for (; *Aliases; ++Aliases)
3436 Regs.insert(*Aliases);
3439 } // end anon namespace.
3442 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3443 /// specified operand. We prefer to assign virtual registers, to allow the
3444 /// register allocator handle the assignment process. However, if the asm uses
3445 /// features that we can't model on machineinstrs, we have SDISel do the
3446 /// allocation. This produces generally horrible, but correct, code.
3448 /// OpInfo describes the operand.
3449 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3450 /// or any explicitly clobbered registers.
3451 /// Input and OutputRegs are the set of already allocated physical registers.
3453 void SelectionDAGLowering::
3454 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3455 std::set<unsigned> &OutputRegs,
3456 std::set<unsigned> &InputRegs) {
3457 // Compute whether this value requires an input register, an output register,
3459 bool isOutReg = false;
3460 bool isInReg = false;
3461 switch (OpInfo.Type) {
3462 case InlineAsm::isOutput:
3465 // If this is an early-clobber output, or if there is an input
3466 // constraint that matches this, we need to reserve the input register
3467 // so no other inputs allocate to it.
3468 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3470 case InlineAsm::isInput:
3474 case InlineAsm::isClobber:
3481 MachineFunction &MF = DAG.getMachineFunction();
3482 std::vector<unsigned> Regs;
3484 // If this is a constraint for a single physreg, or a constraint for a
3485 // register class, find it.
3486 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3487 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3488 OpInfo.ConstraintVT);
3490 unsigned NumRegs = 1;
3491 if (OpInfo.ConstraintVT != MVT::Other)
3492 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3493 MVT::ValueType RegVT;
3494 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3497 // If this is a constraint for a specific physical register, like {r17},
3499 if (PhysReg.first) {
3500 if (OpInfo.ConstraintVT == MVT::Other)
3501 ValueVT = *PhysReg.second->vt_begin();
3503 // Get the actual register value type. This is important, because the user
3504 // may have asked for (e.g.) the AX register in i32 type. We need to
3505 // remember that AX is actually i16 to get the right extension.
3506 RegVT = *PhysReg.second->vt_begin();
3508 // This is a explicit reference to a physical register.
3509 Regs.push_back(PhysReg.first);
3511 // If this is an expanded reference, add the rest of the regs to Regs.
3513 TargetRegisterClass::iterator I = PhysReg.second->begin();
3514 TargetRegisterClass::iterator E = PhysReg.second->end();
3515 for (; *I != PhysReg.first; ++I)
3516 assert(I != E && "Didn't find reg!");
3518 // Already added the first reg.
3520 for (; NumRegs; --NumRegs, ++I) {
3521 assert(I != E && "Ran out of registers to allocate!");
3525 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3526 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3527 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3531 // Otherwise, if this was a reference to an LLVM register class, create vregs
3532 // for this reference.
3533 std::vector<unsigned> RegClassRegs;
3534 const TargetRegisterClass *RC = PhysReg.second;
3536 // If this is an early clobber or tied register, our regalloc doesn't know
3537 // how to maintain the constraint. If it isn't, go ahead and create vreg
3538 // and let the regalloc do the right thing.
3539 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3540 // If there is some other early clobber and this is an input register,
3541 // then we are forced to pre-allocate the input reg so it doesn't
3542 // conflict with the earlyclobber.
3543 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3544 RegVT = *PhysReg.second->vt_begin();
3546 if (OpInfo.ConstraintVT == MVT::Other)
3549 // Create the appropriate number of virtual registers.
3550 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3551 for (; NumRegs; --NumRegs)
3552 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3554 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3558 // Otherwise, we can't allocate it. Let the code below figure out how to
3559 // maintain these constraints.
3560 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3563 // This is a reference to a register class that doesn't directly correspond
3564 // to an LLVM register class. Allocate NumRegs consecutive, available,
3565 // registers from the class.
3566 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3567 OpInfo.ConstraintVT);
3570 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3571 unsigned NumAllocated = 0;
3572 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3573 unsigned Reg = RegClassRegs[i];
3574 // See if this register is available.
3575 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3576 (isInReg && InputRegs.count(Reg))) { // Already used.
3577 // Make sure we find consecutive registers.
3582 // Check to see if this register is allocatable (i.e. don't give out the
3585 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
3586 if (!RC) { // Couldn't allocate this register.
3587 // Reset NumAllocated to make sure we return consecutive registers.
3593 // Okay, this register is good, we can use it.
3596 // If we allocated enough consecutive registers, succeed.
3597 if (NumAllocated == NumRegs) {
3598 unsigned RegStart = (i-NumAllocated)+1;
3599 unsigned RegEnd = i+1;
3600 // Mark all of the allocated registers used.
3601 for (unsigned i = RegStart; i != RegEnd; ++i)
3602 Regs.push_back(RegClassRegs[i]);
3604 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3605 OpInfo.ConstraintVT);
3606 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3611 // Otherwise, we couldn't allocate enough registers for this.
3616 /// visitInlineAsm - Handle a call to an InlineAsm object.
3618 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3619 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3621 /// ConstraintOperands - Information about all of the constraints.
3622 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
3624 SDOperand Chain = getRoot();
3627 std::set<unsigned> OutputRegs, InputRegs;
3629 // Do a prepass over the constraints, canonicalizing them, and building up the
3630 // ConstraintOperands list.
3631 std::vector<InlineAsm::ConstraintInfo>
3632 ConstraintInfos = IA->ParseConstraints();
3634 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3635 // constraint. If so, we can't let the register allocator allocate any input
3636 // registers, because it will not know to avoid the earlyclobbered output reg.
3637 bool SawEarlyClobber = false;
3639 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3640 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3641 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
3642 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
3644 MVT::ValueType OpVT = MVT::Other;
3646 // Compute the value type for each operand.
3647 switch (OpInfo.Type) {
3648 case InlineAsm::isOutput:
3649 if (!OpInfo.isIndirect) {
3650 // The return value of the call is this value. As such, there is no
3651 // corresponding argument.
3652 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3653 OpVT = TLI.getValueType(CS.getType());
3655 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3658 case InlineAsm::isInput:
3659 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3661 case InlineAsm::isClobber:
3666 // If this is an input or an indirect output, process the call argument.
3667 // BasicBlocks are labels, currently appearing only in asm's.
3668 if (OpInfo.CallOperandVal) {
3669 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3670 OpInfo.CallOperand =
3671 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(
3672 OpInfo.CallOperandVal)]);
3674 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3675 const Type *OpTy = OpInfo.CallOperandVal->getType();
3676 // If this is an indirect operand, the operand is a pointer to the
3678 if (OpInfo.isIndirect)
3679 OpTy = cast<PointerType>(OpTy)->getElementType();
3681 // If OpTy is not a first-class value, it may be a struct/union that we
3682 // can tile with integers.
3683 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3684 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3692 OpTy = IntegerType::get(BitSize);
3697 OpVT = TLI.getValueType(OpTy, true);
3701 OpInfo.ConstraintVT = OpVT;
3703 // Compute the constraint code and ConstraintType to use.
3704 OpInfo.ComputeConstraintToUse(TLI);
3706 // Keep track of whether we see an earlyclobber.
3707 SawEarlyClobber |= OpInfo.isEarlyClobber;
3709 // If we see a clobber of a register, it is an early clobber.
3710 if (!SawEarlyClobber &&
3711 OpInfo.Type == InlineAsm::isClobber &&
3712 OpInfo.ConstraintType == TargetLowering::C_Register) {
3713 // Note that we want to ignore things that we don't trick here, like
3714 // dirflag, fpsr, flags, etc.
3715 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3716 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3717 OpInfo.ConstraintVT);
3718 if (PhysReg.first || PhysReg.second) {
3719 // This is a register we know of.
3720 SawEarlyClobber = true;
3724 // If this is a memory input, and if the operand is not indirect, do what we
3725 // need to to provide an address for the memory input.
3726 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3727 !OpInfo.isIndirect) {
3728 assert(OpInfo.Type == InlineAsm::isInput &&
3729 "Can only indirectify direct input operands!");
3731 // Memory operands really want the address of the value. If we don't have
3732 // an indirect input, put it in the constpool if we can, otherwise spill
3733 // it to a stack slot.
3735 // If the operand is a float, integer, or vector constant, spill to a
3736 // constant pool entry to get its address.
3737 Value *OpVal = OpInfo.CallOperandVal;
3738 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3739 isa<ConstantVector>(OpVal)) {
3740 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3741 TLI.getPointerTy());
3743 // Otherwise, create a stack slot and emit a store to it before the
3745 const Type *Ty = OpVal->getType();
3746 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3747 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3748 MachineFunction &MF = DAG.getMachineFunction();
3749 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3750 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3751 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3752 OpInfo.CallOperand = StackSlot;
3755 // There is no longer a Value* corresponding to this operand.
3756 OpInfo.CallOperandVal = 0;
3757 // It is now an indirect operand.
3758 OpInfo.isIndirect = true;
3761 // If this constraint is for a specific register, allocate it before
3763 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3764 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3766 ConstraintInfos.clear();
3769 // Second pass - Loop over all of the operands, assigning virtual or physregs
3770 // to registerclass operands.
3771 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3772 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
3774 // C_Register operands have already been allocated, Other/Memory don't need
3776 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3777 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3780 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3781 std::vector<SDOperand> AsmNodeOperands;
3782 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3783 AsmNodeOperands.push_back(
3784 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3787 // Loop over all of the inputs, copying the operand values into the
3788 // appropriate registers and processing the output regs.
3789 RegsForValue RetValRegs;
3791 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3792 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3794 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3795 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
3797 switch (OpInfo.Type) {
3798 case InlineAsm::isOutput: {
3799 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3800 OpInfo.ConstraintType != TargetLowering::C_Register) {
3801 // Memory output, or 'other' output (e.g. 'X' constraint).
3802 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3804 // Add information to the INLINEASM node to know about this output.
3805 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3806 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3807 TLI.getPointerTy()));
3808 AsmNodeOperands.push_back(OpInfo.CallOperand);
3812 // Otherwise, this is a register or register class output.
3814 // Copy the output from the appropriate register. Find a register that
3816 if (OpInfo.AssignedRegs.Regs.empty()) {
3817 cerr << "Couldn't allocate output reg for contraint '"
3818 << OpInfo.ConstraintCode << "'!\n";
3822 if (!OpInfo.isIndirect) {
3823 // This is the result value of the call.
3824 assert(RetValRegs.Regs.empty() &&
3825 "Cannot have multiple output constraints yet!");
3826 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3827 RetValRegs = OpInfo.AssignedRegs;
3829 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3830 OpInfo.CallOperandVal));
3833 // Add information to the INLINEASM node to know that this register is
3835 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3839 case InlineAsm::isInput: {
3840 SDOperand InOperandVal = OpInfo.CallOperand;
3842 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3843 // If this is required to match an output register we have already set,
3844 // just use its register.
3845 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3847 // Scan until we find the definition we already emitted of this operand.
3848 // When we find it, create a RegsForValue operand.
3849 unsigned CurOp = 2; // The first operand.
3850 for (; OperandNo; --OperandNo) {
3851 // Advance to the next operand.
3853 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3854 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3855 (NumOps & 7) == 4 /*MEM*/) &&
3856 "Skipped past definitions?");
3857 CurOp += (NumOps>>3)+1;
3861 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3862 if ((NumOps & 7) == 2 /*REGDEF*/) {
3863 // Add NumOps>>3 registers to MatchedRegs.
3864 RegsForValue MatchedRegs;
3865 MatchedRegs.ValueVT = InOperandVal.getValueType();
3866 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3867 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3869 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3870 MatchedRegs.Regs.push_back(Reg);
3873 // Use the produced MatchedRegs object to
3874 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3875 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3878 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3879 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
3880 // Add information to the INLINEASM node to know about this input.
3881 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3882 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3883 TLI.getPointerTy()));
3884 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
3889 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3890 assert(!OpInfo.isIndirect &&
3891 "Don't know how to handle indirect other inputs yet!");
3893 std::vector<SDOperand> Ops;
3894 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3897 cerr << "Invalid operand for inline asm constraint '"
3898 << OpInfo.ConstraintCode << "'!\n";
3902 // Add information to the INLINEASM node to know about this input.
3903 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3904 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3905 TLI.getPointerTy()));
3906 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3908 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3909 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3910 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3911 "Memory operands expect pointer values");
3913 // Add information to the INLINEASM node to know about this input.
3914 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3915 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3916 TLI.getPointerTy()));
3917 AsmNodeOperands.push_back(InOperandVal);
3921 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3922 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3923 "Unknown constraint type!");
3924 assert(!OpInfo.isIndirect &&
3925 "Don't know how to handle indirect register inputs yet!");
3927 // Copy the input into the appropriate registers.
3928 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3929 "Couldn't allocate input reg!");
3931 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3933 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3937 case InlineAsm::isClobber: {
3938 // Add the clobbered value to the operand list, so that the register
3939 // allocator is aware that the physreg got clobbered.
3940 if (!OpInfo.AssignedRegs.Regs.empty())
3941 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3948 // Finish up input operands.
3949 AsmNodeOperands[0] = Chain;
3950 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3952 Chain = DAG.getNode(ISD::INLINEASM,
3953 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3954 &AsmNodeOperands[0], AsmNodeOperands.size());
3955 Flag = Chain.getValue(1);
3957 // If this asm returns a register value, copy the result from that register
3958 // and set it as the value of the call.
3959 if (!RetValRegs.Regs.empty()) {
3960 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3962 // If the result of the inline asm is a vector, it may have the wrong
3963 // width/num elts. Make sure to convert it to the right type with
3965 if (MVT::isVector(Val.getValueType())) {
3966 const VectorType *VTy = cast<VectorType>(CS.getType());
3967 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3969 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3972 setValue(CS.getInstruction(), Val);
3975 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3977 // Process indirect outputs, first output all of the flagged copies out of
3979 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3980 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3981 Value *Ptr = IndirectStoresToEmit[i].second;
3982 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3983 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3986 // Emit the non-flagged stores from the physregs.
3987 SmallVector<SDOperand, 8> OutChains;
3988 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3989 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3990 getValue(StoresToEmit[i].second),
3991 StoresToEmit[i].second, 0));
3992 if (!OutChains.empty())
3993 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3994 &OutChains[0], OutChains.size());
3999 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4000 SDOperand Src = getValue(I.getOperand(0));
4002 MVT::ValueType IntPtr = TLI.getPointerTy();
4004 if (IntPtr < Src.getValueType())
4005 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4006 else if (IntPtr > Src.getValueType())
4007 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4009 // Scale the source by the type size.
4010 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4011 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4012 Src, DAG.getIntPtrConstant(ElementSize));
4014 TargetLowering::ArgListTy Args;
4015 TargetLowering::ArgListEntry Entry;
4017 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4018 Args.push_back(Entry);
4020 std::pair<SDOperand,SDOperand> Result =
4021 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4022 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4023 setValue(&I, Result.first); // Pointers always fit in registers
4024 DAG.setRoot(Result.second);
4027 void SelectionDAGLowering::visitFree(FreeInst &I) {
4028 TargetLowering::ArgListTy Args;
4029 TargetLowering::ArgListEntry Entry;
4030 Entry.Node = getValue(I.getOperand(0));
4031 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4032 Args.push_back(Entry);
4033 MVT::ValueType IntPtr = TLI.getPointerTy();
4034 std::pair<SDOperand,SDOperand> Result =
4035 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4036 CallingConv::C, true,
4037 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4038 DAG.setRoot(Result.second);
4041 // EmitInstrWithCustomInserter - This method should be implemented by targets
4042 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4043 // instructions are special in various ways, which require special support to
4044 // insert. The specified MachineInstr is created but not inserted into any
4045 // basic blocks, and the scheduler passes ownership of it to this method.
4046 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4047 MachineBasicBlock *MBB) {
4048 cerr << "If a target marks an instruction with "
4049 << "'usesCustomDAGSchedInserter', it must implement "
4050 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4055 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4056 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4057 getValue(I.getOperand(1)),
4058 DAG.getSrcValue(I.getOperand(1))));
4061 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4062 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4063 getValue(I.getOperand(0)),
4064 DAG.getSrcValue(I.getOperand(0)));
4066 DAG.setRoot(V.getValue(1));
4069 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4070 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4071 getValue(I.getOperand(1)),
4072 DAG.getSrcValue(I.getOperand(1))));
4075 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4076 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4077 getValue(I.getOperand(1)),
4078 getValue(I.getOperand(2)),
4079 DAG.getSrcValue(I.getOperand(1)),
4080 DAG.getSrcValue(I.getOperand(2))));
4083 /// TargetLowering::LowerArguments - This is the default LowerArguments
4084 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4085 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4086 /// integrated into SDISel.
4087 std::vector<SDOperand>
4088 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
4089 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4090 std::vector<SDOperand> Ops;
4091 Ops.push_back(DAG.getRoot());
4092 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4093 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4095 // Add one result value for each formal argument.
4096 std::vector<MVT::ValueType> RetVals;
4098 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4100 MVT::ValueType VT = getValueType(I->getType());
4101 ISD::ArgFlagsTy Flags;
4102 unsigned OriginalAlignment =
4103 getTargetData()->getABITypeAlignment(I->getType());
4105 if (F.paramHasAttr(j, ParamAttr::ZExt))
4107 if (F.paramHasAttr(j, ParamAttr::SExt))
4109 if (F.paramHasAttr(j, ParamAttr::InReg))
4111 if (F.paramHasAttr(j, ParamAttr::StructRet))
4113 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4115 const PointerType *Ty = cast<PointerType>(I->getType());
4116 const Type *ElementTy = Ty->getElementType();
4117 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4118 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4119 // For ByVal, alignment should be passed from FE. BE will guess if
4120 // this info is not there but there are cases it cannot get right.
4121 if (F.getParamAlignment(j))
4122 FrameAlign = F.getParamAlignment(j);
4123 Flags.setByValAlign(FrameAlign);
4124 Flags.setByValSize(FrameSize);
4126 if (F.paramHasAttr(j, ParamAttr::Nest))
4128 Flags.setOrigAlign(OriginalAlignment);
4130 MVT::ValueType RegisterVT = getRegisterType(VT);
4131 unsigned NumRegs = getNumRegisters(VT);
4132 for (unsigned i = 0; i != NumRegs; ++i) {
4133 RetVals.push_back(RegisterVT);
4134 // if it isn't first piece, alignment must be 1
4136 Flags.setOrigAlign(1);
4137 Ops.push_back(DAG.getArgFlags(Flags));
4141 RetVals.push_back(MVT::Other);
4144 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4145 DAG.getVTList(&RetVals[0], RetVals.size()),
4146 &Ops[0], Ops.size()).Val;
4148 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4149 // allows exposing the loads that may be part of the argument access to the
4150 // first DAGCombiner pass.
4151 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4153 // The number of results should match up, except that the lowered one may have
4154 // an extra flag result.
4155 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4156 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4157 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4158 && "Lowering produced unexpected number of results!");
4159 Result = TmpRes.Val;
4161 unsigned NumArgRegs = Result->getNumValues() - 1;
4162 DAG.setRoot(SDOperand(Result, NumArgRegs));
4164 // Set up the return result vector.
4168 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4170 MVT::ValueType VT = getValueType(I->getType());
4171 MVT::ValueType PartVT = getRegisterType(VT);
4173 unsigned NumParts = getNumRegisters(VT);
4174 SmallVector<SDOperand, 4> Parts(NumParts);
4175 for (unsigned j = 0; j != NumParts; ++j)
4176 Parts[j] = SDOperand(Result, i++);
4178 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4179 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4180 AssertOp = ISD::AssertSext;
4181 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4182 AssertOp = ISD::AssertZext;
4184 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4187 assert(i == NumArgRegs && "Argument register count mismatch!");
4192 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4193 /// implementation, which just inserts an ISD::CALL node, which is later custom
4194 /// lowered by the target to something concrete. FIXME: When all targets are
4195 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4196 std::pair<SDOperand, SDOperand>
4197 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4198 bool RetSExt, bool RetZExt, bool isVarArg,
4199 unsigned CallingConv, bool isTailCall,
4201 ArgListTy &Args, SelectionDAG &DAG) {
4202 SmallVector<SDOperand, 32> Ops;
4203 Ops.push_back(Chain); // Op#0 - Chain
4204 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4205 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4206 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4207 Ops.push_back(Callee);
4209 // Handle all of the outgoing arguments.
4210 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4211 MVT::ValueType VT = getValueType(Args[i].Ty);
4212 SDOperand Op = Args[i].Node;
4213 ISD::ArgFlagsTy Flags;
4214 unsigned OriginalAlignment =
4215 getTargetData()->getABITypeAlignment(Args[i].Ty);
4221 if (Args[i].isInReg)
4225 if (Args[i].isByVal) {
4227 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4228 const Type *ElementTy = Ty->getElementType();
4229 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4230 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4231 // For ByVal, alignment should come from FE. BE will guess if this
4232 // info is not there but there are cases it cannot get right.
4233 if (Args[i].Alignment)
4234 FrameAlign = Args[i].Alignment;
4235 Flags.setByValAlign(FrameAlign);
4236 Flags.setByValSize(FrameSize);
4240 Flags.setOrigAlign(OriginalAlignment);
4242 MVT::ValueType PartVT = getRegisterType(VT);
4243 unsigned NumParts = getNumRegisters(VT);
4244 SmallVector<SDOperand, 4> Parts(NumParts);
4245 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4248 ExtendKind = ISD::SIGN_EXTEND;
4249 else if (Args[i].isZExt)
4250 ExtendKind = ISD::ZERO_EXTEND;
4252 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4254 for (unsigned i = 0; i != NumParts; ++i) {
4255 // if it isn't first piece, alignment must be 1
4256 ISD::ArgFlagsTy MyFlags = Flags;
4258 MyFlags.setOrigAlign(1);
4260 Ops.push_back(Parts[i]);
4261 Ops.push_back(DAG.getArgFlags(MyFlags));
4265 // Figure out the result value types. We start by making a list of
4266 // the high-level LLVM return types.
4267 SmallVector<const Type *, 4> LLVMRetTys;
4268 if (const StructType *ST = dyn_cast<StructType>(RetTy))
4269 // A struct return type in the LLVM IR means we have multiple return values.
4270 LLVMRetTys.insert(LLVMRetTys.end(), ST->element_begin(), ST->element_end());
4272 LLVMRetTys.push_back(RetTy);
4274 // Then we translate that to a list of lowered codegen result types.
4275 SmallVector<MVT::ValueType, 4> LoweredRetTys;
4276 SmallVector<MVT::ValueType, 4> RetTys;
4277 for (unsigned I = 0, E = LLVMRetTys.size(); I != E; ++I) {
4278 MVT::ValueType VT = getValueType(LLVMRetTys[I]);
4279 RetTys.push_back(VT);
4281 MVT::ValueType RegisterVT = getRegisterType(VT);
4282 unsigned NumRegs = getNumRegisters(VT);
4283 for (unsigned i = 0; i != NumRegs; ++i)
4284 LoweredRetTys.push_back(RegisterVT);
4287 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4289 // Create the CALL node.
4290 SDOperand Res = DAG.getNode(ISD::CALL,
4291 DAG.getVTList(&LoweredRetTys[0],
4292 LoweredRetTys.size()),
4293 &Ops[0], Ops.size());
4294 Chain = Res.getValue(LoweredRetTys.size() - 1);
4296 // Gather up the call result into a single value.
4297 if (RetTy != Type::VoidTy) {
4298 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4301 AssertOp = ISD::AssertSext;
4303 AssertOp = ISD::AssertZext;
4305 SmallVector<SDOperand, 4> ReturnValues;
4307 for (unsigned I = 0, E = LLVMRetTys.size(); I != E; ++I) {
4308 MVT::ValueType VT = getValueType(LLVMRetTys[I]);
4309 MVT::ValueType RegisterVT = getRegisterType(VT);
4310 unsigned NumRegs = getNumRegisters(VT);
4311 unsigned RegNoEnd = NumRegs + RegNo;
4312 SmallVector<SDOperand, 4> Results;
4313 for (; RegNo != RegNoEnd; ++RegNo)
4314 Results.push_back(Res.getValue(RegNo));
4315 SDOperand ReturnValue =
4316 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4318 ReturnValues.push_back(ReturnValue);
4320 Res = ReturnValues.size() == 1 ? ReturnValues.front() :
4321 DAG.getNode(ISD::MERGE_VALUES,
4322 DAG.getVTList(&RetTys[0], RetTys.size()),
4323 &ReturnValues[0], ReturnValues.size());
4326 return std::make_pair(Res, Chain);
4329 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4330 assert(0 && "LowerOperation not implemented for this target!");
4335 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4336 SelectionDAG &DAG) {
4337 assert(0 && "CustomPromoteOperation not implemented for this target!");
4342 /// getMemsetValue - Vectorized representation of the memset value
4344 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4345 SelectionDAG &DAG) {
4346 MVT::ValueType CurVT = VT;
4347 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4348 uint64_t Val = C->getValue() & 255;
4350 while (CurVT != MVT::i8) {
4351 Val = (Val << Shift) | Val;
4353 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4355 return DAG.getConstant(Val, VT);
4357 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4359 while (CurVT != MVT::i8) {
4361 DAG.getNode(ISD::OR, VT,
4362 DAG.getNode(ISD::SHL, VT, Value,
4363 DAG.getConstant(Shift, MVT::i8)), Value);
4365 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4372 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4373 /// used when a memcpy is turned into a memset when the source is a constant
4375 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4376 SelectionDAG &DAG, TargetLowering &TLI,
4377 std::string &Str, unsigned Offset) {
4379 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4380 if (TLI.isLittleEndian())
4381 Offset = Offset + MSB - 1;
4382 for (unsigned i = 0; i != MSB; ++i) {
4383 Val = (Val << 8) | (unsigned char)Str[Offset];
4384 Offset += TLI.isLittleEndian() ? -1 : 1;
4386 return DAG.getConstant(Val, VT);
4389 /// getMemBasePlusOffset - Returns base and offset node for the
4390 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4391 SelectionDAG &DAG, TargetLowering &TLI) {
4392 MVT::ValueType VT = Base.getValueType();
4393 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4396 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4397 /// to replace the memset / memcpy is below the threshold. It also returns the
4398 /// types of the sequence of memory ops to perform memset / memcpy.
4399 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4400 unsigned Limit, uint64_t Size,
4401 unsigned Align, TargetLowering &TLI) {
4404 if (TLI.allowsUnalignedMemoryAccesses()) {
4407 switch (Align & 7) {
4423 MVT::ValueType LVT = MVT::i64;
4424 while (!TLI.isTypeLegal(LVT))
4425 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4426 assert(MVT::isInteger(LVT));
4431 unsigned NumMemOps = 0;
4433 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4434 while (VTSize > Size) {
4435 VT = (MVT::ValueType)((unsigned)VT - 1);
4438 assert(MVT::isInteger(VT));
4440 if (++NumMemOps > Limit)
4442 MemOps.push_back(VT);
4449 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4450 SDOperand Op1 = getValue(I.getOperand(1));
4451 SDOperand Op2 = getValue(I.getOperand(2));
4452 SDOperand Op3 = getValue(I.getOperand(3));
4453 SDOperand Op4 = getValue(I.getOperand(4));
4454 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4455 if (Align == 0) Align = 1;
4457 // If the source and destination are known to not be aliases, we can
4458 // lower memmove as memcpy.
4459 if (Op == ISD::MEMMOVE) {
4460 uint64_t Size = -1ULL;
4461 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4462 Size = C->getValue();
4463 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4464 AliasAnalysis::NoAlias)
4468 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4469 std::vector<MVT::ValueType> MemOps;
4471 // Expand memset / memcpy to a series of load / store ops
4472 // if the size operand falls below a certain threshold.
4473 SmallVector<SDOperand, 8> OutChains;
4475 default: break; // Do nothing for now.
4477 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4478 Size->getValue(), Align, TLI)) {
4479 unsigned NumMemOps = MemOps.size();
4480 unsigned Offset = 0;
4481 for (unsigned i = 0; i < NumMemOps; i++) {
4482 MVT::ValueType VT = MemOps[i];
4483 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4484 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4485 SDOperand Store = DAG.getStore(getRoot(), Value,
4486 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4487 I.getOperand(1), Offset);
4488 OutChains.push_back(Store);
4495 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4496 Size->getValue(), Align, TLI)) {
4497 unsigned NumMemOps = MemOps.size();
4498 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4499 GlobalAddressSDNode *G = NULL;
4501 bool CopyFromStr = false;
4503 if (Op2.getOpcode() == ISD::GlobalAddress)
4504 G = cast<GlobalAddressSDNode>(Op2);
4505 else if (Op2.getOpcode() == ISD::ADD &&
4506 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4507 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4508 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4509 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4512 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4513 if (GV && GV->isConstant()) {
4514 Str = GV->getStringValue(false);
4522 for (unsigned i = 0; i < NumMemOps; i++) {
4523 MVT::ValueType VT = MemOps[i];
4524 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4525 SDOperand Value, Chain, Store;
4528 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4531 DAG.getStore(Chain, Value,
4532 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4533 I.getOperand(1), DstOff);
4535 Value = DAG.getLoad(VT, getRoot(),
4536 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4537 I.getOperand(2), SrcOff, false, Align);
4538 Chain = Value.getValue(1);
4540 DAG.getStore(Chain, Value,
4541 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4542 I.getOperand(1), DstOff, false, Align);
4544 OutChains.push_back(Store);
4553 if (!OutChains.empty()) {
4554 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4555 &OutChains[0], OutChains.size()));
4560 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4564 assert(0 && "Unknown Op");
4566 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4569 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4572 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4578 //===----------------------------------------------------------------------===//
4579 // SelectionDAGISel code
4580 //===----------------------------------------------------------------------===//
4582 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4583 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4586 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4587 AU.addRequired<AliasAnalysis>();
4588 AU.addRequired<CollectorModuleMetadata>();
4589 AU.setPreservesAll();
4594 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4595 // Get alias analysis for load/store combining.
4596 AA = &getAnalysis<AliasAnalysis>();
4598 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4599 if (MF.getFunction()->hasCollector())
4600 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4603 RegInfo = &MF.getRegInfo();
4604 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4606 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4608 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4609 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4610 // Mark landing pad.
4611 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4613 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4614 SelectBasicBlock(I, MF, FuncInfo);
4616 // Add function live-ins to entry block live-in set.
4617 BasicBlock *EntryBB = &Fn.getEntryBlock();
4618 BB = FuncInfo.MBBMap[EntryBB];
4619 if (!RegInfo->livein_empty())
4620 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4621 E = RegInfo->livein_end(); I != E; ++I)
4622 BB->addLiveIn(I->first);
4625 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4626 "Not all catch info was assigned to a landing pad!");
4632 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4634 SDOperand Op = getValue(V);
4635 assert((Op.getOpcode() != ISD::CopyFromReg ||
4636 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4637 "Copy from a reg to the same reg!");
4638 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4640 MVT::ValueType SrcVT = Op.getValueType();
4641 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4642 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4643 SmallVector<SDOperand, 8> Regs(NumRegs);
4644 SmallVector<SDOperand, 8> Chains(NumRegs);
4646 // Copy the value by legal parts into sequential virtual registers.
4647 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4648 for (unsigned i = 0; i != NumRegs; ++i)
4649 Chains[i] = DAG.getCopyToReg(DAG.getEntryNode(), Reg + i, Regs[i]);
4650 SDOperand Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4651 PendingExports.push_back(Ch);
4654 void SelectionDAGISel::
4655 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4656 // If this is the entry block, emit arguments.
4657 Function &F = *LLVMBB->getParent();
4658 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4659 SDOperand OldRoot = SDL.DAG.getRoot();
4660 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4663 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4665 if (!AI->use_empty()) {
4666 SDL.setValue(AI, Args[a]);
4668 // If this argument is live outside of the entry block, insert a copy from
4669 // whereever we got it to the vreg that other BB's will reference it as.
4670 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4671 if (VMI != FuncInfo.ValueMap.end()) {
4672 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4676 // Finally, if the target has anything special to do, allow it to do so.
4677 // FIXME: this should insert code into the DAG!
4678 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4681 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4682 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4683 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4684 if (isSelector(I)) {
4685 // Apply the catch info to DestBB.
4686 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4688 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4689 FLI.CatchInfoFound.insert(I);
4694 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4695 /// DAG and fixes their tailcall attribute operand.
4696 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4697 TargetLowering& TLI) {
4698 SDNode * Ret = NULL;
4699 SDOperand Terminator = DAG.getRoot();
4702 if (Terminator.getOpcode() == ISD::RET) {
4703 Ret = Terminator.Val;
4706 // Fix tail call attribute of CALL nodes.
4707 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4708 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4709 if (BI->getOpcode() == ISD::CALL) {
4710 SDOperand OpRet(Ret, 0);
4711 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4712 bool isMarkedTailCall =
4713 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4714 // If CALL node has tail call attribute set to true and the call is not
4715 // eligible (no RET or the target rejects) the attribute is fixed to
4716 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4717 // must correctly identify tail call optimizable calls.
4718 if (isMarkedTailCall &&
4720 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4721 SmallVector<SDOperand, 32> Ops;
4723 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4724 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4728 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4730 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4736 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4737 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4738 FunctionLoweringInfo &FuncInfo) {
4739 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4741 // Lower any arguments needed in this block if this is the entry block.
4742 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4743 LowerArguments(LLVMBB, SDL);
4745 BB = FuncInfo.MBBMap[LLVMBB];
4746 SDL.setCurrentBasicBlock(BB);
4748 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4750 if (MMI && BB->isLandingPad()) {
4751 // Add a label to mark the beginning of the landing pad. Deletion of the
4752 // landing pad can thus be detected via the MachineModuleInfo.
4753 unsigned LabelID = MMI->addLandingPad(BB);
4754 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4755 DAG.getConstant(LabelID, MVT::i32),
4756 DAG.getConstant(1, MVT::i32)));
4758 // Mark exception register as live in.
4759 unsigned Reg = TLI.getExceptionAddressRegister();
4760 if (Reg) BB->addLiveIn(Reg);
4762 // Mark exception selector register as live in.
4763 Reg = TLI.getExceptionSelectorRegister();
4764 if (Reg) BB->addLiveIn(Reg);
4766 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4767 // function and list of typeids logically belong to the invoke (or, if you
4768 // like, the basic block containing the invoke), and need to be associated
4769 // with it in the dwarf exception handling tables. Currently however the
4770 // information is provided by an intrinsic (eh.selector) that can be moved
4771 // to unexpected places by the optimizers: if the unwind edge is critical,
4772 // then breaking it can result in the intrinsics being in the successor of
4773 // the landing pad, not the landing pad itself. This results in exceptions
4774 // not being caught because no typeids are associated with the invoke.
4775 // This may not be the only way things can go wrong, but it is the only way
4776 // we try to work around for the moment.
4777 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4779 if (Br && Br->isUnconditional()) { // Critical edge?
4780 BasicBlock::iterator I, E;
4781 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4786 // No catch info found - try to extract some from the successor.
4787 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4791 // Lower all of the non-terminator instructions.
4792 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4796 // Ensure that all instructions which are used outside of their defining
4797 // blocks are available as virtual registers. Invoke is handled elsewhere.
4798 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4799 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4800 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4801 if (VMI != FuncInfo.ValueMap.end())
4802 SDL.CopyValueToVirtualRegister(I, VMI->second);
4805 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4806 // ensure constants are generated when needed. Remember the virtual registers
4807 // that need to be added to the Machine PHI nodes as input. We cannot just
4808 // directly add them, because expansion might result in multiple MBB's for one
4809 // BB. As such, the start of the BB might correspond to a different MBB than
4812 TerminatorInst *TI = LLVMBB->getTerminator();
4814 // Emit constants only once even if used by multiple PHI nodes.
4815 std::map<Constant*, unsigned> ConstantsOut;
4817 // Vector bool would be better, but vector<bool> is really slow.
4818 std::vector<unsigned char> SuccsHandled;
4819 if (TI->getNumSuccessors())
4820 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4822 // Check successor nodes' PHI nodes that expect a constant to be available
4824 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4825 BasicBlock *SuccBB = TI->getSuccessor(succ);
4826 if (!isa<PHINode>(SuccBB->begin())) continue;
4827 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4829 // If this terminator has multiple identical successors (common for
4830 // switches), only handle each succ once.
4831 unsigned SuccMBBNo = SuccMBB->getNumber();
4832 if (SuccsHandled[SuccMBBNo]) continue;
4833 SuccsHandled[SuccMBBNo] = true;
4835 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4838 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4839 // nodes and Machine PHI nodes, but the incoming operands have not been
4841 for (BasicBlock::iterator I = SuccBB->begin();
4842 (PN = dyn_cast<PHINode>(I)); ++I) {
4843 // Ignore dead phi's.
4844 if (PN->use_empty()) continue;
4847 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4849 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4850 unsigned &RegOut = ConstantsOut[C];
4852 RegOut = FuncInfo.CreateRegForValue(C);
4853 SDL.CopyValueToVirtualRegister(C, RegOut);
4857 Reg = FuncInfo.ValueMap[PHIOp];
4859 assert(isa<AllocaInst>(PHIOp) &&
4860 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4861 "Didn't codegen value into a register!??");
4862 Reg = FuncInfo.CreateRegForValue(PHIOp);
4863 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
4867 // Remember that this register needs to added to the machine PHI node as
4868 // the input for this MBB.
4869 MVT::ValueType VT = TLI.getValueType(PN->getType());
4870 unsigned NumRegisters = TLI.getNumRegisters(VT);
4871 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4872 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4875 ConstantsOut.clear();
4877 // Lower the terminator after the copies are emitted.
4878 SDL.visit(*LLVMBB->getTerminator());
4880 // Copy over any CaseBlock records that may now exist due to SwitchInst
4881 // lowering, as well as any jump table information.
4882 SwitchCases.clear();
4883 SwitchCases = SDL.SwitchCases;
4885 JTCases = SDL.JTCases;
4886 BitTestCases.clear();
4887 BitTestCases = SDL.BitTestCases;
4889 // Make sure the root of the DAG is up-to-date.
4890 DAG.setRoot(SDL.getControlRoot());
4892 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4893 // with correct tailcall attribute so that the target can rely on the tailcall
4894 // attribute indicating whether the call is really eligible for tail call
4896 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4899 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4900 DOUT << "Lowered selection DAG:\n";
4903 // Run the DAG combiner in pre-legalize mode.
4904 DAG.Combine(false, *AA);
4906 DOUT << "Optimized lowered selection DAG:\n";
4909 // Second step, hack on the DAG until it only uses operations and types that
4910 // the target supports.
4911 #if 0 // Enable this some day.
4912 DAG.LegalizeTypes();
4913 // Someday even later, enable a dag combine pass here.
4917 DOUT << "Legalized selection DAG:\n";
4920 // Run the DAG combiner in post-legalize mode.
4921 DAG.Combine(true, *AA);
4923 DOUT << "Optimized legalized selection DAG:\n";
4926 if (ViewISelDAGs) DAG.viewGraph();
4928 // Third, instruction select all of the operations to machine code, adding the
4929 // code to the MachineBasicBlock.
4930 InstructionSelectBasicBlock(DAG);
4932 DOUT << "Selected machine code:\n";
4936 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4937 FunctionLoweringInfo &FuncInfo) {
4938 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4940 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4943 // First step, lower LLVM code to some DAG. This DAG may use operations and
4944 // types that are not supported by the target.
4945 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4947 // Second step, emit the lowered DAG as machine code.
4948 CodeGenAndEmitDAG(DAG);
4951 DOUT << "Total amount of phi nodes to update: "
4952 << PHINodesToUpdate.size() << "\n";
4953 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4954 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4955 << ", " << PHINodesToUpdate[i].second << ")\n";);
4957 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4958 // PHI nodes in successors.
4959 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4960 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4961 MachineInstr *PHI = PHINodesToUpdate[i].first;
4962 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4963 "This is not a machine PHI node that we are updating!");
4964 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4966 PHI->addOperand(MachineOperand::CreateMBB(BB));
4971 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4972 // Lower header first, if it wasn't already lowered
4973 if (!BitTestCases[i].Emitted) {
4974 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4976 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4977 // Set the current basic block to the mbb we wish to insert the code into
4978 BB = BitTestCases[i].Parent;
4979 HSDL.setCurrentBasicBlock(BB);
4981 HSDL.visitBitTestHeader(BitTestCases[i]);
4982 HSDAG.setRoot(HSDL.getRoot());
4983 CodeGenAndEmitDAG(HSDAG);
4986 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4987 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4989 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
4990 // Set the current basic block to the mbb we wish to insert the code into
4991 BB = BitTestCases[i].Cases[j].ThisBB;
4992 BSDL.setCurrentBasicBlock(BB);
4995 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4996 BitTestCases[i].Reg,
4997 BitTestCases[i].Cases[j]);
4999 BSDL.visitBitTestCase(BitTestCases[i].Default,
5000 BitTestCases[i].Reg,
5001 BitTestCases[i].Cases[j]);
5004 BSDAG.setRoot(BSDL.getRoot());
5005 CodeGenAndEmitDAG(BSDAG);
5009 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5010 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5011 MachineBasicBlock *PHIBB = PHI->getParent();
5012 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5013 "This is not a machine PHI node that we are updating!");
5014 // This is "default" BB. We have two jumps to it. From "header" BB and
5015 // from last "case" BB.
5016 if (PHIBB == BitTestCases[i].Default) {
5017 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5019 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5020 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5022 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5025 // One of "cases" BB.
5026 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5027 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5028 if (cBB->succ_end() !=
5029 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5030 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5032 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5038 // If the JumpTable record is filled in, then we need to emit a jump table.
5039 // Updating the PHI nodes is tricky in this case, since we need to determine
5040 // whether the PHI is a successor of the range check MBB or the jump table MBB
5041 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5042 // Lower header first, if it wasn't already lowered
5043 if (!JTCases[i].first.Emitted) {
5044 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5046 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5047 // Set the current basic block to the mbb we wish to insert the code into
5048 BB = JTCases[i].first.HeaderBB;
5049 HSDL.setCurrentBasicBlock(BB);
5051 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5052 HSDAG.setRoot(HSDL.getRoot());
5053 CodeGenAndEmitDAG(HSDAG);
5056 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5058 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5059 // Set the current basic block to the mbb we wish to insert the code into
5060 BB = JTCases[i].second.MBB;
5061 JSDL.setCurrentBasicBlock(BB);
5063 JSDL.visitJumpTable(JTCases[i].second);
5064 JSDAG.setRoot(JSDL.getRoot());
5065 CodeGenAndEmitDAG(JSDAG);
5068 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5069 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5070 MachineBasicBlock *PHIBB = PHI->getParent();
5071 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5072 "This is not a machine PHI node that we are updating!");
5073 // "default" BB. We can go there only from header BB.
5074 if (PHIBB == JTCases[i].second.Default) {
5075 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5077 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5079 // JT BB. Just iterate over successors here
5080 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5081 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5083 PHI->addOperand(MachineOperand::CreateMBB(BB));
5088 // If the switch block involved a branch to one of the actual successors, we
5089 // need to update PHI nodes in that block.
5090 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5091 MachineInstr *PHI = PHINodesToUpdate[i].first;
5092 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5093 "This is not a machine PHI node that we are updating!");
5094 if (BB->isSuccessor(PHI->getParent())) {
5095 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5097 PHI->addOperand(MachineOperand::CreateMBB(BB));
5101 // If we generated any switch lowering information, build and codegen any
5102 // additional DAGs necessary.
5103 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5104 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5106 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5108 // Set the current basic block to the mbb we wish to insert the code into
5109 BB = SwitchCases[i].ThisBB;
5110 SDL.setCurrentBasicBlock(BB);
5113 SDL.visitSwitchCase(SwitchCases[i]);
5114 SDAG.setRoot(SDL.getRoot());
5115 CodeGenAndEmitDAG(SDAG);
5117 // Handle any PHI nodes in successors of this chunk, as if we were coming
5118 // from the original BB before switch expansion. Note that PHI nodes can
5119 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5120 // handle them the right number of times.
5121 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5122 for (MachineBasicBlock::iterator Phi = BB->begin();
5123 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5124 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5125 for (unsigned pn = 0; ; ++pn) {
5126 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5127 if (PHINodesToUpdate[pn].first == Phi) {
5128 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5130 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5136 // Don't process RHS if same block as LHS.
5137 if (BB == SwitchCases[i].FalseBB)
5138 SwitchCases[i].FalseBB = 0;
5140 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5141 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5142 SwitchCases[i].FalseBB = 0;
5144 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5149 //===----------------------------------------------------------------------===//
5150 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5151 /// target node in the graph.
5152 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5153 if (ViewSchedDAGs) DAG.viewGraph();
5155 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5159 RegisterScheduler::setDefault(Ctor);
5162 ScheduleDAG *SL = Ctor(this, &DAG, BB);
5165 if (ViewSUnitDAGs) SL->viewGraph();
5171 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5172 return new HazardRecognizer();
5175 //===----------------------------------------------------------------------===//
5176 // Helper functions used by the generated instruction selector.
5177 //===----------------------------------------------------------------------===//
5178 // Calls to these methods are generated by tblgen.
5180 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5181 /// the dag combiner simplified the 255, we still want to match. RHS is the
5182 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5183 /// specified in the .td file (e.g. 255).
5184 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5185 int64_t DesiredMaskS) const {
5186 const APInt &ActualMask = RHS->getAPIntValue();
5187 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5189 // If the actual mask exactly matches, success!
5190 if (ActualMask == DesiredMask)
5193 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5194 if (ActualMask.intersects(~DesiredMask))
5197 // Otherwise, the DAG Combiner may have proven that the value coming in is
5198 // either already zero or is not demanded. Check for known zero input bits.
5199 APInt NeededMask = DesiredMask & ~ActualMask;
5200 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5203 // TODO: check to see if missing bits are just not demanded.
5205 // Otherwise, this pattern doesn't match.
5209 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5210 /// the dag combiner simplified the 255, we still want to match. RHS is the
5211 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5212 /// specified in the .td file (e.g. 255).
5213 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5214 int64_t DesiredMaskS) const {
5215 const APInt &ActualMask = RHS->getAPIntValue();
5216 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5218 // If the actual mask exactly matches, success!
5219 if (ActualMask == DesiredMask)
5222 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5223 if (ActualMask.intersects(~DesiredMask))
5226 // Otherwise, the DAG Combiner may have proven that the value coming in is
5227 // either already zero or is not demanded. Check for known zero input bits.
5228 APInt NeededMask = DesiredMask & ~ActualMask;
5230 APInt KnownZero, KnownOne;
5231 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5233 // If all the missing bits in the or are already known to be set, match!
5234 if ((NeededMask & KnownOne) == NeededMask)
5237 // TODO: check to see if missing bits are just not demanded.
5239 // Otherwise, this pattern doesn't match.
5244 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5245 /// by tblgen. Others should not call it.
5246 void SelectionDAGISel::
5247 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5248 std::vector<SDOperand> InOps;
5249 std::swap(InOps, Ops);
5251 Ops.push_back(InOps[0]); // input chain.
5252 Ops.push_back(InOps[1]); // input asm string.
5254 unsigned i = 2, e = InOps.size();
5255 if (InOps[e-1].getValueType() == MVT::Flag)
5256 --e; // Don't process a flag operand if it is here.
5259 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5260 if ((Flags & 7) != 4 /*MEM*/) {
5261 // Just skip over this operand, copying the operands verbatim.
5262 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5263 i += (Flags >> 3) + 1;
5265 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5266 // Otherwise, this is a memory operand. Ask the target to select it.
5267 std::vector<SDOperand> SelOps;
5268 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5269 cerr << "Could not match memory address. Inline asm failure!\n";
5273 // Add this to the output node.
5274 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5275 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5277 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5282 // Add the flag input back if present.
5283 if (e != InOps.size())
5284 Ops.push_back(InOps.back());
5287 char SelectionDAGISel::ID = 0;