1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SSARegMap.h"
37 #include "llvm/Target/MRegisterInfo.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetFrameInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
52 ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
55 ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
61 //===---------------------------------------------------------------------===//
63 /// RegisterScheduler class - Track the registration of instruction schedulers.
65 //===---------------------------------------------------------------------===//
66 MachinePassRegistry RegisterScheduler::Registry;
68 //===---------------------------------------------------------------------===//
70 /// ISHeuristic command line option for instruction schedulers.
72 //===---------------------------------------------------------------------===//
74 cl::opt<RegisterScheduler::FunctionPassCtor, false,
75 RegisterPassParser<RegisterScheduler> >
76 ISHeuristic("pre-RA-sched",
77 cl::init(&createDefaultScheduler),
78 cl::desc("Instruction schedulers available (before register allocation):"));
80 static RegisterScheduler
81 defaultListDAGScheduler("default", " Best scheduler for the target",
82 createDefaultScheduler);
85 namespace { struct AsmOperandInfo; }
88 /// RegsForValue - This struct represents the physical registers that a
89 /// particular value is assigned and the type information about the value.
90 /// This is needed because values can be promoted into larger registers and
91 /// expanded into multiple smaller registers than the value.
92 struct VISIBILITY_HIDDEN RegsForValue {
93 /// Regs - This list holds the register (for legal and promoted values)
94 /// or register set (for expanded values) that the value should be assigned
96 std::vector<unsigned> Regs;
98 /// RegVT - The value type of each register.
100 MVT::ValueType RegVT;
102 /// ValueVT - The value type of the LLVM value, which may be promoted from
103 /// RegVT or made from merging the two expanded parts.
104 MVT::ValueType ValueVT;
106 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
108 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
109 : RegVT(regvt), ValueVT(valuevt) {
112 RegsForValue(const std::vector<unsigned> ®s,
113 MVT::ValueType regvt, MVT::ValueType valuevt)
114 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
117 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
118 /// this value and returns the result as a ValueVT value. This uses
119 /// Chain/Flag as the input and updates them for the output Chain/Flag.
120 /// If the Flag pointer is NULL, no flag is used.
121 SDOperand getCopyFromRegs(SelectionDAG &DAG,
122 SDOperand &Chain, SDOperand *Flag) const;
124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
125 /// specified value into the registers specified by this object. This uses
126 /// Chain/Flag as the input and updates them for the output Chain/Flag.
127 /// If the Flag pointer is NULL, no flag is used.
128 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
129 SDOperand &Chain, SDOperand *Flag) const;
131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
132 /// operand list. This adds the code marker and includes the number of
133 /// values added into it.
134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
135 std::vector<SDOperand> &Ops) const;
140 //===--------------------------------------------------------------------===//
141 /// createDefaultScheduler - This creates an instruction scheduler appropriate
143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
145 MachineBasicBlock *BB) {
146 TargetLowering &TLI = IS->getTargetLowering();
148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
149 return createTDListDAGScheduler(IS, DAG, BB);
151 assert(TLI.getSchedulingPreference() ==
152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
153 return createBURRListDAGScheduler(IS, DAG, BB);
158 //===--------------------------------------------------------------------===//
159 /// FunctionLoweringInfo - This contains information that is global to a
160 /// function that is used when lowering a region of the function.
161 class FunctionLoweringInfo {
168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
173 /// ValueMap - Since we emit code for the function a basic block at a time,
174 /// we must remember which virtual registers hold the values for
175 /// cross-basic-block values.
176 DenseMap<const Value*, unsigned> ValueMap;
178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
179 /// the entry block. This allows the allocas to be efficiently referenced
180 /// anywhere in the function.
181 std::map<const AllocaInst*, int> StaticAllocaMap;
184 SmallSet<Instruction*, 8> CatchInfoLost;
185 SmallSet<Instruction*, 8> CatchInfoFound;
188 unsigned MakeReg(MVT::ValueType VT) {
189 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
192 /// isExportedInst - Return true if the specified value is an instruction
193 /// exported from its block.
194 bool isExportedInst(const Value *V) {
195 return ValueMap.count(V);
198 unsigned CreateRegForValue(const Value *V);
200 unsigned InitializeRegForValue(const Value *V) {
201 unsigned &R = ValueMap[V];
202 assert(R == 0 && "Already initialized this value register!");
203 return R = CreateRegForValue(V);
208 /// isSelector - Return true if this instruction is a call to the
209 /// eh.selector intrinsic.
210 static bool isSelector(Instruction *I) {
211 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
212 return II->getIntrinsicID() == Intrinsic::eh_selector;
216 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
217 /// PHI nodes or outside of the basic block that defines it, or used by a
218 /// switch instruction, which may expand to multiple basic blocks.
219 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
220 if (isa<PHINode>(I)) return true;
221 BasicBlock *BB = I->getParent();
222 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
223 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
224 // FIXME: Remove switchinst special case.
225 isa<SwitchInst>(*UI))
230 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
231 /// entry block, return true. This includes arguments used by switches, since
232 /// the switch may expand into multiple basic blocks.
233 static bool isOnlyUsedInEntryBlock(Argument *A) {
234 BasicBlock *Entry = A->getParent()->begin();
235 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
236 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
237 return false; // Use not in entry block.
241 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
242 Function &fn, MachineFunction &mf)
243 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
245 // Create a vreg for each argument register that is not dead and is used
246 // outside of the entry block for the function.
247 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
249 if (!isOnlyUsedInEntryBlock(AI))
250 InitializeRegForValue(AI);
252 // Initialize the mapping of values to registers. This is only set up for
253 // instruction values that are used outside of the block that defines
255 Function::iterator BB = Fn.begin(), EB = Fn.end();
256 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
257 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
258 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
259 const Type *Ty = AI->getAllocatedType();
260 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
262 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
265 TySize *= CUI->getZExtValue(); // Get total allocated size.
266 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
267 StaticAllocaMap[AI] =
268 MF.getFrameInfo()->CreateStackObject(TySize, Align);
271 for (; BB != EB; ++BB)
272 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
273 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
274 if (!isa<AllocaInst>(I) ||
275 !StaticAllocaMap.count(cast<AllocaInst>(I)))
276 InitializeRegForValue(I);
278 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
279 // also creates the initial PHI MachineInstrs, though none of the input
280 // operands are populated.
281 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
282 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
284 MF.getBasicBlockList().push_back(MBB);
286 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
289 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
290 if (PN->use_empty()) continue;
292 MVT::ValueType VT = TLI.getValueType(PN->getType());
293 unsigned NumRegisters = TLI.getNumRegisters(VT);
294 unsigned PHIReg = ValueMap[PN];
295 assert(PHIReg && "PHI node does not have an assigned virtual register!");
296 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
297 for (unsigned i = 0; i != NumRegisters; ++i)
298 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
303 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
304 /// the correctly promoted or expanded types. Assign these registers
305 /// consecutive vreg numbers and return the first assigned number.
306 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
307 MVT::ValueType VT = TLI.getValueType(V->getType());
309 unsigned NumRegisters = TLI.getNumRegisters(VT);
310 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
312 unsigned R = MakeReg(RegisterVT);
313 for (unsigned i = 1; i != NumRegisters; ++i)
319 //===----------------------------------------------------------------------===//
320 /// SelectionDAGLowering - This is the common target-independent lowering
321 /// implementation that is parameterized by a TargetLowering object.
322 /// Also, targets can overload any lowering method.
325 class SelectionDAGLowering {
326 MachineBasicBlock *CurMBB;
328 DenseMap<const Value*, SDOperand> NodeMap;
330 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
331 /// them up and then emit token factor nodes when possible. This allows us to
332 /// get simple disambiguation between loads without worrying about alias
334 std::vector<SDOperand> PendingLoads;
336 /// Case - A struct to record the Value for a switch case, and the
337 /// case's target basic block.
341 MachineBasicBlock* BB;
343 Case() : Low(0), High(0), BB(0) { }
344 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
345 Low(low), High(high), BB(bb) { }
346 uint64_t size() const {
347 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
348 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
349 return (rHigh - rLow + 1ULL);
355 MachineBasicBlock* BB;
358 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
359 Mask(mask), BB(bb), Bits(bits) { }
362 typedef std::vector<Case> CaseVector;
363 typedef std::vector<CaseBits> CaseBitsVector;
364 typedef CaseVector::iterator CaseItr;
365 typedef std::pair<CaseItr, CaseItr> CaseRange;
367 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
368 /// of conditional branches.
370 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
371 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
373 /// CaseBB - The MBB in which to emit the compare and branch
374 MachineBasicBlock *CaseBB;
375 /// LT, GE - If nonzero, we know the current case value must be less-than or
376 /// greater-than-or-equal-to these Constants.
379 /// Range - A pair of iterators representing the range of case values to be
380 /// processed at this point in the binary search tree.
384 typedef std::vector<CaseRec> CaseRecVector;
386 /// The comparison function for sorting the switch case values in the vector.
387 /// WARNING: Case ranges should be disjoint!
389 bool operator () (const Case& C1, const Case& C2) {
390 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
391 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
392 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
393 return CI1->getValue().slt(CI2->getValue());
398 bool operator () (const CaseBits& C1, const CaseBits& C2) {
399 return C1.Bits > C2.Bits;
403 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
406 // TLI - This is information that describes the available target features we
407 // need for lowering. This indicates when operations are unavailable,
408 // implemented with a libcall, etc.
411 const TargetData *TD;
413 /// SwitchCases - Vector of CaseBlock structures used to communicate
414 /// SwitchInst code generation information.
415 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
416 /// JTCases - Vector of JumpTable structures used to communicate
417 /// SwitchInst code generation information.
418 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
419 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
421 /// FuncInfo - Information about the function as a whole.
423 FunctionLoweringInfo &FuncInfo;
425 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
426 FunctionLoweringInfo &funcinfo)
427 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
431 /// getRoot - Return the current virtual root of the Selection DAG.
433 SDOperand getRoot() {
434 if (PendingLoads.empty())
435 return DAG.getRoot();
437 if (PendingLoads.size() == 1) {
438 SDOperand Root = PendingLoads[0];
440 PendingLoads.clear();
444 // Otherwise, we have to make a token factor node.
445 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
446 &PendingLoads[0], PendingLoads.size());
447 PendingLoads.clear();
452 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
454 void visit(Instruction &I) { visit(I.getOpcode(), I); }
456 void visit(unsigned Opcode, User &I) {
457 // Note: this doesn't use InstVisitor, because it has to work with
458 // ConstantExpr's in addition to instructions.
460 default: assert(0 && "Unknown instruction type encountered!");
462 // Build the switch statement using the Instruction.def file.
463 #define HANDLE_INST(NUM, OPCODE, CLASS) \
464 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
465 #include "llvm/Instruction.def"
469 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
471 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
472 const Value *SV, SDOperand Root,
473 bool isVolatile, unsigned Alignment);
475 SDOperand getIntPtrConstant(uint64_t Val) {
476 return DAG.getConstant(Val, TLI.getPointerTy());
479 SDOperand getValue(const Value *V);
481 void setValue(const Value *V, SDOperand NewN) {
482 SDOperand &N = NodeMap[V];
483 assert(N.Val == 0 && "Already set a value for this node!");
487 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
488 std::set<unsigned> &OutputRegs,
489 std::set<unsigned> &InputRegs);
491 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
492 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
494 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
495 void ExportFromCurrentBlock(Value *V);
496 void LowerCallTo(Instruction &I,
497 const Type *CalledValueTy, unsigned CallingConv,
498 bool IsTailCall, SDOperand Callee, unsigned OpIdx,
499 MachineBasicBlock *LandingPad = NULL);
501 // Terminator instructions.
502 void visitRet(ReturnInst &I);
503 void visitBr(BranchInst &I);
504 void visitSwitch(SwitchInst &I);
505 void visitUnreachable(UnreachableInst &I) { /* noop */ }
507 // Helpers for visitSwitch
508 bool handleSmallSwitchRange(CaseRec& CR,
509 CaseRecVector& WorkList,
511 MachineBasicBlock* Default);
512 bool handleJTSwitchCase(CaseRec& CR,
513 CaseRecVector& WorkList,
515 MachineBasicBlock* Default);
516 bool handleBTSplitSwitchCase(CaseRec& CR,
517 CaseRecVector& WorkList,
519 MachineBasicBlock* Default);
520 bool handleBitTestsSwitchCase(CaseRec& CR,
521 CaseRecVector& WorkList,
523 MachineBasicBlock* Default);
524 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
525 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
526 void visitBitTestCase(MachineBasicBlock* NextMBB,
528 SelectionDAGISel::BitTestCase &B);
529 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
530 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
531 SelectionDAGISel::JumpTableHeader &JTH);
533 // These all get lowered before this pass.
534 void visitInvoke(InvokeInst &I);
535 void visitUnwind(UnwindInst &I);
537 void visitBinary(User &I, unsigned OpCode);
538 void visitShift(User &I, unsigned Opcode);
539 void visitAdd(User &I) {
540 if (I.getType()->isFPOrFPVector())
541 visitBinary(I, ISD::FADD);
543 visitBinary(I, ISD::ADD);
545 void visitSub(User &I);
546 void visitMul(User &I) {
547 if (I.getType()->isFPOrFPVector())
548 visitBinary(I, ISD::FMUL);
550 visitBinary(I, ISD::MUL);
552 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
553 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
554 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
555 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
556 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
557 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
558 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
559 void visitOr (User &I) { visitBinary(I, ISD::OR); }
560 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
561 void visitShl (User &I) { visitShift(I, ISD::SHL); }
562 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
563 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
564 void visitICmp(User &I);
565 void visitFCmp(User &I);
566 // Visit the conversion instructions
567 void visitTrunc(User &I);
568 void visitZExt(User &I);
569 void visitSExt(User &I);
570 void visitFPTrunc(User &I);
571 void visitFPExt(User &I);
572 void visitFPToUI(User &I);
573 void visitFPToSI(User &I);
574 void visitUIToFP(User &I);
575 void visitSIToFP(User &I);
576 void visitPtrToInt(User &I);
577 void visitIntToPtr(User &I);
578 void visitBitCast(User &I);
580 void visitExtractElement(User &I);
581 void visitInsertElement(User &I);
582 void visitShuffleVector(User &I);
584 void visitGetElementPtr(User &I);
585 void visitSelect(User &I);
587 void visitMalloc(MallocInst &I);
588 void visitFree(FreeInst &I);
589 void visitAlloca(AllocaInst &I);
590 void visitLoad(LoadInst &I);
591 void visitStore(StoreInst &I);
592 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
593 void visitCall(CallInst &I);
594 void visitInlineAsm(CallInst &I);
595 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
596 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
598 void visitVAStart(CallInst &I);
599 void visitVAArg(VAArgInst &I);
600 void visitVAEnd(CallInst &I);
601 void visitVACopy(CallInst &I);
603 void visitMemIntrinsic(CallInst &I, unsigned Op);
605 void visitUserOp1(Instruction &I) {
606 assert(0 && "UserOp1 should not exist at instruction selection time!");
609 void visitUserOp2(Instruction &I) {
610 assert(0 && "UserOp2 should not exist at instruction selection time!");
614 } // end namespace llvm
617 /// getCopyFromParts - Create a value that contains the
618 /// specified legal parts combined into the value they represent.
619 static SDOperand getCopyFromParts(SelectionDAG &DAG,
620 const SDOperand *Parts,
622 MVT::ValueType PartVT,
623 MVT::ValueType ValueVT,
624 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
625 if (!MVT::isVector(ValueVT) || NumParts == 1) {
626 SDOperand Val = Parts[0];
628 // If the value was expanded, copy from the top part.
630 assert(NumParts == 2 &&
631 "Cannot expand to more than 2 elts yet!");
632 SDOperand Hi = Parts[1];
633 if (!DAG.getTargetLoweringInfo().isLittleEndian())
635 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
638 // Otherwise, if the value was promoted or extended, truncate it to the
640 if (PartVT == ValueVT)
643 if (MVT::isVector(PartVT)) {
644 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
645 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
648 if (MVT::isInteger(PartVT) &&
649 MVT::isInteger(ValueVT)) {
650 if (ValueVT < PartVT) {
651 // For a truncate, see if we have any information to
652 // indicate whether the truncated bits will always be
653 // zero or sign-extension.
654 if (AssertOp != ISD::DELETED_NODE)
655 Val = DAG.getNode(AssertOp, PartVT, Val,
656 DAG.getValueType(ValueVT));
657 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
659 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
663 if (MVT::isFloatingPoint(PartVT) &&
664 MVT::isFloatingPoint(ValueVT))
665 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
667 if (MVT::getSizeInBits(PartVT) ==
668 MVT::getSizeInBits(ValueVT))
669 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
671 assert(0 && "Unknown mismatch!");
674 // Handle a multi-element vector.
675 MVT::ValueType IntermediateVT, RegisterVT;
676 unsigned NumIntermediates;
678 DAG.getTargetLoweringInfo()
679 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
682 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
683 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
684 assert(RegisterVT == Parts[0].getValueType() &&
685 "Part type doesn't match part!");
687 // Assemble the parts into intermediate operands.
688 SmallVector<SDOperand, 8> Ops(NumIntermediates);
689 if (NumIntermediates == NumParts) {
690 // If the register was not expanded, truncate or copy the value,
692 for (unsigned i = 0; i != NumParts; ++i)
693 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
694 PartVT, IntermediateVT);
695 } else if (NumParts > 0) {
696 // If the intermediate type was expanded, build the intermediate operands
698 assert(NumIntermediates % NumParts == 0 &&
699 "Must expand into a divisible number of parts!");
700 unsigned Factor = NumIntermediates / NumParts;
701 for (unsigned i = 0; i != NumIntermediates; ++i)
702 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
703 PartVT, IntermediateVT);
706 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
708 return DAG.getNode(MVT::isVector(IntermediateVT) ?
709 ISD::CONCAT_VECTORS :
711 ValueVT, &Ops[0], NumParts);
714 /// getCopyToParts - Create a series of nodes that contain the
715 /// specified value split into legal parts.
716 static void getCopyToParts(SelectionDAG &DAG,
720 MVT::ValueType PartVT) {
721 MVT::ValueType ValueVT = Val.getValueType();
723 if (!MVT::isVector(ValueVT) || NumParts == 1) {
724 // If the value was expanded, copy from the parts.
726 for (unsigned i = 0; i != NumParts; ++i)
727 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
728 DAG.getConstant(i, MVT::i32));
729 if (!DAG.getTargetLoweringInfo().isLittleEndian())
730 std::reverse(Parts, Parts + NumParts);
734 // If there is a single part and the types differ, this must be
736 if (PartVT != ValueVT) {
737 if (MVT::isVector(PartVT)) {
738 assert(MVT::isVector(ValueVT) &&
739 "Not a vector-vector cast?");
740 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
741 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
742 if (PartVT < ValueVT)
743 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
745 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
746 } else if (MVT::isFloatingPoint(PartVT) &&
747 MVT::isFloatingPoint(ValueVT)) {
748 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
749 } else if (MVT::getSizeInBits(PartVT) ==
750 MVT::getSizeInBits(ValueVT)) {
751 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
753 assert(0 && "Unknown mismatch!");
760 // Handle a multi-element vector.
761 MVT::ValueType IntermediateVT, RegisterVT;
762 unsigned NumIntermediates;
764 DAG.getTargetLoweringInfo()
765 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
767 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
769 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
770 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
772 // Split the vector into intermediate operands.
773 SmallVector<SDOperand, 8> Ops(NumIntermediates);
774 for (unsigned i = 0; i != NumIntermediates; ++i)
775 if (MVT::isVector(IntermediateVT))
776 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
778 DAG.getConstant(i * (NumElements / NumIntermediates),
781 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
783 DAG.getConstant(i, MVT::i32));
785 // Split the intermediate operands into legal parts.
786 if (NumParts == NumIntermediates) {
787 // If the register was not expanded, promote or copy the value,
789 for (unsigned i = 0; i != NumParts; ++i)
790 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
791 } else if (NumParts > 0) {
792 // If the intermediate type was expanded, split each the value into
794 assert(NumParts % NumIntermediates == 0 &&
795 "Must expand into a divisible number of parts!");
796 unsigned Factor = NumParts / NumIntermediates;
797 for (unsigned i = 0; i != NumIntermediates; ++i)
798 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
803 SDOperand SelectionDAGLowering::getValue(const Value *V) {
804 SDOperand &N = NodeMap[V];
807 const Type *VTy = V->getType();
808 MVT::ValueType VT = TLI.getValueType(VTy);
809 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
810 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
811 visit(CE->getOpcode(), *CE);
812 SDOperand N1 = NodeMap[V];
813 assert(N1.Val && "visit didn't populate the ValueMap!");
815 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
816 return N = DAG.getGlobalAddress(GV, VT);
817 } else if (isa<ConstantPointerNull>(C)) {
818 return N = DAG.getConstant(0, TLI.getPointerTy());
819 } else if (isa<UndefValue>(C)) {
820 if (!isa<VectorType>(VTy))
821 return N = DAG.getNode(ISD::UNDEF, VT);
823 // Create a BUILD_VECTOR of undef nodes.
824 const VectorType *PTy = cast<VectorType>(VTy);
825 unsigned NumElements = PTy->getNumElements();
826 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
828 SmallVector<SDOperand, 8> Ops;
829 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
831 // Create a VConstant node with generic Vector type.
832 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
833 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
834 &Ops[0], Ops.size());
835 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
836 return N = DAG.getConstantFP(CFP->getValue(), VT);
837 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
838 unsigned NumElements = PTy->getNumElements();
839 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
841 // Now that we know the number and type of the elements, push a
842 // Constant or ConstantFP node onto the ops list for each element of
843 // the packed constant.
844 SmallVector<SDOperand, 8> Ops;
845 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
846 for (unsigned i = 0; i != NumElements; ++i)
847 Ops.push_back(getValue(CP->getOperand(i)));
849 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
851 if (MVT::isFloatingPoint(PVT))
852 Op = DAG.getConstantFP(0, PVT);
854 Op = DAG.getConstant(0, PVT);
855 Ops.assign(NumElements, Op);
858 // Create a BUILD_VECTOR node.
859 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
860 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
863 // Canonicalize all constant ints to be unsigned.
864 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
868 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
869 std::map<const AllocaInst*, int>::iterator SI =
870 FuncInfo.StaticAllocaMap.find(AI);
871 if (SI != FuncInfo.StaticAllocaMap.end())
872 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
875 unsigned InReg = FuncInfo.ValueMap[V];
876 assert(InReg && "Value not in map!");
878 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
879 unsigned NumRegs = TLI.getNumRegisters(VT);
881 std::vector<unsigned> Regs(NumRegs);
882 for (unsigned i = 0; i != NumRegs; ++i)
885 RegsForValue RFV(Regs, RegisterVT, VT);
886 SDOperand Chain = DAG.getEntryNode();
888 return RFV.getCopyFromRegs(DAG, Chain, NULL);
892 void SelectionDAGLowering::visitRet(ReturnInst &I) {
893 if (I.getNumOperands() == 0) {
894 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
897 SmallVector<SDOperand, 8> NewValues;
898 NewValues.push_back(getRoot());
899 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
900 SDOperand RetOp = getValue(I.getOperand(i));
902 // If this is an integer return value, we need to promote it ourselves to
903 // the full width of a register, since getCopyToParts and Legalize will use
904 // ANY_EXTEND rather than sign/zero.
905 // FIXME: C calling convention requires the return type to be promoted to
906 // at least 32-bit. But this is not necessary for non-C calling conventions.
907 if (MVT::isInteger(RetOp.getValueType()) &&
908 RetOp.getValueType() < MVT::i64) {
909 MVT::ValueType TmpVT;
910 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
911 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
914 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType();
915 const ParamAttrsList *Attrs = FTy->getParamAttrs();
916 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
917 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt))
918 ExtendKind = ISD::SIGN_EXTEND;
919 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt))
920 ExtendKind = ISD::ZERO_EXTEND;
921 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
922 NewValues.push_back(RetOp);
923 NewValues.push_back(DAG.getConstant(false, MVT::i32));
925 MVT::ValueType VT = RetOp.getValueType();
926 unsigned NumParts = TLI.getNumRegisters(VT);
927 MVT::ValueType PartVT = TLI.getRegisterType(VT);
928 SmallVector<SDOperand, 4> Parts(NumParts);
929 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
930 for (unsigned i = 0; i < NumParts; ++i) {
931 NewValues.push_back(Parts[i]);
932 NewValues.push_back(DAG.getConstant(false, MVT::i32));
936 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
937 &NewValues[0], NewValues.size()));
940 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
941 /// the current basic block, add it to ValueMap now so that we'll get a
943 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
944 // No need to export constants.
945 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
948 if (FuncInfo.isExportedInst(V)) return;
950 unsigned Reg = FuncInfo.InitializeRegForValue(V);
951 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
954 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
955 const BasicBlock *FromBB) {
956 // The operands of the setcc have to be in this block. We don't know
957 // how to export them from some other block.
958 if (Instruction *VI = dyn_cast<Instruction>(V)) {
959 // Can export from current BB.
960 if (VI->getParent() == FromBB)
963 // Is already exported, noop.
964 return FuncInfo.isExportedInst(V);
967 // If this is an argument, we can export it if the BB is the entry block or
968 // if it is already exported.
969 if (isa<Argument>(V)) {
970 if (FromBB == &FromBB->getParent()->getEntryBlock())
973 // Otherwise, can only export this if it is already exported.
974 return FuncInfo.isExportedInst(V);
977 // Otherwise, constants can always be exported.
981 static bool InBlock(const Value *V, const BasicBlock *BB) {
982 if (const Instruction *I = dyn_cast<Instruction>(V))
983 return I->getParent() == BB;
987 /// FindMergedConditions - If Cond is an expression like
988 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
989 MachineBasicBlock *TBB,
990 MachineBasicBlock *FBB,
991 MachineBasicBlock *CurBB,
993 // If this node is not part of the or/and tree, emit it as a branch.
994 Instruction *BOp = dyn_cast<Instruction>(Cond);
996 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
997 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
998 BOp->getParent() != CurBB->getBasicBlock() ||
999 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1000 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1001 const BasicBlock *BB = CurBB->getBasicBlock();
1003 // If the leaf of the tree is a comparison, merge the condition into
1005 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1006 // The operands of the cmp have to be in this block. We don't know
1007 // how to export them from some other block. If this is the first block
1008 // of the sequence, no exporting is needed.
1010 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1011 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1012 BOp = cast<Instruction>(Cond);
1013 ISD::CondCode Condition;
1014 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1015 switch (IC->getPredicate()) {
1016 default: assert(0 && "Unknown icmp predicate opcode!");
1017 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1018 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1019 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1020 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1021 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1022 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1023 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1024 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1025 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1026 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1028 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1029 ISD::CondCode FPC, FOC;
1030 switch (FC->getPredicate()) {
1031 default: assert(0 && "Unknown fcmp predicate opcode!");
1032 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1033 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1034 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1035 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1036 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1037 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1038 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1039 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1040 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1041 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1042 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1043 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1044 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1045 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1046 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1047 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1049 if (FiniteOnlyFPMath())
1054 Condition = ISD::SETEQ; // silence warning.
1055 assert(0 && "Unknown compare instruction");
1058 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1059 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1060 SwitchCases.push_back(CB);
1064 // Create a CaseBlock record representing this branch.
1065 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1066 NULL, TBB, FBB, CurBB);
1067 SwitchCases.push_back(CB);
1072 // Create TmpBB after CurBB.
1073 MachineFunction::iterator BBI = CurBB;
1074 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1075 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1077 if (Opc == Instruction::Or) {
1078 // Codegen X | Y as:
1086 // Emit the LHS condition.
1087 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1089 // Emit the RHS condition into TmpBB.
1090 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1092 assert(Opc == Instruction::And && "Unknown merge op!");
1093 // Codegen X & Y as:
1100 // This requires creation of TmpBB after CurBB.
1102 // Emit the LHS condition.
1103 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1105 // Emit the RHS condition into TmpBB.
1106 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1110 /// If the set of cases should be emitted as a series of branches, return true.
1111 /// If we should emit this as a bunch of and/or'd together conditions, return
1114 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1115 if (Cases.size() != 2) return true;
1117 // If this is two comparisons of the same values or'd or and'd together, they
1118 // will get folded into a single comparison, so don't emit two blocks.
1119 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1120 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1121 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1122 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1129 void SelectionDAGLowering::visitBr(BranchInst &I) {
1130 // Update machine-CFG edges.
1131 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1133 // Figure out which block is immediately after the current one.
1134 MachineBasicBlock *NextBlock = 0;
1135 MachineFunction::iterator BBI = CurMBB;
1136 if (++BBI != CurMBB->getParent()->end())
1139 if (I.isUnconditional()) {
1140 // If this is not a fall-through branch, emit the branch.
1141 if (Succ0MBB != NextBlock)
1142 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1143 DAG.getBasicBlock(Succ0MBB)));
1145 // Update machine-CFG edges.
1146 CurMBB->addSuccessor(Succ0MBB);
1151 // If this condition is one of the special cases we handle, do special stuff
1153 Value *CondVal = I.getCondition();
1154 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1156 // If this is a series of conditions that are or'd or and'd together, emit
1157 // this as a sequence of branches instead of setcc's with and/or operations.
1158 // For example, instead of something like:
1171 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1172 if (BOp->hasOneUse() &&
1173 (BOp->getOpcode() == Instruction::And ||
1174 BOp->getOpcode() == Instruction::Or)) {
1175 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1176 // If the compares in later blocks need to use values not currently
1177 // exported from this block, export them now. This block should always
1178 // be the first entry.
1179 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1181 // Allow some cases to be rejected.
1182 if (ShouldEmitAsBranches(SwitchCases)) {
1183 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1184 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1185 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1188 // Emit the branch for this block.
1189 visitSwitchCase(SwitchCases[0]);
1190 SwitchCases.erase(SwitchCases.begin());
1194 // Okay, we decided not to do this, remove any inserted MBB's and clear
1196 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1197 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1199 SwitchCases.clear();
1203 // Create a CaseBlock record representing this branch.
1204 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1205 NULL, Succ0MBB, Succ1MBB, CurMBB);
1206 // Use visitSwitchCase to actually insert the fast branch sequence for this
1208 visitSwitchCase(CB);
1211 /// visitSwitchCase - Emits the necessary code to represent a single node in
1212 /// the binary search tree resulting from lowering a switch instruction.
1213 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1215 SDOperand CondLHS = getValue(CB.CmpLHS);
1217 // Build the setcc now.
1218 if (CB.CmpMHS == NULL) {
1219 // Fold "(X == true)" to X and "(X == false)" to !X to
1220 // handle common cases produced by branch lowering.
1221 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1223 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1224 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1225 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1227 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1229 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1231 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1232 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1234 SDOperand CmpOp = getValue(CB.CmpMHS);
1235 MVT::ValueType VT = CmpOp.getValueType();
1237 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1238 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1240 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1241 Cond = DAG.getSetCC(MVT::i1, SUB,
1242 DAG.getConstant(High-Low, VT), ISD::SETULE);
1247 // Set NextBlock to be the MBB immediately after the current one, if any.
1248 // This is used to avoid emitting unnecessary branches to the next block.
1249 MachineBasicBlock *NextBlock = 0;
1250 MachineFunction::iterator BBI = CurMBB;
1251 if (++BBI != CurMBB->getParent()->end())
1254 // If the lhs block is the next block, invert the condition so that we can
1255 // fall through to the lhs instead of the rhs block.
1256 if (CB.TrueBB == NextBlock) {
1257 std::swap(CB.TrueBB, CB.FalseBB);
1258 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1259 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1261 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1262 DAG.getBasicBlock(CB.TrueBB));
1263 if (CB.FalseBB == NextBlock)
1264 DAG.setRoot(BrCond);
1266 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1267 DAG.getBasicBlock(CB.FalseBB)));
1268 // Update successor info
1269 CurMBB->addSuccessor(CB.TrueBB);
1270 CurMBB->addSuccessor(CB.FalseBB);
1273 /// visitJumpTable - Emit JumpTable node in the current MBB
1274 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1275 // Emit the code for the jump table
1276 assert(JT.Reg != -1U && "Should lower JT Header first!");
1277 MVT::ValueType PTy = TLI.getPointerTy();
1278 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1279 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1280 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1285 /// visitJumpTableHeader - This function emits necessary code to produce index
1286 /// in the JumpTable from switch case.
1287 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1288 SelectionDAGISel::JumpTableHeader &JTH) {
1289 // Subtract the lowest switch case value from the value being switched on
1290 // and conditional branch to default mbb if the result is greater than the
1291 // difference between smallest and largest cases.
1292 SDOperand SwitchOp = getValue(JTH.SValue);
1293 MVT::ValueType VT = SwitchOp.getValueType();
1294 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1295 DAG.getConstant(JTH.First, VT));
1297 // The SDNode we just created, which holds the value being switched on
1298 // minus the the smallest case value, needs to be copied to a virtual
1299 // register so it can be used as an index into the jump table in a
1300 // subsequent basic block. This value may be smaller or larger than the
1301 // target's pointer type, and therefore require extension or truncating.
1302 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1303 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1305 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1307 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1308 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1309 JT.Reg = JumpTableReg;
1311 // Emit the range check for the jump table, and branch to the default
1312 // block for the switch statement if the value being switched on exceeds
1313 // the largest case in the switch.
1314 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1315 DAG.getConstant(JTH.Last-JTH.First,VT),
1318 // Set NextBlock to be the MBB immediately after the current one, if any.
1319 // This is used to avoid emitting unnecessary branches to the next block.
1320 MachineBasicBlock *NextBlock = 0;
1321 MachineFunction::iterator BBI = CurMBB;
1322 if (++BBI != CurMBB->getParent()->end())
1325 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1326 DAG.getBasicBlock(JT.Default));
1328 if (JT.MBB == NextBlock)
1329 DAG.setRoot(BrCond);
1331 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1332 DAG.getBasicBlock(JT.MBB)));
1337 /// visitBitTestHeader - This function emits necessary code to produce value
1338 /// suitable for "bit tests"
1339 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1340 // Subtract the minimum value
1341 SDOperand SwitchOp = getValue(B.SValue);
1342 MVT::ValueType VT = SwitchOp.getValueType();
1343 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1344 DAG.getConstant(B.First, VT));
1347 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1348 DAG.getConstant(B.Range, VT),
1352 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1353 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1355 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1357 // Make desired shift
1358 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1359 DAG.getConstant(1, TLI.getPointerTy()),
1362 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1363 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1366 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1367 DAG.getBasicBlock(B.Default));
1369 // Set NextBlock to be the MBB immediately after the current one, if any.
1370 // This is used to avoid emitting unnecessary branches to the next block.
1371 MachineBasicBlock *NextBlock = 0;
1372 MachineFunction::iterator BBI = CurMBB;
1373 if (++BBI != CurMBB->getParent()->end())
1376 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1377 if (MBB == NextBlock)
1378 DAG.setRoot(BrRange);
1380 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1381 DAG.getBasicBlock(MBB)));
1383 CurMBB->addSuccessor(B.Default);
1384 CurMBB->addSuccessor(MBB);
1389 /// visitBitTestCase - this function produces one "bit test"
1390 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1392 SelectionDAGISel::BitTestCase &B) {
1393 // Emit bit tests and jumps
1394 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1396 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1398 DAG.getConstant(B.Mask,
1399 TLI.getPointerTy()));
1400 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1401 DAG.getConstant(0, TLI.getPointerTy()),
1403 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1404 AndCmp, DAG.getBasicBlock(B.TargetBB));
1406 // Set NextBlock to be the MBB immediately after the current one, if any.
1407 // This is used to avoid emitting unnecessary branches to the next block.
1408 MachineBasicBlock *NextBlock = 0;
1409 MachineFunction::iterator BBI = CurMBB;
1410 if (++BBI != CurMBB->getParent()->end())
1413 if (NextMBB == NextBlock)
1416 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1417 DAG.getBasicBlock(NextMBB)));
1419 CurMBB->addSuccessor(B.TargetBB);
1420 CurMBB->addSuccessor(NextMBB);
1425 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1426 // Retrieve successors.
1427 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1428 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1430 LowerCallTo(I, I.getCalledValue()->getType(),
1433 getValue(I.getOperand(0)),
1436 // If the value of the invoke is used outside of its defining block, make it
1437 // available as a virtual register.
1438 if (!I.use_empty()) {
1439 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1440 if (VMI != FuncInfo.ValueMap.end())
1441 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1444 // Drop into normal successor.
1445 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1446 DAG.getBasicBlock(Return)));
1448 // Update successor info
1449 CurMBB->addSuccessor(Return);
1450 CurMBB->addSuccessor(LandingPad);
1453 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1456 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1457 /// small case ranges).
1458 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1459 CaseRecVector& WorkList,
1461 MachineBasicBlock* Default) {
1462 Case& BackCase = *(CR.Range.second-1);
1464 // Size is the number of Cases represented by this range.
1465 unsigned Size = CR.Range.second - CR.Range.first;
1469 // Get the MachineFunction which holds the current MBB. This is used when
1470 // inserting any additional MBBs necessary to represent the switch.
1471 MachineFunction *CurMF = CurMBB->getParent();
1473 // Figure out which block is immediately after the current one.
1474 MachineBasicBlock *NextBlock = 0;
1475 MachineFunction::iterator BBI = CR.CaseBB;
1477 if (++BBI != CurMBB->getParent()->end())
1480 // TODO: If any two of the cases has the same destination, and if one value
1481 // is the same as the other, but has one bit unset that the other has set,
1482 // use bit manipulation to do two compares at once. For example:
1483 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1485 // Rearrange the case blocks so that the last one falls through if possible.
1486 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1487 // The last case block won't fall through into 'NextBlock' if we emit the
1488 // branches in this order. See if rearranging a case value would help.
1489 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1490 if (I->BB == NextBlock) {
1491 std::swap(*I, BackCase);
1497 // Create a CaseBlock record representing a conditional branch to
1498 // the Case's target mbb if the value being switched on SV is equal
1500 MachineBasicBlock *CurBlock = CR.CaseBB;
1501 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1502 MachineBasicBlock *FallThrough;
1504 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1505 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1507 // If the last case doesn't match, go to the default block.
1508 FallThrough = Default;
1511 Value *RHS, *LHS, *MHS;
1513 if (I->High == I->Low) {
1514 // This is just small small case range :) containing exactly 1 case
1516 LHS = SV; RHS = I->High; MHS = NULL;
1519 LHS = I->Low; MHS = SV; RHS = I->High;
1521 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1522 I->BB, FallThrough, CurBlock);
1524 // If emitting the first comparison, just call visitSwitchCase to emit the
1525 // code into the current block. Otherwise, push the CaseBlock onto the
1526 // vector to be later processed by SDISel, and insert the node's MBB
1527 // before the next MBB.
1528 if (CurBlock == CurMBB)
1529 visitSwitchCase(CB);
1531 SwitchCases.push_back(CB);
1533 CurBlock = FallThrough;
1539 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1540 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1541 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1544 /// handleJTSwitchCase - Emit jumptable for current switch case range
1545 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1546 CaseRecVector& WorkList,
1548 MachineBasicBlock* Default) {
1549 Case& FrontCase = *CR.Range.first;
1550 Case& BackCase = *(CR.Range.second-1);
1552 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1553 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1556 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1560 if (!areJTsAllowed(TLI) || TSize <= 3)
1563 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1567 DOUT << "Lowering jump table\n"
1568 << "First entry: " << First << ". Last entry: " << Last << "\n"
1569 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1571 // Get the MachineFunction which holds the current MBB. This is used when
1572 // inserting any additional MBBs necessary to represent the switch.
1573 MachineFunction *CurMF = CurMBB->getParent();
1575 // Figure out which block is immediately after the current one.
1576 MachineBasicBlock *NextBlock = 0;
1577 MachineFunction::iterator BBI = CR.CaseBB;
1579 if (++BBI != CurMBB->getParent()->end())
1582 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1584 // Create a new basic block to hold the code for loading the address
1585 // of the jump table, and jumping to it. Update successor information;
1586 // we will either branch to the default case for the switch, or the jump
1588 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1589 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1590 CR.CaseBB->addSuccessor(Default);
1591 CR.CaseBB->addSuccessor(JumpTableBB);
1593 // Build a vector of destination BBs, corresponding to each target
1594 // of the jump table. If the value of the jump table slot corresponds to
1595 // a case statement, push the case's BB onto the vector, otherwise, push
1597 std::vector<MachineBasicBlock*> DestBBs;
1598 int64_t TEI = First;
1599 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1600 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1601 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1603 if ((Low <= TEI) && (TEI <= High)) {
1604 DestBBs.push_back(I->BB);
1608 DestBBs.push_back(Default);
1612 // Update successor info. Add one edge to each unique successor.
1613 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1614 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1615 E = DestBBs.end(); I != E; ++I) {
1616 if (!SuccsHandled[(*I)->getNumber()]) {
1617 SuccsHandled[(*I)->getNumber()] = true;
1618 JumpTableBB->addSuccessor(*I);
1622 // Create a jump table index for this jump table, or return an existing
1624 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1626 // Set the jump table information so that we can codegen it as a second
1627 // MachineBasicBlock
1628 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1629 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1630 (CR.CaseBB == CurMBB));
1631 if (CR.CaseBB == CurMBB)
1632 visitJumpTableHeader(JT, JTH);
1634 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1639 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1641 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1642 CaseRecVector& WorkList,
1644 MachineBasicBlock* Default) {
1645 // Get the MachineFunction which holds the current MBB. This is used when
1646 // inserting any additional MBBs necessary to represent the switch.
1647 MachineFunction *CurMF = CurMBB->getParent();
1649 // Figure out which block is immediately after the current one.
1650 MachineBasicBlock *NextBlock = 0;
1651 MachineFunction::iterator BBI = CR.CaseBB;
1653 if (++BBI != CurMBB->getParent()->end())
1656 Case& FrontCase = *CR.Range.first;
1657 Case& BackCase = *(CR.Range.second-1);
1658 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1660 // Size is the number of Cases represented by this range.
1661 unsigned Size = CR.Range.second - CR.Range.first;
1663 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1664 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1666 CaseItr Pivot = CR.Range.first + Size/2;
1668 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1669 // (heuristically) allow us to emit JumpTable's later.
1671 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1675 uint64_t LSize = FrontCase.size();
1676 uint64_t RSize = TSize-LSize;
1677 DOUT << "Selecting best pivot: \n"
1678 << "First: " << First << ", Last: " << Last <<"\n"
1679 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1680 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1682 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1683 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1684 assert((RBegin-LEnd>=1) && "Invalid case distance");
1685 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1686 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1687 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1688 // Should always split in some non-trivial place
1690 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1691 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1692 << "Metric: " << Metric << "\n";
1693 if (FMetric < Metric) {
1696 DOUT << "Current metric set to: " << FMetric << "\n";
1702 if (areJTsAllowed(TLI)) {
1703 // If our case is dense we *really* should handle it earlier!
1704 assert((FMetric > 0) && "Should handle dense range earlier!");
1706 Pivot = CR.Range.first + Size/2;
1709 CaseRange LHSR(CR.Range.first, Pivot);
1710 CaseRange RHSR(Pivot, CR.Range.second);
1711 Constant *C = Pivot->Low;
1712 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1714 // We know that we branch to the LHS if the Value being switched on is
1715 // less than the Pivot value, C. We use this to optimize our binary
1716 // tree a bit, by recognizing that if SV is greater than or equal to the
1717 // LHS's Case Value, and that Case Value is exactly one less than the
1718 // Pivot's Value, then we can branch directly to the LHS's Target,
1719 // rather than creating a leaf node for it.
1720 if ((LHSR.second - LHSR.first) == 1 &&
1721 LHSR.first->High == CR.GE &&
1722 cast<ConstantInt>(C)->getSExtValue() ==
1723 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1724 TrueBB = LHSR.first->BB;
1726 TrueBB = new MachineBasicBlock(LLVMBB);
1727 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1728 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1731 // Similar to the optimization above, if the Value being switched on is
1732 // known to be less than the Constant CR.LT, and the current Case Value
1733 // is CR.LT - 1, then we can branch directly to the target block for
1734 // the current Case Value, rather than emitting a RHS leaf node for it.
1735 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1736 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1737 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1738 FalseBB = RHSR.first->BB;
1740 FalseBB = new MachineBasicBlock(LLVMBB);
1741 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1742 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1745 // Create a CaseBlock record representing a conditional branch to
1746 // the LHS node if the value being switched on SV is less than C.
1747 // Otherwise, branch to LHS.
1748 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1749 TrueBB, FalseBB, CR.CaseBB);
1751 if (CR.CaseBB == CurMBB)
1752 visitSwitchCase(CB);
1754 SwitchCases.push_back(CB);
1759 /// handleBitTestsSwitchCase - if current case range has few destination and
1760 /// range span less, than machine word bitwidth, encode case range into series
1761 /// of masks and emit bit tests with these masks.
1762 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1763 CaseRecVector& WorkList,
1765 MachineBasicBlock* Default){
1766 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1768 Case& FrontCase = *CR.Range.first;
1769 Case& BackCase = *(CR.Range.second-1);
1771 // Get the MachineFunction which holds the current MBB. This is used when
1772 // inserting any additional MBBs necessary to represent the switch.
1773 MachineFunction *CurMF = CurMBB->getParent();
1775 unsigned numCmps = 0;
1776 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1778 // Single case counts one, case range - two.
1779 if (I->Low == I->High)
1785 // Count unique destinations
1786 SmallSet<MachineBasicBlock*, 4> Dests;
1787 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1788 Dests.insert(I->BB);
1789 if (Dests.size() > 3)
1790 // Don't bother the code below, if there are too much unique destinations
1793 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1794 << "Total number of comparisons: " << numCmps << "\n";
1796 // Compute span of values.
1797 Constant* minValue = FrontCase.Low;
1798 Constant* maxValue = BackCase.High;
1799 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1800 cast<ConstantInt>(minValue)->getSExtValue();
1801 DOUT << "Compare range: " << range << "\n"
1802 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1803 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1805 if (range>=IntPtrBits ||
1806 (!(Dests.size() == 1 && numCmps >= 3) &&
1807 !(Dests.size() == 2 && numCmps >= 5) &&
1808 !(Dests.size() >= 3 && numCmps >= 6)))
1811 DOUT << "Emitting bit tests\n";
1812 int64_t lowBound = 0;
1814 // Optimize the case where all the case values fit in a
1815 // word without having to subtract minValue. In this case,
1816 // we can optimize away the subtraction.
1817 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1818 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1819 range = cast<ConstantInt>(maxValue)->getSExtValue();
1821 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1824 CaseBitsVector CasesBits;
1825 unsigned i, count = 0;
1827 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1828 MachineBasicBlock* Dest = I->BB;
1829 for (i = 0; i < count; ++i)
1830 if (Dest == CasesBits[i].BB)
1834 assert((count < 3) && "Too much destinations to test!");
1835 CasesBits.push_back(CaseBits(0, Dest, 0));
1839 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1840 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1842 for (uint64_t j = lo; j <= hi; j++) {
1843 CasesBits[i].Mask |= 1ULL << j;
1844 CasesBits[i].Bits++;
1848 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1850 SelectionDAGISel::BitTestInfo BTC;
1852 // Figure out which block is immediately after the current one.
1853 MachineFunction::iterator BBI = CR.CaseBB;
1856 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1859 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1860 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1861 << ", BB: " << CasesBits[i].BB << "\n";
1863 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1864 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1865 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1870 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1871 -1U, (CR.CaseBB == CurMBB),
1872 CR.CaseBB, Default, BTC);
1874 if (CR.CaseBB == CurMBB)
1875 visitBitTestHeader(BTB);
1877 BitTestCases.push_back(BTB);
1883 // Clusterify - Transform simple list of Cases into list of CaseRange's
1884 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1885 const SwitchInst& SI) {
1886 unsigned numCmps = 0;
1888 // Start with "simple" cases
1889 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1890 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1891 Cases.push_back(Case(SI.getSuccessorValue(i),
1892 SI.getSuccessorValue(i),
1895 sort(Cases.begin(), Cases.end(), CaseCmp());
1897 // Merge case into clusters
1898 if (Cases.size()>=2)
1899 // Must recompute end() each iteration because it may be
1900 // invalidated by erase if we hold on to it
1901 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1902 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1903 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1904 MachineBasicBlock* nextBB = J->BB;
1905 MachineBasicBlock* currentBB = I->BB;
1907 // If the two neighboring cases go to the same destination, merge them
1908 // into a single case.
1909 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1917 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1918 if (I->Low != I->High)
1919 // A range counts double, since it requires two compares.
1926 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1927 // Figure out which block is immediately after the current one.
1928 MachineBasicBlock *NextBlock = 0;
1929 MachineFunction::iterator BBI = CurMBB;
1931 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1933 // If there is only the default destination, branch to it if it is not the
1934 // next basic block. Otherwise, just fall through.
1935 if (SI.getNumOperands() == 2) {
1936 // Update machine-CFG edges.
1938 // If this is not a fall-through branch, emit the branch.
1939 if (Default != NextBlock)
1940 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1941 DAG.getBasicBlock(Default)));
1943 CurMBB->addSuccessor(Default);
1947 // If there are any non-default case statements, create a vector of Cases
1948 // representing each one, and sort the vector so that we can efficiently
1949 // create a binary search tree from them.
1951 unsigned numCmps = Clusterify(Cases, SI);
1952 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1953 << ". Total compares: " << numCmps << "\n";
1955 // Get the Value to be switched on and default basic blocks, which will be
1956 // inserted into CaseBlock records, representing basic blocks in the binary
1958 Value *SV = SI.getOperand(0);
1960 // Push the initial CaseRec onto the worklist
1961 CaseRecVector WorkList;
1962 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1964 while (!WorkList.empty()) {
1965 // Grab a record representing a case range to process off the worklist
1966 CaseRec CR = WorkList.back();
1967 WorkList.pop_back();
1969 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1972 // If the range has few cases (two or less) emit a series of specific
1974 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1977 // If the switch has more than 5 blocks, and at least 40% dense, and the
1978 // target supports indirect branches, then emit a jump table rather than
1979 // lowering the switch to a binary tree of conditional branches.
1980 if (handleJTSwitchCase(CR, WorkList, SV, Default))
1983 // Emit binary tree. We need to pick a pivot, and push left and right ranges
1984 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
1985 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
1990 void SelectionDAGLowering::visitSub(User &I) {
1991 // -0.0 - X --> fneg
1992 const Type *Ty = I.getType();
1993 if (isa<VectorType>(Ty)) {
1994 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
1995 const VectorType *DestTy = cast<VectorType>(I.getType());
1996 const Type *ElTy = DestTy->getElementType();
1997 if (ElTy->isFloatingPoint()) {
1998 unsigned VL = DestTy->getNumElements();
1999 std::vector<Constant*> NZ(VL, ConstantFP::get(ElTy, -0.0));
2000 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2002 SDOperand Op2 = getValue(I.getOperand(1));
2003 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2009 if (Ty->isFloatingPoint()) {
2010 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2011 if (CFP->isExactlyValue(-0.0)) {
2012 SDOperand Op2 = getValue(I.getOperand(1));
2013 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2018 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2021 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2022 SDOperand Op1 = getValue(I.getOperand(0));
2023 SDOperand Op2 = getValue(I.getOperand(1));
2025 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2028 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2029 SDOperand Op1 = getValue(I.getOperand(0));
2030 SDOperand Op2 = getValue(I.getOperand(1));
2032 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2033 MVT::getSizeInBits(Op2.getValueType()))
2034 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2035 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2036 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2038 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2041 void SelectionDAGLowering::visitICmp(User &I) {
2042 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2043 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2044 predicate = IC->getPredicate();
2045 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2046 predicate = ICmpInst::Predicate(IC->getPredicate());
2047 SDOperand Op1 = getValue(I.getOperand(0));
2048 SDOperand Op2 = getValue(I.getOperand(1));
2049 ISD::CondCode Opcode;
2050 switch (predicate) {
2051 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2052 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2053 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2054 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2055 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2056 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2057 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2058 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2059 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2060 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2062 assert(!"Invalid ICmp predicate value");
2063 Opcode = ISD::SETEQ;
2066 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2069 void SelectionDAGLowering::visitFCmp(User &I) {
2070 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2071 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2072 predicate = FC->getPredicate();
2073 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2074 predicate = FCmpInst::Predicate(FC->getPredicate());
2075 SDOperand Op1 = getValue(I.getOperand(0));
2076 SDOperand Op2 = getValue(I.getOperand(1));
2077 ISD::CondCode Condition, FOC, FPC;
2078 switch (predicate) {
2079 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2080 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2081 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2082 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2083 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2084 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2085 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2086 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2087 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2088 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2089 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2090 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2091 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2092 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2093 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2094 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2096 assert(!"Invalid FCmp predicate value");
2097 FOC = FPC = ISD::SETFALSE;
2100 if (FiniteOnlyFPMath())
2104 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2107 void SelectionDAGLowering::visitSelect(User &I) {
2108 SDOperand Cond = getValue(I.getOperand(0));
2109 SDOperand TrueVal = getValue(I.getOperand(1));
2110 SDOperand FalseVal = getValue(I.getOperand(2));
2111 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2112 TrueVal, FalseVal));
2116 void SelectionDAGLowering::visitTrunc(User &I) {
2117 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2118 SDOperand N = getValue(I.getOperand(0));
2119 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2120 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2123 void SelectionDAGLowering::visitZExt(User &I) {
2124 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2125 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2126 SDOperand N = getValue(I.getOperand(0));
2127 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2128 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2131 void SelectionDAGLowering::visitSExt(User &I) {
2132 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2133 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2134 SDOperand N = getValue(I.getOperand(0));
2135 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2136 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2139 void SelectionDAGLowering::visitFPTrunc(User &I) {
2140 // FPTrunc is never a no-op cast, no need to check
2141 SDOperand N = getValue(I.getOperand(0));
2142 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2143 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
2146 void SelectionDAGLowering::visitFPExt(User &I){
2147 // FPTrunc is never a no-op cast, no need to check
2148 SDOperand N = getValue(I.getOperand(0));
2149 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2150 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2153 void SelectionDAGLowering::visitFPToUI(User &I) {
2154 // FPToUI is never a no-op cast, no need to check
2155 SDOperand N = getValue(I.getOperand(0));
2156 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2157 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2160 void SelectionDAGLowering::visitFPToSI(User &I) {
2161 // FPToSI is never a no-op cast, no need to check
2162 SDOperand N = getValue(I.getOperand(0));
2163 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2164 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2167 void SelectionDAGLowering::visitUIToFP(User &I) {
2168 // UIToFP is never a no-op cast, no need to check
2169 SDOperand N = getValue(I.getOperand(0));
2170 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2171 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2174 void SelectionDAGLowering::visitSIToFP(User &I){
2175 // UIToFP is never a no-op cast, no need to check
2176 SDOperand N = getValue(I.getOperand(0));
2177 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2178 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2181 void SelectionDAGLowering::visitPtrToInt(User &I) {
2182 // What to do depends on the size of the integer and the size of the pointer.
2183 // We can either truncate, zero extend, or no-op, accordingly.
2184 SDOperand N = getValue(I.getOperand(0));
2185 MVT::ValueType SrcVT = N.getValueType();
2186 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2188 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2189 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2191 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2192 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2193 setValue(&I, Result);
2196 void SelectionDAGLowering::visitIntToPtr(User &I) {
2197 // What to do depends on the size of the integer and the size of the pointer.
2198 // We can either truncate, zero extend, or no-op, accordingly.
2199 SDOperand N = getValue(I.getOperand(0));
2200 MVT::ValueType SrcVT = N.getValueType();
2201 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2202 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2203 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2205 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2206 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2209 void SelectionDAGLowering::visitBitCast(User &I) {
2210 SDOperand N = getValue(I.getOperand(0));
2211 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2213 // BitCast assures us that source and destination are the same size so this
2214 // is either a BIT_CONVERT or a no-op.
2215 if (DestVT != N.getValueType())
2216 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2218 setValue(&I, N); // noop cast.
2221 void SelectionDAGLowering::visitInsertElement(User &I) {
2222 SDOperand InVec = getValue(I.getOperand(0));
2223 SDOperand InVal = getValue(I.getOperand(1));
2224 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2225 getValue(I.getOperand(2)));
2227 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2228 TLI.getValueType(I.getType()),
2229 InVec, InVal, InIdx));
2232 void SelectionDAGLowering::visitExtractElement(User &I) {
2233 SDOperand InVec = getValue(I.getOperand(0));
2234 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2235 getValue(I.getOperand(1)));
2236 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2237 TLI.getValueType(I.getType()), InVec, InIdx));
2240 void SelectionDAGLowering::visitShuffleVector(User &I) {
2241 SDOperand V1 = getValue(I.getOperand(0));
2242 SDOperand V2 = getValue(I.getOperand(1));
2243 SDOperand Mask = getValue(I.getOperand(2));
2245 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2246 TLI.getValueType(I.getType()),
2251 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2252 SDOperand N = getValue(I.getOperand(0));
2253 const Type *Ty = I.getOperand(0)->getType();
2255 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2258 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2259 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2262 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2263 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2264 getIntPtrConstant(Offset));
2266 Ty = StTy->getElementType(Field);
2268 Ty = cast<SequentialType>(Ty)->getElementType();
2270 // If this is a constant subscript, handle it quickly.
2271 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2272 if (CI->getZExtValue() == 0) continue;
2274 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2275 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
2279 // N = N + Idx * ElementSize;
2280 uint64_t ElementSize = TD->getTypeSize(Ty);
2281 SDOperand IdxN = getValue(Idx);
2283 // If the index is smaller or larger than intptr_t, truncate or extend
2285 if (IdxN.getValueType() < N.getValueType()) {
2286 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2287 } else if (IdxN.getValueType() > N.getValueType())
2288 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2290 // If this is a multiply by a power of two, turn it into a shl
2291 // immediately. This is a very common case.
2292 if (isPowerOf2_64(ElementSize)) {
2293 unsigned Amt = Log2_64(ElementSize);
2294 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2295 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2296 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2300 SDOperand Scale = getIntPtrConstant(ElementSize);
2301 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2302 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2308 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2309 // If this is a fixed sized alloca in the entry block of the function,
2310 // allocate it statically on the stack.
2311 if (FuncInfo.StaticAllocaMap.count(&I))
2312 return; // getValue will auto-populate this.
2314 const Type *Ty = I.getAllocatedType();
2315 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
2317 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2320 SDOperand AllocSize = getValue(I.getArraySize());
2321 MVT::ValueType IntPtr = TLI.getPointerTy();
2322 if (IntPtr < AllocSize.getValueType())
2323 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2324 else if (IntPtr > AllocSize.getValueType())
2325 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2327 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2328 getIntPtrConstant(TySize));
2330 // Handle alignment. If the requested alignment is less than or equal to the
2331 // stack alignment, ignore it and round the size of the allocation up to the
2332 // stack alignment size. If the size is greater than the stack alignment, we
2333 // note this in the DYNAMIC_STACKALLOC node.
2334 unsigned StackAlign =
2335 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2336 if (Align <= StackAlign) {
2338 // Add SA-1 to the size.
2339 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2340 getIntPtrConstant(StackAlign-1));
2341 // Mask out the low bits for alignment purposes.
2342 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2343 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2346 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
2347 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2349 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2351 DAG.setRoot(DSA.getValue(1));
2353 // Inform the Frame Information that we have just allocated a variable-sized
2355 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2358 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2359 SDOperand Ptr = getValue(I.getOperand(0));
2365 // Do not serialize non-volatile loads against each other.
2366 Root = DAG.getRoot();
2369 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2370 Root, I.isVolatile(), I.getAlignment()));
2373 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2374 const Value *SV, SDOperand Root,
2376 unsigned Alignment) {
2378 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2379 isVolatile, Alignment);
2382 DAG.setRoot(L.getValue(1));
2384 PendingLoads.push_back(L.getValue(1));
2390 void SelectionDAGLowering::visitStore(StoreInst &I) {
2391 Value *SrcV = I.getOperand(0);
2392 SDOperand Src = getValue(SrcV);
2393 SDOperand Ptr = getValue(I.getOperand(1));
2394 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2395 I.isVolatile(), I.getAlignment()));
2398 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
2399 /// access memory and has no other side effects at all.
2400 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
2401 #define GET_NO_MEMORY_INTRINSICS
2402 #include "llvm/Intrinsics.gen"
2403 #undef GET_NO_MEMORY_INTRINSICS
2407 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
2408 // have any side-effects or if it only reads memory.
2409 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
2410 #define GET_SIDE_EFFECT_INFO
2411 #include "llvm/Intrinsics.gen"
2412 #undef GET_SIDE_EFFECT_INFO
2416 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2418 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2419 unsigned Intrinsic) {
2420 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
2421 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
2423 // Build the operand list.
2424 SmallVector<SDOperand, 8> Ops;
2425 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2427 // We don't need to serialize loads against other loads.
2428 Ops.push_back(DAG.getRoot());
2430 Ops.push_back(getRoot());
2434 // Add the intrinsic ID as an integer operand.
2435 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2437 // Add all operands of the call to the operand list.
2438 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2439 SDOperand Op = getValue(I.getOperand(i));
2440 assert(TLI.isTypeLegal(Op.getValueType()) &&
2441 "Intrinsic uses a non-legal type?");
2445 std::vector<MVT::ValueType> VTs;
2446 if (I.getType() != Type::VoidTy) {
2447 MVT::ValueType VT = TLI.getValueType(I.getType());
2448 if (MVT::isVector(VT)) {
2449 const VectorType *DestTy = cast<VectorType>(I.getType());
2450 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2452 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2453 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2456 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2460 VTs.push_back(MVT::Other);
2462 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2467 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2468 &Ops[0], Ops.size());
2469 else if (I.getType() != Type::VoidTy)
2470 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2471 &Ops[0], Ops.size());
2473 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2474 &Ops[0], Ops.size());
2477 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2479 PendingLoads.push_back(Chain);
2483 if (I.getType() != Type::VoidTy) {
2484 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2485 MVT::ValueType VT = TLI.getValueType(PTy);
2486 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2488 setValue(&I, Result);
2492 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2493 static GlobalVariable *ExtractTypeInfo (Value *V) {
2494 V = IntrinsicInst::StripPointerCasts(V);
2495 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2496 assert (GV || isa<ConstantPointerNull>(V) &&
2497 "TypeInfo must be a global variable or NULL");
2501 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2502 /// call, and add them to the specified machine basic block.
2503 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2504 MachineBasicBlock *MBB) {
2505 // Inform the MachineModuleInfo of the personality for this landing pad.
2506 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2507 assert(CE->getOpcode() == Instruction::BitCast &&
2508 isa<Function>(CE->getOperand(0)) &&
2509 "Personality should be a function");
2510 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2512 // Gather all the type infos for this landing pad and pass them along to
2513 // MachineModuleInfo.
2514 std::vector<GlobalVariable *> TyInfo;
2515 unsigned N = I.getNumOperands();
2517 for (unsigned i = N - 1; i > 2; --i) {
2518 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2519 unsigned FilterLength = CI->getZExtValue();
2520 unsigned FirstCatch = i + FilterLength + 1;
2521 assert (FirstCatch <= N && "Invalid filter length");
2523 if (FirstCatch < N) {
2524 TyInfo.reserve(N - FirstCatch);
2525 for (unsigned j = FirstCatch; j < N; ++j)
2526 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2527 MMI->addCatchTypeInfo(MBB, TyInfo);
2531 TyInfo.reserve(FilterLength);
2532 for (unsigned j = i + 1; j < FirstCatch; ++j)
2533 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2534 MMI->addFilterTypeInfo(MBB, TyInfo);
2542 TyInfo.reserve(N - 3);
2543 for (unsigned j = 3; j < N; ++j)
2544 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2545 MMI->addCatchTypeInfo(MBB, TyInfo);
2549 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2550 /// we want to emit this as a call to a named external function, return the name
2551 /// otherwise lower it and return null.
2553 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2554 switch (Intrinsic) {
2556 // By default, turn this into a target intrinsic node.
2557 visitTargetIntrinsic(I, Intrinsic);
2559 case Intrinsic::vastart: visitVAStart(I); return 0;
2560 case Intrinsic::vaend: visitVAEnd(I); return 0;
2561 case Intrinsic::vacopy: visitVACopy(I); return 0;
2562 case Intrinsic::returnaddress:
2563 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2564 getValue(I.getOperand(1))));
2566 case Intrinsic::frameaddress:
2567 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2568 getValue(I.getOperand(1))));
2570 case Intrinsic::setjmp:
2571 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2573 case Intrinsic::longjmp:
2574 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2576 case Intrinsic::memcpy_i32:
2577 case Intrinsic::memcpy_i64:
2578 visitMemIntrinsic(I, ISD::MEMCPY);
2580 case Intrinsic::memset_i32:
2581 case Intrinsic::memset_i64:
2582 visitMemIntrinsic(I, ISD::MEMSET);
2584 case Intrinsic::memmove_i32:
2585 case Intrinsic::memmove_i64:
2586 visitMemIntrinsic(I, ISD::MEMMOVE);
2589 case Intrinsic::dbg_stoppoint: {
2590 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2591 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2592 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2596 Ops[1] = getValue(SPI.getLineValue());
2597 Ops[2] = getValue(SPI.getColumnValue());
2599 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2600 assert(DD && "Not a debug information descriptor");
2601 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2603 Ops[3] = DAG.getString(CompileUnit->getFileName());
2604 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2606 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2611 case Intrinsic::dbg_region_start: {
2612 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2613 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2614 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2615 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2616 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2617 DAG.getConstant(LabelID, MVT::i32)));
2622 case Intrinsic::dbg_region_end: {
2623 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2624 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2625 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2626 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2627 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2628 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2633 case Intrinsic::dbg_func_start: {
2634 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2635 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2636 if (MMI && FSI.getSubprogram() &&
2637 MMI->Verify(FSI.getSubprogram())) {
2638 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
2639 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2640 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2645 case Intrinsic::dbg_declare: {
2646 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2647 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2648 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
2649 SDOperand AddressOp = getValue(DI.getAddress());
2650 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2651 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
2657 case Intrinsic::eh_exception: {
2658 if (ExceptionHandling) {
2659 if (!CurMBB->isLandingPad()) {
2660 // FIXME: Mark exception register as live in. Hack for PR1508.
2661 unsigned Reg = TLI.getExceptionAddressRegister();
2662 if (Reg) CurMBB->addLiveIn(Reg);
2664 // Insert the EXCEPTIONADDR instruction.
2665 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2667 Ops[0] = DAG.getRoot();
2668 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2670 DAG.setRoot(Op.getValue(1));
2672 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2677 case Intrinsic::eh_selector:{
2678 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2680 if (ExceptionHandling && MMI) {
2681 if (CurMBB->isLandingPad())
2682 addCatchInfo(I, MMI, CurMBB);
2685 FuncInfo.CatchInfoLost.insert(&I);
2687 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2688 unsigned Reg = TLI.getExceptionSelectorRegister();
2689 if (Reg) CurMBB->addLiveIn(Reg);
2692 // Insert the EHSELECTION instruction.
2693 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2695 Ops[0] = getValue(I.getOperand(1));
2697 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2699 DAG.setRoot(Op.getValue(1));
2701 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2707 case Intrinsic::eh_typeid_for: {
2708 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2711 // Find the type id for the given typeinfo.
2712 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2714 unsigned TypeID = MMI->getTypeIDFor(GV);
2715 setValue(&I, DAG.getConstant(TypeID, MVT::i32));
2717 // Return something different to eh_selector.
2718 setValue(&I, DAG.getConstant(1, MVT::i32));
2724 case Intrinsic::eh_return: {
2725 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2727 if (MMI && ExceptionHandling) {
2728 MMI->setCallsEHReturn(true);
2729 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2732 getValue(I.getOperand(1)),
2733 getValue(I.getOperand(2))));
2735 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2741 case Intrinsic::eh_unwind_init: {
2742 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2743 MMI->setCallsUnwindInit(true);
2749 case Intrinsic::eh_dwarf_cfa: {
2750 if (ExceptionHandling) {
2751 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2752 SDOperand Offset = DAG.getNode(ISD::ADD,
2754 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2756 getValue(I.getOperand(1)));
2757 setValue(&I, DAG.getNode(ISD::ADD,
2759 DAG.getNode(ISD::FRAMEADDR,
2762 TLI.getPointerTy())),
2765 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2771 case Intrinsic::sqrt_f32:
2772 case Intrinsic::sqrt_f64:
2773 setValue(&I, DAG.getNode(ISD::FSQRT,
2774 getValue(I.getOperand(1)).getValueType(),
2775 getValue(I.getOperand(1))));
2777 case Intrinsic::powi_f32:
2778 case Intrinsic::powi_f64:
2779 setValue(&I, DAG.getNode(ISD::FPOWI,
2780 getValue(I.getOperand(1)).getValueType(),
2781 getValue(I.getOperand(1)),
2782 getValue(I.getOperand(2))));
2784 case Intrinsic::pcmarker: {
2785 SDOperand Tmp = getValue(I.getOperand(1));
2786 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2789 case Intrinsic::readcyclecounter: {
2790 SDOperand Op = getRoot();
2791 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2792 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2795 DAG.setRoot(Tmp.getValue(1));
2798 case Intrinsic::part_select: {
2799 // Currently not implemented: just abort
2800 assert(0 && "part_select intrinsic not implemented");
2803 case Intrinsic::part_set: {
2804 // Currently not implemented: just abort
2805 assert(0 && "part_set intrinsic not implemented");
2808 case Intrinsic::bswap:
2809 setValue(&I, DAG.getNode(ISD::BSWAP,
2810 getValue(I.getOperand(1)).getValueType(),
2811 getValue(I.getOperand(1))));
2813 case Intrinsic::cttz: {
2814 SDOperand Arg = getValue(I.getOperand(1));
2815 MVT::ValueType Ty = Arg.getValueType();
2816 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2818 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
2819 else if (Ty > MVT::i32)
2820 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
2821 setValue(&I, result);
2824 case Intrinsic::ctlz: {
2825 SDOperand Arg = getValue(I.getOperand(1));
2826 MVT::ValueType Ty = Arg.getValueType();
2827 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2829 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
2830 else if (Ty > MVT::i32)
2831 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
2832 setValue(&I, result);
2835 case Intrinsic::ctpop: {
2836 SDOperand Arg = getValue(I.getOperand(1));
2837 MVT::ValueType Ty = Arg.getValueType();
2838 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2840 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
2841 else if (Ty > MVT::i32)
2842 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
2843 setValue(&I, result);
2846 case Intrinsic::stacksave: {
2847 SDOperand Op = getRoot();
2848 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2849 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2851 DAG.setRoot(Tmp.getValue(1));
2854 case Intrinsic::stackrestore: {
2855 SDOperand Tmp = getValue(I.getOperand(1));
2856 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2859 case Intrinsic::prefetch:
2860 // FIXME: Currently discarding prefetches.
2863 case Intrinsic::var_annotation:
2864 // Discard annotate attributes
2870 void SelectionDAGLowering::LowerCallTo(Instruction &I,
2871 const Type *CalledValueTy,
2872 unsigned CallingConv,
2874 SDOperand Callee, unsigned OpIdx,
2875 MachineBasicBlock *LandingPad) {
2876 const PointerType *PT = cast<PointerType>(CalledValueTy);
2877 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2878 const ParamAttrsList *Attrs = FTy->getParamAttrs();
2879 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2880 unsigned BeginLabel = 0, EndLabel = 0;
2882 TargetLowering::ArgListTy Args;
2883 TargetLowering::ArgListEntry Entry;
2884 Args.reserve(I.getNumOperands());
2885 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) {
2886 Value *Arg = I.getOperand(i);
2887 SDOperand ArgNode = getValue(Arg);
2888 Entry.Node = ArgNode; Entry.Ty = Arg->getType();
2890 unsigned attrInd = i - OpIdx + 1;
2891 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt);
2892 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt);
2893 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg);
2894 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet);
2895 Args.push_back(Entry);
2898 if (ExceptionHandling && MMI) {
2899 // Insert a label before the invoke call to mark the try range. This can be
2900 // used to detect deletion of the invoke via the MachineModuleInfo.
2901 BeginLabel = MMI->NextLabelID();
2902 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2903 DAG.getConstant(BeginLabel, MVT::i32)));
2906 std::pair<SDOperand,SDOperand> Result =
2907 TLI.LowerCallTo(getRoot(), I.getType(),
2908 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt),
2909 FTy->isVarArg(), CallingConv, IsTailCall,
2911 if (I.getType() != Type::VoidTy)
2912 setValue(&I, Result.first);
2913 DAG.setRoot(Result.second);
2915 if (ExceptionHandling && MMI) {
2916 // Insert a label at the end of the invoke call to mark the try range. This
2917 // can be used to detect deletion of the invoke via the MachineModuleInfo.
2918 EndLabel = MMI->NextLabelID();
2919 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2920 DAG.getConstant(EndLabel, MVT::i32)));
2922 // Inform MachineModuleInfo of range.
2923 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
2928 void SelectionDAGLowering::visitCall(CallInst &I) {
2929 const char *RenameFn = 0;
2930 if (Function *F = I.getCalledFunction()) {
2931 if (F->isDeclaration())
2932 if (unsigned IID = F->getIntrinsicID()) {
2933 RenameFn = visitIntrinsicCall(I, IID);
2936 } else { // Not an LLVM intrinsic.
2937 const std::string &Name = F->getName();
2938 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
2939 if (I.getNumOperands() == 3 && // Basic sanity checks.
2940 I.getOperand(1)->getType()->isFloatingPoint() &&
2941 I.getType() == I.getOperand(1)->getType() &&
2942 I.getType() == I.getOperand(2)->getType()) {
2943 SDOperand LHS = getValue(I.getOperand(1));
2944 SDOperand RHS = getValue(I.getOperand(2));
2945 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
2949 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
2950 if (I.getNumOperands() == 2 && // Basic sanity checks.
2951 I.getOperand(1)->getType()->isFloatingPoint() &&
2952 I.getType() == I.getOperand(1)->getType()) {
2953 SDOperand Tmp = getValue(I.getOperand(1));
2954 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
2957 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
2958 if (I.getNumOperands() == 2 && // Basic sanity checks.
2959 I.getOperand(1)->getType()->isFloatingPoint() &&
2960 I.getType() == I.getOperand(1)->getType()) {
2961 SDOperand Tmp = getValue(I.getOperand(1));
2962 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
2965 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
2966 if (I.getNumOperands() == 2 && // Basic sanity checks.
2967 I.getOperand(1)->getType()->isFloatingPoint() &&
2968 I.getType() == I.getOperand(1)->getType()) {
2969 SDOperand Tmp = getValue(I.getOperand(1));
2970 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
2975 } else if (isa<InlineAsm>(I.getOperand(0))) {
2982 Callee = getValue(I.getOperand(0));
2984 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
2986 LowerCallTo(I, I.getCalledValue()->getType(),
2994 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
2995 /// this value and returns the result as a ValueVT value. This uses
2996 /// Chain/Flag as the input and updates them for the output Chain/Flag.
2997 /// If the Flag pointer is NULL, no flag is used.
2998 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
2999 SDOperand &Chain, SDOperand *Flag)const{
3000 // Copy the legal parts from the registers.
3001 unsigned NumParts = Regs.size();
3002 SmallVector<SDOperand, 8> Parts(NumParts);
3003 for (unsigned i = 0; i != NumParts; ++i) {
3004 SDOperand Part = Flag ?
3005 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3006 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3007 Chain = Part.getValue(1);
3009 *Flag = Part.getValue(2);
3013 // Assemble the legal parts into the final value.
3014 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3017 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3018 /// specified value into the registers specified by this object. This uses
3019 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3020 /// If the Flag pointer is NULL, no flag is used.
3021 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3022 SDOperand &Chain, SDOperand *Flag) const {
3023 // Get the list of the values's legal parts.
3024 unsigned NumParts = Regs.size();
3025 SmallVector<SDOperand, 8> Parts(NumParts);
3026 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3028 // Copy the parts into the registers.
3029 for (unsigned i = 0; i != NumParts; ++i) {
3030 SDOperand Part = Flag ?
3031 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3032 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3033 Chain = Part.getValue(0);
3035 *Flag = Part.getValue(1);
3039 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3040 /// operand list. This adds the code marker and includes the number of
3041 /// values added into it.
3042 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3043 std::vector<SDOperand> &Ops) const {
3044 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3045 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3046 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3047 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3050 /// isAllocatableRegister - If the specified register is safe to allocate,
3051 /// i.e. it isn't a stack pointer or some other special register, return the
3052 /// register class for the register. Otherwise, return null.
3053 static const TargetRegisterClass *
3054 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3055 const TargetLowering &TLI, const MRegisterInfo *MRI) {
3056 MVT::ValueType FoundVT = MVT::Other;
3057 const TargetRegisterClass *FoundRC = 0;
3058 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
3059 E = MRI->regclass_end(); RCI != E; ++RCI) {
3060 MVT::ValueType ThisVT = MVT::Other;
3062 const TargetRegisterClass *RC = *RCI;
3063 // If none of the the value types for this register class are valid, we
3064 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3065 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3067 if (TLI.isTypeLegal(*I)) {
3068 // If we have already found this register in a different register class,
3069 // choose the one with the largest VT specified. For example, on
3070 // PowerPC, we favor f64 register classes over f32.
3071 if (FoundVT == MVT::Other ||
3072 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3079 if (ThisVT == MVT::Other) continue;
3081 // NOTE: This isn't ideal. In particular, this might allocate the
3082 // frame pointer in functions that need it (due to them not being taken
3083 // out of allocation, because a variable sized allocation hasn't been seen
3084 // yet). This is a slight code pessimization, but should still work.
3085 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3086 E = RC->allocation_order_end(MF); I != E; ++I)
3088 // We found a matching register class. Keep looking at others in case
3089 // we find one with larger registers that this physreg is also in.
3100 /// AsmOperandInfo - This contains information for each constraint that we are
3102 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3103 /// ConstraintCode - This contains the actual string for the code, like "m".
3104 std::string ConstraintCode;
3106 /// ConstraintType - Information about the constraint code, e.g. Register,
3107 /// RegisterClass, Memory, Other, Unknown.
3108 TargetLowering::ConstraintType ConstraintType;
3110 /// CallOperand/CallOperandval - If this is the result output operand or a
3111 /// clobber, this is null, otherwise it is the incoming operand to the
3112 /// CallInst. This gets modified as the asm is processed.
3113 SDOperand CallOperand;
3114 Value *CallOperandVal;
3116 /// ConstraintVT - The ValueType for the operand value.
3117 MVT::ValueType ConstraintVT;
3119 /// AssignedRegs - If this is a register or register class operand, this
3120 /// contains the set of register corresponding to the operand.
3121 RegsForValue AssignedRegs;
3123 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3124 : InlineAsm::ConstraintInfo(info),
3125 ConstraintType(TargetLowering::C_Unknown),
3126 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3129 void ComputeConstraintToUse(const TargetLowering &TLI);
3131 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3132 /// busy in OutputRegs/InputRegs.
3133 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3134 std::set<unsigned> &OutputRegs,
3135 std::set<unsigned> &InputRegs) const {
3137 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3139 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3142 } // end anon namespace.
3144 /// getConstraintGenerality - Return an integer indicating how general CT is.
3145 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3147 default: assert(0 && "Unknown constraint type!");
3148 case TargetLowering::C_Other:
3149 case TargetLowering::C_Unknown:
3151 case TargetLowering::C_Register:
3153 case TargetLowering::C_RegisterClass:
3155 case TargetLowering::C_Memory:
3160 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3161 assert(!Codes.empty() && "Must have at least one constraint");
3163 std::string *Current = &Codes[0];
3164 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3165 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3166 ConstraintCode = *Current;
3167 ConstraintType = CurType;
3171 unsigned CurGenerality = getConstraintGenerality(CurType);
3173 // If we have multiple constraints, try to pick the most general one ahead
3174 // of time. This isn't a wonderful solution, but handles common cases.
3175 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3176 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3177 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3178 if (ThisGenerality > CurGenerality) {
3179 // This constraint letter is more general than the previous one,
3182 Current = &Codes[j];
3183 CurGenerality = ThisGenerality;
3187 ConstraintCode = *Current;
3188 ConstraintType = CurType;
3192 void SelectionDAGLowering::
3193 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3194 std::set<unsigned> &OutputRegs,
3195 std::set<unsigned> &InputRegs) {
3196 // Compute whether this value requires an input register, an output register,
3198 bool isOutReg = false;
3199 bool isInReg = false;
3200 switch (OpInfo.Type) {
3201 case InlineAsm::isOutput:
3204 // If this is an early-clobber output, or if there is an input
3205 // constraint that matches this, we need to reserve the input register
3206 // so no other inputs allocate to it.
3207 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3209 case InlineAsm::isInput:
3213 case InlineAsm::isClobber:
3220 MachineFunction &MF = DAG.getMachineFunction();
3221 std::vector<unsigned> Regs;
3223 // If this is a constraint for a single physreg, or a constraint for a
3224 // register class, find it.
3225 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3226 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3227 OpInfo.ConstraintVT);
3229 unsigned NumRegs = 1;
3230 if (OpInfo.ConstraintVT != MVT::Other)
3231 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3232 MVT::ValueType RegVT;
3233 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3236 // If this is a constraint for a specific physical register, like {r17},
3238 if (PhysReg.first) {
3239 if (OpInfo.ConstraintVT == MVT::Other)
3240 ValueVT = *PhysReg.second->vt_begin();
3242 // Get the actual register value type. This is important, because the user
3243 // may have asked for (e.g.) the AX register in i32 type. We need to
3244 // remember that AX is actually i16 to get the right extension.
3245 RegVT = *PhysReg.second->vt_begin();
3247 // This is a explicit reference to a physical register.
3248 Regs.push_back(PhysReg.first);
3250 // If this is an expanded reference, add the rest of the regs to Regs.
3252 TargetRegisterClass::iterator I = PhysReg.second->begin();
3253 TargetRegisterClass::iterator E = PhysReg.second->end();
3254 for (; *I != PhysReg.first; ++I)
3255 assert(I != E && "Didn't find reg!");
3257 // Already added the first reg.
3259 for (; NumRegs; --NumRegs, ++I) {
3260 assert(I != E && "Ran out of registers to allocate!");
3264 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3265 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3269 // Otherwise, if this was a reference to an LLVM register class, create vregs
3270 // for this reference.
3271 std::vector<unsigned> RegClassRegs;
3272 const TargetRegisterClass *RC = PhysReg.second;
3274 // If this is an early clobber or tied register, our regalloc doesn't know
3275 // how to maintain the constraint. If it isn't, go ahead and create vreg
3276 // and let the regalloc do the right thing.
3277 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3278 // If there is some other early clobber and this is an input register,
3279 // then we are forced to pre-allocate the input reg so it doesn't
3280 // conflict with the earlyclobber.
3281 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3282 RegVT = *PhysReg.second->vt_begin();
3284 if (OpInfo.ConstraintVT == MVT::Other)
3287 // Create the appropriate number of virtual registers.
3288 SSARegMap *RegMap = MF.getSSARegMap();
3289 for (; NumRegs; --NumRegs)
3290 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
3292 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3293 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3297 // Otherwise, we can't allocate it. Let the code below figure out how to
3298 // maintain these constraints.
3299 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3302 // This is a reference to a register class that doesn't directly correspond
3303 // to an LLVM register class. Allocate NumRegs consecutive, available,
3304 // registers from the class.
3305 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3306 OpInfo.ConstraintVT);
3309 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3310 unsigned NumAllocated = 0;
3311 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3312 unsigned Reg = RegClassRegs[i];
3313 // See if this register is available.
3314 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3315 (isInReg && InputRegs.count(Reg))) { // Already used.
3316 // Make sure we find consecutive registers.
3321 // Check to see if this register is allocatable (i.e. don't give out the
3324 RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3325 if (!RC) { // Couldn't allocate this register.
3326 // Reset NumAllocated to make sure we return consecutive registers.
3332 // Okay, this register is good, we can use it.
3335 // If we allocated enough consecutive registers, succeed.
3336 if (NumAllocated == NumRegs) {
3337 unsigned RegStart = (i-NumAllocated)+1;
3338 unsigned RegEnd = i+1;
3339 // Mark all of the allocated registers used.
3340 for (unsigned i = RegStart; i != RegEnd; ++i)
3341 Regs.push_back(RegClassRegs[i]);
3343 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3344 OpInfo.ConstraintVT);
3345 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3350 // Otherwise, we couldn't allocate enough registers for this.
3355 /// visitInlineAsm - Handle a call to an InlineAsm object.
3357 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
3358 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
3360 /// ConstraintOperands - Information about all of the constraints.
3361 std::vector<AsmOperandInfo> ConstraintOperands;
3363 SDOperand Chain = getRoot();
3366 std::set<unsigned> OutputRegs, InputRegs;
3368 // Do a prepass over the constraints, canonicalizing them, and building up the
3369 // ConstraintOperands list.
3370 std::vector<InlineAsm::ConstraintInfo>
3371 ConstraintInfos = IA->ParseConstraints();
3373 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3374 // constraint. If so, we can't let the register allocator allocate any input
3375 // registers, because it will not know to avoid the earlyclobbered output reg.
3376 bool SawEarlyClobber = false;
3378 unsigned OpNo = 1; // OpNo - The operand of the CallInst.
3379 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3380 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3381 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3383 MVT::ValueType OpVT = MVT::Other;
3385 // Compute the value type for each operand.
3386 switch (OpInfo.Type) {
3387 case InlineAsm::isOutput:
3388 if (!OpInfo.isIndirect) {
3389 // The return value of the call is this value. As such, there is no
3390 // corresponding argument.
3391 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
3392 OpVT = TLI.getValueType(I.getType());
3394 OpInfo.CallOperandVal = I.getOperand(OpNo++);
3397 case InlineAsm::isInput:
3398 OpInfo.CallOperandVal = I.getOperand(OpNo++);
3400 case InlineAsm::isClobber:
3405 // If this is an input or an indirect output, process the call argument.
3406 if (OpInfo.CallOperandVal) {
3407 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3408 const Type *OpTy = OpInfo.CallOperandVal->getType();
3409 // If this is an indirect operand, the operand is a pointer to the
3411 if (OpInfo.isIndirect)
3412 OpTy = cast<PointerType>(OpTy)->getElementType();
3414 // If OpTy is not a first-class value, it may be a struct/union that we
3415 // can tile with integers.
3416 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3417 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3425 OpTy = IntegerType::get(BitSize);
3430 OpVT = TLI.getValueType(OpTy, true);
3433 OpInfo.ConstraintVT = OpVT;
3435 // Compute the constraint code and ConstraintType to use.
3436 OpInfo.ComputeConstraintToUse(TLI);
3438 // Keep track of whether we see an earlyclobber.
3439 SawEarlyClobber |= OpInfo.isEarlyClobber;
3441 // If this is a memory input, and if the operand is not indirect, do what we
3442 // need to to provide an address for the memory input.
3443 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3444 !OpInfo.isIndirect) {
3445 assert(OpInfo.Type == InlineAsm::isInput &&
3446 "Can only indirectify direct input operands!");
3448 // Memory operands really want the address of the value. If we don't have
3449 // an indirect input, put it in the constpool if we can, otherwise spill
3450 // it to a stack slot.
3452 // If the operand is a float, integer, or vector constant, spill to a
3453 // constant pool entry to get its address.
3454 Value *OpVal = OpInfo.CallOperandVal;
3455 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3456 isa<ConstantVector>(OpVal)) {
3457 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3458 TLI.getPointerTy());
3460 // Otherwise, create a stack slot and emit a store to it before the
3462 const Type *Ty = OpVal->getType();
3463 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3464 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3465 MachineFunction &MF = DAG.getMachineFunction();
3466 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3467 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3468 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3469 OpInfo.CallOperand = StackSlot;
3472 // There is no longer a Value* corresponding to this operand.
3473 OpInfo.CallOperandVal = 0;
3474 // It is now an indirect operand.
3475 OpInfo.isIndirect = true;
3478 // If this constraint is for a specific register, allocate it before
3480 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3481 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3483 ConstraintInfos.clear();
3486 // Second pass - Loop over all of the operands, assigning virtual or physregs
3487 // to registerclass operands.
3488 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3489 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3491 // C_Register operands have already been allocated, Other/Memory don't need
3493 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3494 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3497 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3498 std::vector<SDOperand> AsmNodeOperands;
3499 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3500 AsmNodeOperands.push_back(
3501 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3504 // Loop over all of the inputs, copying the operand values into the
3505 // appropriate registers and processing the output regs.
3506 RegsForValue RetValRegs;
3508 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3509 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3511 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3512 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3514 switch (OpInfo.Type) {
3515 case InlineAsm::isOutput: {
3516 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3517 OpInfo.ConstraintType != TargetLowering::C_Register) {
3518 // Memory output, or 'other' output (e.g. 'X' constraint).
3519 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3521 // Add information to the INLINEASM node to know about this output.
3522 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3523 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3524 TLI.getPointerTy()));
3525 AsmNodeOperands.push_back(OpInfo.CallOperand);
3529 // Otherwise, this is a register or register class output.
3531 // Copy the output from the appropriate register. Find a register that
3533 if (OpInfo.AssignedRegs.Regs.empty()) {
3534 cerr << "Couldn't allocate output reg for contraint '"
3535 << OpInfo.ConstraintCode << "'!\n";
3539 if (!OpInfo.isIndirect) {
3540 // This is the result value of the call.
3541 assert(RetValRegs.Regs.empty() &&
3542 "Cannot have multiple output constraints yet!");
3543 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
3544 RetValRegs = OpInfo.AssignedRegs;
3546 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3547 OpInfo.CallOperandVal));
3550 // Add information to the INLINEASM node to know that this register is
3552 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3556 case InlineAsm::isInput: {
3557 SDOperand InOperandVal = OpInfo.CallOperand;
3559 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3560 // If this is required to match an output register we have already set,
3561 // just use its register.
3562 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3564 // Scan until we find the definition we already emitted of this operand.
3565 // When we find it, create a RegsForValue operand.
3566 unsigned CurOp = 2; // The first operand.
3567 for (; OperandNo; --OperandNo) {
3568 // Advance to the next operand.
3570 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3571 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3572 (NumOps & 7) == 4 /*MEM*/) &&
3573 "Skipped past definitions?");
3574 CurOp += (NumOps>>3)+1;
3578 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3579 if ((NumOps & 7) == 2 /*REGDEF*/) {
3580 // Add NumOps>>3 registers to MatchedRegs.
3581 RegsForValue MatchedRegs;
3582 MatchedRegs.ValueVT = InOperandVal.getValueType();
3583 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3584 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3586 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3587 MatchedRegs.Regs.push_back(Reg);
3590 // Use the produced MatchedRegs object to
3591 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3592 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3595 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3596 assert(0 && "matching constraints for memory operands unimp");
3600 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3601 assert(!OpInfo.isIndirect &&
3602 "Don't know how to handle indirect other inputs yet!");
3604 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
3605 OpInfo.ConstraintCode[0],
3607 if (!InOperandVal.Val) {
3608 cerr << "Invalid operand for inline asm constraint '"
3609 << OpInfo.ConstraintCode << "'!\n";
3613 // Add information to the INLINEASM node to know about this input.
3614 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
3615 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3616 TLI.getPointerTy()));
3617 AsmNodeOperands.push_back(InOperandVal);
3619 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3620 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3621 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3622 "Memory operands expect pointer values");
3624 // Add information to the INLINEASM node to know about this input.
3625 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3626 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3627 TLI.getPointerTy()));
3628 AsmNodeOperands.push_back(InOperandVal);
3632 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3633 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3634 "Unknown constraint type!");
3635 assert(!OpInfo.isIndirect &&
3636 "Don't know how to handle indirect register inputs yet!");
3638 // Copy the input into the appropriate registers.
3639 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3640 "Couldn't allocate input reg!");
3642 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3644 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3648 case InlineAsm::isClobber: {
3649 // Add the clobbered value to the operand list, so that the register
3650 // allocator is aware that the physreg got clobbered.
3651 if (!OpInfo.AssignedRegs.Regs.empty())
3652 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3659 // Finish up input operands.
3660 AsmNodeOperands[0] = Chain;
3661 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3663 Chain = DAG.getNode(ISD::INLINEASM,
3664 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3665 &AsmNodeOperands[0], AsmNodeOperands.size());
3666 Flag = Chain.getValue(1);
3668 // If this asm returns a register value, copy the result from that register
3669 // and set it as the value of the call.
3670 if (!RetValRegs.Regs.empty()) {
3671 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3673 // If the result of the inline asm is a vector, it may have the wrong
3674 // width/num elts. Make sure to convert it to the right type with
3676 if (MVT::isVector(Val.getValueType())) {
3677 const VectorType *VTy = cast<VectorType>(I.getType());
3678 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3680 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3686 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3688 // Process indirect outputs, first output all of the flagged copies out of
3690 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3691 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3692 Value *Ptr = IndirectStoresToEmit[i].second;
3693 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3694 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3697 // Emit the non-flagged stores from the physregs.
3698 SmallVector<SDOperand, 8> OutChains;
3699 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3700 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3701 getValue(StoresToEmit[i].second),
3702 StoresToEmit[i].second, 0));
3703 if (!OutChains.empty())
3704 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3705 &OutChains[0], OutChains.size());
3710 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3711 SDOperand Src = getValue(I.getOperand(0));
3713 MVT::ValueType IntPtr = TLI.getPointerTy();
3715 if (IntPtr < Src.getValueType())
3716 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3717 else if (IntPtr > Src.getValueType())
3718 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3720 // Scale the source by the type size.
3721 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
3722 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3723 Src, getIntPtrConstant(ElementSize));
3725 TargetLowering::ArgListTy Args;
3726 TargetLowering::ArgListEntry Entry;
3728 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3729 Args.push_back(Entry);
3731 std::pair<SDOperand,SDOperand> Result =
3732 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
3733 DAG.getExternalSymbol("malloc", IntPtr),
3735 setValue(&I, Result.first); // Pointers always fit in registers
3736 DAG.setRoot(Result.second);
3739 void SelectionDAGLowering::visitFree(FreeInst &I) {
3740 TargetLowering::ArgListTy Args;
3741 TargetLowering::ArgListEntry Entry;
3742 Entry.Node = getValue(I.getOperand(0));
3743 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3744 Args.push_back(Entry);
3745 MVT::ValueType IntPtr = TLI.getPointerTy();
3746 std::pair<SDOperand,SDOperand> Result =
3747 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
3748 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3749 DAG.setRoot(Result.second);
3752 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
3753 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3754 // instructions are special in various ways, which require special support to
3755 // insert. The specified MachineInstr is created but not inserted into any
3756 // basic blocks, and the scheduler passes ownership of it to this method.
3757 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
3758 MachineBasicBlock *MBB) {
3759 cerr << "If a target marks an instruction with "
3760 << "'usesCustomDAGSchedInserter', it must implement "
3761 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
3766 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3767 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3768 getValue(I.getOperand(1)),
3769 DAG.getSrcValue(I.getOperand(1))));
3772 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3773 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3774 getValue(I.getOperand(0)),
3775 DAG.getSrcValue(I.getOperand(0)));
3777 DAG.setRoot(V.getValue(1));
3780 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3781 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3782 getValue(I.getOperand(1)),
3783 DAG.getSrcValue(I.getOperand(1))));
3786 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3787 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3788 getValue(I.getOperand(1)),
3789 getValue(I.getOperand(2)),
3790 DAG.getSrcValue(I.getOperand(1)),
3791 DAG.getSrcValue(I.getOperand(2))));
3794 /// TargetLowering::LowerArguments - This is the default LowerArguments
3795 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3796 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3797 /// integrated into SDISel.
3798 std::vector<SDOperand>
3799 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3800 const FunctionType *FTy = F.getFunctionType();
3801 const ParamAttrsList *Attrs = FTy->getParamAttrs();
3802 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3803 std::vector<SDOperand> Ops;
3804 Ops.push_back(DAG.getRoot());
3805 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3806 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3808 // Add one result value for each formal argument.
3809 std::vector<MVT::ValueType> RetVals;
3811 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3813 MVT::ValueType VT = getValueType(I->getType());
3814 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3815 unsigned OriginalAlignment =
3816 getTargetData()->getABITypeAlignment(I->getType());
3818 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3819 // that is zero extended!
3820 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt))
3821 Flags &= ~(ISD::ParamFlags::SExt);
3822 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt))
3823 Flags |= ISD::ParamFlags::SExt;
3824 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg))
3825 Flags |= ISD::ParamFlags::InReg;
3826 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet))
3827 Flags |= ISD::ParamFlags::StructReturn;
3828 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ByVal))
3829 Flags |= ISD::ParamFlags::ByVal;
3830 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
3832 switch (getTypeAction(VT)) {
3833 default: assert(0 && "Unknown type action!");
3835 RetVals.push_back(VT);
3836 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3839 RetVals.push_back(getTypeToTransformTo(VT));
3840 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3843 // If this is an illegal type, it needs to be broken up to fit into
3845 MVT::ValueType RegisterVT = getRegisterType(VT);
3846 unsigned NumRegs = getNumRegisters(VT);
3847 for (unsigned i = 0; i != NumRegs; ++i) {
3848 RetVals.push_back(RegisterVT);
3849 // if it isn't first piece, alignment must be 1
3851 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3852 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3853 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3860 RetVals.push_back(MVT::Other);
3863 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3864 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3865 &Ops[0], Ops.size()).Val;
3866 unsigned NumArgRegs = Result->getNumValues() - 1;
3867 DAG.setRoot(SDOperand(Result, NumArgRegs));
3869 // Set up the return result vector.
3873 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3875 MVT::ValueType VT = getValueType(I->getType());
3877 switch (getTypeAction(VT)) {
3878 default: assert(0 && "Unknown type action!");
3880 Ops.push_back(SDOperand(Result, i++));
3883 SDOperand Op(Result, i++);
3884 if (MVT::isInteger(VT)) {
3885 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt))
3886 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
3887 DAG.getValueType(VT));
3888 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt))
3889 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
3890 DAG.getValueType(VT));
3891 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
3893 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3894 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
3900 MVT::ValueType PartVT = getRegisterType(VT);
3901 unsigned NumParts = getNumRegisters(VT);
3902 SmallVector<SDOperand, 4> Parts(NumParts);
3903 for (unsigned j = 0; j != NumParts; ++j)
3904 Parts[j] = SDOperand(Result, i++);
3905 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
3910 assert(i == NumArgRegs && "Argument register count mismatch!");
3915 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
3916 /// implementation, which just inserts an ISD::CALL node, which is later custom
3917 /// lowered by the target to something concrete. FIXME: When all targets are
3918 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
3919 std::pair<SDOperand, SDOperand>
3920 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
3921 bool RetTyIsSigned, bool isVarArg,
3922 unsigned CallingConv, bool isTailCall,
3924 ArgListTy &Args, SelectionDAG &DAG) {
3925 SmallVector<SDOperand, 32> Ops;
3926 Ops.push_back(Chain); // Op#0 - Chain
3927 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
3928 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
3929 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
3930 Ops.push_back(Callee);
3932 // Handle all of the outgoing arguments.
3933 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
3934 MVT::ValueType VT = getValueType(Args[i].Ty);
3935 SDOperand Op = Args[i].Node;
3936 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3937 unsigned OriginalAlignment =
3938 getTargetData()->getABITypeAlignment(Args[i].Ty);
3941 Flags |= ISD::ParamFlags::SExt;
3943 Flags |= ISD::ParamFlags::ZExt;
3944 if (Args[i].isInReg)
3945 Flags |= ISD::ParamFlags::InReg;
3947 Flags |= ISD::ParamFlags::StructReturn;
3948 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
3950 switch (getTypeAction(VT)) {
3951 default: assert(0 && "Unknown type action!");
3954 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3957 if (MVT::isInteger(VT)) {
3960 ExtOp = ISD::SIGN_EXTEND;
3961 else if (Args[i].isZExt)
3962 ExtOp = ISD::ZERO_EXTEND;
3964 ExtOp = ISD::ANY_EXTEND;
3965 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
3967 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3968 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
3971 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3974 MVT::ValueType PartVT = getRegisterType(VT);
3975 unsigned NumParts = getNumRegisters(VT);
3976 SmallVector<SDOperand, 4> Parts(NumParts);
3977 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
3978 for (unsigned i = 0; i != NumParts; ++i) {
3979 // if it isn't first piece, alignment must be 1
3980 unsigned MyFlags = Flags;
3982 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
3983 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3985 Ops.push_back(Parts[i]);
3986 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
3993 // Figure out the result value types.
3994 MVT::ValueType VT = getValueType(RetTy);
3995 MVT::ValueType RegisterVT = getRegisterType(VT);
3996 unsigned NumRegs = getNumRegisters(VT);
3997 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
3998 for (unsigned i = 0; i != NumRegs; ++i)
3999 RetTys[i] = RegisterVT;
4001 RetTys.push_back(MVT::Other); // Always has a chain.
4003 // Create the CALL node.
4004 SDOperand Res = DAG.getNode(ISD::CALL,
4005 DAG.getVTList(&RetTys[0], NumRegs + 1),
4006 &Ops[0], Ops.size());
4007 SDOperand Chain = Res.getValue(NumRegs);
4009 // Gather up the call result into a single value.
4010 if (RetTy != Type::VoidTy) {
4011 ISD::NodeType AssertOp = ISD::AssertSext;
4013 AssertOp = ISD::AssertZext;
4014 SmallVector<SDOperand, 4> Results(NumRegs);
4015 for (unsigned i = 0; i != NumRegs; ++i)
4016 Results[i] = Res.getValue(i);
4017 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
4020 return std::make_pair(Res, Chain);
4023 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4024 assert(0 && "LowerOperation not implemented for this target!");
4029 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4030 SelectionDAG &DAG) {
4031 assert(0 && "CustomPromoteOperation not implemented for this target!");
4036 /// getMemsetValue - Vectorized representation of the memset value
4038 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4039 SelectionDAG &DAG) {
4040 MVT::ValueType CurVT = VT;
4041 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4042 uint64_t Val = C->getValue() & 255;
4044 while (CurVT != MVT::i8) {
4045 Val = (Val << Shift) | Val;
4047 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4049 return DAG.getConstant(Val, VT);
4051 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4053 while (CurVT != MVT::i8) {
4055 DAG.getNode(ISD::OR, VT,
4056 DAG.getNode(ISD::SHL, VT, Value,
4057 DAG.getConstant(Shift, MVT::i8)), Value);
4059 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4066 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4067 /// used when a memcpy is turned into a memset when the source is a constant
4069 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4070 SelectionDAG &DAG, TargetLowering &TLI,
4071 std::string &Str, unsigned Offset) {
4073 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4074 if (TLI.isLittleEndian())
4075 Offset = Offset + MSB - 1;
4076 for (unsigned i = 0; i != MSB; ++i) {
4077 Val = (Val << 8) | (unsigned char)Str[Offset];
4078 Offset += TLI.isLittleEndian() ? -1 : 1;
4080 return DAG.getConstant(Val, VT);
4083 /// getMemBasePlusOffset - Returns base and offset node for the
4084 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4085 SelectionDAG &DAG, TargetLowering &TLI) {
4086 MVT::ValueType VT = Base.getValueType();
4087 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4090 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4091 /// to replace the memset / memcpy is below the threshold. It also returns the
4092 /// types of the sequence of memory ops to perform memset / memcpy.
4093 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4094 unsigned Limit, uint64_t Size,
4095 unsigned Align, TargetLowering &TLI) {
4098 if (TLI.allowsUnalignedMemoryAccesses()) {
4101 switch (Align & 7) {
4117 MVT::ValueType LVT = MVT::i64;
4118 while (!TLI.isTypeLegal(LVT))
4119 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4120 assert(MVT::isInteger(LVT));
4125 unsigned NumMemOps = 0;
4127 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4128 while (VTSize > Size) {
4129 VT = (MVT::ValueType)((unsigned)VT - 1);
4132 assert(MVT::isInteger(VT));
4134 if (++NumMemOps > Limit)
4136 MemOps.push_back(VT);
4143 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4144 SDOperand Op1 = getValue(I.getOperand(1));
4145 SDOperand Op2 = getValue(I.getOperand(2));
4146 SDOperand Op3 = getValue(I.getOperand(3));
4147 SDOperand Op4 = getValue(I.getOperand(4));
4148 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4149 if (Align == 0) Align = 1;
4151 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4152 std::vector<MVT::ValueType> MemOps;
4154 // Expand memset / memcpy to a series of load / store ops
4155 // if the size operand falls below a certain threshold.
4156 SmallVector<SDOperand, 8> OutChains;
4158 default: break; // Do nothing for now.
4160 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4161 Size->getValue(), Align, TLI)) {
4162 unsigned NumMemOps = MemOps.size();
4163 unsigned Offset = 0;
4164 for (unsigned i = 0; i < NumMemOps; i++) {
4165 MVT::ValueType VT = MemOps[i];
4166 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4167 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4168 SDOperand Store = DAG.getStore(getRoot(), Value,
4169 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4170 I.getOperand(1), Offset);
4171 OutChains.push_back(Store);
4178 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4179 Size->getValue(), Align, TLI)) {
4180 unsigned NumMemOps = MemOps.size();
4181 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4182 GlobalAddressSDNode *G = NULL;
4184 bool CopyFromStr = false;
4186 if (Op2.getOpcode() == ISD::GlobalAddress)
4187 G = cast<GlobalAddressSDNode>(Op2);
4188 else if (Op2.getOpcode() == ISD::ADD &&
4189 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4190 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4191 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4192 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4195 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4196 if (GV && GV->isConstant()) {
4197 Str = GV->getStringValue(false);
4205 for (unsigned i = 0; i < NumMemOps; i++) {
4206 MVT::ValueType VT = MemOps[i];
4207 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4208 SDOperand Value, Chain, Store;
4211 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4214 DAG.getStore(Chain, Value,
4215 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4216 I.getOperand(1), DstOff);
4218 Value = DAG.getLoad(VT, getRoot(),
4219 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4220 I.getOperand(2), SrcOff);
4221 Chain = Value.getValue(1);
4223 DAG.getStore(Chain, Value,
4224 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4225 I.getOperand(1), DstOff);
4227 OutChains.push_back(Store);
4236 if (!OutChains.empty()) {
4237 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4238 &OutChains[0], OutChains.size()));
4243 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
4246 //===----------------------------------------------------------------------===//
4247 // SelectionDAGISel code
4248 //===----------------------------------------------------------------------===//
4250 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4251 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
4254 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4255 AU.addRequired<AliasAnalysis>();
4256 AU.setPreservesAll();
4261 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4262 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4263 RegMap = MF.getSSARegMap();
4264 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4266 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4268 if (ExceptionHandling)
4269 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4270 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4271 // Mark landing pad.
4272 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4274 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4275 SelectBasicBlock(I, MF, FuncInfo);
4277 // Add function live-ins to entry block live-in set.
4278 BasicBlock *EntryBB = &Fn.getEntryBlock();
4279 BB = FuncInfo.MBBMap[EntryBB];
4280 if (!MF.livein_empty())
4281 for (MachineFunction::livein_iterator I = MF.livein_begin(),
4282 E = MF.livein_end(); I != E; ++I)
4283 BB->addLiveIn(I->first);
4286 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4287 "Not all catch info was assigned to a landing pad!");
4293 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4295 SDOperand Op = getValue(V);
4296 assert((Op.getOpcode() != ISD::CopyFromReg ||
4297 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4298 "Copy from a reg to the same reg!");
4300 MVT::ValueType SrcVT = Op.getValueType();
4301 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4302 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4303 SmallVector<SDOperand, 8> Regs(NumRegs);
4304 SmallVector<SDOperand, 8> Chains(NumRegs);
4306 // Copy the value by legal parts into sequential virtual registers.
4307 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4308 for (unsigned i = 0; i != NumRegs; ++i)
4309 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4310 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4313 void SelectionDAGISel::
4314 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4315 std::vector<SDOperand> &UnorderedChains) {
4316 // If this is the entry block, emit arguments.
4317 Function &F = *LLVMBB->getParent();
4318 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4319 SDOperand OldRoot = SDL.DAG.getRoot();
4320 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4323 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4325 if (!AI->use_empty()) {
4326 SDL.setValue(AI, Args[a]);
4328 // If this argument is live outside of the entry block, insert a copy from
4329 // whereever we got it to the vreg that other BB's will reference it as.
4330 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4331 if (VMI != FuncInfo.ValueMap.end()) {
4332 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4333 UnorderedChains.push_back(Copy);
4337 // Finally, if the target has anything special to do, allow it to do so.
4338 // FIXME: this should insert code into the DAG!
4339 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4342 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4343 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4344 assert(!FLI.MBBMap[SrcBB]->isLandingPad() &&
4345 "Copying catch info out of a landing pad!");
4346 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4347 if (isSelector(I)) {
4348 // Apply the catch info to DestBB.
4349 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4351 FLI.CatchInfoFound.insert(I);
4356 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4357 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4358 FunctionLoweringInfo &FuncInfo) {
4359 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
4361 std::vector<SDOperand> UnorderedChains;
4363 // Lower any arguments needed in this block if this is the entry block.
4364 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4365 LowerArguments(LLVMBB, SDL, UnorderedChains);
4367 BB = FuncInfo.MBBMap[LLVMBB];
4368 SDL.setCurrentBasicBlock(BB);
4370 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4372 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4373 // Add a label to mark the beginning of the landing pad. Deletion of the
4374 // landing pad can thus be detected via the MachineModuleInfo.
4375 unsigned LabelID = MMI->addLandingPad(BB);
4376 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4377 DAG.getConstant(LabelID, MVT::i32)));
4379 // Mark exception register as live in.
4380 unsigned Reg = TLI.getExceptionAddressRegister();
4381 if (Reg) BB->addLiveIn(Reg);
4383 // Mark exception selector register as live in.
4384 Reg = TLI.getExceptionSelectorRegister();
4385 if (Reg) BB->addLiveIn(Reg);
4387 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4388 // function and list of typeids logically belong to the invoke (or, if you
4389 // like, the basic block containing the invoke), and need to be associated
4390 // with it in the dwarf exception handling tables. Currently however the
4391 // information is provided by an intrinsic (eh.selector) that can be moved
4392 // to unexpected places by the optimizers: if the unwind edge is critical,
4393 // then breaking it can result in the intrinsics being in the successor of
4394 // the landing pad, not the landing pad itself. This results in exceptions
4395 // not being caught because no typeids are associated with the invoke.
4396 // This may not be the only way things can go wrong, but it is the only way
4397 // we try to work around for the moment.
4398 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4400 if (Br && Br->isUnconditional()) { // Critical edge?
4401 BasicBlock::iterator I, E;
4402 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4407 // No catch info found - try to extract some from the successor.
4408 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4412 // Lower all of the non-terminator instructions.
4413 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4417 // Ensure that all instructions which are used outside of their defining
4418 // blocks are available as virtual registers. Invoke is handled elsewhere.
4419 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4420 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4421 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4422 if (VMI != FuncInfo.ValueMap.end())
4423 UnorderedChains.push_back(
4424 SDL.CopyValueToVirtualRegister(I, VMI->second));
4427 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4428 // ensure constants are generated when needed. Remember the virtual registers
4429 // that need to be added to the Machine PHI nodes as input. We cannot just
4430 // directly add them, because expansion might result in multiple MBB's for one
4431 // BB. As such, the start of the BB might correspond to a different MBB than
4434 TerminatorInst *TI = LLVMBB->getTerminator();
4436 // Emit constants only once even if used by multiple PHI nodes.
4437 std::map<Constant*, unsigned> ConstantsOut;
4439 // Vector bool would be better, but vector<bool> is really slow.
4440 std::vector<unsigned char> SuccsHandled;
4441 if (TI->getNumSuccessors())
4442 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4444 // Check successor nodes' PHI nodes that expect a constant to be available
4446 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4447 BasicBlock *SuccBB = TI->getSuccessor(succ);
4448 if (!isa<PHINode>(SuccBB->begin())) continue;
4449 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4451 // If this terminator has multiple identical successors (common for
4452 // switches), only handle each succ once.
4453 unsigned SuccMBBNo = SuccMBB->getNumber();
4454 if (SuccsHandled[SuccMBBNo]) continue;
4455 SuccsHandled[SuccMBBNo] = true;
4457 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4460 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4461 // nodes and Machine PHI nodes, but the incoming operands have not been
4463 for (BasicBlock::iterator I = SuccBB->begin();
4464 (PN = dyn_cast<PHINode>(I)); ++I) {
4465 // Ignore dead phi's.
4466 if (PN->use_empty()) continue;
4469 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4471 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4472 unsigned &RegOut = ConstantsOut[C];
4474 RegOut = FuncInfo.CreateRegForValue(C);
4475 UnorderedChains.push_back(
4476 SDL.CopyValueToVirtualRegister(C, RegOut));
4480 Reg = FuncInfo.ValueMap[PHIOp];
4482 assert(isa<AllocaInst>(PHIOp) &&
4483 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4484 "Didn't codegen value into a register!??");
4485 Reg = FuncInfo.CreateRegForValue(PHIOp);
4486 UnorderedChains.push_back(
4487 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4491 // Remember that this register needs to added to the machine PHI node as
4492 // the input for this MBB.
4493 MVT::ValueType VT = TLI.getValueType(PN->getType());
4494 unsigned NumRegisters = TLI.getNumRegisters(VT);
4495 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4496 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4499 ConstantsOut.clear();
4501 // Turn all of the unordered chains into one factored node.
4502 if (!UnorderedChains.empty()) {
4503 SDOperand Root = SDL.getRoot();
4504 if (Root.getOpcode() != ISD::EntryToken) {
4505 unsigned i = 0, e = UnorderedChains.size();
4506 for (; i != e; ++i) {
4507 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4508 if (UnorderedChains[i].Val->getOperand(0) == Root)
4509 break; // Don't add the root if we already indirectly depend on it.
4513 UnorderedChains.push_back(Root);
4515 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4516 &UnorderedChains[0], UnorderedChains.size()));
4519 // Lower the terminator after the copies are emitted.
4520 SDL.visit(*LLVMBB->getTerminator());
4522 // Copy over any CaseBlock records that may now exist due to SwitchInst
4523 // lowering, as well as any jump table information.
4524 SwitchCases.clear();
4525 SwitchCases = SDL.SwitchCases;
4527 JTCases = SDL.JTCases;
4528 BitTestCases.clear();
4529 BitTestCases = SDL.BitTestCases;
4531 // Make sure the root of the DAG is up-to-date.
4532 DAG.setRoot(SDL.getRoot());
4535 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4536 // Get alias analysis for load/store combining.
4537 AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
4539 // Run the DAG combiner in pre-legalize mode.
4540 DAG.Combine(false, AA);
4542 DOUT << "Lowered selection DAG:\n";
4545 // Second step, hack on the DAG until it only uses operations and types that
4546 // the target supports.
4549 DOUT << "Legalized selection DAG:\n";
4552 // Run the DAG combiner in post-legalize mode.
4553 DAG.Combine(true, AA);
4555 if (ViewISelDAGs) DAG.viewGraph();
4557 // Third, instruction select all of the operations to machine code, adding the
4558 // code to the MachineBasicBlock.
4559 InstructionSelectBasicBlock(DAG);
4561 DOUT << "Selected machine code:\n";
4565 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4566 FunctionLoweringInfo &FuncInfo) {
4567 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4569 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4572 // First step, lower LLVM code to some DAG. This DAG may use operations and
4573 // types that are not supported by the target.
4574 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4576 // Second step, emit the lowered DAG as machine code.
4577 CodeGenAndEmitDAG(DAG);
4580 DOUT << "Total amount of phi nodes to update: "
4581 << PHINodesToUpdate.size() << "\n";
4582 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4583 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4584 << ", " << PHINodesToUpdate[i].second << ")\n";);
4586 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4587 // PHI nodes in successors.
4588 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4589 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4590 MachineInstr *PHI = PHINodesToUpdate[i].first;
4591 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4592 "This is not a machine PHI node that we are updating!");
4593 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4594 PHI->addMachineBasicBlockOperand(BB);
4599 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4600 // Lower header first, if it wasn't already lowered
4601 if (!BitTestCases[i].Emitted) {
4602 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4604 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo);
4605 // Set the current basic block to the mbb we wish to insert the code into
4606 BB = BitTestCases[i].Parent;
4607 HSDL.setCurrentBasicBlock(BB);
4609 HSDL.visitBitTestHeader(BitTestCases[i]);
4610 HSDAG.setRoot(HSDL.getRoot());
4611 CodeGenAndEmitDAG(HSDAG);
4614 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4615 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4617 SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo);
4618 // Set the current basic block to the mbb we wish to insert the code into
4619 BB = BitTestCases[i].Cases[j].ThisBB;
4620 BSDL.setCurrentBasicBlock(BB);
4623 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4624 BitTestCases[i].Reg,
4625 BitTestCases[i].Cases[j]);
4627 BSDL.visitBitTestCase(BitTestCases[i].Default,
4628 BitTestCases[i].Reg,
4629 BitTestCases[i].Cases[j]);
4632 BSDAG.setRoot(BSDL.getRoot());
4633 CodeGenAndEmitDAG(BSDAG);
4637 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4638 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4639 MachineBasicBlock *PHIBB = PHI->getParent();
4640 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4641 "This is not a machine PHI node that we are updating!");
4642 // This is "default" BB. We have two jumps to it. From "header" BB and
4643 // from last "case" BB.
4644 if (PHIBB == BitTestCases[i].Default) {
4645 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4646 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent);
4647 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4648 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB);
4650 // One of "cases" BB.
4651 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4652 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4653 if (cBB->succ_end() !=
4654 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4655 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4656 PHI->addMachineBasicBlockOperand(cBB);
4662 // If the JumpTable record is filled in, then we need to emit a jump table.
4663 // Updating the PHI nodes is tricky in this case, since we need to determine
4664 // whether the PHI is a successor of the range check MBB or the jump table MBB
4665 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4666 // Lower header first, if it wasn't already lowered
4667 if (!JTCases[i].first.Emitted) {
4668 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4670 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo);
4671 // Set the current basic block to the mbb we wish to insert the code into
4672 BB = JTCases[i].first.HeaderBB;
4673 HSDL.setCurrentBasicBlock(BB);
4675 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4676 HSDAG.setRoot(HSDL.getRoot());
4677 CodeGenAndEmitDAG(HSDAG);
4680 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4682 SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo);
4683 // Set the current basic block to the mbb we wish to insert the code into
4684 BB = JTCases[i].second.MBB;
4685 JSDL.setCurrentBasicBlock(BB);
4687 JSDL.visitJumpTable(JTCases[i].second);
4688 JSDAG.setRoot(JSDL.getRoot());
4689 CodeGenAndEmitDAG(JSDAG);
4692 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4693 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4694 MachineBasicBlock *PHIBB = PHI->getParent();
4695 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4696 "This is not a machine PHI node that we are updating!");
4697 // "default" BB. We can go there only from header BB.
4698 if (PHIBB == JTCases[i].second.Default) {
4699 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4700 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB);
4702 // JT BB. Just iterate over successors here
4703 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4704 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4705 PHI->addMachineBasicBlockOperand(BB);
4710 // If the switch block involved a branch to one of the actual successors, we
4711 // need to update PHI nodes in that block.
4712 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4713 MachineInstr *PHI = PHINodesToUpdate[i].first;
4714 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4715 "This is not a machine PHI node that we are updating!");
4716 if (BB->isSuccessor(PHI->getParent())) {
4717 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4718 PHI->addMachineBasicBlockOperand(BB);
4722 // If we generated any switch lowering information, build and codegen any
4723 // additional DAGs necessary.
4724 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4725 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4727 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4729 // Set the current basic block to the mbb we wish to insert the code into
4730 BB = SwitchCases[i].ThisBB;
4731 SDL.setCurrentBasicBlock(BB);
4734 SDL.visitSwitchCase(SwitchCases[i]);
4735 SDAG.setRoot(SDL.getRoot());
4736 CodeGenAndEmitDAG(SDAG);
4738 // Handle any PHI nodes in successors of this chunk, as if we were coming
4739 // from the original BB before switch expansion. Note that PHI nodes can
4740 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4741 // handle them the right number of times.
4742 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4743 for (MachineBasicBlock::iterator Phi = BB->begin();
4744 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4745 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4746 for (unsigned pn = 0; ; ++pn) {
4747 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4748 if (PHINodesToUpdate[pn].first == Phi) {
4749 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4750 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4756 // Don't process RHS if same block as LHS.
4757 if (BB == SwitchCases[i].FalseBB)
4758 SwitchCases[i].FalseBB = 0;
4760 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4761 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4762 SwitchCases[i].FalseBB = 0;
4764 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4769 //===----------------------------------------------------------------------===//
4770 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4771 /// target node in the graph.
4772 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4773 if (ViewSchedDAGs) DAG.viewGraph();
4775 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4779 RegisterScheduler::setDefault(Ctor);
4782 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4788 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4789 return new HazardRecognizer();
4792 //===----------------------------------------------------------------------===//
4793 // Helper functions used by the generated instruction selector.
4794 //===----------------------------------------------------------------------===//
4795 // Calls to these methods are generated by tblgen.
4797 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4798 /// the dag combiner simplified the 255, we still want to match. RHS is the
4799 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4800 /// specified in the .td file (e.g. 255).
4801 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4802 int64_t DesiredMaskS) {
4803 uint64_t ActualMask = RHS->getValue();
4804 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4806 // If the actual mask exactly matches, success!
4807 if (ActualMask == DesiredMask)
4810 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4811 if (ActualMask & ~DesiredMask)
4814 // Otherwise, the DAG Combiner may have proven that the value coming in is
4815 // either already zero or is not demanded. Check for known zero input bits.
4816 uint64_t NeededMask = DesiredMask & ~ActualMask;
4817 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
4820 // TODO: check to see if missing bits are just not demanded.
4822 // Otherwise, this pattern doesn't match.
4826 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
4827 /// the dag combiner simplified the 255, we still want to match. RHS is the
4828 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
4829 /// specified in the .td file (e.g. 255).
4830 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
4831 int64_t DesiredMaskS) {
4832 uint64_t ActualMask = RHS->getValue();
4833 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4835 // If the actual mask exactly matches, success!
4836 if (ActualMask == DesiredMask)
4839 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4840 if (ActualMask & ~DesiredMask)
4843 // Otherwise, the DAG Combiner may have proven that the value coming in is
4844 // either already zero or is not demanded. Check for known zero input bits.
4845 uint64_t NeededMask = DesiredMask & ~ActualMask;
4847 uint64_t KnownZero, KnownOne;
4848 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
4850 // If all the missing bits in the or are already known to be set, match!
4851 if ((NeededMask & KnownOne) == NeededMask)
4854 // TODO: check to see if missing bits are just not demanded.
4856 // Otherwise, this pattern doesn't match.
4861 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
4862 /// by tblgen. Others should not call it.
4863 void SelectionDAGISel::
4864 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
4865 std::vector<SDOperand> InOps;
4866 std::swap(InOps, Ops);
4868 Ops.push_back(InOps[0]); // input chain.
4869 Ops.push_back(InOps[1]); // input asm string.
4871 unsigned i = 2, e = InOps.size();
4872 if (InOps[e-1].getValueType() == MVT::Flag)
4873 --e; // Don't process a flag operand if it is here.
4876 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
4877 if ((Flags & 7) != 4 /*MEM*/) {
4878 // Just skip over this operand, copying the operands verbatim.
4879 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
4880 i += (Flags >> 3) + 1;
4882 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
4883 // Otherwise, this is a memory operand. Ask the target to select it.
4884 std::vector<SDOperand> SelOps;
4885 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
4886 cerr << "Could not match memory address. Inline asm failure!\n";
4890 // Add this to the output node.
4891 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4892 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
4894 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
4899 // Add the flag input back if present.
4900 if (e != InOps.size())
4901 Ops.push_back(InOps.back());
4904 char SelectionDAGISel::ID = 0;