1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/Timer.h"
53 EnableValueProp("enable-value-prop", cl::Hidden);
55 EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
60 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
61 cl::desc("Pop up a window to show dags before the first "
64 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
65 cl::desc("Pop up a window to show dags before legalize types"));
67 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
68 cl::desc("Pop up a window to show dags before legalize"));
70 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before the second "
74 ViewISelDAGs("view-isel-dags", cl::Hidden,
75 cl::desc("Pop up a window to show isel dags as they are selected"));
77 ViewSchedDAGs("view-sched-dags", cl::Hidden,
78 cl::desc("Pop up a window to show sched dags as they are processed"));
80 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
81 cl::desc("Pop up a window to show SUnit dags after they are processed"));
83 static const bool ViewDAGCombine1 = false,
84 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
85 ViewDAGCombine2 = false,
86 ViewISelDAGs = false, ViewSchedDAGs = false,
87 ViewSUnitDAGs = false;
90 //===---------------------------------------------------------------------===//
92 /// RegisterScheduler class - Track the registration of instruction schedulers.
94 //===---------------------------------------------------------------------===//
95 MachinePassRegistry RegisterScheduler::Registry;
97 //===---------------------------------------------------------------------===//
99 /// ISHeuristic command line option for instruction schedulers.
101 //===---------------------------------------------------------------------===//
102 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
103 RegisterPassParser<RegisterScheduler> >
104 ISHeuristic("pre-RA-sched",
105 cl::init(&createDefaultScheduler),
106 cl::desc("Instruction schedulers available (before register"
109 static RegisterScheduler
110 defaultListDAGScheduler("default", " Best scheduler for the target",
111 createDefaultScheduler);
113 namespace { struct SDISelAsmOperandInfo; }
115 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
116 /// insertvalue or extractvalue indices that identify a member, return
117 /// the linearized index of the start of the member.
119 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
120 const unsigned *Indices,
121 const unsigned *IndicesEnd,
122 unsigned CurIndex = 0) {
123 // Base case: We're done.
124 if (Indices && Indices == IndicesEnd)
127 // Given a struct type, recursively traverse the elements.
128 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
129 for (StructType::element_iterator EB = STy->element_begin(),
131 EE = STy->element_end();
133 if (Indices && *Indices == unsigned(EI - EB))
134 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
135 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
138 // Given an array type, recursively traverse the elements.
139 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
140 const Type *EltTy = ATy->getElementType();
141 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
142 if (Indices && *Indices == i)
143 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
144 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
147 // We haven't found the type we're looking for, so keep searching.
151 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
152 /// MVTs that represent all the individual underlying
153 /// non-aggregate types that comprise it.
155 /// If Offsets is non-null, it points to a vector to be filled in
156 /// with the in-memory offsets of each of the individual values.
158 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
159 SmallVectorImpl<MVT> &ValueVTs,
160 SmallVectorImpl<uint64_t> *Offsets = 0,
161 uint64_t StartingOffset = 0) {
162 // Given a struct type, recursively traverse the elements.
163 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
164 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
165 for (StructType::element_iterator EB = STy->element_begin(),
167 EE = STy->element_end();
169 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
170 StartingOffset + SL->getElementOffset(EI - EB));
173 // Given an array type, recursively traverse the elements.
174 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
175 const Type *EltTy = ATy->getElementType();
176 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
177 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
178 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
179 StartingOffset + i * EltSize);
182 // Base case: we can get an MVT for this LLVM IR type.
183 ValueVTs.push_back(TLI.getValueType(Ty));
185 Offsets->push_back(StartingOffset);
189 /// RegsForValue - This struct represents the registers (physical or virtual)
190 /// that a particular set of values is assigned, and the type information about
191 /// the value. The most common situation is to represent one value at a time,
192 /// but struct or array values are handled element-wise as multiple values.
193 /// The splitting of aggregates is performed recursively, so that we never
194 /// have aggregate-typed registers. The values at this point do not necessarily
195 /// have legal types, so each value may require one or more registers of some
198 struct VISIBILITY_HIDDEN RegsForValue {
199 /// TLI - The TargetLowering object.
201 const TargetLowering *TLI;
203 /// ValueVTs - The value types of the values, which may not be legal, and
204 /// may need be promoted or synthesized from one or more registers.
206 SmallVector<MVT, 4> ValueVTs;
208 /// RegVTs - The value types of the registers. This is the same size as
209 /// ValueVTs and it records, for each value, what the type of the assigned
210 /// register or registers are. (Individual values are never synthesized
211 /// from more than one type of register.)
213 /// With virtual registers, the contents of RegVTs is redundant with TLI's
214 /// getRegisterType member function, however when with physical registers
215 /// it is necessary to have a separate record of the types.
217 SmallVector<MVT, 4> RegVTs;
219 /// Regs - This list holds the registers assigned to the values.
220 /// Each legal or promoted value requires one register, and each
221 /// expanded value requires multiple registers.
223 SmallVector<unsigned, 4> Regs;
225 RegsForValue() : TLI(0) {}
227 RegsForValue(const TargetLowering &tli,
228 const SmallVector<unsigned, 4> ®s,
229 MVT regvt, MVT valuevt)
230 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
231 RegsForValue(const TargetLowering &tli,
232 const SmallVector<unsigned, 4> ®s,
233 const SmallVector<MVT, 4> ®vts,
234 const SmallVector<MVT, 4> &valuevts)
235 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
236 RegsForValue(const TargetLowering &tli,
237 unsigned Reg, const Type *Ty) : TLI(&tli) {
238 ComputeValueVTs(tli, Ty, ValueVTs);
240 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
241 MVT ValueVT = ValueVTs[Value];
242 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
243 MVT RegisterVT = TLI->getRegisterType(ValueVT);
244 for (unsigned i = 0; i != NumRegs; ++i)
245 Regs.push_back(Reg + i);
246 RegVTs.push_back(RegisterVT);
251 /// append - Add the specified values to this one.
252 void append(const RegsForValue &RHS) {
254 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
255 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
256 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
260 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
261 /// this value and returns the result as a ValueVTs value. This uses
262 /// Chain/Flag as the input and updates them for the output Chain/Flag.
263 /// If the Flag pointer is NULL, no flag is used.
264 SDOperand getCopyFromRegs(SelectionDAG &DAG,
265 SDOperand &Chain, SDOperand *Flag) const;
267 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
268 /// specified value into the registers specified by this object. This uses
269 /// Chain/Flag as the input and updates them for the output Chain/Flag.
270 /// If the Flag pointer is NULL, no flag is used.
271 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
272 SDOperand &Chain, SDOperand *Flag) const;
274 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
275 /// operand list. This adds the code marker and includes the number of
276 /// values added into it.
277 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
278 std::vector<SDOperand> &Ops) const;
283 //===--------------------------------------------------------------------===//
284 /// createDefaultScheduler - This creates an instruction scheduler appropriate
286 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
288 MachineBasicBlock *BB,
290 TargetLowering &TLI = IS->getTargetLowering();
292 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
293 return createTDListDAGScheduler(IS, DAG, BB, Fast);
295 assert(TLI.getSchedulingPreference() ==
296 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
297 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
302 //===--------------------------------------------------------------------===//
303 /// FunctionLoweringInfo - This contains information that is global to a
304 /// function that is used when lowering a region of the function.
305 class FunctionLoweringInfo {
310 MachineRegisterInfo &RegInfo;
312 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
314 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
315 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
317 /// ValueMap - Since we emit code for the function a basic block at a time,
318 /// we must remember which virtual registers hold the values for
319 /// cross-basic-block values.
320 DenseMap<const Value*, unsigned> ValueMap;
322 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
323 /// the entry block. This allows the allocas to be efficiently referenced
324 /// anywhere in the function.
325 std::map<const AllocaInst*, int> StaticAllocaMap;
328 SmallSet<Instruction*, 8> CatchInfoLost;
329 SmallSet<Instruction*, 8> CatchInfoFound;
332 unsigned MakeReg(MVT VT) {
333 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
336 /// isExportedInst - Return true if the specified value is an instruction
337 /// exported from its block.
338 bool isExportedInst(const Value *V) {
339 return ValueMap.count(V);
342 unsigned CreateRegForValue(const Value *V);
344 unsigned InitializeRegForValue(const Value *V) {
345 unsigned &R = ValueMap[V];
346 assert(R == 0 && "Already initialized this value register!");
347 return R = CreateRegForValue(V);
351 unsigned NumSignBits;
352 APInt KnownOne, KnownZero;
353 LiveOutInfo() : NumSignBits(0) {}
356 /// LiveOutRegInfo - Information about live out vregs, indexed by their
357 /// register number offset by 'FirstVirtualRegister'.
358 std::vector<LiveOutInfo> LiveOutRegInfo;
362 /// isSelector - Return true if this instruction is a call to the
363 /// eh.selector intrinsic.
364 static bool isSelector(Instruction *I) {
365 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
366 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
367 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
371 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
372 /// PHI nodes or outside of the basic block that defines it, or used by a
373 /// switch or atomic instruction, which may expand to multiple basic blocks.
374 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
375 if (isa<PHINode>(I)) return true;
376 BasicBlock *BB = I->getParent();
377 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
378 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
379 // FIXME: Remove switchinst special case.
380 isa<SwitchInst>(*UI))
385 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
386 /// entry block, return true. This includes arguments used by switches, since
387 /// the switch may expand into multiple basic blocks.
388 static bool isOnlyUsedInEntryBlock(Argument *A) {
389 BasicBlock *Entry = A->getParent()->begin();
390 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
391 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
392 return false; // Use not in entry block.
396 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
397 Function &fn, MachineFunction &mf)
398 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
400 // Create a vreg for each argument register that is not dead and is used
401 // outside of the entry block for the function.
402 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
404 if (!isOnlyUsedInEntryBlock(AI))
405 InitializeRegForValue(AI);
407 // Initialize the mapping of values to registers. This is only set up for
408 // instruction values that are used outside of the block that defines
410 Function::iterator BB = Fn.begin(), EB = Fn.end();
411 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
412 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
413 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
414 const Type *Ty = AI->getAllocatedType();
415 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
417 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
420 TySize *= CUI->getZExtValue(); // Get total allocated size.
421 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
422 StaticAllocaMap[AI] =
423 MF.getFrameInfo()->CreateStackObject(TySize, Align);
426 for (; BB != EB; ++BB)
427 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
428 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
429 if (!isa<AllocaInst>(I) ||
430 !StaticAllocaMap.count(cast<AllocaInst>(I)))
431 InitializeRegForValue(I);
433 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
434 // also creates the initial PHI MachineInstrs, though none of the input
435 // operands are populated.
436 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
437 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
441 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
444 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
445 if (PN->use_empty()) continue;
447 MVT VT = TLI.getValueType(PN->getType());
448 unsigned NumRegisters = TLI.getNumRegisters(VT);
449 unsigned PHIReg = ValueMap[PN];
450 assert(PHIReg && "PHI node does not have an assigned virtual register!");
451 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
452 for (unsigned i = 0; i != NumRegisters; ++i)
453 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
458 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
459 /// the correctly promoted or expanded types. Assign these registers
460 /// consecutive vreg numbers and return the first assigned number.
462 /// In the case that the given value has struct or array type, this function
463 /// will assign registers for each member or element.
465 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
466 SmallVector<MVT, 4> ValueVTs;
467 ComputeValueVTs(TLI, V->getType(), ValueVTs);
469 unsigned FirstReg = 0;
470 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
471 MVT ValueVT = ValueVTs[Value];
472 MVT RegisterVT = TLI.getRegisterType(ValueVT);
474 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
475 for (unsigned i = 0; i != NumRegs; ++i) {
476 unsigned R = MakeReg(RegisterVT);
477 if (!FirstReg) FirstReg = R;
483 //===----------------------------------------------------------------------===//
484 /// SelectionDAGLowering - This is the common target-independent lowering
485 /// implementation that is parameterized by a TargetLowering object.
486 /// Also, targets can overload any lowering method.
489 class SelectionDAGLowering {
490 MachineBasicBlock *CurMBB;
492 DenseMap<const Value*, SDOperand> NodeMap;
494 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
495 /// them up and then emit token factor nodes when possible. This allows us to
496 /// get simple disambiguation between loads without worrying about alias
498 SmallVector<SDOperand, 8> PendingLoads;
500 /// PendingExports - CopyToReg nodes that copy values to virtual registers
501 /// for export to other blocks need to be emitted before any terminator
502 /// instruction, but they have no other ordering requirements. We bunch them
503 /// up and the emit a single tokenfactor for them just before terminator
505 std::vector<SDOperand> PendingExports;
507 /// Case - A struct to record the Value for a switch case, and the
508 /// case's target basic block.
512 MachineBasicBlock* BB;
514 Case() : Low(0), High(0), BB(0) { }
515 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
516 Low(low), High(high), BB(bb) { }
517 uint64_t size() const {
518 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
519 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
520 return (rHigh - rLow + 1ULL);
526 MachineBasicBlock* BB;
529 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
530 Mask(mask), BB(bb), Bits(bits) { }
533 typedef std::vector<Case> CaseVector;
534 typedef std::vector<CaseBits> CaseBitsVector;
535 typedef CaseVector::iterator CaseItr;
536 typedef std::pair<CaseItr, CaseItr> CaseRange;
538 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
539 /// of conditional branches.
541 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
542 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
544 /// CaseBB - The MBB in which to emit the compare and branch
545 MachineBasicBlock *CaseBB;
546 /// LT, GE - If nonzero, we know the current case value must be less-than or
547 /// greater-than-or-equal-to these Constants.
550 /// Range - A pair of iterators representing the range of case values to be
551 /// processed at this point in the binary search tree.
555 typedef std::vector<CaseRec> CaseRecVector;
557 /// The comparison function for sorting the switch case values in the vector.
558 /// WARNING: Case ranges should be disjoint!
560 bool operator () (const Case& C1, const Case& C2) {
561 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
562 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
563 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
564 return CI1->getValue().slt(CI2->getValue());
569 bool operator () (const CaseBits& C1, const CaseBits& C2) {
570 return C1.Bits > C2.Bits;
574 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
577 // TLI - This is information that describes the available target features we
578 // need for lowering. This indicates when operations are unavailable,
579 // implemented with a libcall, etc.
582 const TargetData *TD;
585 /// SwitchCases - Vector of CaseBlock structures used to communicate
586 /// SwitchInst code generation information.
587 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
588 /// JTCases - Vector of JumpTable structures used to communicate
589 /// SwitchInst code generation information.
590 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
591 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
593 /// FuncInfo - Information about the function as a whole.
595 FunctionLoweringInfo &FuncInfo;
597 /// GCI - Garbage collection metadata for the function.
598 CollectorMetadata *GCI;
600 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
602 FunctionLoweringInfo &funcinfo,
603 CollectorMetadata *gci)
604 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
605 FuncInfo(funcinfo), GCI(gci) {
608 /// getRoot - Return the current virtual root of the Selection DAG,
609 /// flushing any PendingLoad items. This must be done before emitting
610 /// a store or any other node that may need to be ordered after any
611 /// prior load instructions.
613 SDOperand getRoot() {
614 if (PendingLoads.empty())
615 return DAG.getRoot();
617 if (PendingLoads.size() == 1) {
618 SDOperand Root = PendingLoads[0];
620 PendingLoads.clear();
624 // Otherwise, we have to make a token factor node.
625 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
626 &PendingLoads[0], PendingLoads.size());
627 PendingLoads.clear();
632 /// getControlRoot - Similar to getRoot, but instead of flushing all the
633 /// PendingLoad items, flush all the PendingExports items. It is necessary
634 /// to do this before emitting a terminator instruction.
636 SDOperand getControlRoot() {
637 SDOperand Root = DAG.getRoot();
639 if (PendingExports.empty())
642 // Turn all of the CopyToReg chains into one factored node.
643 if (Root.getOpcode() != ISD::EntryToken) {
644 unsigned i = 0, e = PendingExports.size();
645 for (; i != e; ++i) {
646 assert(PendingExports[i].Val->getNumOperands() > 1);
647 if (PendingExports[i].Val->getOperand(0) == Root)
648 break; // Don't add the root if we already indirectly depend on it.
652 PendingExports.push_back(Root);
655 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
657 PendingExports.size());
658 PendingExports.clear();
663 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
665 void visit(Instruction &I) { visit(I.getOpcode(), I); }
667 void visit(unsigned Opcode, User &I) {
668 // Note: this doesn't use InstVisitor, because it has to work with
669 // ConstantExpr's in addition to instructions.
671 default: assert(0 && "Unknown instruction type encountered!");
673 // Build the switch statement using the Instruction.def file.
674 #define HANDLE_INST(NUM, OPCODE, CLASS) \
675 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
676 #include "llvm/Instruction.def"
680 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
682 SDOperand getValue(const Value *V);
684 void setValue(const Value *V, SDOperand NewN) {
685 SDOperand &N = NodeMap[V];
686 assert(N.Val == 0 && "Already set a value for this node!");
690 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
691 std::set<unsigned> &OutputRegs,
692 std::set<unsigned> &InputRegs);
694 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
695 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
697 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
698 void ExportFromCurrentBlock(Value *V);
699 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
700 MachineBasicBlock *LandingPad = NULL);
702 // Terminator instructions.
703 void visitRet(ReturnInst &I);
704 void visitBr(BranchInst &I);
705 void visitSwitch(SwitchInst &I);
706 void visitUnreachable(UnreachableInst &I) { /* noop */ }
708 // Helpers for visitSwitch
709 bool handleSmallSwitchRange(CaseRec& CR,
710 CaseRecVector& WorkList,
712 MachineBasicBlock* Default);
713 bool handleJTSwitchCase(CaseRec& CR,
714 CaseRecVector& WorkList,
716 MachineBasicBlock* Default);
717 bool handleBTSplitSwitchCase(CaseRec& CR,
718 CaseRecVector& WorkList,
720 MachineBasicBlock* Default);
721 bool handleBitTestsSwitchCase(CaseRec& CR,
722 CaseRecVector& WorkList,
724 MachineBasicBlock* Default);
725 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
726 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
727 void visitBitTestCase(MachineBasicBlock* NextMBB,
729 SelectionDAGISel::BitTestCase &B);
730 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
731 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
732 SelectionDAGISel::JumpTableHeader &JTH);
734 // These all get lowered before this pass.
735 void visitInvoke(InvokeInst &I);
736 void visitUnwind(UnwindInst &I);
738 void visitBinary(User &I, unsigned OpCode);
739 void visitShift(User &I, unsigned Opcode);
740 void visitAdd(User &I) {
741 if (I.getType()->isFPOrFPVector())
742 visitBinary(I, ISD::FADD);
744 visitBinary(I, ISD::ADD);
746 void visitSub(User &I);
747 void visitMul(User &I) {
748 if (I.getType()->isFPOrFPVector())
749 visitBinary(I, ISD::FMUL);
751 visitBinary(I, ISD::MUL);
753 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
754 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
755 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
756 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
757 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
758 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
759 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
760 void visitOr (User &I) { visitBinary(I, ISD::OR); }
761 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
762 void visitShl (User &I) { visitShift(I, ISD::SHL); }
763 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
764 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
765 void visitICmp(User &I);
766 void visitFCmp(User &I);
767 void visitVICmp(User &I);
768 void visitVFCmp(User &I);
769 // Visit the conversion instructions
770 void visitTrunc(User &I);
771 void visitZExt(User &I);
772 void visitSExt(User &I);
773 void visitFPTrunc(User &I);
774 void visitFPExt(User &I);
775 void visitFPToUI(User &I);
776 void visitFPToSI(User &I);
777 void visitUIToFP(User &I);
778 void visitSIToFP(User &I);
779 void visitPtrToInt(User &I);
780 void visitIntToPtr(User &I);
781 void visitBitCast(User &I);
783 void visitExtractElement(User &I);
784 void visitInsertElement(User &I);
785 void visitShuffleVector(User &I);
787 void visitExtractValue(ExtractValueInst &I);
788 void visitInsertValue(InsertValueInst &I);
790 void visitGetElementPtr(User &I);
791 void visitSelect(User &I);
793 void visitMalloc(MallocInst &I);
794 void visitFree(FreeInst &I);
795 void visitAlloca(AllocaInst &I);
796 void visitLoad(LoadInst &I);
797 void visitStore(StoreInst &I);
798 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
799 void visitCall(CallInst &I);
800 void visitInlineAsm(CallSite CS);
801 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
802 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
804 void visitVAStart(CallInst &I);
805 void visitVAArg(VAArgInst &I);
806 void visitVAEnd(CallInst &I);
807 void visitVACopy(CallInst &I);
809 void visitGetResult(GetResultInst &I);
811 void visitUserOp1(Instruction &I) {
812 assert(0 && "UserOp1 should not exist at instruction selection time!");
815 void visitUserOp2(Instruction &I) {
816 assert(0 && "UserOp2 should not exist at instruction selection time!");
821 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
824 } // end namespace llvm
827 /// getCopyFromParts - Create a value that contains the specified legal parts
828 /// combined into the value they represent. If the parts combine to a type
829 /// larger then ValueVT then AssertOp can be used to specify whether the extra
830 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
831 /// (ISD::AssertSext).
832 static SDOperand getCopyFromParts(SelectionDAG &DAG,
833 const SDOperand *Parts,
837 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
838 assert(NumParts > 0 && "No parts to assemble!");
839 TargetLowering &TLI = DAG.getTargetLoweringInfo();
840 SDOperand Val = Parts[0];
843 // Assemble the value from multiple parts.
844 if (!ValueVT.isVector()) {
845 unsigned PartBits = PartVT.getSizeInBits();
846 unsigned ValueBits = ValueVT.getSizeInBits();
848 // Assemble the power of 2 part.
849 unsigned RoundParts = NumParts & (NumParts - 1) ?
850 1 << Log2_32(NumParts) : NumParts;
851 unsigned RoundBits = PartBits * RoundParts;
852 MVT RoundVT = RoundBits == ValueBits ?
853 ValueVT : MVT::getIntegerVT(RoundBits);
856 if (RoundParts > 2) {
857 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
858 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
859 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
865 if (TLI.isBigEndian())
867 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
869 if (RoundParts < NumParts) {
870 // Assemble the trailing non-power-of-2 part.
871 unsigned OddParts = NumParts - RoundParts;
872 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
873 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
875 // Combine the round and odd parts.
877 if (TLI.isBigEndian())
879 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
880 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
881 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
882 DAG.getConstant(Lo.getValueType().getSizeInBits(),
883 TLI.getShiftAmountTy()));
884 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
885 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
888 // Handle a multi-element vector.
889 MVT IntermediateVT, RegisterVT;
890 unsigned NumIntermediates;
892 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
894 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
895 NumParts = NumRegs; // Silence a compiler warning.
896 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
897 assert(RegisterVT == Parts[0].getValueType() &&
898 "Part type doesn't match part!");
900 // Assemble the parts into intermediate operands.
901 SmallVector<SDOperand, 8> Ops(NumIntermediates);
902 if (NumIntermediates == NumParts) {
903 // If the register was not expanded, truncate or copy the value,
905 for (unsigned i = 0; i != NumParts; ++i)
906 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
907 PartVT, IntermediateVT);
908 } else if (NumParts > 0) {
909 // If the intermediate type was expanded, build the intermediate operands
911 assert(NumParts % NumIntermediates == 0 &&
912 "Must expand into a divisible number of parts!");
913 unsigned Factor = NumParts / NumIntermediates;
914 for (unsigned i = 0; i != NumIntermediates; ++i)
915 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
916 PartVT, IntermediateVT);
919 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
921 Val = DAG.getNode(IntermediateVT.isVector() ?
922 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
923 ValueVT, &Ops[0], NumIntermediates);
927 // There is now one part, held in Val. Correct it to match ValueVT.
928 PartVT = Val.getValueType();
930 if (PartVT == ValueVT)
933 if (PartVT.isVector()) {
934 assert(ValueVT.isVector() && "Unknown vector conversion!");
935 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
938 if (ValueVT.isVector()) {
939 assert(ValueVT.getVectorElementType() == PartVT &&
940 ValueVT.getVectorNumElements() == 1 &&
941 "Only trivial scalar-to-vector conversions should get here!");
942 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
945 if (PartVT.isInteger() &&
946 ValueVT.isInteger()) {
947 if (ValueVT.bitsLT(PartVT)) {
948 // For a truncate, see if we have any information to
949 // indicate whether the truncated bits will always be
950 // zero or sign-extension.
951 if (AssertOp != ISD::DELETED_NODE)
952 Val = DAG.getNode(AssertOp, PartVT, Val,
953 DAG.getValueType(ValueVT));
954 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
956 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
960 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
961 if (ValueVT.bitsLT(Val.getValueType()))
962 // FP_ROUND's are always exact here.
963 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
964 DAG.getIntPtrConstant(1));
965 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
968 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
969 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
971 assert(0 && "Unknown mismatch!");
975 /// getCopyToParts - Create a series of nodes that contain the specified value
976 /// split into legal parts. If the parts contain more bits than Val, then, for
977 /// integers, ExtendKind can be used to specify how to generate the extra bits.
978 static void getCopyToParts(SelectionDAG &DAG,
983 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
984 TargetLowering &TLI = DAG.getTargetLoweringInfo();
985 MVT PtrVT = TLI.getPointerTy();
986 MVT ValueVT = Val.getValueType();
987 unsigned PartBits = PartVT.getSizeInBits();
988 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
993 if (!ValueVT.isVector()) {
994 if (PartVT == ValueVT) {
995 assert(NumParts == 1 && "No-op copy with multiple parts!");
1000 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
1001 // If the parts cover more bits than the value has, promote the value.
1002 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
1003 assert(NumParts == 1 && "Do not know what to promote to!");
1004 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
1005 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
1006 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1007 Val = DAG.getNode(ExtendKind, ValueVT, Val);
1009 assert(0 && "Unknown mismatch!");
1011 } else if (PartBits == ValueVT.getSizeInBits()) {
1012 // Different types of the same size.
1013 assert(NumParts == 1 && PartVT != ValueVT);
1014 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1015 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
1016 // If the parts cover less bits than value has, truncate the value.
1017 if (PartVT.isInteger() && ValueVT.isInteger()) {
1018 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1019 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1021 assert(0 && "Unknown mismatch!");
1025 // The value may have changed - recompute ValueVT.
1026 ValueVT = Val.getValueType();
1027 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1028 "Failed to tile the value with PartVT!");
1030 if (NumParts == 1) {
1031 assert(PartVT == ValueVT && "Type conversion failed!");
1036 // Expand the value into multiple parts.
1037 if (NumParts & (NumParts - 1)) {
1038 // The number of parts is not a power of 2. Split off and copy the tail.
1039 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1040 "Do not know what to expand to!");
1041 unsigned RoundParts = 1 << Log2_32(NumParts);
1042 unsigned RoundBits = RoundParts * PartBits;
1043 unsigned OddParts = NumParts - RoundParts;
1044 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1045 DAG.getConstant(RoundBits,
1046 TLI.getShiftAmountTy()));
1047 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1048 if (TLI.isBigEndian())
1049 // The odd parts were reversed by getCopyToParts - unreverse them.
1050 std::reverse(Parts + RoundParts, Parts + NumParts);
1051 NumParts = RoundParts;
1052 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1053 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1056 // The number of parts is a power of 2. Repeatedly bisect the value using
1058 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1059 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1061 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1062 for (unsigned i = 0; i < NumParts; i += StepSize) {
1063 unsigned ThisBits = StepSize * PartBits / 2;
1064 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1065 SDOperand &Part0 = Parts[i];
1066 SDOperand &Part1 = Parts[i+StepSize/2];
1068 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1069 DAG.getConstant(1, PtrVT));
1070 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1071 DAG.getConstant(0, PtrVT));
1073 if (ThisBits == PartBits && ThisVT != PartVT) {
1074 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1075 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1080 if (TLI.isBigEndian())
1081 std::reverse(Parts, Parts + NumParts);
1087 if (NumParts == 1) {
1088 if (PartVT != ValueVT) {
1089 if (PartVT.isVector()) {
1090 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1092 assert(ValueVT.getVectorElementType() == PartVT &&
1093 ValueVT.getVectorNumElements() == 1 &&
1094 "Only trivial vector-to-scalar conversions should get here!");
1095 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1096 DAG.getConstant(0, PtrVT));
1104 // Handle a multi-element vector.
1105 MVT IntermediateVT, RegisterVT;
1106 unsigned NumIntermediates;
1108 DAG.getTargetLoweringInfo()
1109 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1111 unsigned NumElements = ValueVT.getVectorNumElements();
1113 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1114 NumParts = NumRegs; // Silence a compiler warning.
1115 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1117 // Split the vector into intermediate operands.
1118 SmallVector<SDOperand, 8> Ops(NumIntermediates);
1119 for (unsigned i = 0; i != NumIntermediates; ++i)
1120 if (IntermediateVT.isVector())
1121 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1122 IntermediateVT, Val,
1123 DAG.getConstant(i * (NumElements / NumIntermediates),
1126 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1127 IntermediateVT, Val,
1128 DAG.getConstant(i, PtrVT));
1130 // Split the intermediate operands into legal parts.
1131 if (NumParts == NumIntermediates) {
1132 // If the register was not expanded, promote or copy the value,
1134 for (unsigned i = 0; i != NumParts; ++i)
1135 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1136 } else if (NumParts > 0) {
1137 // If the intermediate type was expanded, split each the value into
1139 assert(NumParts % NumIntermediates == 0 &&
1140 "Must expand into a divisible number of parts!");
1141 unsigned Factor = NumParts / NumIntermediates;
1142 for (unsigned i = 0; i != NumIntermediates; ++i)
1143 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1148 SDOperand SelectionDAGLowering::getValue(const Value *V) {
1149 SDOperand &N = NodeMap[V];
1150 if (N.Val) return N;
1152 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1153 MVT VT = TLI.getValueType(V->getType(), true);
1155 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1156 return N = DAG.getConstant(CI->getValue(), VT);
1158 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1159 return N = DAG.getGlobalAddress(GV, VT);
1161 if (isa<ConstantPointerNull>(C))
1162 return N = DAG.getConstant(0, TLI.getPointerTy());
1164 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1165 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1167 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1168 !V->getType()->isAggregateType())
1169 return N = DAG.getNode(ISD::UNDEF, VT);
1171 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1172 visit(CE->getOpcode(), *CE);
1173 SDOperand N1 = NodeMap[V];
1174 assert(N1.Val && "visit didn't populate the ValueMap!");
1178 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1179 SmallVector<SDOperand, 4> Constants;
1180 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1182 SDNode *Val = getValue(*OI).Val;
1183 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1184 Constants.push_back(SDOperand(Val, i));
1186 return DAG.getMergeValues(&Constants[0], Constants.size());
1189 if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) {
1190 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1191 "Unknown array constant!");
1192 unsigned NumElts = ATy->getNumElements();
1194 return SDOperand(); // empty array
1195 MVT EltVT = TLI.getValueType(ATy->getElementType());
1196 SmallVector<SDOperand, 4> Constants(NumElts);
1197 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1198 if (isa<UndefValue>(C))
1199 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1200 else if (EltVT.isFloatingPoint())
1201 Constants[i] = DAG.getConstantFP(0, EltVT);
1203 Constants[i] = DAG.getConstant(0, EltVT);
1205 return DAG.getMergeValues(&Constants[0], Constants.size());
1208 if (const StructType *STy = dyn_cast<StructType>(C->getType())) {
1209 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1210 "Unknown struct constant!");
1211 unsigned NumElts = STy->getNumElements();
1213 return SDOperand(); // empty struct
1214 SmallVector<SDOperand, 4> Constants(NumElts);
1215 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1216 MVT EltVT = TLI.getValueType(STy->getElementType(i));
1217 if (isa<UndefValue>(C))
1218 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1219 else if (EltVT.isFloatingPoint())
1220 Constants[i] = DAG.getConstantFP(0, EltVT);
1222 Constants[i] = DAG.getConstant(0, EltVT);
1224 return DAG.getMergeValues(&Constants[0], Constants.size());
1227 const VectorType *VecTy = cast<VectorType>(V->getType());
1228 unsigned NumElements = VecTy->getNumElements();
1230 // Now that we know the number and type of the elements, get that number of
1231 // elements into the Ops array based on what kind of constant it is.
1232 SmallVector<SDOperand, 16> Ops;
1233 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1234 for (unsigned i = 0; i != NumElements; ++i)
1235 Ops.push_back(getValue(CP->getOperand(i)));
1237 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1238 "Unknown vector constant!");
1239 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1242 if (isa<UndefValue>(C))
1243 Op = DAG.getNode(ISD::UNDEF, EltVT);
1244 else if (EltVT.isFloatingPoint())
1245 Op = DAG.getConstantFP(0, EltVT);
1247 Op = DAG.getConstant(0, EltVT);
1248 Ops.assign(NumElements, Op);
1251 // Create a BUILD_VECTOR node.
1252 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1255 // If this is a static alloca, generate it as the frameindex instead of
1257 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1258 std::map<const AllocaInst*, int>::iterator SI =
1259 FuncInfo.StaticAllocaMap.find(AI);
1260 if (SI != FuncInfo.StaticAllocaMap.end())
1261 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1264 unsigned InReg = FuncInfo.ValueMap[V];
1265 assert(InReg && "Value not in map!");
1267 RegsForValue RFV(TLI, InReg, V->getType());
1268 SDOperand Chain = DAG.getEntryNode();
1269 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1273 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1274 if (I.getNumOperands() == 0) {
1275 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1279 SmallVector<SDOperand, 8> NewValues;
1280 NewValues.push_back(getControlRoot());
1281 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1282 SDOperand RetOp = getValue(I.getOperand(i));
1284 SmallVector<MVT, 4> ValueVTs;
1285 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1286 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1287 MVT VT = ValueVTs[j];
1289 // FIXME: C calling convention requires the return type to be promoted to
1290 // at least 32-bit. But this is not necessary for non-C calling conventions.
1291 if (VT.isInteger()) {
1292 MVT MinVT = TLI.getRegisterType(MVT::i32);
1293 if (VT.bitsLT(MinVT))
1297 unsigned NumParts = TLI.getNumRegisters(VT);
1298 MVT PartVT = TLI.getRegisterType(VT);
1299 SmallVector<SDOperand, 4> Parts(NumParts);
1300 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1302 const Function *F = I.getParent()->getParent();
1303 if (F->paramHasAttr(0, ParamAttr::SExt))
1304 ExtendKind = ISD::SIGN_EXTEND;
1305 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1306 ExtendKind = ISD::ZERO_EXTEND;
1308 getCopyToParts(DAG, SDOperand(RetOp.Val, RetOp.ResNo + j),
1309 &Parts[0], NumParts, PartVT, ExtendKind);
1311 for (unsigned i = 0; i < NumParts; ++i) {
1312 NewValues.push_back(Parts[i]);
1313 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1317 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1318 &NewValues[0], NewValues.size()));
1321 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1322 /// the current basic block, add it to ValueMap now so that we'll get a
1324 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1325 // No need to export constants.
1326 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1328 // Already exported?
1329 if (FuncInfo.isExportedInst(V)) return;
1331 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1332 CopyValueToVirtualRegister(V, Reg);
1335 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1336 const BasicBlock *FromBB) {
1337 // The operands of the setcc have to be in this block. We don't know
1338 // how to export them from some other block.
1339 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1340 // Can export from current BB.
1341 if (VI->getParent() == FromBB)
1344 // Is already exported, noop.
1345 return FuncInfo.isExportedInst(V);
1348 // If this is an argument, we can export it if the BB is the entry block or
1349 // if it is already exported.
1350 if (isa<Argument>(V)) {
1351 if (FromBB == &FromBB->getParent()->getEntryBlock())
1354 // Otherwise, can only export this if it is already exported.
1355 return FuncInfo.isExportedInst(V);
1358 // Otherwise, constants can always be exported.
1362 static bool InBlock(const Value *V, const BasicBlock *BB) {
1363 if (const Instruction *I = dyn_cast<Instruction>(V))
1364 return I->getParent() == BB;
1368 /// FindMergedConditions - If Cond is an expression like
1369 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1370 MachineBasicBlock *TBB,
1371 MachineBasicBlock *FBB,
1372 MachineBasicBlock *CurBB,
1374 // If this node is not part of the or/and tree, emit it as a branch.
1375 Instruction *BOp = dyn_cast<Instruction>(Cond);
1377 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1378 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1379 BOp->getParent() != CurBB->getBasicBlock() ||
1380 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1381 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1382 const BasicBlock *BB = CurBB->getBasicBlock();
1384 // If the leaf of the tree is a comparison, merge the condition into
1386 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1387 // The operands of the cmp have to be in this block. We don't know
1388 // how to export them from some other block. If this is the first block
1389 // of the sequence, no exporting is needed.
1391 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1392 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1393 BOp = cast<Instruction>(Cond);
1394 ISD::CondCode Condition;
1395 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1396 switch (IC->getPredicate()) {
1397 default: assert(0 && "Unknown icmp predicate opcode!");
1398 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1399 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1400 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1401 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1402 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1403 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1404 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1405 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1406 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1407 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1409 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1410 ISD::CondCode FPC, FOC;
1411 switch (FC->getPredicate()) {
1412 default: assert(0 && "Unknown fcmp predicate opcode!");
1413 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1414 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1415 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1416 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1417 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1418 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1419 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1420 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1421 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1422 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1423 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1424 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1425 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1426 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1427 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1428 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1430 if (FiniteOnlyFPMath())
1435 Condition = ISD::SETEQ; // silence warning.
1436 assert(0 && "Unknown compare instruction");
1439 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1440 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1441 SwitchCases.push_back(CB);
1445 // Create a CaseBlock record representing this branch.
1446 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1447 NULL, TBB, FBB, CurBB);
1448 SwitchCases.push_back(CB);
1453 // Create TmpBB after CurBB.
1454 MachineFunction::iterator BBI = CurBB;
1455 MachineFunction &MF = DAG.getMachineFunction();
1456 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1457 CurBB->getParent()->insert(++BBI, TmpBB);
1459 if (Opc == Instruction::Or) {
1460 // Codegen X | Y as:
1468 // Emit the LHS condition.
1469 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1471 // Emit the RHS condition into TmpBB.
1472 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1474 assert(Opc == Instruction::And && "Unknown merge op!");
1475 // Codegen X & Y as:
1482 // This requires creation of TmpBB after CurBB.
1484 // Emit the LHS condition.
1485 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1487 // Emit the RHS condition into TmpBB.
1488 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1492 /// If the set of cases should be emitted as a series of branches, return true.
1493 /// If we should emit this as a bunch of and/or'd together conditions, return
1496 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1497 if (Cases.size() != 2) return true;
1499 // If this is two comparisons of the same values or'd or and'd together, they
1500 // will get folded into a single comparison, so don't emit two blocks.
1501 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1502 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1503 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1504 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1511 void SelectionDAGLowering::visitBr(BranchInst &I) {
1512 // Update machine-CFG edges.
1513 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1515 // Figure out which block is immediately after the current one.
1516 MachineBasicBlock *NextBlock = 0;
1517 MachineFunction::iterator BBI = CurMBB;
1518 if (++BBI != CurMBB->getParent()->end())
1521 if (I.isUnconditional()) {
1522 // Update machine-CFG edges.
1523 CurMBB->addSuccessor(Succ0MBB);
1525 // If this is not a fall-through branch, emit the branch.
1526 if (Succ0MBB != NextBlock)
1527 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1528 DAG.getBasicBlock(Succ0MBB)));
1532 // If this condition is one of the special cases we handle, do special stuff
1534 Value *CondVal = I.getCondition();
1535 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1537 // If this is a series of conditions that are or'd or and'd together, emit
1538 // this as a sequence of branches instead of setcc's with and/or operations.
1539 // For example, instead of something like:
1552 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1553 if (BOp->hasOneUse() &&
1554 (BOp->getOpcode() == Instruction::And ||
1555 BOp->getOpcode() == Instruction::Or)) {
1556 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1557 // If the compares in later blocks need to use values not currently
1558 // exported from this block, export them now. This block should always
1559 // be the first entry.
1560 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1562 // Allow some cases to be rejected.
1563 if (ShouldEmitAsBranches(SwitchCases)) {
1564 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1565 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1566 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1569 // Emit the branch for this block.
1570 visitSwitchCase(SwitchCases[0]);
1571 SwitchCases.erase(SwitchCases.begin());
1575 // Okay, we decided not to do this, remove any inserted MBB's and clear
1577 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1578 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1580 SwitchCases.clear();
1584 // Create a CaseBlock record representing this branch.
1585 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1586 NULL, Succ0MBB, Succ1MBB, CurMBB);
1587 // Use visitSwitchCase to actually insert the fast branch sequence for this
1589 visitSwitchCase(CB);
1592 /// visitSwitchCase - Emits the necessary code to represent a single node in
1593 /// the binary search tree resulting from lowering a switch instruction.
1594 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1596 SDOperand CondLHS = getValue(CB.CmpLHS);
1598 // Build the setcc now.
1599 if (CB.CmpMHS == NULL) {
1600 // Fold "(X == true)" to X and "(X == false)" to !X to
1601 // handle common cases produced by branch lowering.
1602 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1604 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1605 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1606 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1608 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1610 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1612 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1613 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1615 SDOperand CmpOp = getValue(CB.CmpMHS);
1616 MVT VT = CmpOp.getValueType();
1618 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1619 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1621 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1622 Cond = DAG.getSetCC(MVT::i1, SUB,
1623 DAG.getConstant(High-Low, VT), ISD::SETULE);
1627 // Update successor info
1628 CurMBB->addSuccessor(CB.TrueBB);
1629 CurMBB->addSuccessor(CB.FalseBB);
1631 // Set NextBlock to be the MBB immediately after the current one, if any.
1632 // This is used to avoid emitting unnecessary branches to the next block.
1633 MachineBasicBlock *NextBlock = 0;
1634 MachineFunction::iterator BBI = CurMBB;
1635 if (++BBI != CurMBB->getParent()->end())
1638 // If the lhs block is the next block, invert the condition so that we can
1639 // fall through to the lhs instead of the rhs block.
1640 if (CB.TrueBB == NextBlock) {
1641 std::swap(CB.TrueBB, CB.FalseBB);
1642 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1643 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1645 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1646 DAG.getBasicBlock(CB.TrueBB));
1647 if (CB.FalseBB == NextBlock)
1648 DAG.setRoot(BrCond);
1650 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1651 DAG.getBasicBlock(CB.FalseBB)));
1654 /// visitJumpTable - Emit JumpTable node in the current MBB
1655 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1656 // Emit the code for the jump table
1657 assert(JT.Reg != -1U && "Should lower JT Header first!");
1658 MVT PTy = TLI.getPointerTy();
1659 SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1660 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1661 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1666 /// visitJumpTableHeader - This function emits necessary code to produce index
1667 /// in the JumpTable from switch case.
1668 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1669 SelectionDAGISel::JumpTableHeader &JTH) {
1670 // Subtract the lowest switch case value from the value being switched on
1671 // and conditional branch to default mbb if the result is greater than the
1672 // difference between smallest and largest cases.
1673 SDOperand SwitchOp = getValue(JTH.SValue);
1674 MVT VT = SwitchOp.getValueType();
1675 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1676 DAG.getConstant(JTH.First, VT));
1678 // The SDNode we just created, which holds the value being switched on
1679 // minus the the smallest case value, needs to be copied to a virtual
1680 // register so it can be used as an index into the jump table in a
1681 // subsequent basic block. This value may be smaller or larger than the
1682 // target's pointer type, and therefore require extension or truncating.
1683 if (VT.bitsGT(TLI.getPointerTy()))
1684 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1686 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1688 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1689 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1690 JT.Reg = JumpTableReg;
1692 // Emit the range check for the jump table, and branch to the default
1693 // block for the switch statement if the value being switched on exceeds
1694 // the largest case in the switch.
1695 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1696 DAG.getConstant(JTH.Last-JTH.First,VT),
1699 // Set NextBlock to be the MBB immediately after the current one, if any.
1700 // This is used to avoid emitting unnecessary branches to the next block.
1701 MachineBasicBlock *NextBlock = 0;
1702 MachineFunction::iterator BBI = CurMBB;
1703 if (++BBI != CurMBB->getParent()->end())
1706 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1707 DAG.getBasicBlock(JT.Default));
1709 if (JT.MBB == NextBlock)
1710 DAG.setRoot(BrCond);
1712 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1713 DAG.getBasicBlock(JT.MBB)));
1718 /// visitBitTestHeader - This function emits necessary code to produce value
1719 /// suitable for "bit tests"
1720 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1721 // Subtract the minimum value
1722 SDOperand SwitchOp = getValue(B.SValue);
1723 MVT VT = SwitchOp.getValueType();
1724 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1725 DAG.getConstant(B.First, VT));
1728 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1729 DAG.getConstant(B.Range, VT),
1733 if (VT.bitsGT(TLI.getShiftAmountTy()))
1734 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1736 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1738 // Make desired shift
1739 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1740 DAG.getConstant(1, TLI.getPointerTy()),
1743 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1744 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1747 // Set NextBlock to be the MBB immediately after the current one, if any.
1748 // This is used to avoid emitting unnecessary branches to the next block.
1749 MachineBasicBlock *NextBlock = 0;
1750 MachineFunction::iterator BBI = CurMBB;
1751 if (++BBI != CurMBB->getParent()->end())
1754 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1756 CurMBB->addSuccessor(B.Default);
1757 CurMBB->addSuccessor(MBB);
1759 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1760 DAG.getBasicBlock(B.Default));
1762 if (MBB == NextBlock)
1763 DAG.setRoot(BrRange);
1765 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1766 DAG.getBasicBlock(MBB)));
1771 /// visitBitTestCase - this function produces one "bit test"
1772 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1774 SelectionDAGISel::BitTestCase &B) {
1775 // Emit bit tests and jumps
1776 SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1777 TLI.getPointerTy());
1779 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1780 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1781 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1782 DAG.getConstant(0, TLI.getPointerTy()),
1785 CurMBB->addSuccessor(B.TargetBB);
1786 CurMBB->addSuccessor(NextMBB);
1788 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1789 AndCmp, DAG.getBasicBlock(B.TargetBB));
1791 // Set NextBlock to be the MBB immediately after the current one, if any.
1792 // This is used to avoid emitting unnecessary branches to the next block.
1793 MachineBasicBlock *NextBlock = 0;
1794 MachineFunction::iterator BBI = CurMBB;
1795 if (++BBI != CurMBB->getParent()->end())
1798 if (NextMBB == NextBlock)
1801 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1802 DAG.getBasicBlock(NextMBB)));
1807 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1808 // Retrieve successors.
1809 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1810 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1812 if (isa<InlineAsm>(I.getCalledValue()))
1815 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1817 // If the value of the invoke is used outside of its defining block, make it
1818 // available as a virtual register.
1819 if (!I.use_empty()) {
1820 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1821 if (VMI != FuncInfo.ValueMap.end())
1822 CopyValueToVirtualRegister(&I, VMI->second);
1825 // Update successor info
1826 CurMBB->addSuccessor(Return);
1827 CurMBB->addSuccessor(LandingPad);
1829 // Drop into normal successor.
1830 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1831 DAG.getBasicBlock(Return)));
1834 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1837 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1838 /// small case ranges).
1839 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1840 CaseRecVector& WorkList,
1842 MachineBasicBlock* Default) {
1843 Case& BackCase = *(CR.Range.second-1);
1845 // Size is the number of Cases represented by this range.
1846 unsigned Size = CR.Range.second - CR.Range.first;
1850 // Get the MachineFunction which holds the current MBB. This is used when
1851 // inserting any additional MBBs necessary to represent the switch.
1852 MachineFunction *CurMF = CurMBB->getParent();
1854 // Figure out which block is immediately after the current one.
1855 MachineBasicBlock *NextBlock = 0;
1856 MachineFunction::iterator BBI = CR.CaseBB;
1858 if (++BBI != CurMBB->getParent()->end())
1861 // TODO: If any two of the cases has the same destination, and if one value
1862 // is the same as the other, but has one bit unset that the other has set,
1863 // use bit manipulation to do two compares at once. For example:
1864 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1866 // Rearrange the case blocks so that the last one falls through if possible.
1867 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1868 // The last case block won't fall through into 'NextBlock' if we emit the
1869 // branches in this order. See if rearranging a case value would help.
1870 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1871 if (I->BB == NextBlock) {
1872 std::swap(*I, BackCase);
1878 // Create a CaseBlock record representing a conditional branch to
1879 // the Case's target mbb if the value being switched on SV is equal
1881 MachineBasicBlock *CurBlock = CR.CaseBB;
1882 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1883 MachineBasicBlock *FallThrough;
1885 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1886 CurMF->insert(BBI, FallThrough);
1888 // If the last case doesn't match, go to the default block.
1889 FallThrough = Default;
1892 Value *RHS, *LHS, *MHS;
1894 if (I->High == I->Low) {
1895 // This is just small small case range :) containing exactly 1 case
1897 LHS = SV; RHS = I->High; MHS = NULL;
1900 LHS = I->Low; MHS = SV; RHS = I->High;
1902 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1903 I->BB, FallThrough, CurBlock);
1905 // If emitting the first comparison, just call visitSwitchCase to emit the
1906 // code into the current block. Otherwise, push the CaseBlock onto the
1907 // vector to be later processed by SDISel, and insert the node's MBB
1908 // before the next MBB.
1909 if (CurBlock == CurMBB)
1910 visitSwitchCase(CB);
1912 SwitchCases.push_back(CB);
1914 CurBlock = FallThrough;
1920 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1921 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1922 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1925 /// handleJTSwitchCase - Emit jumptable for current switch case range
1926 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1927 CaseRecVector& WorkList,
1929 MachineBasicBlock* Default) {
1930 Case& FrontCase = *CR.Range.first;
1931 Case& BackCase = *(CR.Range.second-1);
1933 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1934 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1937 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1941 if (!areJTsAllowed(TLI) || TSize <= 3)
1944 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1948 DOUT << "Lowering jump table\n"
1949 << "First entry: " << First << ". Last entry: " << Last << "\n"
1950 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1952 // Get the MachineFunction which holds the current MBB. This is used when
1953 // inserting any additional MBBs necessary to represent the switch.
1954 MachineFunction *CurMF = CurMBB->getParent();
1956 // Figure out which block is immediately after the current one.
1957 MachineBasicBlock *NextBlock = 0;
1958 MachineFunction::iterator BBI = CR.CaseBB;
1960 if (++BBI != CurMBB->getParent()->end())
1963 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1965 // Create a new basic block to hold the code for loading the address
1966 // of the jump table, and jumping to it. Update successor information;
1967 // we will either branch to the default case for the switch, or the jump
1969 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1970 CurMF->insert(BBI, JumpTableBB);
1971 CR.CaseBB->addSuccessor(Default);
1972 CR.CaseBB->addSuccessor(JumpTableBB);
1974 // Build a vector of destination BBs, corresponding to each target
1975 // of the jump table. If the value of the jump table slot corresponds to
1976 // a case statement, push the case's BB onto the vector, otherwise, push
1978 std::vector<MachineBasicBlock*> DestBBs;
1979 int64_t TEI = First;
1980 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1981 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1982 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1984 if ((Low <= TEI) && (TEI <= High)) {
1985 DestBBs.push_back(I->BB);
1989 DestBBs.push_back(Default);
1993 // Update successor info. Add one edge to each unique successor.
1994 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1995 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1996 E = DestBBs.end(); I != E; ++I) {
1997 if (!SuccsHandled[(*I)->getNumber()]) {
1998 SuccsHandled[(*I)->getNumber()] = true;
1999 JumpTableBB->addSuccessor(*I);
2003 // Create a jump table index for this jump table, or return an existing
2005 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
2007 // Set the jump table information so that we can codegen it as a second
2008 // MachineBasicBlock
2009 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
2010 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
2011 (CR.CaseBB == CurMBB));
2012 if (CR.CaseBB == CurMBB)
2013 visitJumpTableHeader(JT, JTH);
2015 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2020 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2022 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2023 CaseRecVector& WorkList,
2025 MachineBasicBlock* Default) {
2026 // Get the MachineFunction which holds the current MBB. This is used when
2027 // inserting any additional MBBs necessary to represent the switch.
2028 MachineFunction *CurMF = CurMBB->getParent();
2030 // Figure out which block is immediately after the current one.
2031 MachineBasicBlock *NextBlock = 0;
2032 MachineFunction::iterator BBI = CR.CaseBB;
2034 if (++BBI != CurMBB->getParent()->end())
2037 Case& FrontCase = *CR.Range.first;
2038 Case& BackCase = *(CR.Range.second-1);
2039 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2041 // Size is the number of Cases represented by this range.
2042 unsigned Size = CR.Range.second - CR.Range.first;
2044 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2045 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2047 CaseItr Pivot = CR.Range.first + Size/2;
2049 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2050 // (heuristically) allow us to emit JumpTable's later.
2052 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2056 uint64_t LSize = FrontCase.size();
2057 uint64_t RSize = TSize-LSize;
2058 DOUT << "Selecting best pivot: \n"
2059 << "First: " << First << ", Last: " << Last <<"\n"
2060 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2061 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2063 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2064 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2065 assert((RBegin-LEnd>=1) && "Invalid case distance");
2066 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2067 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2068 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2069 // Should always split in some non-trivial place
2071 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2072 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2073 << "Metric: " << Metric << "\n";
2074 if (FMetric < Metric) {
2077 DOUT << "Current metric set to: " << FMetric << "\n";
2083 if (areJTsAllowed(TLI)) {
2084 // If our case is dense we *really* should handle it earlier!
2085 assert((FMetric > 0) && "Should handle dense range earlier!");
2087 Pivot = CR.Range.first + Size/2;
2090 CaseRange LHSR(CR.Range.first, Pivot);
2091 CaseRange RHSR(Pivot, CR.Range.second);
2092 Constant *C = Pivot->Low;
2093 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2095 // We know that we branch to the LHS if the Value being switched on is
2096 // less than the Pivot value, C. We use this to optimize our binary
2097 // tree a bit, by recognizing that if SV is greater than or equal to the
2098 // LHS's Case Value, and that Case Value is exactly one less than the
2099 // Pivot's Value, then we can branch directly to the LHS's Target,
2100 // rather than creating a leaf node for it.
2101 if ((LHSR.second - LHSR.first) == 1 &&
2102 LHSR.first->High == CR.GE &&
2103 cast<ConstantInt>(C)->getSExtValue() ==
2104 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2105 TrueBB = LHSR.first->BB;
2107 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2108 CurMF->insert(BBI, TrueBB);
2109 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2112 // Similar to the optimization above, if the Value being switched on is
2113 // known to be less than the Constant CR.LT, and the current Case Value
2114 // is CR.LT - 1, then we can branch directly to the target block for
2115 // the current Case Value, rather than emitting a RHS leaf node for it.
2116 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2117 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2118 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2119 FalseBB = RHSR.first->BB;
2121 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2122 CurMF->insert(BBI, FalseBB);
2123 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2126 // Create a CaseBlock record representing a conditional branch to
2127 // the LHS node if the value being switched on SV is less than C.
2128 // Otherwise, branch to LHS.
2129 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2130 TrueBB, FalseBB, CR.CaseBB);
2132 if (CR.CaseBB == CurMBB)
2133 visitSwitchCase(CB);
2135 SwitchCases.push_back(CB);
2140 /// handleBitTestsSwitchCase - if current case range has few destination and
2141 /// range span less, than machine word bitwidth, encode case range into series
2142 /// of masks and emit bit tests with these masks.
2143 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2144 CaseRecVector& WorkList,
2146 MachineBasicBlock* Default){
2147 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2149 Case& FrontCase = *CR.Range.first;
2150 Case& BackCase = *(CR.Range.second-1);
2152 // Get the MachineFunction which holds the current MBB. This is used when
2153 // inserting any additional MBBs necessary to represent the switch.
2154 MachineFunction *CurMF = CurMBB->getParent();
2156 unsigned numCmps = 0;
2157 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2159 // Single case counts one, case range - two.
2160 if (I->Low == I->High)
2166 // Count unique destinations
2167 SmallSet<MachineBasicBlock*, 4> Dests;
2168 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2169 Dests.insert(I->BB);
2170 if (Dests.size() > 3)
2171 // Don't bother the code below, if there are too much unique destinations
2174 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2175 << "Total number of comparisons: " << numCmps << "\n";
2177 // Compute span of values.
2178 Constant* minValue = FrontCase.Low;
2179 Constant* maxValue = BackCase.High;
2180 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2181 cast<ConstantInt>(minValue)->getSExtValue();
2182 DOUT << "Compare range: " << range << "\n"
2183 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2184 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2186 if (range>=IntPtrBits ||
2187 (!(Dests.size() == 1 && numCmps >= 3) &&
2188 !(Dests.size() == 2 && numCmps >= 5) &&
2189 !(Dests.size() >= 3 && numCmps >= 6)))
2192 DOUT << "Emitting bit tests\n";
2193 int64_t lowBound = 0;
2195 // Optimize the case where all the case values fit in a
2196 // word without having to subtract minValue. In this case,
2197 // we can optimize away the subtraction.
2198 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2199 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2200 range = cast<ConstantInt>(maxValue)->getSExtValue();
2202 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2205 CaseBitsVector CasesBits;
2206 unsigned i, count = 0;
2208 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2209 MachineBasicBlock* Dest = I->BB;
2210 for (i = 0; i < count; ++i)
2211 if (Dest == CasesBits[i].BB)
2215 assert((count < 3) && "Too much destinations to test!");
2216 CasesBits.push_back(CaseBits(0, Dest, 0));
2220 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2221 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2223 for (uint64_t j = lo; j <= hi; j++) {
2224 CasesBits[i].Mask |= 1ULL << j;
2225 CasesBits[i].Bits++;
2229 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2231 SelectionDAGISel::BitTestInfo BTC;
2233 // Figure out which block is immediately after the current one.
2234 MachineFunction::iterator BBI = CR.CaseBB;
2237 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2240 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2241 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2242 << ", BB: " << CasesBits[i].BB << "\n";
2244 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2245 CurMF->insert(BBI, CaseBB);
2246 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2251 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2252 -1U, (CR.CaseBB == CurMBB),
2253 CR.CaseBB, Default, BTC);
2255 if (CR.CaseBB == CurMBB)
2256 visitBitTestHeader(BTB);
2258 BitTestCases.push_back(BTB);
2264 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2265 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2266 const SwitchInst& SI) {
2267 unsigned numCmps = 0;
2269 // Start with "simple" cases
2270 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2271 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2272 Cases.push_back(Case(SI.getSuccessorValue(i),
2273 SI.getSuccessorValue(i),
2276 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2278 // Merge case into clusters
2279 if (Cases.size()>=2)
2280 // Must recompute end() each iteration because it may be
2281 // invalidated by erase if we hold on to it
2282 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2283 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2284 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2285 MachineBasicBlock* nextBB = J->BB;
2286 MachineBasicBlock* currentBB = I->BB;
2288 // If the two neighboring cases go to the same destination, merge them
2289 // into a single case.
2290 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2298 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2299 if (I->Low != I->High)
2300 // A range counts double, since it requires two compares.
2307 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2308 // Figure out which block is immediately after the current one.
2309 MachineBasicBlock *NextBlock = 0;
2310 MachineFunction::iterator BBI = CurMBB;
2312 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2314 // If there is only the default destination, branch to it if it is not the
2315 // next basic block. Otherwise, just fall through.
2316 if (SI.getNumOperands() == 2) {
2317 // Update machine-CFG edges.
2319 // If this is not a fall-through branch, emit the branch.
2320 CurMBB->addSuccessor(Default);
2321 if (Default != NextBlock)
2322 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2323 DAG.getBasicBlock(Default)));
2328 // If there are any non-default case statements, create a vector of Cases
2329 // representing each one, and sort the vector so that we can efficiently
2330 // create a binary search tree from them.
2332 unsigned numCmps = Clusterify(Cases, SI);
2333 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2334 << ". Total compares: " << numCmps << "\n";
2336 // Get the Value to be switched on and default basic blocks, which will be
2337 // inserted into CaseBlock records, representing basic blocks in the binary
2339 Value *SV = SI.getOperand(0);
2341 // Push the initial CaseRec onto the worklist
2342 CaseRecVector WorkList;
2343 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2345 while (!WorkList.empty()) {
2346 // Grab a record representing a case range to process off the worklist
2347 CaseRec CR = WorkList.back();
2348 WorkList.pop_back();
2350 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2353 // If the range has few cases (two or less) emit a series of specific
2355 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2358 // If the switch has more than 5 blocks, and at least 40% dense, and the
2359 // target supports indirect branches, then emit a jump table rather than
2360 // lowering the switch to a binary tree of conditional branches.
2361 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2364 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2365 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2366 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2371 void SelectionDAGLowering::visitSub(User &I) {
2372 // -0.0 - X --> fneg
2373 const Type *Ty = I.getType();
2374 if (isa<VectorType>(Ty)) {
2375 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2376 const VectorType *DestTy = cast<VectorType>(I.getType());
2377 const Type *ElTy = DestTy->getElementType();
2378 if (ElTy->isFloatingPoint()) {
2379 unsigned VL = DestTy->getNumElements();
2380 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2381 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2383 SDOperand Op2 = getValue(I.getOperand(1));
2384 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2390 if (Ty->isFloatingPoint()) {
2391 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2392 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2393 SDOperand Op2 = getValue(I.getOperand(1));
2394 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2399 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2402 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2403 SDOperand Op1 = getValue(I.getOperand(0));
2404 SDOperand Op2 = getValue(I.getOperand(1));
2406 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2409 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2410 SDOperand Op1 = getValue(I.getOperand(0));
2411 SDOperand Op2 = getValue(I.getOperand(1));
2413 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2414 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2415 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2416 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2418 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2421 void SelectionDAGLowering::visitICmp(User &I) {
2422 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2423 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2424 predicate = IC->getPredicate();
2425 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2426 predicate = ICmpInst::Predicate(IC->getPredicate());
2427 SDOperand Op1 = getValue(I.getOperand(0));
2428 SDOperand Op2 = getValue(I.getOperand(1));
2429 ISD::CondCode Opcode;
2430 switch (predicate) {
2431 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2432 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2433 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2434 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2435 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2436 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2437 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2438 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2439 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2440 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2442 assert(!"Invalid ICmp predicate value");
2443 Opcode = ISD::SETEQ;
2446 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2449 void SelectionDAGLowering::visitFCmp(User &I) {
2450 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2451 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2452 predicate = FC->getPredicate();
2453 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2454 predicate = FCmpInst::Predicate(FC->getPredicate());
2455 SDOperand Op1 = getValue(I.getOperand(0));
2456 SDOperand Op2 = getValue(I.getOperand(1));
2457 ISD::CondCode Condition, FOC, FPC;
2458 switch (predicate) {
2459 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2460 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2461 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2462 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2463 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2464 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2465 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2466 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2467 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2468 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2469 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2470 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2471 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2472 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2473 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2474 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2476 assert(!"Invalid FCmp predicate value");
2477 FOC = FPC = ISD::SETFALSE;
2480 if (FiniteOnlyFPMath())
2484 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2487 void SelectionDAGLowering::visitVICmp(User &I) {
2488 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2489 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2490 predicate = IC->getPredicate();
2491 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2492 predicate = ICmpInst::Predicate(IC->getPredicate());
2493 SDOperand Op1 = getValue(I.getOperand(0));
2494 SDOperand Op2 = getValue(I.getOperand(1));
2495 ISD::CondCode Opcode;
2496 switch (predicate) {
2497 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2498 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2499 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2500 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2501 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2502 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2503 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2504 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2505 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2506 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2508 assert(!"Invalid ICmp predicate value");
2509 Opcode = ISD::SETEQ;
2512 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2515 void SelectionDAGLowering::visitVFCmp(User &I) {
2516 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2517 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2518 predicate = FC->getPredicate();
2519 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2520 predicate = FCmpInst::Predicate(FC->getPredicate());
2521 SDOperand Op1 = getValue(I.getOperand(0));
2522 SDOperand Op2 = getValue(I.getOperand(1));
2523 ISD::CondCode Condition, FOC, FPC;
2524 switch (predicate) {
2525 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2526 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2527 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2528 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2529 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2530 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2531 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2532 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2533 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2534 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2535 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2536 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2537 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2538 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2539 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2540 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2542 assert(!"Invalid VFCmp predicate value");
2543 FOC = FPC = ISD::SETFALSE;
2546 if (FiniteOnlyFPMath())
2551 MVT DestVT = TLI.getValueType(I.getType());
2553 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2556 void SelectionDAGLowering::visitSelect(User &I) {
2557 SDOperand Cond = getValue(I.getOperand(0));
2558 SDOperand TrueVal = getValue(I.getOperand(1));
2559 SDOperand FalseVal = getValue(I.getOperand(2));
2560 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2561 TrueVal, FalseVal));
2565 void SelectionDAGLowering::visitTrunc(User &I) {
2566 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2567 SDOperand N = getValue(I.getOperand(0));
2568 MVT DestVT = TLI.getValueType(I.getType());
2569 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2572 void SelectionDAGLowering::visitZExt(User &I) {
2573 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2574 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2575 SDOperand N = getValue(I.getOperand(0));
2576 MVT DestVT = TLI.getValueType(I.getType());
2577 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2580 void SelectionDAGLowering::visitSExt(User &I) {
2581 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2582 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2583 SDOperand N = getValue(I.getOperand(0));
2584 MVT DestVT = TLI.getValueType(I.getType());
2585 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2588 void SelectionDAGLowering::visitFPTrunc(User &I) {
2589 // FPTrunc is never a no-op cast, no need to check
2590 SDOperand N = getValue(I.getOperand(0));
2591 MVT DestVT = TLI.getValueType(I.getType());
2592 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2595 void SelectionDAGLowering::visitFPExt(User &I){
2596 // FPTrunc is never a no-op cast, no need to check
2597 SDOperand N = getValue(I.getOperand(0));
2598 MVT DestVT = TLI.getValueType(I.getType());
2599 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2602 void SelectionDAGLowering::visitFPToUI(User &I) {
2603 // FPToUI is never a no-op cast, no need to check
2604 SDOperand N = getValue(I.getOperand(0));
2605 MVT DestVT = TLI.getValueType(I.getType());
2606 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2609 void SelectionDAGLowering::visitFPToSI(User &I) {
2610 // FPToSI is never a no-op cast, no need to check
2611 SDOperand N = getValue(I.getOperand(0));
2612 MVT DestVT = TLI.getValueType(I.getType());
2613 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2616 void SelectionDAGLowering::visitUIToFP(User &I) {
2617 // UIToFP is never a no-op cast, no need to check
2618 SDOperand N = getValue(I.getOperand(0));
2619 MVT DestVT = TLI.getValueType(I.getType());
2620 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2623 void SelectionDAGLowering::visitSIToFP(User &I){
2624 // UIToFP is never a no-op cast, no need to check
2625 SDOperand N = getValue(I.getOperand(0));
2626 MVT DestVT = TLI.getValueType(I.getType());
2627 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2630 void SelectionDAGLowering::visitPtrToInt(User &I) {
2631 // What to do depends on the size of the integer and the size of the pointer.
2632 // We can either truncate, zero extend, or no-op, accordingly.
2633 SDOperand N = getValue(I.getOperand(0));
2634 MVT SrcVT = N.getValueType();
2635 MVT DestVT = TLI.getValueType(I.getType());
2637 if (DestVT.bitsLT(SrcVT))
2638 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2640 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2641 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2642 setValue(&I, Result);
2645 void SelectionDAGLowering::visitIntToPtr(User &I) {
2646 // What to do depends on the size of the integer and the size of the pointer.
2647 // We can either truncate, zero extend, or no-op, accordingly.
2648 SDOperand N = getValue(I.getOperand(0));
2649 MVT SrcVT = N.getValueType();
2650 MVT DestVT = TLI.getValueType(I.getType());
2651 if (DestVT.bitsLT(SrcVT))
2652 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2654 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2655 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2658 void SelectionDAGLowering::visitBitCast(User &I) {
2659 SDOperand N = getValue(I.getOperand(0));
2660 MVT DestVT = TLI.getValueType(I.getType());
2662 // BitCast assures us that source and destination are the same size so this
2663 // is either a BIT_CONVERT or a no-op.
2664 if (DestVT != N.getValueType())
2665 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2667 setValue(&I, N); // noop cast.
2670 void SelectionDAGLowering::visitInsertElement(User &I) {
2671 SDOperand InVec = getValue(I.getOperand(0));
2672 SDOperand InVal = getValue(I.getOperand(1));
2673 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2674 getValue(I.getOperand(2)));
2676 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2677 TLI.getValueType(I.getType()),
2678 InVec, InVal, InIdx));
2681 void SelectionDAGLowering::visitExtractElement(User &I) {
2682 SDOperand InVec = getValue(I.getOperand(0));
2683 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2684 getValue(I.getOperand(1)));
2685 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2686 TLI.getValueType(I.getType()), InVec, InIdx));
2689 void SelectionDAGLowering::visitShuffleVector(User &I) {
2690 SDOperand V1 = getValue(I.getOperand(0));
2691 SDOperand V2 = getValue(I.getOperand(1));
2692 SDOperand Mask = getValue(I.getOperand(2));
2694 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2695 TLI.getValueType(I.getType()),
2699 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2700 const Value *Op0 = I.getOperand(0);
2701 const Value *Op1 = I.getOperand(1);
2702 const Type *AggTy = I.getType();
2703 const Type *ValTy = Op1->getType();
2704 bool IntoUndef = isa<UndefValue>(Op0);
2705 bool FromUndef = isa<UndefValue>(Op1);
2707 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2708 I.idx_begin(), I.idx_end());
2710 SmallVector<MVT, 4> AggValueVTs;
2711 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2712 SmallVector<MVT, 4> ValValueVTs;
2713 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2715 unsigned NumAggValues = AggValueVTs.size();
2716 unsigned NumValValues = ValValueVTs.size();
2717 SmallVector<SDOperand, 4> Values(NumAggValues);
2719 SDOperand Agg = getValue(Op0);
2720 SDOperand Val = getValue(Op1);
2722 // Copy the beginning value(s) from the original aggregate.
2723 for (; i != LinearIndex; ++i)
2724 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2725 SDOperand(Agg.Val, Agg.ResNo + i);
2726 // Copy values from the inserted value(s).
2727 for (; i != LinearIndex + NumValValues; ++i)
2728 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2729 SDOperand(Val.Val, Val.ResNo + i - LinearIndex);
2730 // Copy remaining value(s) from the original aggregate.
2731 for (; i != NumAggValues; ++i)
2732 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2733 SDOperand(Agg.Val, Agg.ResNo + i);
2735 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2736 &Values[0], NumAggValues));
2739 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2740 const Value *Op0 = I.getOperand(0);
2741 const Type *AggTy = Op0->getType();
2742 const Type *ValTy = I.getType();
2743 bool OutOfUndef = isa<UndefValue>(Op0);
2745 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2746 I.idx_begin(), I.idx_end());
2748 SmallVector<MVT, 4> ValValueVTs;
2749 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2751 unsigned NumValValues = ValValueVTs.size();
2752 SmallVector<SDOperand, 4> Values(NumValValues);
2754 SDOperand Agg = getValue(Op0);
2755 // Copy out the selected value(s).
2756 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2757 Values[i - LinearIndex] =
2758 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2759 SDOperand(Agg.Val, Agg.ResNo + i);
2761 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2762 &Values[0], NumValValues));
2766 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2767 SDOperand N = getValue(I.getOperand(0));
2768 const Type *Ty = I.getOperand(0)->getType();
2770 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2773 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2774 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2777 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2778 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2779 DAG.getIntPtrConstant(Offset));
2781 Ty = StTy->getElementType(Field);
2783 Ty = cast<SequentialType>(Ty)->getElementType();
2785 // If this is a constant subscript, handle it quickly.
2786 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2787 if (CI->getZExtValue() == 0) continue;
2789 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2790 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2791 DAG.getIntPtrConstant(Offs));
2795 // N = N + Idx * ElementSize;
2796 uint64_t ElementSize = TD->getABITypeSize(Ty);
2797 SDOperand IdxN = getValue(Idx);
2799 // If the index is smaller or larger than intptr_t, truncate or extend
2801 if (IdxN.getValueType().bitsLT(N.getValueType())) {
2802 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2803 } else if (IdxN.getValueType().bitsGT(N.getValueType()))
2804 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2806 // If this is a multiply by a power of two, turn it into a shl
2807 // immediately. This is a very common case.
2808 if (isPowerOf2_64(ElementSize)) {
2809 unsigned Amt = Log2_64(ElementSize);
2810 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2811 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2812 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2816 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2817 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2818 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2824 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2825 // If this is a fixed sized alloca in the entry block of the function,
2826 // allocate it statically on the stack.
2827 if (FuncInfo.StaticAllocaMap.count(&I))
2828 return; // getValue will auto-populate this.
2830 const Type *Ty = I.getAllocatedType();
2831 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2833 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2836 SDOperand AllocSize = getValue(I.getArraySize());
2837 MVT IntPtr = TLI.getPointerTy();
2838 if (IntPtr.bitsLT(AllocSize.getValueType()))
2839 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2840 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2841 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2843 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2844 DAG.getIntPtrConstant(TySize));
2846 // Handle alignment. If the requested alignment is less than or equal to
2847 // the stack alignment, ignore it. If the size is greater than or equal to
2848 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2849 unsigned StackAlign =
2850 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2851 if (Align <= StackAlign)
2854 // Round the size of the allocation up to the stack alignment size
2855 // by add SA-1 to the size.
2856 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2857 DAG.getIntPtrConstant(StackAlign-1));
2858 // Mask out the low bits for alignment purposes.
2859 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2860 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2862 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2863 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2865 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2867 DAG.setRoot(DSA.getValue(1));
2869 // Inform the Frame Information that we have just allocated a variable-sized
2871 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2874 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2875 const Value *SV = I.getOperand(0);
2876 SDOperand Ptr = getValue(SV);
2878 const Type *Ty = I.getType();
2879 bool isVolatile = I.isVolatile();
2880 unsigned Alignment = I.getAlignment();
2882 SmallVector<MVT, 4> ValueVTs;
2883 SmallVector<uint64_t, 4> Offsets;
2884 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2885 unsigned NumValues = ValueVTs.size();
2893 // Do not serialize non-volatile loads against each other.
2894 Root = DAG.getRoot();
2897 SmallVector<SDOperand, 4> Values(NumValues);
2898 SmallVector<SDOperand, 4> Chains(NumValues);
2899 MVT PtrVT = Ptr.getValueType();
2900 for (unsigned i = 0; i != NumValues; ++i) {
2901 SDOperand L = DAG.getLoad(ValueVTs[i], Root,
2902 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2903 DAG.getConstant(Offsets[i], PtrVT)),
2905 isVolatile, Alignment);
2907 Chains[i] = L.getValue(1);
2910 SDOperand Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2911 &Chains[0], NumValues);
2915 PendingLoads.push_back(Chain);
2917 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2918 &Values[0], NumValues));
2922 void SelectionDAGLowering::visitStore(StoreInst &I) {
2923 Value *SrcV = I.getOperand(0);
2924 SDOperand Src = getValue(SrcV);
2925 Value *PtrV = I.getOperand(1);
2926 SDOperand Ptr = getValue(PtrV);
2928 SmallVector<MVT, 4> ValueVTs;
2929 SmallVector<uint64_t, 4> Offsets;
2930 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2931 unsigned NumValues = ValueVTs.size();
2935 SDOperand Root = getRoot();
2936 SmallVector<SDOperand, 4> Chains(NumValues);
2937 MVT PtrVT = Ptr.getValueType();
2938 bool isVolatile = I.isVolatile();
2939 unsigned Alignment = I.getAlignment();
2940 for (unsigned i = 0; i != NumValues; ++i)
2941 Chains[i] = DAG.getStore(Root, SDOperand(Src.Val, Src.ResNo + i),
2942 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2943 DAG.getConstant(Offsets[i], PtrVT)),
2945 isVolatile, Alignment);
2947 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2950 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2952 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2953 unsigned Intrinsic) {
2954 bool HasChain = !I.doesNotAccessMemory();
2955 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2957 // Build the operand list.
2958 SmallVector<SDOperand, 8> Ops;
2959 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2961 // We don't need to serialize loads against other loads.
2962 Ops.push_back(DAG.getRoot());
2964 Ops.push_back(getRoot());
2968 // Add the intrinsic ID as an integer operand.
2969 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2971 // Add all operands of the call to the operand list.
2972 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2973 SDOperand Op = getValue(I.getOperand(i));
2974 assert(TLI.isTypeLegal(Op.getValueType()) &&
2975 "Intrinsic uses a non-legal type?");
2979 std::vector<MVT> VTs;
2980 if (I.getType() != Type::VoidTy) {
2981 MVT VT = TLI.getValueType(I.getType());
2982 if (VT.isVector()) {
2983 const VectorType *DestTy = cast<VectorType>(I.getType());
2984 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2986 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2987 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2990 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2994 VTs.push_back(MVT::Other);
2996 const MVT *VTList = DAG.getNodeValueTypes(VTs);
3001 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
3002 &Ops[0], Ops.size());
3003 else if (I.getType() != Type::VoidTy)
3004 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
3005 &Ops[0], Ops.size());
3007 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
3008 &Ops[0], Ops.size());
3011 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
3013 PendingLoads.push_back(Chain);
3017 if (I.getType() != Type::VoidTy) {
3018 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3019 MVT VT = TLI.getValueType(PTy);
3020 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3022 setValue(&I, Result);
3026 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3027 static GlobalVariable *ExtractTypeInfo (Value *V) {
3028 V = V->stripPointerCasts();
3029 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3030 assert ((GV || isa<ConstantPointerNull>(V)) &&
3031 "TypeInfo must be a global variable or NULL");
3035 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3036 /// call, and add them to the specified machine basic block.
3037 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3038 MachineBasicBlock *MBB) {
3039 // Inform the MachineModuleInfo of the personality for this landing pad.
3040 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3041 assert(CE->getOpcode() == Instruction::BitCast &&
3042 isa<Function>(CE->getOperand(0)) &&
3043 "Personality should be a function");
3044 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3046 // Gather all the type infos for this landing pad and pass them along to
3047 // MachineModuleInfo.
3048 std::vector<GlobalVariable *> TyInfo;
3049 unsigned N = I.getNumOperands();
3051 for (unsigned i = N - 1; i > 2; --i) {
3052 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3053 unsigned FilterLength = CI->getZExtValue();
3054 unsigned FirstCatch = i + FilterLength + !FilterLength;
3055 assert (FirstCatch <= N && "Invalid filter length");
3057 if (FirstCatch < N) {
3058 TyInfo.reserve(N - FirstCatch);
3059 for (unsigned j = FirstCatch; j < N; ++j)
3060 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3061 MMI->addCatchTypeInfo(MBB, TyInfo);
3065 if (!FilterLength) {
3067 MMI->addCleanup(MBB);
3070 TyInfo.reserve(FilterLength - 1);
3071 for (unsigned j = i + 1; j < FirstCatch; ++j)
3072 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3073 MMI->addFilterTypeInfo(MBB, TyInfo);
3082 TyInfo.reserve(N - 3);
3083 for (unsigned j = 3; j < N; ++j)
3084 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3085 MMI->addCatchTypeInfo(MBB, TyInfo);
3090 /// Inlined utility function to implement binary input atomic intrinsics for
3091 // visitIntrinsicCall: I is a call instruction
3092 // Op is the associated NodeType for I
3094 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3095 SDOperand Root = getRoot();
3096 SDOperand L = DAG.getAtomic(Op, Root,
3097 getValue(I.getOperand(1)),
3098 getValue(I.getOperand(2)),
3101 DAG.setRoot(L.getValue(1));
3105 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3106 /// we want to emit this as a call to a named external function, return the name
3107 /// otherwise lower it and return null.
3109 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3110 switch (Intrinsic) {
3112 // By default, turn this into a target intrinsic node.
3113 visitTargetIntrinsic(I, Intrinsic);
3115 case Intrinsic::vastart: visitVAStart(I); return 0;
3116 case Intrinsic::vaend: visitVAEnd(I); return 0;
3117 case Intrinsic::vacopy: visitVACopy(I); return 0;
3118 case Intrinsic::returnaddress:
3119 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3120 getValue(I.getOperand(1))));
3122 case Intrinsic::frameaddress:
3123 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3124 getValue(I.getOperand(1))));
3126 case Intrinsic::setjmp:
3127 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3129 case Intrinsic::longjmp:
3130 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3132 case Intrinsic::memcpy_i32:
3133 case Intrinsic::memcpy_i64: {
3134 SDOperand Op1 = getValue(I.getOperand(1));
3135 SDOperand Op2 = getValue(I.getOperand(2));
3136 SDOperand Op3 = getValue(I.getOperand(3));
3137 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3138 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3139 I.getOperand(1), 0, I.getOperand(2), 0));
3142 case Intrinsic::memset_i32:
3143 case Intrinsic::memset_i64: {
3144 SDOperand Op1 = getValue(I.getOperand(1));
3145 SDOperand Op2 = getValue(I.getOperand(2));
3146 SDOperand Op3 = getValue(I.getOperand(3));
3147 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3148 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3149 I.getOperand(1), 0));
3152 case Intrinsic::memmove_i32:
3153 case Intrinsic::memmove_i64: {
3154 SDOperand Op1 = getValue(I.getOperand(1));
3155 SDOperand Op2 = getValue(I.getOperand(2));
3156 SDOperand Op3 = getValue(I.getOperand(3));
3157 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3159 // If the source and destination are known to not be aliases, we can
3160 // lower memmove as memcpy.
3161 uint64_t Size = -1ULL;
3162 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3163 Size = C->getValue();
3164 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3165 AliasAnalysis::NoAlias) {
3166 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3167 I.getOperand(1), 0, I.getOperand(2), 0));
3171 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3172 I.getOperand(1), 0, I.getOperand(2), 0));
3175 case Intrinsic::dbg_stoppoint: {
3176 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3177 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3178 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3179 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3180 assert(DD && "Not a debug information descriptor");
3181 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3184 cast<CompileUnitDesc>(DD)));
3189 case Intrinsic::dbg_region_start: {
3190 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3191 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3192 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3193 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3194 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3199 case Intrinsic::dbg_region_end: {
3200 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3201 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3202 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3203 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3204 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3209 case Intrinsic::dbg_func_start: {
3210 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3212 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3213 Value *SP = FSI.getSubprogram();
3214 if (SP && MMI->Verify(SP)) {
3215 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3216 // what (most?) gdb expects.
3217 DebugInfoDesc *DD = MMI->getDescFor(SP);
3218 assert(DD && "Not a debug information descriptor");
3219 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3220 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3221 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3222 // Record the source line but does create a label. It will be emitted
3223 // at asm emission time.
3224 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3229 case Intrinsic::dbg_declare: {
3230 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3231 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3232 Value *Variable = DI.getVariable();
3233 if (MMI && Variable && MMI->Verify(Variable))
3234 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3235 getValue(DI.getAddress()), getValue(Variable)));
3239 case Intrinsic::eh_exception: {
3240 if (!CurMBB->isLandingPad()) {
3241 // FIXME: Mark exception register as live in. Hack for PR1508.
3242 unsigned Reg = TLI.getExceptionAddressRegister();
3243 if (Reg) CurMBB->addLiveIn(Reg);
3245 // Insert the EXCEPTIONADDR instruction.
3246 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3248 Ops[0] = DAG.getRoot();
3249 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3251 DAG.setRoot(Op.getValue(1));
3255 case Intrinsic::eh_selector_i32:
3256 case Intrinsic::eh_selector_i64: {
3257 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3258 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3259 MVT::i32 : MVT::i64);
3262 if (CurMBB->isLandingPad())
3263 addCatchInfo(I, MMI, CurMBB);
3266 FuncInfo.CatchInfoLost.insert(&I);
3268 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3269 unsigned Reg = TLI.getExceptionSelectorRegister();
3270 if (Reg) CurMBB->addLiveIn(Reg);
3273 // Insert the EHSELECTION instruction.
3274 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3276 Ops[0] = getValue(I.getOperand(1));
3278 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3280 DAG.setRoot(Op.getValue(1));
3282 setValue(&I, DAG.getConstant(0, VT));
3288 case Intrinsic::eh_typeid_for_i32:
3289 case Intrinsic::eh_typeid_for_i64: {
3290 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3291 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3292 MVT::i32 : MVT::i64);
3295 // Find the type id for the given typeinfo.
3296 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3298 unsigned TypeID = MMI->getTypeIDFor(GV);
3299 setValue(&I, DAG.getConstant(TypeID, VT));
3301 // Return something different to eh_selector.
3302 setValue(&I, DAG.getConstant(1, VT));
3308 case Intrinsic::eh_return: {
3309 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3312 MMI->setCallsEHReturn(true);
3313 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3316 getValue(I.getOperand(1)),
3317 getValue(I.getOperand(2))));
3319 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3325 case Intrinsic::eh_unwind_init: {
3326 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3327 MMI->setCallsUnwindInit(true);
3333 case Intrinsic::eh_dwarf_cfa: {
3334 MVT VT = getValue(I.getOperand(1)).getValueType();
3336 if (VT.bitsGT(TLI.getPointerTy()))
3337 CfaArg = DAG.getNode(ISD::TRUNCATE,
3338 TLI.getPointerTy(), getValue(I.getOperand(1)));
3340 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3341 TLI.getPointerTy(), getValue(I.getOperand(1)));
3343 SDOperand Offset = DAG.getNode(ISD::ADD,
3345 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3346 TLI.getPointerTy()),
3348 setValue(&I, DAG.getNode(ISD::ADD,
3350 DAG.getNode(ISD::FRAMEADDR,
3353 TLI.getPointerTy())),
3358 case Intrinsic::sqrt:
3359 setValue(&I, DAG.getNode(ISD::FSQRT,
3360 getValue(I.getOperand(1)).getValueType(),
3361 getValue(I.getOperand(1))));
3363 case Intrinsic::powi:
3364 setValue(&I, DAG.getNode(ISD::FPOWI,
3365 getValue(I.getOperand(1)).getValueType(),
3366 getValue(I.getOperand(1)),
3367 getValue(I.getOperand(2))));
3369 case Intrinsic::sin:
3370 setValue(&I, DAG.getNode(ISD::FSIN,
3371 getValue(I.getOperand(1)).getValueType(),
3372 getValue(I.getOperand(1))));
3374 case Intrinsic::cos:
3375 setValue(&I, DAG.getNode(ISD::FCOS,
3376 getValue(I.getOperand(1)).getValueType(),
3377 getValue(I.getOperand(1))));
3379 case Intrinsic::pow:
3380 setValue(&I, DAG.getNode(ISD::FPOW,
3381 getValue(I.getOperand(1)).getValueType(),
3382 getValue(I.getOperand(1)),
3383 getValue(I.getOperand(2))));
3385 case Intrinsic::pcmarker: {
3386 SDOperand Tmp = getValue(I.getOperand(1));
3387 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3390 case Intrinsic::readcyclecounter: {
3391 SDOperand Op = getRoot();
3392 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3393 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3396 DAG.setRoot(Tmp.getValue(1));
3399 case Intrinsic::part_select: {
3400 // Currently not implemented: just abort
3401 assert(0 && "part_select intrinsic not implemented");
3404 case Intrinsic::part_set: {
3405 // Currently not implemented: just abort
3406 assert(0 && "part_set intrinsic not implemented");
3409 case Intrinsic::bswap:
3410 setValue(&I, DAG.getNode(ISD::BSWAP,
3411 getValue(I.getOperand(1)).getValueType(),
3412 getValue(I.getOperand(1))));
3414 case Intrinsic::cttz: {
3415 SDOperand Arg = getValue(I.getOperand(1));
3416 MVT Ty = Arg.getValueType();
3417 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3418 setValue(&I, result);
3421 case Intrinsic::ctlz: {
3422 SDOperand Arg = getValue(I.getOperand(1));
3423 MVT Ty = Arg.getValueType();
3424 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3425 setValue(&I, result);
3428 case Intrinsic::ctpop: {
3429 SDOperand Arg = getValue(I.getOperand(1));
3430 MVT Ty = Arg.getValueType();
3431 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3432 setValue(&I, result);
3435 case Intrinsic::stacksave: {
3436 SDOperand Op = getRoot();
3437 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
3438 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3440 DAG.setRoot(Tmp.getValue(1));
3443 case Intrinsic::stackrestore: {
3444 SDOperand Tmp = getValue(I.getOperand(1));
3445 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3448 case Intrinsic::var_annotation:
3449 // Discard annotate attributes
3452 case Intrinsic::init_trampoline: {
3453 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3457 Ops[1] = getValue(I.getOperand(1));
3458 Ops[2] = getValue(I.getOperand(2));
3459 Ops[3] = getValue(I.getOperand(3));
3460 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3461 Ops[5] = DAG.getSrcValue(F);
3463 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3464 DAG.getNodeValueTypes(TLI.getPointerTy(),
3469 DAG.setRoot(Tmp.getValue(1));
3473 case Intrinsic::gcroot:
3475 Value *Alloca = I.getOperand(1);
3476 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3478 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3479 GCI->addStackRoot(FI->getIndex(), TypeMap);
3483 case Intrinsic::gcread:
3484 case Intrinsic::gcwrite:
3485 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3488 case Intrinsic::flt_rounds: {
3489 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3493 case Intrinsic::trap: {
3494 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3497 case Intrinsic::prefetch: {
3500 Ops[1] = getValue(I.getOperand(1));
3501 Ops[2] = getValue(I.getOperand(2));
3502 Ops[3] = getValue(I.getOperand(3));
3503 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3507 case Intrinsic::memory_barrier: {
3510 for (int x = 1; x < 6; ++x)
3511 Ops[x] = getValue(I.getOperand(x));
3513 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3516 case Intrinsic::atomic_cmp_swap: {
3517 SDOperand Root = getRoot();
3518 SDOperand L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
3519 getValue(I.getOperand(1)),
3520 getValue(I.getOperand(2)),
3521 getValue(I.getOperand(3)),
3524 DAG.setRoot(L.getValue(1));
3527 case Intrinsic::atomic_load_add:
3528 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3529 case Intrinsic::atomic_load_sub:
3530 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
3531 case Intrinsic::atomic_load_and:
3532 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3533 case Intrinsic::atomic_load_or:
3534 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3535 case Intrinsic::atomic_load_xor:
3536 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3537 case Intrinsic::atomic_load_nand:
3538 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3539 case Intrinsic::atomic_load_min:
3540 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3541 case Intrinsic::atomic_load_max:
3542 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3543 case Intrinsic::atomic_load_umin:
3544 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3545 case Intrinsic::atomic_load_umax:
3546 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3547 case Intrinsic::atomic_swap:
3548 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3553 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3555 MachineBasicBlock *LandingPad) {
3556 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3557 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3558 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3559 unsigned BeginLabel = 0, EndLabel = 0;
3561 TargetLowering::ArgListTy Args;
3562 TargetLowering::ArgListEntry Entry;
3563 Args.reserve(CS.arg_size());
3564 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3566 SDOperand ArgNode = getValue(*i);
3567 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3569 unsigned attrInd = i - CS.arg_begin() + 1;
3570 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3571 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3572 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3573 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3574 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3575 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3576 Entry.Alignment = CS.getParamAlignment(attrInd);
3577 Args.push_back(Entry);
3580 if (LandingPad && MMI) {
3581 // Insert a label before the invoke call to mark the try range. This can be
3582 // used to detect deletion of the invoke via the MachineModuleInfo.
3583 BeginLabel = MMI->NextLabelID();
3584 // Both PendingLoads and PendingExports must be flushed here;
3585 // this call might not return.
3587 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
3590 std::pair<SDOperand,SDOperand> Result =
3591 TLI.LowerCallTo(getRoot(), CS.getType(),
3592 CS.paramHasAttr(0, ParamAttr::SExt),
3593 CS.paramHasAttr(0, ParamAttr::ZExt),
3594 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3596 if (CS.getType() != Type::VoidTy)
3597 setValue(CS.getInstruction(), Result.first);
3598 DAG.setRoot(Result.second);
3600 if (LandingPad && MMI) {
3601 // Insert a label at the end of the invoke call to mark the try range. This
3602 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3603 EndLabel = MMI->NextLabelID();
3604 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
3606 // Inform MachineModuleInfo of range.
3607 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3612 void SelectionDAGLowering::visitCall(CallInst &I) {
3613 const char *RenameFn = 0;
3614 if (Function *F = I.getCalledFunction()) {
3615 if (F->isDeclaration()) {
3616 if (unsigned IID = F->getIntrinsicID()) {
3617 RenameFn = visitIntrinsicCall(I, IID);
3623 // Check for well-known libc/libm calls. If the function is internal, it
3624 // can't be a library call.
3625 unsigned NameLen = F->getNameLen();
3626 if (!F->hasInternalLinkage() && NameLen) {
3627 const char *NameStr = F->getNameStart();
3628 if (NameStr[0] == 'c' &&
3629 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3630 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3631 if (I.getNumOperands() == 3 && // Basic sanity checks.
3632 I.getOperand(1)->getType()->isFloatingPoint() &&
3633 I.getType() == I.getOperand(1)->getType() &&
3634 I.getType() == I.getOperand(2)->getType()) {
3635 SDOperand LHS = getValue(I.getOperand(1));
3636 SDOperand RHS = getValue(I.getOperand(2));
3637 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3641 } else if (NameStr[0] == 'f' &&
3642 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3643 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3644 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3645 if (I.getNumOperands() == 2 && // Basic sanity checks.
3646 I.getOperand(1)->getType()->isFloatingPoint() &&
3647 I.getType() == I.getOperand(1)->getType()) {
3648 SDOperand Tmp = getValue(I.getOperand(1));
3649 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3652 } else if (NameStr[0] == 's' &&
3653 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3654 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3655 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3656 if (I.getNumOperands() == 2 && // Basic sanity checks.
3657 I.getOperand(1)->getType()->isFloatingPoint() &&
3658 I.getType() == I.getOperand(1)->getType()) {
3659 SDOperand Tmp = getValue(I.getOperand(1));
3660 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3663 } else if (NameStr[0] == 'c' &&
3664 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3665 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3666 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3667 if (I.getNumOperands() == 2 && // Basic sanity checks.
3668 I.getOperand(1)->getType()->isFloatingPoint() &&
3669 I.getType() == I.getOperand(1)->getType()) {
3670 SDOperand Tmp = getValue(I.getOperand(1));
3671 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3676 } else if (isa<InlineAsm>(I.getOperand(0))) {
3683 Callee = getValue(I.getOperand(0));
3685 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3687 LowerCallTo(&I, Callee, I.isTailCall());
3691 void SelectionDAGLowering::visitGetResult(GetResultInst &I) {
3692 if (isa<UndefValue>(I.getOperand(0))) {
3693 SDOperand Undef = DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType()));
3694 setValue(&I, Undef);
3698 // To add support for individual return values with aggregate types,
3699 // we'd need a way to take a getresult index and determine which
3700 // values of the Call SDNode are associated with it.
3701 assert(TLI.getValueType(I.getType(), true) != MVT::Other &&
3702 "Individual return values must not be aggregates!");
3704 SDOperand Call = getValue(I.getOperand(0));
3705 setValue(&I, SDOperand(Call.Val, I.getIndex()));
3709 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3710 /// this value and returns the result as a ValueVT value. This uses
3711 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3712 /// If the Flag pointer is NULL, no flag is used.
3713 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3715 SDOperand *Flag) const {
3716 // Assemble the legal parts into the final values.
3717 SmallVector<SDOperand, 4> Values(ValueVTs.size());
3718 SmallVector<SDOperand, 8> Parts;
3719 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3720 // Copy the legal parts from the registers.
3721 MVT ValueVT = ValueVTs[Value];
3722 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3723 MVT RegisterVT = RegVTs[Value];
3725 Parts.resize(NumRegs);
3726 for (unsigned i = 0; i != NumRegs; ++i) {
3729 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3731 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3732 *Flag = P.getValue(2);
3734 Chain = P.getValue(1);
3736 // If the source register was virtual and if we know something about it,
3737 // add an assert node.
3738 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3739 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3740 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3741 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3742 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3743 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3745 unsigned RegSize = RegisterVT.getSizeInBits();
3746 unsigned NumSignBits = LOI.NumSignBits;
3747 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3749 // FIXME: We capture more information than the dag can represent. For
3750 // now, just use the tightest assertzext/assertsext possible.
3752 MVT FromVT(MVT::Other);
3753 if (NumSignBits == RegSize)
3754 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3755 else if (NumZeroBits >= RegSize-1)
3756 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3757 else if (NumSignBits > RegSize-8)
3758 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3759 else if (NumZeroBits >= RegSize-9)
3760 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3761 else if (NumSignBits > RegSize-16)
3762 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3763 else if (NumZeroBits >= RegSize-17)
3764 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3765 else if (NumSignBits > RegSize-32)
3766 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3767 else if (NumZeroBits >= RegSize-33)
3768 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3770 if (FromVT != MVT::Other) {
3771 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3772 RegisterVT, P, DAG.getValueType(FromVT));
3781 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3786 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3787 &Values[0], ValueVTs.size());
3790 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3791 /// specified value into the registers specified by this object. This uses
3792 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3793 /// If the Flag pointer is NULL, no flag is used.
3794 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3795 SDOperand &Chain, SDOperand *Flag) const {
3796 // Get the list of the values's legal parts.
3797 unsigned NumRegs = Regs.size();
3798 SmallVector<SDOperand, 8> Parts(NumRegs);
3799 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3800 MVT ValueVT = ValueVTs[Value];
3801 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3802 MVT RegisterVT = RegVTs[Value];
3804 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3805 &Parts[Part], NumParts, RegisterVT);
3809 // Copy the parts into the registers.
3810 SmallVector<SDOperand, 8> Chains(NumRegs);
3811 for (unsigned i = 0; i != NumRegs; ++i) {
3814 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3816 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3817 *Flag = Part.getValue(1);
3819 Chains[i] = Part.getValue(0);
3822 if (NumRegs == 1 || Flag)
3823 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3824 // flagged to it. That is the CopyToReg nodes and the user are considered
3825 // a single scheduling unit. If we create a TokenFactor and return it as
3826 // chain, then the TokenFactor is both a predecessor (operand) of the
3827 // user as well as a successor (the TF operands are flagged to the user).
3828 // c1, f1 = CopyToReg
3829 // c2, f2 = CopyToReg
3830 // c3 = TokenFactor c1, c2
3833 Chain = Chains[NumRegs-1];
3835 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3838 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3839 /// operand list. This adds the code marker and includes the number of
3840 /// values added into it.
3841 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3842 std::vector<SDOperand> &Ops) const {
3843 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3844 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3845 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3846 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3847 MVT RegisterVT = RegVTs[Value];
3848 for (unsigned i = 0; i != NumRegs; ++i)
3849 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3853 /// isAllocatableRegister - If the specified register is safe to allocate,
3854 /// i.e. it isn't a stack pointer or some other special register, return the
3855 /// register class for the register. Otherwise, return null.
3856 static const TargetRegisterClass *
3857 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3858 const TargetLowering &TLI,
3859 const TargetRegisterInfo *TRI) {
3860 MVT FoundVT = MVT::Other;
3861 const TargetRegisterClass *FoundRC = 0;
3862 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3863 E = TRI->regclass_end(); RCI != E; ++RCI) {
3864 MVT ThisVT = MVT::Other;
3866 const TargetRegisterClass *RC = *RCI;
3867 // If none of the the value types for this register class are valid, we
3868 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3869 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3871 if (TLI.isTypeLegal(*I)) {
3872 // If we have already found this register in a different register class,
3873 // choose the one with the largest VT specified. For example, on
3874 // PowerPC, we favor f64 register classes over f32.
3875 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3882 if (ThisVT == MVT::Other) continue;
3884 // NOTE: This isn't ideal. In particular, this might allocate the
3885 // frame pointer in functions that need it (due to them not being taken
3886 // out of allocation, because a variable sized allocation hasn't been seen
3887 // yet). This is a slight code pessimization, but should still work.
3888 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3889 E = RC->allocation_order_end(MF); I != E; ++I)
3891 // We found a matching register class. Keep looking at others in case
3892 // we find one with larger registers that this physreg is also in.
3903 /// AsmOperandInfo - This contains information for each constraint that we are
3905 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3906 /// CallOperand - If this is the result output operand or a clobber
3907 /// this is null, otherwise it is the incoming operand to the CallInst.
3908 /// This gets modified as the asm is processed.
3909 SDOperand CallOperand;
3911 /// AssignedRegs - If this is a register or register class operand, this
3912 /// contains the set of register corresponding to the operand.
3913 RegsForValue AssignedRegs;
3915 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3916 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3919 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3920 /// busy in OutputRegs/InputRegs.
3921 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3922 std::set<unsigned> &OutputRegs,
3923 std::set<unsigned> &InputRegs,
3924 const TargetRegisterInfo &TRI) const {
3926 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3927 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3930 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3931 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3936 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3938 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3939 const TargetRegisterInfo &TRI) {
3940 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3942 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3943 for (; *Aliases; ++Aliases)
3944 Regs.insert(*Aliases);
3947 } // end anon namespace.
3950 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3951 /// specified operand. We prefer to assign virtual registers, to allow the
3952 /// register allocator handle the assignment process. However, if the asm uses
3953 /// features that we can't model on machineinstrs, we have SDISel do the
3954 /// allocation. This produces generally horrible, but correct, code.
3956 /// OpInfo describes the operand.
3957 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3958 /// or any explicitly clobbered registers.
3959 /// Input and OutputRegs are the set of already allocated physical registers.
3961 void SelectionDAGLowering::
3962 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3963 std::set<unsigned> &OutputRegs,
3964 std::set<unsigned> &InputRegs) {
3965 // Compute whether this value requires an input register, an output register,
3967 bool isOutReg = false;
3968 bool isInReg = false;
3969 switch (OpInfo.Type) {
3970 case InlineAsm::isOutput:
3973 // If this is an early-clobber output, or if there is an input
3974 // constraint that matches this, we need to reserve the input register
3975 // so no other inputs allocate to it.
3976 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3978 case InlineAsm::isInput:
3982 case InlineAsm::isClobber:
3989 MachineFunction &MF = DAG.getMachineFunction();
3990 SmallVector<unsigned, 4> Regs;
3992 // If this is a constraint for a single physreg, or a constraint for a
3993 // register class, find it.
3994 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3995 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3996 OpInfo.ConstraintVT);
3998 unsigned NumRegs = 1;
3999 if (OpInfo.ConstraintVT != MVT::Other)
4000 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4002 MVT ValueVT = OpInfo.ConstraintVT;
4005 // If this is a constraint for a specific physical register, like {r17},
4007 if (PhysReg.first) {
4008 if (OpInfo.ConstraintVT == MVT::Other)
4009 ValueVT = *PhysReg.second->vt_begin();
4011 // Get the actual register value type. This is important, because the user
4012 // may have asked for (e.g.) the AX register in i32 type. We need to
4013 // remember that AX is actually i16 to get the right extension.
4014 RegVT = *PhysReg.second->vt_begin();
4016 // This is a explicit reference to a physical register.
4017 Regs.push_back(PhysReg.first);
4019 // If this is an expanded reference, add the rest of the regs to Regs.
4021 TargetRegisterClass::iterator I = PhysReg.second->begin();
4022 for (; *I != PhysReg.first; ++I)
4023 assert(I != PhysReg.second->end() && "Didn't find reg!");
4025 // Already added the first reg.
4027 for (; NumRegs; --NumRegs, ++I) {
4028 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4032 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4033 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4034 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4038 // Otherwise, if this was a reference to an LLVM register class, create vregs
4039 // for this reference.
4040 std::vector<unsigned> RegClassRegs;
4041 const TargetRegisterClass *RC = PhysReg.second;
4043 // If this is an early clobber or tied register, our regalloc doesn't know
4044 // how to maintain the constraint. If it isn't, go ahead and create vreg
4045 // and let the regalloc do the right thing.
4046 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4047 // If there is some other early clobber and this is an input register,
4048 // then we are forced to pre-allocate the input reg so it doesn't
4049 // conflict with the earlyclobber.
4050 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4051 RegVT = *PhysReg.second->vt_begin();
4053 if (OpInfo.ConstraintVT == MVT::Other)
4056 // Create the appropriate number of virtual registers.
4057 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4058 for (; NumRegs; --NumRegs)
4059 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4061 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4065 // Otherwise, we can't allocate it. Let the code below figure out how to
4066 // maintain these constraints.
4067 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4070 // This is a reference to a register class that doesn't directly correspond
4071 // to an LLVM register class. Allocate NumRegs consecutive, available,
4072 // registers from the class.
4073 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4074 OpInfo.ConstraintVT);
4077 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4078 unsigned NumAllocated = 0;
4079 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4080 unsigned Reg = RegClassRegs[i];
4081 // See if this register is available.
4082 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4083 (isInReg && InputRegs.count(Reg))) { // Already used.
4084 // Make sure we find consecutive registers.
4089 // Check to see if this register is allocatable (i.e. don't give out the
4092 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4093 if (!RC) { // Couldn't allocate this register.
4094 // Reset NumAllocated to make sure we return consecutive registers.
4100 // Okay, this register is good, we can use it.
4103 // If we allocated enough consecutive registers, succeed.
4104 if (NumAllocated == NumRegs) {
4105 unsigned RegStart = (i-NumAllocated)+1;
4106 unsigned RegEnd = i+1;
4107 // Mark all of the allocated registers used.
4108 for (unsigned i = RegStart; i != RegEnd; ++i)
4109 Regs.push_back(RegClassRegs[i]);
4111 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4112 OpInfo.ConstraintVT);
4113 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4118 // Otherwise, we couldn't allocate enough registers for this.
4122 /// visitInlineAsm - Handle a call to an InlineAsm object.
4124 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4125 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4127 /// ConstraintOperands - Information about all of the constraints.
4128 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4130 SDOperand Chain = getRoot();
4133 std::set<unsigned> OutputRegs, InputRegs;
4135 // Do a prepass over the constraints, canonicalizing them, and building up the
4136 // ConstraintOperands list.
4137 std::vector<InlineAsm::ConstraintInfo>
4138 ConstraintInfos = IA->ParseConstraints();
4140 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4141 // constraint. If so, we can't let the register allocator allocate any input
4142 // registers, because it will not know to avoid the earlyclobbered output reg.
4143 bool SawEarlyClobber = false;
4145 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4146 unsigned ResNo = 0; // ResNo - The result number of the next output.
4147 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4148 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4149 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4151 MVT OpVT = MVT::Other;
4153 // Compute the value type for each operand.
4154 switch (OpInfo.Type) {
4155 case InlineAsm::isOutput:
4156 // Indirect outputs just consume an argument.
4157 if (OpInfo.isIndirect) {
4158 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4161 // The return value of the call is this value. As such, there is no
4162 // corresponding argument.
4163 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4164 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4165 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4167 assert(ResNo == 0 && "Asm only has one result!");
4168 OpVT = TLI.getValueType(CS.getType());
4172 case InlineAsm::isInput:
4173 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4175 case InlineAsm::isClobber:
4180 // If this is an input or an indirect output, process the call argument.
4181 // BasicBlocks are labels, currently appearing only in asm's.
4182 if (OpInfo.CallOperandVal) {
4183 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4184 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4186 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4187 const Type *OpTy = OpInfo.CallOperandVal->getType();
4188 // If this is an indirect operand, the operand is a pointer to the
4190 if (OpInfo.isIndirect)
4191 OpTy = cast<PointerType>(OpTy)->getElementType();
4193 // If OpTy is not a single value, it may be a struct/union that we
4194 // can tile with integers.
4195 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4196 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4204 OpTy = IntegerType::get(BitSize);
4209 OpVT = TLI.getValueType(OpTy, true);
4213 OpInfo.ConstraintVT = OpVT;
4215 // Compute the constraint code and ConstraintType to use.
4216 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4218 // Keep track of whether we see an earlyclobber.
4219 SawEarlyClobber |= OpInfo.isEarlyClobber;
4221 // If we see a clobber of a register, it is an early clobber.
4222 if (!SawEarlyClobber &&
4223 OpInfo.Type == InlineAsm::isClobber &&
4224 OpInfo.ConstraintType == TargetLowering::C_Register) {
4225 // Note that we want to ignore things that we don't trick here, like
4226 // dirflag, fpsr, flags, etc.
4227 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4228 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4229 OpInfo.ConstraintVT);
4230 if (PhysReg.first || PhysReg.second) {
4231 // This is a register we know of.
4232 SawEarlyClobber = true;
4236 // If this is a memory input, and if the operand is not indirect, do what we
4237 // need to to provide an address for the memory input.
4238 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4239 !OpInfo.isIndirect) {
4240 assert(OpInfo.Type == InlineAsm::isInput &&
4241 "Can only indirectify direct input operands!");
4243 // Memory operands really want the address of the value. If we don't have
4244 // an indirect input, put it in the constpool if we can, otherwise spill
4245 // it to a stack slot.
4247 // If the operand is a float, integer, or vector constant, spill to a
4248 // constant pool entry to get its address.
4249 Value *OpVal = OpInfo.CallOperandVal;
4250 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4251 isa<ConstantVector>(OpVal)) {
4252 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4253 TLI.getPointerTy());
4255 // Otherwise, create a stack slot and emit a store to it before the
4257 const Type *Ty = OpVal->getType();
4258 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4259 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4260 MachineFunction &MF = DAG.getMachineFunction();
4261 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4262 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4263 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4264 OpInfo.CallOperand = StackSlot;
4267 // There is no longer a Value* corresponding to this operand.
4268 OpInfo.CallOperandVal = 0;
4269 // It is now an indirect operand.
4270 OpInfo.isIndirect = true;
4273 // If this constraint is for a specific register, allocate it before
4275 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4276 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4278 ConstraintInfos.clear();
4281 // Second pass - Loop over all of the operands, assigning virtual or physregs
4282 // to registerclass operands.
4283 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4284 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4286 // C_Register operands have already been allocated, Other/Memory don't need
4288 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4289 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4292 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4293 std::vector<SDOperand> AsmNodeOperands;
4294 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
4295 AsmNodeOperands.push_back(
4296 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4299 // Loop over all of the inputs, copying the operand values into the
4300 // appropriate registers and processing the output regs.
4301 RegsForValue RetValRegs;
4303 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4304 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4306 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4307 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4309 switch (OpInfo.Type) {
4310 case InlineAsm::isOutput: {
4311 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4312 OpInfo.ConstraintType != TargetLowering::C_Register) {
4313 // Memory output, or 'other' output (e.g. 'X' constraint).
4314 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4316 // Add information to the INLINEASM node to know about this output.
4317 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4318 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4319 TLI.getPointerTy()));
4320 AsmNodeOperands.push_back(OpInfo.CallOperand);
4324 // Otherwise, this is a register or register class output.
4326 // Copy the output from the appropriate register. Find a register that
4328 if (OpInfo.AssignedRegs.Regs.empty()) {
4329 cerr << "Couldn't allocate output reg for constraint '"
4330 << OpInfo.ConstraintCode << "'!\n";
4334 // If this is an indirect operand, store through the pointer after the
4336 if (OpInfo.isIndirect) {
4337 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4338 OpInfo.CallOperandVal));
4340 // This is the result value of the call.
4341 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4342 // Concatenate this output onto the outputs list.
4343 RetValRegs.append(OpInfo.AssignedRegs);
4346 // Add information to the INLINEASM node to know that this register is
4348 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4352 case InlineAsm::isInput: {
4353 SDOperand InOperandVal = OpInfo.CallOperand;
4355 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4356 // If this is required to match an output register we have already set,
4357 // just use its register.
4358 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4360 // Scan until we find the definition we already emitted of this operand.
4361 // When we find it, create a RegsForValue operand.
4362 unsigned CurOp = 2; // The first operand.
4363 for (; OperandNo; --OperandNo) {
4364 // Advance to the next operand.
4366 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4367 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4368 (NumOps & 7) == 4 /*MEM*/) &&
4369 "Skipped past definitions?");
4370 CurOp += (NumOps>>3)+1;
4374 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4375 if ((NumOps & 7) == 2 /*REGDEF*/) {
4376 // Add NumOps>>3 registers to MatchedRegs.
4377 RegsForValue MatchedRegs;
4378 MatchedRegs.TLI = &TLI;
4379 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4380 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4381 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4383 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4384 MatchedRegs.Regs.push_back(Reg);
4387 // Use the produced MatchedRegs object to
4388 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4389 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4392 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4393 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4394 // Add information to the INLINEASM node to know about this input.
4395 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4396 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4397 TLI.getPointerTy()));
4398 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4403 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4404 assert(!OpInfo.isIndirect &&
4405 "Don't know how to handle indirect other inputs yet!");
4407 std::vector<SDOperand> Ops;
4408 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4411 cerr << "Invalid operand for inline asm constraint '"
4412 << OpInfo.ConstraintCode << "'!\n";
4416 // Add information to the INLINEASM node to know about this input.
4417 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4418 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4419 TLI.getPointerTy()));
4420 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4422 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4423 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4424 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4425 "Memory operands expect pointer values");
4427 // Add information to the INLINEASM node to know about this input.
4428 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4429 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4430 TLI.getPointerTy()));
4431 AsmNodeOperands.push_back(InOperandVal);
4435 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4436 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4437 "Unknown constraint type!");
4438 assert(!OpInfo.isIndirect &&
4439 "Don't know how to handle indirect register inputs yet!");
4441 // Copy the input into the appropriate registers.
4442 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4443 "Couldn't allocate input reg!");
4445 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4447 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4451 case InlineAsm::isClobber: {
4452 // Add the clobbered value to the operand list, so that the register
4453 // allocator is aware that the physreg got clobbered.
4454 if (!OpInfo.AssignedRegs.Regs.empty())
4455 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4462 // Finish up input operands.
4463 AsmNodeOperands[0] = Chain;
4464 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4466 Chain = DAG.getNode(ISD::INLINEASM,
4467 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4468 &AsmNodeOperands[0], AsmNodeOperands.size());
4469 Flag = Chain.getValue(1);
4471 // If this asm returns a register value, copy the result from that register
4472 // and set it as the value of the call.
4473 if (!RetValRegs.Regs.empty()) {
4474 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4476 // If any of the results of the inline asm is a vector, it may have the
4477 // wrong width/num elts. This can happen for register classes that can
4478 // contain multiple different value types. The preg or vreg allocated may
4479 // not have the same VT as was expected. Convert it to the right type with
4481 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4482 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4483 if (Val.Val->getValueType(i).isVector())
4484 Val = DAG.getNode(ISD::BIT_CONVERT,
4485 TLI.getValueType(ResSTy->getElementType(i)), Val);
4488 if (Val.getValueType().isVector())
4489 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4493 setValue(CS.getInstruction(), Val);
4496 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
4498 // Process indirect outputs, first output all of the flagged copies out of
4500 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4501 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4502 Value *Ptr = IndirectStoresToEmit[i].second;
4503 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4504 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4507 // Emit the non-flagged stores from the physregs.
4508 SmallVector<SDOperand, 8> OutChains;
4509 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4510 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4511 getValue(StoresToEmit[i].second),
4512 StoresToEmit[i].second, 0));
4513 if (!OutChains.empty())
4514 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4515 &OutChains[0], OutChains.size());
4520 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4521 SDOperand Src = getValue(I.getOperand(0));
4523 MVT IntPtr = TLI.getPointerTy();
4525 if (IntPtr.bitsLT(Src.getValueType()))
4526 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4527 else if (IntPtr.bitsGT(Src.getValueType()))
4528 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4530 // Scale the source by the type size.
4531 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4532 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4533 Src, DAG.getIntPtrConstant(ElementSize));
4535 TargetLowering::ArgListTy Args;
4536 TargetLowering::ArgListEntry Entry;
4538 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4539 Args.push_back(Entry);
4541 std::pair<SDOperand,SDOperand> Result =
4542 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4543 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4544 setValue(&I, Result.first); // Pointers always fit in registers
4545 DAG.setRoot(Result.second);
4548 void SelectionDAGLowering::visitFree(FreeInst &I) {
4549 TargetLowering::ArgListTy Args;
4550 TargetLowering::ArgListEntry Entry;
4551 Entry.Node = getValue(I.getOperand(0));
4552 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4553 Args.push_back(Entry);
4554 MVT IntPtr = TLI.getPointerTy();
4555 std::pair<SDOperand,SDOperand> Result =
4556 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4557 CallingConv::C, true,
4558 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4559 DAG.setRoot(Result.second);
4562 // EmitInstrWithCustomInserter - This method should be implemented by targets
4563 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4564 // instructions are special in various ways, which require special support to
4565 // insert. The specified MachineInstr is created but not inserted into any
4566 // basic blocks, and the scheduler passes ownership of it to this method.
4567 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4568 MachineBasicBlock *MBB) {
4569 cerr << "If a target marks an instruction with "
4570 << "'usesCustomDAGSchedInserter', it must implement "
4571 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4576 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4577 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4578 getValue(I.getOperand(1)),
4579 DAG.getSrcValue(I.getOperand(1))));
4582 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4583 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4584 getValue(I.getOperand(0)),
4585 DAG.getSrcValue(I.getOperand(0)));
4587 DAG.setRoot(V.getValue(1));
4590 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4591 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4592 getValue(I.getOperand(1)),
4593 DAG.getSrcValue(I.getOperand(1))));
4596 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4597 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4598 getValue(I.getOperand(1)),
4599 getValue(I.getOperand(2)),
4600 DAG.getSrcValue(I.getOperand(1)),
4601 DAG.getSrcValue(I.getOperand(2))));
4604 /// TargetLowering::LowerArguments - This is the default LowerArguments
4605 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4606 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4607 /// integrated into SDISel.
4608 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4609 SmallVectorImpl<SDOperand> &ArgValues) {
4610 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4611 SmallVector<SDOperand, 3+16> Ops;
4612 Ops.push_back(DAG.getRoot());
4613 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4614 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4616 // Add one result value for each formal argument.
4617 SmallVector<MVT, 16> RetVals;
4619 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4621 SmallVector<MVT, 4> ValueVTs;
4622 ComputeValueVTs(*this, I->getType(), ValueVTs);
4623 for (unsigned Value = 0, NumValues = ValueVTs.size();
4624 Value != NumValues; ++Value) {
4625 MVT VT = ValueVTs[Value];
4626 const Type *ArgTy = VT.getTypeForMVT();
4627 ISD::ArgFlagsTy Flags;
4628 unsigned OriginalAlignment =
4629 getTargetData()->getABITypeAlignment(ArgTy);
4631 if (F.paramHasAttr(j, ParamAttr::ZExt))
4633 if (F.paramHasAttr(j, ParamAttr::SExt))
4635 if (F.paramHasAttr(j, ParamAttr::InReg))
4637 if (F.paramHasAttr(j, ParamAttr::StructRet))
4639 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4641 const PointerType *Ty = cast<PointerType>(I->getType());
4642 const Type *ElementTy = Ty->getElementType();
4643 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4644 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4645 // For ByVal, alignment should be passed from FE. BE will guess if
4646 // this info is not there but there are cases it cannot get right.
4647 if (F.getParamAlignment(j))
4648 FrameAlign = F.getParamAlignment(j);
4649 Flags.setByValAlign(FrameAlign);
4650 Flags.setByValSize(FrameSize);
4652 if (F.paramHasAttr(j, ParamAttr::Nest))
4654 Flags.setOrigAlign(OriginalAlignment);
4656 MVT RegisterVT = getRegisterType(VT);
4657 unsigned NumRegs = getNumRegisters(VT);
4658 for (unsigned i = 0; i != NumRegs; ++i) {
4659 RetVals.push_back(RegisterVT);
4660 ISD::ArgFlagsTy MyFlags = Flags;
4661 if (NumRegs > 1 && i == 0)
4663 // if it isn't first piece, alignment must be 1
4665 MyFlags.setOrigAlign(1);
4666 Ops.push_back(DAG.getArgFlags(MyFlags));
4671 RetVals.push_back(MVT::Other);
4674 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4675 DAG.getVTList(&RetVals[0], RetVals.size()),
4676 &Ops[0], Ops.size()).Val;
4678 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4679 // allows exposing the loads that may be part of the argument access to the
4680 // first DAGCombiner pass.
4681 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4683 // The number of results should match up, except that the lowered one may have
4684 // an extra flag result.
4685 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4686 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4687 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4688 && "Lowering produced unexpected number of results!");
4690 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
4691 if (Result != TmpRes.Val && Result->use_empty()) {
4692 HandleSDNode Dummy(DAG.getRoot());
4693 DAG.RemoveDeadNode(Result);
4696 Result = TmpRes.Val;
4698 unsigned NumArgRegs = Result->getNumValues() - 1;
4699 DAG.setRoot(SDOperand(Result, NumArgRegs));
4701 // Set up the return result vector.
4704 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4706 SmallVector<MVT, 4> ValueVTs;
4707 ComputeValueVTs(*this, I->getType(), ValueVTs);
4708 for (unsigned Value = 0, NumValues = ValueVTs.size();
4709 Value != NumValues; ++Value) {
4710 MVT VT = ValueVTs[Value];
4711 MVT PartVT = getRegisterType(VT);
4713 unsigned NumParts = getNumRegisters(VT);
4714 SmallVector<SDOperand, 4> Parts(NumParts);
4715 for (unsigned j = 0; j != NumParts; ++j)
4716 Parts[j] = SDOperand(Result, i++);
4718 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4719 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4720 AssertOp = ISD::AssertSext;
4721 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4722 AssertOp = ISD::AssertZext;
4724 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4728 assert(i == NumArgRegs && "Argument register count mismatch!");
4732 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4733 /// implementation, which just inserts an ISD::CALL node, which is later custom
4734 /// lowered by the target to something concrete. FIXME: When all targets are
4735 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4736 std::pair<SDOperand, SDOperand>
4737 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4738 bool RetSExt, bool RetZExt, bool isVarArg,
4739 unsigned CallingConv, bool isTailCall,
4741 ArgListTy &Args, SelectionDAG &DAG) {
4742 SmallVector<SDOperand, 32> Ops;
4743 Ops.push_back(Chain); // Op#0 - Chain
4744 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4745 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4746 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4747 Ops.push_back(Callee);
4749 // Handle all of the outgoing arguments.
4750 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4751 SmallVector<MVT, 4> ValueVTs;
4752 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4753 for (unsigned Value = 0, NumValues = ValueVTs.size();
4754 Value != NumValues; ++Value) {
4755 MVT VT = ValueVTs[Value];
4756 const Type *ArgTy = VT.getTypeForMVT();
4757 SDOperand Op = SDOperand(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4758 ISD::ArgFlagsTy Flags;
4759 unsigned OriginalAlignment =
4760 getTargetData()->getABITypeAlignment(ArgTy);
4766 if (Args[i].isInReg)
4770 if (Args[i].isByVal) {
4772 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4773 const Type *ElementTy = Ty->getElementType();
4774 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4775 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4776 // For ByVal, alignment should come from FE. BE will guess if this
4777 // info is not there but there are cases it cannot get right.
4778 if (Args[i].Alignment)
4779 FrameAlign = Args[i].Alignment;
4780 Flags.setByValAlign(FrameAlign);
4781 Flags.setByValSize(FrameSize);
4785 Flags.setOrigAlign(OriginalAlignment);
4787 MVT PartVT = getRegisterType(VT);
4788 unsigned NumParts = getNumRegisters(VT);
4789 SmallVector<SDOperand, 4> Parts(NumParts);
4790 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4793 ExtendKind = ISD::SIGN_EXTEND;
4794 else if (Args[i].isZExt)
4795 ExtendKind = ISD::ZERO_EXTEND;
4797 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4799 for (unsigned i = 0; i != NumParts; ++i) {
4800 // if it isn't first piece, alignment must be 1
4801 ISD::ArgFlagsTy MyFlags = Flags;
4802 if (NumParts > 1 && i == 0)
4805 MyFlags.setOrigAlign(1);
4807 Ops.push_back(Parts[i]);
4808 Ops.push_back(DAG.getArgFlags(MyFlags));
4813 // Figure out the result value types. We start by making a list of
4814 // the potentially illegal return value types.
4815 SmallVector<MVT, 4> LoweredRetTys;
4816 SmallVector<MVT, 4> RetTys;
4817 ComputeValueVTs(*this, RetTy, RetTys);
4819 // Then we translate that to a list of legal types.
4820 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4822 MVT RegisterVT = getRegisterType(VT);
4823 unsigned NumRegs = getNumRegisters(VT);
4824 for (unsigned i = 0; i != NumRegs; ++i)
4825 LoweredRetTys.push_back(RegisterVT);
4828 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4830 // Create the CALL node.
4831 SDOperand Res = DAG.getNode(ISD::CALL,
4832 DAG.getVTList(&LoweredRetTys[0],
4833 LoweredRetTys.size()),
4834 &Ops[0], Ops.size());
4835 Chain = Res.getValue(LoweredRetTys.size() - 1);
4837 // Gather up the call result into a single value.
4838 if (RetTy != Type::VoidTy) {
4839 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4842 AssertOp = ISD::AssertSext;
4844 AssertOp = ISD::AssertZext;
4846 SmallVector<SDOperand, 4> ReturnValues;
4848 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4850 MVT RegisterVT = getRegisterType(VT);
4851 unsigned NumRegs = getNumRegisters(VT);
4852 unsigned RegNoEnd = NumRegs + RegNo;
4853 SmallVector<SDOperand, 4> Results;
4854 for (; RegNo != RegNoEnd; ++RegNo)
4855 Results.push_back(Res.getValue(RegNo));
4856 SDOperand ReturnValue =
4857 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4859 ReturnValues.push_back(ReturnValue);
4861 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4862 &ReturnValues[0], ReturnValues.size());
4865 return std::make_pair(Res, Chain);
4868 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4869 assert(0 && "LowerOperation not implemented for this target!");
4875 //===----------------------------------------------------------------------===//
4876 // SelectionDAGISel code
4877 //===----------------------------------------------------------------------===//
4879 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4880 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4883 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4884 AU.addRequired<AliasAnalysis>();
4885 AU.addRequired<CollectorModuleMetadata>();
4886 AU.setPreservesAll();
4889 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4890 // Get alias analysis for load/store combining.
4891 AA = &getAnalysis<AliasAnalysis>();
4893 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4894 if (MF.getFunction()->hasCollector())
4895 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4898 RegInfo = &MF.getRegInfo();
4899 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4901 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4903 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4904 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4905 // Mark landing pad.
4906 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4908 SelectAllBasicBlocks(Fn, MF, FuncInfo);
4910 // Add function live-ins to entry block live-in set.
4911 BasicBlock *EntryBB = &Fn.getEntryBlock();
4912 BB = FuncInfo.MBBMap[EntryBB];
4913 if (!RegInfo->livein_empty())
4914 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4915 E = RegInfo->livein_end(); I != E; ++I)
4916 BB->addLiveIn(I->first);
4919 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4920 "Not all catch info was assigned to a landing pad!");
4926 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4927 SDOperand Op = getValue(V);
4928 assert((Op.getOpcode() != ISD::CopyFromReg ||
4929 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4930 "Copy from a reg to the same reg!");
4931 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4933 RegsForValue RFV(TLI, Reg, V->getType());
4934 SDOperand Chain = DAG.getEntryNode();
4935 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4936 PendingExports.push_back(Chain);
4939 void SelectionDAGISel::
4940 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4941 // If this is the entry block, emit arguments.
4942 Function &F = *LLVMBB->getParent();
4943 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4944 SDOperand OldRoot = SDL.DAG.getRoot();
4945 SmallVector<SDOperand, 16> Args;
4946 TLI.LowerArguments(F, SDL.DAG, Args);
4949 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4951 SmallVector<MVT, 4> ValueVTs;
4952 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4953 unsigned NumValues = ValueVTs.size();
4954 if (!AI->use_empty()) {
4955 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
4956 // If this argument is live outside of the entry block, insert a copy from
4957 // whereever we got it to the vreg that other BB's will reference it as.
4958 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4959 if (VMI != FuncInfo.ValueMap.end()) {
4960 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4966 // Finally, if the target has anything special to do, allow it to do so.
4967 // FIXME: this should insert code into the DAG!
4968 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4971 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4972 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4973 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4974 if (isSelector(I)) {
4975 // Apply the catch info to DestBB.
4976 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4978 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4979 FLI.CatchInfoFound.insert(I);
4984 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4985 /// whether object offset >= 0.
4987 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDOperand Op) {
4988 if (!isa<FrameIndexSDNode>(Op)) return false;
4990 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4991 int FrameIdx = FrameIdxNode->getIndex();
4992 return MFI->isFixedObjectIndex(FrameIdx) &&
4993 MFI->getObjectOffset(FrameIdx) >= 0;
4996 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
4997 /// possibly be overwritten when lowering the outgoing arguments in a tail
4998 /// call. Currently the implementation of this call is very conservative and
4999 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
5000 /// virtual registers would be overwritten by direct lowering.
5001 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
5002 MachineFrameInfo * MFI) {
5003 RegisterSDNode * OpReg = NULL;
5004 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
5005 (Op.getOpcode()== ISD::CopyFromReg &&
5006 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
5007 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
5008 (Op.getOpcode() == ISD::LOAD &&
5009 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
5010 (Op.getOpcode() == ISD::MERGE_VALUES &&
5011 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
5012 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
5018 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
5019 /// DAG and fixes their tailcall attribute operand.
5020 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
5021 TargetLowering& TLI) {
5022 SDNode * Ret = NULL;
5023 SDOperand Terminator = DAG.getRoot();
5026 if (Terminator.getOpcode() == ISD::RET) {
5027 Ret = Terminator.Val;
5030 // Fix tail call attribute of CALL nodes.
5031 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5032 BI = DAG.allnodes_end(); BI != BE; ) {
5034 if (BI->getOpcode() == ISD::CALL) {
5035 SDOperand OpRet(Ret, 0);
5036 SDOperand OpCall(BI, 0);
5037 bool isMarkedTailCall =
5038 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5039 // If CALL node has tail call attribute set to true and the call is not
5040 // eligible (no RET or the target rejects) the attribute is fixed to
5041 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5042 // must correctly identify tail call optimizable calls.
5043 if (!isMarkedTailCall) continue;
5045 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5046 // Not eligible. Mark CALL node as non tail call.
5047 SmallVector<SDOperand, 32> Ops;
5049 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5050 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5054 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5056 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5058 // Look for tail call clobbered arguments. Emit a series of
5059 // copyto/copyfrom virtual register nodes to protect them.
5060 SmallVector<SDOperand, 32> Ops;
5061 SDOperand Chain = OpCall.getOperand(0), InFlag;
5063 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5064 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5066 if (idx > 4 && (idx % 2)) {
5067 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5068 getArgFlags().isByVal();
5069 MachineFunction &MF = DAG.getMachineFunction();
5070 MachineFrameInfo *MFI = MF.getFrameInfo();
5072 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5073 MVT VT = Arg.getValueType();
5074 unsigned VReg = MF.getRegInfo().
5075 createVirtualRegister(TLI.getRegClassFor(VT));
5076 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5077 InFlag = Chain.getValue(1);
5078 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5079 Chain = Arg.getValue(1);
5080 InFlag = Arg.getValue(2);
5085 // Link in chain of CopyTo/CopyFromReg.
5087 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5093 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5094 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5095 FunctionLoweringInfo &FuncInfo) {
5096 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
5098 // Lower any arguments needed in this block if this is the entry block.
5099 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5100 LowerArguments(LLVMBB, SDL);
5102 BB = FuncInfo.MBBMap[LLVMBB];
5103 SDL.setCurrentBasicBlock(BB);
5105 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5107 if (MMI && BB->isLandingPad()) {
5108 // Add a label to mark the beginning of the landing pad. Deletion of the
5109 // landing pad can thus be detected via the MachineModuleInfo.
5110 unsigned LabelID = MMI->addLandingPad(BB);
5111 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
5113 // Mark exception register as live in.
5114 unsigned Reg = TLI.getExceptionAddressRegister();
5115 if (Reg) BB->addLiveIn(Reg);
5117 // Mark exception selector register as live in.
5118 Reg = TLI.getExceptionSelectorRegister();
5119 if (Reg) BB->addLiveIn(Reg);
5121 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5122 // function and list of typeids logically belong to the invoke (or, if you
5123 // like, the basic block containing the invoke), and need to be associated
5124 // with it in the dwarf exception handling tables. Currently however the
5125 // information is provided by an intrinsic (eh.selector) that can be moved
5126 // to unexpected places by the optimizers: if the unwind edge is critical,
5127 // then breaking it can result in the intrinsics being in the successor of
5128 // the landing pad, not the landing pad itself. This results in exceptions
5129 // not being caught because no typeids are associated with the invoke.
5130 // This may not be the only way things can go wrong, but it is the only way
5131 // we try to work around for the moment.
5132 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5134 if (Br && Br->isUnconditional()) { // Critical edge?
5135 BasicBlock::iterator I, E;
5136 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5141 // No catch info found - try to extract some from the successor.
5142 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5146 // Lower all of the non-terminator instructions.
5147 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
5151 // Ensure that all instructions which are used outside of their defining
5152 // blocks are available as virtual registers. Invoke is handled elsewhere.
5153 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
5154 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5155 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5156 if (VMI != FuncInfo.ValueMap.end())
5157 SDL.CopyValueToVirtualRegister(I, VMI->second);
5160 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5161 // ensure constants are generated when needed. Remember the virtual registers
5162 // that need to be added to the Machine PHI nodes as input. We cannot just
5163 // directly add them, because expansion might result in multiple MBB's for one
5164 // BB. As such, the start of the BB might correspond to a different MBB than
5167 TerminatorInst *TI = LLVMBB->getTerminator();
5169 // Emit constants only once even if used by multiple PHI nodes.
5170 std::map<Constant*, unsigned> ConstantsOut;
5172 // Vector bool would be better, but vector<bool> is really slow.
5173 std::vector<unsigned char> SuccsHandled;
5174 if (TI->getNumSuccessors())
5175 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5177 // Check successor nodes' PHI nodes that expect a constant to be available
5179 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5180 BasicBlock *SuccBB = TI->getSuccessor(succ);
5181 if (!isa<PHINode>(SuccBB->begin())) continue;
5182 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5184 // If this terminator has multiple identical successors (common for
5185 // switches), only handle each succ once.
5186 unsigned SuccMBBNo = SuccMBB->getNumber();
5187 if (SuccsHandled[SuccMBBNo]) continue;
5188 SuccsHandled[SuccMBBNo] = true;
5190 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5193 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5194 // nodes and Machine PHI nodes, but the incoming operands have not been
5196 for (BasicBlock::iterator I = SuccBB->begin();
5197 (PN = dyn_cast<PHINode>(I)); ++I) {
5198 // Ignore dead phi's.
5199 if (PN->use_empty()) continue;
5202 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5204 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5205 unsigned &RegOut = ConstantsOut[C];
5207 RegOut = FuncInfo.CreateRegForValue(C);
5208 SDL.CopyValueToVirtualRegister(C, RegOut);
5212 Reg = FuncInfo.ValueMap[PHIOp];
5214 assert(isa<AllocaInst>(PHIOp) &&
5215 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5216 "Didn't codegen value into a register!??");
5217 Reg = FuncInfo.CreateRegForValue(PHIOp);
5218 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5222 // Remember that this register needs to added to the machine PHI node as
5223 // the input for this MBB.
5224 MVT VT = TLI.getValueType(PN->getType());
5225 unsigned NumRegisters = TLI.getNumRegisters(VT);
5226 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5227 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5230 ConstantsOut.clear();
5232 // Lower the terminator after the copies are emitted.
5233 SDL.visit(*LLVMBB->getTerminator());
5235 // Copy over any CaseBlock records that may now exist due to SwitchInst
5236 // lowering, as well as any jump table information.
5237 SwitchCases.clear();
5238 SwitchCases = SDL.SwitchCases;
5240 JTCases = SDL.JTCases;
5241 BitTestCases.clear();
5242 BitTestCases = SDL.BitTestCases;
5244 // Make sure the root of the DAG is up-to-date.
5245 DAG.setRoot(SDL.getControlRoot());
5247 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5248 // with correct tailcall attribute so that the target can rely on the tailcall
5249 // attribute indicating whether the call is really eligible for tail call
5251 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5254 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5255 SmallPtrSet<SDNode*, 128> VisitedNodes;
5256 SmallVector<SDNode*, 128> Worklist;
5258 Worklist.push_back(DAG.getRoot().Val);
5264 while (!Worklist.empty()) {
5265 SDNode *N = Worklist.back();
5266 Worklist.pop_back();
5268 // If we've already seen this node, ignore it.
5269 if (!VisitedNodes.insert(N))
5272 // Otherwise, add all chain operands to the worklist.
5273 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5274 if (N->getOperand(i).getValueType() == MVT::Other)
5275 Worklist.push_back(N->getOperand(i).Val);
5277 // If this is a CopyToReg with a vreg dest, process it.
5278 if (N->getOpcode() != ISD::CopyToReg)
5281 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5282 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5285 // Ignore non-scalar or non-integer values.
5286 SDOperand Src = N->getOperand(2);
5287 MVT SrcVT = Src.getValueType();
5288 if (!SrcVT.isInteger() || SrcVT.isVector())
5291 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5292 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5293 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5295 // Only install this information if it tells us something.
5296 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5297 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5298 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5299 if (DestReg >= FLI.LiveOutRegInfo.size())
5300 FLI.LiveOutRegInfo.resize(DestReg+1);
5301 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5302 LOI.NumSignBits = NumSignBits;
5303 LOI.KnownOne = NumSignBits;
5304 LOI.KnownZero = NumSignBits;
5309 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5310 std::string GroupName;
5311 if (TimePassesIsEnabled)
5312 GroupName = "Instruction Selection and Scheduling";
5313 std::string BlockName;
5314 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
5315 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
5316 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' +
5317 BB->getBasicBlock()->getName();
5319 DOUT << "Initial selection DAG:\n";
5322 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName);
5324 // Run the DAG combiner in pre-legalize mode.
5325 if (TimePassesIsEnabled) {
5326 NamedRegionTimer T("DAG Combining 1", GroupName);
5327 DAG.Combine(false, *AA);
5329 DAG.Combine(false, *AA);
5332 DOUT << "Optimized lowered selection DAG:\n";
5335 // Second step, hack on the DAG until it only uses operations and types that
5336 // the target supports.
5337 if (EnableLegalizeTypes) {// Enable this some day.
5338 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " +
5341 if (TimePassesIsEnabled) {
5342 NamedRegionTimer T("Type Legalization", GroupName);
5343 DAG.LegalizeTypes();
5345 DAG.LegalizeTypes();
5348 DOUT << "Type-legalized selection DAG:\n";
5351 // TODO: enable a dag combine pass here.
5354 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName);
5356 if (TimePassesIsEnabled) {
5357 NamedRegionTimer T("DAG Legalization", GroupName);
5363 DOUT << "Legalized selection DAG:\n";
5366 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName);
5368 // Run the DAG combiner in post-legalize mode.
5369 if (TimePassesIsEnabled) {
5370 NamedRegionTimer T("DAG Combining 2", GroupName);
5371 DAG.Combine(true, *AA);
5373 DAG.Combine(true, *AA);
5376 DOUT << "Optimized legalized selection DAG:\n";
5379 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
5381 if (!FastISel && EnableValueProp)
5382 ComputeLiveOutVRegInfo(DAG);
5384 // Third, instruction select all of the operations to machine code, adding the
5385 // code to the MachineBasicBlock.
5386 if (TimePassesIsEnabled) {
5387 NamedRegionTimer T("Instruction Selection", GroupName);
5388 InstructionSelect(DAG);
5390 InstructionSelect(DAG);
5393 DOUT << "Selected selection DAG:\n";
5396 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName);
5398 // Schedule machine code.
5399 ScheduleDAG *Scheduler;
5400 if (TimePassesIsEnabled) {
5401 NamedRegionTimer T("Instruction Scheduling", GroupName);
5402 Scheduler = Schedule(DAG);
5404 Scheduler = Schedule(DAG);
5407 if (ViewSUnitDAGs) Scheduler->viewGraph();
5409 // Emit machine code to BB. This can change 'BB' to the last block being
5411 if (TimePassesIsEnabled) {
5412 NamedRegionTimer T("Instruction Creation", GroupName);
5413 BB = Scheduler->EmitSchedule();
5415 BB = Scheduler->EmitSchedule();
5418 // Free the scheduler state.
5419 if (TimePassesIsEnabled) {
5420 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
5426 // Perform target specific isel post processing.
5427 if (TimePassesIsEnabled) {
5428 NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
5429 InstructionSelectPostProcessing();
5431 InstructionSelectPostProcessing();
5434 DOUT << "Selected machine code:\n";
5438 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
5439 FunctionLoweringInfo &FuncInfo) {
5440 // Define AllNodes here so that memory allocation is reused for
5441 // each basic block.
5442 alist<SDNode, LargestSDNode> AllNodes;
5444 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
5445 SelectBasicBlock(I, MF, FuncInfo, AllNodes);
5450 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5451 FunctionLoweringInfo &FuncInfo,
5452 alist<SDNode, LargestSDNode> &AllNodes) {
5453 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5455 SelectionDAG DAG(TLI, MF, FuncInfo,
5456 getAnalysisToUpdate<MachineModuleInfo>(),
5460 // First step, lower LLVM code to some DAG. This DAG may use operations and
5461 // types that are not supported by the target.
5462 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5464 // Second step, emit the lowered DAG as machine code.
5465 CodeGenAndEmitDAG(DAG);
5468 DOUT << "Total amount of phi nodes to update: "
5469 << PHINodesToUpdate.size() << "\n";
5470 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5471 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5472 << ", " << PHINodesToUpdate[i].second << ")\n";);
5474 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5475 // PHI nodes in successors.
5476 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5477 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5478 MachineInstr *PHI = PHINodesToUpdate[i].first;
5479 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5480 "This is not a machine PHI node that we are updating!");
5481 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5483 PHI->addOperand(MachineOperand::CreateMBB(BB));
5488 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5489 // Lower header first, if it wasn't already lowered
5490 if (!BitTestCases[i].Emitted) {
5491 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5492 getAnalysisToUpdate<MachineModuleInfo>(),
5495 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5496 // Set the current basic block to the mbb we wish to insert the code into
5497 BB = BitTestCases[i].Parent;
5498 HSDL.setCurrentBasicBlock(BB);
5500 HSDL.visitBitTestHeader(BitTestCases[i]);
5501 HSDAG.setRoot(HSDL.getRoot());
5502 CodeGenAndEmitDAG(HSDAG);
5505 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5506 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5507 getAnalysisToUpdate<MachineModuleInfo>(),
5510 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5511 // Set the current basic block to the mbb we wish to insert the code into
5512 BB = BitTestCases[i].Cases[j].ThisBB;
5513 BSDL.setCurrentBasicBlock(BB);
5516 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5517 BitTestCases[i].Reg,
5518 BitTestCases[i].Cases[j]);
5520 BSDL.visitBitTestCase(BitTestCases[i].Default,
5521 BitTestCases[i].Reg,
5522 BitTestCases[i].Cases[j]);
5525 BSDAG.setRoot(BSDL.getRoot());
5526 CodeGenAndEmitDAG(BSDAG);
5530 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5531 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5532 MachineBasicBlock *PHIBB = PHI->getParent();
5533 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5534 "This is not a machine PHI node that we are updating!");
5535 // This is "default" BB. We have two jumps to it. From "header" BB and
5536 // from last "case" BB.
5537 if (PHIBB == BitTestCases[i].Default) {
5538 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5540 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5541 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5543 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5546 // One of "cases" BB.
5547 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5548 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5549 if (cBB->succ_end() !=
5550 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5551 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5553 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5559 // If the JumpTable record is filled in, then we need to emit a jump table.
5560 // Updating the PHI nodes is tricky in this case, since we need to determine
5561 // whether the PHI is a successor of the range check MBB or the jump table MBB
5562 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5563 // Lower header first, if it wasn't already lowered
5564 if (!JTCases[i].first.Emitted) {
5565 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5566 getAnalysisToUpdate<MachineModuleInfo>(),
5569 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5570 // Set the current basic block to the mbb we wish to insert the code into
5571 BB = JTCases[i].first.HeaderBB;
5572 HSDL.setCurrentBasicBlock(BB);
5574 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5575 HSDAG.setRoot(HSDL.getRoot());
5576 CodeGenAndEmitDAG(HSDAG);
5579 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5580 getAnalysisToUpdate<MachineModuleInfo>(),
5583 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5584 // Set the current basic block to the mbb we wish to insert the code into
5585 BB = JTCases[i].second.MBB;
5586 JSDL.setCurrentBasicBlock(BB);
5588 JSDL.visitJumpTable(JTCases[i].second);
5589 JSDAG.setRoot(JSDL.getRoot());
5590 CodeGenAndEmitDAG(JSDAG);
5593 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5594 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5595 MachineBasicBlock *PHIBB = PHI->getParent();
5596 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5597 "This is not a machine PHI node that we are updating!");
5598 // "default" BB. We can go there only from header BB.
5599 if (PHIBB == JTCases[i].second.Default) {
5600 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5602 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5604 // JT BB. Just iterate over successors here
5605 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5606 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5608 PHI->addOperand(MachineOperand::CreateMBB(BB));
5613 // If the switch block involved a branch to one of the actual successors, we
5614 // need to update PHI nodes in that block.
5615 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5616 MachineInstr *PHI = PHINodesToUpdate[i].first;
5617 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5618 "This is not a machine PHI node that we are updating!");
5619 if (BB->isSuccessor(PHI->getParent())) {
5620 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5622 PHI->addOperand(MachineOperand::CreateMBB(BB));
5626 // If we generated any switch lowering information, build and codegen any
5627 // additional DAGs necessary.
5628 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5629 SelectionDAG SDAG(TLI, MF, FuncInfo,
5630 getAnalysisToUpdate<MachineModuleInfo>(),
5633 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5635 // Set the current basic block to the mbb we wish to insert the code into
5636 BB = SwitchCases[i].ThisBB;
5637 SDL.setCurrentBasicBlock(BB);
5640 SDL.visitSwitchCase(SwitchCases[i]);
5641 SDAG.setRoot(SDL.getRoot());
5642 CodeGenAndEmitDAG(SDAG);
5644 // Handle any PHI nodes in successors of this chunk, as if we were coming
5645 // from the original BB before switch expansion. Note that PHI nodes can
5646 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5647 // handle them the right number of times.
5648 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5649 for (MachineBasicBlock::iterator Phi = BB->begin();
5650 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5651 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5652 for (unsigned pn = 0; ; ++pn) {
5653 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5654 if (PHINodesToUpdate[pn].first == Phi) {
5655 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5657 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5663 // Don't process RHS if same block as LHS.
5664 if (BB == SwitchCases[i].FalseBB)
5665 SwitchCases[i].FalseBB = 0;
5667 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5668 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5669 SwitchCases[i].FalseBB = 0;
5671 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5676 /// Schedule - Pick a safe ordering for instructions for each
5677 /// target node in the graph.
5679 ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
5680 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5684 RegisterScheduler::setDefault(Ctor);
5687 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
5694 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5695 return new HazardRecognizer();
5698 //===----------------------------------------------------------------------===//
5699 // Helper functions used by the generated instruction selector.
5700 //===----------------------------------------------------------------------===//
5701 // Calls to these methods are generated by tblgen.
5703 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5704 /// the dag combiner simplified the 255, we still want to match. RHS is the
5705 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5706 /// specified in the .td file (e.g. 255).
5707 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5708 int64_t DesiredMaskS) const {
5709 const APInt &ActualMask = RHS->getAPIntValue();
5710 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5712 // If the actual mask exactly matches, success!
5713 if (ActualMask == DesiredMask)
5716 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5717 if (ActualMask.intersects(~DesiredMask))
5720 // Otherwise, the DAG Combiner may have proven that the value coming in is
5721 // either already zero or is not demanded. Check for known zero input bits.
5722 APInt NeededMask = DesiredMask & ~ActualMask;
5723 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5726 // TODO: check to see if missing bits are just not demanded.
5728 // Otherwise, this pattern doesn't match.
5732 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5733 /// the dag combiner simplified the 255, we still want to match. RHS is the
5734 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5735 /// specified in the .td file (e.g. 255).
5736 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5737 int64_t DesiredMaskS) const {
5738 const APInt &ActualMask = RHS->getAPIntValue();
5739 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5741 // If the actual mask exactly matches, success!
5742 if (ActualMask == DesiredMask)
5745 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5746 if (ActualMask.intersects(~DesiredMask))
5749 // Otherwise, the DAG Combiner may have proven that the value coming in is
5750 // either already zero or is not demanded. Check for known zero input bits.
5751 APInt NeededMask = DesiredMask & ~ActualMask;
5753 APInt KnownZero, KnownOne;
5754 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5756 // If all the missing bits in the or are already known to be set, match!
5757 if ((NeededMask & KnownOne) == NeededMask)
5760 // TODO: check to see if missing bits are just not demanded.
5762 // Otherwise, this pattern doesn't match.
5767 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5768 /// by tblgen. Others should not call it.
5769 void SelectionDAGISel::
5770 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5771 std::vector<SDOperand> InOps;
5772 std::swap(InOps, Ops);
5774 Ops.push_back(InOps[0]); // input chain.
5775 Ops.push_back(InOps[1]); // input asm string.
5777 unsigned i = 2, e = InOps.size();
5778 if (InOps[e-1].getValueType() == MVT::Flag)
5779 --e; // Don't process a flag operand if it is here.
5782 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5783 if ((Flags & 7) != 4 /*MEM*/) {
5784 // Just skip over this operand, copying the operands verbatim.
5785 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5786 i += (Flags >> 3) + 1;
5788 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5789 // Otherwise, this is a memory operand. Ask the target to select it.
5790 std::vector<SDOperand> SelOps;
5791 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5792 cerr << "Could not match memory address. Inline asm failure!\n";
5796 // Add this to the output node.
5797 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5798 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5800 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5805 // Add the flag input back if present.
5806 if (e != InOps.size())
5807 Ops.push_back(InOps.back());
5810 char SelectionDAGISel::ID = 0;