1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "SimpleBBISel.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/ScheduleDAG.h"
37 #include "llvm/CodeGen/SchedulerRegistry.h"
38 #include "llvm/CodeGen/SelectionDAG.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetData.h"
41 #include "llvm/Target/TargetFrameInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/MathExtras.h"
49 #include "llvm/Support/Timer.h"
54 EnableValueProp("enable-value-prop", cl::Hidden);
56 EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
61 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
62 cl::desc("Pop up a window to show dags before the first "
65 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
66 cl::desc("Pop up a window to show dags before legalize types"));
68 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before legalize"));
71 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
72 cl::desc("Pop up a window to show dags before the second "
75 ViewISelDAGs("view-isel-dags", cl::Hidden,
76 cl::desc("Pop up a window to show isel dags as they are selected"));
78 ViewSchedDAGs("view-sched-dags", cl::Hidden,
79 cl::desc("Pop up a window to show sched dags as they are processed"));
81 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
82 cl::desc("Pop up a window to show SUnit dags after they are processed"));
84 static const bool ViewDAGCombine1 = false,
85 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
86 ViewDAGCombine2 = false,
87 ViewISelDAGs = false, ViewSchedDAGs = false,
88 ViewSUnitDAGs = false;
91 //===---------------------------------------------------------------------===//
93 /// RegisterScheduler class - Track the registration of instruction schedulers.
95 //===---------------------------------------------------------------------===//
96 MachinePassRegistry RegisterScheduler::Registry;
98 //===---------------------------------------------------------------------===//
100 /// ISHeuristic command line option for instruction schedulers.
102 //===---------------------------------------------------------------------===//
103 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
104 RegisterPassParser<RegisterScheduler> >
105 ISHeuristic("pre-RA-sched",
106 cl::init(&createDefaultScheduler),
107 cl::desc("Instruction schedulers available (before register"
110 static RegisterScheduler
111 defaultListDAGScheduler("default", " Best scheduler for the target",
112 createDefaultScheduler);
114 namespace { struct SDISelAsmOperandInfo; }
116 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
117 /// insertvalue or extractvalue indices that identify a member, return
118 /// the linearized index of the start of the member.
120 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
121 const unsigned *Indices,
122 const unsigned *IndicesEnd,
123 unsigned CurIndex = 0) {
124 // Base case: We're done.
125 if (Indices && Indices == IndicesEnd)
128 // Given a struct type, recursively traverse the elements.
129 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
130 for (StructType::element_iterator EB = STy->element_begin(),
132 EE = STy->element_end();
134 if (Indices && *Indices == unsigned(EI - EB))
135 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
136 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
139 // Given an array type, recursively traverse the elements.
140 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
141 const Type *EltTy = ATy->getElementType();
142 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
143 if (Indices && *Indices == i)
144 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
145 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
148 // We haven't found the type we're looking for, so keep searching.
152 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
153 /// MVTs that represent all the individual underlying
154 /// non-aggregate types that comprise it.
156 /// If Offsets is non-null, it points to a vector to be filled in
157 /// with the in-memory offsets of each of the individual values.
159 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
160 SmallVectorImpl<MVT> &ValueVTs,
161 SmallVectorImpl<uint64_t> *Offsets = 0,
162 uint64_t StartingOffset = 0) {
163 // Given a struct type, recursively traverse the elements.
164 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
165 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
166 for (StructType::element_iterator EB = STy->element_begin(),
168 EE = STy->element_end();
170 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
171 StartingOffset + SL->getElementOffset(EI - EB));
174 // Given an array type, recursively traverse the elements.
175 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
176 const Type *EltTy = ATy->getElementType();
177 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
178 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
179 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
180 StartingOffset + i * EltSize);
183 // Base case: we can get an MVT for this LLVM IR type.
184 ValueVTs.push_back(TLI.getValueType(Ty));
186 Offsets->push_back(StartingOffset);
190 /// RegsForValue - This struct represents the registers (physical or virtual)
191 /// that a particular set of values is assigned, and the type information about
192 /// the value. The most common situation is to represent one value at a time,
193 /// but struct or array values are handled element-wise as multiple values.
194 /// The splitting of aggregates is performed recursively, so that we never
195 /// have aggregate-typed registers. The values at this point do not necessarily
196 /// have legal types, so each value may require one or more registers of some
199 struct VISIBILITY_HIDDEN RegsForValue {
200 /// TLI - The TargetLowering object.
202 const TargetLowering *TLI;
204 /// ValueVTs - The value types of the values, which may not be legal, and
205 /// may need be promoted or synthesized from one or more registers.
207 SmallVector<MVT, 4> ValueVTs;
209 /// RegVTs - The value types of the registers. This is the same size as
210 /// ValueVTs and it records, for each value, what the type of the assigned
211 /// register or registers are. (Individual values are never synthesized
212 /// from more than one type of register.)
214 /// With virtual registers, the contents of RegVTs is redundant with TLI's
215 /// getRegisterType member function, however when with physical registers
216 /// it is necessary to have a separate record of the types.
218 SmallVector<MVT, 4> RegVTs;
220 /// Regs - This list holds the registers assigned to the values.
221 /// Each legal or promoted value requires one register, and each
222 /// expanded value requires multiple registers.
224 SmallVector<unsigned, 4> Regs;
226 RegsForValue() : TLI(0) {}
228 RegsForValue(const TargetLowering &tli,
229 const SmallVector<unsigned, 4> ®s,
230 MVT regvt, MVT valuevt)
231 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
232 RegsForValue(const TargetLowering &tli,
233 const SmallVector<unsigned, 4> ®s,
234 const SmallVector<MVT, 4> ®vts,
235 const SmallVector<MVT, 4> &valuevts)
236 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
237 RegsForValue(const TargetLowering &tli,
238 unsigned Reg, const Type *Ty) : TLI(&tli) {
239 ComputeValueVTs(tli, Ty, ValueVTs);
241 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
242 MVT ValueVT = ValueVTs[Value];
243 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
244 MVT RegisterVT = TLI->getRegisterType(ValueVT);
245 for (unsigned i = 0; i != NumRegs; ++i)
246 Regs.push_back(Reg + i);
247 RegVTs.push_back(RegisterVT);
252 /// append - Add the specified values to this one.
253 void append(const RegsForValue &RHS) {
255 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
256 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
257 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
261 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
262 /// this value and returns the result as a ValueVTs value. This uses
263 /// Chain/Flag as the input and updates them for the output Chain/Flag.
264 /// If the Flag pointer is NULL, no flag is used.
265 SDValue getCopyFromRegs(SelectionDAG &DAG,
266 SDValue &Chain, SDValue *Flag) const;
268 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
269 /// specified value into the registers specified by this object. This uses
270 /// Chain/Flag as the input and updates them for the output Chain/Flag.
271 /// If the Flag pointer is NULL, no flag is used.
272 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
273 SDValue &Chain, SDValue *Flag) const;
275 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
276 /// operand list. This adds the code marker and includes the number of
277 /// values added into it.
278 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
279 std::vector<SDValue> &Ops) const;
284 //===--------------------------------------------------------------------===//
285 /// createDefaultScheduler - This creates an instruction scheduler appropriate
287 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
289 MachineBasicBlock *BB,
291 TargetLowering &TLI = IS->getTargetLowering();
293 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
294 return createTDListDAGScheduler(IS, DAG, BB, Fast);
296 assert(TLI.getSchedulingPreference() ==
297 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
298 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
303 //===--------------------------------------------------------------------===//
304 /// FunctionLoweringInfo - This contains information that is global to a
305 /// function that is used when lowering a region of the function.
306 class FunctionLoweringInfo {
311 MachineRegisterInfo &RegInfo;
313 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
315 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
316 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
318 /// ValueMap - Since we emit code for the function a basic block at a time,
319 /// we must remember which virtual registers hold the values for
320 /// cross-basic-block values.
321 DenseMap<const Value*, unsigned> ValueMap;
323 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
324 /// the entry block. This allows the allocas to be efficiently referenced
325 /// anywhere in the function.
326 std::map<const AllocaInst*, int> StaticAllocaMap;
329 SmallSet<Instruction*, 8> CatchInfoLost;
330 SmallSet<Instruction*, 8> CatchInfoFound;
333 unsigned MakeReg(MVT VT) {
334 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
337 /// isExportedInst - Return true if the specified value is an instruction
338 /// exported from its block.
339 bool isExportedInst(const Value *V) {
340 return ValueMap.count(V);
343 unsigned CreateRegForValue(const Value *V);
345 unsigned InitializeRegForValue(const Value *V) {
346 unsigned &R = ValueMap[V];
347 assert(R == 0 && "Already initialized this value register!");
348 return R = CreateRegForValue(V);
352 unsigned NumSignBits;
353 APInt KnownOne, KnownZero;
354 LiveOutInfo() : NumSignBits(0) {}
357 /// LiveOutRegInfo - Information about live out vregs, indexed by their
358 /// register number offset by 'FirstVirtualRegister'.
359 std::vector<LiveOutInfo> LiveOutRegInfo;
363 /// isSelector - Return true if this instruction is a call to the
364 /// eh.selector intrinsic.
365 static bool isSelector(Instruction *I) {
366 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
367 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
368 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
372 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
373 /// PHI nodes or outside of the basic block that defines it, or used by a
374 /// switch or atomic instruction, which may expand to multiple basic blocks.
375 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
376 if (isa<PHINode>(I)) return true;
377 BasicBlock *BB = I->getParent();
378 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
379 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
380 // FIXME: Remove switchinst special case.
381 isa<SwitchInst>(*UI))
386 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
387 /// entry block, return true. This includes arguments used by switches, since
388 /// the switch may expand into multiple basic blocks.
389 static bool isOnlyUsedInEntryBlock(Argument *A) {
390 BasicBlock *Entry = A->getParent()->begin();
391 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
392 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
393 return false; // Use not in entry block.
397 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
398 Function &fn, MachineFunction &mf)
399 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
401 // Create a vreg for each argument register that is not dead and is used
402 // outside of the entry block for the function.
403 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
405 if (!isOnlyUsedInEntryBlock(AI))
406 InitializeRegForValue(AI);
408 // Initialize the mapping of values to registers. This is only set up for
409 // instruction values that are used outside of the block that defines
411 Function::iterator BB = Fn.begin(), EB = Fn.end();
412 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
413 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
414 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
415 const Type *Ty = AI->getAllocatedType();
416 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
418 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
421 TySize *= CUI->getZExtValue(); // Get total allocated size.
422 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
423 StaticAllocaMap[AI] =
424 MF.getFrameInfo()->CreateStackObject(TySize, Align);
427 for (; BB != EB; ++BB)
428 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
429 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
430 if (!isa<AllocaInst>(I) ||
431 !StaticAllocaMap.count(cast<AllocaInst>(I)))
432 InitializeRegForValue(I);
434 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
435 // also creates the initial PHI MachineInstrs, though none of the input
436 // operands are populated.
437 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
438 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
442 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
445 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
446 if (PN->use_empty()) continue;
448 unsigned PHIReg = ValueMap[PN];
449 assert(PHIReg && "PHI node does not have an assigned virtual register!");
451 SmallVector<MVT, 4> ValueVTs;
452 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
453 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
454 MVT VT = ValueVTs[vti];
455 unsigned NumRegisters = TLI.getNumRegisters(VT);
456 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
457 for (unsigned i = 0; i != NumRegisters; ++i)
458 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
459 PHIReg += NumRegisters;
465 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
466 /// the correctly promoted or expanded types. Assign these registers
467 /// consecutive vreg numbers and return the first assigned number.
469 /// In the case that the given value has struct or array type, this function
470 /// will assign registers for each member or element.
472 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
473 SmallVector<MVT, 4> ValueVTs;
474 ComputeValueVTs(TLI, V->getType(), ValueVTs);
476 unsigned FirstReg = 0;
477 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
478 MVT ValueVT = ValueVTs[Value];
479 MVT RegisterVT = TLI.getRegisterType(ValueVT);
481 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
482 for (unsigned i = 0; i != NumRegs; ++i) {
483 unsigned R = MakeReg(RegisterVT);
484 if (!FirstReg) FirstReg = R;
490 //===----------------------------------------------------------------------===//
491 /// SelectionDAGLowering - This is the common target-independent lowering
492 /// implementation that is parameterized by a TargetLowering object.
493 /// Also, targets can overload any lowering method.
496 class SelectionDAGLowering {
497 MachineBasicBlock *CurMBB;
499 DenseMap<const Value*, SDValue> NodeMap;
501 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
502 /// them up and then emit token factor nodes when possible. This allows us to
503 /// get simple disambiguation between loads without worrying about alias
505 SmallVector<SDValue, 8> PendingLoads;
507 /// PendingExports - CopyToReg nodes that copy values to virtual registers
508 /// for export to other blocks need to be emitted before any terminator
509 /// instruction, but they have no other ordering requirements. We bunch them
510 /// up and the emit a single tokenfactor for them just before terminator
512 std::vector<SDValue> PendingExports;
514 /// Case - A struct to record the Value for a switch case, and the
515 /// case's target basic block.
519 MachineBasicBlock* BB;
521 Case() : Low(0), High(0), BB(0) { }
522 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
523 Low(low), High(high), BB(bb) { }
524 uint64_t size() const {
525 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
526 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
527 return (rHigh - rLow + 1ULL);
533 MachineBasicBlock* BB;
536 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
537 Mask(mask), BB(bb), Bits(bits) { }
540 typedef std::vector<Case> CaseVector;
541 typedef std::vector<CaseBits> CaseBitsVector;
542 typedef CaseVector::iterator CaseItr;
543 typedef std::pair<CaseItr, CaseItr> CaseRange;
545 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
546 /// of conditional branches.
548 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
549 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
551 /// CaseBB - The MBB in which to emit the compare and branch
552 MachineBasicBlock *CaseBB;
553 /// LT, GE - If nonzero, we know the current case value must be less-than or
554 /// greater-than-or-equal-to these Constants.
557 /// Range - A pair of iterators representing the range of case values to be
558 /// processed at this point in the binary search tree.
562 typedef std::vector<CaseRec> CaseRecVector;
564 /// The comparison function for sorting the switch case values in the vector.
565 /// WARNING: Case ranges should be disjoint!
567 bool operator () (const Case& C1, const Case& C2) {
568 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
569 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
570 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
571 return CI1->getValue().slt(CI2->getValue());
576 bool operator () (const CaseBits& C1, const CaseBits& C2) {
577 return C1.Bits > C2.Bits;
581 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
584 // TLI - This is information that describes the available target features we
585 // need for lowering. This indicates when operations are unavailable,
586 // implemented with a libcall, etc.
589 const TargetData *TD;
592 /// SwitchCases - Vector of CaseBlock structures used to communicate
593 /// SwitchInst code generation information.
594 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
595 /// JTCases - Vector of JumpTable structures used to communicate
596 /// SwitchInst code generation information.
597 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
598 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
600 /// FuncInfo - Information about the function as a whole.
602 FunctionLoweringInfo &FuncInfo;
604 /// GCI - Garbage collection metadata for the function.
605 CollectorMetadata *GCI;
607 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
609 FunctionLoweringInfo &funcinfo,
610 CollectorMetadata *gci)
611 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
612 FuncInfo(funcinfo), GCI(gci) {
615 /// getRoot - Return the current virtual root of the Selection DAG,
616 /// flushing any PendingLoad items. This must be done before emitting
617 /// a store or any other node that may need to be ordered after any
618 /// prior load instructions.
621 if (PendingLoads.empty())
622 return DAG.getRoot();
624 if (PendingLoads.size() == 1) {
625 SDValue Root = PendingLoads[0];
627 PendingLoads.clear();
631 // Otherwise, we have to make a token factor node.
632 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
633 &PendingLoads[0], PendingLoads.size());
634 PendingLoads.clear();
639 /// getControlRoot - Similar to getRoot, but instead of flushing all the
640 /// PendingLoad items, flush all the PendingExports items. It is necessary
641 /// to do this before emitting a terminator instruction.
643 SDValue getControlRoot() {
644 SDValue Root = DAG.getRoot();
646 if (PendingExports.empty())
649 // Turn all of the CopyToReg chains into one factored node.
650 if (Root.getOpcode() != ISD::EntryToken) {
651 unsigned i = 0, e = PendingExports.size();
652 for (; i != e; ++i) {
653 assert(PendingExports[i].Val->getNumOperands() > 1);
654 if (PendingExports[i].Val->getOperand(0) == Root)
655 break; // Don't add the root if we already indirectly depend on it.
659 PendingExports.push_back(Root);
662 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
664 PendingExports.size());
665 PendingExports.clear();
670 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
672 void visit(Instruction &I) { visit(I.getOpcode(), I); }
674 void visit(unsigned Opcode, User &I) {
675 // Note: this doesn't use InstVisitor, because it has to work with
676 // ConstantExpr's in addition to instructions.
678 default: assert(0 && "Unknown instruction type encountered!");
680 // Build the switch statement using the Instruction.def file.
681 #define HANDLE_INST(NUM, OPCODE, CLASS) \
682 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
683 #include "llvm/Instruction.def"
687 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
689 SDValue getValue(const Value *V);
691 void setValue(const Value *V, SDValue NewN) {
692 SDValue &N = NodeMap[V];
693 assert(N.Val == 0 && "Already set a value for this node!");
697 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
698 std::set<unsigned> &OutputRegs,
699 std::set<unsigned> &InputRegs);
701 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
702 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
704 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
705 void ExportFromCurrentBlock(Value *V);
706 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
707 MachineBasicBlock *LandingPad = NULL);
709 // Terminator instructions.
710 void visitRet(ReturnInst &I);
711 void visitBr(BranchInst &I);
712 void visitSwitch(SwitchInst &I);
713 void visitUnreachable(UnreachableInst &I) { /* noop */ }
715 // Helpers for visitSwitch
716 bool handleSmallSwitchRange(CaseRec& CR,
717 CaseRecVector& WorkList,
719 MachineBasicBlock* Default);
720 bool handleJTSwitchCase(CaseRec& CR,
721 CaseRecVector& WorkList,
723 MachineBasicBlock* Default);
724 bool handleBTSplitSwitchCase(CaseRec& CR,
725 CaseRecVector& WorkList,
727 MachineBasicBlock* Default);
728 bool handleBitTestsSwitchCase(CaseRec& CR,
729 CaseRecVector& WorkList,
731 MachineBasicBlock* Default);
732 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
733 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
734 void visitBitTestCase(MachineBasicBlock* NextMBB,
736 SelectionDAGISel::BitTestCase &B);
737 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
738 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
739 SelectionDAGISel::JumpTableHeader &JTH);
741 // These all get lowered before this pass.
742 void visitInvoke(InvokeInst &I);
743 void visitUnwind(UnwindInst &I);
745 void visitBinary(User &I, unsigned OpCode);
746 void visitShift(User &I, unsigned Opcode);
747 void visitAdd(User &I) {
748 if (I.getType()->isFPOrFPVector())
749 visitBinary(I, ISD::FADD);
751 visitBinary(I, ISD::ADD);
753 void visitSub(User &I);
754 void visitMul(User &I) {
755 if (I.getType()->isFPOrFPVector())
756 visitBinary(I, ISD::FMUL);
758 visitBinary(I, ISD::MUL);
760 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
761 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
762 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
763 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
764 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
765 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
766 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
767 void visitOr (User &I) { visitBinary(I, ISD::OR); }
768 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
769 void visitShl (User &I) { visitShift(I, ISD::SHL); }
770 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
771 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
772 void visitICmp(User &I);
773 void visitFCmp(User &I);
774 void visitVICmp(User &I);
775 void visitVFCmp(User &I);
776 // Visit the conversion instructions
777 void visitTrunc(User &I);
778 void visitZExt(User &I);
779 void visitSExt(User &I);
780 void visitFPTrunc(User &I);
781 void visitFPExt(User &I);
782 void visitFPToUI(User &I);
783 void visitFPToSI(User &I);
784 void visitUIToFP(User &I);
785 void visitSIToFP(User &I);
786 void visitPtrToInt(User &I);
787 void visitIntToPtr(User &I);
788 void visitBitCast(User &I);
790 void visitExtractElement(User &I);
791 void visitInsertElement(User &I);
792 void visitShuffleVector(User &I);
794 void visitExtractValue(ExtractValueInst &I);
795 void visitInsertValue(InsertValueInst &I);
797 void visitGetElementPtr(User &I);
798 void visitSelect(User &I);
800 void visitMalloc(MallocInst &I);
801 void visitFree(FreeInst &I);
802 void visitAlloca(AllocaInst &I);
803 void visitLoad(LoadInst &I);
804 void visitStore(StoreInst &I);
805 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
806 void visitCall(CallInst &I);
807 void visitInlineAsm(CallSite CS);
808 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
809 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
811 void visitVAStart(CallInst &I);
812 void visitVAArg(VAArgInst &I);
813 void visitVAEnd(CallInst &I);
814 void visitVACopy(CallInst &I);
816 void visitUserOp1(Instruction &I) {
817 assert(0 && "UserOp1 should not exist at instruction selection time!");
820 void visitUserOp2(Instruction &I) {
821 assert(0 && "UserOp2 should not exist at instruction selection time!");
826 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
829 } // end namespace llvm
832 /// getCopyFromParts - Create a value that contains the specified legal parts
833 /// combined into the value they represent. If the parts combine to a type
834 /// larger then ValueVT then AssertOp can be used to specify whether the extra
835 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
836 /// (ISD::AssertSext).
837 static SDValue getCopyFromParts(SelectionDAG &DAG,
838 const SDValue *Parts,
842 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
843 assert(NumParts > 0 && "No parts to assemble!");
844 TargetLowering &TLI = DAG.getTargetLoweringInfo();
845 SDValue Val = Parts[0];
848 // Assemble the value from multiple parts.
849 if (!ValueVT.isVector()) {
850 unsigned PartBits = PartVT.getSizeInBits();
851 unsigned ValueBits = ValueVT.getSizeInBits();
853 // Assemble the power of 2 part.
854 unsigned RoundParts = NumParts & (NumParts - 1) ?
855 1 << Log2_32(NumParts) : NumParts;
856 unsigned RoundBits = PartBits * RoundParts;
857 MVT RoundVT = RoundBits == ValueBits ?
858 ValueVT : MVT::getIntegerVT(RoundBits);
861 if (RoundParts > 2) {
862 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
863 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
864 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
870 if (TLI.isBigEndian())
872 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
874 if (RoundParts < NumParts) {
875 // Assemble the trailing non-power-of-2 part.
876 unsigned OddParts = NumParts - RoundParts;
877 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
878 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
880 // Combine the round and odd parts.
882 if (TLI.isBigEndian())
884 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
885 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
886 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
887 DAG.getConstant(Lo.getValueType().getSizeInBits(),
888 TLI.getShiftAmountTy()));
889 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
890 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
893 // Handle a multi-element vector.
894 MVT IntermediateVT, RegisterVT;
895 unsigned NumIntermediates;
897 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
899 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
900 NumParts = NumRegs; // Silence a compiler warning.
901 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
902 assert(RegisterVT == Parts[0].getValueType() &&
903 "Part type doesn't match part!");
905 // Assemble the parts into intermediate operands.
906 SmallVector<SDValue, 8> Ops(NumIntermediates);
907 if (NumIntermediates == NumParts) {
908 // If the register was not expanded, truncate or copy the value,
910 for (unsigned i = 0; i != NumParts; ++i)
911 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
912 PartVT, IntermediateVT);
913 } else if (NumParts > 0) {
914 // If the intermediate type was expanded, build the intermediate operands
916 assert(NumParts % NumIntermediates == 0 &&
917 "Must expand into a divisible number of parts!");
918 unsigned Factor = NumParts / NumIntermediates;
919 for (unsigned i = 0; i != NumIntermediates; ++i)
920 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
921 PartVT, IntermediateVT);
924 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
926 Val = DAG.getNode(IntermediateVT.isVector() ?
927 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
928 ValueVT, &Ops[0], NumIntermediates);
932 // There is now one part, held in Val. Correct it to match ValueVT.
933 PartVT = Val.getValueType();
935 if (PartVT == ValueVT)
938 if (PartVT.isVector()) {
939 assert(ValueVT.isVector() && "Unknown vector conversion!");
940 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
943 if (ValueVT.isVector()) {
944 assert(ValueVT.getVectorElementType() == PartVT &&
945 ValueVT.getVectorNumElements() == 1 &&
946 "Only trivial scalar-to-vector conversions should get here!");
947 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
950 if (PartVT.isInteger() &&
951 ValueVT.isInteger()) {
952 if (ValueVT.bitsLT(PartVT)) {
953 // For a truncate, see if we have any information to
954 // indicate whether the truncated bits will always be
955 // zero or sign-extension.
956 if (AssertOp != ISD::DELETED_NODE)
957 Val = DAG.getNode(AssertOp, PartVT, Val,
958 DAG.getValueType(ValueVT));
959 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
961 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
965 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
966 if (ValueVT.bitsLT(Val.getValueType()))
967 // FP_ROUND's are always exact here.
968 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
969 DAG.getIntPtrConstant(1));
970 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
973 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
974 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
976 assert(0 && "Unknown mismatch!");
980 /// getCopyToParts - Create a series of nodes that contain the specified value
981 /// split into legal parts. If the parts contain more bits than Val, then, for
982 /// integers, ExtendKind can be used to specify how to generate the extra bits.
983 static void getCopyToParts(SelectionDAG &DAG,
988 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
989 TargetLowering &TLI = DAG.getTargetLoweringInfo();
990 MVT PtrVT = TLI.getPointerTy();
991 MVT ValueVT = Val.getValueType();
992 unsigned PartBits = PartVT.getSizeInBits();
993 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
998 if (!ValueVT.isVector()) {
999 if (PartVT == ValueVT) {
1000 assert(NumParts == 1 && "No-op copy with multiple parts!");
1005 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
1006 // If the parts cover more bits than the value has, promote the value.
1007 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
1008 assert(NumParts == 1 && "Do not know what to promote to!");
1009 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
1010 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
1011 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1012 Val = DAG.getNode(ExtendKind, ValueVT, Val);
1014 assert(0 && "Unknown mismatch!");
1016 } else if (PartBits == ValueVT.getSizeInBits()) {
1017 // Different types of the same size.
1018 assert(NumParts == 1 && PartVT != ValueVT);
1019 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1020 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
1021 // If the parts cover less bits than value has, truncate the value.
1022 if (PartVT.isInteger() && ValueVT.isInteger()) {
1023 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1024 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1026 assert(0 && "Unknown mismatch!");
1030 // The value may have changed - recompute ValueVT.
1031 ValueVT = Val.getValueType();
1032 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1033 "Failed to tile the value with PartVT!");
1035 if (NumParts == 1) {
1036 assert(PartVT == ValueVT && "Type conversion failed!");
1041 // Expand the value into multiple parts.
1042 if (NumParts & (NumParts - 1)) {
1043 // The number of parts is not a power of 2. Split off and copy the tail.
1044 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1045 "Do not know what to expand to!");
1046 unsigned RoundParts = 1 << Log2_32(NumParts);
1047 unsigned RoundBits = RoundParts * PartBits;
1048 unsigned OddParts = NumParts - RoundParts;
1049 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1050 DAG.getConstant(RoundBits,
1051 TLI.getShiftAmountTy()));
1052 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1053 if (TLI.isBigEndian())
1054 // The odd parts were reversed by getCopyToParts - unreverse them.
1055 std::reverse(Parts + RoundParts, Parts + NumParts);
1056 NumParts = RoundParts;
1057 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1058 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1061 // The number of parts is a power of 2. Repeatedly bisect the value using
1063 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1064 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1066 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1067 for (unsigned i = 0; i < NumParts; i += StepSize) {
1068 unsigned ThisBits = StepSize * PartBits / 2;
1069 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1070 SDValue &Part0 = Parts[i];
1071 SDValue &Part1 = Parts[i+StepSize/2];
1073 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1074 DAG.getConstant(1, PtrVT));
1075 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1076 DAG.getConstant(0, PtrVT));
1078 if (ThisBits == PartBits && ThisVT != PartVT) {
1079 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1080 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1085 if (TLI.isBigEndian())
1086 std::reverse(Parts, Parts + NumParts);
1092 if (NumParts == 1) {
1093 if (PartVT != ValueVT) {
1094 if (PartVT.isVector()) {
1095 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1097 assert(ValueVT.getVectorElementType() == PartVT &&
1098 ValueVT.getVectorNumElements() == 1 &&
1099 "Only trivial vector-to-scalar conversions should get here!");
1100 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1101 DAG.getConstant(0, PtrVT));
1109 // Handle a multi-element vector.
1110 MVT IntermediateVT, RegisterVT;
1111 unsigned NumIntermediates;
1113 DAG.getTargetLoweringInfo()
1114 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1116 unsigned NumElements = ValueVT.getVectorNumElements();
1118 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1119 NumParts = NumRegs; // Silence a compiler warning.
1120 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1122 // Split the vector into intermediate operands.
1123 SmallVector<SDValue, 8> Ops(NumIntermediates);
1124 for (unsigned i = 0; i != NumIntermediates; ++i)
1125 if (IntermediateVT.isVector())
1126 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1127 IntermediateVT, Val,
1128 DAG.getConstant(i * (NumElements / NumIntermediates),
1131 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1132 IntermediateVT, Val,
1133 DAG.getConstant(i, PtrVT));
1135 // Split the intermediate operands into legal parts.
1136 if (NumParts == NumIntermediates) {
1137 // If the register was not expanded, promote or copy the value,
1139 for (unsigned i = 0; i != NumParts; ++i)
1140 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1141 } else if (NumParts > 0) {
1142 // If the intermediate type was expanded, split each the value into
1144 assert(NumParts % NumIntermediates == 0 &&
1145 "Must expand into a divisible number of parts!");
1146 unsigned Factor = NumParts / NumIntermediates;
1147 for (unsigned i = 0; i != NumIntermediates; ++i)
1148 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1153 SDValue SelectionDAGLowering::getValue(const Value *V) {
1154 SDValue &N = NodeMap[V];
1155 if (N.Val) return N;
1157 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1158 MVT VT = TLI.getValueType(V->getType(), true);
1160 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1161 return N = DAG.getConstant(CI->getValue(), VT);
1163 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1164 return N = DAG.getGlobalAddress(GV, VT);
1166 if (isa<ConstantPointerNull>(C))
1167 return N = DAG.getConstant(0, TLI.getPointerTy());
1169 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1170 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1172 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1173 !V->getType()->isAggregateType())
1174 return N = DAG.getNode(ISD::UNDEF, VT);
1176 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1177 visit(CE->getOpcode(), *CE);
1178 SDValue N1 = NodeMap[V];
1179 assert(N1.Val && "visit didn't populate the ValueMap!");
1183 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1184 SmallVector<SDValue, 4> Constants;
1185 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1187 SDNode *Val = getValue(*OI).Val;
1188 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1189 Constants.push_back(SDValue(Val, i));
1191 return DAG.getMergeValues(&Constants[0], Constants.size());
1194 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
1195 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1196 "Unknown struct or array constant!");
1198 SmallVector<MVT, 4> ValueVTs;
1199 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1200 unsigned NumElts = ValueVTs.size();
1202 return SDValue(); // empty struct
1203 SmallVector<SDValue, 4> Constants(NumElts);
1204 for (unsigned i = 0; i != NumElts; ++i) {
1205 MVT EltVT = ValueVTs[i];
1206 if (isa<UndefValue>(C))
1207 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1208 else if (EltVT.isFloatingPoint())
1209 Constants[i] = DAG.getConstantFP(0, EltVT);
1211 Constants[i] = DAG.getConstant(0, EltVT);
1213 return DAG.getMergeValues(&Constants[0], NumElts);
1216 const VectorType *VecTy = cast<VectorType>(V->getType());
1217 unsigned NumElements = VecTy->getNumElements();
1219 // Now that we know the number and type of the elements, get that number of
1220 // elements into the Ops array based on what kind of constant it is.
1221 SmallVector<SDValue, 16> Ops;
1222 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1223 for (unsigned i = 0; i != NumElements; ++i)
1224 Ops.push_back(getValue(CP->getOperand(i)));
1226 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1227 "Unknown vector constant!");
1228 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1231 if (isa<UndefValue>(C))
1232 Op = DAG.getNode(ISD::UNDEF, EltVT);
1233 else if (EltVT.isFloatingPoint())
1234 Op = DAG.getConstantFP(0, EltVT);
1236 Op = DAG.getConstant(0, EltVT);
1237 Ops.assign(NumElements, Op);
1240 // Create a BUILD_VECTOR node.
1241 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1244 // If this is a static alloca, generate it as the frameindex instead of
1246 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1247 std::map<const AllocaInst*, int>::iterator SI =
1248 FuncInfo.StaticAllocaMap.find(AI);
1249 if (SI != FuncInfo.StaticAllocaMap.end())
1250 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1253 unsigned InReg = FuncInfo.ValueMap[V];
1254 assert(InReg && "Value not in map!");
1256 RegsForValue RFV(TLI, InReg, V->getType());
1257 SDValue Chain = DAG.getEntryNode();
1258 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1262 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1263 if (I.getNumOperands() == 0) {
1264 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1268 SmallVector<SDValue, 8> NewValues;
1269 NewValues.push_back(getControlRoot());
1270 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1271 SDValue RetOp = getValue(I.getOperand(i));
1273 SmallVector<MVT, 4> ValueVTs;
1274 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1275 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1276 MVT VT = ValueVTs[j];
1278 // FIXME: C calling convention requires the return type to be promoted to
1279 // at least 32-bit. But this is not necessary for non-C calling conventions.
1280 if (VT.isInteger()) {
1281 MVT MinVT = TLI.getRegisterType(MVT::i32);
1282 if (VT.bitsLT(MinVT))
1286 unsigned NumParts = TLI.getNumRegisters(VT);
1287 MVT PartVT = TLI.getRegisterType(VT);
1288 SmallVector<SDValue, 4> Parts(NumParts);
1289 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1291 const Function *F = I.getParent()->getParent();
1292 if (F->paramHasAttr(0, ParamAttr::SExt))
1293 ExtendKind = ISD::SIGN_EXTEND;
1294 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1295 ExtendKind = ISD::ZERO_EXTEND;
1297 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
1298 &Parts[0], NumParts, PartVT, ExtendKind);
1300 for (unsigned i = 0; i < NumParts; ++i) {
1301 NewValues.push_back(Parts[i]);
1302 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1306 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1307 &NewValues[0], NewValues.size()));
1310 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1311 /// the current basic block, add it to ValueMap now so that we'll get a
1313 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1314 // No need to export constants.
1315 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1317 // Already exported?
1318 if (FuncInfo.isExportedInst(V)) return;
1320 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1321 CopyValueToVirtualRegister(V, Reg);
1324 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1325 const BasicBlock *FromBB) {
1326 // The operands of the setcc have to be in this block. We don't know
1327 // how to export them from some other block.
1328 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1329 // Can export from current BB.
1330 if (VI->getParent() == FromBB)
1333 // Is already exported, noop.
1334 return FuncInfo.isExportedInst(V);
1337 // If this is an argument, we can export it if the BB is the entry block or
1338 // if it is already exported.
1339 if (isa<Argument>(V)) {
1340 if (FromBB == &FromBB->getParent()->getEntryBlock())
1343 // Otherwise, can only export this if it is already exported.
1344 return FuncInfo.isExportedInst(V);
1347 // Otherwise, constants can always be exported.
1351 static bool InBlock(const Value *V, const BasicBlock *BB) {
1352 if (const Instruction *I = dyn_cast<Instruction>(V))
1353 return I->getParent() == BB;
1357 /// FindMergedConditions - If Cond is an expression like
1358 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1359 MachineBasicBlock *TBB,
1360 MachineBasicBlock *FBB,
1361 MachineBasicBlock *CurBB,
1363 // If this node is not part of the or/and tree, emit it as a branch.
1364 Instruction *BOp = dyn_cast<Instruction>(Cond);
1366 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1367 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1368 BOp->getParent() != CurBB->getBasicBlock() ||
1369 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1370 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1371 const BasicBlock *BB = CurBB->getBasicBlock();
1373 // If the leaf of the tree is a comparison, merge the condition into
1375 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1376 // The operands of the cmp have to be in this block. We don't know
1377 // how to export them from some other block. If this is the first block
1378 // of the sequence, no exporting is needed.
1380 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1381 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1382 BOp = cast<Instruction>(Cond);
1383 ISD::CondCode Condition;
1384 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1385 switch (IC->getPredicate()) {
1386 default: assert(0 && "Unknown icmp predicate opcode!");
1387 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1388 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1389 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1390 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1391 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1392 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1393 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1394 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1395 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1396 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1398 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1399 ISD::CondCode FPC, FOC;
1400 switch (FC->getPredicate()) {
1401 default: assert(0 && "Unknown fcmp predicate opcode!");
1402 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1403 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1404 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1405 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1406 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1407 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1408 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1409 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1410 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1411 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1412 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1413 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1414 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1415 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1416 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1417 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1419 if (FiniteOnlyFPMath())
1424 Condition = ISD::SETEQ; // silence warning.
1425 assert(0 && "Unknown compare instruction");
1428 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1429 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1430 SwitchCases.push_back(CB);
1434 // Create a CaseBlock record representing this branch.
1435 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1436 NULL, TBB, FBB, CurBB);
1437 SwitchCases.push_back(CB);
1442 // Create TmpBB after CurBB.
1443 MachineFunction::iterator BBI = CurBB;
1444 MachineFunction &MF = DAG.getMachineFunction();
1445 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1446 CurBB->getParent()->insert(++BBI, TmpBB);
1448 if (Opc == Instruction::Or) {
1449 // Codegen X | Y as:
1457 // Emit the LHS condition.
1458 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1460 // Emit the RHS condition into TmpBB.
1461 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1463 assert(Opc == Instruction::And && "Unknown merge op!");
1464 // Codegen X & Y as:
1471 // This requires creation of TmpBB after CurBB.
1473 // Emit the LHS condition.
1474 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1476 // Emit the RHS condition into TmpBB.
1477 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1481 /// If the set of cases should be emitted as a series of branches, return true.
1482 /// If we should emit this as a bunch of and/or'd together conditions, return
1485 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1486 if (Cases.size() != 2) return true;
1488 // If this is two comparisons of the same values or'd or and'd together, they
1489 // will get folded into a single comparison, so don't emit two blocks.
1490 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1491 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1492 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1493 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1500 void SelectionDAGLowering::visitBr(BranchInst &I) {
1501 // Update machine-CFG edges.
1502 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1504 // Figure out which block is immediately after the current one.
1505 MachineBasicBlock *NextBlock = 0;
1506 MachineFunction::iterator BBI = CurMBB;
1507 if (++BBI != CurMBB->getParent()->end())
1510 if (I.isUnconditional()) {
1511 // Update machine-CFG edges.
1512 CurMBB->addSuccessor(Succ0MBB);
1514 // If this is not a fall-through branch, emit the branch.
1515 if (Succ0MBB != NextBlock)
1516 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1517 DAG.getBasicBlock(Succ0MBB)));
1521 // If this condition is one of the special cases we handle, do special stuff
1523 Value *CondVal = I.getCondition();
1524 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1526 // If this is a series of conditions that are or'd or and'd together, emit
1527 // this as a sequence of branches instead of setcc's with and/or operations.
1528 // For example, instead of something like:
1541 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1542 if (BOp->hasOneUse() &&
1543 (BOp->getOpcode() == Instruction::And ||
1544 BOp->getOpcode() == Instruction::Or)) {
1545 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1546 // If the compares in later blocks need to use values not currently
1547 // exported from this block, export them now. This block should always
1548 // be the first entry.
1549 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1551 // Allow some cases to be rejected.
1552 if (ShouldEmitAsBranches(SwitchCases)) {
1553 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1554 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1555 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1558 // Emit the branch for this block.
1559 visitSwitchCase(SwitchCases[0]);
1560 SwitchCases.erase(SwitchCases.begin());
1564 // Okay, we decided not to do this, remove any inserted MBB's and clear
1566 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1567 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1569 SwitchCases.clear();
1573 // Create a CaseBlock record representing this branch.
1574 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1575 NULL, Succ0MBB, Succ1MBB, CurMBB);
1576 // Use visitSwitchCase to actually insert the fast branch sequence for this
1578 visitSwitchCase(CB);
1581 /// visitSwitchCase - Emits the necessary code to represent a single node in
1582 /// the binary search tree resulting from lowering a switch instruction.
1583 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1585 SDValue CondLHS = getValue(CB.CmpLHS);
1587 // Build the setcc now.
1588 if (CB.CmpMHS == NULL) {
1589 // Fold "(X == true)" to X and "(X == false)" to !X to
1590 // handle common cases produced by branch lowering.
1591 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1593 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1594 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1595 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1597 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1599 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1601 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1602 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1604 SDValue CmpOp = getValue(CB.CmpMHS);
1605 MVT VT = CmpOp.getValueType();
1607 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1608 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1610 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1611 Cond = DAG.getSetCC(MVT::i1, SUB,
1612 DAG.getConstant(High-Low, VT), ISD::SETULE);
1616 // Update successor info
1617 CurMBB->addSuccessor(CB.TrueBB);
1618 CurMBB->addSuccessor(CB.FalseBB);
1620 // Set NextBlock to be the MBB immediately after the current one, if any.
1621 // This is used to avoid emitting unnecessary branches to the next block.
1622 MachineBasicBlock *NextBlock = 0;
1623 MachineFunction::iterator BBI = CurMBB;
1624 if (++BBI != CurMBB->getParent()->end())
1627 // If the lhs block is the next block, invert the condition so that we can
1628 // fall through to the lhs instead of the rhs block.
1629 if (CB.TrueBB == NextBlock) {
1630 std::swap(CB.TrueBB, CB.FalseBB);
1631 SDValue True = DAG.getConstant(1, Cond.getValueType());
1632 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1634 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1635 DAG.getBasicBlock(CB.TrueBB));
1637 // If the branch was constant folded, fix up the CFG.
1638 if (BrCond.getOpcode() == ISD::BR) {
1639 CurMBB->removeSuccessor(CB.FalseBB);
1640 DAG.setRoot(BrCond);
1642 // Otherwise, go ahead and insert the false branch.
1643 if (BrCond == getControlRoot())
1644 CurMBB->removeSuccessor(CB.TrueBB);
1646 if (CB.FalseBB == NextBlock)
1647 DAG.setRoot(BrCond);
1649 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1650 DAG.getBasicBlock(CB.FalseBB)));
1654 /// visitJumpTable - Emit JumpTable node in the current MBB
1655 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1656 // Emit the code for the jump table
1657 assert(JT.Reg != -1U && "Should lower JT Header first!");
1658 MVT PTy = TLI.getPointerTy();
1659 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1660 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1661 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1666 /// visitJumpTableHeader - This function emits necessary code to produce index
1667 /// in the JumpTable from switch case.
1668 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1669 SelectionDAGISel::JumpTableHeader &JTH) {
1670 // Subtract the lowest switch case value from the value being switched on
1671 // and conditional branch to default mbb if the result is greater than the
1672 // difference between smallest and largest cases.
1673 SDValue SwitchOp = getValue(JTH.SValue);
1674 MVT VT = SwitchOp.getValueType();
1675 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1676 DAG.getConstant(JTH.First, VT));
1678 // The SDNode we just created, which holds the value being switched on
1679 // minus the the smallest case value, needs to be copied to a virtual
1680 // register so it can be used as an index into the jump table in a
1681 // subsequent basic block. This value may be smaller or larger than the
1682 // target's pointer type, and therefore require extension or truncating.
1683 if (VT.bitsGT(TLI.getPointerTy()))
1684 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1686 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1688 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1689 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1690 JT.Reg = JumpTableReg;
1692 // Emit the range check for the jump table, and branch to the default
1693 // block for the switch statement if the value being switched on exceeds
1694 // the largest case in the switch.
1695 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1696 DAG.getConstant(JTH.Last-JTH.First,VT),
1699 // Set NextBlock to be the MBB immediately after the current one, if any.
1700 // This is used to avoid emitting unnecessary branches to the next block.
1701 MachineBasicBlock *NextBlock = 0;
1702 MachineFunction::iterator BBI = CurMBB;
1703 if (++BBI != CurMBB->getParent()->end())
1706 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1707 DAG.getBasicBlock(JT.Default));
1709 if (JT.MBB == NextBlock)
1710 DAG.setRoot(BrCond);
1712 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1713 DAG.getBasicBlock(JT.MBB)));
1718 /// visitBitTestHeader - This function emits necessary code to produce value
1719 /// suitable for "bit tests"
1720 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1721 // Subtract the minimum value
1722 SDValue SwitchOp = getValue(B.SValue);
1723 MVT VT = SwitchOp.getValueType();
1724 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1725 DAG.getConstant(B.First, VT));
1728 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1729 DAG.getConstant(B.Range, VT),
1733 if (VT.bitsGT(TLI.getShiftAmountTy()))
1734 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1736 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1738 // Make desired shift
1739 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1740 DAG.getConstant(1, TLI.getPointerTy()),
1743 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1744 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1747 // Set NextBlock to be the MBB immediately after the current one, if any.
1748 // This is used to avoid emitting unnecessary branches to the next block.
1749 MachineBasicBlock *NextBlock = 0;
1750 MachineFunction::iterator BBI = CurMBB;
1751 if (++BBI != CurMBB->getParent()->end())
1754 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1756 CurMBB->addSuccessor(B.Default);
1757 CurMBB->addSuccessor(MBB);
1759 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1760 DAG.getBasicBlock(B.Default));
1762 if (MBB == NextBlock)
1763 DAG.setRoot(BrRange);
1765 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1766 DAG.getBasicBlock(MBB)));
1771 /// visitBitTestCase - this function produces one "bit test"
1772 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1774 SelectionDAGISel::BitTestCase &B) {
1775 // Emit bit tests and jumps
1776 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1777 TLI.getPointerTy());
1779 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1780 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1781 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1782 DAG.getConstant(0, TLI.getPointerTy()),
1785 CurMBB->addSuccessor(B.TargetBB);
1786 CurMBB->addSuccessor(NextMBB);
1788 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1789 AndCmp, DAG.getBasicBlock(B.TargetBB));
1791 // Set NextBlock to be the MBB immediately after the current one, if any.
1792 // This is used to avoid emitting unnecessary branches to the next block.
1793 MachineBasicBlock *NextBlock = 0;
1794 MachineFunction::iterator BBI = CurMBB;
1795 if (++BBI != CurMBB->getParent()->end())
1798 if (NextMBB == NextBlock)
1801 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1802 DAG.getBasicBlock(NextMBB)));
1807 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1808 // Retrieve successors.
1809 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1810 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1812 if (isa<InlineAsm>(I.getCalledValue()))
1815 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1817 // If the value of the invoke is used outside of its defining block, make it
1818 // available as a virtual register.
1819 if (!I.use_empty()) {
1820 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1821 if (VMI != FuncInfo.ValueMap.end())
1822 CopyValueToVirtualRegister(&I, VMI->second);
1825 // Update successor info
1826 CurMBB->addSuccessor(Return);
1827 CurMBB->addSuccessor(LandingPad);
1829 // Drop into normal successor.
1830 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1831 DAG.getBasicBlock(Return)));
1834 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1837 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1838 /// small case ranges).
1839 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1840 CaseRecVector& WorkList,
1842 MachineBasicBlock* Default) {
1843 Case& BackCase = *(CR.Range.second-1);
1845 // Size is the number of Cases represented by this range.
1846 unsigned Size = CR.Range.second - CR.Range.first;
1850 // Get the MachineFunction which holds the current MBB. This is used when
1851 // inserting any additional MBBs necessary to represent the switch.
1852 MachineFunction *CurMF = CurMBB->getParent();
1854 // Figure out which block is immediately after the current one.
1855 MachineBasicBlock *NextBlock = 0;
1856 MachineFunction::iterator BBI = CR.CaseBB;
1858 if (++BBI != CurMBB->getParent()->end())
1861 // TODO: If any two of the cases has the same destination, and if one value
1862 // is the same as the other, but has one bit unset that the other has set,
1863 // use bit manipulation to do two compares at once. For example:
1864 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1866 // Rearrange the case blocks so that the last one falls through if possible.
1867 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1868 // The last case block won't fall through into 'NextBlock' if we emit the
1869 // branches in this order. See if rearranging a case value would help.
1870 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1871 if (I->BB == NextBlock) {
1872 std::swap(*I, BackCase);
1878 // Create a CaseBlock record representing a conditional branch to
1879 // the Case's target mbb if the value being switched on SV is equal
1881 MachineBasicBlock *CurBlock = CR.CaseBB;
1882 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1883 MachineBasicBlock *FallThrough;
1885 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1886 CurMF->insert(BBI, FallThrough);
1888 // If the last case doesn't match, go to the default block.
1889 FallThrough = Default;
1892 Value *RHS, *LHS, *MHS;
1894 if (I->High == I->Low) {
1895 // This is just small small case range :) containing exactly 1 case
1897 LHS = SV; RHS = I->High; MHS = NULL;
1900 LHS = I->Low; MHS = SV; RHS = I->High;
1902 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1903 I->BB, FallThrough, CurBlock);
1905 // If emitting the first comparison, just call visitSwitchCase to emit the
1906 // code into the current block. Otherwise, push the CaseBlock onto the
1907 // vector to be later processed by SDISel, and insert the node's MBB
1908 // before the next MBB.
1909 if (CurBlock == CurMBB)
1910 visitSwitchCase(CB);
1912 SwitchCases.push_back(CB);
1914 CurBlock = FallThrough;
1920 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1921 return !DisableJumpTables &&
1922 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1923 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1926 /// handleJTSwitchCase - Emit jumptable for current switch case range
1927 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1928 CaseRecVector& WorkList,
1930 MachineBasicBlock* Default) {
1931 Case& FrontCase = *CR.Range.first;
1932 Case& BackCase = *(CR.Range.second-1);
1934 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1935 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1938 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1942 if (!areJTsAllowed(TLI) || TSize <= 3)
1945 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1949 DOUT << "Lowering jump table\n"
1950 << "First entry: " << First << ". Last entry: " << Last << "\n"
1951 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1953 // Get the MachineFunction which holds the current MBB. This is used when
1954 // inserting any additional MBBs necessary to represent the switch.
1955 MachineFunction *CurMF = CurMBB->getParent();
1957 // Figure out which block is immediately after the current one.
1958 MachineBasicBlock *NextBlock = 0;
1959 MachineFunction::iterator BBI = CR.CaseBB;
1961 if (++BBI != CurMBB->getParent()->end())
1964 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1966 // Create a new basic block to hold the code for loading the address
1967 // of the jump table, and jumping to it. Update successor information;
1968 // we will either branch to the default case for the switch, or the jump
1970 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1971 CurMF->insert(BBI, JumpTableBB);
1972 CR.CaseBB->addSuccessor(Default);
1973 CR.CaseBB->addSuccessor(JumpTableBB);
1975 // Build a vector of destination BBs, corresponding to each target
1976 // of the jump table. If the value of the jump table slot corresponds to
1977 // a case statement, push the case's BB onto the vector, otherwise, push
1979 std::vector<MachineBasicBlock*> DestBBs;
1980 int64_t TEI = First;
1981 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1982 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1983 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1985 if ((Low <= TEI) && (TEI <= High)) {
1986 DestBBs.push_back(I->BB);
1990 DestBBs.push_back(Default);
1994 // Update successor info. Add one edge to each unique successor.
1995 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1996 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1997 E = DestBBs.end(); I != E; ++I) {
1998 if (!SuccsHandled[(*I)->getNumber()]) {
1999 SuccsHandled[(*I)->getNumber()] = true;
2000 JumpTableBB->addSuccessor(*I);
2004 // Create a jump table index for this jump table, or return an existing
2006 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
2008 // Set the jump table information so that we can codegen it as a second
2009 // MachineBasicBlock
2010 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
2011 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
2012 (CR.CaseBB == CurMBB));
2013 if (CR.CaseBB == CurMBB)
2014 visitJumpTableHeader(JT, JTH);
2016 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2021 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2023 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2024 CaseRecVector& WorkList,
2026 MachineBasicBlock* Default) {
2027 // Get the MachineFunction which holds the current MBB. This is used when
2028 // inserting any additional MBBs necessary to represent the switch.
2029 MachineFunction *CurMF = CurMBB->getParent();
2031 // Figure out which block is immediately after the current one.
2032 MachineBasicBlock *NextBlock = 0;
2033 MachineFunction::iterator BBI = CR.CaseBB;
2035 if (++BBI != CurMBB->getParent()->end())
2038 Case& FrontCase = *CR.Range.first;
2039 Case& BackCase = *(CR.Range.second-1);
2040 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2042 // Size is the number of Cases represented by this range.
2043 unsigned Size = CR.Range.second - CR.Range.first;
2045 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2046 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2048 CaseItr Pivot = CR.Range.first + Size/2;
2050 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2051 // (heuristically) allow us to emit JumpTable's later.
2053 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2057 uint64_t LSize = FrontCase.size();
2058 uint64_t RSize = TSize-LSize;
2059 DOUT << "Selecting best pivot: \n"
2060 << "First: " << First << ", Last: " << Last <<"\n"
2061 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2062 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2064 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2065 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2066 assert((RBegin-LEnd>=1) && "Invalid case distance");
2067 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2068 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2069 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2070 // Should always split in some non-trivial place
2072 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2073 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2074 << "Metric: " << Metric << "\n";
2075 if (FMetric < Metric) {
2078 DOUT << "Current metric set to: " << FMetric << "\n";
2084 if (areJTsAllowed(TLI)) {
2085 // If our case is dense we *really* should handle it earlier!
2086 assert((FMetric > 0) && "Should handle dense range earlier!");
2088 Pivot = CR.Range.first + Size/2;
2091 CaseRange LHSR(CR.Range.first, Pivot);
2092 CaseRange RHSR(Pivot, CR.Range.second);
2093 Constant *C = Pivot->Low;
2094 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2096 // We know that we branch to the LHS if the Value being switched on is
2097 // less than the Pivot value, C. We use this to optimize our binary
2098 // tree a bit, by recognizing that if SV is greater than or equal to the
2099 // LHS's Case Value, and that Case Value is exactly one less than the
2100 // Pivot's Value, then we can branch directly to the LHS's Target,
2101 // rather than creating a leaf node for it.
2102 if ((LHSR.second - LHSR.first) == 1 &&
2103 LHSR.first->High == CR.GE &&
2104 cast<ConstantInt>(C)->getSExtValue() ==
2105 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2106 TrueBB = LHSR.first->BB;
2108 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2109 CurMF->insert(BBI, TrueBB);
2110 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2113 // Similar to the optimization above, if the Value being switched on is
2114 // known to be less than the Constant CR.LT, and the current Case Value
2115 // is CR.LT - 1, then we can branch directly to the target block for
2116 // the current Case Value, rather than emitting a RHS leaf node for it.
2117 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2118 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2119 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2120 FalseBB = RHSR.first->BB;
2122 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2123 CurMF->insert(BBI, FalseBB);
2124 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2127 // Create a CaseBlock record representing a conditional branch to
2128 // the LHS node if the value being switched on SV is less than C.
2129 // Otherwise, branch to LHS.
2130 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2131 TrueBB, FalseBB, CR.CaseBB);
2133 if (CR.CaseBB == CurMBB)
2134 visitSwitchCase(CB);
2136 SwitchCases.push_back(CB);
2141 /// handleBitTestsSwitchCase - if current case range has few destination and
2142 /// range span less, than machine word bitwidth, encode case range into series
2143 /// of masks and emit bit tests with these masks.
2144 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2145 CaseRecVector& WorkList,
2147 MachineBasicBlock* Default){
2148 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2150 Case& FrontCase = *CR.Range.first;
2151 Case& BackCase = *(CR.Range.second-1);
2153 // Get the MachineFunction which holds the current MBB. This is used when
2154 // inserting any additional MBBs necessary to represent the switch.
2155 MachineFunction *CurMF = CurMBB->getParent();
2157 unsigned numCmps = 0;
2158 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2160 // Single case counts one, case range - two.
2161 if (I->Low == I->High)
2167 // Count unique destinations
2168 SmallSet<MachineBasicBlock*, 4> Dests;
2169 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2170 Dests.insert(I->BB);
2171 if (Dests.size() > 3)
2172 // Don't bother the code below, if there are too much unique destinations
2175 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2176 << "Total number of comparisons: " << numCmps << "\n";
2178 // Compute span of values.
2179 Constant* minValue = FrontCase.Low;
2180 Constant* maxValue = BackCase.High;
2181 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2182 cast<ConstantInt>(minValue)->getSExtValue();
2183 DOUT << "Compare range: " << range << "\n"
2184 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2185 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2187 if (range>=IntPtrBits ||
2188 (!(Dests.size() == 1 && numCmps >= 3) &&
2189 !(Dests.size() == 2 && numCmps >= 5) &&
2190 !(Dests.size() >= 3 && numCmps >= 6)))
2193 DOUT << "Emitting bit tests\n";
2194 int64_t lowBound = 0;
2196 // Optimize the case where all the case values fit in a
2197 // word without having to subtract minValue. In this case,
2198 // we can optimize away the subtraction.
2199 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2200 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2201 range = cast<ConstantInt>(maxValue)->getSExtValue();
2203 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2206 CaseBitsVector CasesBits;
2207 unsigned i, count = 0;
2209 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2210 MachineBasicBlock* Dest = I->BB;
2211 for (i = 0; i < count; ++i)
2212 if (Dest == CasesBits[i].BB)
2216 assert((count < 3) && "Too much destinations to test!");
2217 CasesBits.push_back(CaseBits(0, Dest, 0));
2221 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2222 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2224 for (uint64_t j = lo; j <= hi; j++) {
2225 CasesBits[i].Mask |= 1ULL << j;
2226 CasesBits[i].Bits++;
2230 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2232 SelectionDAGISel::BitTestInfo BTC;
2234 // Figure out which block is immediately after the current one.
2235 MachineFunction::iterator BBI = CR.CaseBB;
2238 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2241 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2242 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2243 << ", BB: " << CasesBits[i].BB << "\n";
2245 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2246 CurMF->insert(BBI, CaseBB);
2247 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2252 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2253 -1U, (CR.CaseBB == CurMBB),
2254 CR.CaseBB, Default, BTC);
2256 if (CR.CaseBB == CurMBB)
2257 visitBitTestHeader(BTB);
2259 BitTestCases.push_back(BTB);
2265 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2266 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2267 const SwitchInst& SI) {
2268 unsigned numCmps = 0;
2270 // Start with "simple" cases
2271 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2272 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2273 Cases.push_back(Case(SI.getSuccessorValue(i),
2274 SI.getSuccessorValue(i),
2277 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2279 // Merge case into clusters
2280 if (Cases.size()>=2)
2281 // Must recompute end() each iteration because it may be
2282 // invalidated by erase if we hold on to it
2283 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2284 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2285 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2286 MachineBasicBlock* nextBB = J->BB;
2287 MachineBasicBlock* currentBB = I->BB;
2289 // If the two neighboring cases go to the same destination, merge them
2290 // into a single case.
2291 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2299 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2300 if (I->Low != I->High)
2301 // A range counts double, since it requires two compares.
2308 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2309 // Figure out which block is immediately after the current one.
2310 MachineBasicBlock *NextBlock = 0;
2311 MachineFunction::iterator BBI = CurMBB;
2313 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2315 // If there is only the default destination, branch to it if it is not the
2316 // next basic block. Otherwise, just fall through.
2317 if (SI.getNumOperands() == 2) {
2318 // Update machine-CFG edges.
2320 // If this is not a fall-through branch, emit the branch.
2321 CurMBB->addSuccessor(Default);
2322 if (Default != NextBlock)
2323 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2324 DAG.getBasicBlock(Default)));
2329 // If there are any non-default case statements, create a vector of Cases
2330 // representing each one, and sort the vector so that we can efficiently
2331 // create a binary search tree from them.
2333 unsigned numCmps = Clusterify(Cases, SI);
2334 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2335 << ". Total compares: " << numCmps << "\n";
2337 // Get the Value to be switched on and default basic blocks, which will be
2338 // inserted into CaseBlock records, representing basic blocks in the binary
2340 Value *SV = SI.getOperand(0);
2342 // Push the initial CaseRec onto the worklist
2343 CaseRecVector WorkList;
2344 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2346 while (!WorkList.empty()) {
2347 // Grab a record representing a case range to process off the worklist
2348 CaseRec CR = WorkList.back();
2349 WorkList.pop_back();
2351 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2354 // If the range has few cases (two or less) emit a series of specific
2356 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2359 // If the switch has more than 5 blocks, and at least 40% dense, and the
2360 // target supports indirect branches, then emit a jump table rather than
2361 // lowering the switch to a binary tree of conditional branches.
2362 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2365 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2366 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2367 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2372 void SelectionDAGLowering::visitSub(User &I) {
2373 // -0.0 - X --> fneg
2374 const Type *Ty = I.getType();
2375 if (isa<VectorType>(Ty)) {
2376 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2377 const VectorType *DestTy = cast<VectorType>(I.getType());
2378 const Type *ElTy = DestTy->getElementType();
2379 if (ElTy->isFloatingPoint()) {
2380 unsigned VL = DestTy->getNumElements();
2381 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2382 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2384 SDValue Op2 = getValue(I.getOperand(1));
2385 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2391 if (Ty->isFloatingPoint()) {
2392 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2393 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2394 SDValue Op2 = getValue(I.getOperand(1));
2395 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2400 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2403 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2404 SDValue Op1 = getValue(I.getOperand(0));
2405 SDValue Op2 = getValue(I.getOperand(1));
2407 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2410 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2411 SDValue Op1 = getValue(I.getOperand(0));
2412 SDValue Op2 = getValue(I.getOperand(1));
2413 if (!isa<VectorType>(I.getType())) {
2414 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2415 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2416 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2417 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2420 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2423 void SelectionDAGLowering::visitICmp(User &I) {
2424 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2425 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2426 predicate = IC->getPredicate();
2427 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2428 predicate = ICmpInst::Predicate(IC->getPredicate());
2429 SDValue Op1 = getValue(I.getOperand(0));
2430 SDValue Op2 = getValue(I.getOperand(1));
2431 ISD::CondCode Opcode;
2432 switch (predicate) {
2433 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2434 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2435 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2436 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2437 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2438 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2439 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2440 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2441 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2442 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2444 assert(!"Invalid ICmp predicate value");
2445 Opcode = ISD::SETEQ;
2448 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2451 void SelectionDAGLowering::visitFCmp(User &I) {
2452 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2453 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2454 predicate = FC->getPredicate();
2455 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2456 predicate = FCmpInst::Predicate(FC->getPredicate());
2457 SDValue Op1 = getValue(I.getOperand(0));
2458 SDValue Op2 = getValue(I.getOperand(1));
2459 ISD::CondCode Condition, FOC, FPC;
2460 switch (predicate) {
2461 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2462 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2463 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2464 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2465 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2466 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2467 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2468 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2469 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2470 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2471 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2472 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2473 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2474 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2475 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2476 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2478 assert(!"Invalid FCmp predicate value");
2479 FOC = FPC = ISD::SETFALSE;
2482 if (FiniteOnlyFPMath())
2486 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2489 void SelectionDAGLowering::visitVICmp(User &I) {
2490 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2491 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2492 predicate = IC->getPredicate();
2493 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2494 predicate = ICmpInst::Predicate(IC->getPredicate());
2495 SDValue Op1 = getValue(I.getOperand(0));
2496 SDValue Op2 = getValue(I.getOperand(1));
2497 ISD::CondCode Opcode;
2498 switch (predicate) {
2499 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2500 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2501 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2502 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2503 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2504 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2505 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2506 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2507 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2508 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2510 assert(!"Invalid ICmp predicate value");
2511 Opcode = ISD::SETEQ;
2514 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2517 void SelectionDAGLowering::visitVFCmp(User &I) {
2518 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2519 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2520 predicate = FC->getPredicate();
2521 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2522 predicate = FCmpInst::Predicate(FC->getPredicate());
2523 SDValue Op1 = getValue(I.getOperand(0));
2524 SDValue Op2 = getValue(I.getOperand(1));
2525 ISD::CondCode Condition, FOC, FPC;
2526 switch (predicate) {
2527 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2528 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2529 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2530 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2531 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2532 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2533 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2534 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2535 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2536 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2537 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2538 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2539 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2540 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2541 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2542 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2544 assert(!"Invalid VFCmp predicate value");
2545 FOC = FPC = ISD::SETFALSE;
2548 if (FiniteOnlyFPMath())
2553 MVT DestVT = TLI.getValueType(I.getType());
2555 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2558 void SelectionDAGLowering::visitSelect(User &I) {
2559 SDValue Cond = getValue(I.getOperand(0));
2560 SDValue TrueVal = getValue(I.getOperand(1));
2561 SDValue FalseVal = getValue(I.getOperand(2));
2562 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2563 TrueVal, FalseVal));
2567 void SelectionDAGLowering::visitTrunc(User &I) {
2568 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2569 SDValue N = getValue(I.getOperand(0));
2570 MVT DestVT = TLI.getValueType(I.getType());
2571 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2574 void SelectionDAGLowering::visitZExt(User &I) {
2575 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2576 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2577 SDValue N = getValue(I.getOperand(0));
2578 MVT DestVT = TLI.getValueType(I.getType());
2579 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2582 void SelectionDAGLowering::visitSExt(User &I) {
2583 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2584 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2585 SDValue N = getValue(I.getOperand(0));
2586 MVT DestVT = TLI.getValueType(I.getType());
2587 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2590 void SelectionDAGLowering::visitFPTrunc(User &I) {
2591 // FPTrunc is never a no-op cast, no need to check
2592 SDValue N = getValue(I.getOperand(0));
2593 MVT DestVT = TLI.getValueType(I.getType());
2594 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2597 void SelectionDAGLowering::visitFPExt(User &I){
2598 // FPTrunc is never a no-op cast, no need to check
2599 SDValue N = getValue(I.getOperand(0));
2600 MVT DestVT = TLI.getValueType(I.getType());
2601 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2604 void SelectionDAGLowering::visitFPToUI(User &I) {
2605 // FPToUI is never a no-op cast, no need to check
2606 SDValue N = getValue(I.getOperand(0));
2607 MVT DestVT = TLI.getValueType(I.getType());
2608 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2611 void SelectionDAGLowering::visitFPToSI(User &I) {
2612 // FPToSI is never a no-op cast, no need to check
2613 SDValue N = getValue(I.getOperand(0));
2614 MVT DestVT = TLI.getValueType(I.getType());
2615 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2618 void SelectionDAGLowering::visitUIToFP(User &I) {
2619 // UIToFP is never a no-op cast, no need to check
2620 SDValue N = getValue(I.getOperand(0));
2621 MVT DestVT = TLI.getValueType(I.getType());
2622 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2625 void SelectionDAGLowering::visitSIToFP(User &I){
2626 // UIToFP is never a no-op cast, no need to check
2627 SDValue N = getValue(I.getOperand(0));
2628 MVT DestVT = TLI.getValueType(I.getType());
2629 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2632 void SelectionDAGLowering::visitPtrToInt(User &I) {
2633 // What to do depends on the size of the integer and the size of the pointer.
2634 // We can either truncate, zero extend, or no-op, accordingly.
2635 SDValue N = getValue(I.getOperand(0));
2636 MVT SrcVT = N.getValueType();
2637 MVT DestVT = TLI.getValueType(I.getType());
2639 if (DestVT.bitsLT(SrcVT))
2640 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2642 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2643 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2644 setValue(&I, Result);
2647 void SelectionDAGLowering::visitIntToPtr(User &I) {
2648 // What to do depends on the size of the integer and the size of the pointer.
2649 // We can either truncate, zero extend, or no-op, accordingly.
2650 SDValue N = getValue(I.getOperand(0));
2651 MVT SrcVT = N.getValueType();
2652 MVT DestVT = TLI.getValueType(I.getType());
2653 if (DestVT.bitsLT(SrcVT))
2654 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2656 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2657 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2660 void SelectionDAGLowering::visitBitCast(User &I) {
2661 SDValue N = getValue(I.getOperand(0));
2662 MVT DestVT = TLI.getValueType(I.getType());
2664 // BitCast assures us that source and destination are the same size so this
2665 // is either a BIT_CONVERT or a no-op.
2666 if (DestVT != N.getValueType())
2667 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2669 setValue(&I, N); // noop cast.
2672 void SelectionDAGLowering::visitInsertElement(User &I) {
2673 SDValue InVec = getValue(I.getOperand(0));
2674 SDValue InVal = getValue(I.getOperand(1));
2675 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2676 getValue(I.getOperand(2)));
2678 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2679 TLI.getValueType(I.getType()),
2680 InVec, InVal, InIdx));
2683 void SelectionDAGLowering::visitExtractElement(User &I) {
2684 SDValue InVec = getValue(I.getOperand(0));
2685 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2686 getValue(I.getOperand(1)));
2687 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2688 TLI.getValueType(I.getType()), InVec, InIdx));
2691 void SelectionDAGLowering::visitShuffleVector(User &I) {
2692 SDValue V1 = getValue(I.getOperand(0));
2693 SDValue V2 = getValue(I.getOperand(1));
2694 SDValue Mask = getValue(I.getOperand(2));
2696 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2697 TLI.getValueType(I.getType()),
2701 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2702 const Value *Op0 = I.getOperand(0);
2703 const Value *Op1 = I.getOperand(1);
2704 const Type *AggTy = I.getType();
2705 const Type *ValTy = Op1->getType();
2706 bool IntoUndef = isa<UndefValue>(Op0);
2707 bool FromUndef = isa<UndefValue>(Op1);
2709 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2710 I.idx_begin(), I.idx_end());
2712 SmallVector<MVT, 4> AggValueVTs;
2713 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2714 SmallVector<MVT, 4> ValValueVTs;
2715 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2717 unsigned NumAggValues = AggValueVTs.size();
2718 unsigned NumValValues = ValValueVTs.size();
2719 SmallVector<SDValue, 4> Values(NumAggValues);
2721 SDValue Agg = getValue(Op0);
2722 SDValue Val = getValue(Op1);
2724 // Copy the beginning value(s) from the original aggregate.
2725 for (; i != LinearIndex; ++i)
2726 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2727 SDValue(Agg.Val, Agg.ResNo + i);
2728 // Copy values from the inserted value(s).
2729 for (; i != LinearIndex + NumValValues; ++i)
2730 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2731 SDValue(Val.Val, Val.ResNo + i - LinearIndex);
2732 // Copy remaining value(s) from the original aggregate.
2733 for (; i != NumAggValues; ++i)
2734 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2735 SDValue(Agg.Val, Agg.ResNo + i);
2737 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2738 &Values[0], NumAggValues));
2741 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2742 const Value *Op0 = I.getOperand(0);
2743 const Type *AggTy = Op0->getType();
2744 const Type *ValTy = I.getType();
2745 bool OutOfUndef = isa<UndefValue>(Op0);
2747 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2748 I.idx_begin(), I.idx_end());
2750 SmallVector<MVT, 4> ValValueVTs;
2751 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2753 unsigned NumValValues = ValValueVTs.size();
2754 SmallVector<SDValue, 4> Values(NumValValues);
2756 SDValue Agg = getValue(Op0);
2757 // Copy out the selected value(s).
2758 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2759 Values[i - LinearIndex] =
2760 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2761 SDValue(Agg.Val, Agg.ResNo + i);
2763 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2764 &Values[0], NumValValues));
2768 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2769 SDValue N = getValue(I.getOperand(0));
2770 const Type *Ty = I.getOperand(0)->getType();
2772 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2775 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2776 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2779 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2780 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2781 DAG.getIntPtrConstant(Offset));
2783 Ty = StTy->getElementType(Field);
2785 Ty = cast<SequentialType>(Ty)->getElementType();
2787 // If this is a constant subscript, handle it quickly.
2788 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2789 if (CI->getZExtValue() == 0) continue;
2791 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2792 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2793 DAG.getIntPtrConstant(Offs));
2797 // N = N + Idx * ElementSize;
2798 uint64_t ElementSize = TD->getABITypeSize(Ty);
2799 SDValue IdxN = getValue(Idx);
2801 // If the index is smaller or larger than intptr_t, truncate or extend
2803 if (IdxN.getValueType().bitsLT(N.getValueType())) {
2804 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2805 } else if (IdxN.getValueType().bitsGT(N.getValueType()))
2806 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2808 // If this is a multiply by a power of two, turn it into a shl
2809 // immediately. This is a very common case.
2810 if (isPowerOf2_64(ElementSize)) {
2811 unsigned Amt = Log2_64(ElementSize);
2812 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2813 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2814 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2818 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2819 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2820 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2826 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2827 // If this is a fixed sized alloca in the entry block of the function,
2828 // allocate it statically on the stack.
2829 if (FuncInfo.StaticAllocaMap.count(&I))
2830 return; // getValue will auto-populate this.
2832 const Type *Ty = I.getAllocatedType();
2833 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2835 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2838 SDValue AllocSize = getValue(I.getArraySize());
2839 MVT IntPtr = TLI.getPointerTy();
2840 if (IntPtr.bitsLT(AllocSize.getValueType()))
2841 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2842 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2843 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2845 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2846 DAG.getIntPtrConstant(TySize));
2848 // Handle alignment. If the requested alignment is less than or equal to
2849 // the stack alignment, ignore it. If the size is greater than or equal to
2850 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2851 unsigned StackAlign =
2852 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2853 if (Align <= StackAlign)
2856 // Round the size of the allocation up to the stack alignment size
2857 // by add SA-1 to the size.
2858 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2859 DAG.getIntPtrConstant(StackAlign-1));
2860 // Mask out the low bits for alignment purposes.
2861 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2862 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2864 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2865 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2867 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2869 DAG.setRoot(DSA.getValue(1));
2871 // Inform the Frame Information that we have just allocated a variable-sized
2873 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2876 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2877 const Value *SV = I.getOperand(0);
2878 SDValue Ptr = getValue(SV);
2880 const Type *Ty = I.getType();
2881 bool isVolatile = I.isVolatile();
2882 unsigned Alignment = I.getAlignment();
2884 SmallVector<MVT, 4> ValueVTs;
2885 SmallVector<uint64_t, 4> Offsets;
2886 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2887 unsigned NumValues = ValueVTs.size();
2892 bool ConstantMemory = false;
2894 // Serialize volatile loads with other side effects.
2896 else if (AA.pointsToConstantMemory(SV)) {
2897 // Do not serialize (non-volatile) loads of constant memory with anything.
2898 Root = DAG.getEntryNode();
2899 ConstantMemory = true;
2901 // Do not serialize non-volatile loads against each other.
2902 Root = DAG.getRoot();
2905 SmallVector<SDValue, 4> Values(NumValues);
2906 SmallVector<SDValue, 4> Chains(NumValues);
2907 MVT PtrVT = Ptr.getValueType();
2908 for (unsigned i = 0; i != NumValues; ++i) {
2909 SDValue L = DAG.getLoad(ValueVTs[i], Root,
2910 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2911 DAG.getConstant(Offsets[i], PtrVT)),
2913 isVolatile, Alignment);
2915 Chains[i] = L.getValue(1);
2918 if (!ConstantMemory) {
2919 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2920 &Chains[0], NumValues);
2924 PendingLoads.push_back(Chain);
2927 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2928 &Values[0], NumValues));
2932 void SelectionDAGLowering::visitStore(StoreInst &I) {
2933 Value *SrcV = I.getOperand(0);
2934 Value *PtrV = I.getOperand(1);
2936 SmallVector<MVT, 4> ValueVTs;
2937 SmallVector<uint64_t, 4> Offsets;
2938 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2939 unsigned NumValues = ValueVTs.size();
2943 // Get the lowered operands. Note that we do this after
2944 // checking if NumResults is zero, because with zero results
2945 // the operands won't have values in the map.
2946 SDValue Src = getValue(SrcV);
2947 SDValue Ptr = getValue(PtrV);
2949 SDValue Root = getRoot();
2950 SmallVector<SDValue, 4> Chains(NumValues);
2951 MVT PtrVT = Ptr.getValueType();
2952 bool isVolatile = I.isVolatile();
2953 unsigned Alignment = I.getAlignment();
2954 for (unsigned i = 0; i != NumValues; ++i)
2955 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
2956 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2957 DAG.getConstant(Offsets[i], PtrVT)),
2959 isVolatile, Alignment);
2961 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2964 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2966 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2967 unsigned Intrinsic) {
2968 bool HasChain = !I.doesNotAccessMemory();
2969 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2971 // Build the operand list.
2972 SmallVector<SDValue, 8> Ops;
2973 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2975 // We don't need to serialize loads against other loads.
2976 Ops.push_back(DAG.getRoot());
2978 Ops.push_back(getRoot());
2982 // Add the intrinsic ID as an integer operand.
2983 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2985 // Add all operands of the call to the operand list.
2986 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2987 SDValue Op = getValue(I.getOperand(i));
2988 assert(TLI.isTypeLegal(Op.getValueType()) &&
2989 "Intrinsic uses a non-legal type?");
2993 std::vector<MVT> VTs;
2994 if (I.getType() != Type::VoidTy) {
2995 MVT VT = TLI.getValueType(I.getType());
2996 if (VT.isVector()) {
2997 const VectorType *DestTy = cast<VectorType>(I.getType());
2998 MVT EltVT = TLI.getValueType(DestTy->getElementType());
3000 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
3001 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
3004 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
3008 VTs.push_back(MVT::Other);
3010 const MVT *VTList = DAG.getNodeValueTypes(VTs);
3015 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
3016 &Ops[0], Ops.size());
3017 else if (I.getType() != Type::VoidTy)
3018 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
3019 &Ops[0], Ops.size());
3021 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
3022 &Ops[0], Ops.size());
3025 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
3027 PendingLoads.push_back(Chain);
3031 if (I.getType() != Type::VoidTy) {
3032 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3033 MVT VT = TLI.getValueType(PTy);
3034 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3036 setValue(&I, Result);
3040 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3041 static GlobalVariable *ExtractTypeInfo (Value *V) {
3042 V = V->stripPointerCasts();
3043 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3044 assert ((GV || isa<ConstantPointerNull>(V)) &&
3045 "TypeInfo must be a global variable or NULL");
3049 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3050 /// call, and add them to the specified machine basic block.
3051 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3052 MachineBasicBlock *MBB) {
3053 // Inform the MachineModuleInfo of the personality for this landing pad.
3054 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3055 assert(CE->getOpcode() == Instruction::BitCast &&
3056 isa<Function>(CE->getOperand(0)) &&
3057 "Personality should be a function");
3058 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3060 // Gather all the type infos for this landing pad and pass them along to
3061 // MachineModuleInfo.
3062 std::vector<GlobalVariable *> TyInfo;
3063 unsigned N = I.getNumOperands();
3065 for (unsigned i = N - 1; i > 2; --i) {
3066 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3067 unsigned FilterLength = CI->getZExtValue();
3068 unsigned FirstCatch = i + FilterLength + !FilterLength;
3069 assert (FirstCatch <= N && "Invalid filter length");
3071 if (FirstCatch < N) {
3072 TyInfo.reserve(N - FirstCatch);
3073 for (unsigned j = FirstCatch; j < N; ++j)
3074 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3075 MMI->addCatchTypeInfo(MBB, TyInfo);
3079 if (!FilterLength) {
3081 MMI->addCleanup(MBB);
3084 TyInfo.reserve(FilterLength - 1);
3085 for (unsigned j = i + 1; j < FirstCatch; ++j)
3086 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3087 MMI->addFilterTypeInfo(MBB, TyInfo);
3096 TyInfo.reserve(N - 3);
3097 for (unsigned j = 3; j < N; ++j)
3098 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3099 MMI->addCatchTypeInfo(MBB, TyInfo);
3104 /// Inlined utility function to implement binary input atomic intrinsics for
3105 // visitIntrinsicCall: I is a call instruction
3106 // Op is the associated NodeType for I
3108 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3109 SDValue Root = getRoot();
3110 SDValue L = DAG.getAtomic(Op, Root,
3111 getValue(I.getOperand(1)),
3112 getValue(I.getOperand(2)),
3115 DAG.setRoot(L.getValue(1));
3119 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3120 /// we want to emit this as a call to a named external function, return the name
3121 /// otherwise lower it and return null.
3123 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3124 switch (Intrinsic) {
3126 // By default, turn this into a target intrinsic node.
3127 visitTargetIntrinsic(I, Intrinsic);
3129 case Intrinsic::vastart: visitVAStart(I); return 0;
3130 case Intrinsic::vaend: visitVAEnd(I); return 0;
3131 case Intrinsic::vacopy: visitVACopy(I); return 0;
3132 case Intrinsic::returnaddress:
3133 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3134 getValue(I.getOperand(1))));
3136 case Intrinsic::frameaddress:
3137 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3138 getValue(I.getOperand(1))));
3140 case Intrinsic::setjmp:
3141 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3143 case Intrinsic::longjmp:
3144 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3146 case Intrinsic::memcpy_i32:
3147 case Intrinsic::memcpy_i64: {
3148 SDValue Op1 = getValue(I.getOperand(1));
3149 SDValue Op2 = getValue(I.getOperand(2));
3150 SDValue Op3 = getValue(I.getOperand(3));
3151 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3152 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3153 I.getOperand(1), 0, I.getOperand(2), 0));
3156 case Intrinsic::memset_i32:
3157 case Intrinsic::memset_i64: {
3158 SDValue Op1 = getValue(I.getOperand(1));
3159 SDValue Op2 = getValue(I.getOperand(2));
3160 SDValue Op3 = getValue(I.getOperand(3));
3161 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3162 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3163 I.getOperand(1), 0));
3166 case Intrinsic::memmove_i32:
3167 case Intrinsic::memmove_i64: {
3168 SDValue Op1 = getValue(I.getOperand(1));
3169 SDValue Op2 = getValue(I.getOperand(2));
3170 SDValue Op3 = getValue(I.getOperand(3));
3171 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3173 // If the source and destination are known to not be aliases, we can
3174 // lower memmove as memcpy.
3175 uint64_t Size = -1ULL;
3176 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3177 Size = C->getValue();
3178 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3179 AliasAnalysis::NoAlias) {
3180 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3181 I.getOperand(1), 0, I.getOperand(2), 0));
3185 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3186 I.getOperand(1), 0, I.getOperand(2), 0));
3189 case Intrinsic::dbg_stoppoint: {
3190 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3191 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3192 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3193 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3194 assert(DD && "Not a debug information descriptor");
3195 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3198 cast<CompileUnitDesc>(DD)));
3203 case Intrinsic::dbg_region_start: {
3204 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3205 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3206 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3207 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3208 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3213 case Intrinsic::dbg_region_end: {
3214 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3215 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3216 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3217 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3218 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3223 case Intrinsic::dbg_func_start: {
3224 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3226 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3227 Value *SP = FSI.getSubprogram();
3228 if (SP && MMI->Verify(SP)) {
3229 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3230 // what (most?) gdb expects.
3231 DebugInfoDesc *DD = MMI->getDescFor(SP);
3232 assert(DD && "Not a debug information descriptor");
3233 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3234 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3235 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3236 // Record the source line but does create a label. It will be emitted
3237 // at asm emission time.
3238 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3243 case Intrinsic::dbg_declare: {
3244 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3245 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3246 Value *Variable = DI.getVariable();
3247 if (MMI && Variable && MMI->Verify(Variable))
3248 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3249 getValue(DI.getAddress()), getValue(Variable)));
3253 case Intrinsic::eh_exception: {
3254 if (!CurMBB->isLandingPad()) {
3255 // FIXME: Mark exception register as live in. Hack for PR1508.
3256 unsigned Reg = TLI.getExceptionAddressRegister();
3257 if (Reg) CurMBB->addLiveIn(Reg);
3259 // Insert the EXCEPTIONADDR instruction.
3260 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3262 Ops[0] = DAG.getRoot();
3263 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3265 DAG.setRoot(Op.getValue(1));
3269 case Intrinsic::eh_selector_i32:
3270 case Intrinsic::eh_selector_i64: {
3271 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3272 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3273 MVT::i32 : MVT::i64);
3276 if (CurMBB->isLandingPad())
3277 addCatchInfo(I, MMI, CurMBB);
3280 FuncInfo.CatchInfoLost.insert(&I);
3282 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3283 unsigned Reg = TLI.getExceptionSelectorRegister();
3284 if (Reg) CurMBB->addLiveIn(Reg);
3287 // Insert the EHSELECTION instruction.
3288 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3290 Ops[0] = getValue(I.getOperand(1));
3292 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3294 DAG.setRoot(Op.getValue(1));
3296 setValue(&I, DAG.getConstant(0, VT));
3302 case Intrinsic::eh_typeid_for_i32:
3303 case Intrinsic::eh_typeid_for_i64: {
3304 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3305 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3306 MVT::i32 : MVT::i64);
3309 // Find the type id for the given typeinfo.
3310 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3312 unsigned TypeID = MMI->getTypeIDFor(GV);
3313 setValue(&I, DAG.getConstant(TypeID, VT));
3315 // Return something different to eh_selector.
3316 setValue(&I, DAG.getConstant(1, VT));
3322 case Intrinsic::eh_return: {
3323 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3326 MMI->setCallsEHReturn(true);
3327 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3330 getValue(I.getOperand(1)),
3331 getValue(I.getOperand(2))));
3333 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3339 case Intrinsic::eh_unwind_init: {
3340 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3341 MMI->setCallsUnwindInit(true);
3347 case Intrinsic::eh_dwarf_cfa: {
3348 MVT VT = getValue(I.getOperand(1)).getValueType();
3350 if (VT.bitsGT(TLI.getPointerTy()))
3351 CfaArg = DAG.getNode(ISD::TRUNCATE,
3352 TLI.getPointerTy(), getValue(I.getOperand(1)));
3354 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3355 TLI.getPointerTy(), getValue(I.getOperand(1)));
3357 SDValue Offset = DAG.getNode(ISD::ADD,
3359 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3360 TLI.getPointerTy()),
3362 setValue(&I, DAG.getNode(ISD::ADD,
3364 DAG.getNode(ISD::FRAMEADDR,
3367 TLI.getPointerTy())),
3372 case Intrinsic::sqrt:
3373 setValue(&I, DAG.getNode(ISD::FSQRT,
3374 getValue(I.getOperand(1)).getValueType(),
3375 getValue(I.getOperand(1))));
3377 case Intrinsic::powi:
3378 setValue(&I, DAG.getNode(ISD::FPOWI,
3379 getValue(I.getOperand(1)).getValueType(),
3380 getValue(I.getOperand(1)),
3381 getValue(I.getOperand(2))));
3383 case Intrinsic::sin:
3384 setValue(&I, DAG.getNode(ISD::FSIN,
3385 getValue(I.getOperand(1)).getValueType(),
3386 getValue(I.getOperand(1))));
3388 case Intrinsic::cos:
3389 setValue(&I, DAG.getNode(ISD::FCOS,
3390 getValue(I.getOperand(1)).getValueType(),
3391 getValue(I.getOperand(1))));
3393 case Intrinsic::pow:
3394 setValue(&I, DAG.getNode(ISD::FPOW,
3395 getValue(I.getOperand(1)).getValueType(),
3396 getValue(I.getOperand(1)),
3397 getValue(I.getOperand(2))));
3399 case Intrinsic::pcmarker: {
3400 SDValue Tmp = getValue(I.getOperand(1));
3401 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3404 case Intrinsic::readcyclecounter: {
3405 SDValue Op = getRoot();
3406 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3407 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3410 DAG.setRoot(Tmp.getValue(1));
3413 case Intrinsic::part_select: {
3414 // Currently not implemented: just abort
3415 assert(0 && "part_select intrinsic not implemented");
3418 case Intrinsic::part_set: {
3419 // Currently not implemented: just abort
3420 assert(0 && "part_set intrinsic not implemented");
3423 case Intrinsic::bswap:
3424 setValue(&I, DAG.getNode(ISD::BSWAP,
3425 getValue(I.getOperand(1)).getValueType(),
3426 getValue(I.getOperand(1))));
3428 case Intrinsic::cttz: {
3429 SDValue Arg = getValue(I.getOperand(1));
3430 MVT Ty = Arg.getValueType();
3431 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3432 setValue(&I, result);
3435 case Intrinsic::ctlz: {
3436 SDValue Arg = getValue(I.getOperand(1));
3437 MVT Ty = Arg.getValueType();
3438 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3439 setValue(&I, result);
3442 case Intrinsic::ctpop: {
3443 SDValue Arg = getValue(I.getOperand(1));
3444 MVT Ty = Arg.getValueType();
3445 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3446 setValue(&I, result);
3449 case Intrinsic::stacksave: {
3450 SDValue Op = getRoot();
3451 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
3452 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3454 DAG.setRoot(Tmp.getValue(1));
3457 case Intrinsic::stackrestore: {
3458 SDValue Tmp = getValue(I.getOperand(1));
3459 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3462 case Intrinsic::var_annotation:
3463 // Discard annotate attributes
3466 case Intrinsic::init_trampoline: {
3467 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3471 Ops[1] = getValue(I.getOperand(1));
3472 Ops[2] = getValue(I.getOperand(2));
3473 Ops[3] = getValue(I.getOperand(3));
3474 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3475 Ops[5] = DAG.getSrcValue(F);
3477 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
3478 DAG.getNodeValueTypes(TLI.getPointerTy(),
3483 DAG.setRoot(Tmp.getValue(1));
3487 case Intrinsic::gcroot:
3489 Value *Alloca = I.getOperand(1);
3490 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3492 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3493 GCI->addStackRoot(FI->getIndex(), TypeMap);
3497 case Intrinsic::gcread:
3498 case Intrinsic::gcwrite:
3499 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3502 case Intrinsic::flt_rounds: {
3503 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3507 case Intrinsic::trap: {
3508 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3511 case Intrinsic::prefetch: {
3514 Ops[1] = getValue(I.getOperand(1));
3515 Ops[2] = getValue(I.getOperand(2));
3516 Ops[3] = getValue(I.getOperand(3));
3517 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3521 case Intrinsic::memory_barrier: {
3524 for (int x = 1; x < 6; ++x)
3525 Ops[x] = getValue(I.getOperand(x));
3527 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3530 case Intrinsic::atomic_cmp_swap: {
3531 SDValue Root = getRoot();
3532 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
3533 getValue(I.getOperand(1)),
3534 getValue(I.getOperand(2)),
3535 getValue(I.getOperand(3)),
3538 DAG.setRoot(L.getValue(1));
3541 case Intrinsic::atomic_load_add:
3542 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3543 case Intrinsic::atomic_load_sub:
3544 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
3545 case Intrinsic::atomic_load_and:
3546 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3547 case Intrinsic::atomic_load_or:
3548 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3549 case Intrinsic::atomic_load_xor:
3550 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3551 case Intrinsic::atomic_load_nand:
3552 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3553 case Intrinsic::atomic_load_min:
3554 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3555 case Intrinsic::atomic_load_max:
3556 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3557 case Intrinsic::atomic_load_umin:
3558 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3559 case Intrinsic::atomic_load_umax:
3560 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3561 case Intrinsic::atomic_swap:
3562 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3567 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
3569 MachineBasicBlock *LandingPad) {
3570 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3571 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3572 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3573 unsigned BeginLabel = 0, EndLabel = 0;
3575 TargetLowering::ArgListTy Args;
3576 TargetLowering::ArgListEntry Entry;
3577 Args.reserve(CS.arg_size());
3578 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3580 SDValue ArgNode = getValue(*i);
3581 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3583 unsigned attrInd = i - CS.arg_begin() + 1;
3584 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3585 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3586 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3587 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3588 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3589 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3590 Entry.Alignment = CS.getParamAlignment(attrInd);
3591 Args.push_back(Entry);
3594 if (LandingPad && MMI) {
3595 // Insert a label before the invoke call to mark the try range. This can be
3596 // used to detect deletion of the invoke via the MachineModuleInfo.
3597 BeginLabel = MMI->NextLabelID();
3598 // Both PendingLoads and PendingExports must be flushed here;
3599 // this call might not return.
3601 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
3604 std::pair<SDValue,SDValue> Result =
3605 TLI.LowerCallTo(getRoot(), CS.getType(),
3606 CS.paramHasAttr(0, ParamAttr::SExt),
3607 CS.paramHasAttr(0, ParamAttr::ZExt),
3608 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3610 if (CS.getType() != Type::VoidTy)
3611 setValue(CS.getInstruction(), Result.first);
3612 DAG.setRoot(Result.second);
3614 if (LandingPad && MMI) {
3615 // Insert a label at the end of the invoke call to mark the try range. This
3616 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3617 EndLabel = MMI->NextLabelID();
3618 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
3620 // Inform MachineModuleInfo of range.
3621 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3626 void SelectionDAGLowering::visitCall(CallInst &I) {
3627 const char *RenameFn = 0;
3628 if (Function *F = I.getCalledFunction()) {
3629 if (F->isDeclaration()) {
3630 if (unsigned IID = F->getIntrinsicID()) {
3631 RenameFn = visitIntrinsicCall(I, IID);
3637 // Check for well-known libc/libm calls. If the function is internal, it
3638 // can't be a library call.
3639 unsigned NameLen = F->getNameLen();
3640 if (!F->hasInternalLinkage() && NameLen) {
3641 const char *NameStr = F->getNameStart();
3642 if (NameStr[0] == 'c' &&
3643 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3644 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3645 if (I.getNumOperands() == 3 && // Basic sanity checks.
3646 I.getOperand(1)->getType()->isFloatingPoint() &&
3647 I.getType() == I.getOperand(1)->getType() &&
3648 I.getType() == I.getOperand(2)->getType()) {
3649 SDValue LHS = getValue(I.getOperand(1));
3650 SDValue RHS = getValue(I.getOperand(2));
3651 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3655 } else if (NameStr[0] == 'f' &&
3656 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3657 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3658 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3659 if (I.getNumOperands() == 2 && // Basic sanity checks.
3660 I.getOperand(1)->getType()->isFloatingPoint() &&
3661 I.getType() == I.getOperand(1)->getType()) {
3662 SDValue Tmp = getValue(I.getOperand(1));
3663 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3666 } else if (NameStr[0] == 's' &&
3667 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3668 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3669 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3670 if (I.getNumOperands() == 2 && // Basic sanity checks.
3671 I.getOperand(1)->getType()->isFloatingPoint() &&
3672 I.getType() == I.getOperand(1)->getType()) {
3673 SDValue Tmp = getValue(I.getOperand(1));
3674 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3677 } else if (NameStr[0] == 'c' &&
3678 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3679 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3680 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3681 if (I.getNumOperands() == 2 && // Basic sanity checks.
3682 I.getOperand(1)->getType()->isFloatingPoint() &&
3683 I.getType() == I.getOperand(1)->getType()) {
3684 SDValue Tmp = getValue(I.getOperand(1));
3685 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3690 } else if (isa<InlineAsm>(I.getOperand(0))) {
3697 Callee = getValue(I.getOperand(0));
3699 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3701 LowerCallTo(&I, Callee, I.isTailCall());
3705 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3706 /// this value and returns the result as a ValueVT value. This uses
3707 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3708 /// If the Flag pointer is NULL, no flag is used.
3709 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3711 SDValue *Flag) const {
3712 // Assemble the legal parts into the final values.
3713 SmallVector<SDValue, 4> Values(ValueVTs.size());
3714 SmallVector<SDValue, 8> Parts;
3715 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3716 // Copy the legal parts from the registers.
3717 MVT ValueVT = ValueVTs[Value];
3718 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3719 MVT RegisterVT = RegVTs[Value];
3721 Parts.resize(NumRegs);
3722 for (unsigned i = 0; i != NumRegs; ++i) {
3725 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3727 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3728 *Flag = P.getValue(2);
3730 Chain = P.getValue(1);
3732 // If the source register was virtual and if we know something about it,
3733 // add an assert node.
3734 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3735 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3736 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3737 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3738 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3739 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3741 unsigned RegSize = RegisterVT.getSizeInBits();
3742 unsigned NumSignBits = LOI.NumSignBits;
3743 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3745 // FIXME: We capture more information than the dag can represent. For
3746 // now, just use the tightest assertzext/assertsext possible.
3748 MVT FromVT(MVT::Other);
3749 if (NumSignBits == RegSize)
3750 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3751 else if (NumZeroBits >= RegSize-1)
3752 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3753 else if (NumSignBits > RegSize-8)
3754 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3755 else if (NumZeroBits >= RegSize-9)
3756 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3757 else if (NumSignBits > RegSize-16)
3758 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3759 else if (NumZeroBits >= RegSize-17)
3760 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3761 else if (NumSignBits > RegSize-32)
3762 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3763 else if (NumZeroBits >= RegSize-33)
3764 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3766 if (FromVT != MVT::Other) {
3767 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3768 RegisterVT, P, DAG.getValueType(FromVT));
3777 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3782 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3783 &Values[0], ValueVTs.size());
3786 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3787 /// specified value into the registers specified by this object. This uses
3788 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3789 /// If the Flag pointer is NULL, no flag is used.
3790 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
3791 SDValue &Chain, SDValue *Flag) const {
3792 // Get the list of the values's legal parts.
3793 unsigned NumRegs = Regs.size();
3794 SmallVector<SDValue, 8> Parts(NumRegs);
3795 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3796 MVT ValueVT = ValueVTs[Value];
3797 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3798 MVT RegisterVT = RegVTs[Value];
3800 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3801 &Parts[Part], NumParts, RegisterVT);
3805 // Copy the parts into the registers.
3806 SmallVector<SDValue, 8> Chains(NumRegs);
3807 for (unsigned i = 0; i != NumRegs; ++i) {
3810 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3812 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3813 *Flag = Part.getValue(1);
3815 Chains[i] = Part.getValue(0);
3818 if (NumRegs == 1 || Flag)
3819 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3820 // flagged to it. That is the CopyToReg nodes and the user are considered
3821 // a single scheduling unit. If we create a TokenFactor and return it as
3822 // chain, then the TokenFactor is both a predecessor (operand) of the
3823 // user as well as a successor (the TF operands are flagged to the user).
3824 // c1, f1 = CopyToReg
3825 // c2, f2 = CopyToReg
3826 // c3 = TokenFactor c1, c2
3829 Chain = Chains[NumRegs-1];
3831 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3834 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3835 /// operand list. This adds the code marker and includes the number of
3836 /// values added into it.
3837 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3838 std::vector<SDValue> &Ops) const {
3839 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3840 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3842 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3843 MVT RegisterVT = RegVTs[Value];
3844 for (unsigned i = 0; i != NumRegs; ++i)
3845 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3849 /// isAllocatableRegister - If the specified register is safe to allocate,
3850 /// i.e. it isn't a stack pointer or some other special register, return the
3851 /// register class for the register. Otherwise, return null.
3852 static const TargetRegisterClass *
3853 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3854 const TargetLowering &TLI,
3855 const TargetRegisterInfo *TRI) {
3856 MVT FoundVT = MVT::Other;
3857 const TargetRegisterClass *FoundRC = 0;
3858 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3859 E = TRI->regclass_end(); RCI != E; ++RCI) {
3860 MVT ThisVT = MVT::Other;
3862 const TargetRegisterClass *RC = *RCI;
3863 // If none of the the value types for this register class are valid, we
3864 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3865 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3867 if (TLI.isTypeLegal(*I)) {
3868 // If we have already found this register in a different register class,
3869 // choose the one with the largest VT specified. For example, on
3870 // PowerPC, we favor f64 register classes over f32.
3871 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3878 if (ThisVT == MVT::Other) continue;
3880 // NOTE: This isn't ideal. In particular, this might allocate the
3881 // frame pointer in functions that need it (due to them not being taken
3882 // out of allocation, because a variable sized allocation hasn't been seen
3883 // yet). This is a slight code pessimization, but should still work.
3884 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3885 E = RC->allocation_order_end(MF); I != E; ++I)
3887 // We found a matching register class. Keep looking at others in case
3888 // we find one with larger registers that this physreg is also in.
3899 /// AsmOperandInfo - This contains information for each constraint that we are
3901 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3902 /// CallOperand - If this is the result output operand or a clobber
3903 /// this is null, otherwise it is the incoming operand to the CallInst.
3904 /// This gets modified as the asm is processed.
3905 SDValue CallOperand;
3907 /// AssignedRegs - If this is a register or register class operand, this
3908 /// contains the set of register corresponding to the operand.
3909 RegsForValue AssignedRegs;
3911 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3912 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3915 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3916 /// busy in OutputRegs/InputRegs.
3917 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3918 std::set<unsigned> &OutputRegs,
3919 std::set<unsigned> &InputRegs,
3920 const TargetRegisterInfo &TRI) const {
3922 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3923 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3926 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3927 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3932 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3934 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3935 const TargetRegisterInfo &TRI) {
3936 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3938 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3939 for (; *Aliases; ++Aliases)
3940 Regs.insert(*Aliases);
3943 } // end anon namespace.
3946 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3947 /// specified operand. We prefer to assign virtual registers, to allow the
3948 /// register allocator handle the assignment process. However, if the asm uses
3949 /// features that we can't model on machineinstrs, we have SDISel do the
3950 /// allocation. This produces generally horrible, but correct, code.
3952 /// OpInfo describes the operand.
3953 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3954 /// or any explicitly clobbered registers.
3955 /// Input and OutputRegs are the set of already allocated physical registers.
3957 void SelectionDAGLowering::
3958 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3959 std::set<unsigned> &OutputRegs,
3960 std::set<unsigned> &InputRegs) {
3961 // Compute whether this value requires an input register, an output register,
3963 bool isOutReg = false;
3964 bool isInReg = false;
3965 switch (OpInfo.Type) {
3966 case InlineAsm::isOutput:
3969 // If this is an early-clobber output, or if there is an input
3970 // constraint that matches this, we need to reserve the input register
3971 // so no other inputs allocate to it.
3972 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3974 case InlineAsm::isInput:
3978 case InlineAsm::isClobber:
3985 MachineFunction &MF = DAG.getMachineFunction();
3986 SmallVector<unsigned, 4> Regs;
3988 // If this is a constraint for a single physreg, or a constraint for a
3989 // register class, find it.
3990 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3991 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3992 OpInfo.ConstraintVT);
3994 unsigned NumRegs = 1;
3995 if (OpInfo.ConstraintVT != MVT::Other)
3996 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3998 MVT ValueVT = OpInfo.ConstraintVT;
4001 // If this is a constraint for a specific physical register, like {r17},
4003 if (PhysReg.first) {
4004 if (OpInfo.ConstraintVT == MVT::Other)
4005 ValueVT = *PhysReg.second->vt_begin();
4007 // Get the actual register value type. This is important, because the user
4008 // may have asked for (e.g.) the AX register in i32 type. We need to
4009 // remember that AX is actually i16 to get the right extension.
4010 RegVT = *PhysReg.second->vt_begin();
4012 // This is a explicit reference to a physical register.
4013 Regs.push_back(PhysReg.first);
4015 // If this is an expanded reference, add the rest of the regs to Regs.
4017 TargetRegisterClass::iterator I = PhysReg.second->begin();
4018 for (; *I != PhysReg.first; ++I)
4019 assert(I != PhysReg.second->end() && "Didn't find reg!");
4021 // Already added the first reg.
4023 for (; NumRegs; --NumRegs, ++I) {
4024 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4028 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4029 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4030 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4034 // Otherwise, if this was a reference to an LLVM register class, create vregs
4035 // for this reference.
4036 std::vector<unsigned> RegClassRegs;
4037 const TargetRegisterClass *RC = PhysReg.second;
4039 // If this is an early clobber or tied register, our regalloc doesn't know
4040 // how to maintain the constraint. If it isn't, go ahead and create vreg
4041 // and let the regalloc do the right thing.
4042 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4043 // If there is some other early clobber and this is an input register,
4044 // then we are forced to pre-allocate the input reg so it doesn't
4045 // conflict with the earlyclobber.
4046 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4047 RegVT = *PhysReg.second->vt_begin();
4049 if (OpInfo.ConstraintVT == MVT::Other)
4052 // Create the appropriate number of virtual registers.
4053 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4054 for (; NumRegs; --NumRegs)
4055 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4057 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4061 // Otherwise, we can't allocate it. Let the code below figure out how to
4062 // maintain these constraints.
4063 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4066 // This is a reference to a register class that doesn't directly correspond
4067 // to an LLVM register class. Allocate NumRegs consecutive, available,
4068 // registers from the class.
4069 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4070 OpInfo.ConstraintVT);
4073 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4074 unsigned NumAllocated = 0;
4075 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4076 unsigned Reg = RegClassRegs[i];
4077 // See if this register is available.
4078 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4079 (isInReg && InputRegs.count(Reg))) { // Already used.
4080 // Make sure we find consecutive registers.
4085 // Check to see if this register is allocatable (i.e. don't give out the
4088 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4089 if (!RC) { // Couldn't allocate this register.
4090 // Reset NumAllocated to make sure we return consecutive registers.
4096 // Okay, this register is good, we can use it.
4099 // If we allocated enough consecutive registers, succeed.
4100 if (NumAllocated == NumRegs) {
4101 unsigned RegStart = (i-NumAllocated)+1;
4102 unsigned RegEnd = i+1;
4103 // Mark all of the allocated registers used.
4104 for (unsigned i = RegStart; i != RegEnd; ++i)
4105 Regs.push_back(RegClassRegs[i]);
4107 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4108 OpInfo.ConstraintVT);
4109 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4114 // Otherwise, we couldn't allocate enough registers for this.
4118 /// visitInlineAsm - Handle a call to an InlineAsm object.
4120 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4121 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4123 /// ConstraintOperands - Information about all of the constraints.
4124 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4126 SDValue Chain = getRoot();
4129 std::set<unsigned> OutputRegs, InputRegs;
4131 // Do a prepass over the constraints, canonicalizing them, and building up the
4132 // ConstraintOperands list.
4133 std::vector<InlineAsm::ConstraintInfo>
4134 ConstraintInfos = IA->ParseConstraints();
4136 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4137 // constraint. If so, we can't let the register allocator allocate any input
4138 // registers, because it will not know to avoid the earlyclobbered output reg.
4139 bool SawEarlyClobber = false;
4141 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4142 unsigned ResNo = 0; // ResNo - The result number of the next output.
4143 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4144 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4145 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4147 MVT OpVT = MVT::Other;
4149 // Compute the value type for each operand.
4150 switch (OpInfo.Type) {
4151 case InlineAsm::isOutput:
4152 // Indirect outputs just consume an argument.
4153 if (OpInfo.isIndirect) {
4154 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4157 // The return value of the call is this value. As such, there is no
4158 // corresponding argument.
4159 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4160 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4161 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4163 assert(ResNo == 0 && "Asm only has one result!");
4164 OpVT = TLI.getValueType(CS.getType());
4168 case InlineAsm::isInput:
4169 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4171 case InlineAsm::isClobber:
4176 // If this is an input or an indirect output, process the call argument.
4177 // BasicBlocks are labels, currently appearing only in asm's.
4178 if (OpInfo.CallOperandVal) {
4179 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4180 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4182 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4183 const Type *OpTy = OpInfo.CallOperandVal->getType();
4184 // If this is an indirect operand, the operand is a pointer to the
4186 if (OpInfo.isIndirect)
4187 OpTy = cast<PointerType>(OpTy)->getElementType();
4189 // If OpTy is not a single value, it may be a struct/union that we
4190 // can tile with integers.
4191 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4192 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4200 OpTy = IntegerType::get(BitSize);
4205 OpVT = TLI.getValueType(OpTy, true);
4209 OpInfo.ConstraintVT = OpVT;
4211 // Compute the constraint code and ConstraintType to use.
4212 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4214 // Keep track of whether we see an earlyclobber.
4215 SawEarlyClobber |= OpInfo.isEarlyClobber;
4217 // If we see a clobber of a register, it is an early clobber.
4218 if (!SawEarlyClobber &&
4219 OpInfo.Type == InlineAsm::isClobber &&
4220 OpInfo.ConstraintType == TargetLowering::C_Register) {
4221 // Note that we want to ignore things that we don't trick here, like
4222 // dirflag, fpsr, flags, etc.
4223 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4224 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4225 OpInfo.ConstraintVT);
4226 if (PhysReg.first || PhysReg.second) {
4227 // This is a register we know of.
4228 SawEarlyClobber = true;
4232 // If this is a memory input, and if the operand is not indirect, do what we
4233 // need to to provide an address for the memory input.
4234 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4235 !OpInfo.isIndirect) {
4236 assert(OpInfo.Type == InlineAsm::isInput &&
4237 "Can only indirectify direct input operands!");
4239 // Memory operands really want the address of the value. If we don't have
4240 // an indirect input, put it in the constpool if we can, otherwise spill
4241 // it to a stack slot.
4243 // If the operand is a float, integer, or vector constant, spill to a
4244 // constant pool entry to get its address.
4245 Value *OpVal = OpInfo.CallOperandVal;
4246 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4247 isa<ConstantVector>(OpVal)) {
4248 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4249 TLI.getPointerTy());
4251 // Otherwise, create a stack slot and emit a store to it before the
4253 const Type *Ty = OpVal->getType();
4254 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4255 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4256 MachineFunction &MF = DAG.getMachineFunction();
4257 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4258 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4259 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4260 OpInfo.CallOperand = StackSlot;
4263 // There is no longer a Value* corresponding to this operand.
4264 OpInfo.CallOperandVal = 0;
4265 // It is now an indirect operand.
4266 OpInfo.isIndirect = true;
4269 // If this constraint is for a specific register, allocate it before
4271 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4272 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4274 ConstraintInfos.clear();
4277 // Second pass - Loop over all of the operands, assigning virtual or physregs
4278 // to registerclass operands.
4279 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4280 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4282 // C_Register operands have already been allocated, Other/Memory don't need
4284 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4285 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4288 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4289 std::vector<SDValue> AsmNodeOperands;
4290 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
4291 AsmNodeOperands.push_back(
4292 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4295 // Loop over all of the inputs, copying the operand values into the
4296 // appropriate registers and processing the output regs.
4297 RegsForValue RetValRegs;
4299 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4300 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4302 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4303 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4305 switch (OpInfo.Type) {
4306 case InlineAsm::isOutput: {
4307 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4308 OpInfo.ConstraintType != TargetLowering::C_Register) {
4309 // Memory output, or 'other' output (e.g. 'X' constraint).
4310 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4312 // Add information to the INLINEASM node to know about this output.
4313 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4314 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4315 TLI.getPointerTy()));
4316 AsmNodeOperands.push_back(OpInfo.CallOperand);
4320 // Otherwise, this is a register or register class output.
4322 // Copy the output from the appropriate register. Find a register that
4324 if (OpInfo.AssignedRegs.Regs.empty()) {
4325 cerr << "Couldn't allocate output reg for constraint '"
4326 << OpInfo.ConstraintCode << "'!\n";
4330 // If this is an indirect operand, store through the pointer after the
4332 if (OpInfo.isIndirect) {
4333 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4334 OpInfo.CallOperandVal));
4336 // This is the result value of the call.
4337 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4338 // Concatenate this output onto the outputs list.
4339 RetValRegs.append(OpInfo.AssignedRegs);
4342 // Add information to the INLINEASM node to know that this register is
4344 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4348 case InlineAsm::isInput: {
4349 SDValue InOperandVal = OpInfo.CallOperand;
4351 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4352 // If this is required to match an output register we have already set,
4353 // just use its register.
4354 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4356 // Scan until we find the definition we already emitted of this operand.
4357 // When we find it, create a RegsForValue operand.
4358 unsigned CurOp = 2; // The first operand.
4359 for (; OperandNo; --OperandNo) {
4360 // Advance to the next operand.
4362 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4363 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4364 (NumOps & 7) == 4 /*MEM*/) &&
4365 "Skipped past definitions?");
4366 CurOp += (NumOps>>3)+1;
4370 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4371 if ((NumOps & 7) == 2 /*REGDEF*/) {
4372 // Add NumOps>>3 registers to MatchedRegs.
4373 RegsForValue MatchedRegs;
4374 MatchedRegs.TLI = &TLI;
4375 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4376 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4377 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4379 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4380 MatchedRegs.Regs.push_back(Reg);
4383 // Use the produced MatchedRegs object to
4384 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4385 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4388 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4389 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4390 // Add information to the INLINEASM node to know about this input.
4391 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4392 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4393 TLI.getPointerTy()));
4394 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4399 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4400 assert(!OpInfo.isIndirect &&
4401 "Don't know how to handle indirect other inputs yet!");
4403 std::vector<SDValue> Ops;
4404 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4407 cerr << "Invalid operand for inline asm constraint '"
4408 << OpInfo.ConstraintCode << "'!\n";
4412 // Add information to the INLINEASM node to know about this input.
4413 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4414 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4415 TLI.getPointerTy()));
4416 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4418 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4419 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4420 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4421 "Memory operands expect pointer values");
4423 // Add information to the INLINEASM node to know about this input.
4424 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4425 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4426 TLI.getPointerTy()));
4427 AsmNodeOperands.push_back(InOperandVal);
4431 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4432 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4433 "Unknown constraint type!");
4434 assert(!OpInfo.isIndirect &&
4435 "Don't know how to handle indirect register inputs yet!");
4437 // Copy the input into the appropriate registers.
4438 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4439 "Couldn't allocate input reg!");
4441 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4443 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4447 case InlineAsm::isClobber: {
4448 // Add the clobbered value to the operand list, so that the register
4449 // allocator is aware that the physreg got clobbered.
4450 if (!OpInfo.AssignedRegs.Regs.empty())
4451 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4458 // Finish up input operands.
4459 AsmNodeOperands[0] = Chain;
4460 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4462 Chain = DAG.getNode(ISD::INLINEASM,
4463 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4464 &AsmNodeOperands[0], AsmNodeOperands.size());
4465 Flag = Chain.getValue(1);
4467 // If this asm returns a register value, copy the result from that register
4468 // and set it as the value of the call.
4469 if (!RetValRegs.Regs.empty()) {
4470 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4472 // If any of the results of the inline asm is a vector, it may have the
4473 // wrong width/num elts. This can happen for register classes that can
4474 // contain multiple different value types. The preg or vreg allocated may
4475 // not have the same VT as was expected. Convert it to the right type with
4477 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4478 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4479 if (Val.Val->getValueType(i).isVector())
4480 Val = DAG.getNode(ISD::BIT_CONVERT,
4481 TLI.getValueType(ResSTy->getElementType(i)), Val);
4484 if (Val.getValueType().isVector())
4485 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4489 setValue(CS.getInstruction(), Val);
4492 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
4494 // Process indirect outputs, first output all of the flagged copies out of
4496 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4497 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4498 Value *Ptr = IndirectStoresToEmit[i].second;
4499 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4500 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4503 // Emit the non-flagged stores from the physregs.
4504 SmallVector<SDValue, 8> OutChains;
4505 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4506 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4507 getValue(StoresToEmit[i].second),
4508 StoresToEmit[i].second, 0));
4509 if (!OutChains.empty())
4510 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4511 &OutChains[0], OutChains.size());
4516 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4517 SDValue Src = getValue(I.getOperand(0));
4519 MVT IntPtr = TLI.getPointerTy();
4521 if (IntPtr.bitsLT(Src.getValueType()))
4522 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4523 else if (IntPtr.bitsGT(Src.getValueType()))
4524 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4526 // Scale the source by the type size.
4527 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4528 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4529 Src, DAG.getIntPtrConstant(ElementSize));
4531 TargetLowering::ArgListTy Args;
4532 TargetLowering::ArgListEntry Entry;
4534 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4535 Args.push_back(Entry);
4537 std::pair<SDValue,SDValue> Result =
4538 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4539 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4540 setValue(&I, Result.first); // Pointers always fit in registers
4541 DAG.setRoot(Result.second);
4544 void SelectionDAGLowering::visitFree(FreeInst &I) {
4545 TargetLowering::ArgListTy Args;
4546 TargetLowering::ArgListEntry Entry;
4547 Entry.Node = getValue(I.getOperand(0));
4548 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4549 Args.push_back(Entry);
4550 MVT IntPtr = TLI.getPointerTy();
4551 std::pair<SDValue,SDValue> Result =
4552 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4553 CallingConv::C, true,
4554 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4555 DAG.setRoot(Result.second);
4558 // EmitInstrWithCustomInserter - This method should be implemented by targets
4559 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4560 // instructions are special in various ways, which require special support to
4561 // insert. The specified MachineInstr is created but not inserted into any
4562 // basic blocks, and the scheduler passes ownership of it to this method.
4563 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4564 MachineBasicBlock *MBB) {
4565 cerr << "If a target marks an instruction with "
4566 << "'usesCustomDAGSchedInserter', it must implement "
4567 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4572 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4573 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4574 getValue(I.getOperand(1)),
4575 DAG.getSrcValue(I.getOperand(1))));
4578 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4579 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4580 getValue(I.getOperand(0)),
4581 DAG.getSrcValue(I.getOperand(0)));
4583 DAG.setRoot(V.getValue(1));
4586 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4587 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4588 getValue(I.getOperand(1)),
4589 DAG.getSrcValue(I.getOperand(1))));
4592 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4593 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4594 getValue(I.getOperand(1)),
4595 getValue(I.getOperand(2)),
4596 DAG.getSrcValue(I.getOperand(1)),
4597 DAG.getSrcValue(I.getOperand(2))));
4600 /// TargetLowering::LowerArguments - This is the default LowerArguments
4601 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4602 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4603 /// integrated into SDISel.
4604 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4605 SmallVectorImpl<SDValue> &ArgValues) {
4606 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4607 SmallVector<SDValue, 3+16> Ops;
4608 Ops.push_back(DAG.getRoot());
4609 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4610 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4612 // Add one result value for each formal argument.
4613 SmallVector<MVT, 16> RetVals;
4615 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4617 SmallVector<MVT, 4> ValueVTs;
4618 ComputeValueVTs(*this, I->getType(), ValueVTs);
4619 for (unsigned Value = 0, NumValues = ValueVTs.size();
4620 Value != NumValues; ++Value) {
4621 MVT VT = ValueVTs[Value];
4622 const Type *ArgTy = VT.getTypeForMVT();
4623 ISD::ArgFlagsTy Flags;
4624 unsigned OriginalAlignment =
4625 getTargetData()->getABITypeAlignment(ArgTy);
4627 if (F.paramHasAttr(j, ParamAttr::ZExt))
4629 if (F.paramHasAttr(j, ParamAttr::SExt))
4631 if (F.paramHasAttr(j, ParamAttr::InReg))
4633 if (F.paramHasAttr(j, ParamAttr::StructRet))
4635 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4637 const PointerType *Ty = cast<PointerType>(I->getType());
4638 const Type *ElementTy = Ty->getElementType();
4639 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4640 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4641 // For ByVal, alignment should be passed from FE. BE will guess if
4642 // this info is not there but there are cases it cannot get right.
4643 if (F.getParamAlignment(j))
4644 FrameAlign = F.getParamAlignment(j);
4645 Flags.setByValAlign(FrameAlign);
4646 Flags.setByValSize(FrameSize);
4648 if (F.paramHasAttr(j, ParamAttr::Nest))
4650 Flags.setOrigAlign(OriginalAlignment);
4652 MVT RegisterVT = getRegisterType(VT);
4653 unsigned NumRegs = getNumRegisters(VT);
4654 for (unsigned i = 0; i != NumRegs; ++i) {
4655 RetVals.push_back(RegisterVT);
4656 ISD::ArgFlagsTy MyFlags = Flags;
4657 if (NumRegs > 1 && i == 0)
4659 // if it isn't first piece, alignment must be 1
4661 MyFlags.setOrigAlign(1);
4662 Ops.push_back(DAG.getArgFlags(MyFlags));
4667 RetVals.push_back(MVT::Other);
4670 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4671 DAG.getVTList(&RetVals[0], RetVals.size()),
4672 &Ops[0], Ops.size()).Val;
4674 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4675 // allows exposing the loads that may be part of the argument access to the
4676 // first DAGCombiner pass.
4677 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
4679 // The number of results should match up, except that the lowered one may have
4680 // an extra flag result.
4681 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4682 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4683 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4684 && "Lowering produced unexpected number of results!");
4686 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
4687 if (Result != TmpRes.Val && Result->use_empty()) {
4688 HandleSDNode Dummy(DAG.getRoot());
4689 DAG.RemoveDeadNode(Result);
4692 Result = TmpRes.Val;
4694 unsigned NumArgRegs = Result->getNumValues() - 1;
4695 DAG.setRoot(SDValue(Result, NumArgRegs));
4697 // Set up the return result vector.
4700 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4702 SmallVector<MVT, 4> ValueVTs;
4703 ComputeValueVTs(*this, I->getType(), ValueVTs);
4704 for (unsigned Value = 0, NumValues = ValueVTs.size();
4705 Value != NumValues; ++Value) {
4706 MVT VT = ValueVTs[Value];
4707 MVT PartVT = getRegisterType(VT);
4709 unsigned NumParts = getNumRegisters(VT);
4710 SmallVector<SDValue, 4> Parts(NumParts);
4711 for (unsigned j = 0; j != NumParts; ++j)
4712 Parts[j] = SDValue(Result, i++);
4714 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4715 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4716 AssertOp = ISD::AssertSext;
4717 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4718 AssertOp = ISD::AssertZext;
4720 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4724 assert(i == NumArgRegs && "Argument register count mismatch!");
4728 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4729 /// implementation, which just inserts an ISD::CALL node, which is later custom
4730 /// lowered by the target to something concrete. FIXME: When all targets are
4731 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4732 std::pair<SDValue, SDValue>
4733 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
4734 bool RetSExt, bool RetZExt, bool isVarArg,
4735 unsigned CallingConv, bool isTailCall,
4737 ArgListTy &Args, SelectionDAG &DAG) {
4738 SmallVector<SDValue, 32> Ops;
4739 Ops.push_back(Chain); // Op#0 - Chain
4740 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4741 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4742 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4743 Ops.push_back(Callee);
4745 // Handle all of the outgoing arguments.
4746 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4747 SmallVector<MVT, 4> ValueVTs;
4748 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4749 for (unsigned Value = 0, NumValues = ValueVTs.size();
4750 Value != NumValues; ++Value) {
4751 MVT VT = ValueVTs[Value];
4752 const Type *ArgTy = VT.getTypeForMVT();
4753 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4754 ISD::ArgFlagsTy Flags;
4755 unsigned OriginalAlignment =
4756 getTargetData()->getABITypeAlignment(ArgTy);
4762 if (Args[i].isInReg)
4766 if (Args[i].isByVal) {
4768 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4769 const Type *ElementTy = Ty->getElementType();
4770 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4771 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4772 // For ByVal, alignment should come from FE. BE will guess if this
4773 // info is not there but there are cases it cannot get right.
4774 if (Args[i].Alignment)
4775 FrameAlign = Args[i].Alignment;
4776 Flags.setByValAlign(FrameAlign);
4777 Flags.setByValSize(FrameSize);
4781 Flags.setOrigAlign(OriginalAlignment);
4783 MVT PartVT = getRegisterType(VT);
4784 unsigned NumParts = getNumRegisters(VT);
4785 SmallVector<SDValue, 4> Parts(NumParts);
4786 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4789 ExtendKind = ISD::SIGN_EXTEND;
4790 else if (Args[i].isZExt)
4791 ExtendKind = ISD::ZERO_EXTEND;
4793 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4795 for (unsigned i = 0; i != NumParts; ++i) {
4796 // if it isn't first piece, alignment must be 1
4797 ISD::ArgFlagsTy MyFlags = Flags;
4798 if (NumParts > 1 && i == 0)
4801 MyFlags.setOrigAlign(1);
4803 Ops.push_back(Parts[i]);
4804 Ops.push_back(DAG.getArgFlags(MyFlags));
4809 // Figure out the result value types. We start by making a list of
4810 // the potentially illegal return value types.
4811 SmallVector<MVT, 4> LoweredRetTys;
4812 SmallVector<MVT, 4> RetTys;
4813 ComputeValueVTs(*this, RetTy, RetTys);
4815 // Then we translate that to a list of legal types.
4816 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4818 MVT RegisterVT = getRegisterType(VT);
4819 unsigned NumRegs = getNumRegisters(VT);
4820 for (unsigned i = 0; i != NumRegs; ++i)
4821 LoweredRetTys.push_back(RegisterVT);
4824 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4826 // Create the CALL node.
4827 SDValue Res = DAG.getNode(ISD::CALL,
4828 DAG.getVTList(&LoweredRetTys[0],
4829 LoweredRetTys.size()),
4830 &Ops[0], Ops.size());
4831 Chain = Res.getValue(LoweredRetTys.size() - 1);
4833 // Gather up the call result into a single value.
4834 if (RetTy != Type::VoidTy) {
4835 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4838 AssertOp = ISD::AssertSext;
4840 AssertOp = ISD::AssertZext;
4842 SmallVector<SDValue, 4> ReturnValues;
4844 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4846 MVT RegisterVT = getRegisterType(VT);
4847 unsigned NumRegs = getNumRegisters(VT);
4848 unsigned RegNoEnd = NumRegs + RegNo;
4849 SmallVector<SDValue, 4> Results;
4850 for (; RegNo != RegNoEnd; ++RegNo)
4851 Results.push_back(Res.getValue(RegNo));
4852 SDValue ReturnValue =
4853 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4855 ReturnValues.push_back(ReturnValue);
4857 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4858 &ReturnValues[0], ReturnValues.size());
4861 return std::make_pair(Res, Chain);
4864 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4865 assert(0 && "LowerOperation not implemented for this target!");
4871 //===----------------------------------------------------------------------===//
4872 // SelectionDAGISel code
4873 //===----------------------------------------------------------------------===//
4875 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4876 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4879 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4880 AU.addRequired<AliasAnalysis>();
4881 AU.addRequired<CollectorModuleMetadata>();
4882 AU.setPreservesAll();
4885 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4886 // Get alias analysis for load/store combining.
4887 AA = &getAnalysis<AliasAnalysis>();
4889 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4890 if (MF.getFunction()->hasCollector())
4891 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4894 RegInfo = &MF.getRegInfo();
4895 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4897 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4899 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4900 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4901 // Mark landing pad.
4902 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4904 SelectAllBasicBlocks(Fn, MF, FuncInfo);
4906 // Add function live-ins to entry block live-in set.
4907 BasicBlock *EntryBB = &Fn.getEntryBlock();
4908 BB = FuncInfo.MBBMap[EntryBB];
4909 if (!RegInfo->livein_empty())
4910 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4911 E = RegInfo->livein_end(); I != E; ++I)
4912 BB->addLiveIn(I->first);
4915 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4916 "Not all catch info was assigned to a landing pad!");
4922 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4923 SDValue Op = getValue(V);
4924 assert((Op.getOpcode() != ISD::CopyFromReg ||
4925 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4926 "Copy from a reg to the same reg!");
4927 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4929 RegsForValue RFV(TLI, Reg, V->getType());
4930 SDValue Chain = DAG.getEntryNode();
4931 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4932 PendingExports.push_back(Chain);
4935 void SelectionDAGISel::
4936 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4937 // If this is the entry block, emit arguments.
4938 Function &F = *LLVMBB->getParent();
4939 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4940 SDValue OldRoot = SDL.DAG.getRoot();
4941 SmallVector<SDValue, 16> Args;
4942 TLI.LowerArguments(F, SDL.DAG, Args);
4945 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4947 SmallVector<MVT, 4> ValueVTs;
4948 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4949 unsigned NumValues = ValueVTs.size();
4950 if (!AI->use_empty()) {
4951 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
4952 // If this argument is live outside of the entry block, insert a copy from
4953 // whereever we got it to the vreg that other BB's will reference it as.
4954 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4955 if (VMI != FuncInfo.ValueMap.end()) {
4956 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4962 // Finally, if the target has anything special to do, allow it to do so.
4963 // FIXME: this should insert code into the DAG!
4964 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4967 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4968 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4969 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4970 if (isSelector(I)) {
4971 // Apply the catch info to DestBB.
4972 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4974 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4975 FLI.CatchInfoFound.insert(I);
4980 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4981 /// whether object offset >= 0.
4983 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
4984 if (!isa<FrameIndexSDNode>(Op)) return false;
4986 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4987 int FrameIdx = FrameIdxNode->getIndex();
4988 return MFI->isFixedObjectIndex(FrameIdx) &&
4989 MFI->getObjectOffset(FrameIdx) >= 0;
4992 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
4993 /// possibly be overwritten when lowering the outgoing arguments in a tail
4994 /// call. Currently the implementation of this call is very conservative and
4995 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
4996 /// virtual registers would be overwritten by direct lowering.
4997 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
4998 MachineFrameInfo * MFI) {
4999 RegisterSDNode * OpReg = NULL;
5000 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
5001 (Op.getOpcode()== ISD::CopyFromReg &&
5002 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
5003 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
5004 (Op.getOpcode() == ISD::LOAD &&
5005 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
5006 (Op.getOpcode() == ISD::MERGE_VALUES &&
5007 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
5008 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
5014 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
5015 /// DAG and fixes their tailcall attribute operand.
5016 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
5017 TargetLowering& TLI) {
5018 SDNode * Ret = NULL;
5019 SDValue Terminator = DAG.getRoot();
5022 if (Terminator.getOpcode() == ISD::RET) {
5023 Ret = Terminator.Val;
5026 // Fix tail call attribute of CALL nodes.
5027 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5028 BI = DAG.allnodes_end(); BI != BE; ) {
5030 if (BI->getOpcode() == ISD::CALL) {
5031 SDValue OpRet(Ret, 0);
5032 SDValue OpCall(BI, 0);
5033 bool isMarkedTailCall =
5034 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5035 // If CALL node has tail call attribute set to true and the call is not
5036 // eligible (no RET or the target rejects) the attribute is fixed to
5037 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5038 // must correctly identify tail call optimizable calls.
5039 if (!isMarkedTailCall) continue;
5041 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5042 // Not eligible. Mark CALL node as non tail call.
5043 SmallVector<SDValue, 32> Ops;
5045 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5046 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5050 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5052 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5054 // Look for tail call clobbered arguments. Emit a series of
5055 // copyto/copyfrom virtual register nodes to protect them.
5056 SmallVector<SDValue, 32> Ops;
5057 SDValue Chain = OpCall.getOperand(0), InFlag;
5059 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5060 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5062 if (idx > 4 && (idx % 2)) {
5063 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5064 getArgFlags().isByVal();
5065 MachineFunction &MF = DAG.getMachineFunction();
5066 MachineFrameInfo *MFI = MF.getFrameInfo();
5068 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5069 MVT VT = Arg.getValueType();
5070 unsigned VReg = MF.getRegInfo().
5071 createVirtualRegister(TLI.getRegClassFor(VT));
5072 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5073 InFlag = Chain.getValue(1);
5074 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5075 Chain = Arg.getValue(1);
5076 InFlag = Arg.getValue(2);
5081 // Link in chain of CopyTo/CopyFromReg.
5083 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5089 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5090 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5091 FunctionLoweringInfo &FuncInfo) {
5092 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
5094 // Lower any arguments needed in this block if this is the entry block.
5095 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5096 LowerArguments(LLVMBB, SDL);
5098 BB = FuncInfo.MBBMap[LLVMBB];
5099 SDL.setCurrentBasicBlock(BB);
5101 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5103 if (MMI && BB->isLandingPad()) {
5104 // Add a label to mark the beginning of the landing pad. Deletion of the
5105 // landing pad can thus be detected via the MachineModuleInfo.
5106 unsigned LabelID = MMI->addLandingPad(BB);
5107 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
5109 // Mark exception register as live in.
5110 unsigned Reg = TLI.getExceptionAddressRegister();
5111 if (Reg) BB->addLiveIn(Reg);
5113 // Mark exception selector register as live in.
5114 Reg = TLI.getExceptionSelectorRegister();
5115 if (Reg) BB->addLiveIn(Reg);
5117 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5118 // function and list of typeids logically belong to the invoke (or, if you
5119 // like, the basic block containing the invoke), and need to be associated
5120 // with it in the dwarf exception handling tables. Currently however the
5121 // information is provided by an intrinsic (eh.selector) that can be moved
5122 // to unexpected places by the optimizers: if the unwind edge is critical,
5123 // then breaking it can result in the intrinsics being in the successor of
5124 // the landing pad, not the landing pad itself. This results in exceptions
5125 // not being caught because no typeids are associated with the invoke.
5126 // This may not be the only way things can go wrong, but it is the only way
5127 // we try to work around for the moment.
5128 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5130 if (Br && Br->isUnconditional()) { // Critical edge?
5131 BasicBlock::iterator I, E;
5132 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5137 // No catch info found - try to extract some from the successor.
5138 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5142 // Lower all of the non-terminator instructions.
5143 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
5147 // Ensure that all instructions which are used outside of their defining
5148 // blocks are available as virtual registers. Invoke is handled elsewhere.
5149 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
5150 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5151 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5152 if (VMI != FuncInfo.ValueMap.end())
5153 SDL.CopyValueToVirtualRegister(I, VMI->second);
5156 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5157 // ensure constants are generated when needed. Remember the virtual registers
5158 // that need to be added to the Machine PHI nodes as input. We cannot just
5159 // directly add them, because expansion might result in multiple MBB's for one
5160 // BB. As such, the start of the BB might correspond to a different MBB than
5163 TerminatorInst *TI = LLVMBB->getTerminator();
5165 // Emit constants only once even if used by multiple PHI nodes.
5166 std::map<Constant*, unsigned> ConstantsOut;
5168 // Vector bool would be better, but vector<bool> is really slow.
5169 std::vector<unsigned char> SuccsHandled;
5170 if (TI->getNumSuccessors())
5171 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5173 // Check successor nodes' PHI nodes that expect a constant to be available
5175 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5176 BasicBlock *SuccBB = TI->getSuccessor(succ);
5177 if (!isa<PHINode>(SuccBB->begin())) continue;
5178 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5180 // If this terminator has multiple identical successors (common for
5181 // switches), only handle each succ once.
5182 unsigned SuccMBBNo = SuccMBB->getNumber();
5183 if (SuccsHandled[SuccMBBNo]) continue;
5184 SuccsHandled[SuccMBBNo] = true;
5186 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5189 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5190 // nodes and Machine PHI nodes, but the incoming operands have not been
5192 for (BasicBlock::iterator I = SuccBB->begin();
5193 (PN = dyn_cast<PHINode>(I)); ++I) {
5194 // Ignore dead phi's.
5195 if (PN->use_empty()) continue;
5198 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5200 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5201 unsigned &RegOut = ConstantsOut[C];
5203 RegOut = FuncInfo.CreateRegForValue(C);
5204 SDL.CopyValueToVirtualRegister(C, RegOut);
5208 Reg = FuncInfo.ValueMap[PHIOp];
5210 assert(isa<AllocaInst>(PHIOp) &&
5211 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5212 "Didn't codegen value into a register!??");
5213 Reg = FuncInfo.CreateRegForValue(PHIOp);
5214 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5218 // Remember that this register needs to added to the machine PHI node as
5219 // the input for this MBB.
5220 SmallVector<MVT, 4> ValueVTs;
5221 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5222 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5223 MVT VT = ValueVTs[vti];
5224 unsigned NumRegisters = TLI.getNumRegisters(VT);
5225 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5226 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5227 Reg += NumRegisters;
5231 ConstantsOut.clear();
5233 // Lower the terminator after the copies are emitted.
5234 SDL.visit(*LLVMBB->getTerminator());
5236 // Copy over any CaseBlock records that may now exist due to SwitchInst
5237 // lowering, as well as any jump table information.
5238 SwitchCases.clear();
5239 SwitchCases = SDL.SwitchCases;
5241 JTCases = SDL.JTCases;
5242 BitTestCases.clear();
5243 BitTestCases = SDL.BitTestCases;
5245 // Make sure the root of the DAG is up-to-date.
5246 DAG.setRoot(SDL.getControlRoot());
5248 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5249 // with correct tailcall attribute so that the target can rely on the tailcall
5250 // attribute indicating whether the call is really eligible for tail call
5252 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5255 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5256 SmallPtrSet<SDNode*, 128> VisitedNodes;
5257 SmallVector<SDNode*, 128> Worklist;
5259 Worklist.push_back(DAG.getRoot().Val);
5265 while (!Worklist.empty()) {
5266 SDNode *N = Worklist.back();
5267 Worklist.pop_back();
5269 // If we've already seen this node, ignore it.
5270 if (!VisitedNodes.insert(N))
5273 // Otherwise, add all chain operands to the worklist.
5274 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5275 if (N->getOperand(i).getValueType() == MVT::Other)
5276 Worklist.push_back(N->getOperand(i).Val);
5278 // If this is a CopyToReg with a vreg dest, process it.
5279 if (N->getOpcode() != ISD::CopyToReg)
5282 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5283 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5286 // Ignore non-scalar or non-integer values.
5287 SDValue Src = N->getOperand(2);
5288 MVT SrcVT = Src.getValueType();
5289 if (!SrcVT.isInteger() || SrcVT.isVector())
5292 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5293 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5294 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5296 // Only install this information if it tells us something.
5297 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5298 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5299 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5300 if (DestReg >= FLI.LiveOutRegInfo.size())
5301 FLI.LiveOutRegInfo.resize(DestReg+1);
5302 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5303 LOI.NumSignBits = NumSignBits;
5304 LOI.KnownOne = NumSignBits;
5305 LOI.KnownZero = NumSignBits;
5310 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5311 std::string GroupName;
5312 if (TimePassesIsEnabled)
5313 GroupName = "Instruction Selection and Scheduling";
5314 std::string BlockName;
5315 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
5316 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
5317 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' +
5318 BB->getBasicBlock()->getName();
5320 DOUT << "Initial selection DAG:\n";
5323 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName);
5325 // Run the DAG combiner in pre-legalize mode.
5326 if (TimePassesIsEnabled) {
5327 NamedRegionTimer T("DAG Combining 1", GroupName);
5328 DAG.Combine(false, *AA);
5330 DAG.Combine(false, *AA);
5333 DOUT << "Optimized lowered selection DAG:\n";
5336 // Second step, hack on the DAG until it only uses operations and types that
5337 // the target supports.
5338 if (EnableLegalizeTypes) {// Enable this some day.
5339 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " +
5342 if (TimePassesIsEnabled) {
5343 NamedRegionTimer T("Type Legalization", GroupName);
5344 DAG.LegalizeTypes();
5346 DAG.LegalizeTypes();
5349 DOUT << "Type-legalized selection DAG:\n";
5352 // TODO: enable a dag combine pass here.
5355 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName);
5357 if (TimePassesIsEnabled) {
5358 NamedRegionTimer T("DAG Legalization", GroupName);
5364 DOUT << "Legalized selection DAG:\n";
5367 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName);
5369 // Run the DAG combiner in post-legalize mode.
5370 if (TimePassesIsEnabled) {
5371 NamedRegionTimer T("DAG Combining 2", GroupName);
5372 DAG.Combine(true, *AA);
5374 DAG.Combine(true, *AA);
5377 DOUT << "Optimized legalized selection DAG:\n";
5380 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
5382 if (!FastISel && EnableValueProp)
5383 ComputeLiveOutVRegInfo(DAG);
5385 // Third, instruction select all of the operations to machine code, adding the
5386 // code to the MachineBasicBlock.
5387 if (TimePassesIsEnabled) {
5388 NamedRegionTimer T("Instruction Selection", GroupName);
5389 InstructionSelect(DAG);
5391 InstructionSelect(DAG);
5394 DOUT << "Selected selection DAG:\n";
5397 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName);
5399 // Schedule machine code.
5400 ScheduleDAG *Scheduler;
5401 if (TimePassesIsEnabled) {
5402 NamedRegionTimer T("Instruction Scheduling", GroupName);
5403 Scheduler = Schedule(DAG);
5405 Scheduler = Schedule(DAG);
5408 if (ViewSUnitDAGs) Scheduler->viewGraph();
5410 // Emit machine code to BB. This can change 'BB' to the last block being
5412 if (TimePassesIsEnabled) {
5413 NamedRegionTimer T("Instruction Creation", GroupName);
5414 BB = Scheduler->EmitSchedule();
5416 BB = Scheduler->EmitSchedule();
5419 // Free the scheduler state.
5420 if (TimePassesIsEnabled) {
5421 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
5427 // Perform target specific isel post processing.
5428 if (TimePassesIsEnabled) {
5429 NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
5430 InstructionSelectPostProcessing();
5432 InstructionSelectPostProcessing();
5435 DOUT << "Selected machine code:\n";
5439 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
5440 FunctionLoweringInfo &FuncInfo) {
5441 // Define NodeAllocator here so that memory allocation is reused for
5442 // each basic block.
5443 NodeAllocatorType NodeAllocator;
5445 SimpleBBISel SISel(MF, TLI);
5446 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5447 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
5448 BasicBlock *LLVMBB = &*I;
5449 PHINodesToUpdate.clear();
5451 if (!FastISel || !SISel.SelectBasicBlock(LLVMBB, FuncInfo.MBBMap[LLVMBB]))
5452 SelectBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
5453 FinishBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
5458 SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5459 FunctionLoweringInfo &FuncInfo,
5460 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5461 NodeAllocatorType &NodeAllocator) {
5462 SelectionDAG DAG(TLI, MF, FuncInfo,
5463 getAnalysisToUpdate<MachineModuleInfo>(),
5467 // First step, lower LLVM code to some DAG. This DAG may use operations and
5468 // types that are not supported by the target.
5469 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5471 // Second step, emit the lowered DAG as machine code.
5472 CodeGenAndEmitDAG(DAG);
5476 SelectionDAGISel::FinishBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5477 FunctionLoweringInfo &FuncInfo,
5478 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5479 NodeAllocatorType &NodeAllocator) {
5480 DOUT << "Total amount of phi nodes to update: "
5481 << PHINodesToUpdate.size() << "\n";
5482 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5483 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5484 << ", " << PHINodesToUpdate[i].second << ")\n";);
5486 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5487 // PHI nodes in successors.
5488 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5489 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5490 MachineInstr *PHI = PHINodesToUpdate[i].first;
5491 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5492 "This is not a machine PHI node that we are updating!");
5493 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5495 PHI->addOperand(MachineOperand::CreateMBB(BB));
5500 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5501 // Lower header first, if it wasn't already lowered
5502 if (!BitTestCases[i].Emitted) {
5503 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5504 getAnalysisToUpdate<MachineModuleInfo>(),
5507 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5508 // Set the current basic block to the mbb we wish to insert the code into
5509 BB = BitTestCases[i].Parent;
5510 HSDL.setCurrentBasicBlock(BB);
5512 HSDL.visitBitTestHeader(BitTestCases[i]);
5513 HSDAG.setRoot(HSDL.getRoot());
5514 CodeGenAndEmitDAG(HSDAG);
5517 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5518 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5519 getAnalysisToUpdate<MachineModuleInfo>(),
5522 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5523 // Set the current basic block to the mbb we wish to insert the code into
5524 BB = BitTestCases[i].Cases[j].ThisBB;
5525 BSDL.setCurrentBasicBlock(BB);
5528 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5529 BitTestCases[i].Reg,
5530 BitTestCases[i].Cases[j]);
5532 BSDL.visitBitTestCase(BitTestCases[i].Default,
5533 BitTestCases[i].Reg,
5534 BitTestCases[i].Cases[j]);
5537 BSDAG.setRoot(BSDL.getRoot());
5538 CodeGenAndEmitDAG(BSDAG);
5542 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5543 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5544 MachineBasicBlock *PHIBB = PHI->getParent();
5545 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5546 "This is not a machine PHI node that we are updating!");
5547 // This is "default" BB. We have two jumps to it. From "header" BB and
5548 // from last "case" BB.
5549 if (PHIBB == BitTestCases[i].Default) {
5550 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5552 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5553 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5555 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5558 // One of "cases" BB.
5559 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5560 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5561 if (cBB->succ_end() !=
5562 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5563 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5565 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5571 // If the JumpTable record is filled in, then we need to emit a jump table.
5572 // Updating the PHI nodes is tricky in this case, since we need to determine
5573 // whether the PHI is a successor of the range check MBB or the jump table MBB
5574 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5575 // Lower header first, if it wasn't already lowered
5576 if (!JTCases[i].first.Emitted) {
5577 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5578 getAnalysisToUpdate<MachineModuleInfo>(),
5581 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5582 // Set the current basic block to the mbb we wish to insert the code into
5583 BB = JTCases[i].first.HeaderBB;
5584 HSDL.setCurrentBasicBlock(BB);
5586 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5587 HSDAG.setRoot(HSDL.getRoot());
5588 CodeGenAndEmitDAG(HSDAG);
5591 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5592 getAnalysisToUpdate<MachineModuleInfo>(),
5595 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5596 // Set the current basic block to the mbb we wish to insert the code into
5597 BB = JTCases[i].second.MBB;
5598 JSDL.setCurrentBasicBlock(BB);
5600 JSDL.visitJumpTable(JTCases[i].second);
5601 JSDAG.setRoot(JSDL.getRoot());
5602 CodeGenAndEmitDAG(JSDAG);
5605 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5606 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5607 MachineBasicBlock *PHIBB = PHI->getParent();
5608 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5609 "This is not a machine PHI node that we are updating!");
5610 // "default" BB. We can go there only from header BB.
5611 if (PHIBB == JTCases[i].second.Default) {
5612 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5614 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5616 // JT BB. Just iterate over successors here
5617 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5618 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5620 PHI->addOperand(MachineOperand::CreateMBB(BB));
5625 // If the switch block involved a branch to one of the actual successors, we
5626 // need to update PHI nodes in that block.
5627 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5628 MachineInstr *PHI = PHINodesToUpdate[i].first;
5629 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5630 "This is not a machine PHI node that we are updating!");
5631 if (BB->isSuccessor(PHI->getParent())) {
5632 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5634 PHI->addOperand(MachineOperand::CreateMBB(BB));
5638 // If we generated any switch lowering information, build and codegen any
5639 // additional DAGs necessary.
5640 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5641 SelectionDAG SDAG(TLI, MF, FuncInfo,
5642 getAnalysisToUpdate<MachineModuleInfo>(),
5645 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5647 // Set the current basic block to the mbb we wish to insert the code into
5648 BB = SwitchCases[i].ThisBB;
5649 SDL.setCurrentBasicBlock(BB);
5652 SDL.visitSwitchCase(SwitchCases[i]);
5653 SDAG.setRoot(SDL.getRoot());
5654 CodeGenAndEmitDAG(SDAG);
5656 // Handle any PHI nodes in successors of this chunk, as if we were coming
5657 // from the original BB before switch expansion. Note that PHI nodes can
5658 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5659 // handle them the right number of times.
5660 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5661 for (MachineBasicBlock::iterator Phi = BB->begin();
5662 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5663 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5664 for (unsigned pn = 0; ; ++pn) {
5665 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5666 if (PHINodesToUpdate[pn].first == Phi) {
5667 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5669 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5675 // Don't process RHS if same block as LHS.
5676 if (BB == SwitchCases[i].FalseBB)
5677 SwitchCases[i].FalseBB = 0;
5679 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5680 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5681 SwitchCases[i].FalseBB = 0;
5683 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5688 /// Schedule - Pick a safe ordering for instructions for each
5689 /// target node in the graph.
5691 ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
5692 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5696 RegisterScheduler::setDefault(Ctor);
5699 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
5706 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5707 return new HazardRecognizer();
5710 //===----------------------------------------------------------------------===//
5711 // Helper functions used by the generated instruction selector.
5712 //===----------------------------------------------------------------------===//
5713 // Calls to these methods are generated by tblgen.
5715 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5716 /// the dag combiner simplified the 255, we still want to match. RHS is the
5717 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5718 /// specified in the .td file (e.g. 255).
5719 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
5720 int64_t DesiredMaskS) const {
5721 const APInt &ActualMask = RHS->getAPIntValue();
5722 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5724 // If the actual mask exactly matches, success!
5725 if (ActualMask == DesiredMask)
5728 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5729 if (ActualMask.intersects(~DesiredMask))
5732 // Otherwise, the DAG Combiner may have proven that the value coming in is
5733 // either already zero or is not demanded. Check for known zero input bits.
5734 APInt NeededMask = DesiredMask & ~ActualMask;
5735 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5738 // TODO: check to see if missing bits are just not demanded.
5740 // Otherwise, this pattern doesn't match.
5744 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5745 /// the dag combiner simplified the 255, we still want to match. RHS is the
5746 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5747 /// specified in the .td file (e.g. 255).
5748 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
5749 int64_t DesiredMaskS) const {
5750 const APInt &ActualMask = RHS->getAPIntValue();
5751 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5753 // If the actual mask exactly matches, success!
5754 if (ActualMask == DesiredMask)
5757 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5758 if (ActualMask.intersects(~DesiredMask))
5761 // Otherwise, the DAG Combiner may have proven that the value coming in is
5762 // either already zero or is not demanded. Check for known zero input bits.
5763 APInt NeededMask = DesiredMask & ~ActualMask;
5765 APInt KnownZero, KnownOne;
5766 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5768 // If all the missing bits in the or are already known to be set, match!
5769 if ((NeededMask & KnownOne) == NeededMask)
5772 // TODO: check to see if missing bits are just not demanded.
5774 // Otherwise, this pattern doesn't match.
5779 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5780 /// by tblgen. Others should not call it.
5781 void SelectionDAGISel::
5782 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) {
5783 std::vector<SDValue> InOps;
5784 std::swap(InOps, Ops);
5786 Ops.push_back(InOps[0]); // input chain.
5787 Ops.push_back(InOps[1]); // input asm string.
5789 unsigned i = 2, e = InOps.size();
5790 if (InOps[e-1].getValueType() == MVT::Flag)
5791 --e; // Don't process a flag operand if it is here.
5794 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5795 if ((Flags & 7) != 4 /*MEM*/) {
5796 // Just skip over this operand, copying the operands verbatim.
5797 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5798 i += (Flags >> 3) + 1;
5800 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5801 // Otherwise, this is a memory operand. Ask the target to select it.
5802 std::vector<SDValue> SelOps;
5803 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5804 cerr << "Could not match memory address. Inline asm failure!\n";
5808 // Add this to the output node.
5809 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5810 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5812 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5817 // Add the flag input back if present.
5818 if (e != InOps.size())
5819 Ops.push_back(InOps.back());
5822 char SelectionDAGISel::ID = 0;