1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the post legalize types"
84 " dag combine pass"));
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewDAGCombineLT = false,
99 ViewISelDAGs = false, ViewSchedDAGs = false,
100 ViewSUnitDAGs = false;
103 //===---------------------------------------------------------------------===//
105 /// RegisterScheduler class - Track the registration of instruction schedulers.
107 //===---------------------------------------------------------------------===//
108 MachinePassRegistry RegisterScheduler::Registry;
110 //===---------------------------------------------------------------------===//
112 /// ISHeuristic command line option for instruction schedulers.
114 //===---------------------------------------------------------------------===//
115 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
116 RegisterPassParser<RegisterScheduler> >
117 ISHeuristic("pre-RA-sched",
118 cl::init(&createDefaultScheduler),
119 cl::desc("Instruction schedulers available (before register"
122 static RegisterScheduler
123 defaultListDAGScheduler("default", "Best scheduler for the target",
124 createDefaultScheduler);
127 //===--------------------------------------------------------------------===//
128 /// createDefaultScheduler - This creates an instruction scheduler appropriate
130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
131 CodeGenOpt::Level OptLevel) {
132 const TargetLowering &TLI = IS->getTargetLowering();
134 if (OptLevel == CodeGenOpt::None)
135 return createFastDAGScheduler(IS, OptLevel);
136 if (TLI.getSchedulingPreference() == Sched::Latency)
137 return createTDListDAGScheduler(IS, OptLevel);
138 if (TLI.getSchedulingPreference() == Sched::RegPressure)
139 return createBURRListDAGScheduler(IS, OptLevel);
140 assert(TLI.getSchedulingPreference() == Sched::Hybrid &&
141 "Unknown sched type!");
142 return createHybridListDAGScheduler(IS, OptLevel);
146 // EmitInstrWithCustomInserter - This method should be implemented by targets
147 // that mark instructions with the 'usesCustomInserter' flag. These
148 // instructions are special in various ways, which require special support to
149 // insert. The specified MachineInstr is created but not inserted into any
150 // basic blocks, and this method is called to expand it into a sequence of
151 // instructions, potentially also creating new basic blocks and control flow.
152 // When new basic blocks are inserted and the edges from MBB to its successors
153 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
156 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
157 MachineBasicBlock *MBB) const {
159 dbgs() << "If a target marks an instruction with "
160 "'usesCustomInserter', it must implement "
161 "TargetLowering::EmitInstrWithCustomInserter!";
167 //===----------------------------------------------------------------------===//
168 // SelectionDAGISel code
169 //===----------------------------------------------------------------------===//
171 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
173 FuncInfo(new FunctionLoweringInfo(TLI)),
174 CurDAG(new SelectionDAG(tm, *FuncInfo)),
175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
181 SelectionDAGISel::~SelectionDAGISel() {
187 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
188 AU.addRequired<AliasAnalysis>();
189 AU.addPreserved<AliasAnalysis>();
190 AU.addRequired<GCModuleInfo>();
191 AU.addPreserved<GCModuleInfo>();
192 MachineFunctionPass::getAnalysisUsage(AU);
195 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
196 /// sigsetjmp. This is used to limit code-gen optimizations on the machine
198 static bool FunctionCallsSetJmp(const Function *F) {
199 const Module *M = F->getParent();
200 const Function *SetJmp = M->getFunction("setjmp");
201 const Function *SigSetJmp = M->getFunction("sigsetjmp");
203 if (!SetJmp && !SigSetJmp)
206 if (SetJmp && !SetJmp->use_empty())
207 for (Value::const_use_iterator
208 I = SetJmp->use_begin(), E = SetJmp->use_end(); I != E; ++I)
209 if (const CallInst *CI = dyn_cast<CallInst>(I))
210 if (CI->getParent()->getParent() == F)
213 if (SigSetJmp && !SigSetJmp->use_empty())
214 for (Value::const_use_iterator
215 I = SigSetJmp->use_begin(), E = SigSetJmp->use_end(); I != E; ++I)
216 if (const CallInst *CI = dyn_cast<CallInst>(I))
217 if (CI->getParent()->getParent() == F)
223 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
224 // Do some sanity-checking on the command-line options.
225 assert((!EnableFastISelVerbose || EnableFastISel) &&
226 "-fast-isel-verbose requires -fast-isel");
227 assert((!EnableFastISelAbort || EnableFastISel) &&
228 "-fast-isel-abort requires -fast-isel");
230 const Function &Fn = *mf.getFunction();
231 const TargetInstrInfo &TII = *TM.getInstrInfo();
232 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
235 RegInfo = &MF->getRegInfo();
236 AA = &getAnalysis<AliasAnalysis>();
237 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
239 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
242 FuncInfo->set(Fn, *MF, EnableFastISel);
245 SelectAllBasicBlocks(Fn);
247 // If the first basic block in the function has live ins that need to be
248 // copied into vregs, emit the copies into the top of the block before
249 // emitting the code for the block.
250 MachineBasicBlock *EntryMBB = MF->begin();
251 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
253 DenseMap<unsigned, unsigned> LiveInMap;
254 if (!FuncInfo->ArgDbgValues.empty())
255 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
256 E = RegInfo->livein_end(); LI != E; ++LI)
258 LiveInMap.insert(std::make_pair(LI->first, LI->second));
260 // Insert DBG_VALUE instructions for function arguments to the entry block.
261 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
262 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
263 unsigned Reg = MI->getOperand(0).getReg();
264 if (TargetRegisterInfo::isPhysicalRegister(Reg))
265 EntryMBB->insert(EntryMBB->begin(), MI);
267 MachineInstr *Def = RegInfo->getVRegDef(Reg);
268 MachineBasicBlock::iterator InsertPos = Def;
269 // FIXME: VR def may not be in entry block.
270 Def->getParent()->insert(llvm::next(InsertPos), MI);
273 // If Reg is live-in then update debug info to track its copy in a vreg.
274 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
275 if (LDI != LiveInMap.end()) {
276 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
277 MachineBasicBlock::iterator InsertPos = Def;
278 const MDNode *Variable =
279 MI->getOperand(MI->getNumOperands()-1).getMetadata();
280 unsigned Offset = MI->getOperand(1).getImm();
281 // Def is never a terminator here, so it is ok to increment InsertPos.
282 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
283 TII.get(TargetOpcode::DBG_VALUE))
284 .addReg(LDI->second, RegState::Debug)
285 .addImm(Offset).addMetadata(Variable);
289 // Determine if there are any calls in this machine function.
290 MachineFrameInfo *MFI = MF->getFrameInfo();
291 if (!MFI->hasCalls()) {
292 for (MachineFunction::const_iterator
293 I = MF->begin(), E = MF->end(); I != E; ++I) {
294 const MachineBasicBlock *MBB = I;
295 for (MachineBasicBlock::const_iterator
296 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
297 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
298 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) {
299 MFI->setHasCalls(true);
307 // Determine if there is a call to setjmp in the machine function.
308 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
310 // Release function-specific state. SDB and CurDAG are already cleared
318 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
319 const BasicBlock *LLVMBB,
320 BasicBlock::const_iterator Begin,
321 BasicBlock::const_iterator End,
323 // Lower all of the non-terminator instructions. If a call is emitted
324 // as a tail call, cease emitting nodes for this block. Terminators
325 // are handled below.
326 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
329 // Make sure the root of the DAG is up-to-date.
330 CurDAG->setRoot(SDB->getControlRoot());
331 HadTailCall = SDB->HasTailCall;
334 // Final step, emit the lowered DAG as machine code.
335 return CodeGenAndEmitDAG(BB);
339 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
340 /// nodes from the worklist.
341 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
342 SmallVector<SDNode*, 128> &Worklist;
343 SmallPtrSet<SDNode*, 128> &InWorklist;
345 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
346 SmallPtrSet<SDNode*, 128> &inwl)
347 : Worklist(wl), InWorklist(inwl) {}
349 void RemoveFromWorklist(SDNode *N) {
350 if (!InWorklist.erase(N)) return;
352 SmallVector<SDNode*, 128>::iterator I =
353 std::find(Worklist.begin(), Worklist.end(), N);
354 assert(I != Worklist.end() && "Not in worklist");
356 *I = Worklist.back();
360 virtual void NodeDeleted(SDNode *N, SDNode *E) {
361 RemoveFromWorklist(N);
364 virtual void NodeUpdated(SDNode *N) {
370 /// TrivialTruncElim - Eliminate some trivial nops that can result from
371 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
372 static bool TrivialTruncElim(SDValue Op,
373 TargetLowering::TargetLoweringOpt &TLO) {
374 SDValue N0 = Op.getOperand(0);
375 EVT VT = Op.getValueType();
376 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
377 N0.getOpcode() == ISD::SIGN_EXTEND ||
378 N0.getOpcode() == ISD::ANY_EXTEND) &&
379 N0.getOperand(0).getValueType() == VT) {
380 return TLO.CombineTo(Op, N0.getOperand(0));
385 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
386 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
387 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
388 void SelectionDAGISel::ShrinkDemandedOps() {
389 SmallVector<SDNode*, 128> Worklist;
390 SmallPtrSet<SDNode*, 128> InWorklist;
392 // Add all the dag nodes to the worklist.
393 Worklist.reserve(CurDAG->allnodes_size());
394 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
395 E = CurDAG->allnodes_end(); I != E; ++I) {
396 Worklist.push_back(I);
397 InWorklist.insert(I);
400 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true);
401 while (!Worklist.empty()) {
402 SDNode *N = Worklist.pop_back_val();
405 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
406 // Deleting this node may make its operands dead, add them to the worklist
407 // if they aren't already there.
408 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
409 if (InWorklist.insert(N->getOperand(i).getNode()))
410 Worklist.push_back(N->getOperand(i).getNode());
412 CurDAG->DeleteNode(N);
416 // Run ShrinkDemandedOp on scalar binary operations.
417 if (N->getNumValues() != 1 ||
418 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
421 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
422 APInt Demanded = APInt::getAllOnesValue(BitWidth);
423 APInt KnownZero, KnownOne;
424 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
425 KnownZero, KnownOne, TLO) &&
426 (N->getOpcode() != ISD::TRUNCATE ||
427 !TrivialTruncElim(SDValue(N, 0), TLO)))
431 assert(!InWorklist.count(N) && "Already in worklist");
432 Worklist.push_back(N);
433 InWorklist.insert(N);
435 // Replace the old value with the new one.
436 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
437 TLO.Old.getNode()->dump(CurDAG);
438 errs() << "\nWith: ";
439 TLO.New.getNode()->dump(CurDAG);
442 if (InWorklist.insert(TLO.New.getNode()))
443 Worklist.push_back(TLO.New.getNode());
445 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
446 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
448 if (!TLO.Old.getNode()->use_empty()) continue;
450 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
452 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
453 if (OpNode->hasOneUse()) {
454 // Add OpNode to the end of the list to revisit.
455 DeadNodes.RemoveFromWorklist(OpNode);
456 Worklist.push_back(OpNode);
457 InWorklist.insert(OpNode);
461 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
462 CurDAG->DeleteNode(TLO.Old.getNode());
466 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
467 SmallPtrSet<SDNode*, 128> VisitedNodes;
468 SmallVector<SDNode*, 128> Worklist;
470 Worklist.push_back(CurDAG->getRoot().getNode());
477 SDNode *N = Worklist.pop_back_val();
479 // If we've already seen this node, ignore it.
480 if (!VisitedNodes.insert(N))
483 // Otherwise, add all chain operands to the worklist.
484 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
485 if (N->getOperand(i).getValueType() == MVT::Other)
486 Worklist.push_back(N->getOperand(i).getNode());
488 // If this is a CopyToReg with a vreg dest, process it.
489 if (N->getOpcode() != ISD::CopyToReg)
492 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
493 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
496 // Ignore non-scalar or non-integer values.
497 SDValue Src = N->getOperand(2);
498 EVT SrcVT = Src.getValueType();
499 if (!SrcVT.isInteger() || SrcVT.isVector())
502 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
503 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
504 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
506 // Only install this information if it tells us something.
507 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
508 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
509 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
510 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
511 FunctionLoweringInfo::LiveOutInfo &LOI =
512 FuncInfo->LiveOutRegInfo[DestReg];
513 LOI.NumSignBits = NumSignBits;
514 LOI.KnownOne = KnownOne;
515 LOI.KnownZero = KnownZero;
517 } while (!Worklist.empty());
520 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
521 std::string GroupName;
522 if (TimePassesIsEnabled)
523 GroupName = "Instruction Selection and Scheduling";
524 std::string BlockName;
525 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
526 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
528 BlockName = MF->getFunction()->getNameStr() + ":" +
529 BB->getBasicBlock()->getNameStr();
531 DEBUG(dbgs() << "Initial selection DAG:\n");
532 DEBUG(CurDAG->dump());
534 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
536 // Run the DAG combiner in pre-legalize mode.
537 if (TimePassesIsEnabled) {
538 NamedRegionTimer T("DAG Combining 1", GroupName);
539 CurDAG->Combine(Unrestricted, *AA, OptLevel);
541 CurDAG->Combine(Unrestricted, *AA, OptLevel);
544 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
545 DEBUG(CurDAG->dump());
547 // Second step, hack on the DAG until it only uses operations and types that
548 // the target supports.
549 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
553 if (TimePassesIsEnabled) {
554 NamedRegionTimer T("Type Legalization", GroupName);
555 Changed = CurDAG->LegalizeTypes();
557 Changed = CurDAG->LegalizeTypes();
560 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
561 DEBUG(CurDAG->dump());
564 if (ViewDAGCombineLT)
565 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
567 // Run the DAG combiner in post-type-legalize mode.
568 if (TimePassesIsEnabled) {
569 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
570 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
572 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
575 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
576 DEBUG(CurDAG->dump());
579 if (TimePassesIsEnabled) {
580 NamedRegionTimer T("Vector Legalization", GroupName);
581 Changed = CurDAG->LegalizeVectors();
583 Changed = CurDAG->LegalizeVectors();
587 if (TimePassesIsEnabled) {
588 NamedRegionTimer T("Type Legalization 2", GroupName);
589 CurDAG->LegalizeTypes();
591 CurDAG->LegalizeTypes();
594 if (ViewDAGCombineLT)
595 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
597 // Run the DAG combiner in post-type-legalize mode.
598 if (TimePassesIsEnabled) {
599 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
600 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
602 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
605 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
606 DEBUG(CurDAG->dump());
609 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
611 if (TimePassesIsEnabled) {
612 NamedRegionTimer T("DAG Legalization", GroupName);
613 CurDAG->Legalize(OptLevel);
615 CurDAG->Legalize(OptLevel);
618 DEBUG(dbgs() << "Legalized selection DAG:\n");
619 DEBUG(CurDAG->dump());
621 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
623 // Run the DAG combiner in post-legalize mode.
624 if (TimePassesIsEnabled) {
625 NamedRegionTimer T("DAG Combining 2", GroupName);
626 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
628 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
631 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
632 DEBUG(CurDAG->dump());
634 if (OptLevel != CodeGenOpt::None) {
636 ComputeLiveOutVRegInfo();
639 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
641 // Third, instruction select all of the operations to machine code, adding the
642 // code to the MachineBasicBlock.
643 if (TimePassesIsEnabled) {
644 NamedRegionTimer T("Instruction Selection", GroupName);
645 DoInstructionSelection();
647 DoInstructionSelection();
650 DEBUG(dbgs() << "Selected selection DAG:\n");
651 DEBUG(CurDAG->dump());
653 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
655 // Schedule machine code.
656 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
657 if (TimePassesIsEnabled) {
658 NamedRegionTimer T("Instruction Scheduling", GroupName);
659 Scheduler->Run(CurDAG, BB, BB->end());
661 Scheduler->Run(CurDAG, BB, BB->end());
664 if (ViewSUnitDAGs) Scheduler->viewGraph();
666 // Emit machine code to BB. This can change 'BB' to the last block being
668 if (TimePassesIsEnabled) {
669 NamedRegionTimer T("Instruction Creation", GroupName);
670 BB = Scheduler->EmitSchedule();
672 BB = Scheduler->EmitSchedule();
675 // Free the scheduler state.
676 if (TimePassesIsEnabled) {
677 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
683 // Free the SelectionDAG state, now that we're finished with it.
689 void SelectionDAGISel::DoInstructionSelection() {
690 DEBUG(errs() << "===== Instruction selection begins:\n");
694 // Select target instructions for the DAG.
696 // Number all nodes with a topological order and set DAGSize.
697 DAGSize = CurDAG->AssignTopologicalOrder();
699 // Create a dummy node (which is not added to allnodes), that adds
700 // a reference to the root node, preventing it from being deleted,
701 // and tracking any changes of the root.
702 HandleSDNode Dummy(CurDAG->getRoot());
703 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
706 // The AllNodes list is now topological-sorted. Visit the
707 // nodes by starting at the end of the list (the root of the
708 // graph) and preceding back toward the beginning (the entry
710 while (ISelPosition != CurDAG->allnodes_begin()) {
711 SDNode *Node = --ISelPosition;
712 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
713 // but there are currently some corner cases that it misses. Also, this
714 // makes it theoretically possible to disable the DAGCombiner.
715 if (Node->use_empty())
718 SDNode *ResNode = Select(Node);
720 // FIXME: This is pretty gross. 'Select' should be changed to not return
721 // anything at all and this code should be nuked with a tactical strike.
723 // If node should not be replaced, continue with the next one.
724 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
728 ReplaceUses(Node, ResNode);
730 // If after the replacement this node is not used any more,
731 // remove this dead node.
732 if (Node->use_empty()) { // Don't delete EntryToken, etc.
733 ISelUpdater ISU(ISelPosition);
734 CurDAG->RemoveDeadNode(Node, &ISU);
738 CurDAG->setRoot(Dummy.getValue());
741 DEBUG(errs() << "===== Instruction selection ends:\n");
743 PostprocessISelDAG();
746 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
747 /// do other setup for EH landing-pad blocks.
748 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
749 // Add a label to mark the beginning of the landing pad. Deletion of the
750 // landing pad can thus be detected via the MachineModuleInfo.
751 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
753 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
754 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
756 // Mark exception register as live in.
757 unsigned Reg = TLI.getExceptionAddressRegister();
758 if (Reg) BB->addLiveIn(Reg);
760 // Mark exception selector register as live in.
761 Reg = TLI.getExceptionSelectorRegister();
762 if (Reg) BB->addLiveIn(Reg);
764 // FIXME: Hack around an exception handling flaw (PR1508): the personality
765 // function and list of typeids logically belong to the invoke (or, if you
766 // like, the basic block containing the invoke), and need to be associated
767 // with it in the dwarf exception handling tables. Currently however the
768 // information is provided by an intrinsic (eh.selector) that can be moved
769 // to unexpected places by the optimizers: if the unwind edge is critical,
770 // then breaking it can result in the intrinsics being in the successor of
771 // the landing pad, not the landing pad itself. This results
772 // in exceptions not being caught because no typeids are associated with
773 // the invoke. This may not be the only way things can go wrong, but it
774 // is the only way we try to work around for the moment.
775 const BasicBlock *LLVMBB = BB->getBasicBlock();
776 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
778 if (Br && Br->isUnconditional()) { // Critical edge?
779 BasicBlock::const_iterator I, E;
780 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
781 if (isa<EHSelectorInst>(I))
785 // No catch info found - try to extract some from the successor.
786 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
790 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
791 // Initialize the Fast-ISel state, if needed.
792 FastISel *FastIS = 0;
794 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
795 FuncInfo->StaticAllocaMap,
796 FuncInfo->PHINodesToUpdate
798 , FuncInfo->CatchInfoLost
802 // Iterate over all basic blocks in the function.
803 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
804 const BasicBlock *LLVMBB = &*I;
805 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
807 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
808 BasicBlock::const_iterator const End = LLVMBB->end();
809 BasicBlock::const_iterator BI = Begin;
811 // Lower any arguments needed in this block if this is the entry block.
812 if (LLVMBB == &Fn.getEntryBlock())
813 LowerArguments(LLVMBB);
815 // Setup an EH landing-pad block.
816 if (BB->isLandingPad())
817 PrepareEHLandingPad(BB);
819 // Before doing SelectionDAG ISel, see if FastISel has been requested.
821 // Emit code for any incoming arguments. This must happen before
822 // beginning FastISel on the entry block.
823 if (LLVMBB == &Fn.getEntryBlock()) {
824 CurDAG->setRoot(SDB->getControlRoot());
826 BB = CodeGenAndEmitDAG(BB);
828 FastIS->startNewBlock(BB);
829 // Do FastISel on as many instructions as possible.
830 for (; BI != End; ++BI) {
831 // Try to select the instruction with FastISel.
832 if (FastIS->SelectInstruction(BI))
835 // Then handle certain instructions as single-LLVM-Instruction blocks.
836 if (isa<CallInst>(BI)) {
837 ++NumFastIselFailures;
838 if (EnableFastISelVerbose || EnableFastISelAbort) {
839 dbgs() << "FastISel missed call: ";
843 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
844 unsigned &R = FuncInfo->ValueMap[BI];
846 R = FuncInfo->CreateRegForValue(BI);
849 bool HadTailCall = false;
850 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall);
852 // If the call was emitted as a tail call, we're done with the block.
858 // If the instruction was codegen'd with multiple blocks,
859 // inform the FastISel object where to resume inserting.
860 FastIS->setCurrentBlock(BB);
864 // Otherwise, give up on FastISel for the rest of the block.
865 // For now, be a little lenient about non-branch terminators.
866 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
867 ++NumFastIselFailures;
868 if (EnableFastISelVerbose || EnableFastISelAbort) {
869 dbgs() << "FastISel miss: ";
872 if (EnableFastISelAbort)
873 // The "fast" selector couldn't handle something and bailed.
874 // For the purpose of debugging, just abort.
875 llvm_unreachable("FastISel didn't select the entire block");
881 // Run SelectionDAG instruction selection on the remainder of the block
882 // not handled by FastISel. If FastISel is not run, this is the entire
886 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall);
889 FinishBasicBlock(BB);
890 FuncInfo->PHINodesToUpdate.clear();
897 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
899 DEBUG(dbgs() << "Total amount of phi nodes to update: "
900 << FuncInfo->PHINodesToUpdate.size() << "\n");
901 DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
902 dbgs() << "Node " << i << " : ("
903 << FuncInfo->PHINodesToUpdate[i].first
904 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
906 // Next, now that we know what the last MBB the LLVM BB expanded is, update
907 // PHI nodes in successors.
908 if (SDB->SwitchCases.empty() &&
909 SDB->JTCases.empty() &&
910 SDB->BitTestCases.empty()) {
911 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
912 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
913 assert(PHI->isPHI() &&
914 "This is not a machine PHI node that we are updating!");
915 if (!BB->isSuccessor(PHI->getParent()))
918 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
919 PHI->addOperand(MachineOperand::CreateMBB(BB));
924 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
925 // Lower header first, if it wasn't already lowered
926 if (!SDB->BitTestCases[i].Emitted) {
927 // Set the current basic block to the mbb we wish to insert the code into
928 BB = SDB->BitTestCases[i].Parent;
930 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
931 CurDAG->setRoot(SDB->getRoot());
933 BB = CodeGenAndEmitDAG(BB);
936 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
937 // Set the current basic block to the mbb we wish to insert the code into
938 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
941 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
942 SDB->BitTestCases[i].Reg,
943 SDB->BitTestCases[i].Cases[j],
946 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
947 SDB->BitTestCases[i].Reg,
948 SDB->BitTestCases[i].Cases[j],
952 CurDAG->setRoot(SDB->getRoot());
954 BB = CodeGenAndEmitDAG(BB);
958 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
960 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
961 MachineBasicBlock *PHIBB = PHI->getParent();
962 assert(PHI->isPHI() &&
963 "This is not a machine PHI node that we are updating!");
964 // This is "default" BB. We have two jumps to it. From "header" BB and
965 // from last "case" BB.
966 if (PHIBB == SDB->BitTestCases[i].Default) {
967 PHI->addOperand(MachineOperand::
968 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
970 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
971 PHI->addOperand(MachineOperand::
972 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
974 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
977 // One of "cases" BB.
978 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
980 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
981 if (cBB->isSuccessor(PHIBB)) {
982 PHI->addOperand(MachineOperand::
983 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
985 PHI->addOperand(MachineOperand::CreateMBB(cBB));
990 SDB->BitTestCases.clear();
992 // If the JumpTable record is filled in, then we need to emit a jump table.
993 // Updating the PHI nodes is tricky in this case, since we need to determine
994 // whether the PHI is a successor of the range check MBB or the jump table MBB
995 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
996 // Lower header first, if it wasn't already lowered
997 if (!SDB->JTCases[i].first.Emitted) {
998 // Set the current basic block to the mbb we wish to insert the code into
999 BB = SDB->JTCases[i].first.HeaderBB;
1001 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1003 CurDAG->setRoot(SDB->getRoot());
1005 BB = CodeGenAndEmitDAG(BB);
1008 // Set the current basic block to the mbb we wish to insert the code into
1009 BB = SDB->JTCases[i].second.MBB;
1011 SDB->visitJumpTable(SDB->JTCases[i].second);
1012 CurDAG->setRoot(SDB->getRoot());
1014 BB = CodeGenAndEmitDAG(BB);
1017 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1019 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1020 MachineBasicBlock *PHIBB = PHI->getParent();
1021 assert(PHI->isPHI() &&
1022 "This is not a machine PHI node that we are updating!");
1023 // "default" BB. We can go there only from header BB.
1024 if (PHIBB == SDB->JTCases[i].second.Default) {
1026 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1029 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1031 // JT BB. Just iterate over successors here
1032 if (BB->isSuccessor(PHIBB)) {
1034 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1036 PHI->addOperand(MachineOperand::CreateMBB(BB));
1040 SDB->JTCases.clear();
1042 // If the switch block involved a branch to one of the actual successors, we
1043 // need to update PHI nodes in that block.
1044 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1045 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1046 assert(PHI->isPHI() &&
1047 "This is not a machine PHI node that we are updating!");
1048 if (BB->isSuccessor(PHI->getParent())) {
1050 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1051 PHI->addOperand(MachineOperand::CreateMBB(BB));
1055 // If we generated any switch lowering information, build and codegen any
1056 // additional DAGs necessary.
1057 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1058 // Set the current basic block to the mbb we wish to insert the code into
1059 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1061 // Determine the unique successors.
1062 SmallVector<MachineBasicBlock *, 2> Succs;
1063 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1064 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1065 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1067 // Emit the code. Note that this could result in ThisBB being split, so
1068 // we need to check for updates.
1069 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
1070 CurDAG->setRoot(SDB->getRoot());
1072 ThisBB = CodeGenAndEmitDAG(BB);
1074 // Handle any PHI nodes in successors of this chunk, as if we were coming
1075 // from the original BB before switch expansion. Note that PHI nodes can
1076 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1077 // handle them the right number of times.
1078 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1080 // BB may have been removed from the CFG if a branch was constant folded.
1081 if (ThisBB->isSuccessor(BB)) {
1082 for (MachineBasicBlock::iterator Phi = BB->begin();
1083 Phi != BB->end() && Phi->isPHI();
1085 // This value for this PHI node is recorded in PHINodesToUpdate.
1086 for (unsigned pn = 0; ; ++pn) {
1087 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1088 "Didn't find PHI entry!");
1089 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1090 Phi->addOperand(MachineOperand::
1091 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1093 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1101 SDB->SwitchCases.clear();
1105 /// Create the scheduler. If a specific scheduler was specified
1106 /// via the SchedulerRegistry, use it, otherwise select the
1107 /// one preferred by the target.
1109 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1110 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1114 RegisterScheduler::setDefault(Ctor);
1117 return Ctor(this, OptLevel);
1120 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1121 return new ScheduleHazardRecognizer();
1124 //===----------------------------------------------------------------------===//
1125 // Helper functions used by the generated instruction selector.
1126 //===----------------------------------------------------------------------===//
1127 // Calls to these methods are generated by tblgen.
1129 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1130 /// the dag combiner simplified the 255, we still want to match. RHS is the
1131 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1132 /// specified in the .td file (e.g. 255).
1133 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1134 int64_t DesiredMaskS) const {
1135 const APInt &ActualMask = RHS->getAPIntValue();
1136 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1138 // If the actual mask exactly matches, success!
1139 if (ActualMask == DesiredMask)
1142 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1143 if (ActualMask.intersects(~DesiredMask))
1146 // Otherwise, the DAG Combiner may have proven that the value coming in is
1147 // either already zero or is not demanded. Check for known zero input bits.
1148 APInt NeededMask = DesiredMask & ~ActualMask;
1149 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1152 // TODO: check to see if missing bits are just not demanded.
1154 // Otherwise, this pattern doesn't match.
1158 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1159 /// the dag combiner simplified the 255, we still want to match. RHS is the
1160 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1161 /// specified in the .td file (e.g. 255).
1162 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1163 int64_t DesiredMaskS) const {
1164 const APInt &ActualMask = RHS->getAPIntValue();
1165 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1167 // If the actual mask exactly matches, success!
1168 if (ActualMask == DesiredMask)
1171 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1172 if (ActualMask.intersects(~DesiredMask))
1175 // Otherwise, the DAG Combiner may have proven that the value coming in is
1176 // either already zero or is not demanded. Check for known zero input bits.
1177 APInt NeededMask = DesiredMask & ~ActualMask;
1179 APInt KnownZero, KnownOne;
1180 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1182 // If all the missing bits in the or are already known to be set, match!
1183 if ((NeededMask & KnownOne) == NeededMask)
1186 // TODO: check to see if missing bits are just not demanded.
1188 // Otherwise, this pattern doesn't match.
1193 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1194 /// by tblgen. Others should not call it.
1195 void SelectionDAGISel::
1196 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1197 std::vector<SDValue> InOps;
1198 std::swap(InOps, Ops);
1200 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1201 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1202 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1204 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1205 if (InOps[e-1].getValueType() == MVT::Flag)
1206 --e; // Don't process a flag operand if it is here.
1209 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1210 if (!InlineAsm::isMemKind(Flags)) {
1211 // Just skip over this operand, copying the operands verbatim.
1212 Ops.insert(Ops.end(), InOps.begin()+i,
1213 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1214 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1216 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1217 "Memory operand with multiple values?");
1218 // Otherwise, this is a memory operand. Ask the target to select it.
1219 std::vector<SDValue> SelOps;
1220 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1221 report_fatal_error("Could not match memory address. Inline asm"
1224 // Add this to the output node.
1226 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1227 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1228 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1233 // Add the flag input back if present.
1234 if (e != InOps.size())
1235 Ops.push_back(InOps.back());
1238 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1241 static SDNode *findFlagUse(SDNode *N) {
1242 unsigned FlagResNo = N->getNumValues()-1;
1243 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1244 SDUse &Use = I.getUse();
1245 if (Use.getResNo() == FlagResNo)
1246 return Use.getUser();
1251 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1252 /// This function recursively traverses up the operand chain, ignoring
1254 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1255 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1256 bool IgnoreChains) {
1257 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1258 // greater than all of its (recursive) operands. If we scan to a point where
1259 // 'use' is smaller than the node we're scanning for, then we know we will
1262 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1263 // happen because we scan down to newly selected nodes in the case of flag
1265 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1268 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1269 // won't fail if we scan it again.
1270 if (!Visited.insert(Use))
1273 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1274 // Ignore chain uses, they are validated by HandleMergeInputChains.
1275 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1278 SDNode *N = Use->getOperand(i).getNode();
1280 if (Use == ImmedUse || Use == Root)
1281 continue; // We are not looking for immediate use.
1286 // Traverse up the operand chain.
1287 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1293 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1294 /// operand node N of U during instruction selection that starts at Root.
1295 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1296 SDNode *Root) const {
1297 if (OptLevel == CodeGenOpt::None) return false;
1298 return N.hasOneUse();
1301 /// IsLegalToFold - Returns true if the specific operand node N of
1302 /// U can be folded during instruction selection that starts at Root.
1303 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1304 CodeGenOpt::Level OptLevel,
1305 bool IgnoreChains) {
1306 if (OptLevel == CodeGenOpt::None) return false;
1308 // If Root use can somehow reach N through a path that that doesn't contain
1309 // U then folding N would create a cycle. e.g. In the following
1310 // diagram, Root can reach N through X. If N is folded into into Root, then
1311 // X is both a predecessor and a successor of U.
1322 // * indicates nodes to be folded together.
1324 // If Root produces a flag, then it gets (even more) interesting. Since it
1325 // will be "glued" together with its flag use in the scheduler, we need to
1326 // check if it might reach N.
1345 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1346 // (call it Fold), then X is a predecessor of FU and a successor of
1347 // Fold. But since Fold and FU are flagged together, this will create
1348 // a cycle in the scheduling graph.
1350 // If the node has flags, walk down the graph to the "lowest" node in the
1352 EVT VT = Root->getValueType(Root->getNumValues()-1);
1353 while (VT == MVT::Flag) {
1354 SDNode *FU = findFlagUse(Root);
1358 VT = Root->getValueType(Root->getNumValues()-1);
1360 // If our query node has a flag result with a use, we've walked up it. If
1361 // the user (which has already been selected) has a chain or indirectly uses
1362 // the chain, our WalkChainUsers predicate will not consider it. Because of
1363 // this, we cannot ignore chains in this predicate.
1364 IgnoreChains = false;
1368 SmallPtrSet<SDNode*, 16> Visited;
1369 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1372 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1373 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1374 SelectInlineAsmMemoryOperands(Ops);
1376 std::vector<EVT> VTs;
1377 VTs.push_back(MVT::Other);
1378 VTs.push_back(MVT::Flag);
1379 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1380 VTs, &Ops[0], Ops.size());
1382 return New.getNode();
1385 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1386 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1389 /// GetVBR - decode a vbr encoding whose top bit is set.
1390 ALWAYS_INLINE static uint64_t
1391 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1392 assert(Val >= 128 && "Not a VBR");
1393 Val &= 127; // Remove first vbr bit.
1398 NextBits = MatcherTable[Idx++];
1399 Val |= (NextBits&127) << Shift;
1401 } while (NextBits & 128);
1407 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1408 /// interior flag and chain results to use the new flag and chain results.
1409 void SelectionDAGISel::
1410 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1411 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1413 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1414 bool isMorphNodeTo) {
1415 SmallVector<SDNode*, 4> NowDeadNodes;
1417 ISelUpdater ISU(ISelPosition);
1419 // Now that all the normal results are replaced, we replace the chain and
1420 // flag results if present.
1421 if (!ChainNodesMatched.empty()) {
1422 assert(InputChain.getNode() != 0 &&
1423 "Matched input chains but didn't produce a chain");
1424 // Loop over all of the nodes we matched that produced a chain result.
1425 // Replace all the chain results with the final chain we ended up with.
1426 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1427 SDNode *ChainNode = ChainNodesMatched[i];
1429 // If this node was already deleted, don't look at it.
1430 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1433 // Don't replace the results of the root node if we're doing a
1435 if (ChainNode == NodeToMatch && isMorphNodeTo)
1438 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1439 if (ChainVal.getValueType() == MVT::Flag)
1440 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1441 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1442 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1444 // If the node became dead and we haven't already seen it, delete it.
1445 if (ChainNode->use_empty() &&
1446 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1447 NowDeadNodes.push_back(ChainNode);
1451 // If the result produces a flag, update any flag results in the matched
1452 // pattern with the flag result.
1453 if (InputFlag.getNode() != 0) {
1454 // Handle any interior nodes explicitly marked.
1455 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1456 SDNode *FRN = FlagResultNodesMatched[i];
1458 // If this node was already deleted, don't look at it.
1459 if (FRN->getOpcode() == ISD::DELETED_NODE)
1462 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1463 "Doesn't have a flag result");
1464 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1467 // If the node became dead and we haven't already seen it, delete it.
1468 if (FRN->use_empty() &&
1469 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1470 NowDeadNodes.push_back(FRN);
1474 if (!NowDeadNodes.empty())
1475 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1477 DEBUG(errs() << "ISEL: Match complete!\n");
1483 CR_LeadsToInteriorNode
1486 /// WalkChainUsers - Walk down the users of the specified chained node that is
1487 /// part of the pattern we're matching, looking at all of the users we find.
1488 /// This determines whether something is an interior node, whether we have a
1489 /// non-pattern node in between two pattern nodes (which prevent folding because
1490 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1491 /// between pattern nodes (in which case the TF becomes part of the pattern).
1493 /// The walk we do here is guaranteed to be small because we quickly get down to
1494 /// already selected nodes "below" us.
1496 WalkChainUsers(SDNode *ChainedNode,
1497 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1498 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1499 ChainResult Result = CR_Simple;
1501 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1502 E = ChainedNode->use_end(); UI != E; ++UI) {
1503 // Make sure the use is of the chain, not some other value we produce.
1504 if (UI.getUse().getValueType() != MVT::Other) continue;
1508 // If we see an already-selected machine node, then we've gone beyond the
1509 // pattern that we're selecting down into the already selected chunk of the
1511 if (User->isMachineOpcode() ||
1512 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1515 if (User->getOpcode() == ISD::CopyToReg ||
1516 User->getOpcode() == ISD::CopyFromReg ||
1517 User->getOpcode() == ISD::INLINEASM ||
1518 User->getOpcode() == ISD::EH_LABEL) {
1519 // If their node ID got reset to -1 then they've already been selected.
1520 // Treat them like a MachineOpcode.
1521 if (User->getNodeId() == -1)
1525 // If we have a TokenFactor, we handle it specially.
1526 if (User->getOpcode() != ISD::TokenFactor) {
1527 // If the node isn't a token factor and isn't part of our pattern, then it
1528 // must be a random chained node in between two nodes we're selecting.
1529 // This happens when we have something like:
1534 // Because we structurally match the load/store as a read/modify/write,
1535 // but the call is chained between them. We cannot fold in this case
1536 // because it would induce a cycle in the graph.
1537 if (!std::count(ChainedNodesInPattern.begin(),
1538 ChainedNodesInPattern.end(), User))
1539 return CR_InducesCycle;
1541 // Otherwise we found a node that is part of our pattern. For example in:
1545 // This would happen when we're scanning down from the load and see the
1546 // store as a user. Record that there is a use of ChainedNode that is
1547 // part of the pattern and keep scanning uses.
1548 Result = CR_LeadsToInteriorNode;
1549 InteriorChainedNodes.push_back(User);
1553 // If we found a TokenFactor, there are two cases to consider: first if the
1554 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1555 // uses of the TF are in our pattern) we just want to ignore it. Second,
1556 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1562 // | \ DAG's like cheese
1565 // [TokenFactor] [Op]
1572 // In this case, the TokenFactor becomes part of our match and we rewrite it
1573 // as a new TokenFactor.
1575 // To distinguish these two cases, do a recursive walk down the uses.
1576 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1578 // If the uses of the TokenFactor are just already-selected nodes, ignore
1579 // it, it is "below" our pattern.
1581 case CR_InducesCycle:
1582 // If the uses of the TokenFactor lead to nodes that are not part of our
1583 // pattern that are not selected, folding would turn this into a cycle,
1585 return CR_InducesCycle;
1586 case CR_LeadsToInteriorNode:
1587 break; // Otherwise, keep processing.
1590 // Okay, we know we're in the interesting interior case. The TokenFactor
1591 // is now going to be considered part of the pattern so that we rewrite its
1592 // uses (it may have uses that are not part of the pattern) with the
1593 // ultimate chain result of the generated code. We will also add its chain
1594 // inputs as inputs to the ultimate TokenFactor we create.
1595 Result = CR_LeadsToInteriorNode;
1596 ChainedNodesInPattern.push_back(User);
1597 InteriorChainedNodes.push_back(User);
1604 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1605 /// operation for when the pattern matched at least one node with a chains. The
1606 /// input vector contains a list of all of the chained nodes that we match. We
1607 /// must determine if this is a valid thing to cover (i.e. matching it won't
1608 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1609 /// be used as the input node chain for the generated nodes.
1611 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1612 SelectionDAG *CurDAG) {
1613 // Walk all of the chained nodes we've matched, recursively scanning down the
1614 // users of the chain result. This adds any TokenFactor nodes that are caught
1615 // in between chained nodes to the chained and interior nodes list.
1616 SmallVector<SDNode*, 3> InteriorChainedNodes;
1617 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1618 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1619 InteriorChainedNodes) == CR_InducesCycle)
1620 return SDValue(); // Would induce a cycle.
1623 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1624 // that we are interested in. Form our input TokenFactor node.
1625 SmallVector<SDValue, 3> InputChains;
1626 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1627 // Add the input chain of this node to the InputChains list (which will be
1628 // the operands of the generated TokenFactor) if it's not an interior node.
1629 SDNode *N = ChainNodesMatched[i];
1630 if (N->getOpcode() != ISD::TokenFactor) {
1631 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1634 // Otherwise, add the input chain.
1635 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1636 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1637 InputChains.push_back(InChain);
1641 // If we have a token factor, we want to add all inputs of the token factor
1642 // that are not part of the pattern we're matching.
1643 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1644 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1645 N->getOperand(op).getNode()))
1646 InputChains.push_back(N->getOperand(op));
1651 if (InputChains.size() == 1)
1652 return InputChains[0];
1653 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1654 MVT::Other, &InputChains[0], InputChains.size());
1657 /// MorphNode - Handle morphing a node in place for the selector.
1658 SDNode *SelectionDAGISel::
1659 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1660 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1661 // It is possible we're using MorphNodeTo to replace a node with no
1662 // normal results with one that has a normal result (or we could be
1663 // adding a chain) and the input could have flags and chains as well.
1664 // In this case we need to shift the operands down.
1665 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1666 // than the old isel though.
1667 int OldFlagResultNo = -1, OldChainResultNo = -1;
1669 unsigned NTMNumResults = Node->getNumValues();
1670 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1671 OldFlagResultNo = NTMNumResults-1;
1672 if (NTMNumResults != 1 &&
1673 Node->getValueType(NTMNumResults-2) == MVT::Other)
1674 OldChainResultNo = NTMNumResults-2;
1675 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1676 OldChainResultNo = NTMNumResults-1;
1678 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1679 // that this deletes operands of the old node that become dead.
1680 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1682 // MorphNodeTo can operate in two ways: if an existing node with the
1683 // specified operands exists, it can just return it. Otherwise, it
1684 // updates the node in place to have the requested operands.
1686 // If we updated the node in place, reset the node ID. To the isel,
1687 // this should be just like a newly allocated machine node.
1691 unsigned ResNumResults = Res->getNumValues();
1692 // Move the flag if needed.
1693 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1694 (unsigned)OldFlagResultNo != ResNumResults-1)
1695 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1696 SDValue(Res, ResNumResults-1));
1698 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1701 // Move the chain reference if needed.
1702 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1703 (unsigned)OldChainResultNo != ResNumResults-1)
1704 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1705 SDValue(Res, ResNumResults-1));
1707 // Otherwise, no replacement happened because the node already exists. Replace
1708 // Uses of the old node with the new one.
1710 CurDAG->ReplaceAllUsesWith(Node, Res);
1715 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1716 ALWAYS_INLINE static bool
1717 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1718 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1719 // Accept if it is exactly the same as a previously recorded node.
1720 unsigned RecNo = MatcherTable[MatcherIndex++];
1721 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1722 return N == RecordedNodes[RecNo];
1725 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1726 ALWAYS_INLINE static bool
1727 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1728 SelectionDAGISel &SDISel) {
1729 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1732 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1733 ALWAYS_INLINE static bool
1734 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1735 SelectionDAGISel &SDISel, SDNode *N) {
1736 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1739 ALWAYS_INLINE static bool
1740 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1742 uint16_t Opc = MatcherTable[MatcherIndex++];
1743 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1744 return N->getOpcode() == Opc;
1747 ALWAYS_INLINE static bool
1748 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1749 SDValue N, const TargetLowering &TLI) {
1750 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1751 if (N.getValueType() == VT) return true;
1753 // Handle the case when VT is iPTR.
1754 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1757 ALWAYS_INLINE static bool
1758 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1759 SDValue N, const TargetLowering &TLI,
1761 if (ChildNo >= N.getNumOperands())
1762 return false; // Match fails if out of range child #.
1763 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1767 ALWAYS_INLINE static bool
1768 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1770 return cast<CondCodeSDNode>(N)->get() ==
1771 (ISD::CondCode)MatcherTable[MatcherIndex++];
1774 ALWAYS_INLINE static bool
1775 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1776 SDValue N, const TargetLowering &TLI) {
1777 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1778 if (cast<VTSDNode>(N)->getVT() == VT)
1781 // Handle the case when VT is iPTR.
1782 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1785 ALWAYS_INLINE static bool
1786 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1788 int64_t Val = MatcherTable[MatcherIndex++];
1790 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1792 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1793 return C != 0 && C->getSExtValue() == Val;
1796 ALWAYS_INLINE static bool
1797 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1798 SDValue N, SelectionDAGISel &SDISel) {
1799 int64_t Val = MatcherTable[MatcherIndex++];
1801 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1803 if (N->getOpcode() != ISD::AND) return false;
1805 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1806 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1809 ALWAYS_INLINE static bool
1810 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1811 SDValue N, SelectionDAGISel &SDISel) {
1812 int64_t Val = MatcherTable[MatcherIndex++];
1814 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1816 if (N->getOpcode() != ISD::OR) return false;
1818 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1819 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1822 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1823 /// scope, evaluate the current node. If the current predicate is known to
1824 /// fail, set Result=true and return anything. If the current predicate is
1825 /// known to pass, set Result=false and return the MatcherIndex to continue
1826 /// with. If the current predicate is unknown, set Result=false and return the
1827 /// MatcherIndex to continue with.
1828 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1829 unsigned Index, SDValue N,
1830 bool &Result, SelectionDAGISel &SDISel,
1831 SmallVectorImpl<SDValue> &RecordedNodes){
1832 switch (Table[Index++]) {
1835 return Index-1; // Could not evaluate this predicate.
1836 case SelectionDAGISel::OPC_CheckSame:
1837 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1839 case SelectionDAGISel::OPC_CheckPatternPredicate:
1840 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1842 case SelectionDAGISel::OPC_CheckPredicate:
1843 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1845 case SelectionDAGISel::OPC_CheckOpcode:
1846 Result = !::CheckOpcode(Table, Index, N.getNode());
1848 case SelectionDAGISel::OPC_CheckType:
1849 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1851 case SelectionDAGISel::OPC_CheckChild0Type:
1852 case SelectionDAGISel::OPC_CheckChild1Type:
1853 case SelectionDAGISel::OPC_CheckChild2Type:
1854 case SelectionDAGISel::OPC_CheckChild3Type:
1855 case SelectionDAGISel::OPC_CheckChild4Type:
1856 case SelectionDAGISel::OPC_CheckChild5Type:
1857 case SelectionDAGISel::OPC_CheckChild6Type:
1858 case SelectionDAGISel::OPC_CheckChild7Type:
1859 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1860 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1862 case SelectionDAGISel::OPC_CheckCondCode:
1863 Result = !::CheckCondCode(Table, Index, N);
1865 case SelectionDAGISel::OPC_CheckValueType:
1866 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1868 case SelectionDAGISel::OPC_CheckInteger:
1869 Result = !::CheckInteger(Table, Index, N);
1871 case SelectionDAGISel::OPC_CheckAndImm:
1872 Result = !::CheckAndImm(Table, Index, N, SDISel);
1874 case SelectionDAGISel::OPC_CheckOrImm:
1875 Result = !::CheckOrImm(Table, Index, N, SDISel);
1883 /// FailIndex - If this match fails, this is the index to continue with.
1886 /// NodeStack - The node stack when the scope was formed.
1887 SmallVector<SDValue, 4> NodeStack;
1889 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1890 unsigned NumRecordedNodes;
1892 /// NumMatchedMemRefs - The number of matched memref entries.
1893 unsigned NumMatchedMemRefs;
1895 /// InputChain/InputFlag - The current chain/flag
1896 SDValue InputChain, InputFlag;
1898 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1899 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1904 SDNode *SelectionDAGISel::
1905 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1906 unsigned TableSize) {
1907 // FIXME: Should these even be selected? Handle these cases in the caller?
1908 switch (NodeToMatch->getOpcode()) {
1911 case ISD::EntryToken: // These nodes remain the same.
1912 case ISD::BasicBlock:
1914 //case ISD::VALUETYPE:
1915 //case ISD::CONDCODE:
1916 case ISD::HANDLENODE:
1917 case ISD::MDNODE_SDNODE:
1918 case ISD::TargetConstant:
1919 case ISD::TargetConstantFP:
1920 case ISD::TargetConstantPool:
1921 case ISD::TargetFrameIndex:
1922 case ISD::TargetExternalSymbol:
1923 case ISD::TargetBlockAddress:
1924 case ISD::TargetJumpTable:
1925 case ISD::TargetGlobalTLSAddress:
1926 case ISD::TargetGlobalAddress:
1927 case ISD::TokenFactor:
1928 case ISD::CopyFromReg:
1929 case ISD::CopyToReg:
1931 NodeToMatch->setNodeId(-1); // Mark selected.
1933 case ISD::AssertSext:
1934 case ISD::AssertZext:
1935 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1936 NodeToMatch->getOperand(0));
1938 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1939 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1942 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1944 // Set up the node stack with NodeToMatch as the only node on the stack.
1945 SmallVector<SDValue, 8> NodeStack;
1946 SDValue N = SDValue(NodeToMatch, 0);
1947 NodeStack.push_back(N);
1949 // MatchScopes - Scopes used when matching, if a match failure happens, this
1950 // indicates where to continue checking.
1951 SmallVector<MatchScope, 8> MatchScopes;
1953 // RecordedNodes - This is the set of nodes that have been recorded by the
1955 SmallVector<SDValue, 8> RecordedNodes;
1957 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1959 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1961 // These are the current input chain and flag for use when generating nodes.
1962 // Various Emit operations change these. For example, emitting a copytoreg
1963 // uses and updates these.
1964 SDValue InputChain, InputFlag;
1966 // ChainNodesMatched - If a pattern matches nodes that have input/output
1967 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1968 // which ones they are. The result is captured into this list so that we can
1969 // update the chain results when the pattern is complete.
1970 SmallVector<SDNode*, 3> ChainNodesMatched;
1971 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1973 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1974 NodeToMatch->dump(CurDAG);
1977 // Determine where to start the interpreter. Normally we start at opcode #0,
1978 // but if the state machine starts with an OPC_SwitchOpcode, then we
1979 // accelerate the first lookup (which is guaranteed to be hot) with the
1980 // OpcodeOffset table.
1981 unsigned MatcherIndex = 0;
1983 if (!OpcodeOffset.empty()) {
1984 // Already computed the OpcodeOffset table, just index into it.
1985 if (N.getOpcode() < OpcodeOffset.size())
1986 MatcherIndex = OpcodeOffset[N.getOpcode()];
1987 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1989 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1990 // Otherwise, the table isn't computed, but the state machine does start
1991 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1992 // is the first time we're selecting an instruction.
1995 // Get the size of this case.
1996 unsigned CaseSize = MatcherTable[Idx++];
1998 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1999 if (CaseSize == 0) break;
2001 // Get the opcode, add the index to the table.
2002 uint16_t Opc = MatcherTable[Idx++];
2003 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2004 if (Opc >= OpcodeOffset.size())
2005 OpcodeOffset.resize((Opc+1)*2);
2006 OpcodeOffset[Opc] = Idx;
2010 // Okay, do the lookup for the first opcode.
2011 if (N.getOpcode() < OpcodeOffset.size())
2012 MatcherIndex = OpcodeOffset[N.getOpcode()];
2016 assert(MatcherIndex < TableSize && "Invalid index");
2018 unsigned CurrentOpcodeIndex = MatcherIndex;
2020 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2023 // Okay, the semantics of this operation are that we should push a scope
2024 // then evaluate the first child. However, pushing a scope only to have
2025 // the first check fail (which then pops it) is inefficient. If we can
2026 // determine immediately that the first check (or first several) will
2027 // immediately fail, don't even bother pushing a scope for them.
2031 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2032 if (NumToSkip & 128)
2033 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2034 // Found the end of the scope with no match.
2035 if (NumToSkip == 0) {
2040 FailIndex = MatcherIndex+NumToSkip;
2042 unsigned MatcherIndexOfPredicate = MatcherIndex;
2043 (void)MatcherIndexOfPredicate; // silence warning.
2045 // If we can't evaluate this predicate without pushing a scope (e.g. if
2046 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2047 // push the scope and evaluate the full predicate chain.
2049 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2050 Result, *this, RecordedNodes);
2054 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2055 << "index " << MatcherIndexOfPredicate
2056 << ", continuing at " << FailIndex << "\n");
2057 ++NumDAGIselRetries;
2059 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2060 // move to the next case.
2061 MatcherIndex = FailIndex;
2064 // If the whole scope failed to match, bail.
2065 if (FailIndex == 0) break;
2067 // Push a MatchScope which indicates where to go if the first child fails
2069 MatchScope NewEntry;
2070 NewEntry.FailIndex = FailIndex;
2071 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2072 NewEntry.NumRecordedNodes = RecordedNodes.size();
2073 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2074 NewEntry.InputChain = InputChain;
2075 NewEntry.InputFlag = InputFlag;
2076 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2077 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2078 MatchScopes.push_back(NewEntry);
2081 case OPC_RecordNode:
2082 // Remember this node, it may end up being an operand in the pattern.
2083 RecordedNodes.push_back(N);
2086 case OPC_RecordChild0: case OPC_RecordChild1:
2087 case OPC_RecordChild2: case OPC_RecordChild3:
2088 case OPC_RecordChild4: case OPC_RecordChild5:
2089 case OPC_RecordChild6: case OPC_RecordChild7: {
2090 unsigned ChildNo = Opcode-OPC_RecordChild0;
2091 if (ChildNo >= N.getNumOperands())
2092 break; // Match fails if out of range child #.
2094 RecordedNodes.push_back(N->getOperand(ChildNo));
2097 case OPC_RecordMemRef:
2098 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2101 case OPC_CaptureFlagInput:
2102 // If the current node has an input flag, capture it in InputFlag.
2103 if (N->getNumOperands() != 0 &&
2104 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2105 InputFlag = N->getOperand(N->getNumOperands()-1);
2108 case OPC_MoveChild: {
2109 unsigned ChildNo = MatcherTable[MatcherIndex++];
2110 if (ChildNo >= N.getNumOperands())
2111 break; // Match fails if out of range child #.
2112 N = N.getOperand(ChildNo);
2113 NodeStack.push_back(N);
2117 case OPC_MoveParent:
2118 // Pop the current node off the NodeStack.
2119 NodeStack.pop_back();
2120 assert(!NodeStack.empty() && "Node stack imbalance!");
2121 N = NodeStack.back();
2125 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2127 case OPC_CheckPatternPredicate:
2128 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2130 case OPC_CheckPredicate:
2131 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2135 case OPC_CheckComplexPat: {
2136 unsigned CPNum = MatcherTable[MatcherIndex++];
2137 unsigned RecNo = MatcherTable[MatcherIndex++];
2138 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2139 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2144 case OPC_CheckOpcode:
2145 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2149 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2152 case OPC_SwitchOpcode: {
2153 unsigned CurNodeOpcode = N.getOpcode();
2154 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2157 // Get the size of this case.
2158 CaseSize = MatcherTable[MatcherIndex++];
2160 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2161 if (CaseSize == 0) break;
2163 uint16_t Opc = MatcherTable[MatcherIndex++];
2164 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2166 // If the opcode matches, then we will execute this case.
2167 if (CurNodeOpcode == Opc)
2170 // Otherwise, skip over this case.
2171 MatcherIndex += CaseSize;
2174 // If no cases matched, bail out.
2175 if (CaseSize == 0) break;
2177 // Otherwise, execute the case we found.
2178 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2179 << " to " << MatcherIndex << "\n");
2183 case OPC_SwitchType: {
2184 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2185 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2188 // Get the size of this case.
2189 CaseSize = MatcherTable[MatcherIndex++];
2191 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2192 if (CaseSize == 0) break;
2194 MVT::SimpleValueType CaseVT =
2195 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2196 if (CaseVT == MVT::iPTR)
2197 CaseVT = TLI.getPointerTy().SimpleTy;
2199 // If the VT matches, then we will execute this case.
2200 if (CurNodeVT == CaseVT)
2203 // Otherwise, skip over this case.
2204 MatcherIndex += CaseSize;
2207 // If no cases matched, bail out.
2208 if (CaseSize == 0) break;
2210 // Otherwise, execute the case we found.
2211 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2212 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2215 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2216 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2217 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2218 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2219 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2220 Opcode-OPC_CheckChild0Type))
2223 case OPC_CheckCondCode:
2224 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2226 case OPC_CheckValueType:
2227 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2229 case OPC_CheckInteger:
2230 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2232 case OPC_CheckAndImm:
2233 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2235 case OPC_CheckOrImm:
2236 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2239 case OPC_CheckFoldableChainNode: {
2240 assert(NodeStack.size() != 1 && "No parent node");
2241 // Verify that all intermediate nodes between the root and this one have
2243 bool HasMultipleUses = false;
2244 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2245 if (!NodeStack[i].hasOneUse()) {
2246 HasMultipleUses = true;
2249 if (HasMultipleUses) break;
2251 // Check to see that the target thinks this is profitable to fold and that
2252 // we can fold it without inducing cycles in the graph.
2253 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2255 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2256 NodeToMatch, OptLevel,
2257 true/*We validate our own chains*/))
2262 case OPC_EmitInteger: {
2263 MVT::SimpleValueType VT =
2264 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2265 int64_t Val = MatcherTable[MatcherIndex++];
2267 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2268 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2271 case OPC_EmitRegister: {
2272 MVT::SimpleValueType VT =
2273 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2274 unsigned RegNo = MatcherTable[MatcherIndex++];
2275 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2279 case OPC_EmitConvertToTarget: {
2280 // Convert from IMM/FPIMM to target version.
2281 unsigned RecNo = MatcherTable[MatcherIndex++];
2282 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2283 SDValue Imm = RecordedNodes[RecNo];
2285 if (Imm->getOpcode() == ISD::Constant) {
2286 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2287 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2288 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2289 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2290 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2293 RecordedNodes.push_back(Imm);
2297 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2298 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2299 // These are space-optimized forms of OPC_EmitMergeInputChains.
2300 assert(InputChain.getNode() == 0 &&
2301 "EmitMergeInputChains should be the first chain producing node");
2302 assert(ChainNodesMatched.empty() &&
2303 "Should only have one EmitMergeInputChains per match");
2305 // Read all of the chained nodes.
2306 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2307 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2308 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2310 // FIXME: What if other value results of the node have uses not matched
2312 if (ChainNodesMatched.back() != NodeToMatch &&
2313 !RecordedNodes[RecNo].hasOneUse()) {
2314 ChainNodesMatched.clear();
2318 // Merge the input chains if they are not intra-pattern references.
2319 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2321 if (InputChain.getNode() == 0)
2322 break; // Failed to merge.
2326 case OPC_EmitMergeInputChains: {
2327 assert(InputChain.getNode() == 0 &&
2328 "EmitMergeInputChains should be the first chain producing node");
2329 // This node gets a list of nodes we matched in the input that have
2330 // chains. We want to token factor all of the input chains to these nodes
2331 // together. However, if any of the input chains is actually one of the
2332 // nodes matched in this pattern, then we have an intra-match reference.
2333 // Ignore these because the newly token factored chain should not refer to
2335 unsigned NumChains = MatcherTable[MatcherIndex++];
2336 assert(NumChains != 0 && "Can't TF zero chains");
2338 assert(ChainNodesMatched.empty() &&
2339 "Should only have one EmitMergeInputChains per match");
2341 // Read all of the chained nodes.
2342 for (unsigned i = 0; i != NumChains; ++i) {
2343 unsigned RecNo = MatcherTable[MatcherIndex++];
2344 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2345 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2347 // FIXME: What if other value results of the node have uses not matched
2349 if (ChainNodesMatched.back() != NodeToMatch &&
2350 !RecordedNodes[RecNo].hasOneUse()) {
2351 ChainNodesMatched.clear();
2356 // If the inner loop broke out, the match fails.
2357 if (ChainNodesMatched.empty())
2360 // Merge the input chains if they are not intra-pattern references.
2361 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2363 if (InputChain.getNode() == 0)
2364 break; // Failed to merge.
2369 case OPC_EmitCopyToReg: {
2370 unsigned RecNo = MatcherTable[MatcherIndex++];
2371 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2372 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2374 if (InputChain.getNode() == 0)
2375 InputChain = CurDAG->getEntryNode();
2377 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2378 DestPhysReg, RecordedNodes[RecNo],
2381 InputFlag = InputChain.getValue(1);
2385 case OPC_EmitNodeXForm: {
2386 unsigned XFormNo = MatcherTable[MatcherIndex++];
2387 unsigned RecNo = MatcherTable[MatcherIndex++];
2388 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2389 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2394 case OPC_MorphNodeTo: {
2395 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2396 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2397 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2398 // Get the result VT list.
2399 unsigned NumVTs = MatcherTable[MatcherIndex++];
2400 SmallVector<EVT, 4> VTs;
2401 for (unsigned i = 0; i != NumVTs; ++i) {
2402 MVT::SimpleValueType VT =
2403 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2404 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2408 if (EmitNodeInfo & OPFL_Chain)
2409 VTs.push_back(MVT::Other);
2410 if (EmitNodeInfo & OPFL_FlagOutput)
2411 VTs.push_back(MVT::Flag);
2413 // This is hot code, so optimize the two most common cases of 1 and 2
2416 if (VTs.size() == 1)
2417 VTList = CurDAG->getVTList(VTs[0]);
2418 else if (VTs.size() == 2)
2419 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2421 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2423 // Get the operand list.
2424 unsigned NumOps = MatcherTable[MatcherIndex++];
2425 SmallVector<SDValue, 8> Ops;
2426 for (unsigned i = 0; i != NumOps; ++i) {
2427 unsigned RecNo = MatcherTable[MatcherIndex++];
2429 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2431 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2432 Ops.push_back(RecordedNodes[RecNo]);
2435 // If there are variadic operands to add, handle them now.
2436 if (EmitNodeInfo & OPFL_VariadicInfo) {
2437 // Determine the start index to copy from.
2438 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2439 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2440 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2441 "Invalid variadic node");
2442 // Copy all of the variadic operands, not including a potential flag
2444 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2446 SDValue V = NodeToMatch->getOperand(i);
2447 if (V.getValueType() == MVT::Flag) break;
2452 // If this has chain/flag inputs, add them.
2453 if (EmitNodeInfo & OPFL_Chain)
2454 Ops.push_back(InputChain);
2455 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2456 Ops.push_back(InputFlag);
2460 if (Opcode != OPC_MorphNodeTo) {
2461 // If this is a normal EmitNode command, just create the new node and
2462 // add the results to the RecordedNodes list.
2463 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2464 VTList, Ops.data(), Ops.size());
2466 // Add all the non-flag/non-chain results to the RecordedNodes list.
2467 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2468 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2469 RecordedNodes.push_back(SDValue(Res, i));
2473 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2477 // If the node had chain/flag results, update our notion of the current
2479 if (EmitNodeInfo & OPFL_FlagOutput) {
2480 InputFlag = SDValue(Res, VTs.size()-1);
2481 if (EmitNodeInfo & OPFL_Chain)
2482 InputChain = SDValue(Res, VTs.size()-2);
2483 } else if (EmitNodeInfo & OPFL_Chain)
2484 InputChain = SDValue(Res, VTs.size()-1);
2486 // If the OPFL_MemRefs flag is set on this node, slap all of the
2487 // accumulated memrefs onto it.
2489 // FIXME: This is vastly incorrect for patterns with multiple outputs
2490 // instructions that access memory and for ComplexPatterns that match
2492 if (EmitNodeInfo & OPFL_MemRefs) {
2493 MachineSDNode::mmo_iterator MemRefs =
2494 MF->allocateMemRefsArray(MatchedMemRefs.size());
2495 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2496 cast<MachineSDNode>(Res)
2497 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2501 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2502 << " node: "; Res->dump(CurDAG); errs() << "\n");
2504 // If this was a MorphNodeTo then we're completely done!
2505 if (Opcode == OPC_MorphNodeTo) {
2506 // Update chain and flag uses.
2507 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2508 InputFlag, FlagResultNodesMatched, true);
2515 case OPC_MarkFlagResults: {
2516 unsigned NumNodes = MatcherTable[MatcherIndex++];
2518 // Read and remember all the flag-result nodes.
2519 for (unsigned i = 0; i != NumNodes; ++i) {
2520 unsigned RecNo = MatcherTable[MatcherIndex++];
2522 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2524 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2525 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2530 case OPC_CompleteMatch: {
2531 // The match has been completed, and any new nodes (if any) have been
2532 // created. Patch up references to the matched dag to use the newly
2534 unsigned NumResults = MatcherTable[MatcherIndex++];
2536 for (unsigned i = 0; i != NumResults; ++i) {
2537 unsigned ResSlot = MatcherTable[MatcherIndex++];
2539 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2541 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2542 SDValue Res = RecordedNodes[ResSlot];
2544 assert(i < NodeToMatch->getNumValues() &&
2545 NodeToMatch->getValueType(i) != MVT::Other &&
2546 NodeToMatch->getValueType(i) != MVT::Flag &&
2547 "Invalid number of results to complete!");
2548 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2549 NodeToMatch->getValueType(i) == MVT::iPTR ||
2550 Res.getValueType() == MVT::iPTR ||
2551 NodeToMatch->getValueType(i).getSizeInBits() ==
2552 Res.getValueType().getSizeInBits()) &&
2553 "invalid replacement");
2554 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2557 // If the root node defines a flag, add it to the flag nodes to update
2559 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2560 FlagResultNodesMatched.push_back(NodeToMatch);
2562 // Update chain and flag uses.
2563 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2564 InputFlag, FlagResultNodesMatched, false);
2566 assert(NodeToMatch->use_empty() &&
2567 "Didn't replace all uses of the node?");
2569 // FIXME: We just return here, which interacts correctly with SelectRoot
2570 // above. We should fix this to not return an SDNode* anymore.
2575 // If the code reached this point, then the match failed. See if there is
2576 // another child to try in the current 'Scope', otherwise pop it until we
2577 // find a case to check.
2578 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2579 ++NumDAGIselRetries;
2581 if (MatchScopes.empty()) {
2582 CannotYetSelect(NodeToMatch);
2586 // Restore the interpreter state back to the point where the scope was
2588 MatchScope &LastScope = MatchScopes.back();
2589 RecordedNodes.resize(LastScope.NumRecordedNodes);
2591 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2592 N = NodeStack.back();
2594 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2595 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2596 MatcherIndex = LastScope.FailIndex;
2598 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2600 InputChain = LastScope.InputChain;
2601 InputFlag = LastScope.InputFlag;
2602 if (!LastScope.HasChainNodesMatched)
2603 ChainNodesMatched.clear();
2604 if (!LastScope.HasFlagResultNodesMatched)
2605 FlagResultNodesMatched.clear();
2607 // Check to see what the offset is at the new MatcherIndex. If it is zero
2608 // we have reached the end of this scope, otherwise we have another child
2609 // in the current scope to try.
2610 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2611 if (NumToSkip & 128)
2612 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2614 // If we have another child in this scope to match, update FailIndex and
2616 if (NumToSkip != 0) {
2617 LastScope.FailIndex = MatcherIndex+NumToSkip;
2621 // End of this scope, pop it and try the next child in the containing
2623 MatchScopes.pop_back();
2630 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2632 raw_string_ostream Msg(msg);
2633 Msg << "Cannot yet select: ";
2635 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2636 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2637 N->getOpcode() != ISD::INTRINSIC_VOID) {
2638 N->printrFull(Msg, CurDAG);
2640 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2642 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2643 if (iid < Intrinsic::num_intrinsics)
2644 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2645 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2646 Msg << "target intrinsic %" << TII->getName(iid);
2648 Msg << "unknown intrinsic #" << iid;
2650 report_fatal_error(Msg.str());
2653 char SelectionDAGISel::ID = 0;