1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/TargetLibraryInfo.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugInfo.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/IntrinsicInst.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/LLVMContext.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetIntrinsicInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "llvm/Target/TargetOptions.h"
57 #include "llvm/Target/TargetRegisterInfo.h"
58 #include "llvm/Target/TargetSubtargetInfo.h"
59 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
63 #define DEBUG_TYPE "isel"
65 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
66 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
67 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
68 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
69 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
70 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
71 STATISTIC(NumFastIselFailLowerArguments,
72 "Number of entry blocks where fast isel failed to lower arguments");
76 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
77 cl::desc("Enable extra verbose messages in the \"fast\" "
78 "instruction selector"));
81 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
82 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
83 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
84 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
85 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
86 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
87 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
89 // Standard binary operators...
90 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
91 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
92 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
93 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
94 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
95 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
96 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
97 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
98 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
99 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
100 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
101 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
103 // Logical operators...
104 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
105 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
106 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
108 // Memory instructions...
109 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
110 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
111 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
112 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
113 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
114 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
115 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
117 // Convert instructions...
118 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
119 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
120 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
121 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
122 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
123 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
124 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
125 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
126 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
127 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
128 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
129 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
131 // Other instructions...
132 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
133 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
134 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
135 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
136 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
137 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
138 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
139 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
140 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
141 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
142 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
143 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
144 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
145 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
146 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
148 // Intrinsic instructions...
149 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
150 STATISTIC(NumFastIselFailSAddWithOverflow,
151 "Fast isel fails on sadd.with.overflow");
152 STATISTIC(NumFastIselFailUAddWithOverflow,
153 "Fast isel fails on uadd.with.overflow");
154 STATISTIC(NumFastIselFailSSubWithOverflow,
155 "Fast isel fails on ssub.with.overflow");
156 STATISTIC(NumFastIselFailUSubWithOverflow,
157 "Fast isel fails on usub.with.overflow");
158 STATISTIC(NumFastIselFailSMulWithOverflow,
159 "Fast isel fails on smul.with.overflow");
160 STATISTIC(NumFastIselFailUMulWithOverflow,
161 "Fast isel fails on umul.with.overflow");
162 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
163 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
164 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
165 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
169 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
170 cl::desc("Enable verbose messages in the \"fast\" "
171 "instruction selector"));
172 static cl::opt<int> EnableFastISelAbort(
173 "fast-isel-abort", cl::Hidden,
174 cl::desc("Enable abort calls when \"fast\" instruction selection "
175 "fails to lower an instruction: 0 disable the abort, 1 will "
176 "abort but for args, calls and terminators, 2 will also "
177 "abort for argument lowering, and 3 will never fallback "
178 "to SelectionDAG."));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None ||
297 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
298 TLI->getSchedulingPreference() == Sched::Source)
299 return createSourceListDAGScheduler(IS, OptLevel);
300 if (TLI->getSchedulingPreference() == Sched::RegPressure)
301 return createBURRListDAGScheduler(IS, OptLevel);
302 if (TLI->getSchedulingPreference() == Sched::Hybrid)
303 return createHybridListDAGScheduler(IS, OptLevel);
304 if (TLI->getSchedulingPreference() == Sched::VLIW)
305 return createVLIWDAGScheduler(IS, OptLevel);
306 assert(TLI->getSchedulingPreference() == Sched::ILP &&
307 "Unknown sched type!");
308 return createILPListDAGScheduler(IS, OptLevel);
312 // EmitInstrWithCustomInserter - This method should be implemented by targets
313 // that mark instructions with the 'usesCustomInserter' flag. These
314 // instructions are special in various ways, which require special support to
315 // insert. The specified MachineInstr is created but not inserted into any
316 // basic blocks, and this method is called to expand it into a sequence of
317 // instructions, potentially also creating new basic blocks and control flow.
318 // When new basic blocks are inserted and the edges from MBB to its successors
319 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
322 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
323 MachineBasicBlock *MBB) const {
325 dbgs() << "If a target marks an instruction with "
326 "'usesCustomInserter', it must implement "
327 "TargetLowering::EmitInstrWithCustomInserter!";
329 llvm_unreachable(nullptr);
332 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
333 SDNode *Node) const {
334 assert(!MI->hasPostISelHook() &&
335 "If a target marks an instruction with 'hasPostISelHook', "
336 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
339 //===----------------------------------------------------------------------===//
340 // SelectionDAGISel code
341 //===----------------------------------------------------------------------===//
343 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
344 CodeGenOpt::Level OL) :
345 MachineFunctionPass(ID), TM(tm),
346 FuncInfo(new FunctionLoweringInfo()),
347 CurDAG(new SelectionDAG(tm, OL)),
348 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
352 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
353 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
354 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
355 initializeTargetLibraryInfoWrapperPassPass(
356 *PassRegistry::getPassRegistry());
359 SelectionDAGISel::~SelectionDAGISel() {
365 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
366 AU.addRequired<AliasAnalysis>();
367 AU.addPreserved<AliasAnalysis>();
368 AU.addRequired<GCModuleInfo>();
369 AU.addPreserved<GCModuleInfo>();
370 AU.addRequired<TargetLibraryInfoWrapperPass>();
371 if (UseMBPI && OptLevel != CodeGenOpt::None)
372 AU.addRequired<BranchProbabilityInfo>();
373 MachineFunctionPass::getAnalysisUsage(AU);
376 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
377 /// may trap on it. In this case we have to split the edge so that the path
378 /// through the predecessor block that doesn't go to the phi block doesn't
379 /// execute the possibly trapping instruction.
381 /// This is required for correctness, so it must be done at -O0.
383 static void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA) {
384 // Loop for blocks with phi nodes.
385 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
386 PHINode *PN = dyn_cast<PHINode>(BB->begin());
390 // For each block with a PHI node, check to see if any of the input values
391 // are potentially trapping constant expressions. Constant expressions are
392 // the only potentially trapping value that can occur as the argument to a
394 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
395 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
396 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
397 if (!CE || !CE->canTrap()) continue;
399 // The only case we have to worry about is when the edge is critical.
400 // Since this block has a PHI Node, we assume it has multiple input
401 // edges: check to see if the pred has multiple successors.
402 BasicBlock *Pred = PN->getIncomingBlock(i);
403 if (Pred->getTerminator()->getNumSuccessors() == 1)
406 // Okay, we have to split this edge.
408 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
409 CriticalEdgeSplittingOptions(AA).setMergeIdenticalEdges());
415 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
416 // Do some sanity-checking on the command-line options.
417 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
418 "-fast-isel-verbose requires -fast-isel");
419 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
420 "-fast-isel-abort > 0 requires -fast-isel");
422 const Function &Fn = *mf.getFunction();
425 // Reset the target options before resetting the optimization
427 // FIXME: This is a horrible hack and should be processed via
428 // codegen looking at the optimization level explicitly when
429 // it wants to look at it.
430 TM.resetTargetOptions(Fn);
431 // Reset OptLevel to None for optnone functions.
432 CodeGenOpt::Level NewOptLevel = OptLevel;
433 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
434 NewOptLevel = CodeGenOpt::None;
435 OptLevelChanger OLC(*this, NewOptLevel);
437 TII = MF->getSubtarget().getInstrInfo();
438 TLI = MF->getSubtarget().getTargetLowering();
439 RegInfo = &MF->getRegInfo();
440 AA = &getAnalysis<AliasAnalysis>();
441 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
442 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
444 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
446 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), AA);
449 FuncInfo->set(Fn, *MF, CurDAG);
451 if (UseMBPI && OptLevel != CodeGenOpt::None)
452 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
454 FuncInfo->BPI = nullptr;
456 SDB->init(GFI, *AA, LibInfo);
458 MF->setHasInlineAsm(false);
460 SelectAllBasicBlocks(Fn);
462 // If the first basic block in the function has live ins that need to be
463 // copied into vregs, emit the copies into the top of the block before
464 // emitting the code for the block.
465 MachineBasicBlock *EntryMBB = MF->begin();
466 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
467 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
469 DenseMap<unsigned, unsigned> LiveInMap;
470 if (!FuncInfo->ArgDbgValues.empty())
471 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
472 E = RegInfo->livein_end(); LI != E; ++LI)
474 LiveInMap.insert(std::make_pair(LI->first, LI->second));
476 // Insert DBG_VALUE instructions for function arguments to the entry block.
477 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
478 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
479 bool hasFI = MI->getOperand(0).isFI();
481 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
482 if (TargetRegisterInfo::isPhysicalRegister(Reg))
483 EntryMBB->insert(EntryMBB->begin(), MI);
485 MachineInstr *Def = RegInfo->getVRegDef(Reg);
487 MachineBasicBlock::iterator InsertPos = Def;
488 // FIXME: VR def may not be in entry block.
489 Def->getParent()->insert(std::next(InsertPos), MI);
491 DEBUG(dbgs() << "Dropping debug info for dead vreg"
492 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
495 // If Reg is live-in then update debug info to track its copy in a vreg.
496 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
497 if (LDI != LiveInMap.end()) {
498 assert(!hasFI && "There's no handling of frame pointer updating here yet "
500 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
501 MachineBasicBlock::iterator InsertPos = Def;
502 const MDNode *Variable = MI->getDebugVariable();
503 const MDNode *Expr = MI->getDebugExpression();
504 DebugLoc DL = MI->getDebugLoc();
505 bool IsIndirect = MI->isIndirectDebugValue();
506 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
507 assert(cast<MDLocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
508 "Expected inlined-at fields to agree");
509 // Def is never a terminator here, so it is ok to increment InsertPos.
510 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
511 IsIndirect, LDI->second, Offset, Variable, Expr);
513 // If this vreg is directly copied into an exported register then
514 // that COPY instructions also need DBG_VALUE, if it is the only
515 // user of LDI->second.
516 MachineInstr *CopyUseMI = nullptr;
517 for (MachineRegisterInfo::use_instr_iterator
518 UI = RegInfo->use_instr_begin(LDI->second),
519 E = RegInfo->use_instr_end(); UI != E; ) {
520 MachineInstr *UseMI = &*(UI++);
521 if (UseMI->isDebugValue()) continue;
522 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
523 CopyUseMI = UseMI; continue;
525 // Otherwise this is another use or second copy use.
526 CopyUseMI = nullptr; break;
529 // Use MI's debug location, which describes where Variable was
530 // declared, rather than whatever is attached to CopyUseMI.
531 MachineInstr *NewMI =
532 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
533 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
534 MachineBasicBlock::iterator Pos = CopyUseMI;
535 EntryMBB->insertAfter(Pos, NewMI);
540 // Determine if there are any calls in this machine function.
541 MachineFrameInfo *MFI = MF->getFrameInfo();
542 for (const auto &MBB : *MF) {
543 if (MFI->hasCalls() && MF->hasInlineAsm())
546 for (const auto &MI : MBB) {
547 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
548 if ((MCID.isCall() && !MCID.isReturn()) ||
549 MI.isStackAligningInlineAsm()) {
550 MFI->setHasCalls(true);
552 if (MI.isInlineAsm()) {
553 MF->setHasInlineAsm(true);
558 // Determine if there is a call to setjmp in the machine function.
559 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
561 // Replace forward-declared registers with the registers containing
562 // the desired value.
563 MachineRegisterInfo &MRI = MF->getRegInfo();
564 for (DenseMap<unsigned, unsigned>::iterator
565 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
567 unsigned From = I->first;
568 unsigned To = I->second;
569 // If To is also scheduled to be replaced, find what its ultimate
572 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
576 // Make sure the new register has a sufficiently constrained register class.
577 if (TargetRegisterInfo::isVirtualRegister(From) &&
578 TargetRegisterInfo::isVirtualRegister(To))
579 MRI.constrainRegClass(To, MRI.getRegClass(From));
581 MRI.replaceRegWith(From, To);
584 // Freeze the set of reserved registers now that MachineFrameInfo has been
585 // set up. All the information required by getReservedRegs() should be
587 MRI.freezeReservedRegs(*MF);
589 // Release function-specific state. SDB and CurDAG are already cleared
593 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
594 DEBUG(MF->print(dbgs()));
599 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
600 BasicBlock::const_iterator End,
602 // Lower the instructions. If a call is emitted as a tail call, cease emitting
603 // nodes for this block.
604 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
607 // Make sure the root of the DAG is up-to-date.
608 CurDAG->setRoot(SDB->getControlRoot());
609 HadTailCall = SDB->HasTailCall;
612 // Final step, emit the lowered DAG as machine code.
616 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
617 SmallPtrSet<SDNode*, 128> VisitedNodes;
618 SmallVector<SDNode*, 128> Worklist;
620 Worklist.push_back(CurDAG->getRoot().getNode());
626 SDNode *N = Worklist.pop_back_val();
628 // If we've already seen this node, ignore it.
629 if (!VisitedNodes.insert(N).second)
632 // Otherwise, add all chain operands to the worklist.
633 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
634 if (N->getOperand(i).getValueType() == MVT::Other)
635 Worklist.push_back(N->getOperand(i).getNode());
637 // If this is a CopyToReg with a vreg dest, process it.
638 if (N->getOpcode() != ISD::CopyToReg)
641 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
642 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
645 // Ignore non-scalar or non-integer values.
646 SDValue Src = N->getOperand(2);
647 EVT SrcVT = Src.getValueType();
648 if (!SrcVT.isInteger() || SrcVT.isVector())
651 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
652 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
653 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
654 } while (!Worklist.empty());
657 void SelectionDAGISel::CodeGenAndEmitDAG() {
658 std::string GroupName;
659 if (TimePassesIsEnabled)
660 GroupName = "Instruction Selection and Scheduling";
661 std::string BlockName;
662 int BlockNumber = -1;
664 bool MatchFilterBB = false; (void)MatchFilterBB;
666 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
667 FilterDAGBasicBlockName ==
668 FuncInfo->MBB->getBasicBlock()->getName().str());
671 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
672 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
676 BlockNumber = FuncInfo->MBB->getNumber();
678 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
680 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
681 << " '" << BlockName << "'\n"; CurDAG->dump());
683 if (ViewDAGCombine1 && MatchFilterBB)
684 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
686 // Run the DAG combiner in pre-legalize mode.
688 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
689 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
692 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
693 << " '" << BlockName << "'\n"; CurDAG->dump());
695 // Second step, hack on the DAG until it only uses operations and types that
696 // the target supports.
697 if (ViewLegalizeTypesDAGs && MatchFilterBB)
698 CurDAG->viewGraph("legalize-types input for " + BlockName);
702 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
703 Changed = CurDAG->LegalizeTypes();
706 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
707 << " '" << BlockName << "'\n"; CurDAG->dump());
709 CurDAG->NewNodesMustHaveLegalTypes = true;
712 if (ViewDAGCombineLT && MatchFilterBB)
713 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
715 // Run the DAG combiner in post-type-legalize mode.
717 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
718 TimePassesIsEnabled);
719 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
722 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
723 << " '" << BlockName << "'\n"; CurDAG->dump());
728 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
729 Changed = CurDAG->LegalizeVectors();
734 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
735 CurDAG->LegalizeTypes();
738 if (ViewDAGCombineLT && MatchFilterBB)
739 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
741 // Run the DAG combiner in post-type-legalize mode.
743 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
744 TimePassesIsEnabled);
745 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
748 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
749 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
752 if (ViewLegalizeDAGs && MatchFilterBB)
753 CurDAG->viewGraph("legalize input for " + BlockName);
756 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
760 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
761 << " '" << BlockName << "'\n"; CurDAG->dump());
763 if (ViewDAGCombine2 && MatchFilterBB)
764 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
766 // Run the DAG combiner in post-legalize mode.
768 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
769 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
772 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
773 << " '" << BlockName << "'\n"; CurDAG->dump());
775 if (OptLevel != CodeGenOpt::None)
776 ComputeLiveOutVRegInfo();
778 if (ViewISelDAGs && MatchFilterBB)
779 CurDAG->viewGraph("isel input for " + BlockName);
781 // Third, instruction select all of the operations to machine code, adding the
782 // code to the MachineBasicBlock.
784 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
785 DoInstructionSelection();
788 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
789 << " '" << BlockName << "'\n"; CurDAG->dump());
791 if (ViewSchedDAGs && MatchFilterBB)
792 CurDAG->viewGraph("scheduler input for " + BlockName);
794 // Schedule machine code.
795 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
797 NamedRegionTimer T("Instruction Scheduling", GroupName,
798 TimePassesIsEnabled);
799 Scheduler->Run(CurDAG, FuncInfo->MBB);
802 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
804 // Emit machine code to BB. This can change 'BB' to the last block being
806 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
808 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
810 // FuncInfo->InsertPt is passed by reference and set to the end of the
811 // scheduled instructions.
812 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
815 // If the block was split, make sure we update any references that are used to
816 // update PHI nodes later on.
817 if (FirstMBB != LastMBB)
818 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
820 // Free the scheduler state.
822 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
823 TimePassesIsEnabled);
827 // Free the SelectionDAG state, now that we're finished with it.
832 /// ISelUpdater - helper class to handle updates of the instruction selection
834 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
835 SelectionDAG::allnodes_iterator &ISelPosition;
837 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
838 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
840 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
841 /// deleted is the current ISelPosition node, update ISelPosition.
843 void NodeDeleted(SDNode *N, SDNode *E) override {
844 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
848 } // end anonymous namespace
850 void SelectionDAGISel::DoInstructionSelection() {
851 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
852 << FuncInfo->MBB->getNumber()
853 << " '" << FuncInfo->MBB->getName() << "'\n");
857 // Select target instructions for the DAG.
859 // Number all nodes with a topological order and set DAGSize.
860 DAGSize = CurDAG->AssignTopologicalOrder();
862 // Create a dummy node (which is not added to allnodes), that adds
863 // a reference to the root node, preventing it from being deleted,
864 // and tracking any changes of the root.
865 HandleSDNode Dummy(CurDAG->getRoot());
866 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
869 // Make sure that ISelPosition gets properly updated when nodes are deleted
870 // in calls made from this function.
871 ISelUpdater ISU(*CurDAG, ISelPosition);
873 // The AllNodes list is now topological-sorted. Visit the
874 // nodes by starting at the end of the list (the root of the
875 // graph) and preceding back toward the beginning (the entry
877 while (ISelPosition != CurDAG->allnodes_begin()) {
878 SDNode *Node = --ISelPosition;
879 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
880 // but there are currently some corner cases that it misses. Also, this
881 // makes it theoretically possible to disable the DAGCombiner.
882 if (Node->use_empty())
885 SDNode *ResNode = Select(Node);
887 // FIXME: This is pretty gross. 'Select' should be changed to not return
888 // anything at all and this code should be nuked with a tactical strike.
890 // If node should not be replaced, continue with the next one.
891 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
895 ReplaceUses(Node, ResNode);
898 // If after the replacement this node is not used any more,
899 // remove this dead node.
900 if (Node->use_empty()) // Don't delete EntryToken, etc.
901 CurDAG->RemoveDeadNode(Node);
904 CurDAG->setRoot(Dummy.getValue());
907 DEBUG(dbgs() << "===== Instruction selection ends:\n");
909 PostprocessISelDAG();
912 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
913 /// do other setup for EH landing-pad blocks.
914 bool SelectionDAGISel::PrepareEHLandingPad() {
915 MachineBasicBlock *MBB = FuncInfo->MBB;
917 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
919 // Add a label to mark the beginning of the landing pad. Deletion of the
920 // landing pad can thus be detected via the MachineModuleInfo.
921 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
923 // Assign the call site to the landing pad's begin label.
924 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
926 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
927 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
930 // If this is an MSVC-style personality function, we need to split the landing
931 // pad into several BBs.
932 const BasicBlock *LLVMBB = MBB->getBasicBlock();
933 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
934 MF->getMMI().addPersonality(
935 MBB, cast<Function>(LPadInst->getPersonalityFn()->stripPointerCasts()));
936 EHPersonality Personality = MF->getMMI().getPersonalityType();
938 if (isMSVCEHPersonality(Personality)) {
939 SmallVector<MachineBasicBlock *, 4> ClauseBBs;
940 const IntrinsicInst *ActionsCall =
941 dyn_cast<IntrinsicInst>(LLVMBB->getFirstInsertionPt());
942 // Get all invoke BBs that unwind to this landingpad.
943 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
945 if (ActionsCall && ActionsCall->getIntrinsicID() == Intrinsic::eh_actions) {
946 // If this is a call to llvm.eh.actions followed by indirectbr, then we've
947 // run WinEHPrepare, and we should remove this block from the machine CFG.
948 // Mark the targets of the indirectbr as landingpads instead.
949 for (const BasicBlock *LLVMSucc : successors(LLVMBB)) {
950 MachineBasicBlock *ClauseBB = FuncInfo->MBBMap[LLVMSucc];
951 // Add the edge from the invoke to the clause.
952 for (MachineBasicBlock *InvokeBB : InvokeBBs)
953 InvokeBB->addSuccessor(ClauseBB);
955 // Mark the clause as a landing pad or MI passes will delete it.
956 ClauseBB->setIsLandingPad();
960 // Remove the edge from the invoke to the lpad.
961 for (MachineBasicBlock *InvokeBB : InvokeBBs)
962 InvokeBB->removeSuccessor(MBB);
964 // Transfer EH state number assigned to the IR block to the MBB.
965 if (Personality == EHPersonality::MSVC_CXX) {
966 WinEHFuncInfo &FI = MF->getMMI().getWinEHFuncInfo(MF->getFunction());
967 MF->getMMI().addWinEHState(MBB, FI.LandingPadStateMap[LPadInst]);
970 // Don't select instructions for the landingpad.
974 // Mark exception register as live in.
975 if (unsigned Reg = TLI->getExceptionPointerRegister())
976 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
978 // Mark exception selector register as live in.
979 if (unsigned Reg = TLI->getExceptionSelectorRegister())
980 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
985 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
986 /// side-effect free and is either dead or folded into a generated instruction.
987 /// Return false if it needs to be emitted.
988 static bool isFoldedOrDeadInstruction(const Instruction *I,
989 FunctionLoweringInfo *FuncInfo) {
990 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
991 !isa<TerminatorInst>(I) && // Terminators aren't folded.
992 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
993 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
994 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
998 // Collect per Instruction statistics for fast-isel misses. Only those
999 // instructions that cause the bail are accounted for. It does not account for
1000 // instructions higher in the block. Thus, summing the per instructions stats
1001 // will not add up to what is reported by NumFastIselFailures.
1002 static void collectFailStats(const Instruction *I) {
1003 switch (I->getOpcode()) {
1004 default: assert (0 && "<Invalid operator> ");
1007 case Instruction::Ret: NumFastIselFailRet++; return;
1008 case Instruction::Br: NumFastIselFailBr++; return;
1009 case Instruction::Switch: NumFastIselFailSwitch++; return;
1010 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1011 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1012 case Instruction::Resume: NumFastIselFailResume++; return;
1013 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1015 // Standard binary operators...
1016 case Instruction::Add: NumFastIselFailAdd++; return;
1017 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1018 case Instruction::Sub: NumFastIselFailSub++; return;
1019 case Instruction::FSub: NumFastIselFailFSub++; return;
1020 case Instruction::Mul: NumFastIselFailMul++; return;
1021 case Instruction::FMul: NumFastIselFailFMul++; return;
1022 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1023 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1024 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1025 case Instruction::URem: NumFastIselFailURem++; return;
1026 case Instruction::SRem: NumFastIselFailSRem++; return;
1027 case Instruction::FRem: NumFastIselFailFRem++; return;
1029 // Logical operators...
1030 case Instruction::And: NumFastIselFailAnd++; return;
1031 case Instruction::Or: NumFastIselFailOr++; return;
1032 case Instruction::Xor: NumFastIselFailXor++; return;
1034 // Memory instructions...
1035 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1036 case Instruction::Load: NumFastIselFailLoad++; return;
1037 case Instruction::Store: NumFastIselFailStore++; return;
1038 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1039 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1040 case Instruction::Fence: NumFastIselFailFence++; return;
1041 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1043 // Convert instructions...
1044 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1045 case Instruction::ZExt: NumFastIselFailZExt++; return;
1046 case Instruction::SExt: NumFastIselFailSExt++; return;
1047 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1048 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1049 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1050 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1051 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1052 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1053 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1054 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1055 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1057 // Other instructions...
1058 case Instruction::ICmp: NumFastIselFailICmp++; return;
1059 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1060 case Instruction::PHI: NumFastIselFailPHI++; return;
1061 case Instruction::Select: NumFastIselFailSelect++; return;
1062 case Instruction::Call: {
1063 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1064 switch (Intrinsic->getIntrinsicID()) {
1066 NumFastIselFailIntrinsicCall++; return;
1067 case Intrinsic::sadd_with_overflow:
1068 NumFastIselFailSAddWithOverflow++; return;
1069 case Intrinsic::uadd_with_overflow:
1070 NumFastIselFailUAddWithOverflow++; return;
1071 case Intrinsic::ssub_with_overflow:
1072 NumFastIselFailSSubWithOverflow++; return;
1073 case Intrinsic::usub_with_overflow:
1074 NumFastIselFailUSubWithOverflow++; return;
1075 case Intrinsic::smul_with_overflow:
1076 NumFastIselFailSMulWithOverflow++; return;
1077 case Intrinsic::umul_with_overflow:
1078 NumFastIselFailUMulWithOverflow++; return;
1079 case Intrinsic::frameaddress:
1080 NumFastIselFailFrameaddress++; return;
1081 case Intrinsic::sqrt:
1082 NumFastIselFailSqrt++; return;
1083 case Intrinsic::experimental_stackmap:
1084 NumFastIselFailStackMap++; return;
1085 case Intrinsic::experimental_patchpoint_void: // fall-through
1086 case Intrinsic::experimental_patchpoint_i64:
1087 NumFastIselFailPatchPoint++; return;
1090 NumFastIselFailCall++;
1093 case Instruction::Shl: NumFastIselFailShl++; return;
1094 case Instruction::LShr: NumFastIselFailLShr++; return;
1095 case Instruction::AShr: NumFastIselFailAShr++; return;
1096 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1097 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1098 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1099 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1100 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1101 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1102 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1107 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1108 // Initialize the Fast-ISel state, if needed.
1109 FastISel *FastIS = nullptr;
1110 if (TM.Options.EnableFastISel)
1111 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1113 // Iterate over all basic blocks in the function.
1114 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1115 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1116 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1117 const BasicBlock *LLVMBB = *I;
1119 if (OptLevel != CodeGenOpt::None) {
1120 bool AllPredsVisited = true;
1121 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1123 if (!FuncInfo->VisitedBBs.count(*PI)) {
1124 AllPredsVisited = false;
1129 if (AllPredsVisited) {
1130 for (BasicBlock::const_iterator I = LLVMBB->begin();
1131 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1132 FuncInfo->ComputePHILiveOutRegInfo(PN);
1134 for (BasicBlock::const_iterator I = LLVMBB->begin();
1135 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1136 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1139 FuncInfo->VisitedBBs.insert(LLVMBB);
1142 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1143 BasicBlock::const_iterator const End = LLVMBB->end();
1144 BasicBlock::const_iterator BI = End;
1146 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1147 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1149 // Setup an EH landing-pad block.
1150 FuncInfo->ExceptionPointerVirtReg = 0;
1151 FuncInfo->ExceptionSelectorVirtReg = 0;
1152 if (LLVMBB->isLandingPad())
1153 if (!PrepareEHLandingPad())
1156 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1158 FastIS->startNewBlock();
1160 // Emit code for any incoming arguments. This must happen before
1161 // beginning FastISel on the entry block.
1162 if (LLVMBB == &Fn.getEntryBlock()) {
1165 // Lower any arguments needed in this block if this is the entry block.
1166 if (!FastIS->lowerArguments()) {
1167 // Fast isel failed to lower these arguments
1168 ++NumFastIselFailLowerArguments;
1169 if (EnableFastISelAbort > 1)
1170 report_fatal_error("FastISel didn't lower all arguments");
1172 // Use SelectionDAG argument lowering
1174 CurDAG->setRoot(SDB->getControlRoot());
1176 CodeGenAndEmitDAG();
1179 // If we inserted any instructions at the beginning, make a note of
1180 // where they are, so we can be sure to emit subsequent instructions
1182 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1183 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1185 FastIS->setLastLocalValue(nullptr);
1188 unsigned NumFastIselRemaining = std::distance(Begin, End);
1189 // Do FastISel on as many instructions as possible.
1190 for (; BI != Begin; --BI) {
1191 const Instruction *Inst = std::prev(BI);
1193 // If we no longer require this instruction, skip it.
1194 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1195 --NumFastIselRemaining;
1199 // Bottom-up: reset the insert pos at the top, after any local-value
1201 FastIS->recomputeInsertPt();
1203 // Try to select the instruction with FastISel.
1204 if (FastIS->selectInstruction(Inst)) {
1205 --NumFastIselRemaining;
1206 ++NumFastIselSuccess;
1207 // If fast isel succeeded, skip over all the folded instructions, and
1208 // then see if there is a load right before the selected instructions.
1209 // Try to fold the load if so.
1210 const Instruction *BeforeInst = Inst;
1211 while (BeforeInst != Begin) {
1212 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1213 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1216 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1217 BeforeInst->hasOneUse() &&
1218 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1219 // If we succeeded, don't re-select the load.
1220 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1221 --NumFastIselRemaining;
1222 ++NumFastIselSuccess;
1228 if (EnableFastISelVerbose2)
1229 collectFailStats(Inst);
1232 // Then handle certain instructions as single-LLVM-Instruction blocks.
1233 if (isa<CallInst>(Inst)) {
1235 if (EnableFastISelVerbose || EnableFastISelAbort) {
1236 dbgs() << "FastISel missed call: ";
1239 if (EnableFastISelAbort > 2)
1240 // FastISel selector couldn't handle something and bailed.
1241 // For the purpose of debugging, just abort.
1242 report_fatal_error("FastISel didn't select the entire block");
1244 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1245 unsigned &R = FuncInfo->ValueMap[Inst];
1247 R = FuncInfo->CreateRegs(Inst->getType());
1250 bool HadTailCall = false;
1251 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1252 SelectBasicBlock(Inst, BI, HadTailCall);
1254 // If the call was emitted as a tail call, we're done with the block.
1255 // We also need to delete any previously emitted instructions.
1257 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1262 // Recompute NumFastIselRemaining as Selection DAG instruction
1263 // selection may have handled the call, input args, etc.
1264 unsigned RemainingNow = std::distance(Begin, BI);
1265 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1266 NumFastIselRemaining = RemainingNow;
1270 bool ShouldAbort = EnableFastISelAbort;
1271 if (EnableFastISelVerbose || EnableFastISelAbort) {
1272 if (isa<TerminatorInst>(Inst)) {
1273 // Use a different message for terminator misses.
1274 dbgs() << "FastISel missed terminator: ";
1275 // Don't abort unless for terminator unless the level is really high
1276 ShouldAbort = (EnableFastISelAbort > 2);
1278 dbgs() << "FastISel miss: ";
1283 // FastISel selector couldn't handle something and bailed.
1284 // For the purpose of debugging, just abort.
1285 report_fatal_error("FastISel didn't select the entire block");
1287 NumFastIselFailures += NumFastIselRemaining;
1291 FastIS->recomputeInsertPt();
1293 // Lower any arguments needed in this block if this is the entry block.
1294 if (LLVMBB == &Fn.getEntryBlock()) {
1303 ++NumFastIselBlocks;
1306 // Run SelectionDAG instruction selection on the remainder of the block
1307 // not handled by FastISel. If FastISel is not run, this is the entire
1310 SelectBasicBlock(Begin, BI, HadTailCall);
1314 FuncInfo->PHINodesToUpdate.clear();
1318 SDB->clearDanglingDebugInfo();
1319 SDB->SPDescriptor.resetPerFunctionState();
1322 /// Given that the input MI is before a partial terminator sequence TSeq, return
1323 /// true if M + TSeq also a partial terminator sequence.
1325 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1326 /// lowering copy vregs into physical registers, which are then passed into
1327 /// terminator instructors so we can satisfy ABI constraints. A partial
1328 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1329 /// may be the whole terminator sequence).
1330 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1331 // If we do not have a copy or an implicit def, we return true if and only if
1332 // MI is a debug value.
1333 if (!MI->isCopy() && !MI->isImplicitDef())
1334 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1335 // physical registers if there is debug info associated with the terminator
1336 // of our mbb. We want to include said debug info in our terminator
1337 // sequence, so we return true in that case.
1338 return MI->isDebugValue();
1340 // We have left the terminator sequence if we are not doing one of the
1343 // 1. Copying a vreg into a physical register.
1344 // 2. Copying a vreg into a vreg.
1345 // 3. Defining a register via an implicit def.
1347 // OPI should always be a register definition...
1348 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1349 if (!OPI->isReg() || !OPI->isDef())
1352 // Defining any register via an implicit def is always ok.
1353 if (MI->isImplicitDef())
1356 // Grab the copy source...
1357 MachineInstr::const_mop_iterator OPI2 = OPI;
1359 assert(OPI2 != MI->operands_end()
1360 && "Should have a copy implying we should have 2 arguments.");
1362 // Make sure that the copy dest is not a vreg when the copy source is a
1363 // physical register.
1364 if (!OPI2->isReg() ||
1365 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1366 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1372 /// Find the split point at which to splice the end of BB into its success stack
1373 /// protector check machine basic block.
1375 /// On many platforms, due to ABI constraints, terminators, even before register
1376 /// allocation, use physical registers. This creates an issue for us since
1377 /// physical registers at this point can not travel across basic
1378 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1379 /// when they enter functions and moves them through a sequence of copies back
1380 /// into the physical registers right before the terminator creating a
1381 /// ``Terminator Sequence''. This function is searching for the beginning of the
1382 /// terminator sequence so that we can ensure that we splice off not just the
1383 /// terminator, but additionally the copies that move the vregs into the
1384 /// physical registers.
1385 static MachineBasicBlock::iterator
1386 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1387 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1389 if (SplitPoint == BB->begin())
1392 MachineBasicBlock::iterator Start = BB->begin();
1393 MachineBasicBlock::iterator Previous = SplitPoint;
1396 while (MIIsInTerminatorSequence(Previous)) {
1397 SplitPoint = Previous;
1398 if (Previous == Start)
1407 SelectionDAGISel::FinishBasicBlock() {
1409 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1410 << FuncInfo->PHINodesToUpdate.size() << "\n";
1411 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1412 dbgs() << "Node " << i << " : ("
1413 << FuncInfo->PHINodesToUpdate[i].first
1414 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1416 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1417 // PHI nodes in successors.
1418 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1419 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1420 assert(PHI->isPHI() &&
1421 "This is not a machine PHI node that we are updating!");
1422 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1424 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1427 // Handle stack protector.
1428 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1429 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1430 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1432 // Find the split point to split the parent mbb. At the same time copy all
1433 // physical registers used in the tail of parent mbb into virtual registers
1434 // before the split point and back into physical registers after the split
1435 // point. This prevents us needing to deal with Live-ins and many other
1436 // register allocation issues caused by us splitting the parent mbb. The
1437 // register allocator will clean up said virtual copies later on.
1438 MachineBasicBlock::iterator SplitPoint =
1439 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1441 // Splice the terminator of ParentMBB into SuccessMBB.
1442 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1446 // Add compare/jump on neq/jump to the parent BB.
1447 FuncInfo->MBB = ParentMBB;
1448 FuncInfo->InsertPt = ParentMBB->end();
1449 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1450 CurDAG->setRoot(SDB->getRoot());
1452 CodeGenAndEmitDAG();
1454 // CodeGen Failure MBB if we have not codegened it yet.
1455 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1456 if (!FailureMBB->size()) {
1457 FuncInfo->MBB = FailureMBB;
1458 FuncInfo->InsertPt = FailureMBB->end();
1459 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1460 CurDAG->setRoot(SDB->getRoot());
1462 CodeGenAndEmitDAG();
1465 // Clear the Per-BB State.
1466 SDB->SPDescriptor.resetPerBBState();
1469 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1470 // Lower header first, if it wasn't already lowered
1471 if (!SDB->BitTestCases[i].Emitted) {
1472 // Set the current basic block to the mbb we wish to insert the code into
1473 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1474 FuncInfo->InsertPt = FuncInfo->MBB->end();
1476 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1477 CurDAG->setRoot(SDB->getRoot());
1479 CodeGenAndEmitDAG();
1482 uint32_t UnhandledWeight = 0;
1483 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1484 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1486 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1487 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1488 // Set the current basic block to the mbb we wish to insert the code into
1489 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1490 FuncInfo->InsertPt = FuncInfo->MBB->end();
1493 SDB->visitBitTestCase(SDB->BitTestCases[i],
1494 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1496 SDB->BitTestCases[i].Reg,
1497 SDB->BitTestCases[i].Cases[j],
1500 SDB->visitBitTestCase(SDB->BitTestCases[i],
1501 SDB->BitTestCases[i].Default,
1503 SDB->BitTestCases[i].Reg,
1504 SDB->BitTestCases[i].Cases[j],
1508 CurDAG->setRoot(SDB->getRoot());
1510 CodeGenAndEmitDAG();
1514 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1516 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1517 MachineBasicBlock *PHIBB = PHI->getParent();
1518 assert(PHI->isPHI() &&
1519 "This is not a machine PHI node that we are updating!");
1520 // This is "default" BB. We have two jumps to it. From "header" BB and
1521 // from last "case" BB.
1522 if (PHIBB == SDB->BitTestCases[i].Default)
1523 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1524 .addMBB(SDB->BitTestCases[i].Parent)
1525 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1526 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1527 // One of "cases" BB.
1528 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1530 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1531 if (cBB->isSuccessor(PHIBB))
1532 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1536 SDB->BitTestCases.clear();
1538 // If the JumpTable record is filled in, then we need to emit a jump table.
1539 // Updating the PHI nodes is tricky in this case, since we need to determine
1540 // whether the PHI is a successor of the range check MBB or the jump table MBB
1541 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1542 // Lower header first, if it wasn't already lowered
1543 if (!SDB->JTCases[i].first.Emitted) {
1544 // Set the current basic block to the mbb we wish to insert the code into
1545 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1546 FuncInfo->InsertPt = FuncInfo->MBB->end();
1548 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1550 CurDAG->setRoot(SDB->getRoot());
1552 CodeGenAndEmitDAG();
1555 // Set the current basic block to the mbb we wish to insert the code into
1556 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1557 FuncInfo->InsertPt = FuncInfo->MBB->end();
1559 SDB->visitJumpTable(SDB->JTCases[i].second);
1560 CurDAG->setRoot(SDB->getRoot());
1562 CodeGenAndEmitDAG();
1565 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1567 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1568 MachineBasicBlock *PHIBB = PHI->getParent();
1569 assert(PHI->isPHI() &&
1570 "This is not a machine PHI node that we are updating!");
1571 // "default" BB. We can go there only from header BB.
1572 if (PHIBB == SDB->JTCases[i].second.Default)
1573 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1574 .addMBB(SDB->JTCases[i].first.HeaderBB);
1575 // JT BB. Just iterate over successors here
1576 if (FuncInfo->MBB->isSuccessor(PHIBB))
1577 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1580 SDB->JTCases.clear();
1582 // If we generated any switch lowering information, build and codegen any
1583 // additional DAGs necessary.
1584 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1585 // Set the current basic block to the mbb we wish to insert the code into
1586 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1587 FuncInfo->InsertPt = FuncInfo->MBB->end();
1589 // Determine the unique successors.
1590 SmallVector<MachineBasicBlock *, 2> Succs;
1591 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1592 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1593 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1595 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1596 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1597 CurDAG->setRoot(SDB->getRoot());
1599 CodeGenAndEmitDAG();
1601 // Remember the last block, now that any splitting is done, for use in
1602 // populating PHI nodes in successors.
1603 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1605 // Handle any PHI nodes in successors of this chunk, as if we were coming
1606 // from the original BB before switch expansion. Note that PHI nodes can
1607 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1608 // handle them the right number of times.
1609 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1610 FuncInfo->MBB = Succs[i];
1611 FuncInfo->InsertPt = FuncInfo->MBB->end();
1612 // FuncInfo->MBB may have been removed from the CFG if a branch was
1614 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1615 for (MachineBasicBlock::iterator
1616 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1617 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1618 MachineInstrBuilder PHI(*MF, MBBI);
1619 // This value for this PHI node is recorded in PHINodesToUpdate.
1620 for (unsigned pn = 0; ; ++pn) {
1621 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1622 "Didn't find PHI entry!");
1623 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1624 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1632 SDB->SwitchCases.clear();
1636 /// Create the scheduler. If a specific scheduler was specified
1637 /// via the SchedulerRegistry, use it, otherwise select the
1638 /// one preferred by the target.
1640 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1641 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1645 RegisterScheduler::setDefault(Ctor);
1648 return Ctor(this, OptLevel);
1651 //===----------------------------------------------------------------------===//
1652 // Helper functions used by the generated instruction selector.
1653 //===----------------------------------------------------------------------===//
1654 // Calls to these methods are generated by tblgen.
1656 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1657 /// the dag combiner simplified the 255, we still want to match. RHS is the
1658 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1659 /// specified in the .td file (e.g. 255).
1660 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1661 int64_t DesiredMaskS) const {
1662 const APInt &ActualMask = RHS->getAPIntValue();
1663 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1665 // If the actual mask exactly matches, success!
1666 if (ActualMask == DesiredMask)
1669 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1670 if (ActualMask.intersects(~DesiredMask))
1673 // Otherwise, the DAG Combiner may have proven that the value coming in is
1674 // either already zero or is not demanded. Check for known zero input bits.
1675 APInt NeededMask = DesiredMask & ~ActualMask;
1676 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1679 // TODO: check to see if missing bits are just not demanded.
1681 // Otherwise, this pattern doesn't match.
1685 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1686 /// the dag combiner simplified the 255, we still want to match. RHS is the
1687 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1688 /// specified in the .td file (e.g. 255).
1689 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1690 int64_t DesiredMaskS) const {
1691 const APInt &ActualMask = RHS->getAPIntValue();
1692 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1694 // If the actual mask exactly matches, success!
1695 if (ActualMask == DesiredMask)
1698 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1699 if (ActualMask.intersects(~DesiredMask))
1702 // Otherwise, the DAG Combiner may have proven that the value coming in is
1703 // either already zero or is not demanded. Check for known zero input bits.
1704 APInt NeededMask = DesiredMask & ~ActualMask;
1706 APInt KnownZero, KnownOne;
1707 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1709 // If all the missing bits in the or are already known to be set, match!
1710 if ((NeededMask & KnownOne) == NeededMask)
1713 // TODO: check to see if missing bits are just not demanded.
1715 // Otherwise, this pattern doesn't match.
1720 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1721 /// by tblgen. Others should not call it.
1722 void SelectionDAGISel::
1723 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1724 std::vector<SDValue> InOps;
1725 std::swap(InOps, Ops);
1727 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1728 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1729 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1730 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1732 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1733 if (InOps[e-1].getValueType() == MVT::Glue)
1734 --e; // Don't process a glue operand if it is here.
1737 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1738 if (!InlineAsm::isMemKind(Flags)) {
1739 // Just skip over this operand, copying the operands verbatim.
1740 Ops.insert(Ops.end(), InOps.begin()+i,
1741 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1742 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1744 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1745 "Memory operand with multiple values?");
1747 unsigned TiedToOperand;
1748 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1749 // We need the constraint ID from the operand this is tied to.
1750 unsigned CurOp = InlineAsm::Op_FirstOperand;
1751 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1752 for (; TiedToOperand; --TiedToOperand) {
1753 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1754 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1758 // Otherwise, this is a memory operand. Ask the target to select it.
1759 std::vector<SDValue> SelOps;
1760 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1761 InlineAsm::getMemoryConstraintID(Flags),
1763 report_fatal_error("Could not match memory address. Inline asm"
1766 // Add this to the output node.
1768 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1769 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1770 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1775 // Add the glue input back if present.
1776 if (e != InOps.size())
1777 Ops.push_back(InOps.back());
1780 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1783 static SDNode *findGlueUse(SDNode *N) {
1784 unsigned FlagResNo = N->getNumValues()-1;
1785 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1786 SDUse &Use = I.getUse();
1787 if (Use.getResNo() == FlagResNo)
1788 return Use.getUser();
1793 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1794 /// This function recursively traverses up the operand chain, ignoring
1796 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1797 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1798 bool IgnoreChains) {
1799 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1800 // greater than all of its (recursive) operands. If we scan to a point where
1801 // 'use' is smaller than the node we're scanning for, then we know we will
1804 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1805 // happen because we scan down to newly selected nodes in the case of glue
1807 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1810 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1811 // won't fail if we scan it again.
1812 if (!Visited.insert(Use).second)
1815 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1816 // Ignore chain uses, they are validated by HandleMergeInputChains.
1817 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1820 SDNode *N = Use->getOperand(i).getNode();
1822 if (Use == ImmedUse || Use == Root)
1823 continue; // We are not looking for immediate use.
1828 // Traverse up the operand chain.
1829 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1835 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1836 /// operand node N of U during instruction selection that starts at Root.
1837 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1838 SDNode *Root) const {
1839 if (OptLevel == CodeGenOpt::None) return false;
1840 return N.hasOneUse();
1843 /// IsLegalToFold - Returns true if the specific operand node N of
1844 /// U can be folded during instruction selection that starts at Root.
1845 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1846 CodeGenOpt::Level OptLevel,
1847 bool IgnoreChains) {
1848 if (OptLevel == CodeGenOpt::None) return false;
1850 // If Root use can somehow reach N through a path that that doesn't contain
1851 // U then folding N would create a cycle. e.g. In the following
1852 // diagram, Root can reach N through X. If N is folded into into Root, then
1853 // X is both a predecessor and a successor of U.
1864 // * indicates nodes to be folded together.
1866 // If Root produces glue, then it gets (even more) interesting. Since it
1867 // will be "glued" together with its glue use in the scheduler, we need to
1868 // check if it might reach N.
1887 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1888 // (call it Fold), then X is a predecessor of GU and a successor of
1889 // Fold. But since Fold and GU are glued together, this will create
1890 // a cycle in the scheduling graph.
1892 // If the node has glue, walk down the graph to the "lowest" node in the
1894 EVT VT = Root->getValueType(Root->getNumValues()-1);
1895 while (VT == MVT::Glue) {
1896 SDNode *GU = findGlueUse(Root);
1900 VT = Root->getValueType(Root->getNumValues()-1);
1902 // If our query node has a glue result with a use, we've walked up it. If
1903 // the user (which has already been selected) has a chain or indirectly uses
1904 // the chain, our WalkChainUsers predicate will not consider it. Because of
1905 // this, we cannot ignore chains in this predicate.
1906 IgnoreChains = false;
1910 SmallPtrSet<SDNode*, 16> Visited;
1911 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1914 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1915 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1916 SelectInlineAsmMemoryOperands(Ops);
1918 const EVT VTs[] = {MVT::Other, MVT::Glue};
1919 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1921 return New.getNode();
1925 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1927 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1928 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1930 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1931 SDValue New = CurDAG->getCopyFromReg(
1932 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1934 return New.getNode();
1938 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1940 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1941 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1942 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1943 Op->getOperand(2).getValueType());
1944 SDValue New = CurDAG->getCopyToReg(
1945 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
1947 return New.getNode();
1952 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1953 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1956 /// GetVBR - decode a vbr encoding whose top bit is set.
1957 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1958 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1959 assert(Val >= 128 && "Not a VBR");
1960 Val &= 127; // Remove first vbr bit.
1965 NextBits = MatcherTable[Idx++];
1966 Val |= (NextBits&127) << Shift;
1968 } while (NextBits & 128);
1974 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1975 /// interior glue and chain results to use the new glue and chain results.
1976 void SelectionDAGISel::
1977 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1978 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1980 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1981 bool isMorphNodeTo) {
1982 SmallVector<SDNode*, 4> NowDeadNodes;
1984 // Now that all the normal results are replaced, we replace the chain and
1985 // glue results if present.
1986 if (!ChainNodesMatched.empty()) {
1987 assert(InputChain.getNode() &&
1988 "Matched input chains but didn't produce a chain");
1989 // Loop over all of the nodes we matched that produced a chain result.
1990 // Replace all the chain results with the final chain we ended up with.
1991 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1992 SDNode *ChainNode = ChainNodesMatched[i];
1994 // If this node was already deleted, don't look at it.
1995 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1998 // Don't replace the results of the root node if we're doing a
2000 if (ChainNode == NodeToMatch && isMorphNodeTo)
2003 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2004 if (ChainVal.getValueType() == MVT::Glue)
2005 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2006 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2007 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2009 // If the node became dead and we haven't already seen it, delete it.
2010 if (ChainNode->use_empty() &&
2011 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2012 NowDeadNodes.push_back(ChainNode);
2016 // If the result produces glue, update any glue results in the matched
2017 // pattern with the glue result.
2018 if (InputGlue.getNode()) {
2019 // Handle any interior nodes explicitly marked.
2020 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2021 SDNode *FRN = GlueResultNodesMatched[i];
2023 // If this node was already deleted, don't look at it.
2024 if (FRN->getOpcode() == ISD::DELETED_NODE)
2027 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2028 "Doesn't have a glue result");
2029 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2032 // If the node became dead and we haven't already seen it, delete it.
2033 if (FRN->use_empty() &&
2034 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2035 NowDeadNodes.push_back(FRN);
2039 if (!NowDeadNodes.empty())
2040 CurDAG->RemoveDeadNodes(NowDeadNodes);
2042 DEBUG(dbgs() << "ISEL: Match complete!\n");
2048 CR_LeadsToInteriorNode
2051 /// WalkChainUsers - Walk down the users of the specified chained node that is
2052 /// part of the pattern we're matching, looking at all of the users we find.
2053 /// This determines whether something is an interior node, whether we have a
2054 /// non-pattern node in between two pattern nodes (which prevent folding because
2055 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2056 /// between pattern nodes (in which case the TF becomes part of the pattern).
2058 /// The walk we do here is guaranteed to be small because we quickly get down to
2059 /// already selected nodes "below" us.
2061 WalkChainUsers(const SDNode *ChainedNode,
2062 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2063 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2064 ChainResult Result = CR_Simple;
2066 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2067 E = ChainedNode->use_end(); UI != E; ++UI) {
2068 // Make sure the use is of the chain, not some other value we produce.
2069 if (UI.getUse().getValueType() != MVT::Other) continue;
2073 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2076 // If we see an already-selected machine node, then we've gone beyond the
2077 // pattern that we're selecting down into the already selected chunk of the
2079 unsigned UserOpcode = User->getOpcode();
2080 if (User->isMachineOpcode() ||
2081 UserOpcode == ISD::CopyToReg ||
2082 UserOpcode == ISD::CopyFromReg ||
2083 UserOpcode == ISD::INLINEASM ||
2084 UserOpcode == ISD::EH_LABEL ||
2085 UserOpcode == ISD::LIFETIME_START ||
2086 UserOpcode == ISD::LIFETIME_END) {
2087 // If their node ID got reset to -1 then they've already been selected.
2088 // Treat them like a MachineOpcode.
2089 if (User->getNodeId() == -1)
2093 // If we have a TokenFactor, we handle it specially.
2094 if (User->getOpcode() != ISD::TokenFactor) {
2095 // If the node isn't a token factor and isn't part of our pattern, then it
2096 // must be a random chained node in between two nodes we're selecting.
2097 // This happens when we have something like:
2102 // Because we structurally match the load/store as a read/modify/write,
2103 // but the call is chained between them. We cannot fold in this case
2104 // because it would induce a cycle in the graph.
2105 if (!std::count(ChainedNodesInPattern.begin(),
2106 ChainedNodesInPattern.end(), User))
2107 return CR_InducesCycle;
2109 // Otherwise we found a node that is part of our pattern. For example in:
2113 // This would happen when we're scanning down from the load and see the
2114 // store as a user. Record that there is a use of ChainedNode that is
2115 // part of the pattern and keep scanning uses.
2116 Result = CR_LeadsToInteriorNode;
2117 InteriorChainedNodes.push_back(User);
2121 // If we found a TokenFactor, there are two cases to consider: first if the
2122 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2123 // uses of the TF are in our pattern) we just want to ignore it. Second,
2124 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2130 // | \ DAG's like cheese
2133 // [TokenFactor] [Op]
2140 // In this case, the TokenFactor becomes part of our match and we rewrite it
2141 // as a new TokenFactor.
2143 // To distinguish these two cases, do a recursive walk down the uses.
2144 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2146 // If the uses of the TokenFactor are just already-selected nodes, ignore
2147 // it, it is "below" our pattern.
2149 case CR_InducesCycle:
2150 // If the uses of the TokenFactor lead to nodes that are not part of our
2151 // pattern that are not selected, folding would turn this into a cycle,
2153 return CR_InducesCycle;
2154 case CR_LeadsToInteriorNode:
2155 break; // Otherwise, keep processing.
2158 // Okay, we know we're in the interesting interior case. The TokenFactor
2159 // is now going to be considered part of the pattern so that we rewrite its
2160 // uses (it may have uses that are not part of the pattern) with the
2161 // ultimate chain result of the generated code. We will also add its chain
2162 // inputs as inputs to the ultimate TokenFactor we create.
2163 Result = CR_LeadsToInteriorNode;
2164 ChainedNodesInPattern.push_back(User);
2165 InteriorChainedNodes.push_back(User);
2172 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2173 /// operation for when the pattern matched at least one node with a chains. The
2174 /// input vector contains a list of all of the chained nodes that we match. We
2175 /// must determine if this is a valid thing to cover (i.e. matching it won't
2176 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2177 /// be used as the input node chain for the generated nodes.
2179 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2180 SelectionDAG *CurDAG) {
2181 // Walk all of the chained nodes we've matched, recursively scanning down the
2182 // users of the chain result. This adds any TokenFactor nodes that are caught
2183 // in between chained nodes to the chained and interior nodes list.
2184 SmallVector<SDNode*, 3> InteriorChainedNodes;
2185 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2186 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2187 InteriorChainedNodes) == CR_InducesCycle)
2188 return SDValue(); // Would induce a cycle.
2191 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2192 // that we are interested in. Form our input TokenFactor node.
2193 SmallVector<SDValue, 3> InputChains;
2194 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2195 // Add the input chain of this node to the InputChains list (which will be
2196 // the operands of the generated TokenFactor) if it's not an interior node.
2197 SDNode *N = ChainNodesMatched[i];
2198 if (N->getOpcode() != ISD::TokenFactor) {
2199 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2202 // Otherwise, add the input chain.
2203 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2204 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2205 InputChains.push_back(InChain);
2209 // If we have a token factor, we want to add all inputs of the token factor
2210 // that are not part of the pattern we're matching.
2211 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2212 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2213 N->getOperand(op).getNode()))
2214 InputChains.push_back(N->getOperand(op));
2218 if (InputChains.size() == 1)
2219 return InputChains[0];
2220 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2221 MVT::Other, InputChains);
2224 /// MorphNode - Handle morphing a node in place for the selector.
2225 SDNode *SelectionDAGISel::
2226 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2227 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2228 // It is possible we're using MorphNodeTo to replace a node with no
2229 // normal results with one that has a normal result (or we could be
2230 // adding a chain) and the input could have glue and chains as well.
2231 // In this case we need to shift the operands down.
2232 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2233 // than the old isel though.
2234 int OldGlueResultNo = -1, OldChainResultNo = -1;
2236 unsigned NTMNumResults = Node->getNumValues();
2237 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2238 OldGlueResultNo = NTMNumResults-1;
2239 if (NTMNumResults != 1 &&
2240 Node->getValueType(NTMNumResults-2) == MVT::Other)
2241 OldChainResultNo = NTMNumResults-2;
2242 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2243 OldChainResultNo = NTMNumResults-1;
2245 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2246 // that this deletes operands of the old node that become dead.
2247 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2249 // MorphNodeTo can operate in two ways: if an existing node with the
2250 // specified operands exists, it can just return it. Otherwise, it
2251 // updates the node in place to have the requested operands.
2253 // If we updated the node in place, reset the node ID. To the isel,
2254 // this should be just like a newly allocated machine node.
2258 unsigned ResNumResults = Res->getNumValues();
2259 // Move the glue if needed.
2260 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2261 (unsigned)OldGlueResultNo != ResNumResults-1)
2262 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2263 SDValue(Res, ResNumResults-1));
2265 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2268 // Move the chain reference if needed.
2269 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2270 (unsigned)OldChainResultNo != ResNumResults-1)
2271 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2272 SDValue(Res, ResNumResults-1));
2274 // Otherwise, no replacement happened because the node already exists. Replace
2275 // Uses of the old node with the new one.
2277 CurDAG->ReplaceAllUsesWith(Node, Res);
2282 /// CheckSame - Implements OP_CheckSame.
2283 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2284 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2286 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2287 // Accept if it is exactly the same as a previously recorded node.
2288 unsigned RecNo = MatcherTable[MatcherIndex++];
2289 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2290 return N == RecordedNodes[RecNo].first;
2293 /// CheckChildSame - Implements OP_CheckChildXSame.
2294 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2295 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2297 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2299 if (ChildNo >= N.getNumOperands())
2300 return false; // Match fails if out of range child #.
2301 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2305 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2306 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2307 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2308 const SelectionDAGISel &SDISel) {
2309 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2312 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2313 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2314 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2315 const SelectionDAGISel &SDISel, SDNode *N) {
2316 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2319 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2320 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2322 uint16_t Opc = MatcherTable[MatcherIndex++];
2323 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2324 return N->getOpcode() == Opc;
2327 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2328 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2329 SDValue N, const TargetLowering *TLI) {
2330 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2331 if (N.getValueType() == VT) return true;
2333 // Handle the case when VT is iPTR.
2334 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2337 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2338 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2339 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2340 if (ChildNo >= N.getNumOperands())
2341 return false; // Match fails if out of range child #.
2342 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2345 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2346 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2348 return cast<CondCodeSDNode>(N)->get() ==
2349 (ISD::CondCode)MatcherTable[MatcherIndex++];
2352 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2353 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2354 SDValue N, const TargetLowering *TLI) {
2355 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2356 if (cast<VTSDNode>(N)->getVT() == VT)
2359 // Handle the case when VT is iPTR.
2360 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2363 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2364 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2366 int64_t Val = MatcherTable[MatcherIndex++];
2368 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2370 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2371 return C && C->getSExtValue() == Val;
2374 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2375 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2376 SDValue N, unsigned ChildNo) {
2377 if (ChildNo >= N.getNumOperands())
2378 return false; // Match fails if out of range child #.
2379 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2382 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2383 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2384 SDValue N, const SelectionDAGISel &SDISel) {
2385 int64_t Val = MatcherTable[MatcherIndex++];
2387 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2389 if (N->getOpcode() != ISD::AND) return false;
2391 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2392 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2395 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2396 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2397 SDValue N, const SelectionDAGISel &SDISel) {
2398 int64_t Val = MatcherTable[MatcherIndex++];
2400 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2402 if (N->getOpcode() != ISD::OR) return false;
2404 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2405 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2408 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2409 /// scope, evaluate the current node. If the current predicate is known to
2410 /// fail, set Result=true and return anything. If the current predicate is
2411 /// known to pass, set Result=false and return the MatcherIndex to continue
2412 /// with. If the current predicate is unknown, set Result=false and return the
2413 /// MatcherIndex to continue with.
2414 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2415 unsigned Index, SDValue N,
2417 const SelectionDAGISel &SDISel,
2418 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2419 switch (Table[Index++]) {
2422 return Index-1; // Could not evaluate this predicate.
2423 case SelectionDAGISel::OPC_CheckSame:
2424 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2426 case SelectionDAGISel::OPC_CheckChild0Same:
2427 case SelectionDAGISel::OPC_CheckChild1Same:
2428 case SelectionDAGISel::OPC_CheckChild2Same:
2429 case SelectionDAGISel::OPC_CheckChild3Same:
2430 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2431 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2433 case SelectionDAGISel::OPC_CheckPatternPredicate:
2434 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2436 case SelectionDAGISel::OPC_CheckPredicate:
2437 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2439 case SelectionDAGISel::OPC_CheckOpcode:
2440 Result = !::CheckOpcode(Table, Index, N.getNode());
2442 case SelectionDAGISel::OPC_CheckType:
2443 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2445 case SelectionDAGISel::OPC_CheckChild0Type:
2446 case SelectionDAGISel::OPC_CheckChild1Type:
2447 case SelectionDAGISel::OPC_CheckChild2Type:
2448 case SelectionDAGISel::OPC_CheckChild3Type:
2449 case SelectionDAGISel::OPC_CheckChild4Type:
2450 case SelectionDAGISel::OPC_CheckChild5Type:
2451 case SelectionDAGISel::OPC_CheckChild6Type:
2452 case SelectionDAGISel::OPC_CheckChild7Type:
2453 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2455 SelectionDAGISel::OPC_CheckChild0Type);
2457 case SelectionDAGISel::OPC_CheckCondCode:
2458 Result = !::CheckCondCode(Table, Index, N);
2460 case SelectionDAGISel::OPC_CheckValueType:
2461 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2463 case SelectionDAGISel::OPC_CheckInteger:
2464 Result = !::CheckInteger(Table, Index, N);
2466 case SelectionDAGISel::OPC_CheckChild0Integer:
2467 case SelectionDAGISel::OPC_CheckChild1Integer:
2468 case SelectionDAGISel::OPC_CheckChild2Integer:
2469 case SelectionDAGISel::OPC_CheckChild3Integer:
2470 case SelectionDAGISel::OPC_CheckChild4Integer:
2471 Result = !::CheckChildInteger(Table, Index, N,
2472 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2474 case SelectionDAGISel::OPC_CheckAndImm:
2475 Result = !::CheckAndImm(Table, Index, N, SDISel);
2477 case SelectionDAGISel::OPC_CheckOrImm:
2478 Result = !::CheckOrImm(Table, Index, N, SDISel);
2486 /// FailIndex - If this match fails, this is the index to continue with.
2489 /// NodeStack - The node stack when the scope was formed.
2490 SmallVector<SDValue, 4> NodeStack;
2492 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2493 unsigned NumRecordedNodes;
2495 /// NumMatchedMemRefs - The number of matched memref entries.
2496 unsigned NumMatchedMemRefs;
2498 /// InputChain/InputGlue - The current chain/glue
2499 SDValue InputChain, InputGlue;
2501 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2502 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2505 /// \\brief A DAG update listener to keep the matching state
2506 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2507 /// change the DAG while matching. X86 addressing mode matcher is an example
2509 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2511 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2512 SmallVectorImpl<MatchScope> &MatchScopes;
2514 MatchStateUpdater(SelectionDAG &DAG,
2515 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2516 SmallVectorImpl<MatchScope> &MS) :
2517 SelectionDAG::DAGUpdateListener(DAG),
2518 RecordedNodes(RN), MatchScopes(MS) { }
2520 void NodeDeleted(SDNode *N, SDNode *E) override {
2521 // Some early-returns here to avoid the search if we deleted the node or
2522 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2523 // do, so it's unnecessary to update matching state at that point).
2524 // Neither of these can occur currently because we only install this
2525 // update listener during matching a complex patterns.
2526 if (!E || E->isMachineOpcode())
2528 // Performing linear search here does not matter because we almost never
2529 // run this code. You'd have to have a CSE during complex pattern
2531 for (auto &I : RecordedNodes)
2532 if (I.first.getNode() == N)
2535 for (auto &I : MatchScopes)
2536 for (auto &J : I.NodeStack)
2537 if (J.getNode() == N)
2543 SDNode *SelectionDAGISel::
2544 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2545 unsigned TableSize) {
2546 // FIXME: Should these even be selected? Handle these cases in the caller?
2547 switch (NodeToMatch->getOpcode()) {
2550 case ISD::EntryToken: // These nodes remain the same.
2551 case ISD::BasicBlock:
2553 case ISD::RegisterMask:
2554 case ISD::HANDLENODE:
2555 case ISD::MDNODE_SDNODE:
2556 case ISD::TargetConstant:
2557 case ISD::TargetConstantFP:
2558 case ISD::TargetConstantPool:
2559 case ISD::TargetFrameIndex:
2560 case ISD::TargetExternalSymbol:
2561 case ISD::TargetBlockAddress:
2562 case ISD::TargetJumpTable:
2563 case ISD::TargetGlobalTLSAddress:
2564 case ISD::TargetGlobalAddress:
2565 case ISD::TokenFactor:
2566 case ISD::CopyFromReg:
2567 case ISD::CopyToReg:
2569 case ISD::LIFETIME_START:
2570 case ISD::LIFETIME_END:
2571 NodeToMatch->setNodeId(-1); // Mark selected.
2573 case ISD::AssertSext:
2574 case ISD::AssertZext:
2575 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2576 NodeToMatch->getOperand(0));
2578 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2579 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2580 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2581 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2584 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2586 // Set up the node stack with NodeToMatch as the only node on the stack.
2587 SmallVector<SDValue, 8> NodeStack;
2588 SDValue N = SDValue(NodeToMatch, 0);
2589 NodeStack.push_back(N);
2591 // MatchScopes - Scopes used when matching, if a match failure happens, this
2592 // indicates where to continue checking.
2593 SmallVector<MatchScope, 8> MatchScopes;
2595 // RecordedNodes - This is the set of nodes that have been recorded by the
2596 // state machine. The second value is the parent of the node, or null if the
2597 // root is recorded.
2598 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2600 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2602 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2604 // These are the current input chain and glue for use when generating nodes.
2605 // Various Emit operations change these. For example, emitting a copytoreg
2606 // uses and updates these.
2607 SDValue InputChain, InputGlue;
2609 // ChainNodesMatched - If a pattern matches nodes that have input/output
2610 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2611 // which ones they are. The result is captured into this list so that we can
2612 // update the chain results when the pattern is complete.
2613 SmallVector<SDNode*, 3> ChainNodesMatched;
2614 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2616 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2617 NodeToMatch->dump(CurDAG);
2620 // Determine where to start the interpreter. Normally we start at opcode #0,
2621 // but if the state machine starts with an OPC_SwitchOpcode, then we
2622 // accelerate the first lookup (which is guaranteed to be hot) with the
2623 // OpcodeOffset table.
2624 unsigned MatcherIndex = 0;
2626 if (!OpcodeOffset.empty()) {
2627 // Already computed the OpcodeOffset table, just index into it.
2628 if (N.getOpcode() < OpcodeOffset.size())
2629 MatcherIndex = OpcodeOffset[N.getOpcode()];
2630 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2632 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2633 // Otherwise, the table isn't computed, but the state machine does start
2634 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2635 // is the first time we're selecting an instruction.
2638 // Get the size of this case.
2639 unsigned CaseSize = MatcherTable[Idx++];
2641 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2642 if (CaseSize == 0) break;
2644 // Get the opcode, add the index to the table.
2645 uint16_t Opc = MatcherTable[Idx++];
2646 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2647 if (Opc >= OpcodeOffset.size())
2648 OpcodeOffset.resize((Opc+1)*2);
2649 OpcodeOffset[Opc] = Idx;
2653 // Okay, do the lookup for the first opcode.
2654 if (N.getOpcode() < OpcodeOffset.size())
2655 MatcherIndex = OpcodeOffset[N.getOpcode()];
2659 assert(MatcherIndex < TableSize && "Invalid index");
2661 unsigned CurrentOpcodeIndex = MatcherIndex;
2663 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2666 // Okay, the semantics of this operation are that we should push a scope
2667 // then evaluate the first child. However, pushing a scope only to have
2668 // the first check fail (which then pops it) is inefficient. If we can
2669 // determine immediately that the first check (or first several) will
2670 // immediately fail, don't even bother pushing a scope for them.
2674 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2675 if (NumToSkip & 128)
2676 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2677 // Found the end of the scope with no match.
2678 if (NumToSkip == 0) {
2683 FailIndex = MatcherIndex+NumToSkip;
2685 unsigned MatcherIndexOfPredicate = MatcherIndex;
2686 (void)MatcherIndexOfPredicate; // silence warning.
2688 // If we can't evaluate this predicate without pushing a scope (e.g. if
2689 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2690 // push the scope and evaluate the full predicate chain.
2692 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2693 Result, *this, RecordedNodes);
2697 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2698 << "index " << MatcherIndexOfPredicate
2699 << ", continuing at " << FailIndex << "\n");
2700 ++NumDAGIselRetries;
2702 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2703 // move to the next case.
2704 MatcherIndex = FailIndex;
2707 // If the whole scope failed to match, bail.
2708 if (FailIndex == 0) break;
2710 // Push a MatchScope which indicates where to go if the first child fails
2712 MatchScope NewEntry;
2713 NewEntry.FailIndex = FailIndex;
2714 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2715 NewEntry.NumRecordedNodes = RecordedNodes.size();
2716 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2717 NewEntry.InputChain = InputChain;
2718 NewEntry.InputGlue = InputGlue;
2719 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2720 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2721 MatchScopes.push_back(NewEntry);
2724 case OPC_RecordNode: {
2725 // Remember this node, it may end up being an operand in the pattern.
2726 SDNode *Parent = nullptr;
2727 if (NodeStack.size() > 1)
2728 Parent = NodeStack[NodeStack.size()-2].getNode();
2729 RecordedNodes.push_back(std::make_pair(N, Parent));
2733 case OPC_RecordChild0: case OPC_RecordChild1:
2734 case OPC_RecordChild2: case OPC_RecordChild3:
2735 case OPC_RecordChild4: case OPC_RecordChild5:
2736 case OPC_RecordChild6: case OPC_RecordChild7: {
2737 unsigned ChildNo = Opcode-OPC_RecordChild0;
2738 if (ChildNo >= N.getNumOperands())
2739 break; // Match fails if out of range child #.
2741 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2745 case OPC_RecordMemRef:
2746 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2749 case OPC_CaptureGlueInput:
2750 // If the current node has an input glue, capture it in InputGlue.
2751 if (N->getNumOperands() != 0 &&
2752 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2753 InputGlue = N->getOperand(N->getNumOperands()-1);
2756 case OPC_MoveChild: {
2757 unsigned ChildNo = MatcherTable[MatcherIndex++];
2758 if (ChildNo >= N.getNumOperands())
2759 break; // Match fails if out of range child #.
2760 N = N.getOperand(ChildNo);
2761 NodeStack.push_back(N);
2765 case OPC_MoveParent:
2766 // Pop the current node off the NodeStack.
2767 NodeStack.pop_back();
2768 assert(!NodeStack.empty() && "Node stack imbalance!");
2769 N = NodeStack.back();
2773 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2776 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2777 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2778 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2779 Opcode-OPC_CheckChild0Same))
2783 case OPC_CheckPatternPredicate:
2784 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2786 case OPC_CheckPredicate:
2787 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2791 case OPC_CheckComplexPat: {
2792 unsigned CPNum = MatcherTable[MatcherIndex++];
2793 unsigned RecNo = MatcherTable[MatcherIndex++];
2794 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2796 // If target can modify DAG during matching, keep the matching state
2798 std::unique_ptr<MatchStateUpdater> MSU;
2799 if (ComplexPatternFuncMutatesDAG())
2800 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2803 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2804 RecordedNodes[RecNo].first, CPNum,
2809 case OPC_CheckOpcode:
2810 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2814 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2818 case OPC_SwitchOpcode: {
2819 unsigned CurNodeOpcode = N.getOpcode();
2820 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2823 // Get the size of this case.
2824 CaseSize = MatcherTable[MatcherIndex++];
2826 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2827 if (CaseSize == 0) break;
2829 uint16_t Opc = MatcherTable[MatcherIndex++];
2830 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2832 // If the opcode matches, then we will execute this case.
2833 if (CurNodeOpcode == Opc)
2836 // Otherwise, skip over this case.
2837 MatcherIndex += CaseSize;
2840 // If no cases matched, bail out.
2841 if (CaseSize == 0) break;
2843 // Otherwise, execute the case we found.
2844 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2845 << " to " << MatcherIndex << "\n");
2849 case OPC_SwitchType: {
2850 MVT CurNodeVT = N.getSimpleValueType();
2851 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2854 // Get the size of this case.
2855 CaseSize = MatcherTable[MatcherIndex++];
2857 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2858 if (CaseSize == 0) break;
2860 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2861 if (CaseVT == MVT::iPTR)
2862 CaseVT = TLI->getPointerTy();
2864 // If the VT matches, then we will execute this case.
2865 if (CurNodeVT == CaseVT)
2868 // Otherwise, skip over this case.
2869 MatcherIndex += CaseSize;
2872 // If no cases matched, bail out.
2873 if (CaseSize == 0) break;
2875 // Otherwise, execute the case we found.
2876 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2877 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2880 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2881 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2882 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2883 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2884 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2885 Opcode-OPC_CheckChild0Type))
2888 case OPC_CheckCondCode:
2889 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2891 case OPC_CheckValueType:
2892 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2895 case OPC_CheckInteger:
2896 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2898 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2899 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2900 case OPC_CheckChild4Integer:
2901 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2902 Opcode-OPC_CheckChild0Integer)) break;
2904 case OPC_CheckAndImm:
2905 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2907 case OPC_CheckOrImm:
2908 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2911 case OPC_CheckFoldableChainNode: {
2912 assert(NodeStack.size() != 1 && "No parent node");
2913 // Verify that all intermediate nodes between the root and this one have
2915 bool HasMultipleUses = false;
2916 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2917 if (!NodeStack[i].hasOneUse()) {
2918 HasMultipleUses = true;
2921 if (HasMultipleUses) break;
2923 // Check to see that the target thinks this is profitable to fold and that
2924 // we can fold it without inducing cycles in the graph.
2925 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2927 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2928 NodeToMatch, OptLevel,
2929 true/*We validate our own chains*/))
2934 case OPC_EmitInteger: {
2935 MVT::SimpleValueType VT =
2936 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2937 int64_t Val = MatcherTable[MatcherIndex++];
2939 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2940 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2941 CurDAG->getTargetConstant(Val, VT), nullptr));
2944 case OPC_EmitRegister: {
2945 MVT::SimpleValueType VT =
2946 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2947 unsigned RegNo = MatcherTable[MatcherIndex++];
2948 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2949 CurDAG->getRegister(RegNo, VT), nullptr));
2952 case OPC_EmitRegister2: {
2953 // For targets w/ more than 256 register names, the register enum
2954 // values are stored in two bytes in the matcher table (just like
2956 MVT::SimpleValueType VT =
2957 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2958 unsigned RegNo = MatcherTable[MatcherIndex++];
2959 RegNo |= MatcherTable[MatcherIndex++] << 8;
2960 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2961 CurDAG->getRegister(RegNo, VT), nullptr));
2965 case OPC_EmitConvertToTarget: {
2966 // Convert from IMM/FPIMM to target version.
2967 unsigned RecNo = MatcherTable[MatcherIndex++];
2968 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2969 SDValue Imm = RecordedNodes[RecNo].first;
2971 if (Imm->getOpcode() == ISD::Constant) {
2972 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2973 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2974 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2975 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2976 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2979 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2983 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2984 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2985 // These are space-optimized forms of OPC_EmitMergeInputChains.
2986 assert(!InputChain.getNode() &&
2987 "EmitMergeInputChains should be the first chain producing node");
2988 assert(ChainNodesMatched.empty() &&
2989 "Should only have one EmitMergeInputChains per match");
2991 // Read all of the chained nodes.
2992 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2993 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2994 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2996 // FIXME: What if other value results of the node have uses not matched
2998 if (ChainNodesMatched.back() != NodeToMatch &&
2999 !RecordedNodes[RecNo].first.hasOneUse()) {
3000 ChainNodesMatched.clear();
3004 // Merge the input chains if they are not intra-pattern references.
3005 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3007 if (!InputChain.getNode())
3008 break; // Failed to merge.
3012 case OPC_EmitMergeInputChains: {
3013 assert(!InputChain.getNode() &&
3014 "EmitMergeInputChains should be the first chain producing node");
3015 // This node gets a list of nodes we matched in the input that have
3016 // chains. We want to token factor all of the input chains to these nodes
3017 // together. However, if any of the input chains is actually one of the
3018 // nodes matched in this pattern, then we have an intra-match reference.
3019 // Ignore these because the newly token factored chain should not refer to
3021 unsigned NumChains = MatcherTable[MatcherIndex++];
3022 assert(NumChains != 0 && "Can't TF zero chains");
3024 assert(ChainNodesMatched.empty() &&
3025 "Should only have one EmitMergeInputChains per match");
3027 // Read all of the chained nodes.
3028 for (unsigned i = 0; i != NumChains; ++i) {
3029 unsigned RecNo = MatcherTable[MatcherIndex++];
3030 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3031 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3033 // FIXME: What if other value results of the node have uses not matched
3035 if (ChainNodesMatched.back() != NodeToMatch &&
3036 !RecordedNodes[RecNo].first.hasOneUse()) {
3037 ChainNodesMatched.clear();
3042 // If the inner loop broke out, the match fails.
3043 if (ChainNodesMatched.empty())
3046 // Merge the input chains if they are not intra-pattern references.
3047 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3049 if (!InputChain.getNode())
3050 break; // Failed to merge.
3055 case OPC_EmitCopyToReg: {
3056 unsigned RecNo = MatcherTable[MatcherIndex++];
3057 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3058 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3060 if (!InputChain.getNode())
3061 InputChain = CurDAG->getEntryNode();
3063 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3064 DestPhysReg, RecordedNodes[RecNo].first,
3067 InputGlue = InputChain.getValue(1);
3071 case OPC_EmitNodeXForm: {
3072 unsigned XFormNo = MatcherTable[MatcherIndex++];
3073 unsigned RecNo = MatcherTable[MatcherIndex++];
3074 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3075 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3076 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3081 case OPC_MorphNodeTo: {
3082 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3083 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3084 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3085 // Get the result VT list.
3086 unsigned NumVTs = MatcherTable[MatcherIndex++];
3087 SmallVector<EVT, 4> VTs;
3088 for (unsigned i = 0; i != NumVTs; ++i) {
3089 MVT::SimpleValueType VT =
3090 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3091 if (VT == MVT::iPTR)
3092 VT = TLI->getPointerTy().SimpleTy;
3096 if (EmitNodeInfo & OPFL_Chain)
3097 VTs.push_back(MVT::Other);
3098 if (EmitNodeInfo & OPFL_GlueOutput)
3099 VTs.push_back(MVT::Glue);
3101 // This is hot code, so optimize the two most common cases of 1 and 2
3104 if (VTs.size() == 1)
3105 VTList = CurDAG->getVTList(VTs[0]);
3106 else if (VTs.size() == 2)
3107 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3109 VTList = CurDAG->getVTList(VTs);
3111 // Get the operand list.
3112 unsigned NumOps = MatcherTable[MatcherIndex++];
3113 SmallVector<SDValue, 8> Ops;
3114 for (unsigned i = 0; i != NumOps; ++i) {
3115 unsigned RecNo = MatcherTable[MatcherIndex++];
3117 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3119 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3120 Ops.push_back(RecordedNodes[RecNo].first);
3123 // If there are variadic operands to add, handle them now.
3124 if (EmitNodeInfo & OPFL_VariadicInfo) {
3125 // Determine the start index to copy from.
3126 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3127 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3128 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3129 "Invalid variadic node");
3130 // Copy all of the variadic operands, not including a potential glue
3132 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3134 SDValue V = NodeToMatch->getOperand(i);
3135 if (V.getValueType() == MVT::Glue) break;
3140 // If this has chain/glue inputs, add them.
3141 if (EmitNodeInfo & OPFL_Chain)
3142 Ops.push_back(InputChain);
3143 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3144 Ops.push_back(InputGlue);
3147 SDNode *Res = nullptr;
3148 if (Opcode != OPC_MorphNodeTo) {
3149 // If this is a normal EmitNode command, just create the new node and
3150 // add the results to the RecordedNodes list.
3151 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3154 // Add all the non-glue/non-chain results to the RecordedNodes list.
3155 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3156 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3157 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3161 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3162 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3164 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3165 // We will visit the equivalent node later.
3166 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3170 // If the node had chain/glue results, update our notion of the current
3172 if (EmitNodeInfo & OPFL_GlueOutput) {
3173 InputGlue = SDValue(Res, VTs.size()-1);
3174 if (EmitNodeInfo & OPFL_Chain)
3175 InputChain = SDValue(Res, VTs.size()-2);
3176 } else if (EmitNodeInfo & OPFL_Chain)
3177 InputChain = SDValue(Res, VTs.size()-1);
3179 // If the OPFL_MemRefs glue is set on this node, slap all of the
3180 // accumulated memrefs onto it.
3182 // FIXME: This is vastly incorrect for patterns with multiple outputs
3183 // instructions that access memory and for ComplexPatterns that match
3185 if (EmitNodeInfo & OPFL_MemRefs) {
3186 // Only attach load or store memory operands if the generated
3187 // instruction may load or store.
3188 const MCInstrDesc &MCID = TII->get(TargetOpc);
3189 bool mayLoad = MCID.mayLoad();
3190 bool mayStore = MCID.mayStore();
3192 unsigned NumMemRefs = 0;
3193 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3194 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3195 if ((*I)->isLoad()) {
3198 } else if ((*I)->isStore()) {
3206 MachineSDNode::mmo_iterator MemRefs =
3207 MF->allocateMemRefsArray(NumMemRefs);
3209 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3210 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3211 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3212 if ((*I)->isLoad()) {
3215 } else if ((*I)->isStore()) {
3223 cast<MachineSDNode>(Res)
3224 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3228 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3229 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3231 // If this was a MorphNodeTo then we're completely done!
3232 if (Opcode == OPC_MorphNodeTo) {
3233 // Update chain and glue uses.
3234 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3235 InputGlue, GlueResultNodesMatched, true);
3242 case OPC_MarkGlueResults: {
3243 unsigned NumNodes = MatcherTable[MatcherIndex++];
3245 // Read and remember all the glue-result nodes.
3246 for (unsigned i = 0; i != NumNodes; ++i) {
3247 unsigned RecNo = MatcherTable[MatcherIndex++];
3249 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3251 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3252 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3257 case OPC_CompleteMatch: {
3258 // The match has been completed, and any new nodes (if any) have been
3259 // created. Patch up references to the matched dag to use the newly
3261 unsigned NumResults = MatcherTable[MatcherIndex++];
3263 for (unsigned i = 0; i != NumResults; ++i) {
3264 unsigned ResSlot = MatcherTable[MatcherIndex++];
3266 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3268 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3269 SDValue Res = RecordedNodes[ResSlot].first;
3271 assert(i < NodeToMatch->getNumValues() &&
3272 NodeToMatch->getValueType(i) != MVT::Other &&
3273 NodeToMatch->getValueType(i) != MVT::Glue &&
3274 "Invalid number of results to complete!");
3275 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3276 NodeToMatch->getValueType(i) == MVT::iPTR ||
3277 Res.getValueType() == MVT::iPTR ||
3278 NodeToMatch->getValueType(i).getSizeInBits() ==
3279 Res.getValueType().getSizeInBits()) &&
3280 "invalid replacement");
3281 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3284 // If the root node defines glue, add it to the glue nodes to update list.
3285 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3286 GlueResultNodesMatched.push_back(NodeToMatch);
3288 // Update chain and glue uses.
3289 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3290 InputGlue, GlueResultNodesMatched, false);
3292 assert(NodeToMatch->use_empty() &&
3293 "Didn't replace all uses of the node?");
3295 // FIXME: We just return here, which interacts correctly with SelectRoot
3296 // above. We should fix this to not return an SDNode* anymore.
3301 // If the code reached this point, then the match failed. See if there is
3302 // another child to try in the current 'Scope', otherwise pop it until we
3303 // find a case to check.
3304 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3305 ++NumDAGIselRetries;
3307 if (MatchScopes.empty()) {
3308 CannotYetSelect(NodeToMatch);
3312 // Restore the interpreter state back to the point where the scope was
3314 MatchScope &LastScope = MatchScopes.back();
3315 RecordedNodes.resize(LastScope.NumRecordedNodes);
3317 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3318 N = NodeStack.back();
3320 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3321 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3322 MatcherIndex = LastScope.FailIndex;
3324 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3326 InputChain = LastScope.InputChain;
3327 InputGlue = LastScope.InputGlue;
3328 if (!LastScope.HasChainNodesMatched)
3329 ChainNodesMatched.clear();
3330 if (!LastScope.HasGlueResultNodesMatched)
3331 GlueResultNodesMatched.clear();
3333 // Check to see what the offset is at the new MatcherIndex. If it is zero
3334 // we have reached the end of this scope, otherwise we have another child
3335 // in the current scope to try.
3336 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3337 if (NumToSkip & 128)
3338 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3340 // If we have another child in this scope to match, update FailIndex and
3342 if (NumToSkip != 0) {
3343 LastScope.FailIndex = MatcherIndex+NumToSkip;
3347 // End of this scope, pop it and try the next child in the containing
3349 MatchScopes.pop_back();
3356 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3358 raw_string_ostream Msg(msg);
3359 Msg << "Cannot select: ";
3361 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3362 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3363 N->getOpcode() != ISD::INTRINSIC_VOID) {
3364 N->printrFull(Msg, CurDAG);
3365 Msg << "\nIn function: " << MF->getName();
3367 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3369 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3370 if (iid < Intrinsic::num_intrinsics)
3371 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3372 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3373 Msg << "target intrinsic %" << TII->getName(iid);
3375 Msg << "unknown intrinsic #" << iid;
3377 report_fatal_error(Msg.str());
3380 char SelectionDAGISel::ID = 0;