1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/CodeGen/DwarfWriter.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetIntrinsicInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetMachine.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/Timer.h"
58 #include "llvm/Support/raw_ostream.h"
63 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
64 cl::desc("Enable verbose messages in the \"fast\" "
65 "instruction selector"));
67 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
68 cl::desc("Enable abort calls when \"fast\" instruction fails"));
70 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
71 cl::desc("Schedule copies of livein registers"),
76 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the first "
80 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before legalize types"));
83 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize"));
86 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before the second "
90 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
91 cl::desc("Pop up a window to show dags before the post legalize types"
92 " dag combine pass"));
94 ViewISelDAGs("view-isel-dags", cl::Hidden,
95 cl::desc("Pop up a window to show isel dags as they are selected"));
97 ViewSchedDAGs("view-sched-dags", cl::Hidden,
98 cl::desc("Pop up a window to show sched dags as they are processed"));
100 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
101 cl::desc("Pop up a window to show SUnit dags after they are processed"));
103 static const bool ViewDAGCombine1 = false,
104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
105 ViewDAGCombine2 = false,
106 ViewDAGCombineLT = false,
107 ViewISelDAGs = false, ViewSchedDAGs = false,
108 ViewSUnitDAGs = false;
111 //===---------------------------------------------------------------------===//
113 /// RegisterScheduler class - Track the registration of instruction schedulers.
115 //===---------------------------------------------------------------------===//
116 MachinePassRegistry RegisterScheduler::Registry;
118 //===---------------------------------------------------------------------===//
120 /// ISHeuristic command line option for instruction schedulers.
122 //===---------------------------------------------------------------------===//
123 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
124 RegisterPassParser<RegisterScheduler> >
125 ISHeuristic("pre-RA-sched",
126 cl::init(&createDefaultScheduler),
127 cl::desc("Instruction schedulers available (before register"
130 static RegisterScheduler
131 defaultListDAGScheduler("default", "Best scheduler for the target",
132 createDefaultScheduler);
135 //===--------------------------------------------------------------------===//
136 /// createDefaultScheduler - This creates an instruction scheduler appropriate
138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
139 CodeGenOpt::Level OptLevel) {
140 const TargetLowering &TLI = IS->getTargetLowering();
142 if (OptLevel == CodeGenOpt::None)
143 return createFastDAGScheduler(IS, OptLevel);
144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
145 return createTDListDAGScheduler(IS, OptLevel);
146 assert(TLI.getSchedulingPreference() ==
147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
148 return createBURRListDAGScheduler(IS, OptLevel);
152 // EmitInstrWithCustomInserter - This method should be implemented by targets
153 // that mark instructions with the 'usesCustomInserter' flag. These
154 // instructions are special in various ways, which require special support to
155 // insert. The specified MachineInstr is created but not inserted into any
156 // basic blocks, and this method is called to expand it into a sequence of
157 // instructions, potentially also creating new basic blocks and control flow.
158 // When new basic blocks are inserted and the edges from MBB to its successors
159 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
161 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
162 MachineBasicBlock *MBB,
163 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
165 dbgs() << "If a target marks an instruction with "
166 "'usesCustomInserter', it must implement "
167 "TargetLowering::EmitInstrWithCustomInserter!";
173 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
174 /// physical register has only a single copy use, then coalesced the copy
176 static void EmitLiveInCopy(MachineBasicBlock *MBB,
177 MachineBasicBlock::iterator &InsertPos,
178 unsigned VirtReg, unsigned PhysReg,
179 const TargetRegisterClass *RC,
180 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
181 const MachineRegisterInfo &MRI,
182 const TargetRegisterInfo &TRI,
183 const TargetInstrInfo &TII) {
184 unsigned NumUses = 0;
185 MachineInstr *UseMI = NULL;
186 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
187 UE = MRI.use_end(); UI != UE; ++UI) {
193 // If the number of uses is not one, or the use is not a move instruction,
194 // don't coalesce. Also, only coalesce away a virtual register to virtual
196 bool Coalesced = false;
197 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
199 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
200 TargetRegisterInfo::isVirtualRegister(DstReg)) {
205 // Now find an ideal location to insert the copy.
206 MachineBasicBlock::iterator Pos = InsertPos;
207 while (Pos != MBB->begin()) {
208 MachineInstr *PrevMI = prior(Pos);
209 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
210 // copyRegToReg might emit multiple instructions to do a copy.
211 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
212 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
213 // This is what the BB looks like right now:
218 // We want to insert "r1025 = mov r1". Inserting this copy below the
219 // move to r1024 makes it impossible for that move to be coalesced.
226 break; // Woot! Found a good location.
230 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
231 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
234 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
236 if (&*InsertPos == UseMI) ++InsertPos;
241 /// EmitLiveInCopies - If this is the first basic block in the function,
242 /// and if it has live ins that need to be copied into vregs, emit the
243 /// copies into the block.
244 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
245 const MachineRegisterInfo &MRI,
246 const TargetRegisterInfo &TRI,
247 const TargetInstrInfo &TII) {
248 if (SchedLiveInCopies) {
249 // Emit the copies at a heuristically-determined location in the block.
250 DenseMap<MachineInstr*, unsigned> CopyRegMap;
251 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
252 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
253 E = MRI.livein_end(); LI != E; ++LI)
255 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
256 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
257 RC, CopyRegMap, MRI, TRI, TII);
260 // Emit the copies into the top of the block.
261 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
262 E = MRI.livein_end(); LI != E; ++LI)
264 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
265 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
266 LI->second, LI->first, RC, RC);
267 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
273 //===----------------------------------------------------------------------===//
274 // SelectionDAGISel code
275 //===----------------------------------------------------------------------===//
277 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
278 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
279 FuncInfo(new FunctionLoweringInfo(TLI)),
280 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
281 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
287 SelectionDAGISel::~SelectionDAGISel() {
293 unsigned SelectionDAGISel::MakeReg(EVT VT) {
294 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
297 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
298 AU.addRequired<AliasAnalysis>();
299 AU.addPreserved<AliasAnalysis>();
300 AU.addRequired<GCModuleInfo>();
301 AU.addPreserved<GCModuleInfo>();
302 AU.addRequired<DwarfWriter>();
303 AU.addPreserved<DwarfWriter>();
304 MachineFunctionPass::getAnalysisUsage(AU);
307 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
308 Function &Fn = *mf.getFunction();
310 // Do some sanity-checking on the command-line options.
311 assert((!EnableFastISelVerbose || EnableFastISel) &&
312 "-fast-isel-verbose requires -fast-isel");
313 assert((!EnableFastISelAbort || EnableFastISel) &&
314 "-fast-isel-abort requires -fast-isel");
316 // Get alias analysis for load/store combining.
317 AA = &getAnalysis<AliasAnalysis>();
320 const TargetInstrInfo &TII = *TM.getInstrInfo();
321 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
324 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
327 RegInfo = &MF->getRegInfo();
328 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
330 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
331 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
332 CurDAG->init(*MF, MMI, DW);
333 FuncInfo->set(Fn, *MF, EnableFastISel);
336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
339 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
341 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
343 // If the first basic block in the function has live ins that need to be
344 // copied into vregs, emit the copies into the top of the block before
345 // emitting the code for the block.
346 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
348 // Add function live-ins to entry block live-in set.
349 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
350 E = RegInfo->livein_end(); I != E; ++I)
351 MF->begin()->addLiveIn(I->first);
354 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
355 "Not all catch info was assigned to a landing pad!");
363 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
364 /// attached with this instruction.
365 static void SetDebugLoc(unsigned MDDbgKind, Instruction *I,
366 SelectionDAGBuilder *SDB,
367 FastISel *FastIS, MachineFunction *MF) {
368 if (isa<DbgInfoIntrinsic>(I)) return;
370 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) {
371 DILocation DILoc(Dbg);
372 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
374 SDB->setCurDebugLoc(Loc);
377 FastIS->setCurDebugLoc(Loc);
379 // If the function doesn't have a default debug location yet, set
380 // it. This is kind of a hack.
381 if (MF->getDefaultDebugLoc().isUnknown())
382 MF->setDefaultDebugLoc(Loc);
386 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
387 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
388 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc());
390 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc());
393 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
394 BasicBlock::iterator Begin,
395 BasicBlock::iterator End,
397 SDB->setCurrentBasicBlock(BB);
398 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg");
400 // Lower all of the non-terminator instructions. If a call is emitted
401 // as a tail call, cease emitting nodes for this block.
402 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
403 SetDebugLoc(MDDbgKind, I, SDB, 0, MF);
405 if (!isa<TerminatorInst>(I)) {
408 // Set the current debug location back to "unknown" so that it doesn't
409 // spuriously apply to subsequent instructions.
410 ResetDebugLoc(SDB, 0);
414 if (!SDB->HasTailCall) {
415 // Ensure that all instructions which are used outside of their defining
416 // blocks are available as virtual registers. Invoke is handled elsewhere.
417 for (BasicBlock::iterator I = Begin; I != End; ++I)
418 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
419 SDB->CopyToExportRegsIfNeeded(I);
421 // Handle PHI nodes in successor blocks.
422 if (End == LLVMBB->end()) {
423 HandlePHINodesInSuccessorBlocks(LLVMBB);
425 // Lower the terminator after the copies are emitted.
426 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF);
427 SDB->visit(*LLVMBB->getTerminator());
428 ResetDebugLoc(SDB, 0);
432 // Make sure the root of the DAG is up-to-date.
433 CurDAG->setRoot(SDB->getControlRoot());
435 // Final step, emit the lowered DAG as machine code.
437 HadTailCall = SDB->HasTailCall;
442 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
443 /// nodes from the worklist.
444 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
445 SmallVector<SDNode*, 128> &Worklist;
447 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl) : Worklist(wl) {}
449 virtual void NodeDeleted(SDNode *N, SDNode *E) {
450 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N),
454 virtual void NodeUpdated(SDNode *N) {
460 /// TrivialTruncElim - Eliminate some trivial nops that can result from
461 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
462 static bool TrivialTruncElim(SDValue Op,
463 TargetLowering::TargetLoweringOpt &TLO) {
464 SDValue N0 = Op.getOperand(0);
465 EVT VT = Op.getValueType();
466 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
467 N0.getOpcode() == ISD::SIGN_EXTEND ||
468 N0.getOpcode() == ISD::ANY_EXTEND) &&
469 N0.getOperand(0).getValueType() == VT) {
470 return TLO.CombineTo(Op, N0.getOperand(0));
475 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
476 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
477 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
478 void SelectionDAGISel::ShrinkDemandedOps() {
479 SmallVector<SDNode*, 128> Worklist;
481 // Add all the dag nodes to the worklist.
482 Worklist.reserve(CurDAG->allnodes_size());
483 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
484 E = CurDAG->allnodes_end(); I != E; ++I)
485 Worklist.push_back(I);
491 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
492 while (!Worklist.empty()) {
493 SDNode *N = Worklist.pop_back_val();
495 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
496 CurDAG->DeleteNode(N);
500 // Run ShrinkDemandedOp on scalar binary operations.
501 if (N->getNumValues() == 1 &&
502 N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) {
503 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
504 APInt Demanded = APInt::getAllOnesValue(BitWidth);
505 APInt KnownZero, KnownOne;
506 if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
507 KnownZero, KnownOne, TLO) ||
508 (N->getOpcode() == ISD::TRUNCATE &&
509 TrivialTruncElim(SDValue(N, 0), TLO))) {
511 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N),
513 Worklist.push_back(N);
515 // Replace the old value with the new one.
516 DEBUG(errs() << "\nReplacing ";
517 TLO.Old.getNode()->dump(CurDAG);
518 errs() << "\nWith: ";
519 TLO.New.getNode()->dump(CurDAG);
522 Worklist.push_back(TLO.New.getNode());
524 SDOPsWorkListRemover DeadNodes(Worklist);
525 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
527 if (TLO.Old.getNode()->use_empty()) {
528 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
530 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
531 if (OpNode->hasOneUse()) {
532 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(),
533 OpNode), Worklist.end());
534 Worklist.push_back(OpNode);
538 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(),
539 TLO.Old.getNode()), Worklist.end());
540 CurDAG->DeleteNode(TLO.Old.getNode());
547 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
548 SmallPtrSet<SDNode*, 128> VisitedNodes;
549 SmallVector<SDNode*, 128> Worklist;
551 Worklist.push_back(CurDAG->getRoot().getNode());
558 SDNode *N = Worklist.pop_back_val();
560 // If we've already seen this node, ignore it.
561 if (!VisitedNodes.insert(N))
564 // Otherwise, add all chain operands to the worklist.
565 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
566 if (N->getOperand(i).getValueType() == MVT::Other)
567 Worklist.push_back(N->getOperand(i).getNode());
569 // If this is a CopyToReg with a vreg dest, process it.
570 if (N->getOpcode() != ISD::CopyToReg)
573 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
574 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
577 // Ignore non-scalar or non-integer values.
578 SDValue Src = N->getOperand(2);
579 EVT SrcVT = Src.getValueType();
580 if (!SrcVT.isInteger() || SrcVT.isVector())
583 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
584 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
585 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
587 // Only install this information if it tells us something.
588 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
589 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
590 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
591 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
592 FunctionLoweringInfo::LiveOutInfo &LOI =
593 FuncInfo->LiveOutRegInfo[DestReg];
594 LOI.NumSignBits = NumSignBits;
595 LOI.KnownOne = KnownOne;
596 LOI.KnownZero = KnownZero;
598 } while (!Worklist.empty());
601 void SelectionDAGISel::CodeGenAndEmitDAG() {
602 std::string GroupName;
603 if (TimePassesIsEnabled)
604 GroupName = "Instruction Selection and Scheduling";
605 std::string BlockName;
606 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
607 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
609 BlockName = MF->getFunction()->getNameStr() + ":" +
610 BB->getBasicBlock()->getNameStr();
612 DEBUG(dbgs() << "Initial selection DAG:\n");
613 DEBUG(CurDAG->dump());
615 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
617 // Run the DAG combiner in pre-legalize mode.
618 if (TimePassesIsEnabled) {
619 NamedRegionTimer T("DAG Combining 1", GroupName);
620 CurDAG->Combine(Unrestricted, *AA, OptLevel);
622 CurDAG->Combine(Unrestricted, *AA, OptLevel);
625 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
626 DEBUG(CurDAG->dump());
628 // Second step, hack on the DAG until it only uses operations and types that
629 // the target supports.
630 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
634 if (TimePassesIsEnabled) {
635 NamedRegionTimer T("Type Legalization", GroupName);
636 Changed = CurDAG->LegalizeTypes();
638 Changed = CurDAG->LegalizeTypes();
641 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
642 DEBUG(CurDAG->dump());
645 if (ViewDAGCombineLT)
646 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
648 // Run the DAG combiner in post-type-legalize mode.
649 if (TimePassesIsEnabled) {
650 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
651 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
653 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
656 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
657 DEBUG(CurDAG->dump());
660 if (TimePassesIsEnabled) {
661 NamedRegionTimer T("Vector Legalization", GroupName);
662 Changed = CurDAG->LegalizeVectors();
664 Changed = CurDAG->LegalizeVectors();
668 if (TimePassesIsEnabled) {
669 NamedRegionTimer T("Type Legalization 2", GroupName);
670 CurDAG->LegalizeTypes();
672 CurDAG->LegalizeTypes();
675 if (ViewDAGCombineLT)
676 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
678 // Run the DAG combiner in post-type-legalize mode.
679 if (TimePassesIsEnabled) {
680 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
681 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
683 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
686 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
687 DEBUG(CurDAG->dump());
690 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
692 if (TimePassesIsEnabled) {
693 NamedRegionTimer T("DAG Legalization", GroupName);
694 CurDAG->Legalize(OptLevel);
696 CurDAG->Legalize(OptLevel);
699 DEBUG(dbgs() << "Legalized selection DAG:\n");
700 DEBUG(CurDAG->dump());
702 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
704 // Run the DAG combiner in post-legalize mode.
705 if (TimePassesIsEnabled) {
706 NamedRegionTimer T("DAG Combining 2", GroupName);
707 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
709 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
712 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
713 DEBUG(CurDAG->dump());
715 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
717 if (OptLevel != CodeGenOpt::None) {
719 ComputeLiveOutVRegInfo();
722 // Third, instruction select all of the operations to machine code, adding the
723 // code to the MachineBasicBlock.
724 if (TimePassesIsEnabled) {
725 NamedRegionTimer T("Instruction Selection", GroupName);
726 DoInstructionSelection();
728 DoInstructionSelection();
731 DEBUG(dbgs() << "Selected selection DAG:\n");
732 DEBUG(CurDAG->dump());
734 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
736 // Schedule machine code.
737 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
738 if (TimePassesIsEnabled) {
739 NamedRegionTimer T("Instruction Scheduling", GroupName);
740 Scheduler->Run(CurDAG, BB, BB->end());
742 Scheduler->Run(CurDAG, BB, BB->end());
745 if (ViewSUnitDAGs) Scheduler->viewGraph();
747 // Emit machine code to BB. This can change 'BB' to the last block being
749 if (TimePassesIsEnabled) {
750 NamedRegionTimer T("Instruction Creation", GroupName);
751 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
753 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
756 // Free the scheduler state.
757 if (TimePassesIsEnabled) {
758 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
764 DEBUG(dbgs() << "Selected machine code:\n");
768 void SelectionDAGISel::DoInstructionSelection() {
769 DEBUG(errs() << "===== Instruction selection begins:\n");
773 // Select target instructions for the DAG.
775 // Number all nodes with a topological order and set DAGSize.
776 DAGSize = CurDAG->AssignTopologicalOrder();
778 // Create a dummy node (which is not added to allnodes), that adds
779 // a reference to the root node, preventing it from being deleted,
780 // and tracking any changes of the root.
781 HandleSDNode Dummy(CurDAG->getRoot());
782 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
785 // The AllNodes list is now topological-sorted. Visit the
786 // nodes by starting at the end of the list (the root of the
787 // graph) and preceding back toward the beginning (the entry
789 while (ISelPosition != CurDAG->allnodes_begin()) {
790 SDNode *Node = --ISelPosition;
791 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
792 // but there are currently some corner cases that it misses. Also, this
793 // makes it theoretically possible to disable the DAGCombiner.
794 if (Node->use_empty())
797 SDNode *ResNode = Select(Node);
799 // If node should not be replaced, continue with the next one.
804 ReplaceUses(Node, ResNode);
806 // If after the replacement this node is not used any more,
807 // remove this dead node.
808 if (Node->use_empty()) { // Don't delete EntryToken, etc.
809 ISelUpdater ISU(ISelPosition);
810 CurDAG->RemoveDeadNode(Node, &ISU);
814 CurDAG->setRoot(Dummy.getValue());
816 DEBUG(errs() << "===== Instruction selection ends:\n");
818 PostprocessISelDAG();
820 // FIXME: This shouldn't be needed, remove it.
821 CurDAG->RemoveDeadNodes();
825 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
827 MachineModuleInfo *MMI,
829 const TargetInstrInfo &TII) {
830 // Initialize the Fast-ISel state, if needed.
831 FastISel *FastIS = 0;
833 FastIS = TLI.createFastISel(MF, MMI, DW,
836 FuncInfo->StaticAllocaMap
838 , FuncInfo->CatchInfoLost
842 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg");
844 // Iterate over all basic blocks in the function.
845 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
846 BasicBlock *LLVMBB = &*I;
847 BB = FuncInfo->MBBMap[LLVMBB];
849 BasicBlock::iterator const Begin = LLVMBB->begin();
850 BasicBlock::iterator const End = LLVMBB->end();
851 BasicBlock::iterator BI = Begin;
853 // Lower any arguments needed in this block if this is the entry block.
854 bool SuppressFastISel = false;
855 if (LLVMBB == &Fn.getEntryBlock()) {
856 LowerArguments(LLVMBB);
858 // If any of the arguments has the byval attribute, forgo
859 // fast-isel in the entry block.
862 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
864 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
865 if (EnableFastISelVerbose || EnableFastISelAbort)
866 dbgs() << "FastISel skips entry block due to byval argument\n";
867 SuppressFastISel = true;
873 if (MMI && BB->isLandingPad()) {
874 // Add a label to mark the beginning of the landing pad. Deletion of the
875 // landing pad can thus be detected via the MachineModuleInfo.
876 unsigned LabelID = MMI->addLandingPad(BB);
878 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
879 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID);
881 // Mark exception register as live in.
882 unsigned Reg = TLI.getExceptionAddressRegister();
883 if (Reg) BB->addLiveIn(Reg);
885 // Mark exception selector register as live in.
886 Reg = TLI.getExceptionSelectorRegister();
887 if (Reg) BB->addLiveIn(Reg);
889 // FIXME: Hack around an exception handling flaw (PR1508): the personality
890 // function and list of typeids logically belong to the invoke (or, if you
891 // like, the basic block containing the invoke), and need to be associated
892 // with it in the dwarf exception handling tables. Currently however the
893 // information is provided by an intrinsic (eh.selector) that can be moved
894 // to unexpected places by the optimizers: if the unwind edge is critical,
895 // then breaking it can result in the intrinsics being in the successor of
896 // the landing pad, not the landing pad itself. This results
897 // in exceptions not being caught because no typeids are associated with
898 // the invoke. This may not be the only way things can go wrong, but it
899 // is the only way we try to work around for the moment.
900 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
902 if (Br && Br->isUnconditional()) { // Critical edge?
903 BasicBlock::iterator I, E;
904 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
905 if (isa<EHSelectorInst>(I))
909 // No catch info found - try to extract some from the successor.
910 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
914 // Before doing SelectionDAG ISel, see if FastISel has been requested.
915 if (FastIS && !SuppressFastISel) {
916 // Emit code for any incoming arguments. This must happen before
917 // beginning FastISel on the entry block.
918 if (LLVMBB == &Fn.getEntryBlock()) {
919 CurDAG->setRoot(SDB->getControlRoot());
923 FastIS->startNewBlock(BB);
924 // Do FastISel on as many instructions as possible.
925 for (; BI != End; ++BI) {
926 // Just before the terminator instruction, insert instructions to
927 // feed PHI nodes in successor blocks.
928 if (isa<TerminatorInst>(BI))
929 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
930 ResetDebugLoc(SDB, FastIS);
931 if (EnableFastISelVerbose || EnableFastISelAbort) {
932 dbgs() << "FastISel miss: ";
935 assert(!EnableFastISelAbort &&
936 "FastISel didn't handle a PHI in a successor");
940 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF);
942 // Try to select the instruction with FastISel.
943 if (FastIS->SelectInstruction(BI)) {
944 ResetDebugLoc(SDB, FastIS);
948 // Clear out the debug location so that it doesn't carry over to
949 // unrelated instructions.
950 ResetDebugLoc(SDB, FastIS);
952 // Then handle certain instructions as single-LLVM-Instruction blocks.
953 if (isa<CallInst>(BI)) {
954 if (EnableFastISelVerbose || EnableFastISelAbort) {
955 dbgs() << "FastISel missed call: ";
959 if (!BI->getType()->isVoidTy()) {
960 unsigned &R = FuncInfo->ValueMap[BI];
962 R = FuncInfo->CreateRegForValue(BI);
965 bool HadTailCall = false;
966 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
968 // If the call was emitted as a tail call, we're done with the block.
974 // If the instruction was codegen'd with multiple blocks,
975 // inform the FastISel object where to resume inserting.
976 FastIS->setCurrentBlock(BB);
980 // Otherwise, give up on FastISel for the rest of the block.
981 // For now, be a little lenient about non-branch terminators.
982 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
983 if (EnableFastISelVerbose || EnableFastISelAbort) {
984 dbgs() << "FastISel miss: ";
987 if (EnableFastISelAbort)
988 // The "fast" selector couldn't handle something and bailed.
989 // For the purpose of debugging, just abort.
990 llvm_unreachable("FastISel didn't select the entire block");
996 // Run SelectionDAG instruction selection on the remainder of the block
997 // not handled by FastISel. If FastISel is not run, this is the entire
1001 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
1011 SelectionDAGISel::FinishBasicBlock() {
1013 DEBUG(dbgs() << "Target-post-processed machine code:\n");
1016 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1017 << SDB->PHINodesToUpdate.size() << "\n");
1018 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
1019 dbgs() << "Node " << i << " : ("
1020 << SDB->PHINodesToUpdate[i].first
1021 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
1023 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1024 // PHI nodes in successors.
1025 if (SDB->SwitchCases.empty() &&
1026 SDB->JTCases.empty() &&
1027 SDB->BitTestCases.empty()) {
1028 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1029 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1030 assert(PHI->isPHI() &&
1031 "This is not a machine PHI node that we are updating!");
1032 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1034 PHI->addOperand(MachineOperand::CreateMBB(BB));
1036 SDB->PHINodesToUpdate.clear();
1040 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1041 // Lower header first, if it wasn't already lowered
1042 if (!SDB->BitTestCases[i].Emitted) {
1043 // Set the current basic block to the mbb we wish to insert the code into
1044 BB = SDB->BitTestCases[i].Parent;
1045 SDB->setCurrentBasicBlock(BB);
1047 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
1048 CurDAG->setRoot(SDB->getRoot());
1049 CodeGenAndEmitDAG();
1053 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1054 // Set the current basic block to the mbb we wish to insert the code into
1055 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
1056 SDB->setCurrentBasicBlock(BB);
1059 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1060 SDB->BitTestCases[i].Reg,
1061 SDB->BitTestCases[i].Cases[j]);
1063 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1064 SDB->BitTestCases[i].Reg,
1065 SDB->BitTestCases[i].Cases[j]);
1068 CurDAG->setRoot(SDB->getRoot());
1069 CodeGenAndEmitDAG();
1074 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1075 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1076 MachineBasicBlock *PHIBB = PHI->getParent();
1077 assert(PHI->isPHI() &&
1078 "This is not a machine PHI node that we are updating!");
1079 // This is "default" BB. We have two jumps to it. From "header" BB and
1080 // from last "case" BB.
1081 if (PHIBB == SDB->BitTestCases[i].Default) {
1082 PHI->addOperand(MachineOperand::
1083 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1084 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1085 PHI->addOperand(MachineOperand::
1086 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1087 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1090 // One of "cases" BB.
1091 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1093 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1094 if (cBB->isSuccessor(PHIBB)) {
1095 PHI->addOperand(MachineOperand::
1096 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1097 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1102 SDB->BitTestCases.clear();
1104 // If the JumpTable record is filled in, then we need to emit a jump table.
1105 // Updating the PHI nodes is tricky in this case, since we need to determine
1106 // whether the PHI is a successor of the range check MBB or the jump table MBB
1107 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1108 // Lower header first, if it wasn't already lowered
1109 if (!SDB->JTCases[i].first.Emitted) {
1110 // Set the current basic block to the mbb we wish to insert the code into
1111 BB = SDB->JTCases[i].first.HeaderBB;
1112 SDB->setCurrentBasicBlock(BB);
1114 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1115 CurDAG->setRoot(SDB->getRoot());
1116 CodeGenAndEmitDAG();
1120 // Set the current basic block to the mbb we wish to insert the code into
1121 BB = SDB->JTCases[i].second.MBB;
1122 SDB->setCurrentBasicBlock(BB);
1124 SDB->visitJumpTable(SDB->JTCases[i].second);
1125 CurDAG->setRoot(SDB->getRoot());
1126 CodeGenAndEmitDAG();
1130 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1131 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1132 MachineBasicBlock *PHIBB = PHI->getParent();
1133 assert(PHI->isPHI() &&
1134 "This is not a machine PHI node that we are updating!");
1135 // "default" BB. We can go there only from header BB.
1136 if (PHIBB == SDB->JTCases[i].second.Default) {
1138 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1140 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1142 // JT BB. Just iterate over successors here
1143 if (BB->isSuccessor(PHIBB)) {
1145 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1146 PHI->addOperand(MachineOperand::CreateMBB(BB));
1150 SDB->JTCases.clear();
1152 // If the switch block involved a branch to one of the actual successors, we
1153 // need to update PHI nodes in that block.
1154 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1155 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1156 assert(PHI->isPHI() &&
1157 "This is not a machine PHI node that we are updating!");
1158 if (BB->isSuccessor(PHI->getParent())) {
1159 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1161 PHI->addOperand(MachineOperand::CreateMBB(BB));
1165 // If we generated any switch lowering information, build and codegen any
1166 // additional DAGs necessary.
1167 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1168 // Set the current basic block to the mbb we wish to insert the code into
1169 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1170 SDB->setCurrentBasicBlock(BB);
1173 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1174 CurDAG->setRoot(SDB->getRoot());
1175 CodeGenAndEmitDAG();
1177 // Handle any PHI nodes in successors of this chunk, as if we were coming
1178 // from the original BB before switch expansion. Note that PHI nodes can
1179 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1180 // handle them the right number of times.
1181 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1182 // If new BB's are created during scheduling, the edges may have been
1183 // updated. That is, the edge from ThisBB to BB may have been split and
1184 // BB's predecessor is now another block.
1185 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1186 SDB->EdgeMapping.find(BB);
1187 if (EI != SDB->EdgeMapping.end())
1188 ThisBB = EI->second;
1190 // BB may have been removed from the CFG if a branch was constant folded.
1191 if (ThisBB->isSuccessor(BB)) {
1192 for (MachineBasicBlock::iterator Phi = BB->begin();
1193 Phi != BB->end() && Phi->isPHI();
1195 // This value for this PHI node is recorded in PHINodesToUpdate.
1196 for (unsigned pn = 0; ; ++pn) {
1197 assert(pn != SDB->PHINodesToUpdate.size() &&
1198 "Didn't find PHI entry!");
1199 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1200 Phi->addOperand(MachineOperand::
1201 CreateReg(SDB->PHINodesToUpdate[pn].second,
1203 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1210 // Don't process RHS if same block as LHS.
1211 if (BB == SDB->SwitchCases[i].FalseBB)
1212 SDB->SwitchCases[i].FalseBB = 0;
1214 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1215 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1216 SDB->SwitchCases[i].FalseBB = 0;
1218 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1221 SDB->SwitchCases.clear();
1223 SDB->PHINodesToUpdate.clear();
1227 /// Create the scheduler. If a specific scheduler was specified
1228 /// via the SchedulerRegistry, use it, otherwise select the
1229 /// one preferred by the target.
1231 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1232 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1236 RegisterScheduler::setDefault(Ctor);
1239 return Ctor(this, OptLevel);
1242 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1243 return new ScheduleHazardRecognizer();
1246 //===----------------------------------------------------------------------===//
1247 // Helper functions used by the generated instruction selector.
1248 //===----------------------------------------------------------------------===//
1249 // Calls to these methods are generated by tblgen.
1251 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1252 /// the dag combiner simplified the 255, we still want to match. RHS is the
1253 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1254 /// specified in the .td file (e.g. 255).
1255 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1256 int64_t DesiredMaskS) const {
1257 const APInt &ActualMask = RHS->getAPIntValue();
1258 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1260 // If the actual mask exactly matches, success!
1261 if (ActualMask == DesiredMask)
1264 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1265 if (ActualMask.intersects(~DesiredMask))
1268 // Otherwise, the DAG Combiner may have proven that the value coming in is
1269 // either already zero or is not demanded. Check for known zero input bits.
1270 APInt NeededMask = DesiredMask & ~ActualMask;
1271 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1274 // TODO: check to see if missing bits are just not demanded.
1276 // Otherwise, this pattern doesn't match.
1280 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1281 /// the dag combiner simplified the 255, we still want to match. RHS is the
1282 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1283 /// specified in the .td file (e.g. 255).
1284 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1285 int64_t DesiredMaskS) const {
1286 const APInt &ActualMask = RHS->getAPIntValue();
1287 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1289 // If the actual mask exactly matches, success!
1290 if (ActualMask == DesiredMask)
1293 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1294 if (ActualMask.intersects(~DesiredMask))
1297 // Otherwise, the DAG Combiner may have proven that the value coming in is
1298 // either already zero or is not demanded. Check for known zero input bits.
1299 APInt NeededMask = DesiredMask & ~ActualMask;
1301 APInt KnownZero, KnownOne;
1302 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1304 // If all the missing bits in the or are already known to be set, match!
1305 if ((NeededMask & KnownOne) == NeededMask)
1308 // TODO: check to see if missing bits are just not demanded.
1310 // Otherwise, this pattern doesn't match.
1315 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1316 /// by tblgen. Others should not call it.
1317 void SelectionDAGISel::
1318 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1319 std::vector<SDValue> InOps;
1320 std::swap(InOps, Ops);
1322 Ops.push_back(InOps[0]); // input chain.
1323 Ops.push_back(InOps[1]); // input asm string.
1325 unsigned i = 2, e = InOps.size();
1326 if (InOps[e-1].getValueType() == MVT::Flag)
1327 --e; // Don't process a flag operand if it is here.
1330 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1331 if ((Flags & 7) != 4 /*MEM*/) {
1332 // Just skip over this operand, copying the operands verbatim.
1333 Ops.insert(Ops.end(), InOps.begin()+i,
1334 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1335 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1337 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1338 "Memory operand with multiple values?");
1339 // Otherwise, this is a memory operand. Ask the target to select it.
1340 std::vector<SDValue> SelOps;
1341 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1342 llvm_report_error("Could not match memory address. Inline asm"
1346 // Add this to the output node.
1347 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1349 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1354 // Add the flag input back if present.
1355 if (e != InOps.size())
1356 Ops.push_back(InOps.back());
1359 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1362 static SDNode *findFlagUse(SDNode *N) {
1363 unsigned FlagResNo = N->getNumValues()-1;
1364 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1365 SDUse &Use = I.getUse();
1366 if (Use.getResNo() == FlagResNo)
1367 return Use.getUser();
1372 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1373 /// This function recursively traverses up the operand chain, ignoring
1375 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1377 SmallPtrSet<SDNode*, 16> &Visited) {
1378 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1379 // greater than all of its (recursive) operands. If we scan to a point where
1380 // 'use' is smaller than the node we're scanning for, then we know we will
1383 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1384 // happen because we scan down to newly selected nodes in the case of flag
1386 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1389 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1390 // won't fail if we scan it again.
1391 if (!Visited.insert(Use))
1394 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1395 SDNode *N = Use->getOperand(i).getNode();
1397 if (Use == ImmedUse || Use == Root)
1398 continue; // We are not looking for immediate use.
1403 // Traverse up the operand chain.
1404 if (findNonImmUse(N, Def, ImmedUse, Root, Visited))
1410 /// isNonImmUse - Start searching from Root up the DAG to check is Def can
1411 /// be reached. Return true if that's the case. However, ignore direct uses
1412 /// by ImmedUse (which would be U in the example illustrated in
1413 /// IsLegalToFold) and by Root (which can happen in the store case).
1414 /// FIXME: to be really generic, we should allow direct use by any node
1415 /// that is being folded. But realisticly since we only fold loads which
1416 /// have one non-chain use, we only need to watch out for load/op/store
1417 /// and load/op/cmp case where the root (store / cmp) may reach the load via
1418 /// its chain operand.
1419 static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
1420 SmallPtrSet<SDNode*, 16> Visited;
1421 return findNonImmUse(Root, Def, ImmedUse, Root, Visited);
1424 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1425 /// operand node N of U during instruction selection that starts at Root.
1426 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1427 SDNode *Root) const {
1428 if (OptLevel == CodeGenOpt::None) return false;
1429 return N.hasOneUse();
1432 /// IsLegalToFold - Returns true if the specific operand node N of
1433 /// U can be folded during instruction selection that starts at Root.
1434 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const {
1435 if (OptLevel == CodeGenOpt::None) return false;
1437 // If Root use can somehow reach N through a path that that doesn't contain
1438 // U then folding N would create a cycle. e.g. In the following
1439 // diagram, Root can reach N through X. If N is folded into into Root, then
1440 // X is both a predecessor and a successor of U.
1451 // * indicates nodes to be folded together.
1453 // If Root produces a flag, then it gets (even more) interesting. Since it
1454 // will be "glued" together with its flag use in the scheduler, we need to
1455 // check if it might reach N.
1474 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1475 // (call it Fold), then X is a predecessor of FU and a successor of
1476 // Fold. But since Fold and FU are flagged together, this will create
1477 // a cycle in the scheduling graph.
1479 EVT VT = Root->getValueType(Root->getNumValues()-1);
1480 while (VT == MVT::Flag) {
1481 SDNode *FU = findFlagUse(Root);
1485 VT = Root->getValueType(Root->getNumValues()-1);
1488 return !isNonImmUse(Root, N.getNode(), U);
1491 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1492 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1493 SelectInlineAsmMemoryOperands(Ops);
1495 std::vector<EVT> VTs;
1496 VTs.push_back(MVT::Other);
1497 VTs.push_back(MVT::Flag);
1498 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1499 VTs, &Ops[0], Ops.size());
1500 return New.getNode();
1503 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1504 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1507 SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) {
1508 SDValue Chain = N->getOperand(0);
1509 unsigned C = cast<LabelSDNode>(N)->getLabelID();
1510 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);
1511 return CurDAG->SelectNodeTo(N, TargetOpcode::EH_LABEL,
1512 MVT::Other, Tmp, Chain);
1515 /// GetVBR - decode a vbr encoding whose top bit is set.
1516 ALWAYS_INLINE static uint64_t
1517 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1518 assert(Val >= 128 && "Not a VBR");
1519 Val &= 127; // Remove first vbr bit.
1524 NextBits = MatcherTable[Idx++];
1525 Val |= (NextBits&127) << Shift;
1527 } while (NextBits & 128);
1533 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1534 /// interior flag and chain results to use the new flag and chain results.
1535 static void UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1536 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1538 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1539 bool isMorphNodeTo, SelectionDAG *CurDAG) {
1540 // Now that all the normal results are replaced, we replace the chain and
1541 // flag results if present.
1542 if (!ChainNodesMatched.empty()) {
1543 assert(InputChain.getNode() != 0 &&
1544 "Matched input chains but didn't produce a chain");
1545 // Loop over all of the nodes we matched that produced a chain result.
1546 // Replace all the chain results with the final chain we ended up with.
1547 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1548 SDNode *ChainNode = ChainNodesMatched[i];
1550 // Don't replace the results of the root node if we're doing a
1552 if (ChainNode == NodeToMatch && isMorphNodeTo)
1555 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1556 if (ChainVal.getValueType() == MVT::Flag)
1557 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1558 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1559 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1563 // If the result produces a flag, update any flag results in the matched
1564 // pattern with the flag result.
1565 if (InputFlag.getNode() != 0) {
1566 // Handle any interior nodes explicitly marked.
1567 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1568 SDNode *FRN = FlagResultNodesMatched[i];
1569 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1570 "Doesn't have a flag result");
1571 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1576 DEBUG(errs() << "ISEL: Match complete!\n");
1582 CR_LeadsToInteriorNode
1585 /// WalkChainUsers - Walk down the users of the specified chained node that is
1586 /// part of the pattern we're matching, looking at all of the users we find.
1587 /// This determines whether something is an interior node, whether we have a
1588 /// non-pattern node in between two pattern nodes (which prevent folding because
1589 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1590 /// between pattern nodes (in which case the TF becomes part of the pattern).
1592 /// The walk we do here is guaranteed to be small because we quickly get down to
1593 /// already selected nodes "below" us.
1595 WalkChainUsers(SDNode *ChainedNode,
1596 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1597 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1598 ChainResult Result = CR_Simple;
1600 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1601 E = ChainedNode->use_end(); UI != E; ++UI) {
1602 // Make sure the use is of the chain, not some other value we produce.
1603 if (UI.getUse().getValueType() != MVT::Other) continue;
1607 // If we see an already-selected machine node, then we've gone beyond the
1608 // pattern that we're selecting down into the already selected chunk of the
1610 if (User->isMachineOpcode() ||
1611 User->getOpcode() == ISD::CopyToReg ||
1612 User->getOpcode() == ISD::CopyFromReg ||
1613 User->getOpcode() == ISD::INLINEASM ||
1614 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1617 // If we have a TokenFactor, we handle it specially.
1618 if (User->getOpcode() != ISD::TokenFactor) {
1619 // If the node isn't a token factor and isn't part of our pattern, then it
1620 // must be a random chained node in between two nodes we're selecting.
1621 // This happens when we have something like:
1626 // Because we structurally match the load/store as a read/modify/write,
1627 // but the call is chained between them. We cannot fold in this case
1628 // because it would induce a cycle in the graph.
1629 if (!std::count(ChainedNodesInPattern.begin(),
1630 ChainedNodesInPattern.end(), User))
1631 return CR_InducesCycle;
1633 // Otherwise we found a node that is part of our pattern. For example in:
1637 // This would happen when we're scanning down from the load and see the
1638 // store as a user. Record that there is a use of ChainedNode that is
1639 // part of the pattern and keep scanning uses.
1640 Result = CR_LeadsToInteriorNode;
1641 InteriorChainedNodes.push_back(User);
1645 // If we found a TokenFactor, there are two cases to consider: first if the
1646 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1647 // uses of the TF are in our pattern) we just want to ignore it. Second,
1648 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1654 // | \ DAG's like cheese
1657 // [TokenFactor] [Op]
1664 // In this case, the TokenFactor becomes part of our match and we rewrite it
1665 // as a new TokenFactor.
1667 // To distinguish these two cases, do a recursive walk down the uses.
1668 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1670 // If the uses of the TokenFactor are just already-selected nodes, ignore
1671 // it, it is "below" our pattern.
1673 case CR_InducesCycle:
1674 // If the uses of the TokenFactor lead to nodes that are not part of our
1675 // pattern that are not selected, folding would turn this into a cycle,
1677 return CR_InducesCycle;
1678 case CR_LeadsToInteriorNode:
1679 break; // Otherwise, keep processing.
1682 // Okay, we know we're in the interesting interior case. The TokenFactor
1683 // is now going to be considered part of the pattern so that we rewrite its
1684 // uses (it may have uses that are not part of the pattern) with the
1685 // ultimate chain result of the generated code. We will also add its chain
1686 // inputs as inputs to the ultimate TokenFactor we create.
1687 Result = CR_LeadsToInteriorNode;
1688 ChainedNodesInPattern.push_back(User);
1689 InteriorChainedNodes.push_back(User);
1696 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1697 /// operation for when the pattern matched multiple nodes with chains. The
1698 /// input vector contains a list of all of the chained nodes that we match. We
1699 /// must determine if this is a valid thing to cover (i.e. matching it won't
1700 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1701 /// be used as the input node chain for the generated nodes.
1703 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1704 SelectionDAG *CurDAG) {
1705 assert(ChainNodesMatched.size() > 1 &&
1706 "Should only happen for multi chain node case");
1708 // Walk all of the chained nodes we've matched, recursively scanning down the
1709 // users of the chain result. This adds any TokenFactor nodes that are caught
1710 // in between chained nodes to the chained and interior nodes list.
1711 SmallVector<SDNode*, 3> InteriorChainedNodes;
1712 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1713 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1714 InteriorChainedNodes) == CR_InducesCycle)
1715 return SDValue(); // Would induce a cycle.
1718 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1719 // that we are interested in. Form our input TokenFactor node.
1720 SmallVector<SDValue, 3> InputChains;
1721 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1722 // Add the input chain of this node to the InputChains list (which will be
1723 // the operands of the generated TokenFactor) if it's not an interior node.
1724 SDNode *N = ChainNodesMatched[i];
1725 if (N->getOpcode() != ISD::TokenFactor) {
1726 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1729 // Otherwise, add the input chain.
1730 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1731 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1732 InputChains.push_back(InChain);
1736 // If we have a token factor, we want to add all inputs of the token factor
1737 // that are not part of the pattern we're matching.
1738 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1739 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1740 N->getOperand(op).getNode()))
1741 InputChains.push_back(N->getOperand(op));
1746 if (InputChains.size() == 1)
1747 return InputChains[0];
1748 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1749 MVT::Other, &InputChains[0], InputChains.size());
1752 /// MorphNode - Handle morphing a node in place for the selector.
1753 SDNode *SelectionDAGISel::
1754 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1755 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1756 // It is possible we're using MorphNodeTo to replace a node with no
1757 // normal results with one that has a normal result (or we could be
1758 // adding a chain) and the input could have flags and chains as well.
1759 // In this case we need to shifting the operands down.
1760 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1761 // than the old isel though. We should sink this into MorphNodeTo.
1762 int OldFlagResultNo = -1, OldChainResultNo = -1;
1764 unsigned NTMNumResults = Node->getNumValues();
1765 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1766 OldFlagResultNo = NTMNumResults-1;
1767 if (NTMNumResults != 1 &&
1768 Node->getValueType(NTMNumResults-2) == MVT::Other)
1769 OldChainResultNo = NTMNumResults-2;
1770 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1771 OldChainResultNo = NTMNumResults-1;
1773 // FIXME: If this matches multiple nodes it will just leave them here
1774 // dead with noone to love them. These dead nodes can block future
1776 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1778 // MorphNodeTo can operate in two ways: if an existing node with the
1779 // specified operands exists, it can just return it. Otherwise, it
1780 // updates the node in place to have the requested operands.
1782 // If we updated the node in place, reset the node ID. To the isel,
1783 // this should be just like a newly allocated machine node.
1787 unsigned ResNumResults = Res->getNumValues();
1788 // Move the flag if needed.
1789 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1790 (unsigned)OldFlagResultNo != ResNumResults-1)
1791 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1792 SDValue(Res, ResNumResults-1));
1794 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1797 // Move the chain reference if needed.
1798 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1799 (unsigned)OldChainResultNo != ResNumResults-1)
1800 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1801 SDValue(Res, ResNumResults-1));
1803 // Otherwise, no replacement happened because the node already exists. Replace
1804 // Uses of the old node with the new one.
1806 CurDAG->ReplaceAllUsesWith(Node, Res);
1813 /// FailIndex - If this match fails, this is the index to continue with.
1816 /// NodeStack - The node stack when the scope was formed.
1817 SmallVector<SDValue, 4> NodeStack;
1819 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1820 unsigned NumRecordedNodes;
1822 /// NumMatchedMemRefs - The number of matched memref entries.
1823 unsigned NumMatchedMemRefs;
1825 /// InputChain/InputFlag - The current chain/flag
1826 SDValue InputChain, InputFlag;
1828 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1829 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1832 SDNode *SelectionDAGISel::
1833 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1834 unsigned TableSize) {
1835 // FIXME: Should these even be selected? Handle these cases in the caller?
1836 switch (NodeToMatch->getOpcode()) {
1839 case ISD::EntryToken: // These nodes remain the same.
1840 case ISD::BasicBlock:
1842 case ISD::HANDLENODE:
1843 case ISD::TargetConstant:
1844 case ISD::TargetConstantFP:
1845 case ISD::TargetConstantPool:
1846 case ISD::TargetFrameIndex:
1847 case ISD::TargetExternalSymbol:
1848 case ISD::TargetBlockAddress:
1849 case ISD::TargetJumpTable:
1850 case ISD::TargetGlobalTLSAddress:
1851 case ISD::TargetGlobalAddress:
1852 case ISD::TokenFactor:
1853 case ISD::CopyFromReg:
1854 case ISD::CopyToReg:
1856 case ISD::AssertSext:
1857 case ISD::AssertZext:
1858 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1859 NodeToMatch->getOperand(0));
1861 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1862 case ISD::EH_LABEL: return Select_EH_LABEL(NodeToMatch);
1863 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1866 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1868 // Set up the node stack with NodeToMatch as the only node on the stack.
1869 SmallVector<SDValue, 8> NodeStack;
1870 SDValue N = SDValue(NodeToMatch, 0);
1871 NodeStack.push_back(N);
1873 // MatchScopes - Scopes used when matching, if a match failure happens, this
1874 // indicates where to continue checking.
1875 SmallVector<MatchScope, 8> MatchScopes;
1877 // RecordedNodes - This is the set of nodes that have been recorded by the
1879 SmallVector<SDValue, 8> RecordedNodes;
1881 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1883 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1885 // These are the current input chain and flag for use when generating nodes.
1886 // Various Emit operations change these. For example, emitting a copytoreg
1887 // uses and updates these.
1888 SDValue InputChain, InputFlag;
1890 // ChainNodesMatched - If a pattern matches nodes that have input/output
1891 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1892 // which ones they are. The result is captured into this list so that we can
1893 // update the chain results when the pattern is complete.
1894 SmallVector<SDNode*, 3> ChainNodesMatched;
1895 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1897 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1898 NodeToMatch->dump(CurDAG);
1901 // Determine where to start the interpreter. Normally we start at opcode #0,
1902 // but if the state machine starts with an OPC_SwitchOpcode, then we
1903 // accelerate the first lookup (which is guaranteed to be hot) with the
1904 // OpcodeOffset table.
1905 unsigned MatcherIndex = 0;
1907 if (!OpcodeOffset.empty()) {
1908 // Already computed the OpcodeOffset table, just index into it.
1909 if (N.getOpcode() < OpcodeOffset.size())
1910 MatcherIndex = OpcodeOffset[N.getOpcode()];
1911 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1913 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1914 // Otherwise, the table isn't computed, but the state machine does start
1915 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1916 // is the first time we're selecting an instruction.
1919 // Get the size of this case.
1920 unsigned CaseSize = MatcherTable[Idx++];
1922 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1923 if (CaseSize == 0) break;
1925 // Get the opcode, add the index to the table.
1926 unsigned Opc = MatcherTable[Idx++];
1927 if (Opc >= OpcodeOffset.size())
1928 OpcodeOffset.resize((Opc+1)*2);
1929 OpcodeOffset[Opc] = Idx;
1933 // Okay, do the lookup for the first opcode.
1934 if (N.getOpcode() < OpcodeOffset.size())
1935 MatcherIndex = OpcodeOffset[N.getOpcode()];
1939 assert(MatcherIndex < TableSize && "Invalid index");
1940 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1943 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1944 if (NumToSkip & 128)
1945 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1946 assert(NumToSkip != 0 &&
1947 "First entry of OPC_Scope shouldn't be 0, scope has no children?");
1949 // Push a MatchScope which indicates where to go if the first child fails
1951 MatchScope NewEntry;
1952 NewEntry.FailIndex = MatcherIndex+NumToSkip;
1953 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
1954 NewEntry.NumRecordedNodes = RecordedNodes.size();
1955 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
1956 NewEntry.InputChain = InputChain;
1957 NewEntry.InputFlag = InputFlag;
1958 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
1959 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
1960 MatchScopes.push_back(NewEntry);
1963 case OPC_RecordNode:
1964 // Remember this node, it may end up being an operand in the pattern.
1965 RecordedNodes.push_back(N);
1968 case OPC_RecordChild0: case OPC_RecordChild1:
1969 case OPC_RecordChild2: case OPC_RecordChild3:
1970 case OPC_RecordChild4: case OPC_RecordChild5:
1971 case OPC_RecordChild6: case OPC_RecordChild7: {
1972 unsigned ChildNo = Opcode-OPC_RecordChild0;
1973 if (ChildNo >= N.getNumOperands())
1974 break; // Match fails if out of range child #.
1976 RecordedNodes.push_back(N->getOperand(ChildNo));
1979 case OPC_RecordMemRef:
1980 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
1983 case OPC_CaptureFlagInput:
1984 // If the current node has an input flag, capture it in InputFlag.
1985 if (N->getNumOperands() != 0 &&
1986 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
1987 InputFlag = N->getOperand(N->getNumOperands()-1);
1990 case OPC_MoveChild: {
1991 unsigned ChildNo = MatcherTable[MatcherIndex++];
1992 if (ChildNo >= N.getNumOperands())
1993 break; // Match fails if out of range child #.
1994 N = N.getOperand(ChildNo);
1995 NodeStack.push_back(N);
1999 case OPC_MoveParent:
2000 // Pop the current node off the NodeStack.
2001 NodeStack.pop_back();
2002 assert(!NodeStack.empty() && "Node stack imbalance!");
2003 N = NodeStack.back();
2006 case OPC_CheckSame: {
2007 // Accept if it is exactly the same as a previously recorded node.
2008 unsigned RecNo = MatcherTable[MatcherIndex++];
2009 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2010 if (N != RecordedNodes[RecNo]) break;
2013 case OPC_CheckPatternPredicate:
2014 if (!CheckPatternPredicate(MatcherTable[MatcherIndex++])) break;
2016 case OPC_CheckPredicate:
2017 if (!CheckNodePredicate(N.getNode(), MatcherTable[MatcherIndex++])) break;
2019 case OPC_CheckComplexPat:
2020 if (!CheckComplexPattern(NodeToMatch, N,
2021 MatcherTable[MatcherIndex++], RecordedNodes))
2024 case OPC_CheckOpcode:
2025 if (N->getOpcode() != MatcherTable[MatcherIndex++]) break;
2028 case OPC_SwitchOpcode: {
2029 unsigned CurNodeOpcode = N.getOpcode();
2031 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2035 // Get the size of this case.
2036 CaseSize = MatcherTable[MatcherIndex++];
2038 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2039 if (CaseSize == 0) break;
2041 // If the opcode matches, then we will execute this case.
2042 if (CurNodeOpcode == MatcherTable[MatcherIndex++])
2045 // Otherwise, skip over this case.
2046 MatcherIndex += CaseSize;
2049 // If we failed to match, bail out.
2050 if (CaseSize == 0) break;
2052 // Otherwise, execute the case we found.
2053 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2054 << " to " << MatcherIndex << "\n");
2058 case OPC_CheckType: {
2059 MVT::SimpleValueType VT =
2060 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2061 if (N.getValueType() != VT) {
2062 // Handle the case when VT is iPTR.
2063 if (VT != MVT::iPTR || N.getValueType() != TLI.getPointerTy())
2068 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2069 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2070 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2071 case OPC_CheckChild6Type: case OPC_CheckChild7Type: {
2072 unsigned ChildNo = Opcode-OPC_CheckChild0Type;
2073 if (ChildNo >= N.getNumOperands())
2074 break; // Match fails if out of range child #.
2076 MVT::SimpleValueType VT =
2077 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2078 EVT ChildVT = N.getOperand(ChildNo).getValueType();
2079 if (ChildVT != VT) {
2080 // Handle the case when VT is iPTR.
2081 if (VT != MVT::iPTR || ChildVT != TLI.getPointerTy())
2086 case OPC_CheckCondCode:
2087 if (cast<CondCodeSDNode>(N)->get() !=
2088 (ISD::CondCode)MatcherTable[MatcherIndex++]) break;
2090 case OPC_CheckValueType: {
2091 MVT::SimpleValueType VT =
2092 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2093 if (cast<VTSDNode>(N)->getVT() != VT) {
2094 // Handle the case when VT is iPTR.
2095 if (VT != MVT::iPTR || cast<VTSDNode>(N)->getVT() != TLI.getPointerTy())
2100 case OPC_CheckInteger: {
2101 int64_t Val = MatcherTable[MatcherIndex++];
2103 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2105 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2106 if (C == 0 || C->getSExtValue() != Val)
2110 case OPC_CheckAndImm: {
2111 int64_t Val = MatcherTable[MatcherIndex++];
2113 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2115 if (N->getOpcode() != ISD::AND) break;
2116 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2117 if (C == 0 || !CheckAndMask(N.getOperand(0), C, Val))
2121 case OPC_CheckOrImm: {
2122 int64_t Val = MatcherTable[MatcherIndex++];
2124 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2126 if (N->getOpcode() != ISD::OR) break;
2128 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2129 if (C == 0 || !CheckOrMask(N.getOperand(0), C, Val))
2134 case OPC_CheckFoldableChainNode: {
2135 assert(NodeStack.size() != 1 && "No parent node");
2136 // Verify that all intermediate nodes between the root and this one have
2138 bool HasMultipleUses = false;
2139 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2140 if (!NodeStack[i].hasOneUse()) {
2141 HasMultipleUses = true;
2144 if (HasMultipleUses) break;
2146 // Check to see that the target thinks this is profitable to fold and that
2147 // we can fold it without inducing cycles in the graph.
2148 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2150 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2156 case OPC_EmitInteger: {
2157 MVT::SimpleValueType VT =
2158 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2159 int64_t Val = MatcherTable[MatcherIndex++];
2161 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2162 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2165 case OPC_EmitRegister: {
2166 MVT::SimpleValueType VT =
2167 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2168 unsigned RegNo = MatcherTable[MatcherIndex++];
2169 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2173 case OPC_EmitConvertToTarget: {
2174 // Convert from IMM/FPIMM to target version.
2175 unsigned RecNo = MatcherTable[MatcherIndex++];
2176 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2177 SDValue Imm = RecordedNodes[RecNo];
2179 if (Imm->getOpcode() == ISD::Constant) {
2180 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2181 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2182 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2183 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2184 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2187 RecordedNodes.push_back(Imm);
2191 case OPC_EmitMergeInputChains: {
2192 assert(InputChain.getNode() == 0 &&
2193 "EmitMergeInputChains should be the first chain producing node");
2194 // This node gets a list of nodes we matched in the input that have
2195 // chains. We want to token factor all of the input chains to these nodes
2196 // together. However, if any of the input chains is actually one of the
2197 // nodes matched in this pattern, then we have an intra-match reference.
2198 // Ignore these because the newly token factored chain should not refer to
2200 unsigned NumChains = MatcherTable[MatcherIndex++];
2201 assert(NumChains != 0 && "Can't TF zero chains");
2203 assert(ChainNodesMatched.empty() &&
2204 "Should only have one EmitMergeInputChains per match");
2206 // Handle the first chain.
2207 unsigned RecNo = MatcherTable[MatcherIndex++];
2208 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2209 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2211 // If the chained node is not the root, we can't fold it if it has
2213 // FIXME: What if other value results of the node have uses not matched by
2215 if (ChainNodesMatched.back() != NodeToMatch &&
2216 !RecordedNodes[RecNo].hasOneUse()) {
2217 ChainNodesMatched.clear();
2221 // The common case here is that we have exactly one chain, which is really
2222 // cheap to handle, just do it.
2223 if (NumChains == 1) {
2224 InputChain = RecordedNodes[RecNo].getOperand(0);
2225 assert(InputChain.getValueType() == MVT::Other && "Not a chain");
2229 // Read all of the chained nodes.
2230 for (unsigned i = 1; i != NumChains; ++i) {
2231 RecNo = MatcherTable[MatcherIndex++];
2232 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2233 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2235 // FIXME: What if other value results of the node have uses not matched
2237 if (ChainNodesMatched.back() != NodeToMatch &&
2238 !RecordedNodes[RecNo].hasOneUse()) {
2239 ChainNodesMatched.clear();
2244 // If the inner loop broke out, the match fails.
2245 if (ChainNodesMatched.empty())
2248 // Merge the input chains if they are not intra-pattern references.
2249 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2251 if (InputChain.getNode() == 0)
2252 break; // Failed to merge.
2257 case OPC_EmitCopyToReg: {
2258 unsigned RecNo = MatcherTable[MatcherIndex++];
2259 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2260 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2262 if (InputChain.getNode() == 0)
2263 InputChain = CurDAG->getEntryNode();
2265 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2266 DestPhysReg, RecordedNodes[RecNo],
2269 InputFlag = InputChain.getValue(1);
2273 case OPC_EmitNodeXForm: {
2274 unsigned XFormNo = MatcherTable[MatcherIndex++];
2275 unsigned RecNo = MatcherTable[MatcherIndex++];
2276 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2277 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2282 case OPC_MorphNodeTo: {
2283 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2284 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2285 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2286 // Get the result VT list.
2287 unsigned NumVTs = MatcherTable[MatcherIndex++];
2288 SmallVector<EVT, 4> VTs;
2289 for (unsigned i = 0; i != NumVTs; ++i) {
2290 MVT::SimpleValueType VT =
2291 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2292 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2296 if (EmitNodeInfo & OPFL_Chain)
2297 VTs.push_back(MVT::Other);
2298 if (EmitNodeInfo & OPFL_FlagOutput)
2299 VTs.push_back(MVT::Flag);
2301 // This is hot code, so optimize the two most common cases of 1 and 2
2304 if (VTs.size() == 1)
2305 VTList = CurDAG->getVTList(VTs[0]);
2306 else if (VTs.size() == 2)
2307 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2309 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2311 // Get the operand list.
2312 unsigned NumOps = MatcherTable[MatcherIndex++];
2313 SmallVector<SDValue, 8> Ops;
2314 for (unsigned i = 0; i != NumOps; ++i) {
2315 unsigned RecNo = MatcherTable[MatcherIndex++];
2317 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2319 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2320 Ops.push_back(RecordedNodes[RecNo]);
2323 // If there are variadic operands to add, handle them now.
2324 if (EmitNodeInfo & OPFL_VariadicInfo) {
2325 // Determine the start index to copy from.
2326 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2327 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2328 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2329 "Invalid variadic node");
2330 // Copy all of the variadic operands, not including a potential flag
2332 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2334 SDValue V = NodeToMatch->getOperand(i);
2335 if (V.getValueType() == MVT::Flag) break;
2340 // If this has chain/flag inputs, add them.
2341 if (EmitNodeInfo & OPFL_Chain)
2342 Ops.push_back(InputChain);
2343 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2344 Ops.push_back(InputFlag);
2348 if (Opcode != OPC_MorphNodeTo) {
2349 // If this is a normal EmitNode command, just create the new node and
2350 // add the results to the RecordedNodes list.
2351 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2352 VTList, Ops.data(), Ops.size());
2354 // Add all the non-flag/non-chain results to the RecordedNodes list.
2355 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2356 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2357 RecordedNodes.push_back(SDValue(Res, i));
2361 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2365 // If the node had chain/flag results, update our notion of the current
2367 if (VTs.back() == MVT::Flag) {
2368 InputFlag = SDValue(Res, VTs.size()-1);
2369 if (EmitNodeInfo & OPFL_Chain)
2370 InputChain = SDValue(Res, VTs.size()-2);
2371 } else if (EmitNodeInfo & OPFL_Chain)
2372 InputChain = SDValue(Res, VTs.size()-1);
2374 // If the OPFL_MemRefs flag is set on this node, slap all of the
2375 // accumulated memrefs onto it.
2377 // FIXME: This is vastly incorrect for patterns with multiple outputs
2378 // instructions that access memory and for ComplexPatterns that match
2380 if (EmitNodeInfo & OPFL_MemRefs) {
2381 MachineSDNode::mmo_iterator MemRefs =
2382 MF->allocateMemRefsArray(MatchedMemRefs.size());
2383 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2384 cast<MachineSDNode>(Res)
2385 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2389 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2390 << " node: "; Res->dump(CurDAG); errs() << "\n");
2392 // If this was a MorphNodeTo then we're completely done!
2393 if (Opcode == OPC_MorphNodeTo) {
2394 // Update chain and flag uses.
2395 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2396 InputFlag, FlagResultNodesMatched, true, CurDAG);
2403 case OPC_MarkFlagResults: {
2404 unsigned NumNodes = MatcherTable[MatcherIndex++];
2406 // Read and remember all the flag-result nodes.
2407 for (unsigned i = 0; i != NumNodes; ++i) {
2408 unsigned RecNo = MatcherTable[MatcherIndex++];
2410 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2412 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2413 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2418 case OPC_CompleteMatch: {
2419 // The match has been completed, and any new nodes (if any) have been
2420 // created. Patch up references to the matched dag to use the newly
2422 unsigned NumResults = MatcherTable[MatcherIndex++];
2424 for (unsigned i = 0; i != NumResults; ++i) {
2425 unsigned ResSlot = MatcherTable[MatcherIndex++];
2427 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2429 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2430 SDValue Res = RecordedNodes[ResSlot];
2432 // FIXME2: Eliminate this horrible hack by fixing the 'Gen' program
2433 // after (parallel) on input patterns are removed. This would also
2434 // allow us to stop encoding #results in OPC_CompleteMatch's table
2436 if (NodeToMatch->getNumValues() <= i ||
2437 NodeToMatch->getValueType(i) == MVT::Other ||
2438 NodeToMatch->getValueType(i) == MVT::Flag)
2440 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2441 NodeToMatch->getValueType(i) == MVT::iPTR ||
2442 Res.getValueType() == MVT::iPTR ||
2443 NodeToMatch->getValueType(i).getSizeInBits() ==
2444 Res.getValueType().getSizeInBits()) &&
2445 "invalid replacement");
2446 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2449 // If the root node defines a flag, add it to the flag nodes to update
2451 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2452 FlagResultNodesMatched.push_back(NodeToMatch);
2454 // Update chain and flag uses.
2455 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2456 InputFlag, FlagResultNodesMatched, false, CurDAG);
2458 assert(NodeToMatch->use_empty() &&
2459 "Didn't replace all uses of the node?");
2461 // FIXME: We just return here, which interacts correctly with SelectRoot
2462 // above. We should fix this to not return an SDNode* anymore.
2467 // If the code reached this point, then the match failed. See if there is
2468 // another child to try in the current 'Scope', otherwise pop it until we
2469 // find a case to check.
2471 if (MatchScopes.empty()) {
2472 CannotYetSelect(NodeToMatch);
2476 // Restore the interpreter state back to the point where the scope was
2478 MatchScope &LastScope = MatchScopes.back();
2479 RecordedNodes.resize(LastScope.NumRecordedNodes);
2481 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2482 N = NodeStack.back();
2484 DEBUG(errs() << " Match failed at index " << MatcherIndex
2485 << " continuing at " << LastScope.FailIndex << "\n");
2487 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2488 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2489 MatcherIndex = LastScope.FailIndex;
2491 InputChain = LastScope.InputChain;
2492 InputFlag = LastScope.InputFlag;
2493 if (!LastScope.HasChainNodesMatched)
2494 ChainNodesMatched.clear();
2495 if (!LastScope.HasFlagResultNodesMatched)
2496 FlagResultNodesMatched.clear();
2498 // Check to see what the offset is at the new MatcherIndex. If it is zero
2499 // we have reached the end of this scope, otherwise we have another child
2500 // in the current scope to try.
2501 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2502 if (NumToSkip & 128)
2503 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2505 // If we have another child in this scope to match, update FailIndex and
2507 if (NumToSkip != 0) {
2508 LastScope.FailIndex = MatcherIndex+NumToSkip;
2512 // End of this scope, pop it and try the next child in the containing
2514 MatchScopes.pop_back();
2521 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2522 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2523 N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2524 N->getOpcode() == ISD::INTRINSIC_VOID)
2525 return CannotYetSelectIntrinsic(N);
2528 raw_string_ostream Msg(msg);
2529 Msg << "Cannot yet select: ";
2530 N->printrFull(Msg, CurDAG);
2531 llvm_report_error(Msg.str());
2534 void SelectionDAGISel::CannotYetSelectIntrinsic(SDNode *N) {
2535 dbgs() << "Cannot yet select: ";
2537 cast<ConstantSDNode>(N->getOperand(N->getOperand(0).getValueType() ==
2538 MVT::Other))->getZExtValue();
2539 if (iid < Intrinsic::num_intrinsics)
2540 llvm_report_error("Cannot yet select: intrinsic %" +
2541 Intrinsic::getName((Intrinsic::ID)iid));
2542 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo())
2543 llvm_report_error(Twine("Cannot yet select: target intrinsic %") +
2547 char SelectionDAGISel::ID = 0;