1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/TargetLibraryInfo.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugInfo.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/IntrinsicInst.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/LLVMContext.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetIntrinsicInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "llvm/Target/TargetOptions.h"
57 #include "llvm/Target/TargetRegisterInfo.h"
58 #include "llvm/Target/TargetSubtargetInfo.h"
59 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
63 #define DEBUG_TYPE "isel"
65 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
66 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
67 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
68 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
69 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
70 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
71 STATISTIC(NumFastIselFailLowerArguments,
72 "Number of entry blocks where fast isel failed to lower arguments");
76 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
77 cl::desc("Enable extra verbose messages in the \"fast\" "
78 "instruction selector"));
81 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
82 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
83 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
84 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
85 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
86 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
87 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
89 // Standard binary operators...
90 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
91 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
92 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
93 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
94 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
95 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
96 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
97 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
98 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
99 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
100 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
101 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
103 // Logical operators...
104 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
105 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
106 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
108 // Memory instructions...
109 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
110 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
111 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
112 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
113 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
114 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
115 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
117 // Convert instructions...
118 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
119 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
120 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
121 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
122 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
123 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
124 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
125 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
126 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
127 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
128 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
129 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
131 // Other instructions...
132 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
133 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
134 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
135 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
136 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
137 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
138 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
139 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
140 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
141 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
142 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
143 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
144 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
145 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
146 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
148 // Intrinsic instructions...
149 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
150 STATISTIC(NumFastIselFailSAddWithOverflow,
151 "Fast isel fails on sadd.with.overflow");
152 STATISTIC(NumFastIselFailUAddWithOverflow,
153 "Fast isel fails on uadd.with.overflow");
154 STATISTIC(NumFastIselFailSSubWithOverflow,
155 "Fast isel fails on ssub.with.overflow");
156 STATISTIC(NumFastIselFailUSubWithOverflow,
157 "Fast isel fails on usub.with.overflow");
158 STATISTIC(NumFastIselFailSMulWithOverflow,
159 "Fast isel fails on smul.with.overflow");
160 STATISTIC(NumFastIselFailUMulWithOverflow,
161 "Fast isel fails on umul.with.overflow");
162 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
163 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
164 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
165 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
169 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
170 cl::desc("Enable verbose messages in the \"fast\" "
171 "instruction selector"));
172 static cl::opt<int> EnableFastISelAbort(
173 "fast-isel-abort", cl::Hidden,
174 cl::desc("Enable abort calls when \"fast\" instruction selection "
175 "fails to lower an instruction: 0 disable the abort, 1 will "
176 "abort but for args, calls and terminators, 2 will also "
177 "abort for argument lowering, and 3 will never fallback "
178 "to SelectionDAG."));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None ||
297 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
298 TLI->getSchedulingPreference() == Sched::Source)
299 return createSourceListDAGScheduler(IS, OptLevel);
300 if (TLI->getSchedulingPreference() == Sched::RegPressure)
301 return createBURRListDAGScheduler(IS, OptLevel);
302 if (TLI->getSchedulingPreference() == Sched::Hybrid)
303 return createHybridListDAGScheduler(IS, OptLevel);
304 if (TLI->getSchedulingPreference() == Sched::VLIW)
305 return createVLIWDAGScheduler(IS, OptLevel);
306 assert(TLI->getSchedulingPreference() == Sched::ILP &&
307 "Unknown sched type!");
308 return createILPListDAGScheduler(IS, OptLevel);
312 // EmitInstrWithCustomInserter - This method should be implemented by targets
313 // that mark instructions with the 'usesCustomInserter' flag. These
314 // instructions are special in various ways, which require special support to
315 // insert. The specified MachineInstr is created but not inserted into any
316 // basic blocks, and this method is called to expand it into a sequence of
317 // instructions, potentially also creating new basic blocks and control flow.
318 // When new basic blocks are inserted and the edges from MBB to its successors
319 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
322 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
323 MachineBasicBlock *MBB) const {
325 dbgs() << "If a target marks an instruction with "
326 "'usesCustomInserter', it must implement "
327 "TargetLowering::EmitInstrWithCustomInserter!";
329 llvm_unreachable(nullptr);
332 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
333 SDNode *Node) const {
334 assert(!MI->hasPostISelHook() &&
335 "If a target marks an instruction with 'hasPostISelHook', "
336 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
339 //===----------------------------------------------------------------------===//
340 // SelectionDAGISel code
341 //===----------------------------------------------------------------------===//
343 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
344 CodeGenOpt::Level OL) :
345 MachineFunctionPass(ID), TM(tm),
346 FuncInfo(new FunctionLoweringInfo()),
347 CurDAG(new SelectionDAG(tm, OL)),
348 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
352 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
353 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
354 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
355 initializeTargetLibraryInfoWrapperPassPass(
356 *PassRegistry::getPassRegistry());
359 SelectionDAGISel::~SelectionDAGISel() {
365 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
366 AU.addRequired<AliasAnalysis>();
367 AU.addPreserved<AliasAnalysis>();
368 AU.addRequired<GCModuleInfo>();
369 AU.addPreserved<GCModuleInfo>();
370 AU.addRequired<TargetLibraryInfoWrapperPass>();
371 if (UseMBPI && OptLevel != CodeGenOpt::None)
372 AU.addRequired<BranchProbabilityInfo>();
373 MachineFunctionPass::getAnalysisUsage(AU);
376 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
377 /// may trap on it. In this case we have to split the edge so that the path
378 /// through the predecessor block that doesn't go to the phi block doesn't
379 /// execute the possibly trapping instruction.
381 /// This is required for correctness, so it must be done at -O0.
383 static void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA) {
384 // Loop for blocks with phi nodes.
385 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
386 PHINode *PN = dyn_cast<PHINode>(BB->begin());
390 // For each block with a PHI node, check to see if any of the input values
391 // are potentially trapping constant expressions. Constant expressions are
392 // the only potentially trapping value that can occur as the argument to a
394 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
395 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
396 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
397 if (!CE || !CE->canTrap()) continue;
399 // The only case we have to worry about is when the edge is critical.
400 // Since this block has a PHI Node, we assume it has multiple input
401 // edges: check to see if the pred has multiple successors.
402 BasicBlock *Pred = PN->getIncomingBlock(i);
403 if (Pred->getTerminator()->getNumSuccessors() == 1)
406 // Okay, we have to split this edge.
408 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
409 CriticalEdgeSplittingOptions(AA).setMergeIdenticalEdges());
415 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
416 // Do some sanity-checking on the command-line options.
417 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
418 "-fast-isel-verbose requires -fast-isel");
419 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
420 "-fast-isel-abort > 0 requires -fast-isel");
422 const Function &Fn = *mf.getFunction();
425 // Reset the target options before resetting the optimization
427 // FIXME: This is a horrible hack and should be processed via
428 // codegen looking at the optimization level explicitly when
429 // it wants to look at it.
430 TM.resetTargetOptions(Fn);
431 // Reset OptLevel to None for optnone functions.
432 CodeGenOpt::Level NewOptLevel = OptLevel;
433 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
434 NewOptLevel = CodeGenOpt::None;
435 OptLevelChanger OLC(*this, NewOptLevel);
437 TII = MF->getSubtarget().getInstrInfo();
438 TLI = MF->getSubtarget().getTargetLowering();
439 RegInfo = &MF->getRegInfo();
440 AA = &getAnalysis<AliasAnalysis>();
441 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
442 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
444 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
446 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), AA);
449 FuncInfo->set(Fn, *MF, CurDAG);
451 if (UseMBPI && OptLevel != CodeGenOpt::None)
452 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
454 FuncInfo->BPI = nullptr;
456 SDB->init(GFI, *AA, LibInfo);
458 MF->setHasInlineAsm(false);
460 SelectAllBasicBlocks(Fn);
462 // If the first basic block in the function has live ins that need to be
463 // copied into vregs, emit the copies into the top of the block before
464 // emitting the code for the block.
465 MachineBasicBlock *EntryMBB = MF->begin();
466 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
467 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
469 DenseMap<unsigned, unsigned> LiveInMap;
470 if (!FuncInfo->ArgDbgValues.empty())
471 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
472 E = RegInfo->livein_end(); LI != E; ++LI)
474 LiveInMap.insert(std::make_pair(LI->first, LI->second));
476 // Insert DBG_VALUE instructions for function arguments to the entry block.
477 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
478 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
479 bool hasFI = MI->getOperand(0).isFI();
481 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
482 if (TargetRegisterInfo::isPhysicalRegister(Reg))
483 EntryMBB->insert(EntryMBB->begin(), MI);
485 MachineInstr *Def = RegInfo->getVRegDef(Reg);
487 MachineBasicBlock::iterator InsertPos = Def;
488 // FIXME: VR def may not be in entry block.
489 Def->getParent()->insert(std::next(InsertPos), MI);
491 DEBUG(dbgs() << "Dropping debug info for dead vreg"
492 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
495 // If Reg is live-in then update debug info to track its copy in a vreg.
496 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
497 if (LDI != LiveInMap.end()) {
498 assert(!hasFI && "There's no handling of frame pointer updating here yet "
500 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
501 MachineBasicBlock::iterator InsertPos = Def;
502 const MDNode *Variable = MI->getDebugVariable();
503 const MDNode *Expr = MI->getDebugExpression();
504 DebugLoc DL = MI->getDebugLoc();
505 bool IsIndirect = MI->isIndirectDebugValue();
506 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
507 assert(cast<MDLocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
508 "Expected inlined-at fields to agree");
509 // Def is never a terminator here, so it is ok to increment InsertPos.
510 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
511 IsIndirect, LDI->second, Offset, Variable, Expr);
513 // If this vreg is directly copied into an exported register then
514 // that COPY instructions also need DBG_VALUE, if it is the only
515 // user of LDI->second.
516 MachineInstr *CopyUseMI = nullptr;
517 for (MachineRegisterInfo::use_instr_iterator
518 UI = RegInfo->use_instr_begin(LDI->second),
519 E = RegInfo->use_instr_end(); UI != E; ) {
520 MachineInstr *UseMI = &*(UI++);
521 if (UseMI->isDebugValue()) continue;
522 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
523 CopyUseMI = UseMI; continue;
525 // Otherwise this is another use or second copy use.
526 CopyUseMI = nullptr; break;
529 // Use MI's debug location, which describes where Variable was
530 // declared, rather than whatever is attached to CopyUseMI.
531 MachineInstr *NewMI =
532 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
533 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
534 MachineBasicBlock::iterator Pos = CopyUseMI;
535 EntryMBB->insertAfter(Pos, NewMI);
540 // Determine if there are any calls in this machine function.
541 MachineFrameInfo *MFI = MF->getFrameInfo();
542 for (const auto &MBB : *MF) {
543 if (MFI->hasCalls() && MF->hasInlineAsm())
546 for (const auto &MI : MBB) {
547 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
548 if ((MCID.isCall() && !MCID.isReturn()) ||
549 MI.isStackAligningInlineAsm()) {
550 MFI->setHasCalls(true);
552 if (MI.isInlineAsm()) {
553 MF->setHasInlineAsm(true);
558 // Determine if there is a call to setjmp in the machine function.
559 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
561 // Replace forward-declared registers with the registers containing
562 // the desired value.
563 MachineRegisterInfo &MRI = MF->getRegInfo();
564 for (DenseMap<unsigned, unsigned>::iterator
565 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
567 unsigned From = I->first;
568 unsigned To = I->second;
569 // If To is also scheduled to be replaced, find what its ultimate
572 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
576 // Make sure the new register has a sufficiently constrained register class.
577 if (TargetRegisterInfo::isVirtualRegister(From) &&
578 TargetRegisterInfo::isVirtualRegister(To))
579 MRI.constrainRegClass(To, MRI.getRegClass(From));
581 MRI.replaceRegWith(From, To);
584 // Freeze the set of reserved registers now that MachineFrameInfo has been
585 // set up. All the information required by getReservedRegs() should be
587 MRI.freezeReservedRegs(*MF);
589 // Release function-specific state. SDB and CurDAG are already cleared
593 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
594 DEBUG(MF->print(dbgs()));
599 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
600 BasicBlock::const_iterator End,
602 // Lower the instructions. If a call is emitted as a tail call, cease emitting
603 // nodes for this block.
604 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
607 // Make sure the root of the DAG is up-to-date.
608 CurDAG->setRoot(SDB->getControlRoot());
609 HadTailCall = SDB->HasTailCall;
612 // Final step, emit the lowered DAG as machine code.
616 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
617 SmallPtrSet<SDNode*, 128> VisitedNodes;
618 SmallVector<SDNode*, 128> Worklist;
620 Worklist.push_back(CurDAG->getRoot().getNode());
626 SDNode *N = Worklist.pop_back_val();
628 // If we've already seen this node, ignore it.
629 if (!VisitedNodes.insert(N).second)
632 // Otherwise, add all chain operands to the worklist.
633 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
634 if (N->getOperand(i).getValueType() == MVT::Other)
635 Worklist.push_back(N->getOperand(i).getNode());
637 // If this is a CopyToReg with a vreg dest, process it.
638 if (N->getOpcode() != ISD::CopyToReg)
641 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
642 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
645 // Ignore non-scalar or non-integer values.
646 SDValue Src = N->getOperand(2);
647 EVT SrcVT = Src.getValueType();
648 if (!SrcVT.isInteger() || SrcVT.isVector())
651 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
652 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
653 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
654 } while (!Worklist.empty());
657 void SelectionDAGISel::CodeGenAndEmitDAG() {
658 std::string GroupName;
659 if (TimePassesIsEnabled)
660 GroupName = "Instruction Selection and Scheduling";
661 std::string BlockName;
662 int BlockNumber = -1;
664 bool MatchFilterBB = false; (void)MatchFilterBB;
666 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
667 FilterDAGBasicBlockName ==
668 FuncInfo->MBB->getBasicBlock()->getName().str());
671 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
672 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
676 BlockNumber = FuncInfo->MBB->getNumber();
678 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
680 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
681 << " '" << BlockName << "'\n"; CurDAG->dump());
683 if (ViewDAGCombine1 && MatchFilterBB)
684 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
686 // Run the DAG combiner in pre-legalize mode.
688 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
689 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
692 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
693 << " '" << BlockName << "'\n"; CurDAG->dump());
695 // Second step, hack on the DAG until it only uses operations and types that
696 // the target supports.
697 if (ViewLegalizeTypesDAGs && MatchFilterBB)
698 CurDAG->viewGraph("legalize-types input for " + BlockName);
702 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
703 Changed = CurDAG->LegalizeTypes();
706 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
707 << " '" << BlockName << "'\n"; CurDAG->dump());
709 CurDAG->NewNodesMustHaveLegalTypes = true;
712 if (ViewDAGCombineLT && MatchFilterBB)
713 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
715 // Run the DAG combiner in post-type-legalize mode.
717 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
718 TimePassesIsEnabled);
719 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
722 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
723 << " '" << BlockName << "'\n"; CurDAG->dump());
728 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
729 Changed = CurDAG->LegalizeVectors();
734 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
735 CurDAG->LegalizeTypes();
738 if (ViewDAGCombineLT && MatchFilterBB)
739 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
741 // Run the DAG combiner in post-type-legalize mode.
743 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
744 TimePassesIsEnabled);
745 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
748 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
749 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
752 if (ViewLegalizeDAGs && MatchFilterBB)
753 CurDAG->viewGraph("legalize input for " + BlockName);
756 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
760 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
761 << " '" << BlockName << "'\n"; CurDAG->dump());
763 if (ViewDAGCombine2 && MatchFilterBB)
764 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
766 // Run the DAG combiner in post-legalize mode.
768 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
769 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
772 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
773 << " '" << BlockName << "'\n"; CurDAG->dump());
775 if (OptLevel != CodeGenOpt::None)
776 ComputeLiveOutVRegInfo();
778 if (ViewISelDAGs && MatchFilterBB)
779 CurDAG->viewGraph("isel input for " + BlockName);
781 // Third, instruction select all of the operations to machine code, adding the
782 // code to the MachineBasicBlock.
784 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
785 DoInstructionSelection();
788 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
789 << " '" << BlockName << "'\n"; CurDAG->dump());
791 if (ViewSchedDAGs && MatchFilterBB)
792 CurDAG->viewGraph("scheduler input for " + BlockName);
794 // Schedule machine code.
795 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
797 NamedRegionTimer T("Instruction Scheduling", GroupName,
798 TimePassesIsEnabled);
799 Scheduler->Run(CurDAG, FuncInfo->MBB);
802 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
804 // Emit machine code to BB. This can change 'BB' to the last block being
806 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
808 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
810 // FuncInfo->InsertPt is passed by reference and set to the end of the
811 // scheduled instructions.
812 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
815 // If the block was split, make sure we update any references that are used to
816 // update PHI nodes later on.
817 if (FirstMBB != LastMBB)
818 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
820 // Free the scheduler state.
822 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
823 TimePassesIsEnabled);
827 // Free the SelectionDAG state, now that we're finished with it.
832 /// ISelUpdater - helper class to handle updates of the instruction selection
834 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
835 SelectionDAG::allnodes_iterator &ISelPosition;
837 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
838 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
840 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
841 /// deleted is the current ISelPosition node, update ISelPosition.
843 void NodeDeleted(SDNode *N, SDNode *E) override {
844 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
848 } // end anonymous namespace
850 void SelectionDAGISel::DoInstructionSelection() {
851 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
852 << FuncInfo->MBB->getNumber()
853 << " '" << FuncInfo->MBB->getName() << "'\n");
857 // Select target instructions for the DAG.
859 // Number all nodes with a topological order and set DAGSize.
860 DAGSize = CurDAG->AssignTopologicalOrder();
862 // Create a dummy node (which is not added to allnodes), that adds
863 // a reference to the root node, preventing it from being deleted,
864 // and tracking any changes of the root.
865 HandleSDNode Dummy(CurDAG->getRoot());
866 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
869 // Make sure that ISelPosition gets properly updated when nodes are deleted
870 // in calls made from this function.
871 ISelUpdater ISU(*CurDAG, ISelPosition);
873 // The AllNodes list is now topological-sorted. Visit the
874 // nodes by starting at the end of the list (the root of the
875 // graph) and preceding back toward the beginning (the entry
877 while (ISelPosition != CurDAG->allnodes_begin()) {
878 SDNode *Node = --ISelPosition;
879 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
880 // but there are currently some corner cases that it misses. Also, this
881 // makes it theoretically possible to disable the DAGCombiner.
882 if (Node->use_empty())
885 SDNode *ResNode = Select(Node);
887 // FIXME: This is pretty gross. 'Select' should be changed to not return
888 // anything at all and this code should be nuked with a tactical strike.
890 // If node should not be replaced, continue with the next one.
891 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
895 ReplaceUses(Node, ResNode);
898 // If after the replacement this node is not used any more,
899 // remove this dead node.
900 if (Node->use_empty()) // Don't delete EntryToken, etc.
901 CurDAG->RemoveDeadNode(Node);
904 CurDAG->setRoot(Dummy.getValue());
907 DEBUG(dbgs() << "===== Instruction selection ends:\n");
909 PostprocessISelDAG();
912 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
913 /// do other setup for EH landing-pad blocks.
914 bool SelectionDAGISel::PrepareEHLandingPad() {
915 MachineBasicBlock *MBB = FuncInfo->MBB;
917 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
919 // Add a label to mark the beginning of the landing pad. Deletion of the
920 // landing pad can thus be detected via the MachineModuleInfo.
921 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
923 // Assign the call site to the landing pad's begin label.
924 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
926 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
927 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
930 // If this is an MSVC-style personality function, we need to split the landing
931 // pad into several BBs.
932 const BasicBlock *LLVMBB = MBB->getBasicBlock();
933 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
934 MF->getMMI().addPersonality(
935 MBB, cast<Function>(LPadInst->getPersonalityFn()->stripPointerCasts()));
936 EHPersonality Personality = MF->getMMI().getPersonalityType();
938 if (isMSVCEHPersonality(Personality)) {
939 SmallVector<MachineBasicBlock *, 4> ClauseBBs;
940 const IntrinsicInst *ActionsCall =
941 dyn_cast<IntrinsicInst>(LLVMBB->getFirstInsertionPt());
942 // Get all invoke BBs that unwind to this landingpad.
943 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
945 if (ActionsCall && ActionsCall->getIntrinsicID() == Intrinsic::eh_actions) {
946 // If this is a call to llvm.eh.actions followed by indirectbr, then we've
947 // run WinEHPrepare, and we should remove this block from the machine CFG.
948 // Mark the targets of the indirectbr as landingpads instead.
949 for (const BasicBlock *LLVMSucc : successors(LLVMBB)) {
950 MachineBasicBlock *ClauseBB = FuncInfo->MBBMap[LLVMSucc];
951 // Add the edge from the invoke to the clause.
952 for (MachineBasicBlock *InvokeBB : InvokeBBs)
953 InvokeBB->addSuccessor(ClauseBB);
955 // Mark the clause as a landing pad or MI passes will delete it.
956 ClauseBB->setIsLandingPad();
959 // Otherwise, we haven't done the preparation, and we need to invent some
960 // clause basic blocks that branch into the landingpad.
961 // FIXME: Remove this code once SEH preparation works.
962 ActionsCall = nullptr;
964 // Make virtual registers and a series of labels that fill in values for
966 auto &RI = MF->getRegInfo();
967 FuncInfo->ExceptionSelectorVirtReg = RI.createVirtualRegister(PtrRC);
969 // Emit separate machine basic blocks with separate labels for each clause
970 // before the main landing pad block.
971 MachineInstrBuilder SelectorPHI = BuildMI(
972 *MBB, MBB->begin(), SDB->getCurDebugLoc(),
973 TII->get(TargetOpcode::PHI), FuncInfo->ExceptionSelectorVirtReg);
974 for (unsigned I = 0, E = LPadInst->getNumClauses(); I != E; ++I) {
975 // Skip filter clauses, we can't implement them.
976 if (LPadInst->isFilter(I))
979 MachineBasicBlock *ClauseBB = MF->CreateMachineBasicBlock(LLVMBB);
980 MF->insert(MBB, ClauseBB);
982 // Add the edge from the invoke to the clause.
983 for (MachineBasicBlock *InvokeBB : InvokeBBs)
984 InvokeBB->addSuccessor(ClauseBB);
986 // Mark the clause as a landing pad or MI passes will delete it.
987 ClauseBB->setIsLandingPad();
989 GlobalValue *ClauseGV = ExtractTypeInfo(LPadInst->getClause(I));
991 // Start the BB with a label.
992 MCSymbol *ClauseLabel = MF->getMMI().addClauseForLandingPad(MBB);
993 BuildMI(*ClauseBB, ClauseBB->begin(), SDB->getCurDebugLoc(), II)
994 .addSym(ClauseLabel);
996 // Construct a simple BB that defines a register with the typeid
998 FuncInfo->MBB = ClauseBB;
999 FuncInfo->InsertPt = ClauseBB->end();
1000 unsigned VReg = SDB->visitLandingPadClauseBB(ClauseGV, MBB);
1001 CurDAG->setRoot(SDB->getRoot());
1003 CodeGenAndEmitDAG();
1005 // Add the typeid virtual register to the phi in the main landing pad.
1006 SelectorPHI.addReg(VReg).addMBB(ClauseBB);
1010 // Remove the edge from the invoke to the lpad.
1011 for (MachineBasicBlock *InvokeBB : InvokeBBs)
1012 InvokeBB->removeSuccessor(MBB);
1014 // Restore FuncInfo back to its previous state and select the main landing
1016 FuncInfo->MBB = MBB;
1017 FuncInfo->InsertPt = MBB->end();
1019 // Transfer EH state number assigned to the IR block to the MBB.
1020 if (Personality == EHPersonality::MSVC_CXX) {
1021 WinEHFuncInfo &FI = MF->getMMI().getWinEHFuncInfo(MF->getFunction());
1022 MF->getMMI().addWinEHState(MBB, FI.LandingPadStateMap[LPadInst]);
1025 // Select instructions for the landingpad if there was no llvm.eh.actions
1027 return ActionsCall == nullptr;
1030 // Mark exception register as live in.
1031 if (unsigned Reg = TLI->getExceptionPointerRegister())
1032 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
1034 // Mark exception selector register as live in.
1035 if (unsigned Reg = TLI->getExceptionSelectorRegister())
1036 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
1041 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
1042 /// side-effect free and is either dead or folded into a generated instruction.
1043 /// Return false if it needs to be emitted.
1044 static bool isFoldedOrDeadInstruction(const Instruction *I,
1045 FunctionLoweringInfo *FuncInfo) {
1046 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1047 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1048 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1049 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
1050 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1054 // Collect per Instruction statistics for fast-isel misses. Only those
1055 // instructions that cause the bail are accounted for. It does not account for
1056 // instructions higher in the block. Thus, summing the per instructions stats
1057 // will not add up to what is reported by NumFastIselFailures.
1058 static void collectFailStats(const Instruction *I) {
1059 switch (I->getOpcode()) {
1060 default: assert (0 && "<Invalid operator> ");
1063 case Instruction::Ret: NumFastIselFailRet++; return;
1064 case Instruction::Br: NumFastIselFailBr++; return;
1065 case Instruction::Switch: NumFastIselFailSwitch++; return;
1066 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1067 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1068 case Instruction::Resume: NumFastIselFailResume++; return;
1069 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1071 // Standard binary operators...
1072 case Instruction::Add: NumFastIselFailAdd++; return;
1073 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1074 case Instruction::Sub: NumFastIselFailSub++; return;
1075 case Instruction::FSub: NumFastIselFailFSub++; return;
1076 case Instruction::Mul: NumFastIselFailMul++; return;
1077 case Instruction::FMul: NumFastIselFailFMul++; return;
1078 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1079 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1080 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1081 case Instruction::URem: NumFastIselFailURem++; return;
1082 case Instruction::SRem: NumFastIselFailSRem++; return;
1083 case Instruction::FRem: NumFastIselFailFRem++; return;
1085 // Logical operators...
1086 case Instruction::And: NumFastIselFailAnd++; return;
1087 case Instruction::Or: NumFastIselFailOr++; return;
1088 case Instruction::Xor: NumFastIselFailXor++; return;
1090 // Memory instructions...
1091 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1092 case Instruction::Load: NumFastIselFailLoad++; return;
1093 case Instruction::Store: NumFastIselFailStore++; return;
1094 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1095 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1096 case Instruction::Fence: NumFastIselFailFence++; return;
1097 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1099 // Convert instructions...
1100 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1101 case Instruction::ZExt: NumFastIselFailZExt++; return;
1102 case Instruction::SExt: NumFastIselFailSExt++; return;
1103 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1104 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1105 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1106 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1107 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1108 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1109 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1110 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1111 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1113 // Other instructions...
1114 case Instruction::ICmp: NumFastIselFailICmp++; return;
1115 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1116 case Instruction::PHI: NumFastIselFailPHI++; return;
1117 case Instruction::Select: NumFastIselFailSelect++; return;
1118 case Instruction::Call: {
1119 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1120 switch (Intrinsic->getIntrinsicID()) {
1122 NumFastIselFailIntrinsicCall++; return;
1123 case Intrinsic::sadd_with_overflow:
1124 NumFastIselFailSAddWithOverflow++; return;
1125 case Intrinsic::uadd_with_overflow:
1126 NumFastIselFailUAddWithOverflow++; return;
1127 case Intrinsic::ssub_with_overflow:
1128 NumFastIselFailSSubWithOverflow++; return;
1129 case Intrinsic::usub_with_overflow:
1130 NumFastIselFailUSubWithOverflow++; return;
1131 case Intrinsic::smul_with_overflow:
1132 NumFastIselFailSMulWithOverflow++; return;
1133 case Intrinsic::umul_with_overflow:
1134 NumFastIselFailUMulWithOverflow++; return;
1135 case Intrinsic::frameaddress:
1136 NumFastIselFailFrameaddress++; return;
1137 case Intrinsic::sqrt:
1138 NumFastIselFailSqrt++; return;
1139 case Intrinsic::experimental_stackmap:
1140 NumFastIselFailStackMap++; return;
1141 case Intrinsic::experimental_patchpoint_void: // fall-through
1142 case Intrinsic::experimental_patchpoint_i64:
1143 NumFastIselFailPatchPoint++; return;
1146 NumFastIselFailCall++;
1149 case Instruction::Shl: NumFastIselFailShl++; return;
1150 case Instruction::LShr: NumFastIselFailLShr++; return;
1151 case Instruction::AShr: NumFastIselFailAShr++; return;
1152 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1153 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1154 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1155 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1156 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1157 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1158 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1163 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1164 // Initialize the Fast-ISel state, if needed.
1165 FastISel *FastIS = nullptr;
1166 if (TM.Options.EnableFastISel)
1167 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1169 // Iterate over all basic blocks in the function.
1170 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1171 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1172 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1173 const BasicBlock *LLVMBB = *I;
1175 if (OptLevel != CodeGenOpt::None) {
1176 bool AllPredsVisited = true;
1177 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1179 if (!FuncInfo->VisitedBBs.count(*PI)) {
1180 AllPredsVisited = false;
1185 if (AllPredsVisited) {
1186 for (BasicBlock::const_iterator I = LLVMBB->begin();
1187 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1188 FuncInfo->ComputePHILiveOutRegInfo(PN);
1190 for (BasicBlock::const_iterator I = LLVMBB->begin();
1191 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1192 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1195 FuncInfo->VisitedBBs.insert(LLVMBB);
1198 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1199 BasicBlock::const_iterator const End = LLVMBB->end();
1200 BasicBlock::const_iterator BI = End;
1202 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1203 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1205 // Setup an EH landing-pad block.
1206 FuncInfo->ExceptionPointerVirtReg = 0;
1207 FuncInfo->ExceptionSelectorVirtReg = 0;
1208 if (LLVMBB->isLandingPad())
1209 if (!PrepareEHLandingPad())
1212 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1214 FastIS->startNewBlock();
1216 // Emit code for any incoming arguments. This must happen before
1217 // beginning FastISel on the entry block.
1218 if (LLVMBB == &Fn.getEntryBlock()) {
1221 // Lower any arguments needed in this block if this is the entry block.
1222 if (!FastIS->lowerArguments()) {
1223 // Fast isel failed to lower these arguments
1224 ++NumFastIselFailLowerArguments;
1225 if (EnableFastISelAbort > 1)
1226 report_fatal_error("FastISel didn't lower all arguments");
1228 // Use SelectionDAG argument lowering
1230 CurDAG->setRoot(SDB->getControlRoot());
1232 CodeGenAndEmitDAG();
1235 // If we inserted any instructions at the beginning, make a note of
1236 // where they are, so we can be sure to emit subsequent instructions
1238 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1239 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1241 FastIS->setLastLocalValue(nullptr);
1244 unsigned NumFastIselRemaining = std::distance(Begin, End);
1245 // Do FastISel on as many instructions as possible.
1246 for (; BI != Begin; --BI) {
1247 const Instruction *Inst = std::prev(BI);
1249 // If we no longer require this instruction, skip it.
1250 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1251 --NumFastIselRemaining;
1255 // Bottom-up: reset the insert pos at the top, after any local-value
1257 FastIS->recomputeInsertPt();
1259 // Try to select the instruction with FastISel.
1260 if (FastIS->selectInstruction(Inst)) {
1261 --NumFastIselRemaining;
1262 ++NumFastIselSuccess;
1263 // If fast isel succeeded, skip over all the folded instructions, and
1264 // then see if there is a load right before the selected instructions.
1265 // Try to fold the load if so.
1266 const Instruction *BeforeInst = Inst;
1267 while (BeforeInst != Begin) {
1268 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1269 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1272 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1273 BeforeInst->hasOneUse() &&
1274 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1275 // If we succeeded, don't re-select the load.
1276 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1277 --NumFastIselRemaining;
1278 ++NumFastIselSuccess;
1284 if (EnableFastISelVerbose2)
1285 collectFailStats(Inst);
1288 // Then handle certain instructions as single-LLVM-Instruction blocks.
1289 if (isa<CallInst>(Inst)) {
1291 if (EnableFastISelVerbose || EnableFastISelAbort) {
1292 dbgs() << "FastISel missed call: ";
1295 if (EnableFastISelAbort > 2)
1296 // FastISel selector couldn't handle something and bailed.
1297 // For the purpose of debugging, just abort.
1298 report_fatal_error("FastISel didn't select the entire block");
1300 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1301 unsigned &R = FuncInfo->ValueMap[Inst];
1303 R = FuncInfo->CreateRegs(Inst->getType());
1306 bool HadTailCall = false;
1307 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1308 SelectBasicBlock(Inst, BI, HadTailCall);
1310 // If the call was emitted as a tail call, we're done with the block.
1311 // We also need to delete any previously emitted instructions.
1313 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1318 // Recompute NumFastIselRemaining as Selection DAG instruction
1319 // selection may have handled the call, input args, etc.
1320 unsigned RemainingNow = std::distance(Begin, BI);
1321 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1322 NumFastIselRemaining = RemainingNow;
1326 bool ShouldAbort = EnableFastISelAbort;
1327 if (EnableFastISelVerbose || EnableFastISelAbort) {
1328 if (isa<TerminatorInst>(Inst)) {
1329 // Use a different message for terminator misses.
1330 dbgs() << "FastISel missed terminator: ";
1331 // Don't abort unless for terminator unless the level is really high
1332 ShouldAbort = (EnableFastISelAbort > 2);
1334 dbgs() << "FastISel miss: ";
1339 // FastISel selector couldn't handle something and bailed.
1340 // For the purpose of debugging, just abort.
1341 report_fatal_error("FastISel didn't select the entire block");
1343 NumFastIselFailures += NumFastIselRemaining;
1347 FastIS->recomputeInsertPt();
1349 // Lower any arguments needed in this block if this is the entry block.
1350 if (LLVMBB == &Fn.getEntryBlock()) {
1359 ++NumFastIselBlocks;
1362 // Run SelectionDAG instruction selection on the remainder of the block
1363 // not handled by FastISel. If FastISel is not run, this is the entire
1366 SelectBasicBlock(Begin, BI, HadTailCall);
1370 FuncInfo->PHINodesToUpdate.clear();
1374 SDB->clearDanglingDebugInfo();
1375 SDB->SPDescriptor.resetPerFunctionState();
1378 /// Given that the input MI is before a partial terminator sequence TSeq, return
1379 /// true if M + TSeq also a partial terminator sequence.
1381 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1382 /// lowering copy vregs into physical registers, which are then passed into
1383 /// terminator instructors so we can satisfy ABI constraints. A partial
1384 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1385 /// may be the whole terminator sequence).
1386 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1387 // If we do not have a copy or an implicit def, we return true if and only if
1388 // MI is a debug value.
1389 if (!MI->isCopy() && !MI->isImplicitDef())
1390 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1391 // physical registers if there is debug info associated with the terminator
1392 // of our mbb. We want to include said debug info in our terminator
1393 // sequence, so we return true in that case.
1394 return MI->isDebugValue();
1396 // We have left the terminator sequence if we are not doing one of the
1399 // 1. Copying a vreg into a physical register.
1400 // 2. Copying a vreg into a vreg.
1401 // 3. Defining a register via an implicit def.
1403 // OPI should always be a register definition...
1404 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1405 if (!OPI->isReg() || !OPI->isDef())
1408 // Defining any register via an implicit def is always ok.
1409 if (MI->isImplicitDef())
1412 // Grab the copy source...
1413 MachineInstr::const_mop_iterator OPI2 = OPI;
1415 assert(OPI2 != MI->operands_end()
1416 && "Should have a copy implying we should have 2 arguments.");
1418 // Make sure that the copy dest is not a vreg when the copy source is a
1419 // physical register.
1420 if (!OPI2->isReg() ||
1421 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1422 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1428 /// Find the split point at which to splice the end of BB into its success stack
1429 /// protector check machine basic block.
1431 /// On many platforms, due to ABI constraints, terminators, even before register
1432 /// allocation, use physical registers. This creates an issue for us since
1433 /// physical registers at this point can not travel across basic
1434 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1435 /// when they enter functions and moves them through a sequence of copies back
1436 /// into the physical registers right before the terminator creating a
1437 /// ``Terminator Sequence''. This function is searching for the beginning of the
1438 /// terminator sequence so that we can ensure that we splice off not just the
1439 /// terminator, but additionally the copies that move the vregs into the
1440 /// physical registers.
1441 static MachineBasicBlock::iterator
1442 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1443 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1445 if (SplitPoint == BB->begin())
1448 MachineBasicBlock::iterator Start = BB->begin();
1449 MachineBasicBlock::iterator Previous = SplitPoint;
1452 while (MIIsInTerminatorSequence(Previous)) {
1453 SplitPoint = Previous;
1454 if (Previous == Start)
1463 SelectionDAGISel::FinishBasicBlock() {
1465 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1466 << FuncInfo->PHINodesToUpdate.size() << "\n";
1467 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1468 dbgs() << "Node " << i << " : ("
1469 << FuncInfo->PHINodesToUpdate[i].first
1470 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1472 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1473 SDB->JTCases.empty() &&
1474 SDB->BitTestCases.empty();
1476 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1477 // PHI nodes in successors.
1478 if (MustUpdatePHINodes) {
1479 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1480 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1481 assert(PHI->isPHI() &&
1482 "This is not a machine PHI node that we are updating!");
1483 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1485 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1489 // Handle stack protector.
1490 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1491 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1492 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1494 // Find the split point to split the parent mbb. At the same time copy all
1495 // physical registers used in the tail of parent mbb into virtual registers
1496 // before the split point and back into physical registers after the split
1497 // point. This prevents us needing to deal with Live-ins and many other
1498 // register allocation issues caused by us splitting the parent mbb. The
1499 // register allocator will clean up said virtual copies later on.
1500 MachineBasicBlock::iterator SplitPoint =
1501 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1503 // Splice the terminator of ParentMBB into SuccessMBB.
1504 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1508 // Add compare/jump on neq/jump to the parent BB.
1509 FuncInfo->MBB = ParentMBB;
1510 FuncInfo->InsertPt = ParentMBB->end();
1511 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1512 CurDAG->setRoot(SDB->getRoot());
1514 CodeGenAndEmitDAG();
1516 // CodeGen Failure MBB if we have not codegened it yet.
1517 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1518 if (!FailureMBB->size()) {
1519 FuncInfo->MBB = FailureMBB;
1520 FuncInfo->InsertPt = FailureMBB->end();
1521 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1522 CurDAG->setRoot(SDB->getRoot());
1524 CodeGenAndEmitDAG();
1527 // Clear the Per-BB State.
1528 SDB->SPDescriptor.resetPerBBState();
1531 // If we updated PHI Nodes, return early.
1532 if (MustUpdatePHINodes)
1535 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1536 // Lower header first, if it wasn't already lowered
1537 if (!SDB->BitTestCases[i].Emitted) {
1538 // Set the current basic block to the mbb we wish to insert the code into
1539 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1540 FuncInfo->InsertPt = FuncInfo->MBB->end();
1542 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1543 CurDAG->setRoot(SDB->getRoot());
1545 CodeGenAndEmitDAG();
1548 uint32_t UnhandledWeight = 0;
1549 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1550 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1552 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1553 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1554 // Set the current basic block to the mbb we wish to insert the code into
1555 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1556 FuncInfo->InsertPt = FuncInfo->MBB->end();
1559 SDB->visitBitTestCase(SDB->BitTestCases[i],
1560 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1562 SDB->BitTestCases[i].Reg,
1563 SDB->BitTestCases[i].Cases[j],
1566 SDB->visitBitTestCase(SDB->BitTestCases[i],
1567 SDB->BitTestCases[i].Default,
1569 SDB->BitTestCases[i].Reg,
1570 SDB->BitTestCases[i].Cases[j],
1574 CurDAG->setRoot(SDB->getRoot());
1576 CodeGenAndEmitDAG();
1580 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1582 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1583 MachineBasicBlock *PHIBB = PHI->getParent();
1584 assert(PHI->isPHI() &&
1585 "This is not a machine PHI node that we are updating!");
1586 // This is "default" BB. We have two jumps to it. From "header" BB and
1587 // from last "case" BB.
1588 if (PHIBB == SDB->BitTestCases[i].Default)
1589 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1590 .addMBB(SDB->BitTestCases[i].Parent)
1591 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1592 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1593 // One of "cases" BB.
1594 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1596 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1597 if (cBB->isSuccessor(PHIBB))
1598 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1602 SDB->BitTestCases.clear();
1604 // If the JumpTable record is filled in, then we need to emit a jump table.
1605 // Updating the PHI nodes is tricky in this case, since we need to determine
1606 // whether the PHI is a successor of the range check MBB or the jump table MBB
1607 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1608 // Lower header first, if it wasn't already lowered
1609 if (!SDB->JTCases[i].first.Emitted) {
1610 // Set the current basic block to the mbb we wish to insert the code into
1611 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1612 FuncInfo->InsertPt = FuncInfo->MBB->end();
1614 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1616 CurDAG->setRoot(SDB->getRoot());
1618 CodeGenAndEmitDAG();
1621 // Set the current basic block to the mbb we wish to insert the code into
1622 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1623 FuncInfo->InsertPt = FuncInfo->MBB->end();
1625 SDB->visitJumpTable(SDB->JTCases[i].second);
1626 CurDAG->setRoot(SDB->getRoot());
1628 CodeGenAndEmitDAG();
1631 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1633 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1634 MachineBasicBlock *PHIBB = PHI->getParent();
1635 assert(PHI->isPHI() &&
1636 "This is not a machine PHI node that we are updating!");
1637 // "default" BB. We can go there only from header BB.
1638 if (PHIBB == SDB->JTCases[i].second.Default)
1639 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1640 .addMBB(SDB->JTCases[i].first.HeaderBB);
1641 // JT BB. Just iterate over successors here
1642 if (FuncInfo->MBB->isSuccessor(PHIBB))
1643 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1646 SDB->JTCases.clear();
1648 // If the switch block involved a branch to one of the actual successors, we
1649 // need to update PHI nodes in that block.
1650 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1651 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1652 assert(PHI->isPHI() &&
1653 "This is not a machine PHI node that we are updating!");
1654 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1655 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1658 // If we generated any switch lowering information, build and codegen any
1659 // additional DAGs necessary.
1660 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1661 // Set the current basic block to the mbb we wish to insert the code into
1662 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1663 FuncInfo->InsertPt = FuncInfo->MBB->end();
1665 // Determine the unique successors.
1666 SmallVector<MachineBasicBlock *, 2> Succs;
1667 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1668 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1669 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1671 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1672 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1673 CurDAG->setRoot(SDB->getRoot());
1675 CodeGenAndEmitDAG();
1677 // Remember the last block, now that any splitting is done, for use in
1678 // populating PHI nodes in successors.
1679 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1681 // Handle any PHI nodes in successors of this chunk, as if we were coming
1682 // from the original BB before switch expansion. Note that PHI nodes can
1683 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1684 // handle them the right number of times.
1685 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1686 FuncInfo->MBB = Succs[i];
1687 FuncInfo->InsertPt = FuncInfo->MBB->end();
1688 // FuncInfo->MBB may have been removed from the CFG if a branch was
1690 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1691 for (MachineBasicBlock::iterator
1692 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1693 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1694 MachineInstrBuilder PHI(*MF, MBBI);
1695 // This value for this PHI node is recorded in PHINodesToUpdate.
1696 for (unsigned pn = 0; ; ++pn) {
1697 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1698 "Didn't find PHI entry!");
1699 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1700 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1708 SDB->SwitchCases.clear();
1712 /// Create the scheduler. If a specific scheduler was specified
1713 /// via the SchedulerRegistry, use it, otherwise select the
1714 /// one preferred by the target.
1716 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1717 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1721 RegisterScheduler::setDefault(Ctor);
1724 return Ctor(this, OptLevel);
1727 //===----------------------------------------------------------------------===//
1728 // Helper functions used by the generated instruction selector.
1729 //===----------------------------------------------------------------------===//
1730 // Calls to these methods are generated by tblgen.
1732 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1733 /// the dag combiner simplified the 255, we still want to match. RHS is the
1734 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1735 /// specified in the .td file (e.g. 255).
1736 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1737 int64_t DesiredMaskS) const {
1738 const APInt &ActualMask = RHS->getAPIntValue();
1739 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1741 // If the actual mask exactly matches, success!
1742 if (ActualMask == DesiredMask)
1745 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1746 if (ActualMask.intersects(~DesiredMask))
1749 // Otherwise, the DAG Combiner may have proven that the value coming in is
1750 // either already zero or is not demanded. Check for known zero input bits.
1751 APInt NeededMask = DesiredMask & ~ActualMask;
1752 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1755 // TODO: check to see if missing bits are just not demanded.
1757 // Otherwise, this pattern doesn't match.
1761 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1762 /// the dag combiner simplified the 255, we still want to match. RHS is the
1763 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1764 /// specified in the .td file (e.g. 255).
1765 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1766 int64_t DesiredMaskS) const {
1767 const APInt &ActualMask = RHS->getAPIntValue();
1768 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1770 // If the actual mask exactly matches, success!
1771 if (ActualMask == DesiredMask)
1774 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1775 if (ActualMask.intersects(~DesiredMask))
1778 // Otherwise, the DAG Combiner may have proven that the value coming in is
1779 // either already zero or is not demanded. Check for known zero input bits.
1780 APInt NeededMask = DesiredMask & ~ActualMask;
1782 APInt KnownZero, KnownOne;
1783 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1785 // If all the missing bits in the or are already known to be set, match!
1786 if ((NeededMask & KnownOne) == NeededMask)
1789 // TODO: check to see if missing bits are just not demanded.
1791 // Otherwise, this pattern doesn't match.
1796 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1797 /// by tblgen. Others should not call it.
1798 void SelectionDAGISel::
1799 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1800 std::vector<SDValue> InOps;
1801 std::swap(InOps, Ops);
1803 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1804 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1805 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1806 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1808 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1809 if (InOps[e-1].getValueType() == MVT::Glue)
1810 --e; // Don't process a glue operand if it is here.
1813 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1814 if (!InlineAsm::isMemKind(Flags)) {
1815 // Just skip over this operand, copying the operands verbatim.
1816 Ops.insert(Ops.end(), InOps.begin()+i,
1817 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1818 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1820 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1821 "Memory operand with multiple values?");
1823 unsigned TiedToOperand;
1824 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1825 // We need the constraint ID from the operand this is tied to.
1826 unsigned CurOp = InlineAsm::Op_FirstOperand;
1827 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1828 for (; TiedToOperand; --TiedToOperand) {
1829 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1830 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1834 // Otherwise, this is a memory operand. Ask the target to select it.
1835 std::vector<SDValue> SelOps;
1836 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1837 InlineAsm::getMemoryConstraintID(Flags),
1839 report_fatal_error("Could not match memory address. Inline asm"
1842 // Add this to the output node.
1844 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1845 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1846 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1851 // Add the glue input back if present.
1852 if (e != InOps.size())
1853 Ops.push_back(InOps.back());
1856 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1859 static SDNode *findGlueUse(SDNode *N) {
1860 unsigned FlagResNo = N->getNumValues()-1;
1861 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1862 SDUse &Use = I.getUse();
1863 if (Use.getResNo() == FlagResNo)
1864 return Use.getUser();
1869 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1870 /// This function recursively traverses up the operand chain, ignoring
1872 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1873 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1874 bool IgnoreChains) {
1875 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1876 // greater than all of its (recursive) operands. If we scan to a point where
1877 // 'use' is smaller than the node we're scanning for, then we know we will
1880 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1881 // happen because we scan down to newly selected nodes in the case of glue
1883 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1886 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1887 // won't fail if we scan it again.
1888 if (!Visited.insert(Use).second)
1891 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1892 // Ignore chain uses, they are validated by HandleMergeInputChains.
1893 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1896 SDNode *N = Use->getOperand(i).getNode();
1898 if (Use == ImmedUse || Use == Root)
1899 continue; // We are not looking for immediate use.
1904 // Traverse up the operand chain.
1905 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1911 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1912 /// operand node N of U during instruction selection that starts at Root.
1913 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1914 SDNode *Root) const {
1915 if (OptLevel == CodeGenOpt::None) return false;
1916 return N.hasOneUse();
1919 /// IsLegalToFold - Returns true if the specific operand node N of
1920 /// U can be folded during instruction selection that starts at Root.
1921 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1922 CodeGenOpt::Level OptLevel,
1923 bool IgnoreChains) {
1924 if (OptLevel == CodeGenOpt::None) return false;
1926 // If Root use can somehow reach N through a path that that doesn't contain
1927 // U then folding N would create a cycle. e.g. In the following
1928 // diagram, Root can reach N through X. If N is folded into into Root, then
1929 // X is both a predecessor and a successor of U.
1940 // * indicates nodes to be folded together.
1942 // If Root produces glue, then it gets (even more) interesting. Since it
1943 // will be "glued" together with its glue use in the scheduler, we need to
1944 // check if it might reach N.
1963 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1964 // (call it Fold), then X is a predecessor of GU and a successor of
1965 // Fold. But since Fold and GU are glued together, this will create
1966 // a cycle in the scheduling graph.
1968 // If the node has glue, walk down the graph to the "lowest" node in the
1970 EVT VT = Root->getValueType(Root->getNumValues()-1);
1971 while (VT == MVT::Glue) {
1972 SDNode *GU = findGlueUse(Root);
1976 VT = Root->getValueType(Root->getNumValues()-1);
1978 // If our query node has a glue result with a use, we've walked up it. If
1979 // the user (which has already been selected) has a chain or indirectly uses
1980 // the chain, our WalkChainUsers predicate will not consider it. Because of
1981 // this, we cannot ignore chains in this predicate.
1982 IgnoreChains = false;
1986 SmallPtrSet<SDNode*, 16> Visited;
1987 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1990 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1991 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1992 SelectInlineAsmMemoryOperands(Ops);
1994 const EVT VTs[] = {MVT::Other, MVT::Glue};
1995 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1997 return New.getNode();
2001 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
2003 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
2004 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2006 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
2007 SDValue New = CurDAG->getCopyFromReg(
2008 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
2010 return New.getNode();
2014 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
2016 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
2017 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2018 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
2019 Op->getOperand(2).getValueType());
2020 SDValue New = CurDAG->getCopyToReg(
2021 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
2023 return New.getNode();
2028 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
2029 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
2032 /// GetVBR - decode a vbr encoding whose top bit is set.
2033 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
2034 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
2035 assert(Val >= 128 && "Not a VBR");
2036 Val &= 127; // Remove first vbr bit.
2041 NextBits = MatcherTable[Idx++];
2042 Val |= (NextBits&127) << Shift;
2044 } while (NextBits & 128);
2050 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
2051 /// interior glue and chain results to use the new glue and chain results.
2052 void SelectionDAGISel::
2053 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
2054 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
2056 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
2057 bool isMorphNodeTo) {
2058 SmallVector<SDNode*, 4> NowDeadNodes;
2060 // Now that all the normal results are replaced, we replace the chain and
2061 // glue results if present.
2062 if (!ChainNodesMatched.empty()) {
2063 assert(InputChain.getNode() &&
2064 "Matched input chains but didn't produce a chain");
2065 // Loop over all of the nodes we matched that produced a chain result.
2066 // Replace all the chain results with the final chain we ended up with.
2067 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2068 SDNode *ChainNode = ChainNodesMatched[i];
2070 // If this node was already deleted, don't look at it.
2071 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2074 // Don't replace the results of the root node if we're doing a
2076 if (ChainNode == NodeToMatch && isMorphNodeTo)
2079 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2080 if (ChainVal.getValueType() == MVT::Glue)
2081 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2082 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2083 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2085 // If the node became dead and we haven't already seen it, delete it.
2086 if (ChainNode->use_empty() &&
2087 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2088 NowDeadNodes.push_back(ChainNode);
2092 // If the result produces glue, update any glue results in the matched
2093 // pattern with the glue result.
2094 if (InputGlue.getNode()) {
2095 // Handle any interior nodes explicitly marked.
2096 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2097 SDNode *FRN = GlueResultNodesMatched[i];
2099 // If this node was already deleted, don't look at it.
2100 if (FRN->getOpcode() == ISD::DELETED_NODE)
2103 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2104 "Doesn't have a glue result");
2105 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2108 // If the node became dead and we haven't already seen it, delete it.
2109 if (FRN->use_empty() &&
2110 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2111 NowDeadNodes.push_back(FRN);
2115 if (!NowDeadNodes.empty())
2116 CurDAG->RemoveDeadNodes(NowDeadNodes);
2118 DEBUG(dbgs() << "ISEL: Match complete!\n");
2124 CR_LeadsToInteriorNode
2127 /// WalkChainUsers - Walk down the users of the specified chained node that is
2128 /// part of the pattern we're matching, looking at all of the users we find.
2129 /// This determines whether something is an interior node, whether we have a
2130 /// non-pattern node in between two pattern nodes (which prevent folding because
2131 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2132 /// between pattern nodes (in which case the TF becomes part of the pattern).
2134 /// The walk we do here is guaranteed to be small because we quickly get down to
2135 /// already selected nodes "below" us.
2137 WalkChainUsers(const SDNode *ChainedNode,
2138 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2139 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2140 ChainResult Result = CR_Simple;
2142 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2143 E = ChainedNode->use_end(); UI != E; ++UI) {
2144 // Make sure the use is of the chain, not some other value we produce.
2145 if (UI.getUse().getValueType() != MVT::Other) continue;
2149 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2152 // If we see an already-selected machine node, then we've gone beyond the
2153 // pattern that we're selecting down into the already selected chunk of the
2155 unsigned UserOpcode = User->getOpcode();
2156 if (User->isMachineOpcode() ||
2157 UserOpcode == ISD::CopyToReg ||
2158 UserOpcode == ISD::CopyFromReg ||
2159 UserOpcode == ISD::INLINEASM ||
2160 UserOpcode == ISD::EH_LABEL ||
2161 UserOpcode == ISD::LIFETIME_START ||
2162 UserOpcode == ISD::LIFETIME_END) {
2163 // If their node ID got reset to -1 then they've already been selected.
2164 // Treat them like a MachineOpcode.
2165 if (User->getNodeId() == -1)
2169 // If we have a TokenFactor, we handle it specially.
2170 if (User->getOpcode() != ISD::TokenFactor) {
2171 // If the node isn't a token factor and isn't part of our pattern, then it
2172 // must be a random chained node in between two nodes we're selecting.
2173 // This happens when we have something like:
2178 // Because we structurally match the load/store as a read/modify/write,
2179 // but the call is chained between them. We cannot fold in this case
2180 // because it would induce a cycle in the graph.
2181 if (!std::count(ChainedNodesInPattern.begin(),
2182 ChainedNodesInPattern.end(), User))
2183 return CR_InducesCycle;
2185 // Otherwise we found a node that is part of our pattern. For example in:
2189 // This would happen when we're scanning down from the load and see the
2190 // store as a user. Record that there is a use of ChainedNode that is
2191 // part of the pattern and keep scanning uses.
2192 Result = CR_LeadsToInteriorNode;
2193 InteriorChainedNodes.push_back(User);
2197 // If we found a TokenFactor, there are two cases to consider: first if the
2198 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2199 // uses of the TF are in our pattern) we just want to ignore it. Second,
2200 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2206 // | \ DAG's like cheese
2209 // [TokenFactor] [Op]
2216 // In this case, the TokenFactor becomes part of our match and we rewrite it
2217 // as a new TokenFactor.
2219 // To distinguish these two cases, do a recursive walk down the uses.
2220 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2222 // If the uses of the TokenFactor are just already-selected nodes, ignore
2223 // it, it is "below" our pattern.
2225 case CR_InducesCycle:
2226 // If the uses of the TokenFactor lead to nodes that are not part of our
2227 // pattern that are not selected, folding would turn this into a cycle,
2229 return CR_InducesCycle;
2230 case CR_LeadsToInteriorNode:
2231 break; // Otherwise, keep processing.
2234 // Okay, we know we're in the interesting interior case. The TokenFactor
2235 // is now going to be considered part of the pattern so that we rewrite its
2236 // uses (it may have uses that are not part of the pattern) with the
2237 // ultimate chain result of the generated code. We will also add its chain
2238 // inputs as inputs to the ultimate TokenFactor we create.
2239 Result = CR_LeadsToInteriorNode;
2240 ChainedNodesInPattern.push_back(User);
2241 InteriorChainedNodes.push_back(User);
2248 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2249 /// operation for when the pattern matched at least one node with a chains. The
2250 /// input vector contains a list of all of the chained nodes that we match. We
2251 /// must determine if this is a valid thing to cover (i.e. matching it won't
2252 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2253 /// be used as the input node chain for the generated nodes.
2255 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2256 SelectionDAG *CurDAG) {
2257 // Walk all of the chained nodes we've matched, recursively scanning down the
2258 // users of the chain result. This adds any TokenFactor nodes that are caught
2259 // in between chained nodes to the chained and interior nodes list.
2260 SmallVector<SDNode*, 3> InteriorChainedNodes;
2261 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2262 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2263 InteriorChainedNodes) == CR_InducesCycle)
2264 return SDValue(); // Would induce a cycle.
2267 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2268 // that we are interested in. Form our input TokenFactor node.
2269 SmallVector<SDValue, 3> InputChains;
2270 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2271 // Add the input chain of this node to the InputChains list (which will be
2272 // the operands of the generated TokenFactor) if it's not an interior node.
2273 SDNode *N = ChainNodesMatched[i];
2274 if (N->getOpcode() != ISD::TokenFactor) {
2275 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2278 // Otherwise, add the input chain.
2279 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2280 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2281 InputChains.push_back(InChain);
2285 // If we have a token factor, we want to add all inputs of the token factor
2286 // that are not part of the pattern we're matching.
2287 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2288 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2289 N->getOperand(op).getNode()))
2290 InputChains.push_back(N->getOperand(op));
2294 if (InputChains.size() == 1)
2295 return InputChains[0];
2296 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2297 MVT::Other, InputChains);
2300 /// MorphNode - Handle morphing a node in place for the selector.
2301 SDNode *SelectionDAGISel::
2302 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2303 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2304 // It is possible we're using MorphNodeTo to replace a node with no
2305 // normal results with one that has a normal result (or we could be
2306 // adding a chain) and the input could have glue and chains as well.
2307 // In this case we need to shift the operands down.
2308 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2309 // than the old isel though.
2310 int OldGlueResultNo = -1, OldChainResultNo = -1;
2312 unsigned NTMNumResults = Node->getNumValues();
2313 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2314 OldGlueResultNo = NTMNumResults-1;
2315 if (NTMNumResults != 1 &&
2316 Node->getValueType(NTMNumResults-2) == MVT::Other)
2317 OldChainResultNo = NTMNumResults-2;
2318 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2319 OldChainResultNo = NTMNumResults-1;
2321 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2322 // that this deletes operands of the old node that become dead.
2323 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2325 // MorphNodeTo can operate in two ways: if an existing node with the
2326 // specified operands exists, it can just return it. Otherwise, it
2327 // updates the node in place to have the requested operands.
2329 // If we updated the node in place, reset the node ID. To the isel,
2330 // this should be just like a newly allocated machine node.
2334 unsigned ResNumResults = Res->getNumValues();
2335 // Move the glue if needed.
2336 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2337 (unsigned)OldGlueResultNo != ResNumResults-1)
2338 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2339 SDValue(Res, ResNumResults-1));
2341 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2344 // Move the chain reference if needed.
2345 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2346 (unsigned)OldChainResultNo != ResNumResults-1)
2347 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2348 SDValue(Res, ResNumResults-1));
2350 // Otherwise, no replacement happened because the node already exists. Replace
2351 // Uses of the old node with the new one.
2353 CurDAG->ReplaceAllUsesWith(Node, Res);
2358 /// CheckSame - Implements OP_CheckSame.
2359 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2360 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2362 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2363 // Accept if it is exactly the same as a previously recorded node.
2364 unsigned RecNo = MatcherTable[MatcherIndex++];
2365 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2366 return N == RecordedNodes[RecNo].first;
2369 /// CheckChildSame - Implements OP_CheckChildXSame.
2370 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2371 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2373 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2375 if (ChildNo >= N.getNumOperands())
2376 return false; // Match fails if out of range child #.
2377 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2381 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2382 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2383 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2384 const SelectionDAGISel &SDISel) {
2385 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2388 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2389 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2390 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2391 const SelectionDAGISel &SDISel, SDNode *N) {
2392 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2395 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2396 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2398 uint16_t Opc = MatcherTable[MatcherIndex++];
2399 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2400 return N->getOpcode() == Opc;
2403 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2404 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2405 SDValue N, const TargetLowering *TLI) {
2406 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2407 if (N.getValueType() == VT) return true;
2409 // Handle the case when VT is iPTR.
2410 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2413 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2414 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2415 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2416 if (ChildNo >= N.getNumOperands())
2417 return false; // Match fails if out of range child #.
2418 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2421 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2422 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2424 return cast<CondCodeSDNode>(N)->get() ==
2425 (ISD::CondCode)MatcherTable[MatcherIndex++];
2428 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2429 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2430 SDValue N, const TargetLowering *TLI) {
2431 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2432 if (cast<VTSDNode>(N)->getVT() == VT)
2435 // Handle the case when VT is iPTR.
2436 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2439 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2440 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2442 int64_t Val = MatcherTable[MatcherIndex++];
2444 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2446 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2447 return C && C->getSExtValue() == Val;
2450 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2451 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2452 SDValue N, unsigned ChildNo) {
2453 if (ChildNo >= N.getNumOperands())
2454 return false; // Match fails if out of range child #.
2455 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2458 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2459 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2460 SDValue N, const SelectionDAGISel &SDISel) {
2461 int64_t Val = MatcherTable[MatcherIndex++];
2463 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2465 if (N->getOpcode() != ISD::AND) return false;
2467 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2468 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2471 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2472 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2473 SDValue N, const SelectionDAGISel &SDISel) {
2474 int64_t Val = MatcherTable[MatcherIndex++];
2476 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2478 if (N->getOpcode() != ISD::OR) return false;
2480 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2481 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2484 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2485 /// scope, evaluate the current node. If the current predicate is known to
2486 /// fail, set Result=true and return anything. If the current predicate is
2487 /// known to pass, set Result=false and return the MatcherIndex to continue
2488 /// with. If the current predicate is unknown, set Result=false and return the
2489 /// MatcherIndex to continue with.
2490 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2491 unsigned Index, SDValue N,
2493 const SelectionDAGISel &SDISel,
2494 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2495 switch (Table[Index++]) {
2498 return Index-1; // Could not evaluate this predicate.
2499 case SelectionDAGISel::OPC_CheckSame:
2500 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2502 case SelectionDAGISel::OPC_CheckChild0Same:
2503 case SelectionDAGISel::OPC_CheckChild1Same:
2504 case SelectionDAGISel::OPC_CheckChild2Same:
2505 case SelectionDAGISel::OPC_CheckChild3Same:
2506 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2507 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2509 case SelectionDAGISel::OPC_CheckPatternPredicate:
2510 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2512 case SelectionDAGISel::OPC_CheckPredicate:
2513 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2515 case SelectionDAGISel::OPC_CheckOpcode:
2516 Result = !::CheckOpcode(Table, Index, N.getNode());
2518 case SelectionDAGISel::OPC_CheckType:
2519 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2521 case SelectionDAGISel::OPC_CheckChild0Type:
2522 case SelectionDAGISel::OPC_CheckChild1Type:
2523 case SelectionDAGISel::OPC_CheckChild2Type:
2524 case SelectionDAGISel::OPC_CheckChild3Type:
2525 case SelectionDAGISel::OPC_CheckChild4Type:
2526 case SelectionDAGISel::OPC_CheckChild5Type:
2527 case SelectionDAGISel::OPC_CheckChild6Type:
2528 case SelectionDAGISel::OPC_CheckChild7Type:
2529 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2531 SelectionDAGISel::OPC_CheckChild0Type);
2533 case SelectionDAGISel::OPC_CheckCondCode:
2534 Result = !::CheckCondCode(Table, Index, N);
2536 case SelectionDAGISel::OPC_CheckValueType:
2537 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2539 case SelectionDAGISel::OPC_CheckInteger:
2540 Result = !::CheckInteger(Table, Index, N);
2542 case SelectionDAGISel::OPC_CheckChild0Integer:
2543 case SelectionDAGISel::OPC_CheckChild1Integer:
2544 case SelectionDAGISel::OPC_CheckChild2Integer:
2545 case SelectionDAGISel::OPC_CheckChild3Integer:
2546 case SelectionDAGISel::OPC_CheckChild4Integer:
2547 Result = !::CheckChildInteger(Table, Index, N,
2548 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2550 case SelectionDAGISel::OPC_CheckAndImm:
2551 Result = !::CheckAndImm(Table, Index, N, SDISel);
2553 case SelectionDAGISel::OPC_CheckOrImm:
2554 Result = !::CheckOrImm(Table, Index, N, SDISel);
2562 /// FailIndex - If this match fails, this is the index to continue with.
2565 /// NodeStack - The node stack when the scope was formed.
2566 SmallVector<SDValue, 4> NodeStack;
2568 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2569 unsigned NumRecordedNodes;
2571 /// NumMatchedMemRefs - The number of matched memref entries.
2572 unsigned NumMatchedMemRefs;
2574 /// InputChain/InputGlue - The current chain/glue
2575 SDValue InputChain, InputGlue;
2577 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2578 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2581 /// \\brief A DAG update listener to keep the matching state
2582 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2583 /// change the DAG while matching. X86 addressing mode matcher is an example
2585 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2587 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2588 SmallVectorImpl<MatchScope> &MatchScopes;
2590 MatchStateUpdater(SelectionDAG &DAG,
2591 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2592 SmallVectorImpl<MatchScope> &MS) :
2593 SelectionDAG::DAGUpdateListener(DAG),
2594 RecordedNodes(RN), MatchScopes(MS) { }
2596 void NodeDeleted(SDNode *N, SDNode *E) override {
2597 // Some early-returns here to avoid the search if we deleted the node or
2598 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2599 // do, so it's unnecessary to update matching state at that point).
2600 // Neither of these can occur currently because we only install this
2601 // update listener during matching a complex patterns.
2602 if (!E || E->isMachineOpcode())
2604 // Performing linear search here does not matter because we almost never
2605 // run this code. You'd have to have a CSE during complex pattern
2607 for (auto &I : RecordedNodes)
2608 if (I.first.getNode() == N)
2611 for (auto &I : MatchScopes)
2612 for (auto &J : I.NodeStack)
2613 if (J.getNode() == N)
2619 SDNode *SelectionDAGISel::
2620 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2621 unsigned TableSize) {
2622 // FIXME: Should these even be selected? Handle these cases in the caller?
2623 switch (NodeToMatch->getOpcode()) {
2626 case ISD::EntryToken: // These nodes remain the same.
2627 case ISD::BasicBlock:
2629 case ISD::RegisterMask:
2630 case ISD::HANDLENODE:
2631 case ISD::MDNODE_SDNODE:
2632 case ISD::TargetConstant:
2633 case ISD::TargetConstantFP:
2634 case ISD::TargetConstantPool:
2635 case ISD::TargetFrameIndex:
2636 case ISD::TargetExternalSymbol:
2637 case ISD::TargetBlockAddress:
2638 case ISD::TargetJumpTable:
2639 case ISD::TargetGlobalTLSAddress:
2640 case ISD::TargetGlobalAddress:
2641 case ISD::TokenFactor:
2642 case ISD::CopyFromReg:
2643 case ISD::CopyToReg:
2645 case ISD::LIFETIME_START:
2646 case ISD::LIFETIME_END:
2647 NodeToMatch->setNodeId(-1); // Mark selected.
2649 case ISD::AssertSext:
2650 case ISD::AssertZext:
2651 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2652 NodeToMatch->getOperand(0));
2654 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2655 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2656 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2657 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2660 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2662 // Set up the node stack with NodeToMatch as the only node on the stack.
2663 SmallVector<SDValue, 8> NodeStack;
2664 SDValue N = SDValue(NodeToMatch, 0);
2665 NodeStack.push_back(N);
2667 // MatchScopes - Scopes used when matching, if a match failure happens, this
2668 // indicates where to continue checking.
2669 SmallVector<MatchScope, 8> MatchScopes;
2671 // RecordedNodes - This is the set of nodes that have been recorded by the
2672 // state machine. The second value is the parent of the node, or null if the
2673 // root is recorded.
2674 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2676 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2678 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2680 // These are the current input chain and glue for use when generating nodes.
2681 // Various Emit operations change these. For example, emitting a copytoreg
2682 // uses and updates these.
2683 SDValue InputChain, InputGlue;
2685 // ChainNodesMatched - If a pattern matches nodes that have input/output
2686 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2687 // which ones they are. The result is captured into this list so that we can
2688 // update the chain results when the pattern is complete.
2689 SmallVector<SDNode*, 3> ChainNodesMatched;
2690 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2692 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2693 NodeToMatch->dump(CurDAG);
2696 // Determine where to start the interpreter. Normally we start at opcode #0,
2697 // but if the state machine starts with an OPC_SwitchOpcode, then we
2698 // accelerate the first lookup (which is guaranteed to be hot) with the
2699 // OpcodeOffset table.
2700 unsigned MatcherIndex = 0;
2702 if (!OpcodeOffset.empty()) {
2703 // Already computed the OpcodeOffset table, just index into it.
2704 if (N.getOpcode() < OpcodeOffset.size())
2705 MatcherIndex = OpcodeOffset[N.getOpcode()];
2706 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2708 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2709 // Otherwise, the table isn't computed, but the state machine does start
2710 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2711 // is the first time we're selecting an instruction.
2714 // Get the size of this case.
2715 unsigned CaseSize = MatcherTable[Idx++];
2717 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2718 if (CaseSize == 0) break;
2720 // Get the opcode, add the index to the table.
2721 uint16_t Opc = MatcherTable[Idx++];
2722 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2723 if (Opc >= OpcodeOffset.size())
2724 OpcodeOffset.resize((Opc+1)*2);
2725 OpcodeOffset[Opc] = Idx;
2729 // Okay, do the lookup for the first opcode.
2730 if (N.getOpcode() < OpcodeOffset.size())
2731 MatcherIndex = OpcodeOffset[N.getOpcode()];
2735 assert(MatcherIndex < TableSize && "Invalid index");
2737 unsigned CurrentOpcodeIndex = MatcherIndex;
2739 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2742 // Okay, the semantics of this operation are that we should push a scope
2743 // then evaluate the first child. However, pushing a scope only to have
2744 // the first check fail (which then pops it) is inefficient. If we can
2745 // determine immediately that the first check (or first several) will
2746 // immediately fail, don't even bother pushing a scope for them.
2750 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2751 if (NumToSkip & 128)
2752 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2753 // Found the end of the scope with no match.
2754 if (NumToSkip == 0) {
2759 FailIndex = MatcherIndex+NumToSkip;
2761 unsigned MatcherIndexOfPredicate = MatcherIndex;
2762 (void)MatcherIndexOfPredicate; // silence warning.
2764 // If we can't evaluate this predicate without pushing a scope (e.g. if
2765 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2766 // push the scope and evaluate the full predicate chain.
2768 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2769 Result, *this, RecordedNodes);
2773 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2774 << "index " << MatcherIndexOfPredicate
2775 << ", continuing at " << FailIndex << "\n");
2776 ++NumDAGIselRetries;
2778 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2779 // move to the next case.
2780 MatcherIndex = FailIndex;
2783 // If the whole scope failed to match, bail.
2784 if (FailIndex == 0) break;
2786 // Push a MatchScope which indicates where to go if the first child fails
2788 MatchScope NewEntry;
2789 NewEntry.FailIndex = FailIndex;
2790 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2791 NewEntry.NumRecordedNodes = RecordedNodes.size();
2792 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2793 NewEntry.InputChain = InputChain;
2794 NewEntry.InputGlue = InputGlue;
2795 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2796 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2797 MatchScopes.push_back(NewEntry);
2800 case OPC_RecordNode: {
2801 // Remember this node, it may end up being an operand in the pattern.
2802 SDNode *Parent = nullptr;
2803 if (NodeStack.size() > 1)
2804 Parent = NodeStack[NodeStack.size()-2].getNode();
2805 RecordedNodes.push_back(std::make_pair(N, Parent));
2809 case OPC_RecordChild0: case OPC_RecordChild1:
2810 case OPC_RecordChild2: case OPC_RecordChild3:
2811 case OPC_RecordChild4: case OPC_RecordChild5:
2812 case OPC_RecordChild6: case OPC_RecordChild7: {
2813 unsigned ChildNo = Opcode-OPC_RecordChild0;
2814 if (ChildNo >= N.getNumOperands())
2815 break; // Match fails if out of range child #.
2817 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2821 case OPC_RecordMemRef:
2822 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2825 case OPC_CaptureGlueInput:
2826 // If the current node has an input glue, capture it in InputGlue.
2827 if (N->getNumOperands() != 0 &&
2828 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2829 InputGlue = N->getOperand(N->getNumOperands()-1);
2832 case OPC_MoveChild: {
2833 unsigned ChildNo = MatcherTable[MatcherIndex++];
2834 if (ChildNo >= N.getNumOperands())
2835 break; // Match fails if out of range child #.
2836 N = N.getOperand(ChildNo);
2837 NodeStack.push_back(N);
2841 case OPC_MoveParent:
2842 // Pop the current node off the NodeStack.
2843 NodeStack.pop_back();
2844 assert(!NodeStack.empty() && "Node stack imbalance!");
2845 N = NodeStack.back();
2849 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2852 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2853 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2854 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2855 Opcode-OPC_CheckChild0Same))
2859 case OPC_CheckPatternPredicate:
2860 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2862 case OPC_CheckPredicate:
2863 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2867 case OPC_CheckComplexPat: {
2868 unsigned CPNum = MatcherTable[MatcherIndex++];
2869 unsigned RecNo = MatcherTable[MatcherIndex++];
2870 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2872 // If target can modify DAG during matching, keep the matching state
2874 std::unique_ptr<MatchStateUpdater> MSU;
2875 if (ComplexPatternFuncMutatesDAG())
2876 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2879 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2880 RecordedNodes[RecNo].first, CPNum,
2885 case OPC_CheckOpcode:
2886 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2890 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2894 case OPC_SwitchOpcode: {
2895 unsigned CurNodeOpcode = N.getOpcode();
2896 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2899 // Get the size of this case.
2900 CaseSize = MatcherTable[MatcherIndex++];
2902 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2903 if (CaseSize == 0) break;
2905 uint16_t Opc = MatcherTable[MatcherIndex++];
2906 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2908 // If the opcode matches, then we will execute this case.
2909 if (CurNodeOpcode == Opc)
2912 // Otherwise, skip over this case.
2913 MatcherIndex += CaseSize;
2916 // If no cases matched, bail out.
2917 if (CaseSize == 0) break;
2919 // Otherwise, execute the case we found.
2920 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2921 << " to " << MatcherIndex << "\n");
2925 case OPC_SwitchType: {
2926 MVT CurNodeVT = N.getSimpleValueType();
2927 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2930 // Get the size of this case.
2931 CaseSize = MatcherTable[MatcherIndex++];
2933 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2934 if (CaseSize == 0) break;
2936 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2937 if (CaseVT == MVT::iPTR)
2938 CaseVT = TLI->getPointerTy();
2940 // If the VT matches, then we will execute this case.
2941 if (CurNodeVT == CaseVT)
2944 // Otherwise, skip over this case.
2945 MatcherIndex += CaseSize;
2948 // If no cases matched, bail out.
2949 if (CaseSize == 0) break;
2951 // Otherwise, execute the case we found.
2952 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2953 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2956 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2957 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2958 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2959 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2960 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2961 Opcode-OPC_CheckChild0Type))
2964 case OPC_CheckCondCode:
2965 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2967 case OPC_CheckValueType:
2968 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2971 case OPC_CheckInteger:
2972 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2974 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2975 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2976 case OPC_CheckChild4Integer:
2977 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2978 Opcode-OPC_CheckChild0Integer)) break;
2980 case OPC_CheckAndImm:
2981 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2983 case OPC_CheckOrImm:
2984 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2987 case OPC_CheckFoldableChainNode: {
2988 assert(NodeStack.size() != 1 && "No parent node");
2989 // Verify that all intermediate nodes between the root and this one have
2991 bool HasMultipleUses = false;
2992 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2993 if (!NodeStack[i].hasOneUse()) {
2994 HasMultipleUses = true;
2997 if (HasMultipleUses) break;
2999 // Check to see that the target thinks this is profitable to fold and that
3000 // we can fold it without inducing cycles in the graph.
3001 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
3003 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
3004 NodeToMatch, OptLevel,
3005 true/*We validate our own chains*/))
3010 case OPC_EmitInteger: {
3011 MVT::SimpleValueType VT =
3012 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3013 int64_t Val = MatcherTable[MatcherIndex++];
3015 Val = GetVBR(Val, MatcherTable, MatcherIndex);
3016 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3017 CurDAG->getTargetConstant(Val, VT), nullptr));
3020 case OPC_EmitRegister: {
3021 MVT::SimpleValueType VT =
3022 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3023 unsigned RegNo = MatcherTable[MatcherIndex++];
3024 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3025 CurDAG->getRegister(RegNo, VT), nullptr));
3028 case OPC_EmitRegister2: {
3029 // For targets w/ more than 256 register names, the register enum
3030 // values are stored in two bytes in the matcher table (just like
3032 MVT::SimpleValueType VT =
3033 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3034 unsigned RegNo = MatcherTable[MatcherIndex++];
3035 RegNo |= MatcherTable[MatcherIndex++] << 8;
3036 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3037 CurDAG->getRegister(RegNo, VT), nullptr));
3041 case OPC_EmitConvertToTarget: {
3042 // Convert from IMM/FPIMM to target version.
3043 unsigned RecNo = MatcherTable[MatcherIndex++];
3044 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
3045 SDValue Imm = RecordedNodes[RecNo].first;
3047 if (Imm->getOpcode() == ISD::Constant) {
3048 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
3049 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
3050 } else if (Imm->getOpcode() == ISD::ConstantFP) {
3051 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
3052 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
3055 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3059 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3060 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3061 // These are space-optimized forms of OPC_EmitMergeInputChains.
3062 assert(!InputChain.getNode() &&
3063 "EmitMergeInputChains should be the first chain producing node");
3064 assert(ChainNodesMatched.empty() &&
3065 "Should only have one EmitMergeInputChains per match");
3067 // Read all of the chained nodes.
3068 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3069 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3070 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3072 // FIXME: What if other value results of the node have uses not matched
3074 if (ChainNodesMatched.back() != NodeToMatch &&
3075 !RecordedNodes[RecNo].first.hasOneUse()) {
3076 ChainNodesMatched.clear();
3080 // Merge the input chains if they are not intra-pattern references.
3081 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3083 if (!InputChain.getNode())
3084 break; // Failed to merge.
3088 case OPC_EmitMergeInputChains: {
3089 assert(!InputChain.getNode() &&
3090 "EmitMergeInputChains should be the first chain producing node");
3091 // This node gets a list of nodes we matched in the input that have
3092 // chains. We want to token factor all of the input chains to these nodes
3093 // together. However, if any of the input chains is actually one of the
3094 // nodes matched in this pattern, then we have an intra-match reference.
3095 // Ignore these because the newly token factored chain should not refer to
3097 unsigned NumChains = MatcherTable[MatcherIndex++];
3098 assert(NumChains != 0 && "Can't TF zero chains");
3100 assert(ChainNodesMatched.empty() &&
3101 "Should only have one EmitMergeInputChains per match");
3103 // Read all of the chained nodes.
3104 for (unsigned i = 0; i != NumChains; ++i) {
3105 unsigned RecNo = MatcherTable[MatcherIndex++];
3106 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3107 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3109 // FIXME: What if other value results of the node have uses not matched
3111 if (ChainNodesMatched.back() != NodeToMatch &&
3112 !RecordedNodes[RecNo].first.hasOneUse()) {
3113 ChainNodesMatched.clear();
3118 // If the inner loop broke out, the match fails.
3119 if (ChainNodesMatched.empty())
3122 // Merge the input chains if they are not intra-pattern references.
3123 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3125 if (!InputChain.getNode())
3126 break; // Failed to merge.
3131 case OPC_EmitCopyToReg: {
3132 unsigned RecNo = MatcherTable[MatcherIndex++];
3133 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3134 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3136 if (!InputChain.getNode())
3137 InputChain = CurDAG->getEntryNode();
3139 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3140 DestPhysReg, RecordedNodes[RecNo].first,
3143 InputGlue = InputChain.getValue(1);
3147 case OPC_EmitNodeXForm: {
3148 unsigned XFormNo = MatcherTable[MatcherIndex++];
3149 unsigned RecNo = MatcherTable[MatcherIndex++];
3150 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3151 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3152 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3157 case OPC_MorphNodeTo: {
3158 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3159 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3160 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3161 // Get the result VT list.
3162 unsigned NumVTs = MatcherTable[MatcherIndex++];
3163 SmallVector<EVT, 4> VTs;
3164 for (unsigned i = 0; i != NumVTs; ++i) {
3165 MVT::SimpleValueType VT =
3166 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3167 if (VT == MVT::iPTR)
3168 VT = TLI->getPointerTy().SimpleTy;
3172 if (EmitNodeInfo & OPFL_Chain)
3173 VTs.push_back(MVT::Other);
3174 if (EmitNodeInfo & OPFL_GlueOutput)
3175 VTs.push_back(MVT::Glue);
3177 // This is hot code, so optimize the two most common cases of 1 and 2
3180 if (VTs.size() == 1)
3181 VTList = CurDAG->getVTList(VTs[0]);
3182 else if (VTs.size() == 2)
3183 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3185 VTList = CurDAG->getVTList(VTs);
3187 // Get the operand list.
3188 unsigned NumOps = MatcherTable[MatcherIndex++];
3189 SmallVector<SDValue, 8> Ops;
3190 for (unsigned i = 0; i != NumOps; ++i) {
3191 unsigned RecNo = MatcherTable[MatcherIndex++];
3193 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3195 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3196 Ops.push_back(RecordedNodes[RecNo].first);
3199 // If there are variadic operands to add, handle them now.
3200 if (EmitNodeInfo & OPFL_VariadicInfo) {
3201 // Determine the start index to copy from.
3202 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3203 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3204 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3205 "Invalid variadic node");
3206 // Copy all of the variadic operands, not including a potential glue
3208 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3210 SDValue V = NodeToMatch->getOperand(i);
3211 if (V.getValueType() == MVT::Glue) break;
3216 // If this has chain/glue inputs, add them.
3217 if (EmitNodeInfo & OPFL_Chain)
3218 Ops.push_back(InputChain);
3219 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3220 Ops.push_back(InputGlue);
3223 SDNode *Res = nullptr;
3224 if (Opcode != OPC_MorphNodeTo) {
3225 // If this is a normal EmitNode command, just create the new node and
3226 // add the results to the RecordedNodes list.
3227 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3230 // Add all the non-glue/non-chain results to the RecordedNodes list.
3231 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3232 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3233 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3237 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3238 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3240 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3241 // We will visit the equivalent node later.
3242 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3246 // If the node had chain/glue results, update our notion of the current
3248 if (EmitNodeInfo & OPFL_GlueOutput) {
3249 InputGlue = SDValue(Res, VTs.size()-1);
3250 if (EmitNodeInfo & OPFL_Chain)
3251 InputChain = SDValue(Res, VTs.size()-2);
3252 } else if (EmitNodeInfo & OPFL_Chain)
3253 InputChain = SDValue(Res, VTs.size()-1);
3255 // If the OPFL_MemRefs glue is set on this node, slap all of the
3256 // accumulated memrefs onto it.
3258 // FIXME: This is vastly incorrect for patterns with multiple outputs
3259 // instructions that access memory and for ComplexPatterns that match
3261 if (EmitNodeInfo & OPFL_MemRefs) {
3262 // Only attach load or store memory operands if the generated
3263 // instruction may load or store.
3264 const MCInstrDesc &MCID = TII->get(TargetOpc);
3265 bool mayLoad = MCID.mayLoad();
3266 bool mayStore = MCID.mayStore();
3268 unsigned NumMemRefs = 0;
3269 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3270 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3271 if ((*I)->isLoad()) {
3274 } else if ((*I)->isStore()) {
3282 MachineSDNode::mmo_iterator MemRefs =
3283 MF->allocateMemRefsArray(NumMemRefs);
3285 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3286 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3287 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3288 if ((*I)->isLoad()) {
3291 } else if ((*I)->isStore()) {
3299 cast<MachineSDNode>(Res)
3300 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3304 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3305 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3307 // If this was a MorphNodeTo then we're completely done!
3308 if (Opcode == OPC_MorphNodeTo) {
3309 // Update chain and glue uses.
3310 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3311 InputGlue, GlueResultNodesMatched, true);
3318 case OPC_MarkGlueResults: {
3319 unsigned NumNodes = MatcherTable[MatcherIndex++];
3321 // Read and remember all the glue-result nodes.
3322 for (unsigned i = 0; i != NumNodes; ++i) {
3323 unsigned RecNo = MatcherTable[MatcherIndex++];
3325 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3327 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3328 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3333 case OPC_CompleteMatch: {
3334 // The match has been completed, and any new nodes (if any) have been
3335 // created. Patch up references to the matched dag to use the newly
3337 unsigned NumResults = MatcherTable[MatcherIndex++];
3339 for (unsigned i = 0; i != NumResults; ++i) {
3340 unsigned ResSlot = MatcherTable[MatcherIndex++];
3342 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3344 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3345 SDValue Res = RecordedNodes[ResSlot].first;
3347 assert(i < NodeToMatch->getNumValues() &&
3348 NodeToMatch->getValueType(i) != MVT::Other &&
3349 NodeToMatch->getValueType(i) != MVT::Glue &&
3350 "Invalid number of results to complete!");
3351 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3352 NodeToMatch->getValueType(i) == MVT::iPTR ||
3353 Res.getValueType() == MVT::iPTR ||
3354 NodeToMatch->getValueType(i).getSizeInBits() ==
3355 Res.getValueType().getSizeInBits()) &&
3356 "invalid replacement");
3357 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3360 // If the root node defines glue, add it to the glue nodes to update list.
3361 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3362 GlueResultNodesMatched.push_back(NodeToMatch);
3364 // Update chain and glue uses.
3365 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3366 InputGlue, GlueResultNodesMatched, false);
3368 assert(NodeToMatch->use_empty() &&
3369 "Didn't replace all uses of the node?");
3371 // FIXME: We just return here, which interacts correctly with SelectRoot
3372 // above. We should fix this to not return an SDNode* anymore.
3377 // If the code reached this point, then the match failed. See if there is
3378 // another child to try in the current 'Scope', otherwise pop it until we
3379 // find a case to check.
3380 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3381 ++NumDAGIselRetries;
3383 if (MatchScopes.empty()) {
3384 CannotYetSelect(NodeToMatch);
3388 // Restore the interpreter state back to the point where the scope was
3390 MatchScope &LastScope = MatchScopes.back();
3391 RecordedNodes.resize(LastScope.NumRecordedNodes);
3393 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3394 N = NodeStack.back();
3396 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3397 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3398 MatcherIndex = LastScope.FailIndex;
3400 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3402 InputChain = LastScope.InputChain;
3403 InputGlue = LastScope.InputGlue;
3404 if (!LastScope.HasChainNodesMatched)
3405 ChainNodesMatched.clear();
3406 if (!LastScope.HasGlueResultNodesMatched)
3407 GlueResultNodesMatched.clear();
3409 // Check to see what the offset is at the new MatcherIndex. If it is zero
3410 // we have reached the end of this scope, otherwise we have another child
3411 // in the current scope to try.
3412 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3413 if (NumToSkip & 128)
3414 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3416 // If we have another child in this scope to match, update FailIndex and
3418 if (NumToSkip != 0) {
3419 LastScope.FailIndex = MatcherIndex+NumToSkip;
3423 // End of this scope, pop it and try the next child in the containing
3425 MatchScopes.pop_back();
3432 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3434 raw_string_ostream Msg(msg);
3435 Msg << "Cannot select: ";
3437 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3438 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3439 N->getOpcode() != ISD::INTRINSIC_VOID) {
3440 N->printrFull(Msg, CurDAG);
3441 Msg << "\nIn function: " << MF->getName();
3443 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3445 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3446 if (iid < Intrinsic::num_intrinsics)
3447 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3448 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3449 Msg << "target intrinsic %" << TII->getName(iid);
3451 Msg << "unknown intrinsic #" << iid;
3453 report_fatal_error(Msg.str());
3456 char SelectionDAGISel::ID = 0;