1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SSARegMap.h"
37 #include "llvm/Target/MRegisterInfo.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetFrameInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
52 ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
55 ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
61 //===---------------------------------------------------------------------===//
63 /// RegisterScheduler class - Track the registration of instruction schedulers.
65 //===---------------------------------------------------------------------===//
66 MachinePassRegistry RegisterScheduler::Registry;
68 //===---------------------------------------------------------------------===//
70 /// ISHeuristic command line option for instruction schedulers.
72 //===---------------------------------------------------------------------===//
74 cl::opt<RegisterScheduler::FunctionPassCtor, false,
75 RegisterPassParser<RegisterScheduler> >
76 ISHeuristic("pre-RA-sched",
77 cl::init(&createDefaultScheduler),
78 cl::desc("Instruction schedulers available (before register allocation):"));
80 static RegisterScheduler
81 defaultListDAGScheduler("default", " Best scheduler for the target",
82 createDefaultScheduler);
85 namespace { struct AsmOperandInfo; }
88 /// RegsForValue - This struct represents the physical registers that a
89 /// particular value is assigned and the type information about the value.
90 /// This is needed because values can be promoted into larger registers and
91 /// expanded into multiple smaller registers than the value.
92 struct VISIBILITY_HIDDEN RegsForValue {
93 /// Regs - This list holds the register (for legal and promoted values)
94 /// or register set (for expanded values) that the value should be assigned
96 std::vector<unsigned> Regs;
98 /// RegVT - The value type of each register.
100 MVT::ValueType RegVT;
102 /// ValueVT - The value type of the LLVM value, which may be promoted from
103 /// RegVT or made from merging the two expanded parts.
104 MVT::ValueType ValueVT;
106 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
108 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
109 : RegVT(regvt), ValueVT(valuevt) {
112 RegsForValue(const std::vector<unsigned> ®s,
113 MVT::ValueType regvt, MVT::ValueType valuevt)
114 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
117 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
118 /// this value and returns the result as a ValueVT value. This uses
119 /// Chain/Flag as the input and updates them for the output Chain/Flag.
120 /// If the Flag pointer is NULL, no flag is used.
121 SDOperand getCopyFromRegs(SelectionDAG &DAG,
122 SDOperand &Chain, SDOperand *Flag) const;
124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
125 /// specified value into the registers specified by this object. This uses
126 /// Chain/Flag as the input and updates them for the output Chain/Flag.
127 /// If the Flag pointer is NULL, no flag is used.
128 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
129 SDOperand &Chain, SDOperand *Flag) const;
131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
132 /// operand list. This adds the code marker and includes the number of
133 /// values added into it.
134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
135 std::vector<SDOperand> &Ops) const;
140 //===--------------------------------------------------------------------===//
141 /// createDefaultScheduler - This creates an instruction scheduler appropriate
143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
145 MachineBasicBlock *BB) {
146 TargetLowering &TLI = IS->getTargetLowering();
148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
149 return createTDListDAGScheduler(IS, DAG, BB);
151 assert(TLI.getSchedulingPreference() ==
152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
153 return createBURRListDAGScheduler(IS, DAG, BB);
158 //===--------------------------------------------------------------------===//
159 /// FunctionLoweringInfo - This contains information that is global to a
160 /// function that is used when lowering a region of the function.
161 class FunctionLoweringInfo {
168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
173 /// ValueMap - Since we emit code for the function a basic block at a time,
174 /// we must remember which virtual registers hold the values for
175 /// cross-basic-block values.
176 DenseMap<const Value*, unsigned> ValueMap;
178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
179 /// the entry block. This allows the allocas to be efficiently referenced
180 /// anywhere in the function.
181 std::map<const AllocaInst*, int> StaticAllocaMap;
184 SmallSet<Instruction*, 8> CatchInfoLost;
185 SmallSet<Instruction*, 8> CatchInfoFound;
188 unsigned MakeReg(MVT::ValueType VT) {
189 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
192 /// isExportedInst - Return true if the specified value is an instruction
193 /// exported from its block.
194 bool isExportedInst(const Value *V) {
195 return ValueMap.count(V);
198 unsigned CreateRegForValue(const Value *V);
200 unsigned InitializeRegForValue(const Value *V) {
201 unsigned &R = ValueMap[V];
202 assert(R == 0 && "Already initialized this value register!");
203 return R = CreateRegForValue(V);
208 /// isSelector - Return true if this instruction is a call to the
209 /// eh.selector intrinsic.
210 static bool isSelector(Instruction *I) {
211 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
212 return II->getIntrinsicID() == Intrinsic::eh_selector;
216 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
217 /// PHI nodes or outside of the basic block that defines it, or used by a
218 /// switch instruction, which may expand to multiple basic blocks.
219 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
220 if (isa<PHINode>(I)) return true;
221 BasicBlock *BB = I->getParent();
222 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
223 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
224 // FIXME: Remove switchinst special case.
225 isa<SwitchInst>(*UI))
230 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
231 /// entry block, return true. This includes arguments used by switches, since
232 /// the switch may expand into multiple basic blocks.
233 static bool isOnlyUsedInEntryBlock(Argument *A) {
234 BasicBlock *Entry = A->getParent()->begin();
235 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
236 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
237 return false; // Use not in entry block.
241 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
242 Function &fn, MachineFunction &mf)
243 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
245 // Create a vreg for each argument register that is not dead and is used
246 // outside of the entry block for the function.
247 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
249 if (!isOnlyUsedInEntryBlock(AI))
250 InitializeRegForValue(AI);
252 // Initialize the mapping of values to registers. This is only set up for
253 // instruction values that are used outside of the block that defines
255 Function::iterator BB = Fn.begin(), EB = Fn.end();
256 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
257 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
258 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
259 const Type *Ty = AI->getAllocatedType();
260 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
262 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
265 TySize *= CUI->getZExtValue(); // Get total allocated size.
266 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
267 StaticAllocaMap[AI] =
268 MF.getFrameInfo()->CreateStackObject(TySize, Align);
271 for (; BB != EB; ++BB)
272 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
273 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
274 if (!isa<AllocaInst>(I) ||
275 !StaticAllocaMap.count(cast<AllocaInst>(I)))
276 InitializeRegForValue(I);
278 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
279 // also creates the initial PHI MachineInstrs, though none of the input
280 // operands are populated.
281 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
282 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
284 MF.getBasicBlockList().push_back(MBB);
286 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
289 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
290 if (PN->use_empty()) continue;
292 MVT::ValueType VT = TLI.getValueType(PN->getType());
293 unsigned NumRegisters = TLI.getNumRegisters(VT);
294 unsigned PHIReg = ValueMap[PN];
295 assert(PHIReg && "PHI node does not have an assigned virtual register!");
296 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
297 for (unsigned i = 0; i != NumRegisters; ++i)
298 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
303 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
304 /// the correctly promoted or expanded types. Assign these registers
305 /// consecutive vreg numbers and return the first assigned number.
306 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
307 MVT::ValueType VT = TLI.getValueType(V->getType());
309 unsigned NumRegisters = TLI.getNumRegisters(VT);
310 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
312 unsigned R = MakeReg(RegisterVT);
313 for (unsigned i = 1; i != NumRegisters; ++i)
319 //===----------------------------------------------------------------------===//
320 /// SelectionDAGLowering - This is the common target-independent lowering
321 /// implementation that is parameterized by a TargetLowering object.
322 /// Also, targets can overload any lowering method.
325 class SelectionDAGLowering {
326 MachineBasicBlock *CurMBB;
328 DenseMap<const Value*, SDOperand> NodeMap;
330 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
331 /// them up and then emit token factor nodes when possible. This allows us to
332 /// get simple disambiguation between loads without worrying about alias
334 std::vector<SDOperand> PendingLoads;
336 /// Case - A struct to record the Value for a switch case, and the
337 /// case's target basic block.
341 MachineBasicBlock* BB;
343 Case() : Low(0), High(0), BB(0) { }
344 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
345 Low(low), High(high), BB(bb) { }
346 uint64_t size() const {
347 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
348 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
349 return (rHigh - rLow + 1ULL);
355 MachineBasicBlock* BB;
358 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
359 Mask(mask), BB(bb), Bits(bits) { }
362 typedef std::vector<Case> CaseVector;
363 typedef std::vector<CaseBits> CaseBitsVector;
364 typedef CaseVector::iterator CaseItr;
365 typedef std::pair<CaseItr, CaseItr> CaseRange;
367 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
368 /// of conditional branches.
370 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
371 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
373 /// CaseBB - The MBB in which to emit the compare and branch
374 MachineBasicBlock *CaseBB;
375 /// LT, GE - If nonzero, we know the current case value must be less-than or
376 /// greater-than-or-equal-to these Constants.
379 /// Range - A pair of iterators representing the range of case values to be
380 /// processed at this point in the binary search tree.
384 typedef std::vector<CaseRec> CaseRecVector;
386 /// The comparison function for sorting the switch case values in the vector.
387 /// WARNING: Case ranges should be disjoint!
389 bool operator () (const Case& C1, const Case& C2) {
390 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
391 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
392 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
393 return CI1->getValue().slt(CI2->getValue());
398 bool operator () (const CaseBits& C1, const CaseBits& C2) {
399 return C1.Bits > C2.Bits;
403 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
406 // TLI - This is information that describes the available target features we
407 // need for lowering. This indicates when operations are unavailable,
408 // implemented with a libcall, etc.
411 const TargetData *TD;
413 /// SwitchCases - Vector of CaseBlock structures used to communicate
414 /// SwitchInst code generation information.
415 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
416 /// JTCases - Vector of JumpTable structures used to communicate
417 /// SwitchInst code generation information.
418 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
419 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
421 /// FuncInfo - Information about the function as a whole.
423 FunctionLoweringInfo &FuncInfo;
425 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
426 FunctionLoweringInfo &funcinfo)
427 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
431 /// getRoot - Return the current virtual root of the Selection DAG.
433 SDOperand getRoot() {
434 if (PendingLoads.empty())
435 return DAG.getRoot();
437 if (PendingLoads.size() == 1) {
438 SDOperand Root = PendingLoads[0];
440 PendingLoads.clear();
444 // Otherwise, we have to make a token factor node.
445 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
446 &PendingLoads[0], PendingLoads.size());
447 PendingLoads.clear();
452 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
454 void visit(Instruction &I) { visit(I.getOpcode(), I); }
456 void visit(unsigned Opcode, User &I) {
457 // Note: this doesn't use InstVisitor, because it has to work with
458 // ConstantExpr's in addition to instructions.
460 default: assert(0 && "Unknown instruction type encountered!");
462 // Build the switch statement using the Instruction.def file.
463 #define HANDLE_INST(NUM, OPCODE, CLASS) \
464 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
465 #include "llvm/Instruction.def"
469 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
471 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
472 const Value *SV, SDOperand Root,
473 bool isVolatile, unsigned Alignment);
475 SDOperand getIntPtrConstant(uint64_t Val) {
476 return DAG.getConstant(Val, TLI.getPointerTy());
479 SDOperand getValue(const Value *V);
481 void setValue(const Value *V, SDOperand NewN) {
482 SDOperand &N = NodeMap[V];
483 assert(N.Val == 0 && "Already set a value for this node!");
487 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
488 std::set<unsigned> &OutputRegs,
489 std::set<unsigned> &InputRegs);
491 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
492 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
494 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
495 void ExportFromCurrentBlock(Value *V);
496 void LowerCallTo(Instruction &I,
497 const Type *CalledValueTy, unsigned CallingConv,
498 bool IsTailCall, SDOperand Callee, unsigned OpIdx,
499 MachineBasicBlock *LandingPad = NULL);
501 // Terminator instructions.
502 void visitRet(ReturnInst &I);
503 void visitBr(BranchInst &I);
504 void visitSwitch(SwitchInst &I);
505 void visitUnreachable(UnreachableInst &I) { /* noop */ }
507 // Helpers for visitSwitch
508 bool handleSmallSwitchRange(CaseRec& CR,
509 CaseRecVector& WorkList,
511 MachineBasicBlock* Default);
512 bool handleJTSwitchCase(CaseRec& CR,
513 CaseRecVector& WorkList,
515 MachineBasicBlock* Default);
516 bool handleBTSplitSwitchCase(CaseRec& CR,
517 CaseRecVector& WorkList,
519 MachineBasicBlock* Default);
520 bool handleBitTestsSwitchCase(CaseRec& CR,
521 CaseRecVector& WorkList,
523 MachineBasicBlock* Default);
524 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
525 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
526 void visitBitTestCase(MachineBasicBlock* NextMBB,
528 SelectionDAGISel::BitTestCase &B);
529 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
530 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
531 SelectionDAGISel::JumpTableHeader &JTH);
533 // These all get lowered before this pass.
534 void visitInvoke(InvokeInst &I);
535 void visitUnwind(UnwindInst &I);
537 void visitBinary(User &I, unsigned OpCode);
538 void visitShift(User &I, unsigned Opcode);
539 void visitAdd(User &I) {
540 if (I.getType()->isFPOrFPVector())
541 visitBinary(I, ISD::FADD);
543 visitBinary(I, ISD::ADD);
545 void visitSub(User &I);
546 void visitMul(User &I) {
547 if (I.getType()->isFPOrFPVector())
548 visitBinary(I, ISD::FMUL);
550 visitBinary(I, ISD::MUL);
552 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
553 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
554 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
555 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
556 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
557 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
558 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
559 void visitOr (User &I) { visitBinary(I, ISD::OR); }
560 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
561 void visitShl (User &I) { visitShift(I, ISD::SHL); }
562 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
563 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
564 void visitICmp(User &I);
565 void visitFCmp(User &I);
566 // Visit the conversion instructions
567 void visitTrunc(User &I);
568 void visitZExt(User &I);
569 void visitSExt(User &I);
570 void visitFPTrunc(User &I);
571 void visitFPExt(User &I);
572 void visitFPToUI(User &I);
573 void visitFPToSI(User &I);
574 void visitUIToFP(User &I);
575 void visitSIToFP(User &I);
576 void visitPtrToInt(User &I);
577 void visitIntToPtr(User &I);
578 void visitBitCast(User &I);
580 void visitExtractElement(User &I);
581 void visitInsertElement(User &I);
582 void visitShuffleVector(User &I);
584 void visitGetElementPtr(User &I);
585 void visitSelect(User &I);
587 void visitMalloc(MallocInst &I);
588 void visitFree(FreeInst &I);
589 void visitAlloca(AllocaInst &I);
590 void visitLoad(LoadInst &I);
591 void visitStore(StoreInst &I);
592 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
593 void visitCall(CallInst &I);
594 void visitInlineAsm(CallInst &I);
595 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
596 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
598 void visitVAStart(CallInst &I);
599 void visitVAArg(VAArgInst &I);
600 void visitVAEnd(CallInst &I);
601 void visitVACopy(CallInst &I);
603 void visitMemIntrinsic(CallInst &I, unsigned Op);
605 void visitUserOp1(Instruction &I) {
606 assert(0 && "UserOp1 should not exist at instruction selection time!");
609 void visitUserOp2(Instruction &I) {
610 assert(0 && "UserOp2 should not exist at instruction selection time!");
614 } // end namespace llvm
617 /// getCopyFromParts - Create a value that contains the
618 /// specified legal parts combined into the value they represent.
619 static SDOperand getCopyFromParts(SelectionDAG &DAG,
620 const SDOperand *Parts,
622 MVT::ValueType PartVT,
623 MVT::ValueType ValueVT,
624 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
625 if (!MVT::isVector(ValueVT) || NumParts == 1) {
626 SDOperand Val = Parts[0];
628 // If the value was expanded, copy from the top part.
630 assert(NumParts == 2 &&
631 "Cannot expand to more than 2 elts yet!");
632 SDOperand Hi = Parts[1];
633 if (!DAG.getTargetLoweringInfo().isLittleEndian())
635 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
638 // Otherwise, if the value was promoted or extended, truncate it to the
640 if (PartVT == ValueVT)
643 if (MVT::isVector(PartVT)) {
644 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
645 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
648 if (MVT::isInteger(PartVT) &&
649 MVT::isInteger(ValueVT)) {
650 if (ValueVT < PartVT) {
651 // For a truncate, see if we have any information to
652 // indicate whether the truncated bits will always be
653 // zero or sign-extension.
654 if (AssertOp != ISD::DELETED_NODE)
655 Val = DAG.getNode(AssertOp, PartVT, Val,
656 DAG.getValueType(ValueVT));
657 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
659 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
663 if (MVT::isFloatingPoint(PartVT) &&
664 MVT::isFloatingPoint(ValueVT))
665 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
667 if (MVT::getSizeInBits(PartVT) ==
668 MVT::getSizeInBits(ValueVT))
669 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
671 assert(0 && "Unknown mismatch!");
674 // Handle a multi-element vector.
675 MVT::ValueType IntermediateVT, RegisterVT;
676 unsigned NumIntermediates;
678 DAG.getTargetLoweringInfo()
679 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
682 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
683 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
684 assert(RegisterVT == Parts[0].getValueType() &&
685 "Part type doesn't match part!");
687 // Assemble the parts into intermediate operands.
688 SmallVector<SDOperand, 8> Ops(NumIntermediates);
689 if (NumIntermediates == NumParts) {
690 // If the register was not expanded, truncate or copy the value,
692 for (unsigned i = 0; i != NumParts; ++i)
693 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
694 PartVT, IntermediateVT);
695 } else if (NumParts > 0) {
696 // If the intermediate type was expanded, build the intermediate operands
698 assert(NumParts % NumIntermediates == 0 &&
699 "Must expand into a divisible number of parts!");
700 unsigned Factor = NumParts / NumIntermediates;
701 for (unsigned i = 0; i != NumIntermediates; ++i)
702 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
703 PartVT, IntermediateVT);
706 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
708 return DAG.getNode(MVT::isVector(IntermediateVT) ?
709 ISD::CONCAT_VECTORS :
711 ValueVT, &Ops[0], NumIntermediates);
714 /// getCopyToParts - Create a series of nodes that contain the
715 /// specified value split into legal parts.
716 static void getCopyToParts(SelectionDAG &DAG,
720 MVT::ValueType PartVT) {
721 TargetLowering &TLI = DAG.getTargetLoweringInfo();
722 MVT::ValueType PtrVT = TLI.getPointerTy();
723 MVT::ValueType ValueVT = Val.getValueType();
725 if (!MVT::isVector(ValueVT) || NumParts == 1) {
726 // If the value was expanded, copy from the parts.
728 for (unsigned i = 0; i != NumParts; ++i)
729 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
730 DAG.getConstant(i, PtrVT));
731 if (!DAG.getTargetLoweringInfo().isLittleEndian())
732 std::reverse(Parts, Parts + NumParts);
736 // If there is a single part and the types differ, this must be
738 if (PartVT != ValueVT) {
739 if (MVT::isVector(PartVT)) {
740 assert(MVT::isVector(ValueVT) &&
741 "Not a vector-vector cast?");
742 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
743 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
744 if (PartVT < ValueVT)
745 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
747 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
748 } else if (MVT::isFloatingPoint(PartVT) &&
749 MVT::isFloatingPoint(ValueVT)) {
750 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
751 } else if (MVT::getSizeInBits(PartVT) ==
752 MVT::getSizeInBits(ValueVT)) {
753 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
755 assert(0 && "Unknown mismatch!");
762 // Handle a multi-element vector.
763 MVT::ValueType IntermediateVT, RegisterVT;
764 unsigned NumIntermediates;
766 DAG.getTargetLoweringInfo()
767 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
769 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
771 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
772 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
774 // Split the vector into intermediate operands.
775 SmallVector<SDOperand, 8> Ops(NumIntermediates);
776 for (unsigned i = 0; i != NumIntermediates; ++i)
777 if (MVT::isVector(IntermediateVT))
778 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
780 DAG.getConstant(i * (NumElements / NumIntermediates),
783 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
785 DAG.getConstant(i, PtrVT));
787 // Split the intermediate operands into legal parts.
788 if (NumParts == NumIntermediates) {
789 // If the register was not expanded, promote or copy the value,
791 for (unsigned i = 0; i != NumParts; ++i)
792 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
793 } else if (NumParts > 0) {
794 // If the intermediate type was expanded, split each the value into
796 assert(NumParts % NumIntermediates == 0 &&
797 "Must expand into a divisible number of parts!");
798 unsigned Factor = NumParts / NumIntermediates;
799 for (unsigned i = 0; i != NumIntermediates; ++i)
800 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
805 SDOperand SelectionDAGLowering::getValue(const Value *V) {
806 SDOperand &N = NodeMap[V];
809 const Type *VTy = V->getType();
810 MVT::ValueType VT = TLI.getValueType(VTy);
811 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
812 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
813 visit(CE->getOpcode(), *CE);
814 SDOperand N1 = NodeMap[V];
815 assert(N1.Val && "visit didn't populate the ValueMap!");
817 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
818 return N = DAG.getGlobalAddress(GV, VT);
819 } else if (isa<ConstantPointerNull>(C)) {
820 return N = DAG.getConstant(0, TLI.getPointerTy());
821 } else if (isa<UndefValue>(C)) {
822 if (!isa<VectorType>(VTy))
823 return N = DAG.getNode(ISD::UNDEF, VT);
825 // Create a BUILD_VECTOR of undef nodes.
826 const VectorType *PTy = cast<VectorType>(VTy);
827 unsigned NumElements = PTy->getNumElements();
828 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
830 SmallVector<SDOperand, 8> Ops;
831 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
833 // Create a VConstant node with generic Vector type.
834 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
835 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
836 &Ops[0], Ops.size());
837 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
838 return N = DAG.getConstantFP(CFP->getValue(), VT);
839 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
840 unsigned NumElements = PTy->getNumElements();
841 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
843 // Now that we know the number and type of the elements, push a
844 // Constant or ConstantFP node onto the ops list for each element of
845 // the vector constant.
846 SmallVector<SDOperand, 8> Ops;
847 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
848 for (unsigned i = 0; i != NumElements; ++i)
849 Ops.push_back(getValue(CP->getOperand(i)));
851 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
853 if (MVT::isFloatingPoint(PVT))
854 Op = DAG.getConstantFP(0, PVT);
856 Op = DAG.getConstant(0, PVT);
857 Ops.assign(NumElements, Op);
860 // Create a BUILD_VECTOR node.
861 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
862 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
865 // Canonicalize all constant ints to be unsigned.
866 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
870 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
871 std::map<const AllocaInst*, int>::iterator SI =
872 FuncInfo.StaticAllocaMap.find(AI);
873 if (SI != FuncInfo.StaticAllocaMap.end())
874 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
877 unsigned InReg = FuncInfo.ValueMap[V];
878 assert(InReg && "Value not in map!");
880 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
881 unsigned NumRegs = TLI.getNumRegisters(VT);
883 std::vector<unsigned> Regs(NumRegs);
884 for (unsigned i = 0; i != NumRegs; ++i)
887 RegsForValue RFV(Regs, RegisterVT, VT);
888 SDOperand Chain = DAG.getEntryNode();
890 return RFV.getCopyFromRegs(DAG, Chain, NULL);
894 void SelectionDAGLowering::visitRet(ReturnInst &I) {
895 if (I.getNumOperands() == 0) {
896 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
899 SmallVector<SDOperand, 8> NewValues;
900 NewValues.push_back(getRoot());
901 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
902 SDOperand RetOp = getValue(I.getOperand(i));
904 // If this is an integer return value, we need to promote it ourselves to
905 // the full width of a register, since getCopyToParts and Legalize will use
906 // ANY_EXTEND rather than sign/zero.
907 // FIXME: C calling convention requires the return type to be promoted to
908 // at least 32-bit. But this is not necessary for non-C calling conventions.
909 if (MVT::isInteger(RetOp.getValueType()) &&
910 RetOp.getValueType() < MVT::i64) {
911 MVT::ValueType TmpVT;
912 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
913 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
916 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType();
917 const ParamAttrsList *Attrs = FTy->getParamAttrs();
918 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
919 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt))
920 ExtendKind = ISD::SIGN_EXTEND;
921 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt))
922 ExtendKind = ISD::ZERO_EXTEND;
923 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
924 NewValues.push_back(RetOp);
925 NewValues.push_back(DAG.getConstant(false, MVT::i32));
927 MVT::ValueType VT = RetOp.getValueType();
928 unsigned NumParts = TLI.getNumRegisters(VT);
929 MVT::ValueType PartVT = TLI.getRegisterType(VT);
930 SmallVector<SDOperand, 4> Parts(NumParts);
931 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
932 for (unsigned i = 0; i < NumParts; ++i) {
933 NewValues.push_back(Parts[i]);
934 NewValues.push_back(DAG.getConstant(false, MVT::i32));
938 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
939 &NewValues[0], NewValues.size()));
942 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
943 /// the current basic block, add it to ValueMap now so that we'll get a
945 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
946 // No need to export constants.
947 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
950 if (FuncInfo.isExportedInst(V)) return;
952 unsigned Reg = FuncInfo.InitializeRegForValue(V);
953 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
956 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
957 const BasicBlock *FromBB) {
958 // The operands of the setcc have to be in this block. We don't know
959 // how to export them from some other block.
960 if (Instruction *VI = dyn_cast<Instruction>(V)) {
961 // Can export from current BB.
962 if (VI->getParent() == FromBB)
965 // Is already exported, noop.
966 return FuncInfo.isExportedInst(V);
969 // If this is an argument, we can export it if the BB is the entry block or
970 // if it is already exported.
971 if (isa<Argument>(V)) {
972 if (FromBB == &FromBB->getParent()->getEntryBlock())
975 // Otherwise, can only export this if it is already exported.
976 return FuncInfo.isExportedInst(V);
979 // Otherwise, constants can always be exported.
983 static bool InBlock(const Value *V, const BasicBlock *BB) {
984 if (const Instruction *I = dyn_cast<Instruction>(V))
985 return I->getParent() == BB;
989 /// FindMergedConditions - If Cond is an expression like
990 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
991 MachineBasicBlock *TBB,
992 MachineBasicBlock *FBB,
993 MachineBasicBlock *CurBB,
995 // If this node is not part of the or/and tree, emit it as a branch.
996 Instruction *BOp = dyn_cast<Instruction>(Cond);
998 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
999 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1000 BOp->getParent() != CurBB->getBasicBlock() ||
1001 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1002 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1003 const BasicBlock *BB = CurBB->getBasicBlock();
1005 // If the leaf of the tree is a comparison, merge the condition into
1007 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1008 // The operands of the cmp have to be in this block. We don't know
1009 // how to export them from some other block. If this is the first block
1010 // of the sequence, no exporting is needed.
1012 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1013 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1014 BOp = cast<Instruction>(Cond);
1015 ISD::CondCode Condition;
1016 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1017 switch (IC->getPredicate()) {
1018 default: assert(0 && "Unknown icmp predicate opcode!");
1019 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1020 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1021 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1022 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1023 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1024 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1025 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1026 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1027 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1028 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1030 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1031 ISD::CondCode FPC, FOC;
1032 switch (FC->getPredicate()) {
1033 default: assert(0 && "Unknown fcmp predicate opcode!");
1034 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1035 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1036 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1037 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1038 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1039 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1040 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1041 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1042 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1043 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1044 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1045 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1046 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1047 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1048 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1049 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1051 if (FiniteOnlyFPMath())
1056 Condition = ISD::SETEQ; // silence warning.
1057 assert(0 && "Unknown compare instruction");
1060 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1061 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1062 SwitchCases.push_back(CB);
1066 // Create a CaseBlock record representing this branch.
1067 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1068 NULL, TBB, FBB, CurBB);
1069 SwitchCases.push_back(CB);
1074 // Create TmpBB after CurBB.
1075 MachineFunction::iterator BBI = CurBB;
1076 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1077 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1079 if (Opc == Instruction::Or) {
1080 // Codegen X | Y as:
1088 // Emit the LHS condition.
1089 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1091 // Emit the RHS condition into TmpBB.
1092 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1094 assert(Opc == Instruction::And && "Unknown merge op!");
1095 // Codegen X & Y as:
1102 // This requires creation of TmpBB after CurBB.
1104 // Emit the LHS condition.
1105 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1107 // Emit the RHS condition into TmpBB.
1108 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1112 /// If the set of cases should be emitted as a series of branches, return true.
1113 /// If we should emit this as a bunch of and/or'd together conditions, return
1116 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1117 if (Cases.size() != 2) return true;
1119 // If this is two comparisons of the same values or'd or and'd together, they
1120 // will get folded into a single comparison, so don't emit two blocks.
1121 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1122 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1123 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1124 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1131 void SelectionDAGLowering::visitBr(BranchInst &I) {
1132 // Update machine-CFG edges.
1133 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1135 // Figure out which block is immediately after the current one.
1136 MachineBasicBlock *NextBlock = 0;
1137 MachineFunction::iterator BBI = CurMBB;
1138 if (++BBI != CurMBB->getParent()->end())
1141 if (I.isUnconditional()) {
1142 // If this is not a fall-through branch, emit the branch.
1143 if (Succ0MBB != NextBlock)
1144 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1145 DAG.getBasicBlock(Succ0MBB)));
1147 // Update machine-CFG edges.
1148 CurMBB->addSuccessor(Succ0MBB);
1153 // If this condition is one of the special cases we handle, do special stuff
1155 Value *CondVal = I.getCondition();
1156 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1158 // If this is a series of conditions that are or'd or and'd together, emit
1159 // this as a sequence of branches instead of setcc's with and/or operations.
1160 // For example, instead of something like:
1173 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1174 if (BOp->hasOneUse() &&
1175 (BOp->getOpcode() == Instruction::And ||
1176 BOp->getOpcode() == Instruction::Or)) {
1177 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1178 // If the compares in later blocks need to use values not currently
1179 // exported from this block, export them now. This block should always
1180 // be the first entry.
1181 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1183 // Allow some cases to be rejected.
1184 if (ShouldEmitAsBranches(SwitchCases)) {
1185 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1186 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1187 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1190 // Emit the branch for this block.
1191 visitSwitchCase(SwitchCases[0]);
1192 SwitchCases.erase(SwitchCases.begin());
1196 // Okay, we decided not to do this, remove any inserted MBB's and clear
1198 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1199 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1201 SwitchCases.clear();
1205 // Create a CaseBlock record representing this branch.
1206 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1207 NULL, Succ0MBB, Succ1MBB, CurMBB);
1208 // Use visitSwitchCase to actually insert the fast branch sequence for this
1210 visitSwitchCase(CB);
1213 /// visitSwitchCase - Emits the necessary code to represent a single node in
1214 /// the binary search tree resulting from lowering a switch instruction.
1215 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1217 SDOperand CondLHS = getValue(CB.CmpLHS);
1219 // Build the setcc now.
1220 if (CB.CmpMHS == NULL) {
1221 // Fold "(X == true)" to X and "(X == false)" to !X to
1222 // handle common cases produced by branch lowering.
1223 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1225 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1226 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1227 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1229 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1231 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1233 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1234 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1236 SDOperand CmpOp = getValue(CB.CmpMHS);
1237 MVT::ValueType VT = CmpOp.getValueType();
1239 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1240 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1242 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1243 Cond = DAG.getSetCC(MVT::i1, SUB,
1244 DAG.getConstant(High-Low, VT), ISD::SETULE);
1249 // Set NextBlock to be the MBB immediately after the current one, if any.
1250 // This is used to avoid emitting unnecessary branches to the next block.
1251 MachineBasicBlock *NextBlock = 0;
1252 MachineFunction::iterator BBI = CurMBB;
1253 if (++BBI != CurMBB->getParent()->end())
1256 // If the lhs block is the next block, invert the condition so that we can
1257 // fall through to the lhs instead of the rhs block.
1258 if (CB.TrueBB == NextBlock) {
1259 std::swap(CB.TrueBB, CB.FalseBB);
1260 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1261 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1263 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1264 DAG.getBasicBlock(CB.TrueBB));
1265 if (CB.FalseBB == NextBlock)
1266 DAG.setRoot(BrCond);
1268 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1269 DAG.getBasicBlock(CB.FalseBB)));
1270 // Update successor info
1271 CurMBB->addSuccessor(CB.TrueBB);
1272 CurMBB->addSuccessor(CB.FalseBB);
1275 /// visitJumpTable - Emit JumpTable node in the current MBB
1276 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1277 // Emit the code for the jump table
1278 assert(JT.Reg != -1U && "Should lower JT Header first!");
1279 MVT::ValueType PTy = TLI.getPointerTy();
1280 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1281 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1282 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1287 /// visitJumpTableHeader - This function emits necessary code to produce index
1288 /// in the JumpTable from switch case.
1289 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1290 SelectionDAGISel::JumpTableHeader &JTH) {
1291 // Subtract the lowest switch case value from the value being switched on
1292 // and conditional branch to default mbb if the result is greater than the
1293 // difference between smallest and largest cases.
1294 SDOperand SwitchOp = getValue(JTH.SValue);
1295 MVT::ValueType VT = SwitchOp.getValueType();
1296 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1297 DAG.getConstant(JTH.First, VT));
1299 // The SDNode we just created, which holds the value being switched on
1300 // minus the the smallest case value, needs to be copied to a virtual
1301 // register so it can be used as an index into the jump table in a
1302 // subsequent basic block. This value may be smaller or larger than the
1303 // target's pointer type, and therefore require extension or truncating.
1304 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1305 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1307 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1309 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1310 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1311 JT.Reg = JumpTableReg;
1313 // Emit the range check for the jump table, and branch to the default
1314 // block for the switch statement if the value being switched on exceeds
1315 // the largest case in the switch.
1316 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1317 DAG.getConstant(JTH.Last-JTH.First,VT),
1320 // Set NextBlock to be the MBB immediately after the current one, if any.
1321 // This is used to avoid emitting unnecessary branches to the next block.
1322 MachineBasicBlock *NextBlock = 0;
1323 MachineFunction::iterator BBI = CurMBB;
1324 if (++BBI != CurMBB->getParent()->end())
1327 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1328 DAG.getBasicBlock(JT.Default));
1330 if (JT.MBB == NextBlock)
1331 DAG.setRoot(BrCond);
1333 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1334 DAG.getBasicBlock(JT.MBB)));
1339 /// visitBitTestHeader - This function emits necessary code to produce value
1340 /// suitable for "bit tests"
1341 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1342 // Subtract the minimum value
1343 SDOperand SwitchOp = getValue(B.SValue);
1344 MVT::ValueType VT = SwitchOp.getValueType();
1345 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1346 DAG.getConstant(B.First, VT));
1349 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1350 DAG.getConstant(B.Range, VT),
1354 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1355 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1357 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1359 // Make desired shift
1360 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1361 DAG.getConstant(1, TLI.getPointerTy()),
1364 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1365 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1368 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1369 DAG.getBasicBlock(B.Default));
1371 // Set NextBlock to be the MBB immediately after the current one, if any.
1372 // This is used to avoid emitting unnecessary branches to the next block.
1373 MachineBasicBlock *NextBlock = 0;
1374 MachineFunction::iterator BBI = CurMBB;
1375 if (++BBI != CurMBB->getParent()->end())
1378 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1379 if (MBB == NextBlock)
1380 DAG.setRoot(BrRange);
1382 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1383 DAG.getBasicBlock(MBB)));
1385 CurMBB->addSuccessor(B.Default);
1386 CurMBB->addSuccessor(MBB);
1391 /// visitBitTestCase - this function produces one "bit test"
1392 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1394 SelectionDAGISel::BitTestCase &B) {
1395 // Emit bit tests and jumps
1396 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1398 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1400 DAG.getConstant(B.Mask,
1401 TLI.getPointerTy()));
1402 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1403 DAG.getConstant(0, TLI.getPointerTy()),
1405 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1406 AndCmp, DAG.getBasicBlock(B.TargetBB));
1408 // Set NextBlock to be the MBB immediately after the current one, if any.
1409 // This is used to avoid emitting unnecessary branches to the next block.
1410 MachineBasicBlock *NextBlock = 0;
1411 MachineFunction::iterator BBI = CurMBB;
1412 if (++BBI != CurMBB->getParent()->end())
1415 if (NextMBB == NextBlock)
1418 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1419 DAG.getBasicBlock(NextMBB)));
1421 CurMBB->addSuccessor(B.TargetBB);
1422 CurMBB->addSuccessor(NextMBB);
1427 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1428 // Retrieve successors.
1429 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1430 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1432 LowerCallTo(I, I.getCalledValue()->getType(),
1435 getValue(I.getOperand(0)),
1438 // If the value of the invoke is used outside of its defining block, make it
1439 // available as a virtual register.
1440 if (!I.use_empty()) {
1441 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1442 if (VMI != FuncInfo.ValueMap.end())
1443 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1446 // Drop into normal successor.
1447 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1448 DAG.getBasicBlock(Return)));
1450 // Update successor info
1451 CurMBB->addSuccessor(Return);
1452 CurMBB->addSuccessor(LandingPad);
1455 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1458 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1459 /// small case ranges).
1460 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1461 CaseRecVector& WorkList,
1463 MachineBasicBlock* Default) {
1464 Case& BackCase = *(CR.Range.second-1);
1466 // Size is the number of Cases represented by this range.
1467 unsigned Size = CR.Range.second - CR.Range.first;
1471 // Get the MachineFunction which holds the current MBB. This is used when
1472 // inserting any additional MBBs necessary to represent the switch.
1473 MachineFunction *CurMF = CurMBB->getParent();
1475 // Figure out which block is immediately after the current one.
1476 MachineBasicBlock *NextBlock = 0;
1477 MachineFunction::iterator BBI = CR.CaseBB;
1479 if (++BBI != CurMBB->getParent()->end())
1482 // TODO: If any two of the cases has the same destination, and if one value
1483 // is the same as the other, but has one bit unset that the other has set,
1484 // use bit manipulation to do two compares at once. For example:
1485 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1487 // Rearrange the case blocks so that the last one falls through if possible.
1488 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1489 // The last case block won't fall through into 'NextBlock' if we emit the
1490 // branches in this order. See if rearranging a case value would help.
1491 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1492 if (I->BB == NextBlock) {
1493 std::swap(*I, BackCase);
1499 // Create a CaseBlock record representing a conditional branch to
1500 // the Case's target mbb if the value being switched on SV is equal
1502 MachineBasicBlock *CurBlock = CR.CaseBB;
1503 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1504 MachineBasicBlock *FallThrough;
1506 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1507 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1509 // If the last case doesn't match, go to the default block.
1510 FallThrough = Default;
1513 Value *RHS, *LHS, *MHS;
1515 if (I->High == I->Low) {
1516 // This is just small small case range :) containing exactly 1 case
1518 LHS = SV; RHS = I->High; MHS = NULL;
1521 LHS = I->Low; MHS = SV; RHS = I->High;
1523 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1524 I->BB, FallThrough, CurBlock);
1526 // If emitting the first comparison, just call visitSwitchCase to emit the
1527 // code into the current block. Otherwise, push the CaseBlock onto the
1528 // vector to be later processed by SDISel, and insert the node's MBB
1529 // before the next MBB.
1530 if (CurBlock == CurMBB)
1531 visitSwitchCase(CB);
1533 SwitchCases.push_back(CB);
1535 CurBlock = FallThrough;
1541 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1542 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1543 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1546 /// handleJTSwitchCase - Emit jumptable for current switch case range
1547 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1548 CaseRecVector& WorkList,
1550 MachineBasicBlock* Default) {
1551 Case& FrontCase = *CR.Range.first;
1552 Case& BackCase = *(CR.Range.second-1);
1554 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1555 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1558 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1562 if (!areJTsAllowed(TLI) || TSize <= 3)
1565 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1569 DOUT << "Lowering jump table\n"
1570 << "First entry: " << First << ". Last entry: " << Last << "\n"
1571 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1573 // Get the MachineFunction which holds the current MBB. This is used when
1574 // inserting any additional MBBs necessary to represent the switch.
1575 MachineFunction *CurMF = CurMBB->getParent();
1577 // Figure out which block is immediately after the current one.
1578 MachineBasicBlock *NextBlock = 0;
1579 MachineFunction::iterator BBI = CR.CaseBB;
1581 if (++BBI != CurMBB->getParent()->end())
1584 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1586 // Create a new basic block to hold the code for loading the address
1587 // of the jump table, and jumping to it. Update successor information;
1588 // we will either branch to the default case for the switch, or the jump
1590 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1591 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1592 CR.CaseBB->addSuccessor(Default);
1593 CR.CaseBB->addSuccessor(JumpTableBB);
1595 // Build a vector of destination BBs, corresponding to each target
1596 // of the jump table. If the value of the jump table slot corresponds to
1597 // a case statement, push the case's BB onto the vector, otherwise, push
1599 std::vector<MachineBasicBlock*> DestBBs;
1600 int64_t TEI = First;
1601 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1602 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1603 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1605 if ((Low <= TEI) && (TEI <= High)) {
1606 DestBBs.push_back(I->BB);
1610 DestBBs.push_back(Default);
1614 // Update successor info. Add one edge to each unique successor.
1615 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1616 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1617 E = DestBBs.end(); I != E; ++I) {
1618 if (!SuccsHandled[(*I)->getNumber()]) {
1619 SuccsHandled[(*I)->getNumber()] = true;
1620 JumpTableBB->addSuccessor(*I);
1624 // Create a jump table index for this jump table, or return an existing
1626 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1628 // Set the jump table information so that we can codegen it as a second
1629 // MachineBasicBlock
1630 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1631 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1632 (CR.CaseBB == CurMBB));
1633 if (CR.CaseBB == CurMBB)
1634 visitJumpTableHeader(JT, JTH);
1636 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1641 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1643 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1644 CaseRecVector& WorkList,
1646 MachineBasicBlock* Default) {
1647 // Get the MachineFunction which holds the current MBB. This is used when
1648 // inserting any additional MBBs necessary to represent the switch.
1649 MachineFunction *CurMF = CurMBB->getParent();
1651 // Figure out which block is immediately after the current one.
1652 MachineBasicBlock *NextBlock = 0;
1653 MachineFunction::iterator BBI = CR.CaseBB;
1655 if (++BBI != CurMBB->getParent()->end())
1658 Case& FrontCase = *CR.Range.first;
1659 Case& BackCase = *(CR.Range.second-1);
1660 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1662 // Size is the number of Cases represented by this range.
1663 unsigned Size = CR.Range.second - CR.Range.first;
1665 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1666 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1668 CaseItr Pivot = CR.Range.first + Size/2;
1670 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1671 // (heuristically) allow us to emit JumpTable's later.
1673 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1677 uint64_t LSize = FrontCase.size();
1678 uint64_t RSize = TSize-LSize;
1679 DOUT << "Selecting best pivot: \n"
1680 << "First: " << First << ", Last: " << Last <<"\n"
1681 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1682 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1684 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1685 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1686 assert((RBegin-LEnd>=1) && "Invalid case distance");
1687 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1688 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1689 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1690 // Should always split in some non-trivial place
1692 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1693 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1694 << "Metric: " << Metric << "\n";
1695 if (FMetric < Metric) {
1698 DOUT << "Current metric set to: " << FMetric << "\n";
1704 if (areJTsAllowed(TLI)) {
1705 // If our case is dense we *really* should handle it earlier!
1706 assert((FMetric > 0) && "Should handle dense range earlier!");
1708 Pivot = CR.Range.first + Size/2;
1711 CaseRange LHSR(CR.Range.first, Pivot);
1712 CaseRange RHSR(Pivot, CR.Range.second);
1713 Constant *C = Pivot->Low;
1714 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1716 // We know that we branch to the LHS if the Value being switched on is
1717 // less than the Pivot value, C. We use this to optimize our binary
1718 // tree a bit, by recognizing that if SV is greater than or equal to the
1719 // LHS's Case Value, and that Case Value is exactly one less than the
1720 // Pivot's Value, then we can branch directly to the LHS's Target,
1721 // rather than creating a leaf node for it.
1722 if ((LHSR.second - LHSR.first) == 1 &&
1723 LHSR.first->High == CR.GE &&
1724 cast<ConstantInt>(C)->getSExtValue() ==
1725 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1726 TrueBB = LHSR.first->BB;
1728 TrueBB = new MachineBasicBlock(LLVMBB);
1729 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1730 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1733 // Similar to the optimization above, if the Value being switched on is
1734 // known to be less than the Constant CR.LT, and the current Case Value
1735 // is CR.LT - 1, then we can branch directly to the target block for
1736 // the current Case Value, rather than emitting a RHS leaf node for it.
1737 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1738 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1739 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1740 FalseBB = RHSR.first->BB;
1742 FalseBB = new MachineBasicBlock(LLVMBB);
1743 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1744 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1747 // Create a CaseBlock record representing a conditional branch to
1748 // the LHS node if the value being switched on SV is less than C.
1749 // Otherwise, branch to LHS.
1750 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1751 TrueBB, FalseBB, CR.CaseBB);
1753 if (CR.CaseBB == CurMBB)
1754 visitSwitchCase(CB);
1756 SwitchCases.push_back(CB);
1761 /// handleBitTestsSwitchCase - if current case range has few destination and
1762 /// range span less, than machine word bitwidth, encode case range into series
1763 /// of masks and emit bit tests with these masks.
1764 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1765 CaseRecVector& WorkList,
1767 MachineBasicBlock* Default){
1768 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1770 Case& FrontCase = *CR.Range.first;
1771 Case& BackCase = *(CR.Range.second-1);
1773 // Get the MachineFunction which holds the current MBB. This is used when
1774 // inserting any additional MBBs necessary to represent the switch.
1775 MachineFunction *CurMF = CurMBB->getParent();
1777 unsigned numCmps = 0;
1778 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1780 // Single case counts one, case range - two.
1781 if (I->Low == I->High)
1787 // Count unique destinations
1788 SmallSet<MachineBasicBlock*, 4> Dests;
1789 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1790 Dests.insert(I->BB);
1791 if (Dests.size() > 3)
1792 // Don't bother the code below, if there are too much unique destinations
1795 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1796 << "Total number of comparisons: " << numCmps << "\n";
1798 // Compute span of values.
1799 Constant* minValue = FrontCase.Low;
1800 Constant* maxValue = BackCase.High;
1801 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1802 cast<ConstantInt>(minValue)->getSExtValue();
1803 DOUT << "Compare range: " << range << "\n"
1804 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1805 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1807 if (range>=IntPtrBits ||
1808 (!(Dests.size() == 1 && numCmps >= 3) &&
1809 !(Dests.size() == 2 && numCmps >= 5) &&
1810 !(Dests.size() >= 3 && numCmps >= 6)))
1813 DOUT << "Emitting bit tests\n";
1814 int64_t lowBound = 0;
1816 // Optimize the case where all the case values fit in a
1817 // word without having to subtract minValue. In this case,
1818 // we can optimize away the subtraction.
1819 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1820 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1821 range = cast<ConstantInt>(maxValue)->getSExtValue();
1823 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1826 CaseBitsVector CasesBits;
1827 unsigned i, count = 0;
1829 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1830 MachineBasicBlock* Dest = I->BB;
1831 for (i = 0; i < count; ++i)
1832 if (Dest == CasesBits[i].BB)
1836 assert((count < 3) && "Too much destinations to test!");
1837 CasesBits.push_back(CaseBits(0, Dest, 0));
1841 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1842 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1844 for (uint64_t j = lo; j <= hi; j++) {
1845 CasesBits[i].Mask |= 1ULL << j;
1846 CasesBits[i].Bits++;
1850 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1852 SelectionDAGISel::BitTestInfo BTC;
1854 // Figure out which block is immediately after the current one.
1855 MachineFunction::iterator BBI = CR.CaseBB;
1858 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1861 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1862 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1863 << ", BB: " << CasesBits[i].BB << "\n";
1865 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1866 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1867 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1872 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1873 -1U, (CR.CaseBB == CurMBB),
1874 CR.CaseBB, Default, BTC);
1876 if (CR.CaseBB == CurMBB)
1877 visitBitTestHeader(BTB);
1879 BitTestCases.push_back(BTB);
1885 // Clusterify - Transform simple list of Cases into list of CaseRange's
1886 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1887 const SwitchInst& SI) {
1888 unsigned numCmps = 0;
1890 // Start with "simple" cases
1891 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1892 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1893 Cases.push_back(Case(SI.getSuccessorValue(i),
1894 SI.getSuccessorValue(i),
1897 sort(Cases.begin(), Cases.end(), CaseCmp());
1899 // Merge case into clusters
1900 if (Cases.size()>=2)
1901 // Must recompute end() each iteration because it may be
1902 // invalidated by erase if we hold on to it
1903 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1904 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1905 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1906 MachineBasicBlock* nextBB = J->BB;
1907 MachineBasicBlock* currentBB = I->BB;
1909 // If the two neighboring cases go to the same destination, merge them
1910 // into a single case.
1911 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1919 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1920 if (I->Low != I->High)
1921 // A range counts double, since it requires two compares.
1928 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1929 // Figure out which block is immediately after the current one.
1930 MachineBasicBlock *NextBlock = 0;
1931 MachineFunction::iterator BBI = CurMBB;
1933 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1935 // If there is only the default destination, branch to it if it is not the
1936 // next basic block. Otherwise, just fall through.
1937 if (SI.getNumOperands() == 2) {
1938 // Update machine-CFG edges.
1940 // If this is not a fall-through branch, emit the branch.
1941 if (Default != NextBlock)
1942 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1943 DAG.getBasicBlock(Default)));
1945 CurMBB->addSuccessor(Default);
1949 // If there are any non-default case statements, create a vector of Cases
1950 // representing each one, and sort the vector so that we can efficiently
1951 // create a binary search tree from them.
1953 unsigned numCmps = Clusterify(Cases, SI);
1954 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1955 << ". Total compares: " << numCmps << "\n";
1957 // Get the Value to be switched on and default basic blocks, which will be
1958 // inserted into CaseBlock records, representing basic blocks in the binary
1960 Value *SV = SI.getOperand(0);
1962 // Push the initial CaseRec onto the worklist
1963 CaseRecVector WorkList;
1964 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1966 while (!WorkList.empty()) {
1967 // Grab a record representing a case range to process off the worklist
1968 CaseRec CR = WorkList.back();
1969 WorkList.pop_back();
1971 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1974 // If the range has few cases (two or less) emit a series of specific
1976 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1979 // If the switch has more than 5 blocks, and at least 40% dense, and the
1980 // target supports indirect branches, then emit a jump table rather than
1981 // lowering the switch to a binary tree of conditional branches.
1982 if (handleJTSwitchCase(CR, WorkList, SV, Default))
1985 // Emit binary tree. We need to pick a pivot, and push left and right ranges
1986 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
1987 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
1992 void SelectionDAGLowering::visitSub(User &I) {
1993 // -0.0 - X --> fneg
1994 const Type *Ty = I.getType();
1995 if (isa<VectorType>(Ty)) {
1996 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
1997 const VectorType *DestTy = cast<VectorType>(I.getType());
1998 const Type *ElTy = DestTy->getElementType();
1999 if (ElTy->isFloatingPoint()) {
2000 unsigned VL = DestTy->getNumElements();
2001 std::vector<Constant*> NZ(VL, ConstantFP::get(ElTy, -0.0));
2002 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2004 SDOperand Op2 = getValue(I.getOperand(1));
2005 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2011 if (Ty->isFloatingPoint()) {
2012 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2013 if (CFP->isExactlyValue(-0.0)) {
2014 SDOperand Op2 = getValue(I.getOperand(1));
2015 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2020 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2023 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2024 SDOperand Op1 = getValue(I.getOperand(0));
2025 SDOperand Op2 = getValue(I.getOperand(1));
2027 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2030 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2031 SDOperand Op1 = getValue(I.getOperand(0));
2032 SDOperand Op2 = getValue(I.getOperand(1));
2034 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2035 MVT::getSizeInBits(Op2.getValueType()))
2036 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2037 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2038 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2040 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2043 void SelectionDAGLowering::visitICmp(User &I) {
2044 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2045 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2046 predicate = IC->getPredicate();
2047 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2048 predicate = ICmpInst::Predicate(IC->getPredicate());
2049 SDOperand Op1 = getValue(I.getOperand(0));
2050 SDOperand Op2 = getValue(I.getOperand(1));
2051 ISD::CondCode Opcode;
2052 switch (predicate) {
2053 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2054 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2055 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2056 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2057 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2058 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2059 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2060 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2061 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2062 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2064 assert(!"Invalid ICmp predicate value");
2065 Opcode = ISD::SETEQ;
2068 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2071 void SelectionDAGLowering::visitFCmp(User &I) {
2072 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2073 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2074 predicate = FC->getPredicate();
2075 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2076 predicate = FCmpInst::Predicate(FC->getPredicate());
2077 SDOperand Op1 = getValue(I.getOperand(0));
2078 SDOperand Op2 = getValue(I.getOperand(1));
2079 ISD::CondCode Condition, FOC, FPC;
2080 switch (predicate) {
2081 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2082 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2083 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2084 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2085 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2086 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2087 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2088 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2089 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2090 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2091 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2092 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2093 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2094 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2095 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2096 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2098 assert(!"Invalid FCmp predicate value");
2099 FOC = FPC = ISD::SETFALSE;
2102 if (FiniteOnlyFPMath())
2106 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2109 void SelectionDAGLowering::visitSelect(User &I) {
2110 SDOperand Cond = getValue(I.getOperand(0));
2111 SDOperand TrueVal = getValue(I.getOperand(1));
2112 SDOperand FalseVal = getValue(I.getOperand(2));
2113 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2114 TrueVal, FalseVal));
2118 void SelectionDAGLowering::visitTrunc(User &I) {
2119 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2120 SDOperand N = getValue(I.getOperand(0));
2121 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2122 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2125 void SelectionDAGLowering::visitZExt(User &I) {
2126 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2127 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2128 SDOperand N = getValue(I.getOperand(0));
2129 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2130 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2133 void SelectionDAGLowering::visitSExt(User &I) {
2134 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2135 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2136 SDOperand N = getValue(I.getOperand(0));
2137 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2138 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2141 void SelectionDAGLowering::visitFPTrunc(User &I) {
2142 // FPTrunc is never a no-op cast, no need to check
2143 SDOperand N = getValue(I.getOperand(0));
2144 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2145 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
2148 void SelectionDAGLowering::visitFPExt(User &I){
2149 // FPTrunc is never a no-op cast, no need to check
2150 SDOperand N = getValue(I.getOperand(0));
2151 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2152 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2155 void SelectionDAGLowering::visitFPToUI(User &I) {
2156 // FPToUI is never a no-op cast, no need to check
2157 SDOperand N = getValue(I.getOperand(0));
2158 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2159 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2162 void SelectionDAGLowering::visitFPToSI(User &I) {
2163 // FPToSI is never a no-op cast, no need to check
2164 SDOperand N = getValue(I.getOperand(0));
2165 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2166 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2169 void SelectionDAGLowering::visitUIToFP(User &I) {
2170 // UIToFP is never a no-op cast, no need to check
2171 SDOperand N = getValue(I.getOperand(0));
2172 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2173 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2176 void SelectionDAGLowering::visitSIToFP(User &I){
2177 // UIToFP is never a no-op cast, no need to check
2178 SDOperand N = getValue(I.getOperand(0));
2179 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2180 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2183 void SelectionDAGLowering::visitPtrToInt(User &I) {
2184 // What to do depends on the size of the integer and the size of the pointer.
2185 // We can either truncate, zero extend, or no-op, accordingly.
2186 SDOperand N = getValue(I.getOperand(0));
2187 MVT::ValueType SrcVT = N.getValueType();
2188 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2190 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2191 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2193 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2194 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2195 setValue(&I, Result);
2198 void SelectionDAGLowering::visitIntToPtr(User &I) {
2199 // What to do depends on the size of the integer and the size of the pointer.
2200 // We can either truncate, zero extend, or no-op, accordingly.
2201 SDOperand N = getValue(I.getOperand(0));
2202 MVT::ValueType SrcVT = N.getValueType();
2203 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2204 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2205 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2207 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2208 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2211 void SelectionDAGLowering::visitBitCast(User &I) {
2212 SDOperand N = getValue(I.getOperand(0));
2213 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2215 // BitCast assures us that source and destination are the same size so this
2216 // is either a BIT_CONVERT or a no-op.
2217 if (DestVT != N.getValueType())
2218 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2220 setValue(&I, N); // noop cast.
2223 void SelectionDAGLowering::visitInsertElement(User &I) {
2224 SDOperand InVec = getValue(I.getOperand(0));
2225 SDOperand InVal = getValue(I.getOperand(1));
2226 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2227 getValue(I.getOperand(2)));
2229 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2230 TLI.getValueType(I.getType()),
2231 InVec, InVal, InIdx));
2234 void SelectionDAGLowering::visitExtractElement(User &I) {
2235 SDOperand InVec = getValue(I.getOperand(0));
2236 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2237 getValue(I.getOperand(1)));
2238 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2239 TLI.getValueType(I.getType()), InVec, InIdx));
2242 void SelectionDAGLowering::visitShuffleVector(User &I) {
2243 SDOperand V1 = getValue(I.getOperand(0));
2244 SDOperand V2 = getValue(I.getOperand(1));
2245 SDOperand Mask = getValue(I.getOperand(2));
2247 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2248 TLI.getValueType(I.getType()),
2253 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2254 SDOperand N = getValue(I.getOperand(0));
2255 const Type *Ty = I.getOperand(0)->getType();
2257 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2260 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2261 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2264 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2265 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2266 getIntPtrConstant(Offset));
2268 Ty = StTy->getElementType(Field);
2270 Ty = cast<SequentialType>(Ty)->getElementType();
2272 // If this is a constant subscript, handle it quickly.
2273 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2274 if (CI->getZExtValue() == 0) continue;
2276 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2277 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
2281 // N = N + Idx * ElementSize;
2282 uint64_t ElementSize = TD->getTypeSize(Ty);
2283 SDOperand IdxN = getValue(Idx);
2285 // If the index is smaller or larger than intptr_t, truncate or extend
2287 if (IdxN.getValueType() < N.getValueType()) {
2288 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2289 } else if (IdxN.getValueType() > N.getValueType())
2290 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2292 // If this is a multiply by a power of two, turn it into a shl
2293 // immediately. This is a very common case.
2294 if (isPowerOf2_64(ElementSize)) {
2295 unsigned Amt = Log2_64(ElementSize);
2296 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2297 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2298 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2302 SDOperand Scale = getIntPtrConstant(ElementSize);
2303 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2304 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2310 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2311 // If this is a fixed sized alloca in the entry block of the function,
2312 // allocate it statically on the stack.
2313 if (FuncInfo.StaticAllocaMap.count(&I))
2314 return; // getValue will auto-populate this.
2316 const Type *Ty = I.getAllocatedType();
2317 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
2319 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2322 SDOperand AllocSize = getValue(I.getArraySize());
2323 MVT::ValueType IntPtr = TLI.getPointerTy();
2324 if (IntPtr < AllocSize.getValueType())
2325 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2326 else if (IntPtr > AllocSize.getValueType())
2327 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2329 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2330 getIntPtrConstant(TySize));
2332 // Handle alignment. If the requested alignment is less than or equal to
2333 // the stack alignment, ignore it. If the size is greater than or equal to
2334 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2335 unsigned StackAlign =
2336 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2337 if (Align <= StackAlign)
2340 // Round the size of the allocation up to the stack alignment size
2341 // by add SA-1 to the size.
2342 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2343 getIntPtrConstant(StackAlign-1));
2344 // Mask out the low bits for alignment purposes.
2345 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2346 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2348 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
2349 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2351 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2353 DAG.setRoot(DSA.getValue(1));
2355 // Inform the Frame Information that we have just allocated a variable-sized
2357 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2360 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2361 SDOperand Ptr = getValue(I.getOperand(0));
2367 // Do not serialize non-volatile loads against each other.
2368 Root = DAG.getRoot();
2371 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2372 Root, I.isVolatile(), I.getAlignment()));
2375 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2376 const Value *SV, SDOperand Root,
2378 unsigned Alignment) {
2380 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2381 isVolatile, Alignment);
2384 DAG.setRoot(L.getValue(1));
2386 PendingLoads.push_back(L.getValue(1));
2392 void SelectionDAGLowering::visitStore(StoreInst &I) {
2393 Value *SrcV = I.getOperand(0);
2394 SDOperand Src = getValue(SrcV);
2395 SDOperand Ptr = getValue(I.getOperand(1));
2396 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2397 I.isVolatile(), I.getAlignment()));
2400 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
2401 /// access memory and has no other side effects at all.
2402 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
2403 #define GET_NO_MEMORY_INTRINSICS
2404 #include "llvm/Intrinsics.gen"
2405 #undef GET_NO_MEMORY_INTRINSICS
2409 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
2410 // have any side-effects or if it only reads memory.
2411 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
2412 #define GET_SIDE_EFFECT_INFO
2413 #include "llvm/Intrinsics.gen"
2414 #undef GET_SIDE_EFFECT_INFO
2418 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2420 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2421 unsigned Intrinsic) {
2422 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
2423 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
2425 // Build the operand list.
2426 SmallVector<SDOperand, 8> Ops;
2427 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2429 // We don't need to serialize loads against other loads.
2430 Ops.push_back(DAG.getRoot());
2432 Ops.push_back(getRoot());
2436 // Add the intrinsic ID as an integer operand.
2437 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2439 // Add all operands of the call to the operand list.
2440 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2441 SDOperand Op = getValue(I.getOperand(i));
2442 assert(TLI.isTypeLegal(Op.getValueType()) &&
2443 "Intrinsic uses a non-legal type?");
2447 std::vector<MVT::ValueType> VTs;
2448 if (I.getType() != Type::VoidTy) {
2449 MVT::ValueType VT = TLI.getValueType(I.getType());
2450 if (MVT::isVector(VT)) {
2451 const VectorType *DestTy = cast<VectorType>(I.getType());
2452 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2454 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2455 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2458 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2462 VTs.push_back(MVT::Other);
2464 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2469 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2470 &Ops[0], Ops.size());
2471 else if (I.getType() != Type::VoidTy)
2472 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2473 &Ops[0], Ops.size());
2475 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2476 &Ops[0], Ops.size());
2479 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2481 PendingLoads.push_back(Chain);
2485 if (I.getType() != Type::VoidTy) {
2486 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2487 MVT::ValueType VT = TLI.getValueType(PTy);
2488 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2490 setValue(&I, Result);
2494 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2495 static GlobalVariable *ExtractTypeInfo (Value *V) {
2496 V = IntrinsicInst::StripPointerCasts(V);
2497 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2498 assert (GV || isa<ConstantPointerNull>(V) &&
2499 "TypeInfo must be a global variable or NULL");
2503 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2504 /// call, and add them to the specified machine basic block.
2505 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2506 MachineBasicBlock *MBB) {
2507 // Inform the MachineModuleInfo of the personality for this landing pad.
2508 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2509 assert(CE->getOpcode() == Instruction::BitCast &&
2510 isa<Function>(CE->getOperand(0)) &&
2511 "Personality should be a function");
2512 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2514 // Gather all the type infos for this landing pad and pass them along to
2515 // MachineModuleInfo.
2516 std::vector<GlobalVariable *> TyInfo;
2517 unsigned N = I.getNumOperands();
2519 for (unsigned i = N - 1; i > 2; --i) {
2520 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2521 unsigned FilterLength = CI->getZExtValue();
2522 unsigned FirstCatch = i + FilterLength + 1;
2523 assert (FirstCatch <= N && "Invalid filter length");
2525 if (FirstCatch < N) {
2526 TyInfo.reserve(N - FirstCatch);
2527 for (unsigned j = FirstCatch; j < N; ++j)
2528 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2529 MMI->addCatchTypeInfo(MBB, TyInfo);
2533 TyInfo.reserve(FilterLength);
2534 for (unsigned j = i + 1; j < FirstCatch; ++j)
2535 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2536 MMI->addFilterTypeInfo(MBB, TyInfo);
2544 TyInfo.reserve(N - 3);
2545 for (unsigned j = 3; j < N; ++j)
2546 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2547 MMI->addCatchTypeInfo(MBB, TyInfo);
2551 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2552 /// we want to emit this as a call to a named external function, return the name
2553 /// otherwise lower it and return null.
2555 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2556 switch (Intrinsic) {
2558 // By default, turn this into a target intrinsic node.
2559 visitTargetIntrinsic(I, Intrinsic);
2561 case Intrinsic::vastart: visitVAStart(I); return 0;
2562 case Intrinsic::vaend: visitVAEnd(I); return 0;
2563 case Intrinsic::vacopy: visitVACopy(I); return 0;
2564 case Intrinsic::returnaddress:
2565 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2566 getValue(I.getOperand(1))));
2568 case Intrinsic::frameaddress:
2569 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2570 getValue(I.getOperand(1))));
2572 case Intrinsic::setjmp:
2573 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2575 case Intrinsic::longjmp:
2576 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2578 case Intrinsic::memcpy_i32:
2579 case Intrinsic::memcpy_i64:
2580 visitMemIntrinsic(I, ISD::MEMCPY);
2582 case Intrinsic::memset_i32:
2583 case Intrinsic::memset_i64:
2584 visitMemIntrinsic(I, ISD::MEMSET);
2586 case Intrinsic::memmove_i32:
2587 case Intrinsic::memmove_i64:
2588 visitMemIntrinsic(I, ISD::MEMMOVE);
2591 case Intrinsic::dbg_stoppoint: {
2592 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2593 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2594 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2598 Ops[1] = getValue(SPI.getLineValue());
2599 Ops[2] = getValue(SPI.getColumnValue());
2601 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2602 assert(DD && "Not a debug information descriptor");
2603 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2605 Ops[3] = DAG.getString(CompileUnit->getFileName());
2606 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2608 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2613 case Intrinsic::dbg_region_start: {
2614 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2615 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2616 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2617 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2618 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2619 DAG.getConstant(LabelID, MVT::i32)));
2624 case Intrinsic::dbg_region_end: {
2625 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2626 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2627 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2628 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2629 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2630 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2635 case Intrinsic::dbg_func_start: {
2636 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2637 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2638 if (MMI && FSI.getSubprogram() &&
2639 MMI->Verify(FSI.getSubprogram())) {
2640 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
2641 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2642 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2647 case Intrinsic::dbg_declare: {
2648 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2649 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2650 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
2651 SDOperand AddressOp = getValue(DI.getAddress());
2652 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2653 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
2659 case Intrinsic::eh_exception: {
2660 if (ExceptionHandling) {
2661 if (!CurMBB->isLandingPad()) {
2662 // FIXME: Mark exception register as live in. Hack for PR1508.
2663 unsigned Reg = TLI.getExceptionAddressRegister();
2664 if (Reg) CurMBB->addLiveIn(Reg);
2666 // Insert the EXCEPTIONADDR instruction.
2667 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2669 Ops[0] = DAG.getRoot();
2670 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2672 DAG.setRoot(Op.getValue(1));
2674 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2679 case Intrinsic::eh_selector:{
2680 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2682 if (ExceptionHandling && MMI) {
2683 if (CurMBB->isLandingPad())
2684 addCatchInfo(I, MMI, CurMBB);
2687 FuncInfo.CatchInfoLost.insert(&I);
2689 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2690 unsigned Reg = TLI.getExceptionSelectorRegister();
2691 if (Reg) CurMBB->addLiveIn(Reg);
2694 // Insert the EHSELECTION instruction.
2695 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2697 Ops[0] = getValue(I.getOperand(1));
2699 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2701 DAG.setRoot(Op.getValue(1));
2703 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2709 case Intrinsic::eh_typeid_for: {
2710 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2713 // Find the type id for the given typeinfo.
2714 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2716 unsigned TypeID = MMI->getTypeIDFor(GV);
2717 setValue(&I, DAG.getConstant(TypeID, MVT::i32));
2719 // Return something different to eh_selector.
2720 setValue(&I, DAG.getConstant(1, MVT::i32));
2726 case Intrinsic::eh_return: {
2727 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2729 if (MMI && ExceptionHandling) {
2730 MMI->setCallsEHReturn(true);
2731 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2734 getValue(I.getOperand(1)),
2735 getValue(I.getOperand(2))));
2737 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2743 case Intrinsic::eh_unwind_init: {
2744 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2745 MMI->setCallsUnwindInit(true);
2751 case Intrinsic::eh_dwarf_cfa: {
2752 if (ExceptionHandling) {
2753 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2754 SDOperand Offset = DAG.getNode(ISD::ADD,
2756 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2758 getValue(I.getOperand(1)));
2759 setValue(&I, DAG.getNode(ISD::ADD,
2761 DAG.getNode(ISD::FRAMEADDR,
2764 TLI.getPointerTy())),
2767 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2773 case Intrinsic::sqrt_f32:
2774 case Intrinsic::sqrt_f64:
2775 setValue(&I, DAG.getNode(ISD::FSQRT,
2776 getValue(I.getOperand(1)).getValueType(),
2777 getValue(I.getOperand(1))));
2779 case Intrinsic::powi_f32:
2780 case Intrinsic::powi_f64:
2781 setValue(&I, DAG.getNode(ISD::FPOWI,
2782 getValue(I.getOperand(1)).getValueType(),
2783 getValue(I.getOperand(1)),
2784 getValue(I.getOperand(2))));
2786 case Intrinsic::pcmarker: {
2787 SDOperand Tmp = getValue(I.getOperand(1));
2788 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2791 case Intrinsic::readcyclecounter: {
2792 SDOperand Op = getRoot();
2793 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2794 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2797 DAG.setRoot(Tmp.getValue(1));
2800 case Intrinsic::part_select: {
2801 // Currently not implemented: just abort
2802 assert(0 && "part_select intrinsic not implemented");
2805 case Intrinsic::part_set: {
2806 // Currently not implemented: just abort
2807 assert(0 && "part_set intrinsic not implemented");
2810 case Intrinsic::bswap:
2811 setValue(&I, DAG.getNode(ISD::BSWAP,
2812 getValue(I.getOperand(1)).getValueType(),
2813 getValue(I.getOperand(1))));
2815 case Intrinsic::cttz: {
2816 SDOperand Arg = getValue(I.getOperand(1));
2817 MVT::ValueType Ty = Arg.getValueType();
2818 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2819 setValue(&I, result);
2822 case Intrinsic::ctlz: {
2823 SDOperand Arg = getValue(I.getOperand(1));
2824 MVT::ValueType Ty = Arg.getValueType();
2825 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2826 setValue(&I, result);
2829 case Intrinsic::ctpop: {
2830 SDOperand Arg = getValue(I.getOperand(1));
2831 MVT::ValueType Ty = Arg.getValueType();
2832 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2833 setValue(&I, result);
2836 case Intrinsic::stacksave: {
2837 SDOperand Op = getRoot();
2838 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2839 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2841 DAG.setRoot(Tmp.getValue(1));
2844 case Intrinsic::stackrestore: {
2845 SDOperand Tmp = getValue(I.getOperand(1));
2846 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2849 case Intrinsic::prefetch:
2850 // FIXME: Currently discarding prefetches.
2853 case Intrinsic::var_annotation:
2854 // Discard annotate attributes
2857 case Intrinsic::adjust_trampoline: {
2858 SDOperand Arg = getValue(I.getOperand(1));
2859 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMP, TLI.getPointerTy(), Arg));
2863 case Intrinsic::init_trampoline: {
2865 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
2869 Ops[1] = getValue(I.getOperand(1));
2870 Ops[2] = getValue(I.getOperand(2));
2871 Ops[3] = getValue(I.getOperand(3));
2872 Ops[4] = DAG.getSrcValue(I.getOperand(1));
2873 Ops[5] = DAG.getSrcValue(F);
2875 DAG.setRoot(DAG.getNode(ISD::TRAMPOLINE, MVT::Other, Ops, 6));
2882 void SelectionDAGLowering::LowerCallTo(Instruction &I,
2883 const Type *CalledValueTy,
2884 unsigned CallingConv,
2886 SDOperand Callee, unsigned OpIdx,
2887 MachineBasicBlock *LandingPad) {
2888 const PointerType *PT = cast<PointerType>(CalledValueTy);
2889 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2890 const ParamAttrsList *Attrs = FTy->getParamAttrs();
2891 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2892 unsigned BeginLabel = 0, EndLabel = 0;
2894 TargetLowering::ArgListTy Args;
2895 TargetLowering::ArgListEntry Entry;
2896 Args.reserve(I.getNumOperands());
2897 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) {
2898 Value *Arg = I.getOperand(i);
2899 SDOperand ArgNode = getValue(Arg);
2900 Entry.Node = ArgNode; Entry.Ty = Arg->getType();
2902 unsigned attrInd = i - OpIdx + 1;
2903 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt);
2904 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt);
2905 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg);
2906 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet);
2907 Entry.isNest = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::Nest);
2908 Args.push_back(Entry);
2911 if (ExceptionHandling && MMI) {
2912 // Insert a label before the invoke call to mark the try range. This can be
2913 // used to detect deletion of the invoke via the MachineModuleInfo.
2914 BeginLabel = MMI->NextLabelID();
2915 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2916 DAG.getConstant(BeginLabel, MVT::i32)));
2919 std::pair<SDOperand,SDOperand> Result =
2920 TLI.LowerCallTo(getRoot(), I.getType(),
2921 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt),
2922 FTy->isVarArg(), CallingConv, IsTailCall,
2924 if (I.getType() != Type::VoidTy)
2925 setValue(&I, Result.first);
2926 DAG.setRoot(Result.second);
2928 if (ExceptionHandling && MMI) {
2929 // Insert a label at the end of the invoke call to mark the try range. This
2930 // can be used to detect deletion of the invoke via the MachineModuleInfo.
2931 EndLabel = MMI->NextLabelID();
2932 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2933 DAG.getConstant(EndLabel, MVT::i32)));
2935 // Inform MachineModuleInfo of range.
2936 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
2941 void SelectionDAGLowering::visitCall(CallInst &I) {
2942 const char *RenameFn = 0;
2943 if (Function *F = I.getCalledFunction()) {
2944 if (F->isDeclaration())
2945 if (unsigned IID = F->getIntrinsicID()) {
2946 RenameFn = visitIntrinsicCall(I, IID);
2949 } else { // Not an LLVM intrinsic.
2950 const std::string &Name = F->getName();
2951 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
2952 if (I.getNumOperands() == 3 && // Basic sanity checks.
2953 I.getOperand(1)->getType()->isFloatingPoint() &&
2954 I.getType() == I.getOperand(1)->getType() &&
2955 I.getType() == I.getOperand(2)->getType()) {
2956 SDOperand LHS = getValue(I.getOperand(1));
2957 SDOperand RHS = getValue(I.getOperand(2));
2958 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
2962 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
2963 if (I.getNumOperands() == 2 && // Basic sanity checks.
2964 I.getOperand(1)->getType()->isFloatingPoint() &&
2965 I.getType() == I.getOperand(1)->getType()) {
2966 SDOperand Tmp = getValue(I.getOperand(1));
2967 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
2970 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
2971 if (I.getNumOperands() == 2 && // Basic sanity checks.
2972 I.getOperand(1)->getType()->isFloatingPoint() &&
2973 I.getType() == I.getOperand(1)->getType()) {
2974 SDOperand Tmp = getValue(I.getOperand(1));
2975 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
2978 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
2979 if (I.getNumOperands() == 2 && // Basic sanity checks.
2980 I.getOperand(1)->getType()->isFloatingPoint() &&
2981 I.getType() == I.getOperand(1)->getType()) {
2982 SDOperand Tmp = getValue(I.getOperand(1));
2983 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
2988 } else if (isa<InlineAsm>(I.getOperand(0))) {
2995 Callee = getValue(I.getOperand(0));
2997 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
2999 LowerCallTo(I, I.getCalledValue()->getType(),
3007 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3008 /// this value and returns the result as a ValueVT value. This uses
3009 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3010 /// If the Flag pointer is NULL, no flag is used.
3011 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3012 SDOperand &Chain, SDOperand *Flag)const{
3013 // Copy the legal parts from the registers.
3014 unsigned NumParts = Regs.size();
3015 SmallVector<SDOperand, 8> Parts(NumParts);
3016 for (unsigned i = 0; i != NumParts; ++i) {
3017 SDOperand Part = Flag ?
3018 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3019 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3020 Chain = Part.getValue(1);
3022 *Flag = Part.getValue(2);
3026 // Assemble the legal parts into the final value.
3027 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3030 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3031 /// specified value into the registers specified by this object. This uses
3032 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3033 /// If the Flag pointer is NULL, no flag is used.
3034 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3035 SDOperand &Chain, SDOperand *Flag) const {
3036 // Get the list of the values's legal parts.
3037 unsigned NumParts = Regs.size();
3038 SmallVector<SDOperand, 8> Parts(NumParts);
3039 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3041 // Copy the parts into the registers.
3042 for (unsigned i = 0; i != NumParts; ++i) {
3043 SDOperand Part = Flag ?
3044 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3045 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3046 Chain = Part.getValue(0);
3048 *Flag = Part.getValue(1);
3052 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3053 /// operand list. This adds the code marker and includes the number of
3054 /// values added into it.
3055 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3056 std::vector<SDOperand> &Ops) const {
3057 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3058 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3059 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3060 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3063 /// isAllocatableRegister - If the specified register is safe to allocate,
3064 /// i.e. it isn't a stack pointer or some other special register, return the
3065 /// register class for the register. Otherwise, return null.
3066 static const TargetRegisterClass *
3067 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3068 const TargetLowering &TLI, const MRegisterInfo *MRI) {
3069 MVT::ValueType FoundVT = MVT::Other;
3070 const TargetRegisterClass *FoundRC = 0;
3071 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
3072 E = MRI->regclass_end(); RCI != E; ++RCI) {
3073 MVT::ValueType ThisVT = MVT::Other;
3075 const TargetRegisterClass *RC = *RCI;
3076 // If none of the the value types for this register class are valid, we
3077 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3078 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3080 if (TLI.isTypeLegal(*I)) {
3081 // If we have already found this register in a different register class,
3082 // choose the one with the largest VT specified. For example, on
3083 // PowerPC, we favor f64 register classes over f32.
3084 if (FoundVT == MVT::Other ||
3085 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3092 if (ThisVT == MVT::Other) continue;
3094 // NOTE: This isn't ideal. In particular, this might allocate the
3095 // frame pointer in functions that need it (due to them not being taken
3096 // out of allocation, because a variable sized allocation hasn't been seen
3097 // yet). This is a slight code pessimization, but should still work.
3098 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3099 E = RC->allocation_order_end(MF); I != E; ++I)
3101 // We found a matching register class. Keep looking at others in case
3102 // we find one with larger registers that this physreg is also in.
3113 /// AsmOperandInfo - This contains information for each constraint that we are
3115 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3116 /// ConstraintCode - This contains the actual string for the code, like "m".
3117 std::string ConstraintCode;
3119 /// ConstraintType - Information about the constraint code, e.g. Register,
3120 /// RegisterClass, Memory, Other, Unknown.
3121 TargetLowering::ConstraintType ConstraintType;
3123 /// CallOperand/CallOperandval - If this is the result output operand or a
3124 /// clobber, this is null, otherwise it is the incoming operand to the
3125 /// CallInst. This gets modified as the asm is processed.
3126 SDOperand CallOperand;
3127 Value *CallOperandVal;
3129 /// ConstraintVT - The ValueType for the operand value.
3130 MVT::ValueType ConstraintVT;
3132 /// AssignedRegs - If this is a register or register class operand, this
3133 /// contains the set of register corresponding to the operand.
3134 RegsForValue AssignedRegs;
3136 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3137 : InlineAsm::ConstraintInfo(info),
3138 ConstraintType(TargetLowering::C_Unknown),
3139 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3142 void ComputeConstraintToUse(const TargetLowering &TLI);
3144 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3145 /// busy in OutputRegs/InputRegs.
3146 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3147 std::set<unsigned> &OutputRegs,
3148 std::set<unsigned> &InputRegs) const {
3150 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3152 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3155 } // end anon namespace.
3157 /// getConstraintGenerality - Return an integer indicating how general CT is.
3158 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3160 default: assert(0 && "Unknown constraint type!");
3161 case TargetLowering::C_Other:
3162 case TargetLowering::C_Unknown:
3164 case TargetLowering::C_Register:
3166 case TargetLowering::C_RegisterClass:
3168 case TargetLowering::C_Memory:
3173 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3174 assert(!Codes.empty() && "Must have at least one constraint");
3176 std::string *Current = &Codes[0];
3177 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3178 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3179 ConstraintCode = *Current;
3180 ConstraintType = CurType;
3184 unsigned CurGenerality = getConstraintGenerality(CurType);
3186 // If we have multiple constraints, try to pick the most general one ahead
3187 // of time. This isn't a wonderful solution, but handles common cases.
3188 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3189 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3190 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3191 if (ThisGenerality > CurGenerality) {
3192 // This constraint letter is more general than the previous one,
3195 Current = &Codes[j];
3196 CurGenerality = ThisGenerality;
3200 ConstraintCode = *Current;
3201 ConstraintType = CurType;
3205 void SelectionDAGLowering::
3206 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3207 std::set<unsigned> &OutputRegs,
3208 std::set<unsigned> &InputRegs) {
3209 // Compute whether this value requires an input register, an output register,
3211 bool isOutReg = false;
3212 bool isInReg = false;
3213 switch (OpInfo.Type) {
3214 case InlineAsm::isOutput:
3217 // If this is an early-clobber output, or if there is an input
3218 // constraint that matches this, we need to reserve the input register
3219 // so no other inputs allocate to it.
3220 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3222 case InlineAsm::isInput:
3226 case InlineAsm::isClobber:
3233 MachineFunction &MF = DAG.getMachineFunction();
3234 std::vector<unsigned> Regs;
3236 // If this is a constraint for a single physreg, or a constraint for a
3237 // register class, find it.
3238 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3239 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3240 OpInfo.ConstraintVT);
3242 unsigned NumRegs = 1;
3243 if (OpInfo.ConstraintVT != MVT::Other)
3244 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3245 MVT::ValueType RegVT;
3246 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3249 // If this is a constraint for a specific physical register, like {r17},
3251 if (PhysReg.first) {
3252 if (OpInfo.ConstraintVT == MVT::Other)
3253 ValueVT = *PhysReg.second->vt_begin();
3255 // Get the actual register value type. This is important, because the user
3256 // may have asked for (e.g.) the AX register in i32 type. We need to
3257 // remember that AX is actually i16 to get the right extension.
3258 RegVT = *PhysReg.second->vt_begin();
3260 // This is a explicit reference to a physical register.
3261 Regs.push_back(PhysReg.first);
3263 // If this is an expanded reference, add the rest of the regs to Regs.
3265 TargetRegisterClass::iterator I = PhysReg.second->begin();
3266 TargetRegisterClass::iterator E = PhysReg.second->end();
3267 for (; *I != PhysReg.first; ++I)
3268 assert(I != E && "Didn't find reg!");
3270 // Already added the first reg.
3272 for (; NumRegs; --NumRegs, ++I) {
3273 assert(I != E && "Ran out of registers to allocate!");
3277 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3278 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3282 // Otherwise, if this was a reference to an LLVM register class, create vregs
3283 // for this reference.
3284 std::vector<unsigned> RegClassRegs;
3285 const TargetRegisterClass *RC = PhysReg.second;
3287 // If this is an early clobber or tied register, our regalloc doesn't know
3288 // how to maintain the constraint. If it isn't, go ahead and create vreg
3289 // and let the regalloc do the right thing.
3290 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3291 // If there is some other early clobber and this is an input register,
3292 // then we are forced to pre-allocate the input reg so it doesn't
3293 // conflict with the earlyclobber.
3294 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3295 RegVT = *PhysReg.second->vt_begin();
3297 if (OpInfo.ConstraintVT == MVT::Other)
3300 // Create the appropriate number of virtual registers.
3301 SSARegMap *RegMap = MF.getSSARegMap();
3302 for (; NumRegs; --NumRegs)
3303 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
3305 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3306 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3310 // Otherwise, we can't allocate it. Let the code below figure out how to
3311 // maintain these constraints.
3312 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3315 // This is a reference to a register class that doesn't directly correspond
3316 // to an LLVM register class. Allocate NumRegs consecutive, available,
3317 // registers from the class.
3318 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3319 OpInfo.ConstraintVT);
3322 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3323 unsigned NumAllocated = 0;
3324 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3325 unsigned Reg = RegClassRegs[i];
3326 // See if this register is available.
3327 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3328 (isInReg && InputRegs.count(Reg))) { // Already used.
3329 // Make sure we find consecutive registers.
3334 // Check to see if this register is allocatable (i.e. don't give out the
3337 RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3338 if (!RC) { // Couldn't allocate this register.
3339 // Reset NumAllocated to make sure we return consecutive registers.
3345 // Okay, this register is good, we can use it.
3348 // If we allocated enough consecutive registers, succeed.
3349 if (NumAllocated == NumRegs) {
3350 unsigned RegStart = (i-NumAllocated)+1;
3351 unsigned RegEnd = i+1;
3352 // Mark all of the allocated registers used.
3353 for (unsigned i = RegStart; i != RegEnd; ++i)
3354 Regs.push_back(RegClassRegs[i]);
3356 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3357 OpInfo.ConstraintVT);
3358 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3363 // Otherwise, we couldn't allocate enough registers for this.
3368 /// visitInlineAsm - Handle a call to an InlineAsm object.
3370 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
3371 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
3373 /// ConstraintOperands - Information about all of the constraints.
3374 std::vector<AsmOperandInfo> ConstraintOperands;
3376 SDOperand Chain = getRoot();
3379 std::set<unsigned> OutputRegs, InputRegs;
3381 // Do a prepass over the constraints, canonicalizing them, and building up the
3382 // ConstraintOperands list.
3383 std::vector<InlineAsm::ConstraintInfo>
3384 ConstraintInfos = IA->ParseConstraints();
3386 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3387 // constraint. If so, we can't let the register allocator allocate any input
3388 // registers, because it will not know to avoid the earlyclobbered output reg.
3389 bool SawEarlyClobber = false;
3391 unsigned OpNo = 1; // OpNo - The operand of the CallInst.
3392 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3393 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3394 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3396 MVT::ValueType OpVT = MVT::Other;
3398 // Compute the value type for each operand.
3399 switch (OpInfo.Type) {
3400 case InlineAsm::isOutput:
3401 if (!OpInfo.isIndirect) {
3402 // The return value of the call is this value. As such, there is no
3403 // corresponding argument.
3404 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
3405 OpVT = TLI.getValueType(I.getType());
3407 OpInfo.CallOperandVal = I.getOperand(OpNo++);
3410 case InlineAsm::isInput:
3411 OpInfo.CallOperandVal = I.getOperand(OpNo++);
3413 case InlineAsm::isClobber:
3418 // If this is an input or an indirect output, process the call argument.
3419 if (OpInfo.CallOperandVal) {
3420 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3421 const Type *OpTy = OpInfo.CallOperandVal->getType();
3422 // If this is an indirect operand, the operand is a pointer to the
3424 if (OpInfo.isIndirect)
3425 OpTy = cast<PointerType>(OpTy)->getElementType();
3427 // If OpTy is not a first-class value, it may be a struct/union that we
3428 // can tile with integers.
3429 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3430 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3438 OpTy = IntegerType::get(BitSize);
3443 OpVT = TLI.getValueType(OpTy, true);
3446 OpInfo.ConstraintVT = OpVT;
3448 // Compute the constraint code and ConstraintType to use.
3449 OpInfo.ComputeConstraintToUse(TLI);
3451 // Keep track of whether we see an earlyclobber.
3452 SawEarlyClobber |= OpInfo.isEarlyClobber;
3454 // If this is a memory input, and if the operand is not indirect, do what we
3455 // need to to provide an address for the memory input.
3456 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3457 !OpInfo.isIndirect) {
3458 assert(OpInfo.Type == InlineAsm::isInput &&
3459 "Can only indirectify direct input operands!");
3461 // Memory operands really want the address of the value. If we don't have
3462 // an indirect input, put it in the constpool if we can, otherwise spill
3463 // it to a stack slot.
3465 // If the operand is a float, integer, or vector constant, spill to a
3466 // constant pool entry to get its address.
3467 Value *OpVal = OpInfo.CallOperandVal;
3468 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3469 isa<ConstantVector>(OpVal)) {
3470 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3471 TLI.getPointerTy());
3473 // Otherwise, create a stack slot and emit a store to it before the
3475 const Type *Ty = OpVal->getType();
3476 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3477 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3478 MachineFunction &MF = DAG.getMachineFunction();
3479 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3480 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3481 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3482 OpInfo.CallOperand = StackSlot;
3485 // There is no longer a Value* corresponding to this operand.
3486 OpInfo.CallOperandVal = 0;
3487 // It is now an indirect operand.
3488 OpInfo.isIndirect = true;
3491 // If this constraint is for a specific register, allocate it before
3493 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3494 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3496 ConstraintInfos.clear();
3499 // Second pass - Loop over all of the operands, assigning virtual or physregs
3500 // to registerclass operands.
3501 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3502 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3504 // C_Register operands have already been allocated, Other/Memory don't need
3506 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3507 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3510 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3511 std::vector<SDOperand> AsmNodeOperands;
3512 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3513 AsmNodeOperands.push_back(
3514 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3517 // Loop over all of the inputs, copying the operand values into the
3518 // appropriate registers and processing the output regs.
3519 RegsForValue RetValRegs;
3521 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3522 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3524 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3525 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3527 switch (OpInfo.Type) {
3528 case InlineAsm::isOutput: {
3529 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3530 OpInfo.ConstraintType != TargetLowering::C_Register) {
3531 // Memory output, or 'other' output (e.g. 'X' constraint).
3532 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3534 // Add information to the INLINEASM node to know about this output.
3535 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3536 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3537 TLI.getPointerTy()));
3538 AsmNodeOperands.push_back(OpInfo.CallOperand);
3542 // Otherwise, this is a register or register class output.
3544 // Copy the output from the appropriate register. Find a register that
3546 if (OpInfo.AssignedRegs.Regs.empty()) {
3547 cerr << "Couldn't allocate output reg for contraint '"
3548 << OpInfo.ConstraintCode << "'!\n";
3552 if (!OpInfo.isIndirect) {
3553 // This is the result value of the call.
3554 assert(RetValRegs.Regs.empty() &&
3555 "Cannot have multiple output constraints yet!");
3556 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
3557 RetValRegs = OpInfo.AssignedRegs;
3559 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3560 OpInfo.CallOperandVal));
3563 // Add information to the INLINEASM node to know that this register is
3565 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3569 case InlineAsm::isInput: {
3570 SDOperand InOperandVal = OpInfo.CallOperand;
3572 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3573 // If this is required to match an output register we have already set,
3574 // just use its register.
3575 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3577 // Scan until we find the definition we already emitted of this operand.
3578 // When we find it, create a RegsForValue operand.
3579 unsigned CurOp = 2; // The first operand.
3580 for (; OperandNo; --OperandNo) {
3581 // Advance to the next operand.
3583 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3584 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3585 (NumOps & 7) == 4 /*MEM*/) &&
3586 "Skipped past definitions?");
3587 CurOp += (NumOps>>3)+1;
3591 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3592 if ((NumOps & 7) == 2 /*REGDEF*/) {
3593 // Add NumOps>>3 registers to MatchedRegs.
3594 RegsForValue MatchedRegs;
3595 MatchedRegs.ValueVT = InOperandVal.getValueType();
3596 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3597 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3599 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3600 MatchedRegs.Regs.push_back(Reg);
3603 // Use the produced MatchedRegs object to
3604 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3605 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3608 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3609 assert(0 && "matching constraints for memory operands unimp");
3613 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3614 assert(!OpInfo.isIndirect &&
3615 "Don't know how to handle indirect other inputs yet!");
3617 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
3618 OpInfo.ConstraintCode[0],
3620 if (!InOperandVal.Val) {
3621 cerr << "Invalid operand for inline asm constraint '"
3622 << OpInfo.ConstraintCode << "'!\n";
3626 // Add information to the INLINEASM node to know about this input.
3627 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
3628 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3629 TLI.getPointerTy()));
3630 AsmNodeOperands.push_back(InOperandVal);
3632 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3633 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3634 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3635 "Memory operands expect pointer values");
3637 // Add information to the INLINEASM node to know about this input.
3638 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3639 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3640 TLI.getPointerTy()));
3641 AsmNodeOperands.push_back(InOperandVal);
3645 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3646 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3647 "Unknown constraint type!");
3648 assert(!OpInfo.isIndirect &&
3649 "Don't know how to handle indirect register inputs yet!");
3651 // Copy the input into the appropriate registers.
3652 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3653 "Couldn't allocate input reg!");
3655 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3657 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3661 case InlineAsm::isClobber: {
3662 // Add the clobbered value to the operand list, so that the register
3663 // allocator is aware that the physreg got clobbered.
3664 if (!OpInfo.AssignedRegs.Regs.empty())
3665 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3672 // Finish up input operands.
3673 AsmNodeOperands[0] = Chain;
3674 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3676 Chain = DAG.getNode(ISD::INLINEASM,
3677 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3678 &AsmNodeOperands[0], AsmNodeOperands.size());
3679 Flag = Chain.getValue(1);
3681 // If this asm returns a register value, copy the result from that register
3682 // and set it as the value of the call.
3683 if (!RetValRegs.Regs.empty()) {
3684 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3686 // If the result of the inline asm is a vector, it may have the wrong
3687 // width/num elts. Make sure to convert it to the right type with
3689 if (MVT::isVector(Val.getValueType())) {
3690 const VectorType *VTy = cast<VectorType>(I.getType());
3691 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3693 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3699 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3701 // Process indirect outputs, first output all of the flagged copies out of
3703 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3704 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3705 Value *Ptr = IndirectStoresToEmit[i].second;
3706 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3707 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3710 // Emit the non-flagged stores from the physregs.
3711 SmallVector<SDOperand, 8> OutChains;
3712 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3713 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3714 getValue(StoresToEmit[i].second),
3715 StoresToEmit[i].second, 0));
3716 if (!OutChains.empty())
3717 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3718 &OutChains[0], OutChains.size());
3723 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3724 SDOperand Src = getValue(I.getOperand(0));
3726 MVT::ValueType IntPtr = TLI.getPointerTy();
3728 if (IntPtr < Src.getValueType())
3729 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3730 else if (IntPtr > Src.getValueType())
3731 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3733 // Scale the source by the type size.
3734 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
3735 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3736 Src, getIntPtrConstant(ElementSize));
3738 TargetLowering::ArgListTy Args;
3739 TargetLowering::ArgListEntry Entry;
3741 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3742 Args.push_back(Entry);
3744 std::pair<SDOperand,SDOperand> Result =
3745 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
3746 DAG.getExternalSymbol("malloc", IntPtr),
3748 setValue(&I, Result.first); // Pointers always fit in registers
3749 DAG.setRoot(Result.second);
3752 void SelectionDAGLowering::visitFree(FreeInst &I) {
3753 TargetLowering::ArgListTy Args;
3754 TargetLowering::ArgListEntry Entry;
3755 Entry.Node = getValue(I.getOperand(0));
3756 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3757 Args.push_back(Entry);
3758 MVT::ValueType IntPtr = TLI.getPointerTy();
3759 std::pair<SDOperand,SDOperand> Result =
3760 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
3761 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3762 DAG.setRoot(Result.second);
3765 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
3766 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3767 // instructions are special in various ways, which require special support to
3768 // insert. The specified MachineInstr is created but not inserted into any
3769 // basic blocks, and the scheduler passes ownership of it to this method.
3770 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
3771 MachineBasicBlock *MBB) {
3772 cerr << "If a target marks an instruction with "
3773 << "'usesCustomDAGSchedInserter', it must implement "
3774 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
3779 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3780 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3781 getValue(I.getOperand(1)),
3782 DAG.getSrcValue(I.getOperand(1))));
3785 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3786 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3787 getValue(I.getOperand(0)),
3788 DAG.getSrcValue(I.getOperand(0)));
3790 DAG.setRoot(V.getValue(1));
3793 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3794 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3795 getValue(I.getOperand(1)),
3796 DAG.getSrcValue(I.getOperand(1))));
3799 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3800 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3801 getValue(I.getOperand(1)),
3802 getValue(I.getOperand(2)),
3803 DAG.getSrcValue(I.getOperand(1)),
3804 DAG.getSrcValue(I.getOperand(2))));
3807 /// TargetLowering::LowerArguments - This is the default LowerArguments
3808 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3809 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3810 /// integrated into SDISel.
3811 std::vector<SDOperand>
3812 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3813 const FunctionType *FTy = F.getFunctionType();
3814 const ParamAttrsList *Attrs = FTy->getParamAttrs();
3815 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3816 std::vector<SDOperand> Ops;
3817 Ops.push_back(DAG.getRoot());
3818 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3819 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3821 // Add one result value for each formal argument.
3822 std::vector<MVT::ValueType> RetVals;
3824 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3826 MVT::ValueType VT = getValueType(I->getType());
3827 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3828 unsigned OriginalAlignment =
3829 getTargetData()->getABITypeAlignment(I->getType());
3831 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3832 // that is zero extended!
3833 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt))
3834 Flags &= ~(ISD::ParamFlags::SExt);
3835 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt))
3836 Flags |= ISD::ParamFlags::SExt;
3837 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg))
3838 Flags |= ISD::ParamFlags::InReg;
3839 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet))
3840 Flags |= ISD::ParamFlags::StructReturn;
3841 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ByVal)) {
3842 Flags |= ISD::ParamFlags::ByVal;
3843 const PointerType *Ty = cast<PointerType>(I->getType());
3844 const StructType *STy = cast<StructType>(Ty->getElementType());
3845 unsigned StructAlign = Log2_32(getTargetData()->getABITypeAlignment(STy));
3846 unsigned StructSize = getTargetData()->getTypeSize(STy);
3847 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
3848 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs);
3850 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::Nest))
3851 Flags |= ISD::ParamFlags::Nest;
3852 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
3854 switch (getTypeAction(VT)) {
3855 default: assert(0 && "Unknown type action!");
3857 RetVals.push_back(VT);
3858 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3861 RetVals.push_back(getTypeToTransformTo(VT));
3862 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3865 // If this is an illegal type, it needs to be broken up to fit into
3867 MVT::ValueType RegisterVT = getRegisterType(VT);
3868 unsigned NumRegs = getNumRegisters(VT);
3869 for (unsigned i = 0; i != NumRegs; ++i) {
3870 RetVals.push_back(RegisterVT);
3871 // if it isn't first piece, alignment must be 1
3873 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3874 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3875 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3882 RetVals.push_back(MVT::Other);
3885 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3886 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3887 &Ops[0], Ops.size()).Val;
3888 unsigned NumArgRegs = Result->getNumValues() - 1;
3889 DAG.setRoot(SDOperand(Result, NumArgRegs));
3891 // Set up the return result vector.
3895 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3897 MVT::ValueType VT = getValueType(I->getType());
3899 switch (getTypeAction(VT)) {
3900 default: assert(0 && "Unknown type action!");
3902 Ops.push_back(SDOperand(Result, i++));
3905 SDOperand Op(Result, i++);
3906 if (MVT::isInteger(VT)) {
3907 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt))
3908 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
3909 DAG.getValueType(VT));
3910 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt))
3911 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
3912 DAG.getValueType(VT));
3913 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
3915 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3916 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
3922 MVT::ValueType PartVT = getRegisterType(VT);
3923 unsigned NumParts = getNumRegisters(VT);
3924 SmallVector<SDOperand, 4> Parts(NumParts);
3925 for (unsigned j = 0; j != NumParts; ++j)
3926 Parts[j] = SDOperand(Result, i++);
3927 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
3932 assert(i == NumArgRegs && "Argument register count mismatch!");
3937 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
3938 /// implementation, which just inserts an ISD::CALL node, which is later custom
3939 /// lowered by the target to something concrete. FIXME: When all targets are
3940 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
3941 std::pair<SDOperand, SDOperand>
3942 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
3943 bool RetTyIsSigned, bool isVarArg,
3944 unsigned CallingConv, bool isTailCall,
3946 ArgListTy &Args, SelectionDAG &DAG) {
3947 SmallVector<SDOperand, 32> Ops;
3948 Ops.push_back(Chain); // Op#0 - Chain
3949 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
3950 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
3951 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
3952 Ops.push_back(Callee);
3954 // Handle all of the outgoing arguments.
3955 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
3956 MVT::ValueType VT = getValueType(Args[i].Ty);
3957 SDOperand Op = Args[i].Node;
3958 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3959 unsigned OriginalAlignment =
3960 getTargetData()->getABITypeAlignment(Args[i].Ty);
3963 Flags |= ISD::ParamFlags::SExt;
3965 Flags |= ISD::ParamFlags::ZExt;
3966 if (Args[i].isInReg)
3967 Flags |= ISD::ParamFlags::InReg;
3969 Flags |= ISD::ParamFlags::StructReturn;
3971 Flags |= ISD::ParamFlags::Nest;
3972 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
3974 switch (getTypeAction(VT)) {
3975 default: assert(0 && "Unknown type action!");
3978 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3981 if (MVT::isInteger(VT)) {
3984 ExtOp = ISD::SIGN_EXTEND;
3985 else if (Args[i].isZExt)
3986 ExtOp = ISD::ZERO_EXTEND;
3988 ExtOp = ISD::ANY_EXTEND;
3989 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
3991 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3992 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
3995 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3998 MVT::ValueType PartVT = getRegisterType(VT);
3999 unsigned NumParts = getNumRegisters(VT);
4000 SmallVector<SDOperand, 4> Parts(NumParts);
4001 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
4002 for (unsigned i = 0; i != NumParts; ++i) {
4003 // if it isn't first piece, alignment must be 1
4004 unsigned MyFlags = Flags;
4006 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4007 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4009 Ops.push_back(Parts[i]);
4010 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
4017 // Figure out the result value types.
4018 MVT::ValueType VT = getValueType(RetTy);
4019 MVT::ValueType RegisterVT = getRegisterType(VT);
4020 unsigned NumRegs = getNumRegisters(VT);
4021 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4022 for (unsigned i = 0; i != NumRegs; ++i)
4023 RetTys[i] = RegisterVT;
4025 RetTys.push_back(MVT::Other); // Always has a chain.
4027 // Create the CALL node.
4028 SDOperand Res = DAG.getNode(ISD::CALL,
4029 DAG.getVTList(&RetTys[0], NumRegs + 1),
4030 &Ops[0], Ops.size());
4031 Chain = Res.getValue(NumRegs);
4033 // Gather up the call result into a single value.
4034 if (RetTy != Type::VoidTy) {
4035 ISD::NodeType AssertOp = ISD::AssertSext;
4037 AssertOp = ISD::AssertZext;
4038 SmallVector<SDOperand, 4> Results(NumRegs);
4039 for (unsigned i = 0; i != NumRegs; ++i)
4040 Results[i] = Res.getValue(i);
4041 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
4044 return std::make_pair(Res, Chain);
4047 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4048 assert(0 && "LowerOperation not implemented for this target!");
4053 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4054 SelectionDAG &DAG) {
4055 assert(0 && "CustomPromoteOperation not implemented for this target!");
4060 /// getMemsetValue - Vectorized representation of the memset value
4062 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4063 SelectionDAG &DAG) {
4064 MVT::ValueType CurVT = VT;
4065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4066 uint64_t Val = C->getValue() & 255;
4068 while (CurVT != MVT::i8) {
4069 Val = (Val << Shift) | Val;
4071 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4073 return DAG.getConstant(Val, VT);
4075 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4077 while (CurVT != MVT::i8) {
4079 DAG.getNode(ISD::OR, VT,
4080 DAG.getNode(ISD::SHL, VT, Value,
4081 DAG.getConstant(Shift, MVT::i8)), Value);
4083 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4090 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4091 /// used when a memcpy is turned into a memset when the source is a constant
4093 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4094 SelectionDAG &DAG, TargetLowering &TLI,
4095 std::string &Str, unsigned Offset) {
4097 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4098 if (TLI.isLittleEndian())
4099 Offset = Offset + MSB - 1;
4100 for (unsigned i = 0; i != MSB; ++i) {
4101 Val = (Val << 8) | (unsigned char)Str[Offset];
4102 Offset += TLI.isLittleEndian() ? -1 : 1;
4104 return DAG.getConstant(Val, VT);
4107 /// getMemBasePlusOffset - Returns base and offset node for the
4108 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4109 SelectionDAG &DAG, TargetLowering &TLI) {
4110 MVT::ValueType VT = Base.getValueType();
4111 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4114 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4115 /// to replace the memset / memcpy is below the threshold. It also returns the
4116 /// types of the sequence of memory ops to perform memset / memcpy.
4117 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4118 unsigned Limit, uint64_t Size,
4119 unsigned Align, TargetLowering &TLI) {
4122 if (TLI.allowsUnalignedMemoryAccesses()) {
4125 switch (Align & 7) {
4141 MVT::ValueType LVT = MVT::i64;
4142 while (!TLI.isTypeLegal(LVT))
4143 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4144 assert(MVT::isInteger(LVT));
4149 unsigned NumMemOps = 0;
4151 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4152 while (VTSize > Size) {
4153 VT = (MVT::ValueType)((unsigned)VT - 1);
4156 assert(MVT::isInteger(VT));
4158 if (++NumMemOps > Limit)
4160 MemOps.push_back(VT);
4167 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4168 SDOperand Op1 = getValue(I.getOperand(1));
4169 SDOperand Op2 = getValue(I.getOperand(2));
4170 SDOperand Op3 = getValue(I.getOperand(3));
4171 SDOperand Op4 = getValue(I.getOperand(4));
4172 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4173 if (Align == 0) Align = 1;
4175 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4176 std::vector<MVT::ValueType> MemOps;
4178 // Expand memset / memcpy to a series of load / store ops
4179 // if the size operand falls below a certain threshold.
4180 SmallVector<SDOperand, 8> OutChains;
4182 default: break; // Do nothing for now.
4184 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4185 Size->getValue(), Align, TLI)) {
4186 unsigned NumMemOps = MemOps.size();
4187 unsigned Offset = 0;
4188 for (unsigned i = 0; i < NumMemOps; i++) {
4189 MVT::ValueType VT = MemOps[i];
4190 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4191 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4192 SDOperand Store = DAG.getStore(getRoot(), Value,
4193 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4194 I.getOperand(1), Offset);
4195 OutChains.push_back(Store);
4202 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4203 Size->getValue(), Align, TLI)) {
4204 unsigned NumMemOps = MemOps.size();
4205 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4206 GlobalAddressSDNode *G = NULL;
4208 bool CopyFromStr = false;
4210 if (Op2.getOpcode() == ISD::GlobalAddress)
4211 G = cast<GlobalAddressSDNode>(Op2);
4212 else if (Op2.getOpcode() == ISD::ADD &&
4213 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4214 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4215 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4216 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4219 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4220 if (GV && GV->isConstant()) {
4221 Str = GV->getStringValue(false);
4229 for (unsigned i = 0; i < NumMemOps; i++) {
4230 MVT::ValueType VT = MemOps[i];
4231 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4232 SDOperand Value, Chain, Store;
4235 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4238 DAG.getStore(Chain, Value,
4239 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4240 I.getOperand(1), DstOff);
4242 Value = DAG.getLoad(VT, getRoot(),
4243 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4244 I.getOperand(2), SrcOff);
4245 Chain = Value.getValue(1);
4247 DAG.getStore(Chain, Value,
4248 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4249 I.getOperand(1), DstOff);
4251 OutChains.push_back(Store);
4260 if (!OutChains.empty()) {
4261 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4262 &OutChains[0], OutChains.size()));
4267 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
4270 //===----------------------------------------------------------------------===//
4271 // SelectionDAGISel code
4272 //===----------------------------------------------------------------------===//
4274 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4275 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
4278 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4279 AU.addRequired<AliasAnalysis>();
4280 AU.setPreservesAll();
4285 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4286 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4287 RegMap = MF.getSSARegMap();
4288 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4290 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4292 if (ExceptionHandling)
4293 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4294 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4295 // Mark landing pad.
4296 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4298 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4299 SelectBasicBlock(I, MF, FuncInfo);
4301 // Add function live-ins to entry block live-in set.
4302 BasicBlock *EntryBB = &Fn.getEntryBlock();
4303 BB = FuncInfo.MBBMap[EntryBB];
4304 if (!MF.livein_empty())
4305 for (MachineFunction::livein_iterator I = MF.livein_begin(),
4306 E = MF.livein_end(); I != E; ++I)
4307 BB->addLiveIn(I->first);
4310 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4311 "Not all catch info was assigned to a landing pad!");
4317 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4319 SDOperand Op = getValue(V);
4320 assert((Op.getOpcode() != ISD::CopyFromReg ||
4321 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4322 "Copy from a reg to the same reg!");
4324 MVT::ValueType SrcVT = Op.getValueType();
4325 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4326 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4327 SmallVector<SDOperand, 8> Regs(NumRegs);
4328 SmallVector<SDOperand, 8> Chains(NumRegs);
4330 // Copy the value by legal parts into sequential virtual registers.
4331 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4332 for (unsigned i = 0; i != NumRegs; ++i)
4333 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4334 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4337 void SelectionDAGISel::
4338 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4339 std::vector<SDOperand> &UnorderedChains) {
4340 // If this is the entry block, emit arguments.
4341 Function &F = *LLVMBB->getParent();
4342 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4343 SDOperand OldRoot = SDL.DAG.getRoot();
4344 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4347 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4349 if (!AI->use_empty()) {
4350 SDL.setValue(AI, Args[a]);
4352 // If this argument is live outside of the entry block, insert a copy from
4353 // whereever we got it to the vreg that other BB's will reference it as.
4354 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4355 if (VMI != FuncInfo.ValueMap.end()) {
4356 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4357 UnorderedChains.push_back(Copy);
4361 // Finally, if the target has anything special to do, allow it to do so.
4362 // FIXME: this should insert code into the DAG!
4363 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4366 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4367 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4368 assert(!FLI.MBBMap[SrcBB]->isLandingPad() &&
4369 "Copying catch info out of a landing pad!");
4370 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4371 if (isSelector(I)) {
4372 // Apply the catch info to DestBB.
4373 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4375 FLI.CatchInfoFound.insert(I);
4380 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4381 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4382 FunctionLoweringInfo &FuncInfo) {
4383 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
4385 std::vector<SDOperand> UnorderedChains;
4387 // Lower any arguments needed in this block if this is the entry block.
4388 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4389 LowerArguments(LLVMBB, SDL, UnorderedChains);
4391 BB = FuncInfo.MBBMap[LLVMBB];
4392 SDL.setCurrentBasicBlock(BB);
4394 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4396 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4397 // Add a label to mark the beginning of the landing pad. Deletion of the
4398 // landing pad can thus be detected via the MachineModuleInfo.
4399 unsigned LabelID = MMI->addLandingPad(BB);
4400 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4401 DAG.getConstant(LabelID, MVT::i32)));
4403 // Mark exception register as live in.
4404 unsigned Reg = TLI.getExceptionAddressRegister();
4405 if (Reg) BB->addLiveIn(Reg);
4407 // Mark exception selector register as live in.
4408 Reg = TLI.getExceptionSelectorRegister();
4409 if (Reg) BB->addLiveIn(Reg);
4411 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4412 // function and list of typeids logically belong to the invoke (or, if you
4413 // like, the basic block containing the invoke), and need to be associated
4414 // with it in the dwarf exception handling tables. Currently however the
4415 // information is provided by an intrinsic (eh.selector) that can be moved
4416 // to unexpected places by the optimizers: if the unwind edge is critical,
4417 // then breaking it can result in the intrinsics being in the successor of
4418 // the landing pad, not the landing pad itself. This results in exceptions
4419 // not being caught because no typeids are associated with the invoke.
4420 // This may not be the only way things can go wrong, but it is the only way
4421 // we try to work around for the moment.
4422 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4424 if (Br && Br->isUnconditional()) { // Critical edge?
4425 BasicBlock::iterator I, E;
4426 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4431 // No catch info found - try to extract some from the successor.
4432 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4436 // Lower all of the non-terminator instructions.
4437 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4441 // Ensure that all instructions which are used outside of their defining
4442 // blocks are available as virtual registers. Invoke is handled elsewhere.
4443 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4444 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4445 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4446 if (VMI != FuncInfo.ValueMap.end())
4447 UnorderedChains.push_back(
4448 SDL.CopyValueToVirtualRegister(I, VMI->second));
4451 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4452 // ensure constants are generated when needed. Remember the virtual registers
4453 // that need to be added to the Machine PHI nodes as input. We cannot just
4454 // directly add them, because expansion might result in multiple MBB's for one
4455 // BB. As such, the start of the BB might correspond to a different MBB than
4458 TerminatorInst *TI = LLVMBB->getTerminator();
4460 // Emit constants only once even if used by multiple PHI nodes.
4461 std::map<Constant*, unsigned> ConstantsOut;
4463 // Vector bool would be better, but vector<bool> is really slow.
4464 std::vector<unsigned char> SuccsHandled;
4465 if (TI->getNumSuccessors())
4466 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4468 // Check successor nodes' PHI nodes that expect a constant to be available
4470 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4471 BasicBlock *SuccBB = TI->getSuccessor(succ);
4472 if (!isa<PHINode>(SuccBB->begin())) continue;
4473 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4475 // If this terminator has multiple identical successors (common for
4476 // switches), only handle each succ once.
4477 unsigned SuccMBBNo = SuccMBB->getNumber();
4478 if (SuccsHandled[SuccMBBNo]) continue;
4479 SuccsHandled[SuccMBBNo] = true;
4481 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4484 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4485 // nodes and Machine PHI nodes, but the incoming operands have not been
4487 for (BasicBlock::iterator I = SuccBB->begin();
4488 (PN = dyn_cast<PHINode>(I)); ++I) {
4489 // Ignore dead phi's.
4490 if (PN->use_empty()) continue;
4493 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4495 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4496 unsigned &RegOut = ConstantsOut[C];
4498 RegOut = FuncInfo.CreateRegForValue(C);
4499 UnorderedChains.push_back(
4500 SDL.CopyValueToVirtualRegister(C, RegOut));
4504 Reg = FuncInfo.ValueMap[PHIOp];
4506 assert(isa<AllocaInst>(PHIOp) &&
4507 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4508 "Didn't codegen value into a register!??");
4509 Reg = FuncInfo.CreateRegForValue(PHIOp);
4510 UnorderedChains.push_back(
4511 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4515 // Remember that this register needs to added to the machine PHI node as
4516 // the input for this MBB.
4517 MVT::ValueType VT = TLI.getValueType(PN->getType());
4518 unsigned NumRegisters = TLI.getNumRegisters(VT);
4519 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4520 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4523 ConstantsOut.clear();
4525 // Turn all of the unordered chains into one factored node.
4526 if (!UnorderedChains.empty()) {
4527 SDOperand Root = SDL.getRoot();
4528 if (Root.getOpcode() != ISD::EntryToken) {
4529 unsigned i = 0, e = UnorderedChains.size();
4530 for (; i != e; ++i) {
4531 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4532 if (UnorderedChains[i].Val->getOperand(0) == Root)
4533 break; // Don't add the root if we already indirectly depend on it.
4537 UnorderedChains.push_back(Root);
4539 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4540 &UnorderedChains[0], UnorderedChains.size()));
4543 // Lower the terminator after the copies are emitted.
4544 SDL.visit(*LLVMBB->getTerminator());
4546 // Copy over any CaseBlock records that may now exist due to SwitchInst
4547 // lowering, as well as any jump table information.
4548 SwitchCases.clear();
4549 SwitchCases = SDL.SwitchCases;
4551 JTCases = SDL.JTCases;
4552 BitTestCases.clear();
4553 BitTestCases = SDL.BitTestCases;
4555 // Make sure the root of the DAG is up-to-date.
4556 DAG.setRoot(SDL.getRoot());
4559 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4560 // Get alias analysis for load/store combining.
4561 AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
4563 // Run the DAG combiner in pre-legalize mode.
4564 DAG.Combine(false, AA);
4566 DOUT << "Lowered selection DAG:\n";
4569 // Second step, hack on the DAG until it only uses operations and types that
4570 // the target supports.
4573 DOUT << "Legalized selection DAG:\n";
4576 // Run the DAG combiner in post-legalize mode.
4577 DAG.Combine(true, AA);
4579 if (ViewISelDAGs) DAG.viewGraph();
4581 // Third, instruction select all of the operations to machine code, adding the
4582 // code to the MachineBasicBlock.
4583 InstructionSelectBasicBlock(DAG);
4585 DOUT << "Selected machine code:\n";
4589 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4590 FunctionLoweringInfo &FuncInfo) {
4591 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4593 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4596 // First step, lower LLVM code to some DAG. This DAG may use operations and
4597 // types that are not supported by the target.
4598 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4600 // Second step, emit the lowered DAG as machine code.
4601 CodeGenAndEmitDAG(DAG);
4604 DOUT << "Total amount of phi nodes to update: "
4605 << PHINodesToUpdate.size() << "\n";
4606 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4607 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4608 << ", " << PHINodesToUpdate[i].second << ")\n";);
4610 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4611 // PHI nodes in successors.
4612 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4613 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4614 MachineInstr *PHI = PHINodesToUpdate[i].first;
4615 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4616 "This is not a machine PHI node that we are updating!");
4617 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4618 PHI->addMachineBasicBlockOperand(BB);
4623 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4624 // Lower header first, if it wasn't already lowered
4625 if (!BitTestCases[i].Emitted) {
4626 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4628 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo);
4629 // Set the current basic block to the mbb we wish to insert the code into
4630 BB = BitTestCases[i].Parent;
4631 HSDL.setCurrentBasicBlock(BB);
4633 HSDL.visitBitTestHeader(BitTestCases[i]);
4634 HSDAG.setRoot(HSDL.getRoot());
4635 CodeGenAndEmitDAG(HSDAG);
4638 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4639 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4641 SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo);
4642 // Set the current basic block to the mbb we wish to insert the code into
4643 BB = BitTestCases[i].Cases[j].ThisBB;
4644 BSDL.setCurrentBasicBlock(BB);
4647 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4648 BitTestCases[i].Reg,
4649 BitTestCases[i].Cases[j]);
4651 BSDL.visitBitTestCase(BitTestCases[i].Default,
4652 BitTestCases[i].Reg,
4653 BitTestCases[i].Cases[j]);
4656 BSDAG.setRoot(BSDL.getRoot());
4657 CodeGenAndEmitDAG(BSDAG);
4661 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4662 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4663 MachineBasicBlock *PHIBB = PHI->getParent();
4664 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4665 "This is not a machine PHI node that we are updating!");
4666 // This is "default" BB. We have two jumps to it. From "header" BB and
4667 // from last "case" BB.
4668 if (PHIBB == BitTestCases[i].Default) {
4669 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4670 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent);
4671 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4672 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB);
4674 // One of "cases" BB.
4675 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4676 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4677 if (cBB->succ_end() !=
4678 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4679 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4680 PHI->addMachineBasicBlockOperand(cBB);
4686 // If the JumpTable record is filled in, then we need to emit a jump table.
4687 // Updating the PHI nodes is tricky in this case, since we need to determine
4688 // whether the PHI is a successor of the range check MBB or the jump table MBB
4689 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4690 // Lower header first, if it wasn't already lowered
4691 if (!JTCases[i].first.Emitted) {
4692 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4694 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo);
4695 // Set the current basic block to the mbb we wish to insert the code into
4696 BB = JTCases[i].first.HeaderBB;
4697 HSDL.setCurrentBasicBlock(BB);
4699 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4700 HSDAG.setRoot(HSDL.getRoot());
4701 CodeGenAndEmitDAG(HSDAG);
4704 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4706 SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo);
4707 // Set the current basic block to the mbb we wish to insert the code into
4708 BB = JTCases[i].second.MBB;
4709 JSDL.setCurrentBasicBlock(BB);
4711 JSDL.visitJumpTable(JTCases[i].second);
4712 JSDAG.setRoot(JSDL.getRoot());
4713 CodeGenAndEmitDAG(JSDAG);
4716 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4717 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4718 MachineBasicBlock *PHIBB = PHI->getParent();
4719 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4720 "This is not a machine PHI node that we are updating!");
4721 // "default" BB. We can go there only from header BB.
4722 if (PHIBB == JTCases[i].second.Default) {
4723 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4724 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB);
4726 // JT BB. Just iterate over successors here
4727 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4728 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4729 PHI->addMachineBasicBlockOperand(BB);
4734 // If the switch block involved a branch to one of the actual successors, we
4735 // need to update PHI nodes in that block.
4736 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4737 MachineInstr *PHI = PHINodesToUpdate[i].first;
4738 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4739 "This is not a machine PHI node that we are updating!");
4740 if (BB->isSuccessor(PHI->getParent())) {
4741 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4742 PHI->addMachineBasicBlockOperand(BB);
4746 // If we generated any switch lowering information, build and codegen any
4747 // additional DAGs necessary.
4748 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4749 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4751 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4753 // Set the current basic block to the mbb we wish to insert the code into
4754 BB = SwitchCases[i].ThisBB;
4755 SDL.setCurrentBasicBlock(BB);
4758 SDL.visitSwitchCase(SwitchCases[i]);
4759 SDAG.setRoot(SDL.getRoot());
4760 CodeGenAndEmitDAG(SDAG);
4762 // Handle any PHI nodes in successors of this chunk, as if we were coming
4763 // from the original BB before switch expansion. Note that PHI nodes can
4764 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4765 // handle them the right number of times.
4766 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4767 for (MachineBasicBlock::iterator Phi = BB->begin();
4768 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4769 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4770 for (unsigned pn = 0; ; ++pn) {
4771 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4772 if (PHINodesToUpdate[pn].first == Phi) {
4773 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4774 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4780 // Don't process RHS if same block as LHS.
4781 if (BB == SwitchCases[i].FalseBB)
4782 SwitchCases[i].FalseBB = 0;
4784 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4785 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4786 SwitchCases[i].FalseBB = 0;
4788 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4793 //===----------------------------------------------------------------------===//
4794 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4795 /// target node in the graph.
4796 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4797 if (ViewSchedDAGs) DAG.viewGraph();
4799 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4803 RegisterScheduler::setDefault(Ctor);
4806 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4812 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4813 return new HazardRecognizer();
4816 //===----------------------------------------------------------------------===//
4817 // Helper functions used by the generated instruction selector.
4818 //===----------------------------------------------------------------------===//
4819 // Calls to these methods are generated by tblgen.
4821 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4822 /// the dag combiner simplified the 255, we still want to match. RHS is the
4823 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4824 /// specified in the .td file (e.g. 255).
4825 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4826 int64_t DesiredMaskS) const {
4827 uint64_t ActualMask = RHS->getValue();
4828 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4830 // If the actual mask exactly matches, success!
4831 if (ActualMask == DesiredMask)
4834 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4835 if (ActualMask & ~DesiredMask)
4838 // Otherwise, the DAG Combiner may have proven that the value coming in is
4839 // either already zero or is not demanded. Check for known zero input bits.
4840 uint64_t NeededMask = DesiredMask & ~ActualMask;
4841 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
4844 // TODO: check to see if missing bits are just not demanded.
4846 // Otherwise, this pattern doesn't match.
4850 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
4851 /// the dag combiner simplified the 255, we still want to match. RHS is the
4852 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
4853 /// specified in the .td file (e.g. 255).
4854 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
4855 int64_t DesiredMaskS) const {
4856 uint64_t ActualMask = RHS->getValue();
4857 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4859 // If the actual mask exactly matches, success!
4860 if (ActualMask == DesiredMask)
4863 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4864 if (ActualMask & ~DesiredMask)
4867 // Otherwise, the DAG Combiner may have proven that the value coming in is
4868 // either already zero or is not demanded. Check for known zero input bits.
4869 uint64_t NeededMask = DesiredMask & ~ActualMask;
4871 uint64_t KnownZero, KnownOne;
4872 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
4874 // If all the missing bits in the or are already known to be set, match!
4875 if ((NeededMask & KnownOne) == NeededMask)
4878 // TODO: check to see if missing bits are just not demanded.
4880 // Otherwise, this pattern doesn't match.
4885 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
4886 /// by tblgen. Others should not call it.
4887 void SelectionDAGISel::
4888 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
4889 std::vector<SDOperand> InOps;
4890 std::swap(InOps, Ops);
4892 Ops.push_back(InOps[0]); // input chain.
4893 Ops.push_back(InOps[1]); // input asm string.
4895 unsigned i = 2, e = InOps.size();
4896 if (InOps[e-1].getValueType() == MVT::Flag)
4897 --e; // Don't process a flag operand if it is here.
4900 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
4901 if ((Flags & 7) != 4 /*MEM*/) {
4902 // Just skip over this operand, copying the operands verbatim.
4903 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
4904 i += (Flags >> 3) + 1;
4906 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
4907 // Otherwise, this is a memory operand. Ask the target to select it.
4908 std::vector<SDOperand> SelOps;
4909 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
4910 cerr << "Could not match memory address. Inline asm failure!\n";
4914 // Add this to the output node.
4915 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4916 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
4918 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
4923 // Add the flag input back if present.
4924 if (e != InOps.size())
4925 Ops.push_back(InOps.back());
4928 char SelectionDAGISel::ID = 0;