1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SSARegMap.h"
37 #include "llvm/Target/MRegisterInfo.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetFrameInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
52 ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
55 ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
59 cl::desc("Pop up a window to show SUnit dags after they are processed"));
61 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
64 //===---------------------------------------------------------------------===//
66 /// RegisterScheduler class - Track the registration of instruction schedulers.
68 //===---------------------------------------------------------------------===//
69 MachinePassRegistry RegisterScheduler::Registry;
71 //===---------------------------------------------------------------------===//
73 /// ISHeuristic command line option for instruction schedulers.
75 //===---------------------------------------------------------------------===//
77 cl::opt<RegisterScheduler::FunctionPassCtor, false,
78 RegisterPassParser<RegisterScheduler> >
79 ISHeuristic("pre-RA-sched",
80 cl::init(&createDefaultScheduler),
81 cl::desc("Instruction schedulers available (before register allocation):"));
83 static RegisterScheduler
84 defaultListDAGScheduler("default", " Best scheduler for the target",
85 createDefaultScheduler);
88 namespace { struct AsmOperandInfo; }
91 /// RegsForValue - This struct represents the physical registers that a
92 /// particular value is assigned and the type information about the value.
93 /// This is needed because values can be promoted into larger registers and
94 /// expanded into multiple smaller registers than the value.
95 struct VISIBILITY_HIDDEN RegsForValue {
96 /// Regs - This list holds the register (for legal and promoted values)
97 /// or register set (for expanded values) that the value should be assigned
99 std::vector<unsigned> Regs;
101 /// RegVT - The value type of each register.
103 MVT::ValueType RegVT;
105 /// ValueVT - The value type of the LLVM value, which may be promoted from
106 /// RegVT or made from merging the two expanded parts.
107 MVT::ValueType ValueVT;
109 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
111 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
112 : RegVT(regvt), ValueVT(valuevt) {
115 RegsForValue(const std::vector<unsigned> ®s,
116 MVT::ValueType regvt, MVT::ValueType valuevt)
117 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
120 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
121 /// this value and returns the result as a ValueVT value. This uses
122 /// Chain/Flag as the input and updates them for the output Chain/Flag.
123 /// If the Flag pointer is NULL, no flag is used.
124 SDOperand getCopyFromRegs(SelectionDAG &DAG,
125 SDOperand &Chain, SDOperand *Flag) const;
127 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
128 /// specified value into the registers specified by this object. This uses
129 /// Chain/Flag as the input and updates them for the output Chain/Flag.
130 /// If the Flag pointer is NULL, no flag is used.
131 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
132 SDOperand &Chain, SDOperand *Flag) const;
134 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
135 /// operand list. This adds the code marker and includes the number of
136 /// values added into it.
137 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
138 std::vector<SDOperand> &Ops) const;
143 //===--------------------------------------------------------------------===//
144 /// createDefaultScheduler - This creates an instruction scheduler appropriate
146 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
148 MachineBasicBlock *BB) {
149 TargetLowering &TLI = IS->getTargetLowering();
151 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
152 return createTDListDAGScheduler(IS, DAG, BB);
154 assert(TLI.getSchedulingPreference() ==
155 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
156 return createBURRListDAGScheduler(IS, DAG, BB);
161 //===--------------------------------------------------------------------===//
162 /// FunctionLoweringInfo - This contains information that is global to a
163 /// function that is used when lowering a region of the function.
164 class FunctionLoweringInfo {
171 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
173 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
174 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
176 /// ValueMap - Since we emit code for the function a basic block at a time,
177 /// we must remember which virtual registers hold the values for
178 /// cross-basic-block values.
179 DenseMap<const Value*, unsigned> ValueMap;
181 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
182 /// the entry block. This allows the allocas to be efficiently referenced
183 /// anywhere in the function.
184 std::map<const AllocaInst*, int> StaticAllocaMap;
187 SmallSet<Instruction*, 8> CatchInfoLost;
188 SmallSet<Instruction*, 8> CatchInfoFound;
191 unsigned MakeReg(MVT::ValueType VT) {
192 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
195 /// isExportedInst - Return true if the specified value is an instruction
196 /// exported from its block.
197 bool isExportedInst(const Value *V) {
198 return ValueMap.count(V);
201 unsigned CreateRegForValue(const Value *V);
203 unsigned InitializeRegForValue(const Value *V) {
204 unsigned &R = ValueMap[V];
205 assert(R == 0 && "Already initialized this value register!");
206 return R = CreateRegForValue(V);
211 /// isSelector - Return true if this instruction is a call to the
212 /// eh.selector intrinsic.
213 static bool isSelector(Instruction *I) {
214 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
215 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
216 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
220 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
221 /// PHI nodes or outside of the basic block that defines it, or used by a
222 /// switch instruction, which may expand to multiple basic blocks.
223 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
224 if (isa<PHINode>(I)) return true;
225 BasicBlock *BB = I->getParent();
226 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
227 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
228 // FIXME: Remove switchinst special case.
229 isa<SwitchInst>(*UI))
234 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
235 /// entry block, return true. This includes arguments used by switches, since
236 /// the switch may expand into multiple basic blocks.
237 static bool isOnlyUsedInEntryBlock(Argument *A) {
238 BasicBlock *Entry = A->getParent()->begin();
239 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
240 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
241 return false; // Use not in entry block.
245 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
246 Function &fn, MachineFunction &mf)
247 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
249 // Create a vreg for each argument register that is not dead and is used
250 // outside of the entry block for the function.
251 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
253 if (!isOnlyUsedInEntryBlock(AI))
254 InitializeRegForValue(AI);
256 // Initialize the mapping of values to registers. This is only set up for
257 // instruction values that are used outside of the block that defines
259 Function::iterator BB = Fn.begin(), EB = Fn.end();
260 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
261 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
262 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
263 const Type *Ty = AI->getAllocatedType();
264 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
266 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
269 TySize *= CUI->getZExtValue(); // Get total allocated size.
270 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
271 StaticAllocaMap[AI] =
272 MF.getFrameInfo()->CreateStackObject(TySize, Align);
275 for (; BB != EB; ++BB)
276 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
277 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
278 if (!isa<AllocaInst>(I) ||
279 !StaticAllocaMap.count(cast<AllocaInst>(I)))
280 InitializeRegForValue(I);
282 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
283 // also creates the initial PHI MachineInstrs, though none of the input
284 // operands are populated.
285 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
286 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
288 MF.getBasicBlockList().push_back(MBB);
290 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
293 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
294 if (PN->use_empty()) continue;
296 MVT::ValueType VT = TLI.getValueType(PN->getType());
297 unsigned NumRegisters = TLI.getNumRegisters(VT);
298 unsigned PHIReg = ValueMap[PN];
299 assert(PHIReg && "PHI node does not have an assigned virtual register!");
300 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
301 for (unsigned i = 0; i != NumRegisters; ++i)
302 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
307 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
308 /// the correctly promoted or expanded types. Assign these registers
309 /// consecutive vreg numbers and return the first assigned number.
310 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
311 MVT::ValueType VT = TLI.getValueType(V->getType());
313 unsigned NumRegisters = TLI.getNumRegisters(VT);
314 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
316 unsigned R = MakeReg(RegisterVT);
317 for (unsigned i = 1; i != NumRegisters; ++i)
323 //===----------------------------------------------------------------------===//
324 /// SelectionDAGLowering - This is the common target-independent lowering
325 /// implementation that is parameterized by a TargetLowering object.
326 /// Also, targets can overload any lowering method.
329 class SelectionDAGLowering {
330 MachineBasicBlock *CurMBB;
332 DenseMap<const Value*, SDOperand> NodeMap;
334 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
335 /// them up and then emit token factor nodes when possible. This allows us to
336 /// get simple disambiguation between loads without worrying about alias
338 std::vector<SDOperand> PendingLoads;
340 /// Case - A struct to record the Value for a switch case, and the
341 /// case's target basic block.
345 MachineBasicBlock* BB;
347 Case() : Low(0), High(0), BB(0) { }
348 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
349 Low(low), High(high), BB(bb) { }
350 uint64_t size() const {
351 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
352 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
353 return (rHigh - rLow + 1ULL);
359 MachineBasicBlock* BB;
362 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
363 Mask(mask), BB(bb), Bits(bits) { }
366 typedef std::vector<Case> CaseVector;
367 typedef std::vector<CaseBits> CaseBitsVector;
368 typedef CaseVector::iterator CaseItr;
369 typedef std::pair<CaseItr, CaseItr> CaseRange;
371 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
372 /// of conditional branches.
374 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
375 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
377 /// CaseBB - The MBB in which to emit the compare and branch
378 MachineBasicBlock *CaseBB;
379 /// LT, GE - If nonzero, we know the current case value must be less-than or
380 /// greater-than-or-equal-to these Constants.
383 /// Range - A pair of iterators representing the range of case values to be
384 /// processed at this point in the binary search tree.
388 typedef std::vector<CaseRec> CaseRecVector;
390 /// The comparison function for sorting the switch case values in the vector.
391 /// WARNING: Case ranges should be disjoint!
393 bool operator () (const Case& C1, const Case& C2) {
394 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
395 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
396 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
397 return CI1->getValue().slt(CI2->getValue());
402 bool operator () (const CaseBits& C1, const CaseBits& C2) {
403 return C1.Bits > C2.Bits;
407 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
410 // TLI - This is information that describes the available target features we
411 // need for lowering. This indicates when operations are unavailable,
412 // implemented with a libcall, etc.
415 const TargetData *TD;
418 /// SwitchCases - Vector of CaseBlock structures used to communicate
419 /// SwitchInst code generation information.
420 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
421 /// JTCases - Vector of JumpTable structures used to communicate
422 /// SwitchInst code generation information.
423 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
424 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
426 /// FuncInfo - Information about the function as a whole.
428 FunctionLoweringInfo &FuncInfo;
430 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
432 FunctionLoweringInfo &funcinfo)
433 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
437 /// getRoot - Return the current virtual root of the Selection DAG.
439 SDOperand getRoot() {
440 if (PendingLoads.empty())
441 return DAG.getRoot();
443 if (PendingLoads.size() == 1) {
444 SDOperand Root = PendingLoads[0];
446 PendingLoads.clear();
450 // Otherwise, we have to make a token factor node.
451 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
452 &PendingLoads[0], PendingLoads.size());
453 PendingLoads.clear();
458 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
460 void visit(Instruction &I) { visit(I.getOpcode(), I); }
462 void visit(unsigned Opcode, User &I) {
463 // Note: this doesn't use InstVisitor, because it has to work with
464 // ConstantExpr's in addition to instructions.
466 default: assert(0 && "Unknown instruction type encountered!");
468 // Build the switch statement using the Instruction.def file.
469 #define HANDLE_INST(NUM, OPCODE, CLASS) \
470 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
471 #include "llvm/Instruction.def"
475 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
477 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
478 const Value *SV, SDOperand Root,
479 bool isVolatile, unsigned Alignment);
481 SDOperand getIntPtrConstant(uint64_t Val) {
482 return DAG.getConstant(Val, TLI.getPointerTy());
485 SDOperand getValue(const Value *V);
487 void setValue(const Value *V, SDOperand NewN) {
488 SDOperand &N = NodeMap[V];
489 assert(N.Val == 0 && "Already set a value for this node!");
493 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
494 std::set<unsigned> &OutputRegs,
495 std::set<unsigned> &InputRegs);
497 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
498 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
500 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
501 void ExportFromCurrentBlock(Value *V);
502 void LowerCallTo(Instruction &I, const Type *CalledValueTy,
503 const ParamAttrsList *PAL, unsigned CallingConv,
504 bool IsTailCall, SDOperand Callee, unsigned OpIdx,
505 MachineBasicBlock *LandingPad = NULL);
507 // Terminator instructions.
508 void visitRet(ReturnInst &I);
509 void visitBr(BranchInst &I);
510 void visitSwitch(SwitchInst &I);
511 void visitUnreachable(UnreachableInst &I) { /* noop */ }
513 // Helpers for visitSwitch
514 bool handleSmallSwitchRange(CaseRec& CR,
515 CaseRecVector& WorkList,
517 MachineBasicBlock* Default);
518 bool handleJTSwitchCase(CaseRec& CR,
519 CaseRecVector& WorkList,
521 MachineBasicBlock* Default);
522 bool handleBTSplitSwitchCase(CaseRec& CR,
523 CaseRecVector& WorkList,
525 MachineBasicBlock* Default);
526 bool handleBitTestsSwitchCase(CaseRec& CR,
527 CaseRecVector& WorkList,
529 MachineBasicBlock* Default);
530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
532 void visitBitTestCase(MachineBasicBlock* NextMBB,
534 SelectionDAGISel::BitTestCase &B);
535 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
537 SelectionDAGISel::JumpTableHeader &JTH);
539 // These all get lowered before this pass.
540 void visitInvoke(InvokeInst &I);
541 void visitUnwind(UnwindInst &I);
543 void visitBinary(User &I, unsigned OpCode);
544 void visitShift(User &I, unsigned Opcode);
545 void visitAdd(User &I) {
546 if (I.getType()->isFPOrFPVector())
547 visitBinary(I, ISD::FADD);
549 visitBinary(I, ISD::ADD);
551 void visitSub(User &I);
552 void visitMul(User &I) {
553 if (I.getType()->isFPOrFPVector())
554 visitBinary(I, ISD::FMUL);
556 visitBinary(I, ISD::MUL);
558 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
564 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
565 void visitOr (User &I) { visitBinary(I, ISD::OR); }
566 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
567 void visitShl (User &I) { visitShift(I, ISD::SHL); }
568 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
569 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
570 void visitICmp(User &I);
571 void visitFCmp(User &I);
572 // Visit the conversion instructions
573 void visitTrunc(User &I);
574 void visitZExt(User &I);
575 void visitSExt(User &I);
576 void visitFPTrunc(User &I);
577 void visitFPExt(User &I);
578 void visitFPToUI(User &I);
579 void visitFPToSI(User &I);
580 void visitUIToFP(User &I);
581 void visitSIToFP(User &I);
582 void visitPtrToInt(User &I);
583 void visitIntToPtr(User &I);
584 void visitBitCast(User &I);
586 void visitExtractElement(User &I);
587 void visitInsertElement(User &I);
588 void visitShuffleVector(User &I);
590 void visitGetElementPtr(User &I);
591 void visitSelect(User &I);
593 void visitMalloc(MallocInst &I);
594 void visitFree(FreeInst &I);
595 void visitAlloca(AllocaInst &I);
596 void visitLoad(LoadInst &I);
597 void visitStore(StoreInst &I);
598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
599 void visitCall(CallInst &I);
600 void visitInlineAsm(CallSite CS);
601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
604 void visitVAStart(CallInst &I);
605 void visitVAArg(VAArgInst &I);
606 void visitVAEnd(CallInst &I);
607 void visitVACopy(CallInst &I);
609 void visitMemIntrinsic(CallInst &I, unsigned Op);
611 void visitUserOp1(Instruction &I) {
612 assert(0 && "UserOp1 should not exist at instruction selection time!");
615 void visitUserOp2(Instruction &I) {
616 assert(0 && "UserOp2 should not exist at instruction selection time!");
620 } // end namespace llvm
623 /// getCopyFromParts - Create a value that contains the
624 /// specified legal parts combined into the value they represent.
625 static SDOperand getCopyFromParts(SelectionDAG &DAG,
626 const SDOperand *Parts,
628 MVT::ValueType PartVT,
629 MVT::ValueType ValueVT,
630 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
631 if (!MVT::isVector(ValueVT) || NumParts == 1) {
632 SDOperand Val = Parts[0];
634 // If the value was expanded, copy from the top part.
636 assert(NumParts == 2 &&
637 "Cannot expand to more than 2 elts yet!");
638 SDOperand Hi = Parts[1];
639 if (!DAG.getTargetLoweringInfo().isLittleEndian())
641 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
644 // Otherwise, if the value was promoted or extended, truncate it to the
646 if (PartVT == ValueVT)
649 if (MVT::isVector(PartVT)) {
650 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
651 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
654 if (MVT::isVector(ValueVT)) {
655 assert(NumParts == 1 &&
656 MVT::getVectorElementType(ValueVT) == PartVT &&
657 MVT::getVectorNumElements(ValueVT) == 1 &&
658 "Only trivial scalar-to-vector conversions should get here!");
659 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
662 if (MVT::isInteger(PartVT) &&
663 MVT::isInteger(ValueVT)) {
664 if (ValueVT < PartVT) {
665 // For a truncate, see if we have any information to
666 // indicate whether the truncated bits will always be
667 // zero or sign-extension.
668 if (AssertOp != ISD::DELETED_NODE)
669 Val = DAG.getNode(AssertOp, PartVT, Val,
670 DAG.getValueType(ValueVT));
671 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
673 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
677 if (MVT::isFloatingPoint(PartVT) &&
678 MVT::isFloatingPoint(ValueVT))
679 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
681 if (MVT::getSizeInBits(PartVT) ==
682 MVT::getSizeInBits(ValueVT))
683 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
685 assert(0 && "Unknown mismatch!");
688 // Handle a multi-element vector.
689 MVT::ValueType IntermediateVT, RegisterVT;
690 unsigned NumIntermediates;
692 DAG.getTargetLoweringInfo()
693 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
696 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
697 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
698 assert(RegisterVT == Parts[0].getValueType() &&
699 "Part type doesn't match part!");
701 // Assemble the parts into intermediate operands.
702 SmallVector<SDOperand, 8> Ops(NumIntermediates);
703 if (NumIntermediates == NumParts) {
704 // If the register was not expanded, truncate or copy the value,
706 for (unsigned i = 0; i != NumParts; ++i)
707 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
708 PartVT, IntermediateVT);
709 } else if (NumParts > 0) {
710 // If the intermediate type was expanded, build the intermediate operands
712 assert(NumParts % NumIntermediates == 0 &&
713 "Must expand into a divisible number of parts!");
714 unsigned Factor = NumParts / NumIntermediates;
715 for (unsigned i = 0; i != NumIntermediates; ++i)
716 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
717 PartVT, IntermediateVT);
720 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
722 return DAG.getNode(MVT::isVector(IntermediateVT) ?
723 ISD::CONCAT_VECTORS :
725 ValueVT, &Ops[0], NumIntermediates);
728 /// getCopyToParts - Create a series of nodes that contain the
729 /// specified value split into legal parts.
730 static void getCopyToParts(SelectionDAG &DAG,
734 MVT::ValueType PartVT) {
735 TargetLowering &TLI = DAG.getTargetLoweringInfo();
736 MVT::ValueType PtrVT = TLI.getPointerTy();
737 MVT::ValueType ValueVT = Val.getValueType();
739 if (!MVT::isVector(ValueVT) || NumParts == 1) {
740 // If the value was expanded, copy from the parts.
742 for (unsigned i = 0; i != NumParts; ++i)
743 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
744 DAG.getConstant(i, PtrVT));
745 if (!DAG.getTargetLoweringInfo().isLittleEndian())
746 std::reverse(Parts, Parts + NumParts);
750 // If there is a single part and the types differ, this must be
752 if (PartVT != ValueVT) {
753 if (MVT::isVector(PartVT)) {
754 assert(MVT::isVector(ValueVT) &&
755 "Not a vector-vector cast?");
756 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
757 } else if (MVT::isVector(ValueVT)) {
758 assert(NumParts == 1 &&
759 MVT::getVectorElementType(ValueVT) == PartVT &&
760 MVT::getVectorNumElements(ValueVT) == 1 &&
761 "Only trivial vector-to-scalar conversions should get here!");
762 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
763 DAG.getConstant(0, PtrVT));
764 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
765 if (PartVT < ValueVT)
766 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
768 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
769 } else if (MVT::isFloatingPoint(PartVT) &&
770 MVT::isFloatingPoint(ValueVT)) {
771 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
772 } else if (MVT::getSizeInBits(PartVT) ==
773 MVT::getSizeInBits(ValueVT)) {
774 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
776 assert(0 && "Unknown mismatch!");
783 // Handle a multi-element vector.
784 MVT::ValueType IntermediateVT, RegisterVT;
785 unsigned NumIntermediates;
787 DAG.getTargetLoweringInfo()
788 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
790 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
792 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
793 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
795 // Split the vector into intermediate operands.
796 SmallVector<SDOperand, 8> Ops(NumIntermediates);
797 for (unsigned i = 0; i != NumIntermediates; ++i)
798 if (MVT::isVector(IntermediateVT))
799 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
801 DAG.getConstant(i * (NumElements / NumIntermediates),
804 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
806 DAG.getConstant(i, PtrVT));
808 // Split the intermediate operands into legal parts.
809 if (NumParts == NumIntermediates) {
810 // If the register was not expanded, promote or copy the value,
812 for (unsigned i = 0; i != NumParts; ++i)
813 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
814 } else if (NumParts > 0) {
815 // If the intermediate type was expanded, split each the value into
817 assert(NumParts % NumIntermediates == 0 &&
818 "Must expand into a divisible number of parts!");
819 unsigned Factor = NumParts / NumIntermediates;
820 for (unsigned i = 0; i != NumIntermediates; ++i)
821 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
826 SDOperand SelectionDAGLowering::getValue(const Value *V) {
827 SDOperand &N = NodeMap[V];
830 const Type *VTy = V->getType();
831 MVT::ValueType VT = TLI.getValueType(VTy);
832 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
833 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
834 visit(CE->getOpcode(), *CE);
835 SDOperand N1 = NodeMap[V];
836 assert(N1.Val && "visit didn't populate the ValueMap!");
838 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
839 return N = DAG.getGlobalAddress(GV, VT);
840 } else if (isa<ConstantPointerNull>(C)) {
841 return N = DAG.getConstant(0, TLI.getPointerTy());
842 } else if (isa<UndefValue>(C)) {
843 if (!isa<VectorType>(VTy))
844 return N = DAG.getNode(ISD::UNDEF, VT);
846 // Create a BUILD_VECTOR of undef nodes.
847 const VectorType *PTy = cast<VectorType>(VTy);
848 unsigned NumElements = PTy->getNumElements();
849 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
851 SmallVector<SDOperand, 8> Ops;
852 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
854 // Create a VConstant node with generic Vector type.
855 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
856 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
857 &Ops[0], Ops.size());
858 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
859 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
860 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
861 unsigned NumElements = PTy->getNumElements();
862 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
864 // Now that we know the number and type of the elements, push a
865 // Constant or ConstantFP node onto the ops list for each element of
866 // the vector constant.
867 SmallVector<SDOperand, 8> Ops;
868 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
869 for (unsigned i = 0; i != NumElements; ++i)
870 Ops.push_back(getValue(CP->getOperand(i)));
872 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
874 if (MVT::isFloatingPoint(PVT))
875 Op = DAG.getConstantFP(0, PVT);
877 Op = DAG.getConstant(0, PVT);
878 Ops.assign(NumElements, Op);
881 // Create a BUILD_VECTOR node.
882 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
883 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
886 // Canonicalize all constant ints to be unsigned.
887 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
891 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
892 std::map<const AllocaInst*, int>::iterator SI =
893 FuncInfo.StaticAllocaMap.find(AI);
894 if (SI != FuncInfo.StaticAllocaMap.end())
895 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
898 unsigned InReg = FuncInfo.ValueMap[V];
899 assert(InReg && "Value not in map!");
901 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
902 unsigned NumRegs = TLI.getNumRegisters(VT);
904 std::vector<unsigned> Regs(NumRegs);
905 for (unsigned i = 0; i != NumRegs; ++i)
908 RegsForValue RFV(Regs, RegisterVT, VT);
909 SDOperand Chain = DAG.getEntryNode();
911 return RFV.getCopyFromRegs(DAG, Chain, NULL);
915 void SelectionDAGLowering::visitRet(ReturnInst &I) {
916 if (I.getNumOperands() == 0) {
917 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
920 SmallVector<SDOperand, 8> NewValues;
921 NewValues.push_back(getRoot());
922 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
923 SDOperand RetOp = getValue(I.getOperand(i));
925 // If this is an integer return value, we need to promote it ourselves to
926 // the full width of a register, since getCopyToParts and Legalize will use
927 // ANY_EXTEND rather than sign/zero.
928 // FIXME: C calling convention requires the return type to be promoted to
929 // at least 32-bit. But this is not necessary for non-C calling conventions.
930 if (MVT::isInteger(RetOp.getValueType()) &&
931 RetOp.getValueType() < MVT::i64) {
932 MVT::ValueType TmpVT;
933 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
934 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
937 const Function *F = I.getParent()->getParent();
938 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
939 if (F->paramHasAttr(0, ParamAttr::SExt))
940 ExtendKind = ISD::SIGN_EXTEND;
941 if (F->paramHasAttr(0, ParamAttr::ZExt))
942 ExtendKind = ISD::ZERO_EXTEND;
943 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
944 NewValues.push_back(RetOp);
945 NewValues.push_back(DAG.getConstant(false, MVT::i32));
947 MVT::ValueType VT = RetOp.getValueType();
948 unsigned NumParts = TLI.getNumRegisters(VT);
949 MVT::ValueType PartVT = TLI.getRegisterType(VT);
950 SmallVector<SDOperand, 4> Parts(NumParts);
951 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
952 for (unsigned i = 0; i < NumParts; ++i) {
953 NewValues.push_back(Parts[i]);
954 NewValues.push_back(DAG.getConstant(false, MVT::i32));
958 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
959 &NewValues[0], NewValues.size()));
962 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
963 /// the current basic block, add it to ValueMap now so that we'll get a
965 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
966 // No need to export constants.
967 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
970 if (FuncInfo.isExportedInst(V)) return;
972 unsigned Reg = FuncInfo.InitializeRegForValue(V);
973 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
976 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
977 const BasicBlock *FromBB) {
978 // The operands of the setcc have to be in this block. We don't know
979 // how to export them from some other block.
980 if (Instruction *VI = dyn_cast<Instruction>(V)) {
981 // Can export from current BB.
982 if (VI->getParent() == FromBB)
985 // Is already exported, noop.
986 return FuncInfo.isExportedInst(V);
989 // If this is an argument, we can export it if the BB is the entry block or
990 // if it is already exported.
991 if (isa<Argument>(V)) {
992 if (FromBB == &FromBB->getParent()->getEntryBlock())
995 // Otherwise, can only export this if it is already exported.
996 return FuncInfo.isExportedInst(V);
999 // Otherwise, constants can always be exported.
1003 static bool InBlock(const Value *V, const BasicBlock *BB) {
1004 if (const Instruction *I = dyn_cast<Instruction>(V))
1005 return I->getParent() == BB;
1009 /// FindMergedConditions - If Cond is an expression like
1010 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1011 MachineBasicBlock *TBB,
1012 MachineBasicBlock *FBB,
1013 MachineBasicBlock *CurBB,
1015 // If this node is not part of the or/and tree, emit it as a branch.
1016 Instruction *BOp = dyn_cast<Instruction>(Cond);
1018 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1019 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1020 BOp->getParent() != CurBB->getBasicBlock() ||
1021 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1022 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1023 const BasicBlock *BB = CurBB->getBasicBlock();
1025 // If the leaf of the tree is a comparison, merge the condition into
1027 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1028 // The operands of the cmp have to be in this block. We don't know
1029 // how to export them from some other block. If this is the first block
1030 // of the sequence, no exporting is needed.
1032 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1033 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1034 BOp = cast<Instruction>(Cond);
1035 ISD::CondCode Condition;
1036 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1037 switch (IC->getPredicate()) {
1038 default: assert(0 && "Unknown icmp predicate opcode!");
1039 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1040 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1041 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1042 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1043 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1044 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1045 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1046 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1047 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1048 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1050 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1051 ISD::CondCode FPC, FOC;
1052 switch (FC->getPredicate()) {
1053 default: assert(0 && "Unknown fcmp predicate opcode!");
1054 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1055 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1056 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1057 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1058 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1059 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1060 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1061 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1062 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1063 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1064 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1065 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1066 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1067 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1068 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1069 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1071 if (FiniteOnlyFPMath())
1076 Condition = ISD::SETEQ; // silence warning.
1077 assert(0 && "Unknown compare instruction");
1080 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1081 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1082 SwitchCases.push_back(CB);
1086 // Create a CaseBlock record representing this branch.
1087 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1088 NULL, TBB, FBB, CurBB);
1089 SwitchCases.push_back(CB);
1094 // Create TmpBB after CurBB.
1095 MachineFunction::iterator BBI = CurBB;
1096 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1097 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1099 if (Opc == Instruction::Or) {
1100 // Codegen X | Y as:
1108 // Emit the LHS condition.
1109 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1111 // Emit the RHS condition into TmpBB.
1112 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1114 assert(Opc == Instruction::And && "Unknown merge op!");
1115 // Codegen X & Y as:
1122 // This requires creation of TmpBB after CurBB.
1124 // Emit the LHS condition.
1125 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1127 // Emit the RHS condition into TmpBB.
1128 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1132 /// If the set of cases should be emitted as a series of branches, return true.
1133 /// If we should emit this as a bunch of and/or'd together conditions, return
1136 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1137 if (Cases.size() != 2) return true;
1139 // If this is two comparisons of the same values or'd or and'd together, they
1140 // will get folded into a single comparison, so don't emit two blocks.
1141 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1142 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1143 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1144 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1151 void SelectionDAGLowering::visitBr(BranchInst &I) {
1152 // Update machine-CFG edges.
1153 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1155 // Figure out which block is immediately after the current one.
1156 MachineBasicBlock *NextBlock = 0;
1157 MachineFunction::iterator BBI = CurMBB;
1158 if (++BBI != CurMBB->getParent()->end())
1161 if (I.isUnconditional()) {
1162 // If this is not a fall-through branch, emit the branch.
1163 if (Succ0MBB != NextBlock)
1164 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1165 DAG.getBasicBlock(Succ0MBB)));
1167 // Update machine-CFG edges.
1168 CurMBB->addSuccessor(Succ0MBB);
1173 // If this condition is one of the special cases we handle, do special stuff
1175 Value *CondVal = I.getCondition();
1176 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1178 // If this is a series of conditions that are or'd or and'd together, emit
1179 // this as a sequence of branches instead of setcc's with and/or operations.
1180 // For example, instead of something like:
1193 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1194 if (BOp->hasOneUse() &&
1195 (BOp->getOpcode() == Instruction::And ||
1196 BOp->getOpcode() == Instruction::Or)) {
1197 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1198 // If the compares in later blocks need to use values not currently
1199 // exported from this block, export them now. This block should always
1200 // be the first entry.
1201 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1203 // Allow some cases to be rejected.
1204 if (ShouldEmitAsBranches(SwitchCases)) {
1205 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1206 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1207 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1210 // Emit the branch for this block.
1211 visitSwitchCase(SwitchCases[0]);
1212 SwitchCases.erase(SwitchCases.begin());
1216 // Okay, we decided not to do this, remove any inserted MBB's and clear
1218 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1219 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1221 SwitchCases.clear();
1225 // Create a CaseBlock record representing this branch.
1226 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1227 NULL, Succ0MBB, Succ1MBB, CurMBB);
1228 // Use visitSwitchCase to actually insert the fast branch sequence for this
1230 visitSwitchCase(CB);
1233 /// visitSwitchCase - Emits the necessary code to represent a single node in
1234 /// the binary search tree resulting from lowering a switch instruction.
1235 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1237 SDOperand CondLHS = getValue(CB.CmpLHS);
1239 // Build the setcc now.
1240 if (CB.CmpMHS == NULL) {
1241 // Fold "(X == true)" to X and "(X == false)" to !X to
1242 // handle common cases produced by branch lowering.
1243 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1245 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1246 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1247 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1249 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1251 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1253 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1254 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1256 SDOperand CmpOp = getValue(CB.CmpMHS);
1257 MVT::ValueType VT = CmpOp.getValueType();
1259 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1260 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1262 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1263 Cond = DAG.getSetCC(MVT::i1, SUB,
1264 DAG.getConstant(High-Low, VT), ISD::SETULE);
1269 // Set NextBlock to be the MBB immediately after the current one, if any.
1270 // This is used to avoid emitting unnecessary branches to the next block.
1271 MachineBasicBlock *NextBlock = 0;
1272 MachineFunction::iterator BBI = CurMBB;
1273 if (++BBI != CurMBB->getParent()->end())
1276 // If the lhs block is the next block, invert the condition so that we can
1277 // fall through to the lhs instead of the rhs block.
1278 if (CB.TrueBB == NextBlock) {
1279 std::swap(CB.TrueBB, CB.FalseBB);
1280 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1281 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1283 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1284 DAG.getBasicBlock(CB.TrueBB));
1285 if (CB.FalseBB == NextBlock)
1286 DAG.setRoot(BrCond);
1288 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1289 DAG.getBasicBlock(CB.FalseBB)));
1290 // Update successor info
1291 CurMBB->addSuccessor(CB.TrueBB);
1292 CurMBB->addSuccessor(CB.FalseBB);
1295 /// visitJumpTable - Emit JumpTable node in the current MBB
1296 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1297 // Emit the code for the jump table
1298 assert(JT.Reg != -1U && "Should lower JT Header first!");
1299 MVT::ValueType PTy = TLI.getPointerTy();
1300 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1301 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1302 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1307 /// visitJumpTableHeader - This function emits necessary code to produce index
1308 /// in the JumpTable from switch case.
1309 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1310 SelectionDAGISel::JumpTableHeader &JTH) {
1311 // Subtract the lowest switch case value from the value being switched on
1312 // and conditional branch to default mbb if the result is greater than the
1313 // difference between smallest and largest cases.
1314 SDOperand SwitchOp = getValue(JTH.SValue);
1315 MVT::ValueType VT = SwitchOp.getValueType();
1316 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1317 DAG.getConstant(JTH.First, VT));
1319 // The SDNode we just created, which holds the value being switched on
1320 // minus the the smallest case value, needs to be copied to a virtual
1321 // register so it can be used as an index into the jump table in a
1322 // subsequent basic block. This value may be smaller or larger than the
1323 // target's pointer type, and therefore require extension or truncating.
1324 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1325 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1327 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1329 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1330 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1331 JT.Reg = JumpTableReg;
1333 // Emit the range check for the jump table, and branch to the default
1334 // block for the switch statement if the value being switched on exceeds
1335 // the largest case in the switch.
1336 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1337 DAG.getConstant(JTH.Last-JTH.First,VT),
1340 // Set NextBlock to be the MBB immediately after the current one, if any.
1341 // This is used to avoid emitting unnecessary branches to the next block.
1342 MachineBasicBlock *NextBlock = 0;
1343 MachineFunction::iterator BBI = CurMBB;
1344 if (++BBI != CurMBB->getParent()->end())
1347 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1348 DAG.getBasicBlock(JT.Default));
1350 if (JT.MBB == NextBlock)
1351 DAG.setRoot(BrCond);
1353 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1354 DAG.getBasicBlock(JT.MBB)));
1359 /// visitBitTestHeader - This function emits necessary code to produce value
1360 /// suitable for "bit tests"
1361 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1362 // Subtract the minimum value
1363 SDOperand SwitchOp = getValue(B.SValue);
1364 MVT::ValueType VT = SwitchOp.getValueType();
1365 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1366 DAG.getConstant(B.First, VT));
1369 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1370 DAG.getConstant(B.Range, VT),
1374 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1375 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1377 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1379 // Make desired shift
1380 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1381 DAG.getConstant(1, TLI.getPointerTy()),
1384 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1385 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1388 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1389 DAG.getBasicBlock(B.Default));
1391 // Set NextBlock to be the MBB immediately after the current one, if any.
1392 // This is used to avoid emitting unnecessary branches to the next block.
1393 MachineBasicBlock *NextBlock = 0;
1394 MachineFunction::iterator BBI = CurMBB;
1395 if (++BBI != CurMBB->getParent()->end())
1398 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1399 if (MBB == NextBlock)
1400 DAG.setRoot(BrRange);
1402 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1403 DAG.getBasicBlock(MBB)));
1405 CurMBB->addSuccessor(B.Default);
1406 CurMBB->addSuccessor(MBB);
1411 /// visitBitTestCase - this function produces one "bit test"
1412 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1414 SelectionDAGISel::BitTestCase &B) {
1415 // Emit bit tests and jumps
1416 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1418 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1420 DAG.getConstant(B.Mask,
1421 TLI.getPointerTy()));
1422 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1423 DAG.getConstant(0, TLI.getPointerTy()),
1425 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1426 AndCmp, DAG.getBasicBlock(B.TargetBB));
1428 // Set NextBlock to be the MBB immediately after the current one, if any.
1429 // This is used to avoid emitting unnecessary branches to the next block.
1430 MachineBasicBlock *NextBlock = 0;
1431 MachineFunction::iterator BBI = CurMBB;
1432 if (++BBI != CurMBB->getParent()->end())
1435 if (NextMBB == NextBlock)
1438 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1439 DAG.getBasicBlock(NextMBB)));
1441 CurMBB->addSuccessor(B.TargetBB);
1442 CurMBB->addSuccessor(NextMBB);
1447 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1448 // Retrieve successors.
1449 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1450 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1452 if (isa<InlineAsm>(I.getCalledValue()))
1455 LowerCallTo(I, I.getCalledValue()->getType(), I.getParamAttrs(),
1458 getValue(I.getOperand(0)),
1461 // If the value of the invoke is used outside of its defining block, make it
1462 // available as a virtual register.
1463 if (!I.use_empty()) {
1464 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1465 if (VMI != FuncInfo.ValueMap.end())
1466 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1469 // Drop into normal successor.
1470 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1471 DAG.getBasicBlock(Return)));
1473 // Update successor info
1474 CurMBB->addSuccessor(Return);
1475 CurMBB->addSuccessor(LandingPad);
1478 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1481 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1482 /// small case ranges).
1483 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1484 CaseRecVector& WorkList,
1486 MachineBasicBlock* Default) {
1487 Case& BackCase = *(CR.Range.second-1);
1489 // Size is the number of Cases represented by this range.
1490 unsigned Size = CR.Range.second - CR.Range.first;
1494 // Get the MachineFunction which holds the current MBB. This is used when
1495 // inserting any additional MBBs necessary to represent the switch.
1496 MachineFunction *CurMF = CurMBB->getParent();
1498 // Figure out which block is immediately after the current one.
1499 MachineBasicBlock *NextBlock = 0;
1500 MachineFunction::iterator BBI = CR.CaseBB;
1502 if (++BBI != CurMBB->getParent()->end())
1505 // TODO: If any two of the cases has the same destination, and if one value
1506 // is the same as the other, but has one bit unset that the other has set,
1507 // use bit manipulation to do two compares at once. For example:
1508 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1510 // Rearrange the case blocks so that the last one falls through if possible.
1511 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1512 // The last case block won't fall through into 'NextBlock' if we emit the
1513 // branches in this order. See if rearranging a case value would help.
1514 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1515 if (I->BB == NextBlock) {
1516 std::swap(*I, BackCase);
1522 // Create a CaseBlock record representing a conditional branch to
1523 // the Case's target mbb if the value being switched on SV is equal
1525 MachineBasicBlock *CurBlock = CR.CaseBB;
1526 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1527 MachineBasicBlock *FallThrough;
1529 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1530 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1532 // If the last case doesn't match, go to the default block.
1533 FallThrough = Default;
1536 Value *RHS, *LHS, *MHS;
1538 if (I->High == I->Low) {
1539 // This is just small small case range :) containing exactly 1 case
1541 LHS = SV; RHS = I->High; MHS = NULL;
1544 LHS = I->Low; MHS = SV; RHS = I->High;
1546 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1547 I->BB, FallThrough, CurBlock);
1549 // If emitting the first comparison, just call visitSwitchCase to emit the
1550 // code into the current block. Otherwise, push the CaseBlock onto the
1551 // vector to be later processed by SDISel, and insert the node's MBB
1552 // before the next MBB.
1553 if (CurBlock == CurMBB)
1554 visitSwitchCase(CB);
1556 SwitchCases.push_back(CB);
1558 CurBlock = FallThrough;
1564 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1565 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1566 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1569 /// handleJTSwitchCase - Emit jumptable for current switch case range
1570 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1571 CaseRecVector& WorkList,
1573 MachineBasicBlock* Default) {
1574 Case& FrontCase = *CR.Range.first;
1575 Case& BackCase = *(CR.Range.second-1);
1577 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1578 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1581 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1585 if (!areJTsAllowed(TLI) || TSize <= 3)
1588 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1592 DOUT << "Lowering jump table\n"
1593 << "First entry: " << First << ". Last entry: " << Last << "\n"
1594 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1596 // Get the MachineFunction which holds the current MBB. This is used when
1597 // inserting any additional MBBs necessary to represent the switch.
1598 MachineFunction *CurMF = CurMBB->getParent();
1600 // Figure out which block is immediately after the current one.
1601 MachineBasicBlock *NextBlock = 0;
1602 MachineFunction::iterator BBI = CR.CaseBB;
1604 if (++BBI != CurMBB->getParent()->end())
1607 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1609 // Create a new basic block to hold the code for loading the address
1610 // of the jump table, and jumping to it. Update successor information;
1611 // we will either branch to the default case for the switch, or the jump
1613 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1614 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1615 CR.CaseBB->addSuccessor(Default);
1616 CR.CaseBB->addSuccessor(JumpTableBB);
1618 // Build a vector of destination BBs, corresponding to each target
1619 // of the jump table. If the value of the jump table slot corresponds to
1620 // a case statement, push the case's BB onto the vector, otherwise, push
1622 std::vector<MachineBasicBlock*> DestBBs;
1623 int64_t TEI = First;
1624 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1625 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1626 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1628 if ((Low <= TEI) && (TEI <= High)) {
1629 DestBBs.push_back(I->BB);
1633 DestBBs.push_back(Default);
1637 // Update successor info. Add one edge to each unique successor.
1638 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1639 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1640 E = DestBBs.end(); I != E; ++I) {
1641 if (!SuccsHandled[(*I)->getNumber()]) {
1642 SuccsHandled[(*I)->getNumber()] = true;
1643 JumpTableBB->addSuccessor(*I);
1647 // Create a jump table index for this jump table, or return an existing
1649 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1651 // Set the jump table information so that we can codegen it as a second
1652 // MachineBasicBlock
1653 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1654 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1655 (CR.CaseBB == CurMBB));
1656 if (CR.CaseBB == CurMBB)
1657 visitJumpTableHeader(JT, JTH);
1659 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1664 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1666 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1667 CaseRecVector& WorkList,
1669 MachineBasicBlock* Default) {
1670 // Get the MachineFunction which holds the current MBB. This is used when
1671 // inserting any additional MBBs necessary to represent the switch.
1672 MachineFunction *CurMF = CurMBB->getParent();
1674 // Figure out which block is immediately after the current one.
1675 MachineBasicBlock *NextBlock = 0;
1676 MachineFunction::iterator BBI = CR.CaseBB;
1678 if (++BBI != CurMBB->getParent()->end())
1681 Case& FrontCase = *CR.Range.first;
1682 Case& BackCase = *(CR.Range.second-1);
1683 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1685 // Size is the number of Cases represented by this range.
1686 unsigned Size = CR.Range.second - CR.Range.first;
1688 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1689 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1691 CaseItr Pivot = CR.Range.first + Size/2;
1693 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1694 // (heuristically) allow us to emit JumpTable's later.
1696 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1700 uint64_t LSize = FrontCase.size();
1701 uint64_t RSize = TSize-LSize;
1702 DOUT << "Selecting best pivot: \n"
1703 << "First: " << First << ", Last: " << Last <<"\n"
1704 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1705 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1707 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1708 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1709 assert((RBegin-LEnd>=1) && "Invalid case distance");
1710 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1711 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1712 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1713 // Should always split in some non-trivial place
1715 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1716 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1717 << "Metric: " << Metric << "\n";
1718 if (FMetric < Metric) {
1721 DOUT << "Current metric set to: " << FMetric << "\n";
1727 if (areJTsAllowed(TLI)) {
1728 // If our case is dense we *really* should handle it earlier!
1729 assert((FMetric > 0) && "Should handle dense range earlier!");
1731 Pivot = CR.Range.first + Size/2;
1734 CaseRange LHSR(CR.Range.first, Pivot);
1735 CaseRange RHSR(Pivot, CR.Range.second);
1736 Constant *C = Pivot->Low;
1737 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1739 // We know that we branch to the LHS if the Value being switched on is
1740 // less than the Pivot value, C. We use this to optimize our binary
1741 // tree a bit, by recognizing that if SV is greater than or equal to the
1742 // LHS's Case Value, and that Case Value is exactly one less than the
1743 // Pivot's Value, then we can branch directly to the LHS's Target,
1744 // rather than creating a leaf node for it.
1745 if ((LHSR.second - LHSR.first) == 1 &&
1746 LHSR.first->High == CR.GE &&
1747 cast<ConstantInt>(C)->getSExtValue() ==
1748 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1749 TrueBB = LHSR.first->BB;
1751 TrueBB = new MachineBasicBlock(LLVMBB);
1752 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1753 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1756 // Similar to the optimization above, if the Value being switched on is
1757 // known to be less than the Constant CR.LT, and the current Case Value
1758 // is CR.LT - 1, then we can branch directly to the target block for
1759 // the current Case Value, rather than emitting a RHS leaf node for it.
1760 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1761 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1762 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1763 FalseBB = RHSR.first->BB;
1765 FalseBB = new MachineBasicBlock(LLVMBB);
1766 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1767 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1770 // Create a CaseBlock record representing a conditional branch to
1771 // the LHS node if the value being switched on SV is less than C.
1772 // Otherwise, branch to LHS.
1773 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1774 TrueBB, FalseBB, CR.CaseBB);
1776 if (CR.CaseBB == CurMBB)
1777 visitSwitchCase(CB);
1779 SwitchCases.push_back(CB);
1784 /// handleBitTestsSwitchCase - if current case range has few destination and
1785 /// range span less, than machine word bitwidth, encode case range into series
1786 /// of masks and emit bit tests with these masks.
1787 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1788 CaseRecVector& WorkList,
1790 MachineBasicBlock* Default){
1791 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1793 Case& FrontCase = *CR.Range.first;
1794 Case& BackCase = *(CR.Range.second-1);
1796 // Get the MachineFunction which holds the current MBB. This is used when
1797 // inserting any additional MBBs necessary to represent the switch.
1798 MachineFunction *CurMF = CurMBB->getParent();
1800 unsigned numCmps = 0;
1801 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1803 // Single case counts one, case range - two.
1804 if (I->Low == I->High)
1810 // Count unique destinations
1811 SmallSet<MachineBasicBlock*, 4> Dests;
1812 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1813 Dests.insert(I->BB);
1814 if (Dests.size() > 3)
1815 // Don't bother the code below, if there are too much unique destinations
1818 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1819 << "Total number of comparisons: " << numCmps << "\n";
1821 // Compute span of values.
1822 Constant* minValue = FrontCase.Low;
1823 Constant* maxValue = BackCase.High;
1824 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1825 cast<ConstantInt>(minValue)->getSExtValue();
1826 DOUT << "Compare range: " << range << "\n"
1827 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1828 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1830 if (range>=IntPtrBits ||
1831 (!(Dests.size() == 1 && numCmps >= 3) &&
1832 !(Dests.size() == 2 && numCmps >= 5) &&
1833 !(Dests.size() >= 3 && numCmps >= 6)))
1836 DOUT << "Emitting bit tests\n";
1837 int64_t lowBound = 0;
1839 // Optimize the case where all the case values fit in a
1840 // word without having to subtract minValue. In this case,
1841 // we can optimize away the subtraction.
1842 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1843 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1844 range = cast<ConstantInt>(maxValue)->getSExtValue();
1846 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1849 CaseBitsVector CasesBits;
1850 unsigned i, count = 0;
1852 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1853 MachineBasicBlock* Dest = I->BB;
1854 for (i = 0; i < count; ++i)
1855 if (Dest == CasesBits[i].BB)
1859 assert((count < 3) && "Too much destinations to test!");
1860 CasesBits.push_back(CaseBits(0, Dest, 0));
1864 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1865 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1867 for (uint64_t j = lo; j <= hi; j++) {
1868 CasesBits[i].Mask |= 1ULL << j;
1869 CasesBits[i].Bits++;
1873 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1875 SelectionDAGISel::BitTestInfo BTC;
1877 // Figure out which block is immediately after the current one.
1878 MachineFunction::iterator BBI = CR.CaseBB;
1881 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1884 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1885 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1886 << ", BB: " << CasesBits[i].BB << "\n";
1888 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1889 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1890 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1895 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1896 -1U, (CR.CaseBB == CurMBB),
1897 CR.CaseBB, Default, BTC);
1899 if (CR.CaseBB == CurMBB)
1900 visitBitTestHeader(BTB);
1902 BitTestCases.push_back(BTB);
1908 // Clusterify - Transform simple list of Cases into list of CaseRange's
1909 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1910 const SwitchInst& SI) {
1911 unsigned numCmps = 0;
1913 // Start with "simple" cases
1914 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1915 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1916 Cases.push_back(Case(SI.getSuccessorValue(i),
1917 SI.getSuccessorValue(i),
1920 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1922 // Merge case into clusters
1923 if (Cases.size()>=2)
1924 // Must recompute end() each iteration because it may be
1925 // invalidated by erase if we hold on to it
1926 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1927 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1928 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1929 MachineBasicBlock* nextBB = J->BB;
1930 MachineBasicBlock* currentBB = I->BB;
1932 // If the two neighboring cases go to the same destination, merge them
1933 // into a single case.
1934 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1942 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1943 if (I->Low != I->High)
1944 // A range counts double, since it requires two compares.
1951 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1952 // Figure out which block is immediately after the current one.
1953 MachineBasicBlock *NextBlock = 0;
1954 MachineFunction::iterator BBI = CurMBB;
1956 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1958 // If there is only the default destination, branch to it if it is not the
1959 // next basic block. Otherwise, just fall through.
1960 if (SI.getNumOperands() == 2) {
1961 // Update machine-CFG edges.
1963 // If this is not a fall-through branch, emit the branch.
1964 if (Default != NextBlock)
1965 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1966 DAG.getBasicBlock(Default)));
1968 CurMBB->addSuccessor(Default);
1972 // If there are any non-default case statements, create a vector of Cases
1973 // representing each one, and sort the vector so that we can efficiently
1974 // create a binary search tree from them.
1976 unsigned numCmps = Clusterify(Cases, SI);
1977 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1978 << ". Total compares: " << numCmps << "\n";
1980 // Get the Value to be switched on and default basic blocks, which will be
1981 // inserted into CaseBlock records, representing basic blocks in the binary
1983 Value *SV = SI.getOperand(0);
1985 // Push the initial CaseRec onto the worklist
1986 CaseRecVector WorkList;
1987 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1989 while (!WorkList.empty()) {
1990 // Grab a record representing a case range to process off the worklist
1991 CaseRec CR = WorkList.back();
1992 WorkList.pop_back();
1994 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1997 // If the range has few cases (two or less) emit a series of specific
1999 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2002 // If the switch has more than 5 blocks, and at least 40% dense, and the
2003 // target supports indirect branches, then emit a jump table rather than
2004 // lowering the switch to a binary tree of conditional branches.
2005 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2008 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2009 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2010 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2015 void SelectionDAGLowering::visitSub(User &I) {
2016 // -0.0 - X --> fneg
2017 const Type *Ty = I.getType();
2018 if (isa<VectorType>(Ty)) {
2019 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2020 const VectorType *DestTy = cast<VectorType>(I.getType());
2021 const Type *ElTy = DestTy->getElementType();
2022 if (ElTy->isFloatingPoint()) {
2023 unsigned VL = DestTy->getNumElements();
2024 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2025 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2027 SDOperand Op2 = getValue(I.getOperand(1));
2028 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2034 if (Ty->isFloatingPoint()) {
2035 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2036 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2037 SDOperand Op2 = getValue(I.getOperand(1));
2038 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2043 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2046 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2047 SDOperand Op1 = getValue(I.getOperand(0));
2048 SDOperand Op2 = getValue(I.getOperand(1));
2050 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2053 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2054 SDOperand Op1 = getValue(I.getOperand(0));
2055 SDOperand Op2 = getValue(I.getOperand(1));
2057 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2058 MVT::getSizeInBits(Op2.getValueType()))
2059 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2060 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2061 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2063 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2066 void SelectionDAGLowering::visitICmp(User &I) {
2067 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2068 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2069 predicate = IC->getPredicate();
2070 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2071 predicate = ICmpInst::Predicate(IC->getPredicate());
2072 SDOperand Op1 = getValue(I.getOperand(0));
2073 SDOperand Op2 = getValue(I.getOperand(1));
2074 ISD::CondCode Opcode;
2075 switch (predicate) {
2076 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2077 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2078 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2079 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2080 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2081 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2082 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2083 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2084 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2085 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2087 assert(!"Invalid ICmp predicate value");
2088 Opcode = ISD::SETEQ;
2091 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2094 void SelectionDAGLowering::visitFCmp(User &I) {
2095 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2096 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2097 predicate = FC->getPredicate();
2098 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2099 predicate = FCmpInst::Predicate(FC->getPredicate());
2100 SDOperand Op1 = getValue(I.getOperand(0));
2101 SDOperand Op2 = getValue(I.getOperand(1));
2102 ISD::CondCode Condition, FOC, FPC;
2103 switch (predicate) {
2104 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2105 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2106 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2107 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2108 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2109 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2110 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2111 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2112 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2113 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2114 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2115 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2116 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2117 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2118 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2119 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2121 assert(!"Invalid FCmp predicate value");
2122 FOC = FPC = ISD::SETFALSE;
2125 if (FiniteOnlyFPMath())
2129 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2132 void SelectionDAGLowering::visitSelect(User &I) {
2133 SDOperand Cond = getValue(I.getOperand(0));
2134 SDOperand TrueVal = getValue(I.getOperand(1));
2135 SDOperand FalseVal = getValue(I.getOperand(2));
2136 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2137 TrueVal, FalseVal));
2141 void SelectionDAGLowering::visitTrunc(User &I) {
2142 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2143 SDOperand N = getValue(I.getOperand(0));
2144 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2145 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2148 void SelectionDAGLowering::visitZExt(User &I) {
2149 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2150 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2151 SDOperand N = getValue(I.getOperand(0));
2152 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2153 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2156 void SelectionDAGLowering::visitSExt(User &I) {
2157 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2158 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2159 SDOperand N = getValue(I.getOperand(0));
2160 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2161 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2164 void SelectionDAGLowering::visitFPTrunc(User &I) {
2165 // FPTrunc is never a no-op cast, no need to check
2166 SDOperand N = getValue(I.getOperand(0));
2167 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2168 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
2171 void SelectionDAGLowering::visitFPExt(User &I){
2172 // FPTrunc is never a no-op cast, no need to check
2173 SDOperand N = getValue(I.getOperand(0));
2174 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2175 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2178 void SelectionDAGLowering::visitFPToUI(User &I) {
2179 // FPToUI is never a no-op cast, no need to check
2180 SDOperand N = getValue(I.getOperand(0));
2181 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2182 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2185 void SelectionDAGLowering::visitFPToSI(User &I) {
2186 // FPToSI is never a no-op cast, no need to check
2187 SDOperand N = getValue(I.getOperand(0));
2188 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2189 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2192 void SelectionDAGLowering::visitUIToFP(User &I) {
2193 // UIToFP is never a no-op cast, no need to check
2194 SDOperand N = getValue(I.getOperand(0));
2195 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2196 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2199 void SelectionDAGLowering::visitSIToFP(User &I){
2200 // UIToFP is never a no-op cast, no need to check
2201 SDOperand N = getValue(I.getOperand(0));
2202 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2203 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2206 void SelectionDAGLowering::visitPtrToInt(User &I) {
2207 // What to do depends on the size of the integer and the size of the pointer.
2208 // We can either truncate, zero extend, or no-op, accordingly.
2209 SDOperand N = getValue(I.getOperand(0));
2210 MVT::ValueType SrcVT = N.getValueType();
2211 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2213 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2214 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2216 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2217 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2218 setValue(&I, Result);
2221 void SelectionDAGLowering::visitIntToPtr(User &I) {
2222 // What to do depends on the size of the integer and the size of the pointer.
2223 // We can either truncate, zero extend, or no-op, accordingly.
2224 SDOperand N = getValue(I.getOperand(0));
2225 MVT::ValueType SrcVT = N.getValueType();
2226 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2227 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2228 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2230 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2231 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2234 void SelectionDAGLowering::visitBitCast(User &I) {
2235 SDOperand N = getValue(I.getOperand(0));
2236 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2238 // BitCast assures us that source and destination are the same size so this
2239 // is either a BIT_CONVERT or a no-op.
2240 if (DestVT != N.getValueType())
2241 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2243 setValue(&I, N); // noop cast.
2246 void SelectionDAGLowering::visitInsertElement(User &I) {
2247 SDOperand InVec = getValue(I.getOperand(0));
2248 SDOperand InVal = getValue(I.getOperand(1));
2249 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2250 getValue(I.getOperand(2)));
2252 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2253 TLI.getValueType(I.getType()),
2254 InVec, InVal, InIdx));
2257 void SelectionDAGLowering::visitExtractElement(User &I) {
2258 SDOperand InVec = getValue(I.getOperand(0));
2259 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2260 getValue(I.getOperand(1)));
2261 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2262 TLI.getValueType(I.getType()), InVec, InIdx));
2265 void SelectionDAGLowering::visitShuffleVector(User &I) {
2266 SDOperand V1 = getValue(I.getOperand(0));
2267 SDOperand V2 = getValue(I.getOperand(1));
2268 SDOperand Mask = getValue(I.getOperand(2));
2270 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2271 TLI.getValueType(I.getType()),
2276 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2277 SDOperand N = getValue(I.getOperand(0));
2278 const Type *Ty = I.getOperand(0)->getType();
2280 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2283 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2284 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2287 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2288 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2289 getIntPtrConstant(Offset));
2291 Ty = StTy->getElementType(Field);
2293 Ty = cast<SequentialType>(Ty)->getElementType();
2295 // If this is a constant subscript, handle it quickly.
2296 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2297 if (CI->getZExtValue() == 0) continue;
2299 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2300 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
2304 // N = N + Idx * ElementSize;
2305 uint64_t ElementSize = TD->getABITypeSize(Ty);
2306 SDOperand IdxN = getValue(Idx);
2308 // If the index is smaller or larger than intptr_t, truncate or extend
2310 if (IdxN.getValueType() < N.getValueType()) {
2311 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2312 } else if (IdxN.getValueType() > N.getValueType())
2313 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2315 // If this is a multiply by a power of two, turn it into a shl
2316 // immediately. This is a very common case.
2317 if (isPowerOf2_64(ElementSize)) {
2318 unsigned Amt = Log2_64(ElementSize);
2319 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2320 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2321 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2325 SDOperand Scale = getIntPtrConstant(ElementSize);
2326 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2327 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2333 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2334 // If this is a fixed sized alloca in the entry block of the function,
2335 // allocate it statically on the stack.
2336 if (FuncInfo.StaticAllocaMap.count(&I))
2337 return; // getValue will auto-populate this.
2339 const Type *Ty = I.getAllocatedType();
2340 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2342 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2345 SDOperand AllocSize = getValue(I.getArraySize());
2346 MVT::ValueType IntPtr = TLI.getPointerTy();
2347 if (IntPtr < AllocSize.getValueType())
2348 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2349 else if (IntPtr > AllocSize.getValueType())
2350 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2352 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2353 getIntPtrConstant(TySize));
2355 // Handle alignment. If the requested alignment is less than or equal to
2356 // the stack alignment, ignore it. If the size is greater than or equal to
2357 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2358 unsigned StackAlign =
2359 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2360 if (Align <= StackAlign)
2363 // Round the size of the allocation up to the stack alignment size
2364 // by add SA-1 to the size.
2365 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2366 getIntPtrConstant(StackAlign-1));
2367 // Mask out the low bits for alignment purposes.
2368 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2369 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2371 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
2372 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2374 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2376 DAG.setRoot(DSA.getValue(1));
2378 // Inform the Frame Information that we have just allocated a variable-sized
2380 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2383 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2384 SDOperand Ptr = getValue(I.getOperand(0));
2390 // Do not serialize non-volatile loads against each other.
2391 Root = DAG.getRoot();
2394 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2395 Root, I.isVolatile(), I.getAlignment()));
2398 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2399 const Value *SV, SDOperand Root,
2401 unsigned Alignment) {
2403 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2404 isVolatile, Alignment);
2407 DAG.setRoot(L.getValue(1));
2409 PendingLoads.push_back(L.getValue(1));
2415 void SelectionDAGLowering::visitStore(StoreInst &I) {
2416 Value *SrcV = I.getOperand(0);
2417 SDOperand Src = getValue(SrcV);
2418 SDOperand Ptr = getValue(I.getOperand(1));
2419 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2420 I.isVolatile(), I.getAlignment()));
2423 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2425 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2426 unsigned Intrinsic) {
2427 bool HasChain = !I.doesNotAccessMemory();
2428 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2430 // Build the operand list.
2431 SmallVector<SDOperand, 8> Ops;
2432 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2434 // We don't need to serialize loads against other loads.
2435 Ops.push_back(DAG.getRoot());
2437 Ops.push_back(getRoot());
2441 // Add the intrinsic ID as an integer operand.
2442 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2444 // Add all operands of the call to the operand list.
2445 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2446 SDOperand Op = getValue(I.getOperand(i));
2447 assert(TLI.isTypeLegal(Op.getValueType()) &&
2448 "Intrinsic uses a non-legal type?");
2452 std::vector<MVT::ValueType> VTs;
2453 if (I.getType() != Type::VoidTy) {
2454 MVT::ValueType VT = TLI.getValueType(I.getType());
2455 if (MVT::isVector(VT)) {
2456 const VectorType *DestTy = cast<VectorType>(I.getType());
2457 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2459 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2460 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2463 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2467 VTs.push_back(MVT::Other);
2469 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2474 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2475 &Ops[0], Ops.size());
2476 else if (I.getType() != Type::VoidTy)
2477 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2478 &Ops[0], Ops.size());
2480 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2481 &Ops[0], Ops.size());
2484 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2486 PendingLoads.push_back(Chain);
2490 if (I.getType() != Type::VoidTy) {
2491 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2492 MVT::ValueType VT = TLI.getValueType(PTy);
2493 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2495 setValue(&I, Result);
2499 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2500 static GlobalVariable *ExtractTypeInfo (Value *V) {
2501 V = IntrinsicInst::StripPointerCasts(V);
2502 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2503 assert (GV || isa<ConstantPointerNull>(V) &&
2504 "TypeInfo must be a global variable or NULL");
2508 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2509 /// call, and add them to the specified machine basic block.
2510 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2511 MachineBasicBlock *MBB) {
2512 // Inform the MachineModuleInfo of the personality for this landing pad.
2513 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2514 assert(CE->getOpcode() == Instruction::BitCast &&
2515 isa<Function>(CE->getOperand(0)) &&
2516 "Personality should be a function");
2517 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2519 // Gather all the type infos for this landing pad and pass them along to
2520 // MachineModuleInfo.
2521 std::vector<GlobalVariable *> TyInfo;
2522 unsigned N = I.getNumOperands();
2524 for (unsigned i = N - 1; i > 2; --i) {
2525 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2526 unsigned FilterLength = CI->getZExtValue();
2527 unsigned FirstCatch = i + FilterLength + !FilterLength;
2528 assert (FirstCatch <= N && "Invalid filter length");
2530 if (FirstCatch < N) {
2531 TyInfo.reserve(N - FirstCatch);
2532 for (unsigned j = FirstCatch; j < N; ++j)
2533 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2534 MMI->addCatchTypeInfo(MBB, TyInfo);
2538 if (!FilterLength) {
2540 MMI->addCleanup(MBB);
2543 TyInfo.reserve(FilterLength - 1);
2544 for (unsigned j = i + 1; j < FirstCatch; ++j)
2545 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2546 MMI->addFilterTypeInfo(MBB, TyInfo);
2555 TyInfo.reserve(N - 3);
2556 for (unsigned j = 3; j < N; ++j)
2557 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2558 MMI->addCatchTypeInfo(MBB, TyInfo);
2562 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2563 /// we want to emit this as a call to a named external function, return the name
2564 /// otherwise lower it and return null.
2566 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2567 switch (Intrinsic) {
2569 // By default, turn this into a target intrinsic node.
2570 visitTargetIntrinsic(I, Intrinsic);
2572 case Intrinsic::vastart: visitVAStart(I); return 0;
2573 case Intrinsic::vaend: visitVAEnd(I); return 0;
2574 case Intrinsic::vacopy: visitVACopy(I); return 0;
2575 case Intrinsic::returnaddress:
2576 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2577 getValue(I.getOperand(1))));
2579 case Intrinsic::frameaddress:
2580 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2581 getValue(I.getOperand(1))));
2583 case Intrinsic::setjmp:
2584 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2586 case Intrinsic::longjmp:
2587 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2589 case Intrinsic::memcpy_i32:
2590 case Intrinsic::memcpy_i64:
2591 visitMemIntrinsic(I, ISD::MEMCPY);
2593 case Intrinsic::memset_i32:
2594 case Intrinsic::memset_i64:
2595 visitMemIntrinsic(I, ISD::MEMSET);
2597 case Intrinsic::memmove_i32:
2598 case Intrinsic::memmove_i64:
2599 visitMemIntrinsic(I, ISD::MEMMOVE);
2602 case Intrinsic::dbg_stoppoint: {
2603 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2604 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2605 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2609 Ops[1] = getValue(SPI.getLineValue());
2610 Ops[2] = getValue(SPI.getColumnValue());
2612 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2613 assert(DD && "Not a debug information descriptor");
2614 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2616 Ops[3] = DAG.getString(CompileUnit->getFileName());
2617 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2619 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2624 case Intrinsic::dbg_region_start: {
2625 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2626 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2627 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2628 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2629 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2630 DAG.getConstant(LabelID, MVT::i32)));
2635 case Intrinsic::dbg_region_end: {
2636 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2637 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2638 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2639 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2640 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2641 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2646 case Intrinsic::dbg_func_start: {
2647 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2648 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2649 if (MMI && FSI.getSubprogram() &&
2650 MMI->Verify(FSI.getSubprogram())) {
2651 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
2652 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2653 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2658 case Intrinsic::dbg_declare: {
2659 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2660 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2661 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
2662 SDOperand AddressOp = getValue(DI.getAddress());
2663 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2664 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
2670 case Intrinsic::eh_exception: {
2671 if (ExceptionHandling) {
2672 if (!CurMBB->isLandingPad()) {
2673 // FIXME: Mark exception register as live in. Hack for PR1508.
2674 unsigned Reg = TLI.getExceptionAddressRegister();
2675 if (Reg) CurMBB->addLiveIn(Reg);
2677 // Insert the EXCEPTIONADDR instruction.
2678 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2680 Ops[0] = DAG.getRoot();
2681 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2683 DAG.setRoot(Op.getValue(1));
2685 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2690 case Intrinsic::eh_selector_i32:
2691 case Intrinsic::eh_selector_i64: {
2692 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2693 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2694 MVT::i32 : MVT::i64);
2696 if (ExceptionHandling && MMI) {
2697 if (CurMBB->isLandingPad())
2698 addCatchInfo(I, MMI, CurMBB);
2701 FuncInfo.CatchInfoLost.insert(&I);
2703 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2704 unsigned Reg = TLI.getExceptionSelectorRegister();
2705 if (Reg) CurMBB->addLiveIn(Reg);
2708 // Insert the EHSELECTION instruction.
2709 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2711 Ops[0] = getValue(I.getOperand(1));
2713 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2715 DAG.setRoot(Op.getValue(1));
2717 setValue(&I, DAG.getConstant(0, VT));
2723 case Intrinsic::eh_typeid_for_i32:
2724 case Intrinsic::eh_typeid_for_i64: {
2725 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2726 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2727 MVT::i32 : MVT::i64);
2730 // Find the type id for the given typeinfo.
2731 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2733 unsigned TypeID = MMI->getTypeIDFor(GV);
2734 setValue(&I, DAG.getConstant(TypeID, VT));
2736 // Return something different to eh_selector.
2737 setValue(&I, DAG.getConstant(1, VT));
2743 case Intrinsic::eh_return: {
2744 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2746 if (MMI && ExceptionHandling) {
2747 MMI->setCallsEHReturn(true);
2748 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2751 getValue(I.getOperand(1)),
2752 getValue(I.getOperand(2))));
2754 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2760 case Intrinsic::eh_unwind_init: {
2761 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2762 MMI->setCallsUnwindInit(true);
2768 case Intrinsic::eh_dwarf_cfa: {
2769 if (ExceptionHandling) {
2770 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2772 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2773 CfaArg = DAG.getNode(ISD::TRUNCATE,
2774 TLI.getPointerTy(), getValue(I.getOperand(1)));
2776 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2777 TLI.getPointerTy(), getValue(I.getOperand(1)));
2779 SDOperand Offset = DAG.getNode(ISD::ADD,
2781 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2782 TLI.getPointerTy()),
2784 setValue(&I, DAG.getNode(ISD::ADD,
2786 DAG.getNode(ISD::FRAMEADDR,
2789 TLI.getPointerTy())),
2792 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2798 case Intrinsic::sqrt:
2799 setValue(&I, DAG.getNode(ISD::FSQRT,
2800 getValue(I.getOperand(1)).getValueType(),
2801 getValue(I.getOperand(1))));
2803 case Intrinsic::powi:
2804 setValue(&I, DAG.getNode(ISD::FPOWI,
2805 getValue(I.getOperand(1)).getValueType(),
2806 getValue(I.getOperand(1)),
2807 getValue(I.getOperand(2))));
2809 case Intrinsic::sin:
2810 setValue(&I, DAG.getNode(ISD::FSIN,
2811 getValue(I.getOperand(1)).getValueType(),
2812 getValue(I.getOperand(1))));
2814 case Intrinsic::cos:
2815 setValue(&I, DAG.getNode(ISD::FCOS,
2816 getValue(I.getOperand(1)).getValueType(),
2817 getValue(I.getOperand(1))));
2819 case Intrinsic::pow:
2820 setValue(&I, DAG.getNode(ISD::FPOW,
2821 getValue(I.getOperand(1)).getValueType(),
2822 getValue(I.getOperand(1)),
2823 getValue(I.getOperand(2))));
2825 case Intrinsic::pcmarker: {
2826 SDOperand Tmp = getValue(I.getOperand(1));
2827 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2830 case Intrinsic::readcyclecounter: {
2831 SDOperand Op = getRoot();
2832 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2833 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2836 DAG.setRoot(Tmp.getValue(1));
2839 case Intrinsic::part_select: {
2840 // Currently not implemented: just abort
2841 assert(0 && "part_select intrinsic not implemented");
2844 case Intrinsic::part_set: {
2845 // Currently not implemented: just abort
2846 assert(0 && "part_set intrinsic not implemented");
2849 case Intrinsic::bswap:
2850 setValue(&I, DAG.getNode(ISD::BSWAP,
2851 getValue(I.getOperand(1)).getValueType(),
2852 getValue(I.getOperand(1))));
2854 case Intrinsic::cttz: {
2855 SDOperand Arg = getValue(I.getOperand(1));
2856 MVT::ValueType Ty = Arg.getValueType();
2857 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2858 setValue(&I, result);
2861 case Intrinsic::ctlz: {
2862 SDOperand Arg = getValue(I.getOperand(1));
2863 MVT::ValueType Ty = Arg.getValueType();
2864 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2865 setValue(&I, result);
2868 case Intrinsic::ctpop: {
2869 SDOperand Arg = getValue(I.getOperand(1));
2870 MVT::ValueType Ty = Arg.getValueType();
2871 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2872 setValue(&I, result);
2875 case Intrinsic::stacksave: {
2876 SDOperand Op = getRoot();
2877 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2878 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2880 DAG.setRoot(Tmp.getValue(1));
2883 case Intrinsic::stackrestore: {
2884 SDOperand Tmp = getValue(I.getOperand(1));
2885 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2888 case Intrinsic::prefetch:
2889 // FIXME: Currently discarding prefetches.
2892 case Intrinsic::var_annotation:
2893 // Discard annotate attributes
2896 case Intrinsic::init_trampoline: {
2898 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
2902 Ops[1] = getValue(I.getOperand(1));
2903 Ops[2] = getValue(I.getOperand(2));
2904 Ops[3] = getValue(I.getOperand(3));
2905 Ops[4] = DAG.getSrcValue(I.getOperand(1));
2906 Ops[5] = DAG.getSrcValue(F);
2908 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
2909 DAG.getNodeValueTypes(TLI.getPointerTy(),
2914 DAG.setRoot(Tmp.getValue(1));
2917 case Intrinsic::flt_rounds: {
2918 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32));
2925 void SelectionDAGLowering::LowerCallTo(Instruction &I,
2926 const Type *CalledValueTy,
2927 const ParamAttrsList *Attrs,
2928 unsigned CallingConv,
2930 SDOperand Callee, unsigned OpIdx,
2931 MachineBasicBlock *LandingPad) {
2932 const PointerType *PT = cast<PointerType>(CalledValueTy);
2933 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2934 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2935 unsigned BeginLabel = 0, EndLabel = 0;
2937 TargetLowering::ArgListTy Args;
2938 TargetLowering::ArgListEntry Entry;
2939 Args.reserve(I.getNumOperands());
2940 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) {
2941 Value *Arg = I.getOperand(i);
2942 SDOperand ArgNode = getValue(Arg);
2943 Entry.Node = ArgNode; Entry.Ty = Arg->getType();
2945 unsigned attrInd = i - OpIdx + 1;
2946 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt);
2947 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt);
2948 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg);
2949 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet);
2950 Entry.isNest = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::Nest);
2951 Entry.isByVal = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ByVal);
2952 Args.push_back(Entry);
2955 bool MarkTryRange = LandingPad ||
2956 // C++ requires special handling of 'nounwind' calls.
2957 (Attrs && Attrs->paramHasAttr(0, ParamAttr::NoUnwind));
2959 if (MarkTryRange && ExceptionHandling && MMI) {
2960 // Insert a label before the invoke call to mark the try range. This can be
2961 // used to detect deletion of the invoke via the MachineModuleInfo.
2962 BeginLabel = MMI->NextLabelID();
2963 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2964 DAG.getConstant(BeginLabel, MVT::i32)));
2967 std::pair<SDOperand,SDOperand> Result =
2968 TLI.LowerCallTo(getRoot(), I.getType(),
2969 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt),
2970 FTy->isVarArg(), CallingConv, IsTailCall,
2972 if (I.getType() != Type::VoidTy)
2973 setValue(&I, Result.first);
2974 DAG.setRoot(Result.second);
2976 if (MarkTryRange && ExceptionHandling && MMI) {
2977 // Insert a label at the end of the invoke call to mark the try range. This
2978 // can be used to detect deletion of the invoke via the MachineModuleInfo.
2979 EndLabel = MMI->NextLabelID();
2980 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2981 DAG.getConstant(EndLabel, MVT::i32)));
2983 // Inform MachineModuleInfo of range.
2984 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
2989 void SelectionDAGLowering::visitCall(CallInst &I) {
2990 const char *RenameFn = 0;
2991 if (Function *F = I.getCalledFunction()) {
2992 if (F->isDeclaration()) {
2993 if (unsigned IID = F->getIntrinsicID()) {
2994 RenameFn = visitIntrinsicCall(I, IID);
3000 // Check for well-known libc/libm calls. If the function is internal, it
3001 // can't be a library call.
3002 unsigned NameLen = F->getNameLen();
3003 if (!F->hasInternalLinkage() && NameLen) {
3004 const char *NameStr = F->getNameStart();
3005 if (NameStr[0] == 'c' &&
3006 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3007 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3008 if (I.getNumOperands() == 3 && // Basic sanity checks.
3009 I.getOperand(1)->getType()->isFloatingPoint() &&
3010 I.getType() == I.getOperand(1)->getType() &&
3011 I.getType() == I.getOperand(2)->getType()) {
3012 SDOperand LHS = getValue(I.getOperand(1));
3013 SDOperand RHS = getValue(I.getOperand(2));
3014 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3018 } else if (NameStr[0] == 'f' &&
3019 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3020 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3021 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3022 if (I.getNumOperands() == 2 && // Basic sanity checks.
3023 I.getOperand(1)->getType()->isFloatingPoint() &&
3024 I.getType() == I.getOperand(1)->getType()) {
3025 SDOperand Tmp = getValue(I.getOperand(1));
3026 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3029 } else if (NameStr[0] == 's' &&
3030 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3031 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3032 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3033 if (I.getNumOperands() == 2 && // Basic sanity checks.
3034 I.getOperand(1)->getType()->isFloatingPoint() &&
3035 I.getType() == I.getOperand(1)->getType()) {
3036 SDOperand Tmp = getValue(I.getOperand(1));
3037 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3040 } else if (NameStr[0] == 'c' &&
3041 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3042 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3043 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3044 if (I.getNumOperands() == 2 && // Basic sanity checks.
3045 I.getOperand(1)->getType()->isFloatingPoint() &&
3046 I.getType() == I.getOperand(1)->getType()) {
3047 SDOperand Tmp = getValue(I.getOperand(1));
3048 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3053 } else if (isa<InlineAsm>(I.getOperand(0))) {
3060 Callee = getValue(I.getOperand(0));
3062 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3064 LowerCallTo(I, I.getCalledValue()->getType(), I.getParamAttrs(),
3072 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3073 /// this value and returns the result as a ValueVT value. This uses
3074 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3075 /// If the Flag pointer is NULL, no flag is used.
3076 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3077 SDOperand &Chain, SDOperand *Flag)const{
3078 // Copy the legal parts from the registers.
3079 unsigned NumParts = Regs.size();
3080 SmallVector<SDOperand, 8> Parts(NumParts);
3081 for (unsigned i = 0; i != NumParts; ++i) {
3082 SDOperand Part = Flag ?
3083 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3084 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3085 Chain = Part.getValue(1);
3087 *Flag = Part.getValue(2);
3091 // Assemble the legal parts into the final value.
3092 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3095 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3096 /// specified value into the registers specified by this object. This uses
3097 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3098 /// If the Flag pointer is NULL, no flag is used.
3099 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3100 SDOperand &Chain, SDOperand *Flag) const {
3101 // Get the list of the values's legal parts.
3102 unsigned NumParts = Regs.size();
3103 SmallVector<SDOperand, 8> Parts(NumParts);
3104 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3106 // Copy the parts into the registers.
3107 for (unsigned i = 0; i != NumParts; ++i) {
3108 SDOperand Part = Flag ?
3109 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3110 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3111 Chain = Part.getValue(0);
3113 *Flag = Part.getValue(1);
3117 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3118 /// operand list. This adds the code marker and includes the number of
3119 /// values added into it.
3120 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3121 std::vector<SDOperand> &Ops) const {
3122 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3123 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3124 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3125 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3128 /// isAllocatableRegister - If the specified register is safe to allocate,
3129 /// i.e. it isn't a stack pointer or some other special register, return the
3130 /// register class for the register. Otherwise, return null.
3131 static const TargetRegisterClass *
3132 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3133 const TargetLowering &TLI, const MRegisterInfo *MRI) {
3134 MVT::ValueType FoundVT = MVT::Other;
3135 const TargetRegisterClass *FoundRC = 0;
3136 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
3137 E = MRI->regclass_end(); RCI != E; ++RCI) {
3138 MVT::ValueType ThisVT = MVT::Other;
3140 const TargetRegisterClass *RC = *RCI;
3141 // If none of the the value types for this register class are valid, we
3142 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3143 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3145 if (TLI.isTypeLegal(*I)) {
3146 // If we have already found this register in a different register class,
3147 // choose the one with the largest VT specified. For example, on
3148 // PowerPC, we favor f64 register classes over f32.
3149 if (FoundVT == MVT::Other ||
3150 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3157 if (ThisVT == MVT::Other) continue;
3159 // NOTE: This isn't ideal. In particular, this might allocate the
3160 // frame pointer in functions that need it (due to them not being taken
3161 // out of allocation, because a variable sized allocation hasn't been seen
3162 // yet). This is a slight code pessimization, but should still work.
3163 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3164 E = RC->allocation_order_end(MF); I != E; ++I)
3166 // We found a matching register class. Keep looking at others in case
3167 // we find one with larger registers that this physreg is also in.
3178 /// AsmOperandInfo - This contains information for each constraint that we are
3180 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3181 /// ConstraintCode - This contains the actual string for the code, like "m".
3182 std::string ConstraintCode;
3184 /// ConstraintType - Information about the constraint code, e.g. Register,
3185 /// RegisterClass, Memory, Other, Unknown.
3186 TargetLowering::ConstraintType ConstraintType;
3188 /// CallOperand/CallOperandval - If this is the result output operand or a
3189 /// clobber, this is null, otherwise it is the incoming operand to the
3190 /// CallInst. This gets modified as the asm is processed.
3191 SDOperand CallOperand;
3192 Value *CallOperandVal;
3194 /// ConstraintVT - The ValueType for the operand value.
3195 MVT::ValueType ConstraintVT;
3197 /// AssignedRegs - If this is a register or register class operand, this
3198 /// contains the set of register corresponding to the operand.
3199 RegsForValue AssignedRegs;
3201 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3202 : InlineAsm::ConstraintInfo(info),
3203 ConstraintType(TargetLowering::C_Unknown),
3204 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3207 void ComputeConstraintToUse(const TargetLowering &TLI);
3209 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3210 /// busy in OutputRegs/InputRegs.
3211 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3212 std::set<unsigned> &OutputRegs,
3213 std::set<unsigned> &InputRegs) const {
3215 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3217 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3220 } // end anon namespace.
3222 /// getConstraintGenerality - Return an integer indicating how general CT is.
3223 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3225 default: assert(0 && "Unknown constraint type!");
3226 case TargetLowering::C_Other:
3227 case TargetLowering::C_Unknown:
3229 case TargetLowering::C_Register:
3231 case TargetLowering::C_RegisterClass:
3233 case TargetLowering::C_Memory:
3238 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3239 assert(!Codes.empty() && "Must have at least one constraint");
3241 std::string *Current = &Codes[0];
3242 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3243 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3244 ConstraintCode = *Current;
3245 ConstraintType = CurType;
3249 unsigned CurGenerality = getConstraintGenerality(CurType);
3251 // If we have multiple constraints, try to pick the most general one ahead
3252 // of time. This isn't a wonderful solution, but handles common cases.
3253 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3254 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3255 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3256 if (ThisGenerality > CurGenerality) {
3257 // This constraint letter is more general than the previous one,
3260 Current = &Codes[j];
3261 CurGenerality = ThisGenerality;
3265 ConstraintCode = *Current;
3266 ConstraintType = CurType;
3270 void SelectionDAGLowering::
3271 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3272 std::set<unsigned> &OutputRegs,
3273 std::set<unsigned> &InputRegs) {
3274 // Compute whether this value requires an input register, an output register,
3276 bool isOutReg = false;
3277 bool isInReg = false;
3278 switch (OpInfo.Type) {
3279 case InlineAsm::isOutput:
3282 // If this is an early-clobber output, or if there is an input
3283 // constraint that matches this, we need to reserve the input register
3284 // so no other inputs allocate to it.
3285 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3287 case InlineAsm::isInput:
3291 case InlineAsm::isClobber:
3298 MachineFunction &MF = DAG.getMachineFunction();
3299 std::vector<unsigned> Regs;
3301 // If this is a constraint for a single physreg, or a constraint for a
3302 // register class, find it.
3303 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3304 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3305 OpInfo.ConstraintVT);
3307 unsigned NumRegs = 1;
3308 if (OpInfo.ConstraintVT != MVT::Other)
3309 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3310 MVT::ValueType RegVT;
3311 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3314 // If this is a constraint for a specific physical register, like {r17},
3316 if (PhysReg.first) {
3317 if (OpInfo.ConstraintVT == MVT::Other)
3318 ValueVT = *PhysReg.second->vt_begin();
3320 // Get the actual register value type. This is important, because the user
3321 // may have asked for (e.g.) the AX register in i32 type. We need to
3322 // remember that AX is actually i16 to get the right extension.
3323 RegVT = *PhysReg.second->vt_begin();
3325 // This is a explicit reference to a physical register.
3326 Regs.push_back(PhysReg.first);
3328 // If this is an expanded reference, add the rest of the regs to Regs.
3330 TargetRegisterClass::iterator I = PhysReg.second->begin();
3331 TargetRegisterClass::iterator E = PhysReg.second->end();
3332 for (; *I != PhysReg.first; ++I)
3333 assert(I != E && "Didn't find reg!");
3335 // Already added the first reg.
3337 for (; NumRegs; --NumRegs, ++I) {
3338 assert(I != E && "Ran out of registers to allocate!");
3342 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3343 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3347 // Otherwise, if this was a reference to an LLVM register class, create vregs
3348 // for this reference.
3349 std::vector<unsigned> RegClassRegs;
3350 const TargetRegisterClass *RC = PhysReg.second;
3352 // If this is an early clobber or tied register, our regalloc doesn't know
3353 // how to maintain the constraint. If it isn't, go ahead and create vreg
3354 // and let the regalloc do the right thing.
3355 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3356 // If there is some other early clobber and this is an input register,
3357 // then we are forced to pre-allocate the input reg so it doesn't
3358 // conflict with the earlyclobber.
3359 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3360 RegVT = *PhysReg.second->vt_begin();
3362 if (OpInfo.ConstraintVT == MVT::Other)
3365 // Create the appropriate number of virtual registers.
3366 SSARegMap *RegMap = MF.getSSARegMap();
3367 for (; NumRegs; --NumRegs)
3368 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
3370 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3371 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3375 // Otherwise, we can't allocate it. Let the code below figure out how to
3376 // maintain these constraints.
3377 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3380 // This is a reference to a register class that doesn't directly correspond
3381 // to an LLVM register class. Allocate NumRegs consecutive, available,
3382 // registers from the class.
3383 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3384 OpInfo.ConstraintVT);
3387 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3388 unsigned NumAllocated = 0;
3389 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3390 unsigned Reg = RegClassRegs[i];
3391 // See if this register is available.
3392 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3393 (isInReg && InputRegs.count(Reg))) { // Already used.
3394 // Make sure we find consecutive registers.
3399 // Check to see if this register is allocatable (i.e. don't give out the
3402 RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3403 if (!RC) { // Couldn't allocate this register.
3404 // Reset NumAllocated to make sure we return consecutive registers.
3410 // Okay, this register is good, we can use it.
3413 // If we allocated enough consecutive registers, succeed.
3414 if (NumAllocated == NumRegs) {
3415 unsigned RegStart = (i-NumAllocated)+1;
3416 unsigned RegEnd = i+1;
3417 // Mark all of the allocated registers used.
3418 for (unsigned i = RegStart; i != RegEnd; ++i)
3419 Regs.push_back(RegClassRegs[i]);
3421 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3422 OpInfo.ConstraintVT);
3423 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3428 // Otherwise, we couldn't allocate enough registers for this.
3433 /// visitInlineAsm - Handle a call to an InlineAsm object.
3435 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3436 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3438 /// ConstraintOperands - Information about all of the constraints.
3439 std::vector<AsmOperandInfo> ConstraintOperands;
3441 SDOperand Chain = getRoot();
3444 std::set<unsigned> OutputRegs, InputRegs;
3446 // Do a prepass over the constraints, canonicalizing them, and building up the
3447 // ConstraintOperands list.
3448 std::vector<InlineAsm::ConstraintInfo>
3449 ConstraintInfos = IA->ParseConstraints();
3451 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3452 // constraint. If so, we can't let the register allocator allocate any input
3453 // registers, because it will not know to avoid the earlyclobbered output reg.
3454 bool SawEarlyClobber = false;
3456 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3457 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3458 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3459 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3461 MVT::ValueType OpVT = MVT::Other;
3463 // Compute the value type for each operand.
3464 switch (OpInfo.Type) {
3465 case InlineAsm::isOutput:
3466 if (!OpInfo.isIndirect) {
3467 // The return value of the call is this value. As such, there is no
3468 // corresponding argument.
3469 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3470 OpVT = TLI.getValueType(CS.getType());
3472 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3475 case InlineAsm::isInput:
3476 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3478 case InlineAsm::isClobber:
3483 // If this is an input or an indirect output, process the call argument.
3484 // BasicBlocks are labels, currently appearing only in asm's.
3485 if (OpInfo.CallOperandVal) {
3486 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3487 OpInfo.CallOperand =
3488 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(OpInfo.CallOperandVal)]);
3490 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3491 const Type *OpTy = OpInfo.CallOperandVal->getType();
3492 // If this is an indirect operand, the operand is a pointer to the
3494 if (OpInfo.isIndirect)
3495 OpTy = cast<PointerType>(OpTy)->getElementType();
3497 // If OpTy is not a first-class value, it may be a struct/union that we
3498 // can tile with integers.
3499 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3500 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3508 OpTy = IntegerType::get(BitSize);
3513 OpVT = TLI.getValueType(OpTy, true);
3517 OpInfo.ConstraintVT = OpVT;
3519 // Compute the constraint code and ConstraintType to use.
3520 OpInfo.ComputeConstraintToUse(TLI);
3522 // Keep track of whether we see an earlyclobber.
3523 SawEarlyClobber |= OpInfo.isEarlyClobber;
3525 // If this is a memory input, and if the operand is not indirect, do what we
3526 // need to to provide an address for the memory input.
3527 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3528 !OpInfo.isIndirect) {
3529 assert(OpInfo.Type == InlineAsm::isInput &&
3530 "Can only indirectify direct input operands!");
3532 // Memory operands really want the address of the value. If we don't have
3533 // an indirect input, put it in the constpool if we can, otherwise spill
3534 // it to a stack slot.
3536 // If the operand is a float, integer, or vector constant, spill to a
3537 // constant pool entry to get its address.
3538 Value *OpVal = OpInfo.CallOperandVal;
3539 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3540 isa<ConstantVector>(OpVal)) {
3541 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3542 TLI.getPointerTy());
3544 // Otherwise, create a stack slot and emit a store to it before the
3546 const Type *Ty = OpVal->getType();
3547 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3548 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3549 MachineFunction &MF = DAG.getMachineFunction();
3550 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3551 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3552 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3553 OpInfo.CallOperand = StackSlot;
3556 // There is no longer a Value* corresponding to this operand.
3557 OpInfo.CallOperandVal = 0;
3558 // It is now an indirect operand.
3559 OpInfo.isIndirect = true;
3562 // If this constraint is for a specific register, allocate it before
3564 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3565 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3567 ConstraintInfos.clear();
3570 // Second pass - Loop over all of the operands, assigning virtual or physregs
3571 // to registerclass operands.
3572 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3573 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3575 // C_Register operands have already been allocated, Other/Memory don't need
3577 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3578 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3581 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3582 std::vector<SDOperand> AsmNodeOperands;
3583 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3584 AsmNodeOperands.push_back(
3585 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3588 // Loop over all of the inputs, copying the operand values into the
3589 // appropriate registers and processing the output regs.
3590 RegsForValue RetValRegs;
3592 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3593 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3595 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3596 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3598 switch (OpInfo.Type) {
3599 case InlineAsm::isOutput: {
3600 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3601 OpInfo.ConstraintType != TargetLowering::C_Register) {
3602 // Memory output, or 'other' output (e.g. 'X' constraint).
3603 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3605 // Add information to the INLINEASM node to know about this output.
3606 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3607 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3608 TLI.getPointerTy()));
3609 AsmNodeOperands.push_back(OpInfo.CallOperand);
3613 // Otherwise, this is a register or register class output.
3615 // Copy the output from the appropriate register. Find a register that
3617 if (OpInfo.AssignedRegs.Regs.empty()) {
3618 cerr << "Couldn't allocate output reg for contraint '"
3619 << OpInfo.ConstraintCode << "'!\n";
3623 if (!OpInfo.isIndirect) {
3624 // This is the result value of the call.
3625 assert(RetValRegs.Regs.empty() &&
3626 "Cannot have multiple output constraints yet!");
3627 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3628 RetValRegs = OpInfo.AssignedRegs;
3630 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3631 OpInfo.CallOperandVal));
3634 // Add information to the INLINEASM node to know that this register is
3636 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3640 case InlineAsm::isInput: {
3641 SDOperand InOperandVal = OpInfo.CallOperand;
3643 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3644 // If this is required to match an output register we have already set,
3645 // just use its register.
3646 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3648 // Scan until we find the definition we already emitted of this operand.
3649 // When we find it, create a RegsForValue operand.
3650 unsigned CurOp = 2; // The first operand.
3651 for (; OperandNo; --OperandNo) {
3652 // Advance to the next operand.
3654 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3655 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3656 (NumOps & 7) == 4 /*MEM*/) &&
3657 "Skipped past definitions?");
3658 CurOp += (NumOps>>3)+1;
3662 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3663 if ((NumOps & 7) == 2 /*REGDEF*/) {
3664 // Add NumOps>>3 registers to MatchedRegs.
3665 RegsForValue MatchedRegs;
3666 MatchedRegs.ValueVT = InOperandVal.getValueType();
3667 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3668 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3670 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3671 MatchedRegs.Regs.push_back(Reg);
3674 // Use the produced MatchedRegs object to
3675 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3676 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3679 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3680 assert(0 && "matching constraints for memory operands unimp");
3684 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3685 assert(!OpInfo.isIndirect &&
3686 "Don't know how to handle indirect other inputs yet!");
3688 std::vector<SDOperand> Ops;
3689 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3692 cerr << "Invalid operand for inline asm constraint '"
3693 << OpInfo.ConstraintCode << "'!\n";
3697 // Add information to the INLINEASM node to know about this input.
3698 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3699 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3700 TLI.getPointerTy()));
3701 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3703 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3704 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3705 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3706 "Memory operands expect pointer values");
3708 // Add information to the INLINEASM node to know about this input.
3709 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3710 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3711 TLI.getPointerTy()));
3712 AsmNodeOperands.push_back(InOperandVal);
3716 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3717 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3718 "Unknown constraint type!");
3719 assert(!OpInfo.isIndirect &&
3720 "Don't know how to handle indirect register inputs yet!");
3722 // Copy the input into the appropriate registers.
3723 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3724 "Couldn't allocate input reg!");
3726 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3728 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3732 case InlineAsm::isClobber: {
3733 // Add the clobbered value to the operand list, so that the register
3734 // allocator is aware that the physreg got clobbered.
3735 if (!OpInfo.AssignedRegs.Regs.empty())
3736 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3743 // Finish up input operands.
3744 AsmNodeOperands[0] = Chain;
3745 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3747 Chain = DAG.getNode(ISD::INLINEASM,
3748 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3749 &AsmNodeOperands[0], AsmNodeOperands.size());
3750 Flag = Chain.getValue(1);
3752 // If this asm returns a register value, copy the result from that register
3753 // and set it as the value of the call.
3754 if (!RetValRegs.Regs.empty()) {
3755 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3757 // If the result of the inline asm is a vector, it may have the wrong
3758 // width/num elts. Make sure to convert it to the right type with
3760 if (MVT::isVector(Val.getValueType())) {
3761 const VectorType *VTy = cast<VectorType>(CS.getType());
3762 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3764 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3767 setValue(CS.getInstruction(), Val);
3770 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3772 // Process indirect outputs, first output all of the flagged copies out of
3774 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3775 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3776 Value *Ptr = IndirectStoresToEmit[i].second;
3777 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3778 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3781 // Emit the non-flagged stores from the physregs.
3782 SmallVector<SDOperand, 8> OutChains;
3783 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3784 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3785 getValue(StoresToEmit[i].second),
3786 StoresToEmit[i].second, 0));
3787 if (!OutChains.empty())
3788 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3789 &OutChains[0], OutChains.size());
3794 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3795 SDOperand Src = getValue(I.getOperand(0));
3797 MVT::ValueType IntPtr = TLI.getPointerTy();
3799 if (IntPtr < Src.getValueType())
3800 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3801 else if (IntPtr > Src.getValueType())
3802 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3804 // Scale the source by the type size.
3805 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
3806 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3807 Src, getIntPtrConstant(ElementSize));
3809 TargetLowering::ArgListTy Args;
3810 TargetLowering::ArgListEntry Entry;
3812 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3813 Args.push_back(Entry);
3815 std::pair<SDOperand,SDOperand> Result =
3816 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
3817 DAG.getExternalSymbol("malloc", IntPtr),
3819 setValue(&I, Result.first); // Pointers always fit in registers
3820 DAG.setRoot(Result.second);
3823 void SelectionDAGLowering::visitFree(FreeInst &I) {
3824 TargetLowering::ArgListTy Args;
3825 TargetLowering::ArgListEntry Entry;
3826 Entry.Node = getValue(I.getOperand(0));
3827 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3828 Args.push_back(Entry);
3829 MVT::ValueType IntPtr = TLI.getPointerTy();
3830 std::pair<SDOperand,SDOperand> Result =
3831 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
3832 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3833 DAG.setRoot(Result.second);
3836 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
3837 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3838 // instructions are special in various ways, which require special support to
3839 // insert. The specified MachineInstr is created but not inserted into any
3840 // basic blocks, and the scheduler passes ownership of it to this method.
3841 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
3842 MachineBasicBlock *MBB) {
3843 cerr << "If a target marks an instruction with "
3844 << "'usesCustomDAGSchedInserter', it must implement "
3845 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
3850 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3851 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3852 getValue(I.getOperand(1)),
3853 DAG.getSrcValue(I.getOperand(1))));
3856 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3857 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3858 getValue(I.getOperand(0)),
3859 DAG.getSrcValue(I.getOperand(0)));
3861 DAG.setRoot(V.getValue(1));
3864 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3865 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3866 getValue(I.getOperand(1)),
3867 DAG.getSrcValue(I.getOperand(1))));
3870 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3871 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3872 getValue(I.getOperand(1)),
3873 getValue(I.getOperand(2)),
3874 DAG.getSrcValue(I.getOperand(1)),
3875 DAG.getSrcValue(I.getOperand(2))));
3878 /// TargetLowering::LowerArguments - This is the default LowerArguments
3879 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3880 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3881 /// integrated into SDISel.
3882 std::vector<SDOperand>
3883 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3884 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3885 std::vector<SDOperand> Ops;
3886 Ops.push_back(DAG.getRoot());
3887 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3888 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3890 // Add one result value for each formal argument.
3891 std::vector<MVT::ValueType> RetVals;
3893 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3895 MVT::ValueType VT = getValueType(I->getType());
3896 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3897 unsigned OriginalAlignment =
3898 getTargetData()->getABITypeAlignment(I->getType());
3900 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3901 // that is zero extended!
3902 if (F.paramHasAttr(j, ParamAttr::ZExt))
3903 Flags &= ~(ISD::ParamFlags::SExt);
3904 if (F.paramHasAttr(j, ParamAttr::SExt))
3905 Flags |= ISD::ParamFlags::SExt;
3906 if (F.paramHasAttr(j, ParamAttr::InReg))
3907 Flags |= ISD::ParamFlags::InReg;
3908 if (F.paramHasAttr(j, ParamAttr::StructRet))
3909 Flags |= ISD::ParamFlags::StructReturn;
3910 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
3911 Flags |= ISD::ParamFlags::ByVal;
3912 const PointerType *Ty = cast<PointerType>(I->getType());
3913 const StructType *STy = cast<StructType>(Ty->getElementType());
3914 unsigned StructAlign =
3915 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy));
3916 unsigned StructSize = getTargetData()->getABITypeSize(STy);
3917 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
3918 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs);
3920 if (F.paramHasAttr(j, ParamAttr::Nest))
3921 Flags |= ISD::ParamFlags::Nest;
3922 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
3924 switch (getTypeAction(VT)) {
3925 default: assert(0 && "Unknown type action!");
3927 RetVals.push_back(VT);
3928 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3931 RetVals.push_back(getTypeToTransformTo(VT));
3932 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3935 // If this is an illegal type, it needs to be broken up to fit into
3937 MVT::ValueType RegisterVT = getRegisterType(VT);
3938 unsigned NumRegs = getNumRegisters(VT);
3939 for (unsigned i = 0; i != NumRegs; ++i) {
3940 RetVals.push_back(RegisterVT);
3941 // if it isn't first piece, alignment must be 1
3943 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3944 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3945 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3952 RetVals.push_back(MVT::Other);
3955 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3956 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3957 &Ops[0], Ops.size()).Val;
3958 unsigned NumArgRegs = Result->getNumValues() - 1;
3959 DAG.setRoot(SDOperand(Result, NumArgRegs));
3961 // Set up the return result vector.
3965 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3967 MVT::ValueType VT = getValueType(I->getType());
3969 switch (getTypeAction(VT)) {
3970 default: assert(0 && "Unknown type action!");
3972 Ops.push_back(SDOperand(Result, i++));
3975 SDOperand Op(Result, i++);
3976 if (MVT::isInteger(VT)) {
3977 if (F.paramHasAttr(Idx, ParamAttr::SExt))
3978 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
3979 DAG.getValueType(VT));
3980 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
3981 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
3982 DAG.getValueType(VT));
3983 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
3985 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3986 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
3992 MVT::ValueType PartVT = getRegisterType(VT);
3993 unsigned NumParts = getNumRegisters(VT);
3994 SmallVector<SDOperand, 4> Parts(NumParts);
3995 for (unsigned j = 0; j != NumParts; ++j)
3996 Parts[j] = SDOperand(Result, i++);
3997 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
4002 assert(i == NumArgRegs && "Argument register count mismatch!");
4007 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4008 /// implementation, which just inserts an ISD::CALL node, which is later custom
4009 /// lowered by the target to something concrete. FIXME: When all targets are
4010 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4011 std::pair<SDOperand, SDOperand>
4012 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4013 bool RetTyIsSigned, bool isVarArg,
4014 unsigned CallingConv, bool isTailCall,
4016 ArgListTy &Args, SelectionDAG &DAG) {
4017 SmallVector<SDOperand, 32> Ops;
4018 Ops.push_back(Chain); // Op#0 - Chain
4019 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4020 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4021 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4022 Ops.push_back(Callee);
4024 // Handle all of the outgoing arguments.
4025 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4026 MVT::ValueType VT = getValueType(Args[i].Ty);
4027 SDOperand Op = Args[i].Node;
4028 unsigned Flags = ISD::ParamFlags::NoFlagSet;
4029 unsigned OriginalAlignment =
4030 getTargetData()->getABITypeAlignment(Args[i].Ty);
4033 Flags |= ISD::ParamFlags::SExt;
4035 Flags |= ISD::ParamFlags::ZExt;
4036 if (Args[i].isInReg)
4037 Flags |= ISD::ParamFlags::InReg;
4039 Flags |= ISD::ParamFlags::StructReturn;
4040 if (Args[i].isByVal) {
4041 Flags |= ISD::ParamFlags::ByVal;
4042 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4043 const StructType *STy = cast<StructType>(Ty->getElementType());
4044 unsigned StructAlign =
4045 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy));
4046 unsigned StructSize = getTargetData()->getABITypeSize(STy);
4047 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
4048 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs);
4051 Flags |= ISD::ParamFlags::Nest;
4052 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
4054 switch (getTypeAction(VT)) {
4055 default: assert(0 && "Unknown type action!");
4058 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4061 if (MVT::isInteger(VT)) {
4064 ExtOp = ISD::SIGN_EXTEND;
4065 else if (Args[i].isZExt)
4066 ExtOp = ISD::ZERO_EXTEND;
4068 ExtOp = ISD::ANY_EXTEND;
4069 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
4071 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
4072 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
4075 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4078 MVT::ValueType PartVT = getRegisterType(VT);
4079 unsigned NumParts = getNumRegisters(VT);
4080 SmallVector<SDOperand, 4> Parts(NumParts);
4081 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
4082 for (unsigned i = 0; i != NumParts; ++i) {
4083 // if it isn't first piece, alignment must be 1
4084 unsigned MyFlags = Flags;
4086 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4087 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4089 Ops.push_back(Parts[i]);
4090 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
4097 // Figure out the result value types.
4098 MVT::ValueType VT = getValueType(RetTy);
4099 MVT::ValueType RegisterVT = getRegisterType(VT);
4100 unsigned NumRegs = getNumRegisters(VT);
4101 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4102 for (unsigned i = 0; i != NumRegs; ++i)
4103 RetTys[i] = RegisterVT;
4105 RetTys.push_back(MVT::Other); // Always has a chain.
4107 // Create the CALL node.
4108 SDOperand Res = DAG.getNode(ISD::CALL,
4109 DAG.getVTList(&RetTys[0], NumRegs + 1),
4110 &Ops[0], Ops.size());
4111 Chain = Res.getValue(NumRegs);
4113 // Gather up the call result into a single value.
4114 if (RetTy != Type::VoidTy) {
4115 ISD::NodeType AssertOp = ISD::AssertSext;
4117 AssertOp = ISD::AssertZext;
4118 SmallVector<SDOperand, 4> Results(NumRegs);
4119 for (unsigned i = 0; i != NumRegs; ++i)
4120 Results[i] = Res.getValue(i);
4121 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
4124 return std::make_pair(Res, Chain);
4127 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4128 assert(0 && "LowerOperation not implemented for this target!");
4133 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4134 SelectionDAG &DAG) {
4135 assert(0 && "CustomPromoteOperation not implemented for this target!");
4140 /// getMemsetValue - Vectorized representation of the memset value
4142 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4143 SelectionDAG &DAG) {
4144 MVT::ValueType CurVT = VT;
4145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4146 uint64_t Val = C->getValue() & 255;
4148 while (CurVT != MVT::i8) {
4149 Val = (Val << Shift) | Val;
4151 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4153 return DAG.getConstant(Val, VT);
4155 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4157 while (CurVT != MVT::i8) {
4159 DAG.getNode(ISD::OR, VT,
4160 DAG.getNode(ISD::SHL, VT, Value,
4161 DAG.getConstant(Shift, MVT::i8)), Value);
4163 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4170 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4171 /// used when a memcpy is turned into a memset when the source is a constant
4173 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4174 SelectionDAG &DAG, TargetLowering &TLI,
4175 std::string &Str, unsigned Offset) {
4177 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4178 if (TLI.isLittleEndian())
4179 Offset = Offset + MSB - 1;
4180 for (unsigned i = 0; i != MSB; ++i) {
4181 Val = (Val << 8) | (unsigned char)Str[Offset];
4182 Offset += TLI.isLittleEndian() ? -1 : 1;
4184 return DAG.getConstant(Val, VT);
4187 /// getMemBasePlusOffset - Returns base and offset node for the
4188 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4189 SelectionDAG &DAG, TargetLowering &TLI) {
4190 MVT::ValueType VT = Base.getValueType();
4191 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4194 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4195 /// to replace the memset / memcpy is below the threshold. It also returns the
4196 /// types of the sequence of memory ops to perform memset / memcpy.
4197 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4198 unsigned Limit, uint64_t Size,
4199 unsigned Align, TargetLowering &TLI) {
4202 if (TLI.allowsUnalignedMemoryAccesses()) {
4205 switch (Align & 7) {
4221 MVT::ValueType LVT = MVT::i64;
4222 while (!TLI.isTypeLegal(LVT))
4223 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4224 assert(MVT::isInteger(LVT));
4229 unsigned NumMemOps = 0;
4231 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4232 while (VTSize > Size) {
4233 VT = (MVT::ValueType)((unsigned)VT - 1);
4236 assert(MVT::isInteger(VT));
4238 if (++NumMemOps > Limit)
4240 MemOps.push_back(VT);
4247 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4248 SDOperand Op1 = getValue(I.getOperand(1));
4249 SDOperand Op2 = getValue(I.getOperand(2));
4250 SDOperand Op3 = getValue(I.getOperand(3));
4251 SDOperand Op4 = getValue(I.getOperand(4));
4252 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4253 if (Align == 0) Align = 1;
4255 // If the source and destination are known to not be aliases, we can
4256 // lower memmove as memcpy.
4257 if (Op == ISD::MEMMOVE) {
4258 uint64_t Size = -1ULL;
4259 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4260 Size = C->getValue();
4261 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4262 AliasAnalysis::NoAlias)
4266 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4267 std::vector<MVT::ValueType> MemOps;
4269 // Expand memset / memcpy to a series of load / store ops
4270 // if the size operand falls below a certain threshold.
4271 SmallVector<SDOperand, 8> OutChains;
4273 default: break; // Do nothing for now.
4275 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4276 Size->getValue(), Align, TLI)) {
4277 unsigned NumMemOps = MemOps.size();
4278 unsigned Offset = 0;
4279 for (unsigned i = 0; i < NumMemOps; i++) {
4280 MVT::ValueType VT = MemOps[i];
4281 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4282 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4283 SDOperand Store = DAG.getStore(getRoot(), Value,
4284 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4285 I.getOperand(1), Offset);
4286 OutChains.push_back(Store);
4293 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4294 Size->getValue(), Align, TLI)) {
4295 unsigned NumMemOps = MemOps.size();
4296 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4297 GlobalAddressSDNode *G = NULL;
4299 bool CopyFromStr = false;
4301 if (Op2.getOpcode() == ISD::GlobalAddress)
4302 G = cast<GlobalAddressSDNode>(Op2);
4303 else if (Op2.getOpcode() == ISD::ADD &&
4304 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4305 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4306 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4307 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4310 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4311 if (GV && GV->isConstant()) {
4312 Str = GV->getStringValue(false);
4320 for (unsigned i = 0; i < NumMemOps; i++) {
4321 MVT::ValueType VT = MemOps[i];
4322 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4323 SDOperand Value, Chain, Store;
4326 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4329 DAG.getStore(Chain, Value,
4330 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4331 I.getOperand(1), DstOff);
4333 Value = DAG.getLoad(VT, getRoot(),
4334 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4335 I.getOperand(2), SrcOff, false, Align);
4336 Chain = Value.getValue(1);
4338 DAG.getStore(Chain, Value,
4339 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4340 I.getOperand(1), DstOff, false, Align);
4342 OutChains.push_back(Store);
4351 if (!OutChains.empty()) {
4352 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4353 &OutChains[0], OutChains.size()));
4358 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4362 assert(0 && "Unknown Op");
4364 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4367 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4370 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4376 //===----------------------------------------------------------------------===//
4377 // SelectionDAGISel code
4378 //===----------------------------------------------------------------------===//
4380 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4381 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
4384 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4385 AU.addRequired<AliasAnalysis>();
4386 AU.setPreservesAll();
4391 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4392 // Get alias analysis for load/store combining.
4393 AA = &getAnalysis<AliasAnalysis>();
4395 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4396 RegMap = MF.getSSARegMap();
4397 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4399 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4401 if (ExceptionHandling)
4402 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4403 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4404 // Mark landing pad.
4405 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4407 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4408 SelectBasicBlock(I, MF, FuncInfo);
4410 // Add function live-ins to entry block live-in set.
4411 BasicBlock *EntryBB = &Fn.getEntryBlock();
4412 BB = FuncInfo.MBBMap[EntryBB];
4413 if (!MF.livein_empty())
4414 for (MachineFunction::livein_iterator I = MF.livein_begin(),
4415 E = MF.livein_end(); I != E; ++I)
4416 BB->addLiveIn(I->first);
4419 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4420 "Not all catch info was assigned to a landing pad!");
4426 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4428 SDOperand Op = getValue(V);
4429 assert((Op.getOpcode() != ISD::CopyFromReg ||
4430 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4431 "Copy from a reg to the same reg!");
4433 MVT::ValueType SrcVT = Op.getValueType();
4434 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4435 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4436 SmallVector<SDOperand, 8> Regs(NumRegs);
4437 SmallVector<SDOperand, 8> Chains(NumRegs);
4439 // Copy the value by legal parts into sequential virtual registers.
4440 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4441 for (unsigned i = 0; i != NumRegs; ++i)
4442 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4443 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4446 void SelectionDAGISel::
4447 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4448 std::vector<SDOperand> &UnorderedChains) {
4449 // If this is the entry block, emit arguments.
4450 Function &F = *LLVMBB->getParent();
4451 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4452 SDOperand OldRoot = SDL.DAG.getRoot();
4453 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4456 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4458 if (!AI->use_empty()) {
4459 SDL.setValue(AI, Args[a]);
4461 // If this argument is live outside of the entry block, insert a copy from
4462 // whereever we got it to the vreg that other BB's will reference it as.
4463 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4464 if (VMI != FuncInfo.ValueMap.end()) {
4465 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4466 UnorderedChains.push_back(Copy);
4470 // Finally, if the target has anything special to do, allow it to do so.
4471 // FIXME: this should insert code into the DAG!
4472 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4475 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4476 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4477 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4478 if (isSelector(I)) {
4479 // Apply the catch info to DestBB.
4480 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4482 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4483 FLI.CatchInfoFound.insert(I);
4488 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4489 /// DAG and fixes their tailcall attribute operand.
4490 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4491 TargetLowering& TLI) {
4492 SDNode * Ret = NULL;
4493 SDOperand Terminator = DAG.getRoot();
4496 if (Terminator.getOpcode() == ISD::RET) {
4497 Ret = Terminator.Val;
4500 // Fix tail call attribute of CALL nodes.
4501 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4502 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4503 if (BI->getOpcode() == ISD::CALL) {
4504 SDOperand OpRet(Ret, 0);
4505 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4506 bool isMarkedTailCall =
4507 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4508 // If CALL node has tail call attribute set to true and the call is not
4509 // eligible (no RET or the target rejects) the attribute is fixed to
4510 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4511 // must correctly identify tail call optimizable calls.
4512 if (isMarkedTailCall &&
4514 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4515 SmallVector<SDOperand, 32> Ops;
4517 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4518 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4522 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4524 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4530 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4531 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4532 FunctionLoweringInfo &FuncInfo) {
4533 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo);
4535 std::vector<SDOperand> UnorderedChains;
4537 // Lower any arguments needed in this block if this is the entry block.
4538 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4539 LowerArguments(LLVMBB, SDL, UnorderedChains);
4541 BB = FuncInfo.MBBMap[LLVMBB];
4542 SDL.setCurrentBasicBlock(BB);
4544 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4546 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4547 // Add a label to mark the beginning of the landing pad. Deletion of the
4548 // landing pad can thus be detected via the MachineModuleInfo.
4549 unsigned LabelID = MMI->addLandingPad(BB);
4550 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4551 DAG.getConstant(LabelID, MVT::i32)));
4553 // Mark exception register as live in.
4554 unsigned Reg = TLI.getExceptionAddressRegister();
4555 if (Reg) BB->addLiveIn(Reg);
4557 // Mark exception selector register as live in.
4558 Reg = TLI.getExceptionSelectorRegister();
4559 if (Reg) BB->addLiveIn(Reg);
4561 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4562 // function and list of typeids logically belong to the invoke (or, if you
4563 // like, the basic block containing the invoke), and need to be associated
4564 // with it in the dwarf exception handling tables. Currently however the
4565 // information is provided by an intrinsic (eh.selector) that can be moved
4566 // to unexpected places by the optimizers: if the unwind edge is critical,
4567 // then breaking it can result in the intrinsics being in the successor of
4568 // the landing pad, not the landing pad itself. This results in exceptions
4569 // not being caught because no typeids are associated with the invoke.
4570 // This may not be the only way things can go wrong, but it is the only way
4571 // we try to work around for the moment.
4572 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4574 if (Br && Br->isUnconditional()) { // Critical edge?
4575 BasicBlock::iterator I, E;
4576 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4581 // No catch info found - try to extract some from the successor.
4582 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4586 // Lower all of the non-terminator instructions.
4587 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4591 // Ensure that all instructions which are used outside of their defining
4592 // blocks are available as virtual registers. Invoke is handled elsewhere.
4593 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4594 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4595 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4596 if (VMI != FuncInfo.ValueMap.end())
4597 UnorderedChains.push_back(
4598 SDL.CopyValueToVirtualRegister(I, VMI->second));
4601 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4602 // ensure constants are generated when needed. Remember the virtual registers
4603 // that need to be added to the Machine PHI nodes as input. We cannot just
4604 // directly add them, because expansion might result in multiple MBB's for one
4605 // BB. As such, the start of the BB might correspond to a different MBB than
4608 TerminatorInst *TI = LLVMBB->getTerminator();
4610 // Emit constants only once even if used by multiple PHI nodes.
4611 std::map<Constant*, unsigned> ConstantsOut;
4613 // Vector bool would be better, but vector<bool> is really slow.
4614 std::vector<unsigned char> SuccsHandled;
4615 if (TI->getNumSuccessors())
4616 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4618 // Check successor nodes' PHI nodes that expect a constant to be available
4620 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4621 BasicBlock *SuccBB = TI->getSuccessor(succ);
4622 if (!isa<PHINode>(SuccBB->begin())) continue;
4623 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4625 // If this terminator has multiple identical successors (common for
4626 // switches), only handle each succ once.
4627 unsigned SuccMBBNo = SuccMBB->getNumber();
4628 if (SuccsHandled[SuccMBBNo]) continue;
4629 SuccsHandled[SuccMBBNo] = true;
4631 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4634 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4635 // nodes and Machine PHI nodes, but the incoming operands have not been
4637 for (BasicBlock::iterator I = SuccBB->begin();
4638 (PN = dyn_cast<PHINode>(I)); ++I) {
4639 // Ignore dead phi's.
4640 if (PN->use_empty()) continue;
4643 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4645 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4646 unsigned &RegOut = ConstantsOut[C];
4648 RegOut = FuncInfo.CreateRegForValue(C);
4649 UnorderedChains.push_back(
4650 SDL.CopyValueToVirtualRegister(C, RegOut));
4654 Reg = FuncInfo.ValueMap[PHIOp];
4656 assert(isa<AllocaInst>(PHIOp) &&
4657 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4658 "Didn't codegen value into a register!??");
4659 Reg = FuncInfo.CreateRegForValue(PHIOp);
4660 UnorderedChains.push_back(
4661 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4665 // Remember that this register needs to added to the machine PHI node as
4666 // the input for this MBB.
4667 MVT::ValueType VT = TLI.getValueType(PN->getType());
4668 unsigned NumRegisters = TLI.getNumRegisters(VT);
4669 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4670 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4673 ConstantsOut.clear();
4675 // Turn all of the unordered chains into one factored node.
4676 if (!UnorderedChains.empty()) {
4677 SDOperand Root = SDL.getRoot();
4678 if (Root.getOpcode() != ISD::EntryToken) {
4679 unsigned i = 0, e = UnorderedChains.size();
4680 for (; i != e; ++i) {
4681 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4682 if (UnorderedChains[i].Val->getOperand(0) == Root)
4683 break; // Don't add the root if we already indirectly depend on it.
4687 UnorderedChains.push_back(Root);
4689 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4690 &UnorderedChains[0], UnorderedChains.size()));
4693 // Lower the terminator after the copies are emitted.
4694 SDL.visit(*LLVMBB->getTerminator());
4696 // Copy over any CaseBlock records that may now exist due to SwitchInst
4697 // lowering, as well as any jump table information.
4698 SwitchCases.clear();
4699 SwitchCases = SDL.SwitchCases;
4701 JTCases = SDL.JTCases;
4702 BitTestCases.clear();
4703 BitTestCases = SDL.BitTestCases;
4705 // Make sure the root of the DAG is up-to-date.
4706 DAG.setRoot(SDL.getRoot());
4708 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4709 // with correct tailcall attribute so that the target can rely on the tailcall
4710 // attribute indicating whether the call is really eligible for tail call
4712 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4715 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4716 DOUT << "Lowered selection DAG:\n";
4719 // Run the DAG combiner in pre-legalize mode.
4720 DAG.Combine(false, *AA);
4722 DOUT << "Optimized lowered selection DAG:\n";
4725 // Second step, hack on the DAG until it only uses operations and types that
4726 // the target supports.
4727 #if 0 // Enable this some day.
4728 DAG.LegalizeTypes();
4729 // Someday even later, enable a dag combine pass here.
4733 DOUT << "Legalized selection DAG:\n";
4736 // Run the DAG combiner in post-legalize mode.
4737 DAG.Combine(true, *AA);
4739 DOUT << "Optimized legalized selection DAG:\n";
4742 if (ViewISelDAGs) DAG.viewGraph();
4744 // Third, instruction select all of the operations to machine code, adding the
4745 // code to the MachineBasicBlock.
4746 InstructionSelectBasicBlock(DAG);
4748 DOUT << "Selected machine code:\n";
4752 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4753 FunctionLoweringInfo &FuncInfo) {
4754 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4756 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4759 // First step, lower LLVM code to some DAG. This DAG may use operations and
4760 // types that are not supported by the target.
4761 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4763 // Second step, emit the lowered DAG as machine code.
4764 CodeGenAndEmitDAG(DAG);
4767 DOUT << "Total amount of phi nodes to update: "
4768 << PHINodesToUpdate.size() << "\n";
4769 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4770 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4771 << ", " << PHINodesToUpdate[i].second << ")\n";);
4773 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4774 // PHI nodes in successors.
4775 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4776 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4777 MachineInstr *PHI = PHINodesToUpdate[i].first;
4778 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4779 "This is not a machine PHI node that we are updating!");
4780 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4781 PHI->addMachineBasicBlockOperand(BB);
4786 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4787 // Lower header first, if it wasn't already lowered
4788 if (!BitTestCases[i].Emitted) {
4789 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4791 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo);
4792 // Set the current basic block to the mbb we wish to insert the code into
4793 BB = BitTestCases[i].Parent;
4794 HSDL.setCurrentBasicBlock(BB);
4796 HSDL.visitBitTestHeader(BitTestCases[i]);
4797 HSDAG.setRoot(HSDL.getRoot());
4798 CodeGenAndEmitDAG(HSDAG);
4801 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4802 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4804 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo);
4805 // Set the current basic block to the mbb we wish to insert the code into
4806 BB = BitTestCases[i].Cases[j].ThisBB;
4807 BSDL.setCurrentBasicBlock(BB);
4810 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4811 BitTestCases[i].Reg,
4812 BitTestCases[i].Cases[j]);
4814 BSDL.visitBitTestCase(BitTestCases[i].Default,
4815 BitTestCases[i].Reg,
4816 BitTestCases[i].Cases[j]);
4819 BSDAG.setRoot(BSDL.getRoot());
4820 CodeGenAndEmitDAG(BSDAG);
4824 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4825 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4826 MachineBasicBlock *PHIBB = PHI->getParent();
4827 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4828 "This is not a machine PHI node that we are updating!");
4829 // This is "default" BB. We have two jumps to it. From "header" BB and
4830 // from last "case" BB.
4831 if (PHIBB == BitTestCases[i].Default) {
4832 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4833 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent);
4834 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4835 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB);
4837 // One of "cases" BB.
4838 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4839 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4840 if (cBB->succ_end() !=
4841 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4842 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4843 PHI->addMachineBasicBlockOperand(cBB);
4849 // If the JumpTable record is filled in, then we need to emit a jump table.
4850 // Updating the PHI nodes is tricky in this case, since we need to determine
4851 // whether the PHI is a successor of the range check MBB or the jump table MBB
4852 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4853 // Lower header first, if it wasn't already lowered
4854 if (!JTCases[i].first.Emitted) {
4855 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4857 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo);
4858 // Set the current basic block to the mbb we wish to insert the code into
4859 BB = JTCases[i].first.HeaderBB;
4860 HSDL.setCurrentBasicBlock(BB);
4862 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4863 HSDAG.setRoot(HSDL.getRoot());
4864 CodeGenAndEmitDAG(HSDAG);
4867 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4869 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo);
4870 // Set the current basic block to the mbb we wish to insert the code into
4871 BB = JTCases[i].second.MBB;
4872 JSDL.setCurrentBasicBlock(BB);
4874 JSDL.visitJumpTable(JTCases[i].second);
4875 JSDAG.setRoot(JSDL.getRoot());
4876 CodeGenAndEmitDAG(JSDAG);
4879 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4880 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4881 MachineBasicBlock *PHIBB = PHI->getParent();
4882 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4883 "This is not a machine PHI node that we are updating!");
4884 // "default" BB. We can go there only from header BB.
4885 if (PHIBB == JTCases[i].second.Default) {
4886 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4887 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB);
4889 // JT BB. Just iterate over successors here
4890 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4891 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4892 PHI->addMachineBasicBlockOperand(BB);
4897 // If the switch block involved a branch to one of the actual successors, we
4898 // need to update PHI nodes in that block.
4899 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4900 MachineInstr *PHI = PHINodesToUpdate[i].first;
4901 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4902 "This is not a machine PHI node that we are updating!");
4903 if (BB->isSuccessor(PHI->getParent())) {
4904 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4905 PHI->addMachineBasicBlockOperand(BB);
4909 // If we generated any switch lowering information, build and codegen any
4910 // additional DAGs necessary.
4911 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4912 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4914 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo);
4916 // Set the current basic block to the mbb we wish to insert the code into
4917 BB = SwitchCases[i].ThisBB;
4918 SDL.setCurrentBasicBlock(BB);
4921 SDL.visitSwitchCase(SwitchCases[i]);
4922 SDAG.setRoot(SDL.getRoot());
4923 CodeGenAndEmitDAG(SDAG);
4925 // Handle any PHI nodes in successors of this chunk, as if we were coming
4926 // from the original BB before switch expansion. Note that PHI nodes can
4927 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4928 // handle them the right number of times.
4929 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4930 for (MachineBasicBlock::iterator Phi = BB->begin();
4931 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4932 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4933 for (unsigned pn = 0; ; ++pn) {
4934 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4935 if (PHINodesToUpdate[pn].first == Phi) {
4936 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4937 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4943 // Don't process RHS if same block as LHS.
4944 if (BB == SwitchCases[i].FalseBB)
4945 SwitchCases[i].FalseBB = 0;
4947 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4948 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4949 SwitchCases[i].FalseBB = 0;
4951 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4956 //===----------------------------------------------------------------------===//
4957 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4958 /// target node in the graph.
4959 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4960 if (ViewSchedDAGs) DAG.viewGraph();
4962 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4966 RegisterScheduler::setDefault(Ctor);
4969 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4972 if (ViewSUnitDAGs) SL->viewGraph();
4978 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4979 return new HazardRecognizer();
4982 //===----------------------------------------------------------------------===//
4983 // Helper functions used by the generated instruction selector.
4984 //===----------------------------------------------------------------------===//
4985 // Calls to these methods are generated by tblgen.
4987 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4988 /// the dag combiner simplified the 255, we still want to match. RHS is the
4989 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4990 /// specified in the .td file (e.g. 255).
4991 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4992 int64_t DesiredMaskS) const {
4993 uint64_t ActualMask = RHS->getValue();
4994 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4996 // If the actual mask exactly matches, success!
4997 if (ActualMask == DesiredMask)
5000 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5001 if (ActualMask & ~DesiredMask)
5004 // Otherwise, the DAG Combiner may have proven that the value coming in is
5005 // either already zero or is not demanded. Check for known zero input bits.
5006 uint64_t NeededMask = DesiredMask & ~ActualMask;
5007 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5010 // TODO: check to see if missing bits are just not demanded.
5012 // Otherwise, this pattern doesn't match.
5016 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5017 /// the dag combiner simplified the 255, we still want to match. RHS is the
5018 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5019 /// specified in the .td file (e.g. 255).
5020 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5021 int64_t DesiredMaskS) const {
5022 uint64_t ActualMask = RHS->getValue();
5023 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5025 // If the actual mask exactly matches, success!
5026 if (ActualMask == DesiredMask)
5029 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5030 if (ActualMask & ~DesiredMask)
5033 // Otherwise, the DAG Combiner may have proven that the value coming in is
5034 // either already zero or is not demanded. Check for known zero input bits.
5035 uint64_t NeededMask = DesiredMask & ~ActualMask;
5037 uint64_t KnownZero, KnownOne;
5038 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5040 // If all the missing bits in the or are already known to be set, match!
5041 if ((NeededMask & KnownOne) == NeededMask)
5044 // TODO: check to see if missing bits are just not demanded.
5046 // Otherwise, this pattern doesn't match.
5051 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5052 /// by tblgen. Others should not call it.
5053 void SelectionDAGISel::
5054 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5055 std::vector<SDOperand> InOps;
5056 std::swap(InOps, Ops);
5058 Ops.push_back(InOps[0]); // input chain.
5059 Ops.push_back(InOps[1]); // input asm string.
5061 unsigned i = 2, e = InOps.size();
5062 if (InOps[e-1].getValueType() == MVT::Flag)
5063 --e; // Don't process a flag operand if it is here.
5066 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5067 if ((Flags & 7) != 4 /*MEM*/) {
5068 // Just skip over this operand, copying the operands verbatim.
5069 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5070 i += (Flags >> 3) + 1;
5072 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5073 // Otherwise, this is a memory operand. Ask the target to select it.
5074 std::vector<SDOperand> SelOps;
5075 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5076 cerr << "Could not match memory address. Inline asm failure!\n";
5080 // Add this to the output node.
5081 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5082 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5084 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5089 // Add the flag input back if present.
5090 if (e != InOps.size())
5091 Ops.push_back(InOps.back());
5094 char SelectionDAGISel::ID = 0;