1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/SelectionDAG.h"
32 #include "llvm/CodeGen/SSARegMap.h"
33 #include "llvm/Target/MRegisterInfo.h"
34 #include "llvm/Target/TargetData.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/MathExtras.h"
42 #include "llvm/Support/Debug.h"
51 ViewISelDAGs("view-isel-dags", cl::Hidden,
52 cl::desc("Pop up a window to show isel dags as they are selected"));
54 ViewSchedDAGs("view-sched-dags", cl::Hidden,
55 cl::desc("Pop up a window to show sched dags as they are processed"));
57 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
60 // Scheduling heuristics
61 enum SchedHeuristics {
62 defaultScheduling, // Let the target specify its preference.
63 noScheduling, // No scheduling, emit breadth first sequence.
64 simpleScheduling, // Two pass, min. critical path, max. utilization.
65 simpleNoItinScheduling, // Same as above exact using generic latency.
66 listSchedulingBURR, // Bottom up reg reduction list scheduling.
67 listSchedulingTD // Top-down list scheduler.
71 cl::opt<SchedHeuristics>
74 cl::desc("Choose scheduling style"),
75 cl::init(defaultScheduling),
77 clEnumValN(defaultScheduling, "default",
78 "Target preferred scheduling style"),
79 clEnumValN(noScheduling, "none",
80 "No scheduling: breadth first sequencing"),
81 clEnumValN(simpleScheduling, "simple",
82 "Simple two pass scheduling: minimize critical path "
83 "and maximize processor utilization"),
84 clEnumValN(simpleNoItinScheduling, "simple-noitin",
85 "Simple two pass scheduling: Same as simple "
86 "except using generic latency"),
87 clEnumValN(listSchedulingBURR, "list-burr",
88 "Bottom up register reduction list scheduling"),
89 clEnumValN(listSchedulingTD, "list-td",
90 "Top-down list scheduler"),
95 /// RegsForValue - This struct represents the physical registers that a
96 /// particular value is assigned and the type information about the value.
97 /// This is needed because values can be promoted into larger registers and
98 /// expanded into multiple smaller registers than the value.
100 /// Regs - This list hold the register (for legal and promoted values)
101 /// or register set (for expanded values) that the value should be assigned
103 std::vector<unsigned> Regs;
105 /// RegVT - The value type of each register.
107 MVT::ValueType RegVT;
109 /// ValueVT - The value type of the LLVM value, which may be promoted from
110 /// RegVT or made from merging the two expanded parts.
111 MVT::ValueType ValueVT;
113 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
115 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
116 : RegVT(regvt), ValueVT(valuevt) {
119 RegsForValue(const std::vector<unsigned> ®s,
120 MVT::ValueType regvt, MVT::ValueType valuevt)
121 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
124 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
125 /// this value and returns the result as a ValueVT value. This uses
126 /// Chain/Flag as the input and updates them for the output Chain/Flag.
127 SDOperand getCopyFromRegs(SelectionDAG &DAG,
128 SDOperand &Chain, SDOperand &Flag) const;
130 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
131 /// specified value into the registers specified by this object. This uses
132 /// Chain/Flag as the input and updates them for the output Chain/Flag.
133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
134 SDOperand &Chain, SDOperand &Flag) const;
136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
137 /// operand list. This adds the code marker and includes the number of
138 /// values added into it.
139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
140 std::vector<SDOperand> &Ops) const;
145 //===--------------------------------------------------------------------===//
146 /// FunctionLoweringInfo - This contains information that is global to a
147 /// function that is used when lowering a region of the function.
148 class FunctionLoweringInfo {
155 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
157 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
158 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
160 /// ValueMap - Since we emit code for the function a basic block at a time,
161 /// we must remember which virtual registers hold the values for
162 /// cross-basic-block values.
163 std::map<const Value*, unsigned> ValueMap;
165 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
166 /// the entry block. This allows the allocas to be efficiently referenced
167 /// anywhere in the function.
168 std::map<const AllocaInst*, int> StaticAllocaMap;
170 unsigned MakeReg(MVT::ValueType VT) {
171 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
174 unsigned CreateRegForValue(const Value *V);
176 unsigned InitializeRegForValue(const Value *V) {
177 unsigned &R = ValueMap[V];
178 assert(R == 0 && "Already initialized this value register!");
179 return R = CreateRegForValue(V);
184 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
185 /// PHI nodes or outside of the basic block that defines it, or used by a
186 /// switch instruction, which may expand to multiple basic blocks.
187 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
188 if (isa<PHINode>(I)) return true;
189 BasicBlock *BB = I->getParent();
190 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
191 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
192 isa<SwitchInst>(*UI))
197 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
198 /// entry block, return true. This includes arguments used by switches, since
199 /// the switch may expand into multiple basic blocks.
200 static bool isOnlyUsedInEntryBlock(Argument *A) {
201 BasicBlock *Entry = A->getParent()->begin();
202 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
203 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
204 return false; // Use not in entry block.
208 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
209 Function &fn, MachineFunction &mf)
210 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
212 // Create a vreg for each argument register that is not dead and is used
213 // outside of the entry block for the function.
214 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
216 if (!isOnlyUsedInEntryBlock(AI))
217 InitializeRegForValue(AI);
219 // Initialize the mapping of values to registers. This is only set up for
220 // instruction values that are used outside of the block that defines
222 Function::iterator BB = Fn.begin(), EB = Fn.end();
223 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
224 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
225 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
226 const Type *Ty = AI->getAllocatedType();
227 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
229 std::max((unsigned)TLI.getTargetData().getTypeAlignment(Ty),
232 // If the alignment of the value is smaller than the size of the value,
233 // and if the size of the value is particularly small (<= 8 bytes),
234 // round up to the size of the value for potentially better performance.
236 // FIXME: This could be made better with a preferred alignment hook in
237 // TargetData. It serves primarily to 8-byte align doubles for X86.
238 if (Align < TySize && TySize <= 8) Align = TySize;
239 TySize *= CUI->getValue(); // Get total allocated size.
240 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
241 StaticAllocaMap[AI] =
242 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
245 for (; BB != EB; ++BB)
246 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
247 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
248 if (!isa<AllocaInst>(I) ||
249 !StaticAllocaMap.count(cast<AllocaInst>(I)))
250 InitializeRegForValue(I);
252 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
253 // also creates the initial PHI MachineInstrs, though none of the input
254 // operands are populated.
255 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
256 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
258 MF.getBasicBlockList().push_back(MBB);
260 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
263 for (BasicBlock::iterator I = BB->begin();
264 (PN = dyn_cast<PHINode>(I)); ++I)
265 if (!PN->use_empty()) {
266 MVT::ValueType VT = TLI.getValueType(PN->getType());
267 unsigned NumElements;
268 if (VT != MVT::Vector)
269 NumElements = TLI.getNumElements(VT);
271 MVT::ValueType VT1,VT2;
273 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
276 unsigned PHIReg = ValueMap[PN];
277 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
278 for (unsigned i = 0; i != NumElements; ++i)
279 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
284 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
285 /// the correctly promoted or expanded types. Assign these registers
286 /// consecutive vreg numbers and return the first assigned number.
287 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
288 MVT::ValueType VT = TLI.getValueType(V->getType());
290 // The number of multiples of registers that we need, to, e.g., split up
291 // a <2 x int64> -> 4 x i32 registers.
292 unsigned NumVectorRegs = 1;
294 // If this is a packed type, figure out what type it will decompose into
295 // and how many of the elements it will use.
296 if (VT == MVT::Vector) {
297 const PackedType *PTy = cast<PackedType>(V->getType());
298 unsigned NumElts = PTy->getNumElements();
299 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
301 // Divide the input until we get to a supported size. This will always
302 // end with a scalar if the target doesn't support vectors.
303 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
310 VT = getVectorType(EltTy, NumElts);
313 // The common case is that we will only create one register for this
314 // value. If we have that case, create and return the virtual register.
315 unsigned NV = TLI.getNumElements(VT);
317 // If we are promoting this value, pick the next largest supported type.
318 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
319 unsigned Reg = MakeReg(PromotedType);
320 // If this is a vector of supported or promoted types (e.g. 4 x i16),
321 // create all of the registers.
322 for (unsigned i = 1; i != NumVectorRegs; ++i)
323 MakeReg(PromotedType);
327 // If this value is represented with multiple target registers, make sure
328 // to create enough consecutive registers of the right (smaller) type.
329 unsigned NT = VT-1; // Find the type to use.
330 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
333 unsigned R = MakeReg((MVT::ValueType)NT);
334 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
335 MakeReg((MVT::ValueType)NT);
339 //===----------------------------------------------------------------------===//
340 /// SelectionDAGLowering - This is the common target-independent lowering
341 /// implementation that is parameterized by a TargetLowering object.
342 /// Also, targets can overload any lowering method.
345 class SelectionDAGLowering {
346 MachineBasicBlock *CurMBB;
348 std::map<const Value*, SDOperand> NodeMap;
350 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
351 /// them up and then emit token factor nodes when possible. This allows us to
352 /// get simple disambiguation between loads without worrying about alias
354 std::vector<SDOperand> PendingLoads;
356 /// Case - A pair of values to record the Value for a switch case, and the
357 /// case's target basic block.
358 typedef std::pair<Constant*, MachineBasicBlock*> Case;
359 typedef std::vector<Case>::iterator CaseItr;
360 typedef std::pair<CaseItr, CaseItr> CaseRange;
362 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
363 /// of conditional branches.
365 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
366 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
368 /// CaseBB - The MBB in which to emit the compare and branch
369 MachineBasicBlock *CaseBB;
370 /// LT, GE - If nonzero, we know the current case value must be less-than or
371 /// greater-than-or-equal-to these Constants.
374 /// Range - A pair of iterators representing the range of case values to be
375 /// processed at this point in the binary search tree.
379 /// The comparison function for sorting Case values.
381 bool operator () (const Case& C1, const Case& C2) {
382 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
383 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
385 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
386 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
391 // TLI - This is information that describes the available target features we
392 // need for lowering. This indicates when operations are unavailable,
393 // implemented with a libcall, etc.
396 const TargetData &TD;
398 /// SwitchCases - Vector of CaseBlock structures used to communicate
399 /// SwitchInst code generation information.
400 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
402 /// FuncInfo - Information about the function as a whole.
404 FunctionLoweringInfo &FuncInfo;
406 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
407 FunctionLoweringInfo &funcinfo)
408 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
412 /// getRoot - Return the current virtual root of the Selection DAG.
414 SDOperand getRoot() {
415 if (PendingLoads.empty())
416 return DAG.getRoot();
418 if (PendingLoads.size() == 1) {
419 SDOperand Root = PendingLoads[0];
421 PendingLoads.clear();
425 // Otherwise, we have to make a token factor node.
426 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
427 PendingLoads.clear();
432 void visit(Instruction &I) { visit(I.getOpcode(), I); }
434 void visit(unsigned Opcode, User &I) {
436 default: assert(0 && "Unknown instruction type encountered!");
438 // Build the switch statement using the Instruction.def file.
439 #define HANDLE_INST(NUM, OPCODE, CLASS) \
440 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
441 #include "llvm/Instruction.def"
445 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
447 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
448 SDOperand SrcValue, SDOperand Root,
451 SDOperand getIntPtrConstant(uint64_t Val) {
452 return DAG.getConstant(Val, TLI.getPointerTy());
455 SDOperand getValue(const Value *V);
457 const SDOperand &setValue(const Value *V, SDOperand NewN) {
458 SDOperand &N = NodeMap[V];
459 assert(N.Val == 0 && "Already set a value for this node!");
463 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
465 bool OutReg, bool InReg,
466 std::set<unsigned> &OutputRegs,
467 std::set<unsigned> &InputRegs);
469 // Terminator instructions.
470 void visitRet(ReturnInst &I);
471 void visitBr(BranchInst &I);
472 void visitSwitch(SwitchInst &I);
473 void visitUnreachable(UnreachableInst &I) { /* noop */ }
475 // Helper for visitSwitch
476 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
478 // These all get lowered before this pass.
479 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
480 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
482 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
483 void visitShift(User &I, unsigned Opcode);
484 void visitAdd(User &I) {
485 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
487 void visitSub(User &I);
488 void visitMul(User &I) {
489 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
491 void visitDiv(User &I) {
492 const Type *Ty = I.getType();
494 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
495 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
497 void visitRem(User &I) {
498 const Type *Ty = I.getType();
499 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
501 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
502 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
503 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
504 void visitShl(User &I) { visitShift(I, ISD::SHL); }
505 void visitShr(User &I) {
506 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
509 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
510 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ); }
511 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE); }
512 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE); }
513 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE); }
514 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
515 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
517 void visitExtractElement(User &I);
518 void visitInsertElement(User &I);
519 void visitShuffleVector(User &I);
521 void visitGetElementPtr(User &I);
522 void visitCast(User &I);
523 void visitSelect(User &I);
525 void visitMalloc(MallocInst &I);
526 void visitFree(FreeInst &I);
527 void visitAlloca(AllocaInst &I);
528 void visitLoad(LoadInst &I);
529 void visitStore(StoreInst &I);
530 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
531 void visitCall(CallInst &I);
532 void visitInlineAsm(CallInst &I);
533 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
534 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
536 void visitVAStart(CallInst &I);
537 void visitVAArg(VAArgInst &I);
538 void visitVAEnd(CallInst &I);
539 void visitVACopy(CallInst &I);
540 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
542 void visitMemIntrinsic(CallInst &I, unsigned Op);
544 void visitUserOp1(Instruction &I) {
545 assert(0 && "UserOp1 should not exist at instruction selection time!");
548 void visitUserOp2(Instruction &I) {
549 assert(0 && "UserOp2 should not exist at instruction selection time!");
553 } // end namespace llvm
555 SDOperand SelectionDAGLowering::getValue(const Value *V) {
556 SDOperand &N = NodeMap[V];
559 const Type *VTy = V->getType();
560 MVT::ValueType VT = TLI.getValueType(VTy);
561 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
562 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
563 visit(CE->getOpcode(), *CE);
564 assert(N.Val && "visit didn't populate the ValueMap!");
566 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
567 return N = DAG.getGlobalAddress(GV, VT);
568 } else if (isa<ConstantPointerNull>(C)) {
569 return N = DAG.getConstant(0, TLI.getPointerTy());
570 } else if (isa<UndefValue>(C)) {
571 if (!isa<PackedType>(VTy))
572 return N = DAG.getNode(ISD::UNDEF, VT);
574 // Create a VBUILD_VECTOR of undef nodes.
575 const PackedType *PTy = cast<PackedType>(VTy);
576 unsigned NumElements = PTy->getNumElements();
577 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
579 std::vector<SDOperand> Ops;
580 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
582 // Create a VConstant node with generic Vector type.
583 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
584 Ops.push_back(DAG.getValueType(PVT));
585 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
586 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
587 return N = DAG.getConstantFP(CFP->getValue(), VT);
588 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
589 unsigned NumElements = PTy->getNumElements();
590 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
592 // Now that we know the number and type of the elements, push a
593 // Constant or ConstantFP node onto the ops list for each element of
594 // the packed constant.
595 std::vector<SDOperand> Ops;
596 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
597 for (unsigned i = 0; i != NumElements; ++i)
598 Ops.push_back(getValue(CP->getOperand(i)));
600 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
602 if (MVT::isFloatingPoint(PVT))
603 Op = DAG.getConstantFP(0, PVT);
605 Op = DAG.getConstant(0, PVT);
606 Ops.assign(NumElements, Op);
609 // Create a VBUILD_VECTOR node with generic Vector type.
610 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
611 Ops.push_back(DAG.getValueType(PVT));
612 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
614 // Canonicalize all constant ints to be unsigned.
615 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
619 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
620 std::map<const AllocaInst*, int>::iterator SI =
621 FuncInfo.StaticAllocaMap.find(AI);
622 if (SI != FuncInfo.StaticAllocaMap.end())
623 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
626 std::map<const Value*, unsigned>::const_iterator VMI =
627 FuncInfo.ValueMap.find(V);
628 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
630 unsigned InReg = VMI->second;
632 // If this type is not legal, make it so now.
633 if (VT != MVT::Vector) {
634 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
636 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
638 // Source must be expanded. This input value is actually coming from the
639 // register pair VMI->second and VMI->second+1.
640 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
641 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
642 } else if (DestVT > VT) { // Promotion case
643 if (MVT::isFloatingPoint(VT))
644 N = DAG.getNode(ISD::FP_ROUND, VT, N);
646 N = DAG.getNode(ISD::TRUNCATE, VT, N);
649 // Otherwise, if this is a vector, make it available as a generic vector
651 MVT::ValueType PTyElementVT, PTyLegalElementVT;
652 const PackedType *PTy = cast<PackedType>(VTy);
653 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
656 // Build a VBUILD_VECTOR with the input registers.
657 std::vector<SDOperand> Ops;
658 if (PTyElementVT == PTyLegalElementVT) {
659 // If the value types are legal, just VBUILD the CopyFromReg nodes.
660 for (unsigned i = 0; i != NE; ++i)
661 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
663 } else if (PTyElementVT < PTyLegalElementVT) {
664 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
665 for (unsigned i = 0; i != NE; ++i) {
666 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
668 if (MVT::isFloatingPoint(PTyElementVT))
669 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
671 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
675 // If the register was expanded, use BUILD_PAIR.
676 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
677 for (unsigned i = 0; i != NE/2; ++i) {
678 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
680 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
682 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
686 Ops.push_back(DAG.getConstant(NE, MVT::i32));
687 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
688 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
690 // Finally, use a VBIT_CONVERT to make this available as the appropriate
692 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
693 DAG.getConstant(PTy->getNumElements(),
695 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
702 void SelectionDAGLowering::visitRet(ReturnInst &I) {
703 if (I.getNumOperands() == 0) {
704 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
707 std::vector<SDOperand> NewValues;
708 NewValues.push_back(getRoot());
709 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
710 SDOperand RetOp = getValue(I.getOperand(i));
712 // If this is an integer return value, we need to promote it ourselves to
713 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
715 if (MVT::isInteger(RetOp.getValueType()) &&
716 RetOp.getValueType() < MVT::i64) {
717 MVT::ValueType TmpVT;
718 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
719 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
723 if (I.getOperand(i)->getType()->isSigned())
724 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
726 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
728 NewValues.push_back(RetOp);
730 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
733 void SelectionDAGLowering::visitBr(BranchInst &I) {
734 // Update machine-CFG edges.
735 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
736 CurMBB->addSuccessor(Succ0MBB);
738 // Figure out which block is immediately after the current one.
739 MachineBasicBlock *NextBlock = 0;
740 MachineFunction::iterator BBI = CurMBB;
741 if (++BBI != CurMBB->getParent()->end())
744 if (I.isUnconditional()) {
745 // If this is not a fall-through branch, emit the branch.
746 if (Succ0MBB != NextBlock)
747 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
748 DAG.getBasicBlock(Succ0MBB)));
750 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
751 CurMBB->addSuccessor(Succ1MBB);
753 SDOperand Cond = getValue(I.getCondition());
754 if (Succ1MBB == NextBlock) {
755 // If the condition is false, fall through. This means we should branch
756 // if the condition is true to Succ #0.
757 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
758 Cond, DAG.getBasicBlock(Succ0MBB)));
759 } else if (Succ0MBB == NextBlock) {
760 // If the condition is true, fall through. This means we should branch if
761 // the condition is false to Succ #1. Invert the condition first.
762 SDOperand True = DAG.getConstant(1, Cond.getValueType());
763 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
764 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
765 Cond, DAG.getBasicBlock(Succ1MBB)));
767 std::vector<SDOperand> Ops;
768 Ops.push_back(getRoot());
769 // If the false case is the current basic block, then this is a self
770 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
771 // adds an extra instruction in the loop. Instead, invert the
772 // condition and emit "Loop: ... br!cond Loop; br Out.
773 if (CurMBB == Succ1MBB) {
774 std::swap(Succ0MBB, Succ1MBB);
775 SDOperand True = DAG.getConstant(1, Cond.getValueType());
776 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
778 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
779 DAG.getBasicBlock(Succ0MBB));
780 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
781 DAG.getBasicBlock(Succ1MBB)));
786 /// visitSwitchCase - Emits the necessary code to represent a single node in
787 /// the binary search tree resulting from lowering a switch instruction.
788 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
789 SDOperand SwitchOp = getValue(CB.SwitchV);
790 SDOperand CaseOp = getValue(CB.CaseC);
791 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
793 // Set NextBlock to be the MBB immediately after the current one, if any.
794 // This is used to avoid emitting unnecessary branches to the next block.
795 MachineBasicBlock *NextBlock = 0;
796 MachineFunction::iterator BBI = CurMBB;
797 if (++BBI != CurMBB->getParent()->end())
800 // If the lhs block is the next block, invert the condition so that we can
801 // fall through to the lhs instead of the rhs block.
802 if (CB.LHSBB == NextBlock) {
803 std::swap(CB.LHSBB, CB.RHSBB);
804 SDOperand True = DAG.getConstant(1, Cond.getValueType());
805 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
807 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
808 DAG.getBasicBlock(CB.LHSBB));
809 if (CB.RHSBB == NextBlock)
812 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
813 DAG.getBasicBlock(CB.RHSBB)));
814 // Update successor info
815 CurMBB->addSuccessor(CB.LHSBB);
816 CurMBB->addSuccessor(CB.RHSBB);
819 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
820 // Figure out which block is immediately after the current one.
821 MachineBasicBlock *NextBlock = 0;
822 MachineFunction::iterator BBI = CurMBB;
823 if (++BBI != CurMBB->getParent()->end())
826 // If there is only the default destination, branch to it if it is not the
827 // next basic block. Otherwise, just fall through.
828 if (I.getNumOperands() == 2) {
829 // Update machine-CFG edges.
830 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
831 // If this is not a fall-through branch, emit the branch.
832 if (DefaultMBB != NextBlock)
833 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
834 DAG.getBasicBlock(DefaultMBB)));
838 // If there are any non-default case statements, create a vector of Cases
839 // representing each one, and sort the vector so that we can efficiently
840 // create a binary search tree from them.
841 std::vector<Case> Cases;
842 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
843 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
844 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
846 std::sort(Cases.begin(), Cases.end(), CaseCmp());
848 // Get the Value to be switched on and default basic blocks, which will be
849 // inserted into CaseBlock records, representing basic blocks in the binary
851 Value *SV = I.getOperand(0);
852 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
854 // Get the current MachineFunction and LLVM basic block, for use in creating
855 // and inserting new MBBs during the creation of the binary search tree.
856 MachineFunction *CurMF = CurMBB->getParent();
857 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
859 // Push the initial CaseRec onto the worklist
860 std::vector<CaseRec> CaseVec;
861 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
863 while (!CaseVec.empty()) {
864 // Grab a record representing a case range to process off the worklist
865 CaseRec CR = CaseVec.back();
868 // Size is the number of Cases represented by this range. If Size is 1,
869 // then we are processing a leaf of the binary search tree. Otherwise,
870 // we need to pick a pivot, and push left and right ranges onto the
872 unsigned Size = CR.Range.second - CR.Range.first;
875 // Create a CaseBlock record representing a conditional branch to
876 // the Case's target mbb if the value being switched on SV is equal
877 // to C. Otherwise, branch to default.
878 Constant *C = CR.Range.first->first;
879 MachineBasicBlock *Target = CR.Range.first->second;
880 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
882 // If the MBB representing the leaf node is the current MBB, then just
883 // call visitSwitchCase to emit the code into the current block.
884 // Otherwise, push the CaseBlock onto the vector to be later processed
885 // by SDISel, and insert the node's MBB before the next MBB.
886 if (CR.CaseBB == CurMBB)
889 SwitchCases.push_back(CB);
890 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
893 // split case range at pivot
894 CaseItr Pivot = CR.Range.first + (Size / 2);
895 CaseRange LHSR(CR.Range.first, Pivot);
896 CaseRange RHSR(Pivot, CR.Range.second);
897 Constant *C = Pivot->first;
898 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
899 // We know that we branch to the LHS if the Value being switched on is
900 // less than the Pivot value, C. We use this to optimize our binary
901 // tree a bit, by recognizing that if SV is greater than or equal to the
902 // LHS's Case Value, and that Case Value is exactly one less than the
903 // Pivot's Value, then we can branch directly to the LHS's Target,
904 // rather than creating a leaf node for it.
905 if ((LHSR.second - LHSR.first) == 1 &&
906 LHSR.first->first == CR.GE &&
907 cast<ConstantIntegral>(C)->getRawValue() ==
908 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
909 LHSBB = LHSR.first->second;
911 LHSBB = new MachineBasicBlock(LLVMBB);
912 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
914 // Similar to the optimization above, if the Value being switched on is
915 // known to be less than the Constant CR.LT, and the current Case Value
916 // is CR.LT - 1, then we can branch directly to the target block for
917 // the current Case Value, rather than emitting a RHS leaf node for it.
918 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
919 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
920 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
921 RHSBB = RHSR.first->second;
923 RHSBB = new MachineBasicBlock(LLVMBB);
924 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
926 // Create a CaseBlock record representing a conditional branch to
927 // the LHS node if the value being switched on SV is less than C.
928 // Otherwise, branch to LHS.
929 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
930 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
931 if (CR.CaseBB == CurMBB)
934 SwitchCases.push_back(CB);
935 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
941 void SelectionDAGLowering::visitSub(User &I) {
943 if (I.getType()->isFloatingPoint()) {
944 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
945 if (CFP->isExactlyValue(-0.0)) {
946 SDOperand Op2 = getValue(I.getOperand(1));
947 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
951 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
954 void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
956 const Type *Ty = I.getType();
957 SDOperand Op1 = getValue(I.getOperand(0));
958 SDOperand Op2 = getValue(I.getOperand(1));
960 if (Ty->isIntegral()) {
961 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
962 } else if (Ty->isFloatingPoint()) {
963 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
965 const PackedType *PTy = cast<PackedType>(Ty);
966 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
967 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
968 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
972 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
973 SDOperand Op1 = getValue(I.getOperand(0));
974 SDOperand Op2 = getValue(I.getOperand(1));
976 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
978 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
981 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
982 ISD::CondCode UnsignedOpcode) {
983 SDOperand Op1 = getValue(I.getOperand(0));
984 SDOperand Op2 = getValue(I.getOperand(1));
985 ISD::CondCode Opcode = SignedOpcode;
986 if (I.getOperand(0)->getType()->isUnsigned())
987 Opcode = UnsignedOpcode;
988 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
991 void SelectionDAGLowering::visitSelect(User &I) {
992 SDOperand Cond = getValue(I.getOperand(0));
993 SDOperand TrueVal = getValue(I.getOperand(1));
994 SDOperand FalseVal = getValue(I.getOperand(2));
995 if (!isa<PackedType>(I.getType())) {
996 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
999 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1000 *(TrueVal.Val->op_end()-2),
1001 *(TrueVal.Val->op_end()-1)));
1005 void SelectionDAGLowering::visitCast(User &I) {
1006 SDOperand N = getValue(I.getOperand(0));
1007 MVT::ValueType SrcVT = N.getValueType();
1008 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1010 if (DestVT == MVT::Vector) {
1011 // This is a cast to a vector from something else. This is always a bit
1012 // convert. Get information about the input vector.
1013 const PackedType *DestTy = cast<PackedType>(I.getType());
1014 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1015 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1016 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1017 DAG.getValueType(EltVT)));
1018 } else if (SrcVT == DestVT) {
1019 setValue(&I, N); // noop cast.
1020 } else if (DestVT == MVT::i1) {
1021 // Cast to bool is a comparison against zero, not truncation to zero.
1022 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1023 DAG.getConstantFP(0.0, N.getValueType());
1024 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1025 } else if (isInteger(SrcVT)) {
1026 if (isInteger(DestVT)) { // Int -> Int cast
1027 if (DestVT < SrcVT) // Truncating cast?
1028 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1029 else if (I.getOperand(0)->getType()->isSigned())
1030 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1032 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1033 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1034 if (I.getOperand(0)->getType()->isSigned())
1035 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1037 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1039 assert(0 && "Unknown cast!");
1041 } else if (isFloatingPoint(SrcVT)) {
1042 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1043 if (DestVT < SrcVT) // Rounding cast?
1044 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1046 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1047 } else if (isInteger(DestVT)) { // FP -> Int cast.
1048 if (I.getType()->isSigned())
1049 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1051 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1053 assert(0 && "Unknown cast!");
1056 assert(SrcVT == MVT::Vector && "Unknown cast!");
1057 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1058 // This is a cast from a vector to something else. This is always a bit
1059 // convert. Get information about the input vector.
1060 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1064 void SelectionDAGLowering::visitInsertElement(User &I) {
1065 SDOperand InVec = getValue(I.getOperand(0));
1066 SDOperand InVal = getValue(I.getOperand(1));
1067 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1068 getValue(I.getOperand(2)));
1070 SDOperand Num = *(InVec.Val->op_end()-2);
1071 SDOperand Typ = *(InVec.Val->op_end()-1);
1072 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1073 InVec, InVal, InIdx, Num, Typ));
1076 void SelectionDAGLowering::visitExtractElement(User &I) {
1077 SDOperand InVec = getValue(I.getOperand(0));
1078 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1079 getValue(I.getOperand(1)));
1080 SDOperand Typ = *(InVec.Val->op_end()-1);
1081 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1082 TLI.getValueType(I.getType()), InVec, InIdx));
1085 void SelectionDAGLowering::visitShuffleVector(User &I) {
1086 SDOperand V1 = getValue(I.getOperand(0));
1087 SDOperand V2 = getValue(I.getOperand(1));
1088 SDOperand Mask = getValue(I.getOperand(2));
1090 SDOperand Num = *(V1.Val->op_end()-2);
1091 SDOperand Typ = *(V2.Val->op_end()-1);
1092 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1093 V1, V2, Mask, Num, Typ));
1097 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1098 SDOperand N = getValue(I.getOperand(0));
1099 const Type *Ty = I.getOperand(0)->getType();
1100 const Type *UIntPtrTy = TD.getIntPtrType();
1102 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1105 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1106 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1109 uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field];
1110 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1111 getIntPtrConstant(Offset));
1113 Ty = StTy->getElementType(Field);
1115 Ty = cast<SequentialType>(Ty)->getElementType();
1117 // If this is a constant subscript, handle it quickly.
1118 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1119 if (CI->getRawValue() == 0) continue;
1122 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1123 Offs = (int64_t)TD.getTypeSize(Ty)*CSI->getValue();
1125 Offs = TD.getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1126 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1130 // N = N + Idx * ElementSize;
1131 uint64_t ElementSize = TD.getTypeSize(Ty);
1132 SDOperand IdxN = getValue(Idx);
1134 // If the index is smaller or larger than intptr_t, truncate or extend
1136 if (IdxN.getValueType() < N.getValueType()) {
1137 if (Idx->getType()->isSigned())
1138 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1140 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1141 } else if (IdxN.getValueType() > N.getValueType())
1142 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1144 // If this is a multiply by a power of two, turn it into a shl
1145 // immediately. This is a very common case.
1146 if (isPowerOf2_64(ElementSize)) {
1147 unsigned Amt = Log2_64(ElementSize);
1148 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1149 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1150 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1154 SDOperand Scale = getIntPtrConstant(ElementSize);
1155 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1156 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1162 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1163 // If this is a fixed sized alloca in the entry block of the function,
1164 // allocate it statically on the stack.
1165 if (FuncInfo.StaticAllocaMap.count(&I))
1166 return; // getValue will auto-populate this.
1168 const Type *Ty = I.getAllocatedType();
1169 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
1170 unsigned Align = std::max((unsigned)TLI.getTargetData().getTypeAlignment(Ty),
1173 SDOperand AllocSize = getValue(I.getArraySize());
1174 MVT::ValueType IntPtr = TLI.getPointerTy();
1175 if (IntPtr < AllocSize.getValueType())
1176 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1177 else if (IntPtr > AllocSize.getValueType())
1178 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1180 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1181 getIntPtrConstant(TySize));
1183 // Handle alignment. If the requested alignment is less than or equal to the
1184 // stack alignment, ignore it and round the size of the allocation up to the
1185 // stack alignment size. If the size is greater than the stack alignment, we
1186 // note this in the DYNAMIC_STACKALLOC node.
1187 unsigned StackAlign =
1188 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1189 if (Align <= StackAlign) {
1191 // Add SA-1 to the size.
1192 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1193 getIntPtrConstant(StackAlign-1));
1194 // Mask out the low bits for alignment purposes.
1195 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1196 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1199 std::vector<MVT::ValueType> VTs;
1200 VTs.push_back(AllocSize.getValueType());
1201 VTs.push_back(MVT::Other);
1202 std::vector<SDOperand> Ops;
1203 Ops.push_back(getRoot());
1204 Ops.push_back(AllocSize);
1205 Ops.push_back(getIntPtrConstant(Align));
1206 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
1207 DAG.setRoot(setValue(&I, DSA).getValue(1));
1209 // Inform the Frame Information that we have just allocated a variable-sized
1211 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1214 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1215 SDOperand Ptr = getValue(I.getOperand(0));
1221 // Do not serialize non-volatile loads against each other.
1222 Root = DAG.getRoot();
1225 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
1226 Root, I.isVolatile()));
1229 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1230 SDOperand SrcValue, SDOperand Root,
1233 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1234 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1235 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
1237 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
1241 DAG.setRoot(L.getValue(1));
1243 PendingLoads.push_back(L.getValue(1));
1249 void SelectionDAGLowering::visitStore(StoreInst &I) {
1250 Value *SrcV = I.getOperand(0);
1251 SDOperand Src = getValue(SrcV);
1252 SDOperand Ptr = getValue(I.getOperand(1));
1253 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
1254 DAG.getSrcValue(I.getOperand(1))));
1257 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1258 /// access memory and has no other side effects at all.
1259 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1260 #define GET_NO_MEMORY_INTRINSICS
1261 #include "llvm/Intrinsics.gen"
1262 #undef GET_NO_MEMORY_INTRINSICS
1266 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1267 // have any side-effects or if it only reads memory.
1268 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1269 #define GET_SIDE_EFFECT_INFO
1270 #include "llvm/Intrinsics.gen"
1271 #undef GET_SIDE_EFFECT_INFO
1275 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1277 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1278 unsigned Intrinsic) {
1279 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1280 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1282 // Build the operand list.
1283 std::vector<SDOperand> Ops;
1284 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1286 // We don't need to serialize loads against other loads.
1287 Ops.push_back(DAG.getRoot());
1289 Ops.push_back(getRoot());
1293 // Add the intrinsic ID as an integer operand.
1294 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1296 // Add all operands of the call to the operand list.
1297 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1298 SDOperand Op = getValue(I.getOperand(i));
1300 // If this is a vector type, force it to the right packed type.
1301 if (Op.getValueType() == MVT::Vector) {
1302 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1303 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1305 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1306 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1307 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1310 assert(TLI.isTypeLegal(Op.getValueType()) &&
1311 "Intrinsic uses a non-legal type?");
1315 std::vector<MVT::ValueType> VTs;
1316 if (I.getType() != Type::VoidTy) {
1317 MVT::ValueType VT = TLI.getValueType(I.getType());
1318 if (VT == MVT::Vector) {
1319 const PackedType *DestTy = cast<PackedType>(I.getType());
1320 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1322 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1323 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1326 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1330 VTs.push_back(MVT::Other);
1335 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
1336 else if (I.getType() != Type::VoidTy)
1337 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
1339 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
1342 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1344 PendingLoads.push_back(Chain);
1348 if (I.getType() != Type::VoidTy) {
1349 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1350 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1351 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1352 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1353 DAG.getValueType(EVT));
1355 setValue(&I, Result);
1359 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1360 /// we want to emit this as a call to a named external function, return the name
1361 /// otherwise lower it and return null.
1363 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1364 switch (Intrinsic) {
1366 // By default, turn this into a target intrinsic node.
1367 visitTargetIntrinsic(I, Intrinsic);
1369 case Intrinsic::vastart: visitVAStart(I); return 0;
1370 case Intrinsic::vaend: visitVAEnd(I); return 0;
1371 case Intrinsic::vacopy: visitVACopy(I); return 0;
1372 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1373 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1374 case Intrinsic::setjmp:
1375 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1377 case Intrinsic::longjmp:
1378 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1380 case Intrinsic::memcpy_i32:
1381 case Intrinsic::memcpy_i64:
1382 visitMemIntrinsic(I, ISD::MEMCPY);
1384 case Intrinsic::memset_i32:
1385 case Intrinsic::memset_i64:
1386 visitMemIntrinsic(I, ISD::MEMSET);
1388 case Intrinsic::memmove_i32:
1389 case Intrinsic::memmove_i64:
1390 visitMemIntrinsic(I, ISD::MEMMOVE);
1393 case Intrinsic::dbg_stoppoint: {
1394 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1395 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1396 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1397 std::vector<SDOperand> Ops;
1399 Ops.push_back(getRoot());
1400 Ops.push_back(getValue(SPI.getLineValue()));
1401 Ops.push_back(getValue(SPI.getColumnValue()));
1403 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1404 assert(DD && "Not a debug information descriptor");
1405 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1407 Ops.push_back(DAG.getString(CompileUnit->getFileName()));
1408 Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
1410 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
1415 case Intrinsic::dbg_region_start: {
1416 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1417 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1418 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1419 std::vector<SDOperand> Ops;
1421 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1423 Ops.push_back(getRoot());
1424 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1426 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1431 case Intrinsic::dbg_region_end: {
1432 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1433 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1434 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1435 std::vector<SDOperand> Ops;
1437 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1439 Ops.push_back(getRoot());
1440 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1442 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1447 case Intrinsic::dbg_func_start: {
1448 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1449 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1450 if (DebugInfo && FSI.getSubprogram() &&
1451 DebugInfo->Verify(FSI.getSubprogram())) {
1452 std::vector<SDOperand> Ops;
1454 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1456 Ops.push_back(getRoot());
1457 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1459 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1464 case Intrinsic::dbg_declare: {
1465 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1466 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1467 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1468 std::vector<SDOperand> Ops;
1470 SDOperand AddressOp = getValue(DI.getAddress());
1471 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
1472 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1479 case Intrinsic::isunordered_f32:
1480 case Intrinsic::isunordered_f64:
1481 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1482 getValue(I.getOperand(2)), ISD::SETUO));
1485 case Intrinsic::sqrt_f32:
1486 case Intrinsic::sqrt_f64:
1487 setValue(&I, DAG.getNode(ISD::FSQRT,
1488 getValue(I.getOperand(1)).getValueType(),
1489 getValue(I.getOperand(1))));
1491 case Intrinsic::pcmarker: {
1492 SDOperand Tmp = getValue(I.getOperand(1));
1493 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1496 case Intrinsic::readcyclecounter: {
1497 std::vector<MVT::ValueType> VTs;
1498 VTs.push_back(MVT::i64);
1499 VTs.push_back(MVT::Other);
1500 std::vector<SDOperand> Ops;
1501 Ops.push_back(getRoot());
1502 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
1504 DAG.setRoot(Tmp.getValue(1));
1507 case Intrinsic::bswap_i16:
1508 case Intrinsic::bswap_i32:
1509 case Intrinsic::bswap_i64:
1510 setValue(&I, DAG.getNode(ISD::BSWAP,
1511 getValue(I.getOperand(1)).getValueType(),
1512 getValue(I.getOperand(1))));
1514 case Intrinsic::cttz_i8:
1515 case Intrinsic::cttz_i16:
1516 case Intrinsic::cttz_i32:
1517 case Intrinsic::cttz_i64:
1518 setValue(&I, DAG.getNode(ISD::CTTZ,
1519 getValue(I.getOperand(1)).getValueType(),
1520 getValue(I.getOperand(1))));
1522 case Intrinsic::ctlz_i8:
1523 case Intrinsic::ctlz_i16:
1524 case Intrinsic::ctlz_i32:
1525 case Intrinsic::ctlz_i64:
1526 setValue(&I, DAG.getNode(ISD::CTLZ,
1527 getValue(I.getOperand(1)).getValueType(),
1528 getValue(I.getOperand(1))));
1530 case Intrinsic::ctpop_i8:
1531 case Intrinsic::ctpop_i16:
1532 case Intrinsic::ctpop_i32:
1533 case Intrinsic::ctpop_i64:
1534 setValue(&I, DAG.getNode(ISD::CTPOP,
1535 getValue(I.getOperand(1)).getValueType(),
1536 getValue(I.getOperand(1))));
1538 case Intrinsic::stacksave: {
1539 std::vector<MVT::ValueType> VTs;
1540 VTs.push_back(TLI.getPointerTy());
1541 VTs.push_back(MVT::Other);
1542 std::vector<SDOperand> Ops;
1543 Ops.push_back(getRoot());
1544 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
1546 DAG.setRoot(Tmp.getValue(1));
1549 case Intrinsic::stackrestore: {
1550 SDOperand Tmp = getValue(I.getOperand(1));
1551 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1554 case Intrinsic::prefetch:
1555 // FIXME: Currently discarding prefetches.
1561 void SelectionDAGLowering::visitCall(CallInst &I) {
1562 const char *RenameFn = 0;
1563 if (Function *F = I.getCalledFunction()) {
1564 if (F->isExternal())
1565 if (unsigned IID = F->getIntrinsicID()) {
1566 RenameFn = visitIntrinsicCall(I, IID);
1569 } else { // Not an LLVM intrinsic.
1570 const std::string &Name = F->getName();
1571 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1572 if (I.getNumOperands() == 3 && // Basic sanity checks.
1573 I.getOperand(1)->getType()->isFloatingPoint() &&
1574 I.getType() == I.getOperand(1)->getType() &&
1575 I.getType() == I.getOperand(2)->getType()) {
1576 SDOperand LHS = getValue(I.getOperand(1));
1577 SDOperand RHS = getValue(I.getOperand(2));
1578 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1582 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1583 if (I.getNumOperands() == 2 && // Basic sanity checks.
1584 I.getOperand(1)->getType()->isFloatingPoint() &&
1585 I.getType() == I.getOperand(1)->getType()) {
1586 SDOperand Tmp = getValue(I.getOperand(1));
1587 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1590 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1591 if (I.getNumOperands() == 2 && // Basic sanity checks.
1592 I.getOperand(1)->getType()->isFloatingPoint() &&
1593 I.getType() == I.getOperand(1)->getType()) {
1594 SDOperand Tmp = getValue(I.getOperand(1));
1595 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1598 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1599 if (I.getNumOperands() == 2 && // Basic sanity checks.
1600 I.getOperand(1)->getType()->isFloatingPoint() &&
1601 I.getType() == I.getOperand(1)->getType()) {
1602 SDOperand Tmp = getValue(I.getOperand(1));
1603 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1608 } else if (isa<InlineAsm>(I.getOperand(0))) {
1615 Callee = getValue(I.getOperand(0));
1617 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1618 std::vector<std::pair<SDOperand, const Type*> > Args;
1619 Args.reserve(I.getNumOperands());
1620 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1621 Value *Arg = I.getOperand(i);
1622 SDOperand ArgNode = getValue(Arg);
1623 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1626 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1627 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1629 std::pair<SDOperand,SDOperand> Result =
1630 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1631 I.isTailCall(), Callee, Args, DAG);
1632 if (I.getType() != Type::VoidTy)
1633 setValue(&I, Result.first);
1634 DAG.setRoot(Result.second);
1637 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1638 SDOperand &Chain, SDOperand &Flag)const{
1639 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1640 Chain = Val.getValue(1);
1641 Flag = Val.getValue(2);
1643 // If the result was expanded, copy from the top part.
1644 if (Regs.size() > 1) {
1645 assert(Regs.size() == 2 &&
1646 "Cannot expand to more than 2 elts yet!");
1647 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1648 Chain = Val.getValue(1);
1649 Flag = Val.getValue(2);
1650 if (DAG.getTargetLoweringInfo().isLittleEndian())
1651 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1653 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1656 // Otherwise, if the return value was promoted, truncate it to the
1657 // appropriate type.
1658 if (RegVT == ValueVT)
1661 if (MVT::isInteger(RegVT))
1662 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1664 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1667 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1668 /// specified value into the registers specified by this object. This uses
1669 /// Chain/Flag as the input and updates them for the output Chain/Flag.
1670 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1671 SDOperand &Chain, SDOperand &Flag) const {
1672 if (Regs.size() == 1) {
1673 // If there is a single register and the types differ, this must be
1675 if (RegVT != ValueVT) {
1676 if (MVT::isInteger(RegVT))
1677 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1679 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1681 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1682 Flag = Chain.getValue(1);
1684 std::vector<unsigned> R(Regs);
1685 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1686 std::reverse(R.begin(), R.end());
1688 for (unsigned i = 0, e = R.size(); i != e; ++i) {
1689 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1690 DAG.getConstant(i, MVT::i32));
1691 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1692 Flag = Chain.getValue(1);
1697 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1698 /// operand list. This adds the code marker and includes the number of
1699 /// values added into it.
1700 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1701 std::vector<SDOperand> &Ops) const {
1702 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1703 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1704 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1707 /// isAllocatableRegister - If the specified register is safe to allocate,
1708 /// i.e. it isn't a stack pointer or some other special register, return the
1709 /// register class for the register. Otherwise, return null.
1710 static const TargetRegisterClass *
1711 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1712 const TargetLowering &TLI, const MRegisterInfo *MRI) {
1713 MVT::ValueType FoundVT = MVT::Other;
1714 const TargetRegisterClass *FoundRC = 0;
1715 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1716 E = MRI->regclass_end(); RCI != E; ++RCI) {
1717 MVT::ValueType ThisVT = MVT::Other;
1719 const TargetRegisterClass *RC = *RCI;
1720 // If none of the the value types for this register class are valid, we
1721 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1722 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1724 if (TLI.isTypeLegal(*I)) {
1725 // If we have already found this register in a different register class,
1726 // choose the one with the largest VT specified. For example, on
1727 // PowerPC, we favor f64 register classes over f32.
1728 if (FoundVT == MVT::Other ||
1729 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1736 if (ThisVT == MVT::Other) continue;
1738 // NOTE: This isn't ideal. In particular, this might allocate the
1739 // frame pointer in functions that need it (due to them not being taken
1740 // out of allocation, because a variable sized allocation hasn't been seen
1741 // yet). This is a slight code pessimization, but should still work.
1742 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1743 E = RC->allocation_order_end(MF); I != E; ++I)
1745 // We found a matching register class. Keep looking at others in case
1746 // we find one with larger registers that this physreg is also in.
1755 RegsForValue SelectionDAGLowering::
1756 GetRegistersForValue(const std::string &ConstrCode,
1757 MVT::ValueType VT, bool isOutReg, bool isInReg,
1758 std::set<unsigned> &OutputRegs,
1759 std::set<unsigned> &InputRegs) {
1760 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1761 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1762 std::vector<unsigned> Regs;
1764 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1765 MVT::ValueType RegVT;
1766 MVT::ValueType ValueVT = VT;
1768 if (PhysReg.first) {
1769 if (VT == MVT::Other)
1770 ValueVT = *PhysReg.second->vt_begin();
1773 // This is a explicit reference to a physical register.
1774 Regs.push_back(PhysReg.first);
1776 // If this is an expanded reference, add the rest of the regs to Regs.
1778 RegVT = *PhysReg.second->vt_begin();
1779 TargetRegisterClass::iterator I = PhysReg.second->begin();
1780 TargetRegisterClass::iterator E = PhysReg.second->end();
1781 for (; *I != PhysReg.first; ++I)
1782 assert(I != E && "Didn't find reg!");
1784 // Already added the first reg.
1786 for (; NumRegs; --NumRegs, ++I) {
1787 assert(I != E && "Ran out of registers to allocate!");
1791 return RegsForValue(Regs, RegVT, ValueVT);
1794 // This is a reference to a register class. Allocate NumRegs consecutive,
1795 // available, registers from the class.
1796 std::vector<unsigned> RegClassRegs =
1797 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1799 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1800 MachineFunction &MF = *CurMBB->getParent();
1801 unsigned NumAllocated = 0;
1802 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1803 unsigned Reg = RegClassRegs[i];
1804 // See if this register is available.
1805 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1806 (isInReg && InputRegs.count(Reg))) { // Already used.
1807 // Make sure we find consecutive registers.
1812 // Check to see if this register is allocatable (i.e. don't give out the
1814 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1816 // Make sure we find consecutive registers.
1821 // Okay, this register is good, we can use it.
1824 // If we allocated enough consecutive
1825 if (NumAllocated == NumRegs) {
1826 unsigned RegStart = (i-NumAllocated)+1;
1827 unsigned RegEnd = i+1;
1828 // Mark all of the allocated registers used.
1829 for (unsigned i = RegStart; i != RegEnd; ++i) {
1830 unsigned Reg = RegClassRegs[i];
1831 Regs.push_back(Reg);
1832 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1833 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1836 return RegsForValue(Regs, *RC->vt_begin(), VT);
1840 // Otherwise, we couldn't allocate enough registers for this.
1841 return RegsForValue();
1845 /// visitInlineAsm - Handle a call to an InlineAsm object.
1847 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1848 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1850 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1853 // Note, we treat inline asms both with and without side-effects as the same.
1854 // If an inline asm doesn't have side effects and doesn't access memory, we
1855 // could not choose to not chain it.
1856 bool hasSideEffects = IA->hasSideEffects();
1858 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
1859 std::vector<MVT::ValueType> ConstraintVTs;
1861 /// AsmNodeOperands - A list of pairs. The first element is a register, the
1862 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
1863 /// if it is a def of that register.
1864 std::vector<SDOperand> AsmNodeOperands;
1865 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
1866 AsmNodeOperands.push_back(AsmStr);
1868 SDOperand Chain = getRoot();
1871 // We fully assign registers here at isel time. This is not optimal, but
1872 // should work. For register classes that correspond to LLVM classes, we
1873 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
1874 // over the constraints, collecting fixed registers that we know we can't use.
1875 std::set<unsigned> OutputRegs, InputRegs;
1877 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
1878 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
1879 std::string &ConstraintCode = Constraints[i].Codes[0];
1881 MVT::ValueType OpVT;
1883 // Compute the value type for each operand and add it to ConstraintVTs.
1884 switch (Constraints[i].Type) {
1885 case InlineAsm::isOutput:
1886 if (!Constraints[i].isIndirectOutput) {
1887 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
1888 OpVT = TLI.getValueType(I.getType());
1890 const Type *OpTy = I.getOperand(OpNum)->getType();
1891 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
1892 OpNum++; // Consumes a call operand.
1895 case InlineAsm::isInput:
1896 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
1897 OpNum++; // Consumes a call operand.
1899 case InlineAsm::isClobber:
1904 ConstraintVTs.push_back(OpVT);
1906 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
1907 continue; // Not assigned a fixed reg.
1909 // Build a list of regs that this operand uses. This always has a single
1910 // element for promoted/expanded operands.
1911 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
1913 OutputRegs, InputRegs);
1915 switch (Constraints[i].Type) {
1916 case InlineAsm::isOutput:
1917 // We can't assign any other output to this register.
1918 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
1919 // If this is an early-clobber output, it cannot be assigned to the same
1920 // value as the input reg.
1921 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
1922 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
1924 case InlineAsm::isInput:
1925 // We can't assign any other input to this register.
1926 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
1928 case InlineAsm::isClobber:
1929 // Clobbered regs cannot be used as inputs or outputs.
1930 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
1931 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
1936 // Loop over all of the inputs, copying the operand values into the
1937 // appropriate registers and processing the output regs.
1938 RegsForValue RetValRegs;
1939 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
1942 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
1943 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
1944 std::string &ConstraintCode = Constraints[i].Codes[0];
1946 switch (Constraints[i].Type) {
1947 case InlineAsm::isOutput: {
1948 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
1949 if (ConstraintCode.size() == 1) // not a physreg name.
1950 CTy = TLI.getConstraintType(ConstraintCode[0]);
1952 if (CTy == TargetLowering::C_Memory) {
1954 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
1956 // Check that the operand (the address to store to) isn't a float.
1957 if (!MVT::isInteger(InOperandVal.getValueType()))
1958 assert(0 && "MATCH FAIL!");
1960 if (!Constraints[i].isIndirectOutput)
1961 assert(0 && "MATCH FAIL!");
1963 OpNum++; // Consumes a call operand.
1965 // Extend/truncate to the right pointer type if needed.
1966 MVT::ValueType PtrType = TLI.getPointerTy();
1967 if (InOperandVal.getValueType() < PtrType)
1968 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
1969 else if (InOperandVal.getValueType() > PtrType)
1970 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
1972 // Add information to the INLINEASM node to know about this output.
1973 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
1974 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
1975 AsmNodeOperands.push_back(InOperandVal);
1979 // Otherwise, this is a register output.
1980 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
1982 // If this is an early-clobber output, or if there is an input
1983 // constraint that matches this, we need to reserve the input register
1984 // so no other inputs allocate to it.
1985 bool UsesInputRegister = false;
1986 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
1987 UsesInputRegister = true;
1989 // Copy the output from the appropriate register. Find a register that
1992 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
1993 true, UsesInputRegister,
1994 OutputRegs, InputRegs);
1995 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
1997 if (!Constraints[i].isIndirectOutput) {
1998 assert(RetValRegs.Regs.empty() &&
1999 "Cannot have multiple output constraints yet!");
2000 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2003 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2004 I.getOperand(OpNum)));
2005 OpNum++; // Consumes a call operand.
2008 // Add information to the INLINEASM node to know that this register is
2010 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2013 case InlineAsm::isInput: {
2014 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2015 OpNum++; // Consumes a call operand.
2017 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2018 // If this is required to match an output register we have already set,
2019 // just use its register.
2020 unsigned OperandNo = atoi(ConstraintCode.c_str());
2022 // Scan until we find the definition we already emitted of this operand.
2023 // When we find it, create a RegsForValue operand.
2024 unsigned CurOp = 2; // The first operand.
2025 for (; OperandNo; --OperandNo) {
2026 // Advance to the next operand.
2028 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2029 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2030 "Skipped past definitions?");
2031 CurOp += (NumOps>>3)+1;
2035 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2036 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2037 "Skipped past definitions?");
2039 // Add NumOps>>3 registers to MatchedRegs.
2040 RegsForValue MatchedRegs;
2041 MatchedRegs.ValueVT = InOperandVal.getValueType();
2042 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2043 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2044 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2045 MatchedRegs.Regs.push_back(Reg);
2048 // Use the produced MatchedRegs object to
2049 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2050 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2054 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2055 if (ConstraintCode.size() == 1) // not a physreg name.
2056 CTy = TLI.getConstraintType(ConstraintCode[0]);
2058 if (CTy == TargetLowering::C_Other) {
2059 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2060 assert(0 && "MATCH FAIL!");
2062 // Add information to the INLINEASM node to know about this input.
2063 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2064 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2065 AsmNodeOperands.push_back(InOperandVal);
2067 } else if (CTy == TargetLowering::C_Memory) {
2070 // Check that the operand isn't a float.
2071 if (!MVT::isInteger(InOperandVal.getValueType()))
2072 assert(0 && "MATCH FAIL!");
2074 // Extend/truncate to the right pointer type if needed.
2075 MVT::ValueType PtrType = TLI.getPointerTy();
2076 if (InOperandVal.getValueType() < PtrType)
2077 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2078 else if (InOperandVal.getValueType() > PtrType)
2079 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2081 // Add information to the INLINEASM node to know about this input.
2082 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2083 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2084 AsmNodeOperands.push_back(InOperandVal);
2088 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2090 // Copy the input into the appropriate registers.
2091 RegsForValue InRegs =
2092 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2093 false, true, OutputRegs, InputRegs);
2094 // FIXME: should be match fail.
2095 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2097 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2099 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2102 case InlineAsm::isClobber: {
2103 RegsForValue ClobberedRegs =
2104 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2105 OutputRegs, InputRegs);
2106 // Add the clobbered value to the operand list, so that the register
2107 // allocator is aware that the physreg got clobbered.
2108 if (!ClobberedRegs.Regs.empty())
2109 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2115 // Finish up input operands.
2116 AsmNodeOperands[0] = Chain;
2117 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2119 std::vector<MVT::ValueType> VTs;
2120 VTs.push_back(MVT::Other);
2121 VTs.push_back(MVT::Flag);
2122 Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
2123 Flag = Chain.getValue(1);
2125 // If this asm returns a register value, copy the result from that register
2126 // and set it as the value of the call.
2127 if (!RetValRegs.Regs.empty())
2128 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2130 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2132 // Process indirect outputs, first output all of the flagged copies out of
2134 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2135 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2136 Value *Ptr = IndirectStoresToEmit[i].second;
2137 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2138 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2141 // Emit the non-flagged stores from the physregs.
2142 std::vector<SDOperand> OutChains;
2143 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2144 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2145 StoresToEmit[i].first,
2146 getValue(StoresToEmit[i].second),
2147 DAG.getSrcValue(StoresToEmit[i].second)));
2148 if (!OutChains.empty())
2149 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
2154 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2155 SDOperand Src = getValue(I.getOperand(0));
2157 MVT::ValueType IntPtr = TLI.getPointerTy();
2159 if (IntPtr < Src.getValueType())
2160 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2161 else if (IntPtr > Src.getValueType())
2162 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2164 // Scale the source by the type size.
2165 uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType());
2166 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2167 Src, getIntPtrConstant(ElementSize));
2169 std::vector<std::pair<SDOperand, const Type*> > Args;
2170 Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
2172 std::pair<SDOperand,SDOperand> Result =
2173 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2174 DAG.getExternalSymbol("malloc", IntPtr),
2176 setValue(&I, Result.first); // Pointers always fit in registers
2177 DAG.setRoot(Result.second);
2180 void SelectionDAGLowering::visitFree(FreeInst &I) {
2181 std::vector<std::pair<SDOperand, const Type*> > Args;
2182 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2183 TLI.getTargetData().getIntPtrType()));
2184 MVT::ValueType IntPtr = TLI.getPointerTy();
2185 std::pair<SDOperand,SDOperand> Result =
2186 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2187 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2188 DAG.setRoot(Result.second);
2191 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2192 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2193 // instructions are special in various ways, which require special support to
2194 // insert. The specified MachineInstr is created but not inserted into any
2195 // basic blocks, and the scheduler passes ownership of it to this method.
2196 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2197 MachineBasicBlock *MBB) {
2198 std::cerr << "If a target marks an instruction with "
2199 "'usesCustomDAGSchedInserter', it must implement "
2200 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2205 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2206 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2207 getValue(I.getOperand(1)),
2208 DAG.getSrcValue(I.getOperand(1))));
2211 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2212 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2213 getValue(I.getOperand(0)),
2214 DAG.getSrcValue(I.getOperand(0)));
2216 DAG.setRoot(V.getValue(1));
2219 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2220 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2221 getValue(I.getOperand(1)),
2222 DAG.getSrcValue(I.getOperand(1))));
2225 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2226 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2227 getValue(I.getOperand(1)),
2228 getValue(I.getOperand(2)),
2229 DAG.getSrcValue(I.getOperand(1)),
2230 DAG.getSrcValue(I.getOperand(2))));
2233 /// TargetLowering::LowerArguments - This is the default LowerArguments
2234 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2235 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be removed.
2236 std::vector<SDOperand>
2237 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2238 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2239 std::vector<SDOperand> Ops;
2240 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2241 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2243 // Add one result value for each formal argument.
2244 std::vector<MVT::ValueType> RetVals;
2245 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2246 MVT::ValueType VT = getValueType(I->getType());
2248 switch (getTypeAction(VT)) {
2249 default: assert(0 && "Unknown type action!");
2251 RetVals.push_back(VT);
2254 RetVals.push_back(getTypeToTransformTo(VT));
2257 if (VT != MVT::Vector) {
2258 // If this is a large integer, it needs to be broken up into small
2259 // integers. Figure out what the destination type is and how many small
2260 // integers it turns into.
2261 MVT::ValueType NVT = getTypeToTransformTo(VT);
2262 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2263 for (unsigned i = 0; i != NumVals; ++i)
2264 RetVals.push_back(NVT);
2266 // Otherwise, this is a vector type. We only support legal vectors
2268 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2269 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2271 // Figure out if there is a Packed type corresponding to this Vector
2272 // type. If so, convert to the packed type.
2273 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2274 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2275 RetVals.push_back(TVT);
2277 assert(0 && "Don't support illegal by-val vector arguments yet!");
2285 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
2287 // Set up the return result vector.
2290 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2291 MVT::ValueType VT = getValueType(I->getType());
2293 switch (getTypeAction(VT)) {
2294 default: assert(0 && "Unknown type action!");
2296 Ops.push_back(SDOperand(Result, i++));
2299 SDOperand Op(Result, i++);
2300 if (MVT::isInteger(VT)) {
2301 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2303 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2304 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2306 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2307 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2313 if (VT != MVT::Vector) {
2314 // If this is a large integer, it needs to be reassembled from small
2315 // integers. Figure out what the source elt type is and how many small
2317 MVT::ValueType NVT = getTypeToTransformTo(VT);
2318 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2320 SDOperand Lo = SDOperand(Result, i++);
2321 SDOperand Hi = SDOperand(Result, i++);
2323 if (!isLittleEndian())
2326 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2328 // Value scalarized into many values. Unimp for now.
2329 assert(0 && "Cannot expand i64 -> i16 yet!");
2332 // Otherwise, this is a vector type. We only support legal vectors
2334 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2335 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2337 // Figure out if there is a Packed type corresponding to this Vector
2338 // type. If so, convert to the packed type.
2339 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2340 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2341 Ops.push_back(SDOperand(Result, i++));
2343 assert(0 && "Don't support illegal by-val vector arguments yet!");
2352 // It is always conservatively correct for llvm.returnaddress and
2353 // llvm.frameaddress to return 0.
2354 std::pair<SDOperand, SDOperand>
2355 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2356 unsigned Depth, SelectionDAG &DAG) {
2357 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2360 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2361 assert(0 && "LowerOperation not implemented for this target!");
2366 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2367 SelectionDAG &DAG) {
2368 assert(0 && "CustomPromoteOperation not implemented for this target!");
2373 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2374 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2375 std::pair<SDOperand,SDOperand> Result =
2376 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2377 setValue(&I, Result.first);
2378 DAG.setRoot(Result.second);
2381 /// getMemsetValue - Vectorized representation of the memset value
2383 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2384 SelectionDAG &DAG) {
2385 MVT::ValueType CurVT = VT;
2386 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2387 uint64_t Val = C->getValue() & 255;
2389 while (CurVT != MVT::i8) {
2390 Val = (Val << Shift) | Val;
2392 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2394 return DAG.getConstant(Val, VT);
2396 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2398 while (CurVT != MVT::i8) {
2400 DAG.getNode(ISD::OR, VT,
2401 DAG.getNode(ISD::SHL, VT, Value,
2402 DAG.getConstant(Shift, MVT::i8)), Value);
2404 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2411 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2412 /// used when a memcpy is turned into a memset when the source is a constant
2414 static SDOperand getMemsetStringVal(MVT::ValueType VT,
2415 SelectionDAG &DAG, TargetLowering &TLI,
2416 std::string &Str, unsigned Offset) {
2417 MVT::ValueType CurVT = VT;
2419 unsigned MSB = getSizeInBits(VT) / 8;
2420 if (TLI.isLittleEndian())
2421 Offset = Offset + MSB - 1;
2422 for (unsigned i = 0; i != MSB; ++i) {
2423 Val = (Val << 8) | Str[Offset];
2424 Offset += TLI.isLittleEndian() ? -1 : 1;
2426 return DAG.getConstant(Val, VT);
2429 /// getMemBasePlusOffset - Returns base and offset node for the
2430 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2431 SelectionDAG &DAG, TargetLowering &TLI) {
2432 MVT::ValueType VT = Base.getValueType();
2433 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2436 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2437 /// to replace the memset / memcpy is below the threshold. It also returns the
2438 /// types of the sequence of memory ops to perform memset / memcpy.
2439 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2440 unsigned Limit, uint64_t Size,
2441 unsigned Align, TargetLowering &TLI) {
2444 if (TLI.allowsUnalignedMemoryAccesses()) {
2447 switch (Align & 7) {
2463 MVT::ValueType LVT = MVT::i64;
2464 while (!TLI.isTypeLegal(LVT))
2465 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2466 assert(MVT::isInteger(LVT));
2471 unsigned NumMemOps = 0;
2473 unsigned VTSize = getSizeInBits(VT) / 8;
2474 while (VTSize > Size) {
2475 VT = (MVT::ValueType)((unsigned)VT - 1);
2478 assert(MVT::isInteger(VT));
2480 if (++NumMemOps > Limit)
2482 MemOps.push_back(VT);
2489 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2490 SDOperand Op1 = getValue(I.getOperand(1));
2491 SDOperand Op2 = getValue(I.getOperand(2));
2492 SDOperand Op3 = getValue(I.getOperand(3));
2493 SDOperand Op4 = getValue(I.getOperand(4));
2494 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2495 if (Align == 0) Align = 1;
2497 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2498 std::vector<MVT::ValueType> MemOps;
2500 // Expand memset / memcpy to a series of load / store ops
2501 // if the size operand falls below a certain threshold.
2502 std::vector<SDOperand> OutChains;
2504 default: break; // Do nothing for now.
2506 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2507 Size->getValue(), Align, TLI)) {
2508 unsigned NumMemOps = MemOps.size();
2509 unsigned Offset = 0;
2510 for (unsigned i = 0; i < NumMemOps; i++) {
2511 MVT::ValueType VT = MemOps[i];
2512 unsigned VTSize = getSizeInBits(VT) / 8;
2513 SDOperand Value = getMemsetValue(Op2, VT, DAG);
2514 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
2516 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2517 DAG.getSrcValue(I.getOperand(1), Offset));
2518 OutChains.push_back(Store);
2525 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2526 Size->getValue(), Align, TLI)) {
2527 unsigned NumMemOps = MemOps.size();
2528 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2529 GlobalAddressSDNode *G = NULL;
2531 bool CopyFromStr = false;
2533 if (Op2.getOpcode() == ISD::GlobalAddress)
2534 G = cast<GlobalAddressSDNode>(Op2);
2535 else if (Op2.getOpcode() == ISD::ADD &&
2536 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2537 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2538 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2539 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2542 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2544 Str = GV->getStringValue(false);
2552 for (unsigned i = 0; i < NumMemOps; i++) {
2553 MVT::ValueType VT = MemOps[i];
2554 unsigned VTSize = getSizeInBits(VT) / 8;
2555 SDOperand Value, Chain, Store;
2558 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2561 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2562 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2563 DAG.getSrcValue(I.getOperand(1), DstOff));
2565 Value = DAG.getLoad(VT, getRoot(),
2566 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2567 DAG.getSrcValue(I.getOperand(2), SrcOff));
2568 Chain = Value.getValue(1);
2570 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2571 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2572 DAG.getSrcValue(I.getOperand(1), DstOff));
2574 OutChains.push_back(Store);
2583 if (!OutChains.empty()) {
2584 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
2589 std::vector<SDOperand> Ops;
2590 Ops.push_back(getRoot());
2595 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
2598 //===----------------------------------------------------------------------===//
2599 // SelectionDAGISel code
2600 //===----------------------------------------------------------------------===//
2602 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2603 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2606 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2607 // FIXME: we only modify the CFG to split critical edges. This
2608 // updates dom and loop info.
2612 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
2613 /// casting to the type of GEPI.
2614 static Value *InsertGEPComputeCode(Value *&V, BasicBlock *BB, Instruction *GEPI,
2615 Value *Ptr, Value *PtrOffset) {
2616 if (V) return V; // Already computed.
2618 BasicBlock::iterator InsertPt;
2619 if (BB == GEPI->getParent()) {
2620 // If insert into the GEP's block, insert right after the GEP.
2624 // Otherwise, insert at the top of BB, after any PHI nodes
2625 InsertPt = BB->begin();
2626 while (isa<PHINode>(InsertPt)) ++InsertPt;
2629 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
2630 // BB so that there is only one value live across basic blocks (the cast
2632 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
2633 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
2634 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
2636 // Add the offset, cast it to the right type.
2637 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
2638 Ptr = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
2643 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
2644 /// selection, we want to be a bit careful about some things. In particular, if
2645 /// we have a GEP instruction that is used in a different block than it is
2646 /// defined, the addressing expression of the GEP cannot be folded into loads or
2647 /// stores that use it. In this case, decompose the GEP and move constant
2648 /// indices into blocks that use it.
2649 static void OptimizeGEPExpression(GetElementPtrInst *GEPI,
2650 const TargetData &TD) {
2651 // If this GEP is only used inside the block it is defined in, there is no
2652 // need to rewrite it.
2653 bool isUsedOutsideDefBB = false;
2654 BasicBlock *DefBB = GEPI->getParent();
2655 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
2657 if (cast<Instruction>(*UI)->getParent() != DefBB) {
2658 isUsedOutsideDefBB = true;
2662 if (!isUsedOutsideDefBB) return;
2664 // If this GEP has no non-zero constant indices, there is nothing we can do,
2666 bool hasConstantIndex = false;
2667 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
2668 E = GEPI->op_end(); OI != E; ++OI) {
2669 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI))
2670 if (CI->getRawValue()) {
2671 hasConstantIndex = true;
2675 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
2676 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0))) return;
2678 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
2679 // constant offset (which we now know is non-zero) and deal with it later.
2680 uint64_t ConstantOffset = 0;
2681 const Type *UIntPtrTy = TD.getIntPtrType();
2682 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
2683 const Type *Ty = GEPI->getOperand(0)->getType();
2685 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
2686 E = GEPI->op_end(); OI != E; ++OI) {
2688 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2689 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
2691 ConstantOffset += TD.getStructLayout(StTy)->MemberOffsets[Field];
2692 Ty = StTy->getElementType(Field);
2694 Ty = cast<SequentialType>(Ty)->getElementType();
2696 // Handle constant subscripts.
2697 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2698 if (CI->getRawValue() == 0) continue;
2700 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
2701 ConstantOffset += (int64_t)TD.getTypeSize(Ty)*CSI->getValue();
2703 ConstantOffset+=TD.getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
2707 // Ptr = Ptr + Idx * ElementSize;
2709 // Cast Idx to UIntPtrTy if needed.
2710 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
2712 uint64_t ElementSize = TD.getTypeSize(Ty);
2713 // Mask off bits that should not be set.
2714 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
2715 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
2717 // Multiply by the element size and add to the base.
2718 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
2719 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
2723 // Make sure that the offset fits in uintptr_t.
2724 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
2725 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
2727 // Okay, we have now emitted all of the variable index parts to the BB that
2728 // the GEP is defined in. Loop over all of the using instructions, inserting
2729 // an "add Ptr, ConstantOffset" into each block that uses it and update the
2730 // instruction to use the newly computed value, making GEPI dead. When the
2731 // user is a load or store instruction address, we emit the add into the user
2732 // block, otherwise we use a canonical version right next to the gep (these
2733 // won't be foldable as addresses, so we might as well share the computation).
2735 std::map<BasicBlock*,Value*> InsertedExprs;
2736 while (!GEPI->use_empty()) {
2737 Instruction *User = cast<Instruction>(GEPI->use_back());
2739 // If this use is not foldable into the addressing mode, use a version
2740 // emitted in the GEP block.
2742 if (!isa<LoadInst>(User) &&
2743 (!isa<StoreInst>(User) || User->getOperand(0) == GEPI)) {
2744 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
2747 // Otherwise, insert the code in the User's block so it can be folded into
2748 // any users in that block.
2749 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
2750 User->getParent(), GEPI,
2753 User->replaceUsesOfWith(GEPI, NewVal);
2756 // Finally, the GEP is dead, remove it.
2757 GEPI->eraseFromParent();
2760 bool SelectionDAGISel::runOnFunction(Function &Fn) {
2761 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
2762 RegMap = MF.getSSARegMap();
2763 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
2765 // First, split all critical edges for PHI nodes with incoming values that are
2766 // constants, this way the load of the constant into a vreg will not be placed
2767 // into MBBs that are used some other way.
2769 // In this pass we also look for GEP instructions that are used across basic
2770 // blocks and rewrites them to improve basic-block-at-a-time selection.
2772 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
2774 BasicBlock::iterator BBI;
2775 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
2776 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
2777 if (isa<Constant>(PN->getIncomingValue(i)))
2778 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
2780 for (BasicBlock::iterator E = BB->end(); BBI != E; )
2781 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(BBI++))
2782 OptimizeGEPExpression(GEPI, TLI.getTargetData());
2785 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
2787 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
2788 SelectBasicBlock(I, MF, FuncInfo);
2794 SDOperand SelectionDAGISel::
2795 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
2796 SDOperand Op = SDL.getValue(V);
2797 assert((Op.getOpcode() != ISD::CopyFromReg ||
2798 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
2799 "Copy from a reg to the same reg!");
2801 // If this type is not legal, we must make sure to not create an invalid
2803 MVT::ValueType SrcVT = Op.getValueType();
2804 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
2805 SelectionDAG &DAG = SDL.DAG;
2806 if (SrcVT == DestVT) {
2807 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
2808 } else if (SrcVT == MVT::Vector) {
2809 // Handle copies from generic vectors to registers.
2810 MVT::ValueType PTyElementVT, PTyLegalElementVT;
2811 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
2812 PTyElementVT, PTyLegalElementVT);
2814 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
2815 // MVT::Vector type.
2816 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
2817 DAG.getConstant(NE, MVT::i32),
2818 DAG.getValueType(PTyElementVT));
2820 // Loop over all of the elements of the resultant vector,
2821 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
2822 // copying them into output registers.
2823 std::vector<SDOperand> OutChains;
2824 SDOperand Root = SDL.getRoot();
2825 for (unsigned i = 0; i != NE; ++i) {
2826 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
2827 Op, DAG.getConstant(i, MVT::i32));
2828 if (PTyElementVT == PTyLegalElementVT) {
2829 // Elements are legal.
2830 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
2831 } else if (PTyLegalElementVT > PTyElementVT) {
2832 // Elements are promoted.
2833 if (MVT::isFloatingPoint(PTyLegalElementVT))
2834 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
2836 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
2837 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
2839 // Elements are expanded.
2840 // The src value is expanded into multiple registers.
2841 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
2842 Elt, DAG.getConstant(0, MVT::i32));
2843 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
2844 Elt, DAG.getConstant(1, MVT::i32));
2845 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
2846 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
2849 return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
2850 } else if (SrcVT < DestVT) {
2851 // The src value is promoted to the register.
2852 if (MVT::isFloatingPoint(SrcVT))
2853 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
2855 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
2856 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
2858 // The src value is expanded into multiple registers.
2859 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
2860 Op, DAG.getConstant(0, MVT::i32));
2861 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
2862 Op, DAG.getConstant(1, MVT::i32));
2863 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
2864 return DAG.getCopyToReg(Op, Reg+1, Hi);
2868 void SelectionDAGISel::
2869 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
2870 std::vector<SDOperand> &UnorderedChains) {
2871 // If this is the entry block, emit arguments.
2872 Function &F = *BB->getParent();
2873 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
2874 SDOperand OldRoot = SDL.DAG.getRoot();
2875 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
2878 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
2880 if (!AI->use_empty()) {
2881 SDL.setValue(AI, Args[a]);
2883 // If this argument is live outside of the entry block, insert a copy from
2884 // whereever we got it to the vreg that other BB's will reference it as.
2885 if (FuncInfo.ValueMap.count(AI)) {
2887 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
2888 UnorderedChains.push_back(Copy);
2892 // Next, if the function has live ins that need to be copied into vregs,
2893 // emit the copies now, into the top of the block.
2894 MachineFunction &MF = SDL.DAG.getMachineFunction();
2895 if (MF.livein_begin() != MF.livein_end()) {
2896 SSARegMap *RegMap = MF.getSSARegMap();
2897 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
2898 for (MachineFunction::livein_iterator LI = MF.livein_begin(),
2899 E = MF.livein_end(); LI != E; ++LI)
2901 MRI.copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
2902 LI->first, RegMap->getRegClass(LI->second));
2905 // Finally, if the target has anything special to do, allow it to do so.
2906 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
2910 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
2911 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
2912 FunctionLoweringInfo &FuncInfo) {
2913 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
2915 std::vector<SDOperand> UnorderedChains;
2917 // Lower any arguments needed in this block if this is the entry block.
2918 if (LLVMBB == &LLVMBB->getParent()->front())
2919 LowerArguments(LLVMBB, SDL, UnorderedChains);
2921 BB = FuncInfo.MBBMap[LLVMBB];
2922 SDL.setCurrentBasicBlock(BB);
2924 // Lower all of the non-terminator instructions.
2925 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
2929 // Ensure that all instructions which are used outside of their defining
2930 // blocks are available as virtual registers.
2931 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
2932 if (!I->use_empty() && !isa<PHINode>(I)) {
2933 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
2934 if (VMI != FuncInfo.ValueMap.end())
2935 UnorderedChains.push_back(
2936 CopyValueToVirtualRegister(SDL, I, VMI->second));
2939 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
2940 // ensure constants are generated when needed. Remember the virtual registers
2941 // that need to be added to the Machine PHI nodes as input. We cannot just
2942 // directly add them, because expansion might result in multiple MBB's for one
2943 // BB. As such, the start of the BB might correspond to a different MBB than
2947 // Emit constants only once even if used by multiple PHI nodes.
2948 std::map<Constant*, unsigned> ConstantsOut;
2950 // Check successor nodes PHI nodes that expect a constant to be available from
2952 TerminatorInst *TI = LLVMBB->getTerminator();
2953 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
2954 BasicBlock *SuccBB = TI->getSuccessor(succ);
2955 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
2958 // At this point we know that there is a 1-1 correspondence between LLVM PHI
2959 // nodes and Machine PHI nodes, but the incoming operands have not been
2961 for (BasicBlock::iterator I = SuccBB->begin();
2962 (PN = dyn_cast<PHINode>(I)); ++I)
2963 if (!PN->use_empty()) {
2965 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
2966 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
2967 unsigned &RegOut = ConstantsOut[C];
2969 RegOut = FuncInfo.CreateRegForValue(C);
2970 UnorderedChains.push_back(
2971 CopyValueToVirtualRegister(SDL, C, RegOut));
2975 Reg = FuncInfo.ValueMap[PHIOp];
2977 assert(isa<AllocaInst>(PHIOp) &&
2978 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
2979 "Didn't codegen value into a register!??");
2980 Reg = FuncInfo.CreateRegForValue(PHIOp);
2981 UnorderedChains.push_back(
2982 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
2986 // Remember that this register needs to added to the machine PHI node as
2987 // the input for this MBB.
2988 MVT::ValueType VT = TLI.getValueType(PN->getType());
2989 unsigned NumElements;
2990 if (VT != MVT::Vector)
2991 NumElements = TLI.getNumElements(VT);
2993 MVT::ValueType VT1,VT2;
2995 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
2998 for (unsigned i = 0, e = NumElements; i != e; ++i)
2999 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3002 ConstantsOut.clear();
3004 // Turn all of the unordered chains into one factored node.
3005 if (!UnorderedChains.empty()) {
3006 SDOperand Root = SDL.getRoot();
3007 if (Root.getOpcode() != ISD::EntryToken) {
3008 unsigned i = 0, e = UnorderedChains.size();
3009 for (; i != e; ++i) {
3010 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3011 if (UnorderedChains[i].Val->getOperand(0) == Root)
3012 break; // Don't add the root if we already indirectly depend on it.
3016 UnorderedChains.push_back(Root);
3018 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
3021 // Lower the terminator after the copies are emitted.
3022 SDL.visit(*LLVMBB->getTerminator());
3024 // Copy over any CaseBlock records that may now exist due to SwitchInst
3026 SwitchCases.clear();
3027 SwitchCases = SDL.SwitchCases;
3029 // Make sure the root of the DAG is up-to-date.
3030 DAG.setRoot(SDL.getRoot());
3033 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3034 // Run the DAG combiner in pre-legalize mode.
3037 DEBUG(std::cerr << "Lowered selection DAG:\n");
3040 // Second step, hack on the DAG until it only uses operations and types that
3041 // the target supports.
3044 DEBUG(std::cerr << "Legalized selection DAG:\n");
3047 // Run the DAG combiner in post-legalize mode.
3050 if (ViewISelDAGs) DAG.viewGraph();
3052 // Third, instruction select all of the operations to machine code, adding the
3053 // code to the MachineBasicBlock.
3054 InstructionSelectBasicBlock(DAG);
3056 DEBUG(std::cerr << "Selected machine code:\n");
3060 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3061 FunctionLoweringInfo &FuncInfo) {
3062 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3064 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3067 // First step, lower LLVM code to some DAG. This DAG may use operations and
3068 // types that are not supported by the target.
3069 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3071 // Second step, emit the lowered DAG as machine code.
3072 CodeGenAndEmitDAG(DAG);
3075 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3076 // PHI nodes in successors.
3077 if (SwitchCases.empty()) {
3078 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3079 MachineInstr *PHI = PHINodesToUpdate[i].first;
3080 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3081 "This is not a machine PHI node that we are updating!");
3082 PHI->addRegOperand(PHINodesToUpdate[i].second);
3083 PHI->addMachineBasicBlockOperand(BB);
3088 // If we generated any switch lowering information, build and codegen any
3089 // additional DAGs necessary.
3090 for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3091 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3093 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3094 // Set the current basic block to the mbb we wish to insert the code into
3095 BB = SwitchCases[i].ThisBB;
3096 SDL.setCurrentBasicBlock(BB);
3098 SDL.visitSwitchCase(SwitchCases[i]);
3099 SDAG.setRoot(SDL.getRoot());
3100 CodeGenAndEmitDAG(SDAG);
3101 // Iterate over the phi nodes, if there is a phi node in a successor of this
3102 // block (for instance, the default block), then add a pair of operands to
3103 // the phi node for this block, as if we were coming from the original
3104 // BB before switch expansion.
3105 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3106 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3107 MachineBasicBlock *PHIBB = PHI->getParent();
3108 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3109 "This is not a machine PHI node that we are updating!");
3110 if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
3111 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3112 PHI->addMachineBasicBlockOperand(BB);
3118 //===----------------------------------------------------------------------===//
3119 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3120 /// target node in the graph.
3121 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3122 if (ViewSchedDAGs) DAG.viewGraph();
3123 ScheduleDAG *SL = NULL;
3125 switch (ISHeuristic) {
3126 default: assert(0 && "Unrecognized scheduling heuristic");
3127 case defaultScheduling:
3128 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
3129 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3131 assert(TLI.getSchedulingPreference() ==
3132 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
3133 SL = createBURRListDAGScheduler(DAG, BB);
3137 SL = createBFS_DAGScheduler(DAG, BB);
3139 case simpleScheduling:
3140 SL = createSimpleDAGScheduler(false, DAG, BB);
3142 case simpleNoItinScheduling:
3143 SL = createSimpleDAGScheduler(true, DAG, BB);
3145 case listSchedulingBURR:
3146 SL = createBURRListDAGScheduler(DAG, BB);
3148 case listSchedulingTD:
3149 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3156 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3157 return new HazardRecognizer();
3160 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3161 /// by tblgen. Others should not call it.
3162 void SelectionDAGISel::
3163 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3164 std::vector<SDOperand> InOps;
3165 std::swap(InOps, Ops);
3167 Ops.push_back(InOps[0]); // input chain.
3168 Ops.push_back(InOps[1]); // input asm string.
3170 const char *AsmStr = cast<ExternalSymbolSDNode>(InOps[1])->getSymbol();
3171 unsigned i = 2, e = InOps.size();
3172 if (InOps[e-1].getValueType() == MVT::Flag)
3173 --e; // Don't process a flag operand if it is here.
3176 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3177 if ((Flags & 7) != 4 /*MEM*/) {
3178 // Just skip over this operand, copying the operands verbatim.
3179 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3180 i += (Flags >> 3) + 1;
3182 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3183 // Otherwise, this is a memory operand. Ask the target to select it.
3184 std::vector<SDOperand> SelOps;
3185 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3186 std::cerr << "Could not match memory address. Inline asm failure!\n";
3190 // Add this to the output node.
3191 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3192 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3197 // Add the flag input back if present.
3198 if (e != InOps.size())
3199 Ops.push_back(InOps.back());