1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/CFG.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/DebugInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/LLVMContext.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLibraryInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
64 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
65 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
66 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
68 STATISTIC(NumFastIselFailLowerArguments,
69 "Number of entry blocks where fast isel failed to lower arguments");
73 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
74 cl::desc("Enable extra verbose messages in the \"fast\" "
75 "instruction selector"));
78 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
79 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
80 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
81 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
82 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
83 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
84 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
86 // Standard binary operators...
87 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
88 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
89 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
90 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
91 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
92 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
93 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
94 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
95 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
96 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
97 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
98 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
100 // Logical operators...
101 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
102 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
103 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
105 // Memory instructions...
106 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
107 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
108 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
109 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
110 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
111 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
112 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
114 // Convert instructions...
115 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
116 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
117 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
118 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
119 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
120 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
121 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
122 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
123 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
124 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
125 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
126 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
128 // Other instructions...
129 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
130 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
131 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
132 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
133 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
134 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
135 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
136 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
137 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
138 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
139 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
140 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
141 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
142 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
143 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
148 cl::desc("Enable verbose messages in the \"fast\" "
149 "instruction selector"));
151 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
152 cl::desc("Enable abort calls when \"fast\" instruction selection "
153 "fails to lower an instruction"));
155 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
156 cl::desc("Enable abort calls when \"fast\" instruction selection "
157 "fails to lower a formal argument"));
161 cl::desc("use Machine Branch Probability Info"),
162 cl::init(true), cl::Hidden);
166 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the first "
168 "dag combine pass"));
170 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before legalize types"));
173 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
174 cl::desc("Pop up a window to show dags before legalize"));
176 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
177 cl::desc("Pop up a window to show dags before the second "
178 "dag combine pass"));
180 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
181 cl::desc("Pop up a window to show dags before the post legalize types"
182 " dag combine pass"));
184 ViewISelDAGs("view-isel-dags", cl::Hidden,
185 cl::desc("Pop up a window to show isel dags as they are selected"));
187 ViewSchedDAGs("view-sched-dags", cl::Hidden,
188 cl::desc("Pop up a window to show sched dags as they are processed"));
190 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
191 cl::desc("Pop up a window to show SUnit dags after they are processed"));
193 static const bool ViewDAGCombine1 = false,
194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
195 ViewDAGCombine2 = false,
196 ViewDAGCombineLT = false,
197 ViewISelDAGs = false, ViewSchedDAGs = false,
198 ViewSUnitDAGs = false;
201 //===---------------------------------------------------------------------===//
203 /// RegisterScheduler class - Track the registration of instruction schedulers.
205 //===---------------------------------------------------------------------===//
206 MachinePassRegistry RegisterScheduler::Registry;
208 //===---------------------------------------------------------------------===//
210 /// ISHeuristic command line option for instruction schedulers.
212 //===---------------------------------------------------------------------===//
213 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
214 RegisterPassParser<RegisterScheduler> >
215 ISHeuristic("pre-RA-sched",
216 cl::init(&createDefaultScheduler),
217 cl::desc("Instruction schedulers available (before register"
220 static RegisterScheduler
221 defaultListDAGScheduler("default", "Best scheduler for the target",
222 createDefaultScheduler);
225 //===--------------------------------------------------------------------===//
226 /// \brief This class is used by SelectionDAGISel to temporarily override
227 /// the optimization level on a per-function basis.
228 class OptLevelChanger {
229 SelectionDAGISel &IS;
230 CodeGenOpt::Level SavedOptLevel;
234 OptLevelChanger(SelectionDAGISel &ISel,
235 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
236 SavedOptLevel = IS.OptLevel;
237 if (NewOptLevel == SavedOptLevel)
239 IS.OptLevel = NewOptLevel;
240 IS.TM.setOptLevel(NewOptLevel);
241 SavedFastISel = IS.TM.Options.EnableFastISel;
242 if (NewOptLevel == CodeGenOpt::None)
243 IS.TM.setFastISel(true);
244 DEBUG(dbgs() << "\nChanging optimization level for Function "
245 << IS.MF->getFunction()->getName() << "\n");
246 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
247 << " ; After: -O" << NewOptLevel << "\n");
251 if (IS.OptLevel == SavedOptLevel)
253 DEBUG(dbgs() << "\nRestoring optimization level for Function "
254 << IS.MF->getFunction()->getName() << "\n");
255 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
256 << " ; After: -O" << SavedOptLevel << "\n");
257 IS.OptLevel = SavedOptLevel;
258 IS.TM.setOptLevel(SavedOptLevel);
259 IS.TM.setFastISel(SavedFastISel);
263 //===--------------------------------------------------------------------===//
264 /// createDefaultScheduler - This creates an instruction scheduler appropriate
266 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
267 CodeGenOpt::Level OptLevel) {
268 const TargetLowering *TLI = IS->getTargetLowering();
269 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
271 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
272 TLI->getSchedulingPreference() == Sched::Source)
273 return createSourceListDAGScheduler(IS, OptLevel);
274 if (TLI->getSchedulingPreference() == Sched::RegPressure)
275 return createBURRListDAGScheduler(IS, OptLevel);
276 if (TLI->getSchedulingPreference() == Sched::Hybrid)
277 return createHybridListDAGScheduler(IS, OptLevel);
278 if (TLI->getSchedulingPreference() == Sched::VLIW)
279 return createVLIWDAGScheduler(IS, OptLevel);
280 assert(TLI->getSchedulingPreference() == Sched::ILP &&
281 "Unknown sched type!");
282 return createILPListDAGScheduler(IS, OptLevel);
286 // EmitInstrWithCustomInserter - This method should be implemented by targets
287 // that mark instructions with the 'usesCustomInserter' flag. These
288 // instructions are special in various ways, which require special support to
289 // insert. The specified MachineInstr is created but not inserted into any
290 // basic blocks, and this method is called to expand it into a sequence of
291 // instructions, potentially also creating new basic blocks and control flow.
292 // When new basic blocks are inserted and the edges from MBB to its successors
293 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
296 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
297 MachineBasicBlock *MBB) const {
299 dbgs() << "If a target marks an instruction with "
300 "'usesCustomInserter', it must implement "
301 "TargetLowering::EmitInstrWithCustomInserter!";
306 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
307 SDNode *Node) const {
308 assert(!MI->hasPostISelHook() &&
309 "If a target marks an instruction with 'hasPostISelHook', "
310 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
313 //===----------------------------------------------------------------------===//
314 // SelectionDAGISel code
315 //===----------------------------------------------------------------------===//
317 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
318 CodeGenOpt::Level OL) :
319 MachineFunctionPass(ID), TM(tm),
320 FuncInfo(new FunctionLoweringInfo(TM)),
321 CurDAG(new SelectionDAG(tm, OL)),
322 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
326 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
327 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
328 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
329 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
332 SelectionDAGISel::~SelectionDAGISel() {
338 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
339 AU.addRequired<AliasAnalysis>();
340 AU.addPreserved<AliasAnalysis>();
341 AU.addRequired<GCModuleInfo>();
342 AU.addPreserved<GCModuleInfo>();
343 AU.addRequired<TargetLibraryInfo>();
344 if (UseMBPI && OptLevel != CodeGenOpt::None)
345 AU.addRequired<BranchProbabilityInfo>();
346 MachineFunctionPass::getAnalysisUsage(AU);
349 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
350 /// may trap on it. In this case we have to split the edge so that the path
351 /// through the predecessor block that doesn't go to the phi block doesn't
352 /// execute the possibly trapping instruction.
354 /// This is required for correctness, so it must be done at -O0.
356 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
357 // Loop for blocks with phi nodes.
358 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
359 PHINode *PN = dyn_cast<PHINode>(BB->begin());
360 if (PN == 0) continue;
363 // For each block with a PHI node, check to see if any of the input values
364 // are potentially trapping constant expressions. Constant expressions are
365 // the only potentially trapping value that can occur as the argument to a
367 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
368 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
369 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
370 if (CE == 0 || !CE->canTrap()) continue;
372 // The only case we have to worry about is when the edge is critical.
373 // Since this block has a PHI Node, we assume it has multiple input
374 // edges: check to see if the pred has multiple successors.
375 BasicBlock *Pred = PN->getIncomingBlock(i);
376 if (Pred->getTerminator()->getNumSuccessors() == 1)
379 // Okay, we have to split this edge.
380 SplitCriticalEdge(Pred->getTerminator(),
381 GetSuccessorNumber(Pred, BB), SDISel, true);
387 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
388 // Do some sanity-checking on the command-line options.
389 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
390 "-fast-isel-verbose requires -fast-isel");
391 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
392 "-fast-isel-abort requires -fast-isel");
394 const Function &Fn = *mf.getFunction();
395 const TargetInstrInfo &TII = *TM.getInstrInfo();
396 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
397 const TargetLowering *TLI = TM.getTargetLowering();
400 RegInfo = &MF->getRegInfo();
401 AA = &getAnalysis<AliasAnalysis>();
402 LibInfo = &getAnalysis<TargetLibraryInfo>();
403 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
404 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
406 TargetSubtargetInfo &ST =
407 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
408 ST.resetSubtargetFeatures(MF);
409 TM.resetTargetOptions(MF);
411 // Reset OptLevel to None for optnone functions.
412 CodeGenOpt::Level NewOptLevel = OptLevel;
413 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
414 NewOptLevel = CodeGenOpt::None;
415 OptLevelChanger OLC(*this, NewOptLevel);
417 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
419 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
421 CurDAG->init(*MF, TTI, TLI);
422 FuncInfo->set(Fn, *MF);
424 if (UseMBPI && OptLevel != CodeGenOpt::None)
425 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
429 SDB->init(GFI, *AA, LibInfo);
431 MF->setHasMSInlineAsm(false);
432 SelectAllBasicBlocks(Fn);
434 // If the first basic block in the function has live ins that need to be
435 // copied into vregs, emit the copies into the top of the block before
436 // emitting the code for the block.
437 MachineBasicBlock *EntryMBB = MF->begin();
438 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
440 DenseMap<unsigned, unsigned> LiveInMap;
441 if (!FuncInfo->ArgDbgValues.empty())
442 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
443 E = RegInfo->livein_end(); LI != E; ++LI)
445 LiveInMap.insert(std::make_pair(LI->first, LI->second));
447 // Insert DBG_VALUE instructions for function arguments to the entry block.
448 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
449 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
450 bool hasFI = MI->getOperand(0).isFI();
452 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
453 if (TargetRegisterInfo::isPhysicalRegister(Reg))
454 EntryMBB->insert(EntryMBB->begin(), MI);
456 MachineInstr *Def = RegInfo->getVRegDef(Reg);
458 MachineBasicBlock::iterator InsertPos = Def;
459 // FIXME: VR def may not be in entry block.
460 Def->getParent()->insert(llvm::next(InsertPos), MI);
462 DEBUG(dbgs() << "Dropping debug info for dead vreg"
463 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
466 // If Reg is live-in then update debug info to track its copy in a vreg.
467 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
468 if (LDI != LiveInMap.end()) {
469 assert(!hasFI && "There's no handling of frame pointer updating here yet "
471 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
472 MachineBasicBlock::iterator InsertPos = Def;
473 const MDNode *Variable =
474 MI->getOperand(MI->getNumOperands()-1).getMetadata();
475 bool IsIndirect = MI->isIndirectDebugValue();
476 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
477 // Def is never a terminator here, so it is ok to increment InsertPos.
478 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
479 TII.get(TargetOpcode::DBG_VALUE),
481 LDI->second, Offset, Variable);
483 // If this vreg is directly copied into an exported register then
484 // that COPY instructions also need DBG_VALUE, if it is the only
485 // user of LDI->second.
486 MachineInstr *CopyUseMI = NULL;
487 for (MachineRegisterInfo::use_iterator
488 UI = RegInfo->use_begin(LDI->second);
489 MachineInstr *UseMI = UI.skipInstruction();) {
490 if (UseMI->isDebugValue()) continue;
491 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
492 CopyUseMI = UseMI; continue;
494 // Otherwise this is another use or second copy use.
495 CopyUseMI = NULL; break;
498 MachineInstr *NewMI =
499 BuildMI(*MF, CopyUseMI->getDebugLoc(),
500 TII.get(TargetOpcode::DBG_VALUE),
502 CopyUseMI->getOperand(0).getReg(),
504 MachineBasicBlock::iterator Pos = CopyUseMI;
505 EntryMBB->insertAfter(Pos, NewMI);
510 // Determine if there are any calls in this machine function.
511 MachineFrameInfo *MFI = MF->getFrameInfo();
512 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
515 if (MFI->hasCalls() && MF->hasMSInlineAsm())
518 const MachineBasicBlock *MBB = I;
519 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
521 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
522 if ((MCID.isCall() && !MCID.isReturn()) ||
523 II->isStackAligningInlineAsm()) {
524 MFI->setHasCalls(true);
526 if (II->isMSInlineAsm()) {
527 MF->setHasMSInlineAsm(true);
532 // Determine if there is a call to setjmp in the machine function.
533 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
535 // Replace forward-declared registers with the registers containing
536 // the desired value.
537 MachineRegisterInfo &MRI = MF->getRegInfo();
538 for (DenseMap<unsigned, unsigned>::iterator
539 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
541 unsigned From = I->first;
542 unsigned To = I->second;
543 // If To is also scheduled to be replaced, find what its ultimate
546 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
550 // Make sure the new register has a sufficiently constrained register class.
551 if (TargetRegisterInfo::isVirtualRegister(From) &&
552 TargetRegisterInfo::isVirtualRegister(To))
553 MRI.constrainRegClass(To, MRI.getRegClass(From));
555 MRI.replaceRegWith(From, To);
558 // Freeze the set of reserved registers now that MachineFrameInfo has been
559 // set up. All the information required by getReservedRegs() should be
561 MRI.freezeReservedRegs(*MF);
563 // Release function-specific state. SDB and CurDAG are already cleared
570 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
571 BasicBlock::const_iterator End,
573 // Lower all of the non-terminator instructions. If a call is emitted
574 // as a tail call, cease emitting nodes for this block. Terminators
575 // are handled below.
576 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
579 // Make sure the root of the DAG is up-to-date.
580 CurDAG->setRoot(SDB->getControlRoot());
581 HadTailCall = SDB->HasTailCall;
584 // Final step, emit the lowered DAG as machine code.
588 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
589 SmallPtrSet<SDNode*, 128> VisitedNodes;
590 SmallVector<SDNode*, 128> Worklist;
592 Worklist.push_back(CurDAG->getRoot().getNode());
598 SDNode *N = Worklist.pop_back_val();
600 // If we've already seen this node, ignore it.
601 if (!VisitedNodes.insert(N))
604 // Otherwise, add all chain operands to the worklist.
605 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
606 if (N->getOperand(i).getValueType() == MVT::Other)
607 Worklist.push_back(N->getOperand(i).getNode());
609 // If this is a CopyToReg with a vreg dest, process it.
610 if (N->getOpcode() != ISD::CopyToReg)
613 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
614 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
617 // Ignore non-scalar or non-integer values.
618 SDValue Src = N->getOperand(2);
619 EVT SrcVT = Src.getValueType();
620 if (!SrcVT.isInteger() || SrcVT.isVector())
623 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
624 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
625 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
626 } while (!Worklist.empty());
629 void SelectionDAGISel::CodeGenAndEmitDAG() {
630 std::string GroupName;
631 if (TimePassesIsEnabled)
632 GroupName = "Instruction Selection and Scheduling";
633 std::string BlockName;
634 int BlockNumber = -1;
637 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
638 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
642 BlockNumber = FuncInfo->MBB->getNumber();
643 BlockName = MF->getName().str() + ":" +
644 FuncInfo->MBB->getBasicBlock()->getName().str();
646 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
647 << " '" << BlockName << "'\n"; CurDAG->dump());
649 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
651 // Run the DAG combiner in pre-legalize mode.
653 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
654 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
657 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
658 << " '" << BlockName << "'\n"; CurDAG->dump());
660 // Second step, hack on the DAG until it only uses operations and types that
661 // the target supports.
662 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
667 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
668 Changed = CurDAG->LegalizeTypes();
671 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
672 << " '" << BlockName << "'\n"; CurDAG->dump());
674 CurDAG->NewNodesMustHaveLegalTypes = true;
677 if (ViewDAGCombineLT)
678 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
680 // Run the DAG combiner in post-type-legalize mode.
682 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
683 TimePassesIsEnabled);
684 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
687 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
688 << " '" << BlockName << "'\n"; CurDAG->dump());
693 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
694 Changed = CurDAG->LegalizeVectors();
699 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
700 CurDAG->LegalizeTypes();
703 if (ViewDAGCombineLT)
704 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
706 // Run the DAG combiner in post-type-legalize mode.
708 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
709 TimePassesIsEnabled);
710 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
713 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
714 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
717 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
720 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
724 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
725 << " '" << BlockName << "'\n"; CurDAG->dump());
727 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
729 // Run the DAG combiner in post-legalize mode.
731 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
732 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
735 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
736 << " '" << BlockName << "'\n"; CurDAG->dump());
738 if (OptLevel != CodeGenOpt::None)
739 ComputeLiveOutVRegInfo();
741 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
743 // Third, instruction select all of the operations to machine code, adding the
744 // code to the MachineBasicBlock.
746 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
747 DoInstructionSelection();
750 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
751 << " '" << BlockName << "'\n"; CurDAG->dump());
753 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
755 // Schedule machine code.
756 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
758 NamedRegionTimer T("Instruction Scheduling", GroupName,
759 TimePassesIsEnabled);
760 Scheduler->Run(CurDAG, FuncInfo->MBB);
763 if (ViewSUnitDAGs) Scheduler->viewGraph();
765 // Emit machine code to BB. This can change 'BB' to the last block being
767 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
769 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
771 // FuncInfo->InsertPt is passed by reference and set to the end of the
772 // scheduled instructions.
773 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
776 // If the block was split, make sure we update any references that are used to
777 // update PHI nodes later on.
778 if (FirstMBB != LastMBB)
779 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
781 // Free the scheduler state.
783 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
784 TimePassesIsEnabled);
788 // Free the SelectionDAG state, now that we're finished with it.
793 /// ISelUpdater - helper class to handle updates of the instruction selection
795 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
796 SelectionDAG::allnodes_iterator &ISelPosition;
798 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
799 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
801 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
802 /// deleted is the current ISelPosition node, update ISelPosition.
804 virtual void NodeDeleted(SDNode *N, SDNode *E) {
805 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
809 } // end anonymous namespace
811 void SelectionDAGISel::DoInstructionSelection() {
812 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
813 << FuncInfo->MBB->getNumber()
814 << " '" << FuncInfo->MBB->getName() << "'\n");
818 // Select target instructions for the DAG.
820 // Number all nodes with a topological order and set DAGSize.
821 DAGSize = CurDAG->AssignTopologicalOrder();
823 // Create a dummy node (which is not added to allnodes), that adds
824 // a reference to the root node, preventing it from being deleted,
825 // and tracking any changes of the root.
826 HandleSDNode Dummy(CurDAG->getRoot());
827 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
830 // Make sure that ISelPosition gets properly updated when nodes are deleted
831 // in calls made from this function.
832 ISelUpdater ISU(*CurDAG, ISelPosition);
834 // The AllNodes list is now topological-sorted. Visit the
835 // nodes by starting at the end of the list (the root of the
836 // graph) and preceding back toward the beginning (the entry
838 while (ISelPosition != CurDAG->allnodes_begin()) {
839 SDNode *Node = --ISelPosition;
840 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
841 // but there are currently some corner cases that it misses. Also, this
842 // makes it theoretically possible to disable the DAGCombiner.
843 if (Node->use_empty())
846 SDNode *ResNode = Select(Node);
848 // FIXME: This is pretty gross. 'Select' should be changed to not return
849 // anything at all and this code should be nuked with a tactical strike.
851 // If node should not be replaced, continue with the next one.
852 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
856 ReplaceUses(Node, ResNode);
859 // If after the replacement this node is not used any more,
860 // remove this dead node.
861 if (Node->use_empty()) // Don't delete EntryToken, etc.
862 CurDAG->RemoveDeadNode(Node);
865 CurDAG->setRoot(Dummy.getValue());
868 DEBUG(dbgs() << "===== Instruction selection ends:\n");
870 PostprocessISelDAG();
873 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
874 /// do other setup for EH landing-pad blocks.
875 void SelectionDAGISel::PrepareEHLandingPad() {
876 MachineBasicBlock *MBB = FuncInfo->MBB;
878 // Add a label to mark the beginning of the landing pad. Deletion of the
879 // landing pad can thus be detected via the MachineModuleInfo.
880 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
882 // Assign the call site to the landing pad's begin label.
883 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
885 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
886 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
889 // Mark exception register as live in.
890 const TargetLowering *TLI = getTargetLowering();
891 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
892 if (unsigned Reg = TLI->getExceptionPointerRegister())
893 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
895 // Mark exception selector register as live in.
896 if (unsigned Reg = TLI->getExceptionSelectorRegister())
897 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
900 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
901 /// side-effect free and is either dead or folded into a generated instruction.
902 /// Return false if it needs to be emitted.
903 static bool isFoldedOrDeadInstruction(const Instruction *I,
904 FunctionLoweringInfo *FuncInfo) {
905 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
906 !isa<TerminatorInst>(I) && // Terminators aren't folded.
907 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
908 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
909 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
913 // Collect per Instruction statistics for fast-isel misses. Only those
914 // instructions that cause the bail are accounted for. It does not account for
915 // instructions higher in the block. Thus, summing the per instructions stats
916 // will not add up to what is reported by NumFastIselFailures.
917 static void collectFailStats(const Instruction *I) {
918 switch (I->getOpcode()) {
919 default: assert (0 && "<Invalid operator> ");
922 case Instruction::Ret: NumFastIselFailRet++; return;
923 case Instruction::Br: NumFastIselFailBr++; return;
924 case Instruction::Switch: NumFastIselFailSwitch++; return;
925 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
926 case Instruction::Invoke: NumFastIselFailInvoke++; return;
927 case Instruction::Resume: NumFastIselFailResume++; return;
928 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
930 // Standard binary operators...
931 case Instruction::Add: NumFastIselFailAdd++; return;
932 case Instruction::FAdd: NumFastIselFailFAdd++; return;
933 case Instruction::Sub: NumFastIselFailSub++; return;
934 case Instruction::FSub: NumFastIselFailFSub++; return;
935 case Instruction::Mul: NumFastIselFailMul++; return;
936 case Instruction::FMul: NumFastIselFailFMul++; return;
937 case Instruction::UDiv: NumFastIselFailUDiv++; return;
938 case Instruction::SDiv: NumFastIselFailSDiv++; return;
939 case Instruction::FDiv: NumFastIselFailFDiv++; return;
940 case Instruction::URem: NumFastIselFailURem++; return;
941 case Instruction::SRem: NumFastIselFailSRem++; return;
942 case Instruction::FRem: NumFastIselFailFRem++; return;
944 // Logical operators...
945 case Instruction::And: NumFastIselFailAnd++; return;
946 case Instruction::Or: NumFastIselFailOr++; return;
947 case Instruction::Xor: NumFastIselFailXor++; return;
949 // Memory instructions...
950 case Instruction::Alloca: NumFastIselFailAlloca++; return;
951 case Instruction::Load: NumFastIselFailLoad++; return;
952 case Instruction::Store: NumFastIselFailStore++; return;
953 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
954 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
955 case Instruction::Fence: NumFastIselFailFence++; return;
956 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
958 // Convert instructions...
959 case Instruction::Trunc: NumFastIselFailTrunc++; return;
960 case Instruction::ZExt: NumFastIselFailZExt++; return;
961 case Instruction::SExt: NumFastIselFailSExt++; return;
962 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
963 case Instruction::FPExt: NumFastIselFailFPExt++; return;
964 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
965 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
966 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
967 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
968 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
969 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
970 case Instruction::BitCast: NumFastIselFailBitCast++; return;
972 // Other instructions...
973 case Instruction::ICmp: NumFastIselFailICmp++; return;
974 case Instruction::FCmp: NumFastIselFailFCmp++; return;
975 case Instruction::PHI: NumFastIselFailPHI++; return;
976 case Instruction::Select: NumFastIselFailSelect++; return;
977 case Instruction::Call: NumFastIselFailCall++; return;
978 case Instruction::Shl: NumFastIselFailShl++; return;
979 case Instruction::LShr: NumFastIselFailLShr++; return;
980 case Instruction::AShr: NumFastIselFailAShr++; return;
981 case Instruction::VAArg: NumFastIselFailVAArg++; return;
982 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
983 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
984 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
985 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
986 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
987 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
992 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
993 // Initialize the Fast-ISel state, if needed.
994 FastISel *FastIS = 0;
995 if (TM.Options.EnableFastISel)
996 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
998 // Iterate over all basic blocks in the function.
999 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1000 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1001 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1002 const BasicBlock *LLVMBB = *I;
1004 if (OptLevel != CodeGenOpt::None) {
1005 bool AllPredsVisited = true;
1006 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1008 if (!FuncInfo->VisitedBBs.count(*PI)) {
1009 AllPredsVisited = false;
1014 if (AllPredsVisited) {
1015 for (BasicBlock::const_iterator I = LLVMBB->begin();
1016 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1017 FuncInfo->ComputePHILiveOutRegInfo(PN);
1019 for (BasicBlock::const_iterator I = LLVMBB->begin();
1020 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1021 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1024 FuncInfo->VisitedBBs.insert(LLVMBB);
1027 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1028 BasicBlock::const_iterator const End = LLVMBB->end();
1029 BasicBlock::const_iterator BI = End;
1031 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1032 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1034 // Setup an EH landing-pad block.
1035 FuncInfo->ExceptionPointerVirtReg = 0;
1036 FuncInfo->ExceptionSelectorVirtReg = 0;
1037 if (FuncInfo->MBB->isLandingPad())
1038 PrepareEHLandingPad();
1040 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1042 FastIS->startNewBlock();
1044 // Emit code for any incoming arguments. This must happen before
1045 // beginning FastISel on the entry block.
1046 if (LLVMBB == &Fn.getEntryBlock()) {
1049 // Lower any arguments needed in this block if this is the entry block.
1050 if (!FastIS->LowerArguments()) {
1051 // Fast isel failed to lower these arguments
1052 ++NumFastIselFailLowerArguments;
1053 if (EnableFastISelAbortArgs)
1054 llvm_unreachable("FastISel didn't lower all arguments");
1056 // Use SelectionDAG argument lowering
1058 CurDAG->setRoot(SDB->getControlRoot());
1060 CodeGenAndEmitDAG();
1063 // If we inserted any instructions at the beginning, make a note of
1064 // where they are, so we can be sure to emit subsequent instructions
1066 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1067 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1069 FastIS->setLastLocalValue(0);
1072 unsigned NumFastIselRemaining = std::distance(Begin, End);
1073 // Do FastISel on as many instructions as possible.
1074 for (; BI != Begin; --BI) {
1075 const Instruction *Inst = llvm::prior(BI);
1077 // If we no longer require this instruction, skip it.
1078 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1079 --NumFastIselRemaining;
1083 // Bottom-up: reset the insert pos at the top, after any local-value
1085 FastIS->recomputeInsertPt();
1087 // Try to select the instruction with FastISel.
1088 if (FastIS->SelectInstruction(Inst)) {
1089 --NumFastIselRemaining;
1090 ++NumFastIselSuccess;
1091 // If fast isel succeeded, skip over all the folded instructions, and
1092 // then see if there is a load right before the selected instructions.
1093 // Try to fold the load if so.
1094 const Instruction *BeforeInst = Inst;
1095 while (BeforeInst != Begin) {
1096 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1097 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1100 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1101 BeforeInst->hasOneUse() &&
1102 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1103 // If we succeeded, don't re-select the load.
1104 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1105 --NumFastIselRemaining;
1106 ++NumFastIselSuccess;
1112 if (EnableFastISelVerbose2)
1113 collectFailStats(Inst);
1116 // Then handle certain instructions as single-LLVM-Instruction blocks.
1117 if (isa<CallInst>(Inst)) {
1119 if (EnableFastISelVerbose || EnableFastISelAbort) {
1120 dbgs() << "FastISel missed call: ";
1124 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1125 unsigned &R = FuncInfo->ValueMap[Inst];
1127 R = FuncInfo->CreateRegs(Inst->getType());
1130 bool HadTailCall = false;
1131 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1132 SelectBasicBlock(Inst, BI, HadTailCall);
1134 // If the call was emitted as a tail call, we're done with the block.
1135 // We also need to delete any previously emitted instructions.
1137 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1142 // Recompute NumFastIselRemaining as Selection DAG instruction
1143 // selection may have handled the call, input args, etc.
1144 unsigned RemainingNow = std::distance(Begin, BI);
1145 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1146 NumFastIselRemaining = RemainingNow;
1150 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1151 // Don't abort, and use a different message for terminator misses.
1152 NumFastIselFailures += NumFastIselRemaining;
1153 if (EnableFastISelVerbose || EnableFastISelAbort) {
1154 dbgs() << "FastISel missed terminator: ";
1158 NumFastIselFailures += NumFastIselRemaining;
1159 if (EnableFastISelVerbose || EnableFastISelAbort) {
1160 dbgs() << "FastISel miss: ";
1163 if (EnableFastISelAbort)
1164 // The "fast" selector couldn't handle something and bailed.
1165 // For the purpose of debugging, just abort.
1166 llvm_unreachable("FastISel didn't select the entire block");
1171 FastIS->recomputeInsertPt();
1173 // Lower any arguments needed in this block if this is the entry block.
1174 if (LLVMBB == &Fn.getEntryBlock()) {
1183 ++NumFastIselBlocks;
1186 // Run SelectionDAG instruction selection on the remainder of the block
1187 // not handled by FastISel. If FastISel is not run, this is the entire
1190 SelectBasicBlock(Begin, BI, HadTailCall);
1194 FuncInfo->PHINodesToUpdate.clear();
1198 SDB->clearDanglingDebugInfo();
1199 SDB->SPDescriptor.resetPerFunctionState();
1202 /// Given that the input MI is before a partial terminator sequence TSeq, return
1203 /// true if M + TSeq also a partial terminator sequence.
1205 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1206 /// lowering copy vregs into physical registers, which are then passed into
1207 /// terminator instructors so we can satisfy ABI constraints. A partial
1208 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1209 /// may be the whole terminator sequence).
1210 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1211 // If we do not have a copy or an implicit def, we return true if and only if
1212 // MI is a debug value.
1213 if (!MI->isCopy() && !MI->isImplicitDef())
1214 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1215 // physical registers if there is debug info associated with the terminator
1216 // of our mbb. We want to include said debug info in our terminator
1217 // sequence, so we return true in that case.
1218 return MI->isDebugValue();
1220 // We have left the terminator sequence if we are not doing one of the
1223 // 1. Copying a vreg into a physical register.
1224 // 2. Copying a vreg into a vreg.
1225 // 3. Defining a register via an implicit def.
1227 // OPI should always be a register definition...
1228 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1229 if (!OPI->isReg() || !OPI->isDef())
1232 // Defining any register via an implicit def is always ok.
1233 if (MI->isImplicitDef())
1236 // Grab the copy source...
1237 MachineInstr::const_mop_iterator OPI2 = OPI;
1239 assert(OPI2 != MI->operands_end()
1240 && "Should have a copy implying we should have 2 arguments.");
1242 // Make sure that the copy dest is not a vreg when the copy source is a
1243 // physical register.
1244 if (!OPI2->isReg() ||
1245 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1246 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1252 /// Find the split point at which to splice the end of BB into its success stack
1253 /// protector check machine basic block.
1255 /// On many platforms, due to ABI constraints, terminators, even before register
1256 /// allocation, use physical registers. This creates an issue for us since
1257 /// physical registers at this point can not travel across basic
1258 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1259 /// when they enter functions and moves them through a sequence of copies back
1260 /// into the physical registers right before the terminator creating a
1261 /// ``Terminator Sequence''. This function is searching for the beginning of the
1262 /// terminator sequence so that we can ensure that we splice off not just the
1263 /// terminator, but additionally the copies that move the vregs into the
1264 /// physical registers.
1265 static MachineBasicBlock::iterator
1266 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1267 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1269 if (SplitPoint == BB->begin())
1272 MachineBasicBlock::iterator Start = BB->begin();
1273 MachineBasicBlock::iterator Previous = SplitPoint;
1276 while (MIIsInTerminatorSequence(Previous)) {
1277 SplitPoint = Previous;
1278 if (Previous == Start)
1287 SelectionDAGISel::FinishBasicBlock() {
1289 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1290 << FuncInfo->PHINodesToUpdate.size() << "\n";
1291 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1292 dbgs() << "Node " << i << " : ("
1293 << FuncInfo->PHINodesToUpdate[i].first
1294 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1296 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1297 SDB->JTCases.empty() &&
1298 SDB->BitTestCases.empty();
1300 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1301 // PHI nodes in successors.
1302 if (MustUpdatePHINodes) {
1303 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1304 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1305 assert(PHI->isPHI() &&
1306 "This is not a machine PHI node that we are updating!");
1307 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1309 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1313 // Handle stack protector.
1314 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1315 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1316 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1318 // Find the split point to split the parent mbb. At the same time copy all
1319 // physical registers used in the tail of parent mbb into virtual registers
1320 // before the split point and back into physical registers after the split
1321 // point. This prevents us needing to deal with Live-ins and many other
1322 // register allocation issues caused by us splitting the parent mbb. The
1323 // register allocator will clean up said virtual copies later on.
1324 MachineBasicBlock::iterator SplitPoint =
1325 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1327 // Splice the terminator of ParentMBB into SuccessMBB.
1328 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1332 // Add compare/jump on neq/jump to the parent BB.
1333 FuncInfo->MBB = ParentMBB;
1334 FuncInfo->InsertPt = ParentMBB->end();
1335 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1336 CurDAG->setRoot(SDB->getRoot());
1338 CodeGenAndEmitDAG();
1340 // CodeGen Failure MBB if we have not codegened it yet.
1341 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1342 if (!FailureMBB->size()) {
1343 FuncInfo->MBB = FailureMBB;
1344 FuncInfo->InsertPt = FailureMBB->end();
1345 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1346 CurDAG->setRoot(SDB->getRoot());
1348 CodeGenAndEmitDAG();
1351 // Clear the Per-BB State.
1352 SDB->SPDescriptor.resetPerBBState();
1355 // If we updated PHI Nodes, return early.
1356 if (MustUpdatePHINodes)
1359 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1360 // Lower header first, if it wasn't already lowered
1361 if (!SDB->BitTestCases[i].Emitted) {
1362 // Set the current basic block to the mbb we wish to insert the code into
1363 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1364 FuncInfo->InsertPt = FuncInfo->MBB->end();
1366 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1367 CurDAG->setRoot(SDB->getRoot());
1369 CodeGenAndEmitDAG();
1372 uint32_t UnhandledWeight = 0;
1373 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1374 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1376 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1377 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1378 // Set the current basic block to the mbb we wish to insert the code into
1379 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1380 FuncInfo->InsertPt = FuncInfo->MBB->end();
1383 SDB->visitBitTestCase(SDB->BitTestCases[i],
1384 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1386 SDB->BitTestCases[i].Reg,
1387 SDB->BitTestCases[i].Cases[j],
1390 SDB->visitBitTestCase(SDB->BitTestCases[i],
1391 SDB->BitTestCases[i].Default,
1393 SDB->BitTestCases[i].Reg,
1394 SDB->BitTestCases[i].Cases[j],
1398 CurDAG->setRoot(SDB->getRoot());
1400 CodeGenAndEmitDAG();
1404 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1406 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1407 MachineBasicBlock *PHIBB = PHI->getParent();
1408 assert(PHI->isPHI() &&
1409 "This is not a machine PHI node that we are updating!");
1410 // This is "default" BB. We have two jumps to it. From "header" BB and
1411 // from last "case" BB.
1412 if (PHIBB == SDB->BitTestCases[i].Default)
1413 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1414 .addMBB(SDB->BitTestCases[i].Parent)
1415 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1416 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1417 // One of "cases" BB.
1418 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1420 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1421 if (cBB->isSuccessor(PHIBB))
1422 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1426 SDB->BitTestCases.clear();
1428 // If the JumpTable record is filled in, then we need to emit a jump table.
1429 // Updating the PHI nodes is tricky in this case, since we need to determine
1430 // whether the PHI is a successor of the range check MBB or the jump table MBB
1431 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1432 // Lower header first, if it wasn't already lowered
1433 if (!SDB->JTCases[i].first.Emitted) {
1434 // Set the current basic block to the mbb we wish to insert the code into
1435 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1436 FuncInfo->InsertPt = FuncInfo->MBB->end();
1438 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1440 CurDAG->setRoot(SDB->getRoot());
1442 CodeGenAndEmitDAG();
1445 // Set the current basic block to the mbb we wish to insert the code into
1446 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1447 FuncInfo->InsertPt = FuncInfo->MBB->end();
1449 SDB->visitJumpTable(SDB->JTCases[i].second);
1450 CurDAG->setRoot(SDB->getRoot());
1452 CodeGenAndEmitDAG();
1455 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1457 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1458 MachineBasicBlock *PHIBB = PHI->getParent();
1459 assert(PHI->isPHI() &&
1460 "This is not a machine PHI node that we are updating!");
1461 // "default" BB. We can go there only from header BB.
1462 if (PHIBB == SDB->JTCases[i].second.Default)
1463 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1464 .addMBB(SDB->JTCases[i].first.HeaderBB);
1465 // JT BB. Just iterate over successors here
1466 if (FuncInfo->MBB->isSuccessor(PHIBB))
1467 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1470 SDB->JTCases.clear();
1472 // If the switch block involved a branch to one of the actual successors, we
1473 // need to update PHI nodes in that block.
1474 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1475 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1476 assert(PHI->isPHI() &&
1477 "This is not a machine PHI node that we are updating!");
1478 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1479 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1482 // If we generated any switch lowering information, build and codegen any
1483 // additional DAGs necessary.
1484 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1485 // Set the current basic block to the mbb we wish to insert the code into
1486 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1487 FuncInfo->InsertPt = FuncInfo->MBB->end();
1489 // Determine the unique successors.
1490 SmallVector<MachineBasicBlock *, 2> Succs;
1491 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1492 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1493 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1495 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1496 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1497 CurDAG->setRoot(SDB->getRoot());
1499 CodeGenAndEmitDAG();
1501 // Remember the last block, now that any splitting is done, for use in
1502 // populating PHI nodes in successors.
1503 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1505 // Handle any PHI nodes in successors of this chunk, as if we were coming
1506 // from the original BB before switch expansion. Note that PHI nodes can
1507 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1508 // handle them the right number of times.
1509 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1510 FuncInfo->MBB = Succs[i];
1511 FuncInfo->InsertPt = FuncInfo->MBB->end();
1512 // FuncInfo->MBB may have been removed from the CFG if a branch was
1514 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1515 for (MachineBasicBlock::iterator
1516 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1517 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1518 MachineInstrBuilder PHI(*MF, MBBI);
1519 // This value for this PHI node is recorded in PHINodesToUpdate.
1520 for (unsigned pn = 0; ; ++pn) {
1521 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1522 "Didn't find PHI entry!");
1523 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1524 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1532 SDB->SwitchCases.clear();
1536 /// Create the scheduler. If a specific scheduler was specified
1537 /// via the SchedulerRegistry, use it, otherwise select the
1538 /// one preferred by the target.
1540 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1541 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1545 RegisterScheduler::setDefault(Ctor);
1548 return Ctor(this, OptLevel);
1551 //===----------------------------------------------------------------------===//
1552 // Helper functions used by the generated instruction selector.
1553 //===----------------------------------------------------------------------===//
1554 // Calls to these methods are generated by tblgen.
1556 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1557 /// the dag combiner simplified the 255, we still want to match. RHS is the
1558 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1559 /// specified in the .td file (e.g. 255).
1560 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1561 int64_t DesiredMaskS) const {
1562 const APInt &ActualMask = RHS->getAPIntValue();
1563 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1565 // If the actual mask exactly matches, success!
1566 if (ActualMask == DesiredMask)
1569 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1570 if (ActualMask.intersects(~DesiredMask))
1573 // Otherwise, the DAG Combiner may have proven that the value coming in is
1574 // either already zero or is not demanded. Check for known zero input bits.
1575 APInt NeededMask = DesiredMask & ~ActualMask;
1576 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1579 // TODO: check to see if missing bits are just not demanded.
1581 // Otherwise, this pattern doesn't match.
1585 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1586 /// the dag combiner simplified the 255, we still want to match. RHS is the
1587 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1588 /// specified in the .td file (e.g. 255).
1589 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1590 int64_t DesiredMaskS) const {
1591 const APInt &ActualMask = RHS->getAPIntValue();
1592 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1594 // If the actual mask exactly matches, success!
1595 if (ActualMask == DesiredMask)
1598 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1599 if (ActualMask.intersects(~DesiredMask))
1602 // Otherwise, the DAG Combiner may have proven that the value coming in is
1603 // either already zero or is not demanded. Check for known zero input bits.
1604 APInt NeededMask = DesiredMask & ~ActualMask;
1606 APInt KnownZero, KnownOne;
1607 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1609 // If all the missing bits in the or are already known to be set, match!
1610 if ((NeededMask & KnownOne) == NeededMask)
1613 // TODO: check to see if missing bits are just not demanded.
1615 // Otherwise, this pattern doesn't match.
1620 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1621 /// by tblgen. Others should not call it.
1622 void SelectionDAGISel::
1623 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1624 std::vector<SDValue> InOps;
1625 std::swap(InOps, Ops);
1627 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1628 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1629 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1630 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1632 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1633 if (InOps[e-1].getValueType() == MVT::Glue)
1634 --e; // Don't process a glue operand if it is here.
1637 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1638 if (!InlineAsm::isMemKind(Flags)) {
1639 // Just skip over this operand, copying the operands verbatim.
1640 Ops.insert(Ops.end(), InOps.begin()+i,
1641 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1642 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1644 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1645 "Memory operand with multiple values?");
1646 // Otherwise, this is a memory operand. Ask the target to select it.
1647 std::vector<SDValue> SelOps;
1648 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1649 report_fatal_error("Could not match memory address. Inline asm"
1652 // Add this to the output node.
1654 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1655 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1656 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1661 // Add the glue input back if present.
1662 if (e != InOps.size())
1663 Ops.push_back(InOps.back());
1666 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1669 static SDNode *findGlueUse(SDNode *N) {
1670 unsigned FlagResNo = N->getNumValues()-1;
1671 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1672 SDUse &Use = I.getUse();
1673 if (Use.getResNo() == FlagResNo)
1674 return Use.getUser();
1679 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1680 /// This function recursively traverses up the operand chain, ignoring
1682 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1683 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1684 bool IgnoreChains) {
1685 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1686 // greater than all of its (recursive) operands. If we scan to a point where
1687 // 'use' is smaller than the node we're scanning for, then we know we will
1690 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1691 // happen because we scan down to newly selected nodes in the case of glue
1693 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1696 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1697 // won't fail if we scan it again.
1698 if (!Visited.insert(Use))
1701 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1702 // Ignore chain uses, they are validated by HandleMergeInputChains.
1703 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1706 SDNode *N = Use->getOperand(i).getNode();
1708 if (Use == ImmedUse || Use == Root)
1709 continue; // We are not looking for immediate use.
1714 // Traverse up the operand chain.
1715 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1721 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1722 /// operand node N of U during instruction selection that starts at Root.
1723 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1724 SDNode *Root) const {
1725 if (OptLevel == CodeGenOpt::None) return false;
1726 return N.hasOneUse();
1729 /// IsLegalToFold - Returns true if the specific operand node N of
1730 /// U can be folded during instruction selection that starts at Root.
1731 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1732 CodeGenOpt::Level OptLevel,
1733 bool IgnoreChains) {
1734 if (OptLevel == CodeGenOpt::None) return false;
1736 // If Root use can somehow reach N through a path that that doesn't contain
1737 // U then folding N would create a cycle. e.g. In the following
1738 // diagram, Root can reach N through X. If N is folded into into Root, then
1739 // X is both a predecessor and a successor of U.
1750 // * indicates nodes to be folded together.
1752 // If Root produces glue, then it gets (even more) interesting. Since it
1753 // will be "glued" together with its glue use in the scheduler, we need to
1754 // check if it might reach N.
1773 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1774 // (call it Fold), then X is a predecessor of GU and a successor of
1775 // Fold. But since Fold and GU are glued together, this will create
1776 // a cycle in the scheduling graph.
1778 // If the node has glue, walk down the graph to the "lowest" node in the
1780 EVT VT = Root->getValueType(Root->getNumValues()-1);
1781 while (VT == MVT::Glue) {
1782 SDNode *GU = findGlueUse(Root);
1786 VT = Root->getValueType(Root->getNumValues()-1);
1788 // If our query node has a glue result with a use, we've walked up it. If
1789 // the user (which has already been selected) has a chain or indirectly uses
1790 // the chain, our WalkChainUsers predicate will not consider it. Because of
1791 // this, we cannot ignore chains in this predicate.
1792 IgnoreChains = false;
1796 SmallPtrSet<SDNode*, 16> Visited;
1797 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1800 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1801 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1802 SelectInlineAsmMemoryOperands(Ops);
1804 EVT VTs[] = { MVT::Other, MVT::Glue };
1805 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1806 VTs, &Ops[0], Ops.size());
1808 return New.getNode();
1811 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1812 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1815 /// GetVBR - decode a vbr encoding whose top bit is set.
1816 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1817 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1818 assert(Val >= 128 && "Not a VBR");
1819 Val &= 127; // Remove first vbr bit.
1824 NextBits = MatcherTable[Idx++];
1825 Val |= (NextBits&127) << Shift;
1827 } while (NextBits & 128);
1833 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1834 /// interior glue and chain results to use the new glue and chain results.
1835 void SelectionDAGISel::
1836 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1837 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1839 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1840 bool isMorphNodeTo) {
1841 SmallVector<SDNode*, 4> NowDeadNodes;
1843 // Now that all the normal results are replaced, we replace the chain and
1844 // glue results if present.
1845 if (!ChainNodesMatched.empty()) {
1846 assert(InputChain.getNode() != 0 &&
1847 "Matched input chains but didn't produce a chain");
1848 // Loop over all of the nodes we matched that produced a chain result.
1849 // Replace all the chain results with the final chain we ended up with.
1850 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1851 SDNode *ChainNode = ChainNodesMatched[i];
1853 // If this node was already deleted, don't look at it.
1854 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1857 // Don't replace the results of the root node if we're doing a
1859 if (ChainNode == NodeToMatch && isMorphNodeTo)
1862 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1863 if (ChainVal.getValueType() == MVT::Glue)
1864 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1865 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1866 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1868 // If the node became dead and we haven't already seen it, delete it.
1869 if (ChainNode->use_empty() &&
1870 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1871 NowDeadNodes.push_back(ChainNode);
1875 // If the result produces glue, update any glue results in the matched
1876 // pattern with the glue result.
1877 if (InputGlue.getNode() != 0) {
1878 // Handle any interior nodes explicitly marked.
1879 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1880 SDNode *FRN = GlueResultNodesMatched[i];
1882 // If this node was already deleted, don't look at it.
1883 if (FRN->getOpcode() == ISD::DELETED_NODE)
1886 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1887 "Doesn't have a glue result");
1888 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1891 // If the node became dead and we haven't already seen it, delete it.
1892 if (FRN->use_empty() &&
1893 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1894 NowDeadNodes.push_back(FRN);
1898 if (!NowDeadNodes.empty())
1899 CurDAG->RemoveDeadNodes(NowDeadNodes);
1901 DEBUG(dbgs() << "ISEL: Match complete!\n");
1907 CR_LeadsToInteriorNode
1910 /// WalkChainUsers - Walk down the users of the specified chained node that is
1911 /// part of the pattern we're matching, looking at all of the users we find.
1912 /// This determines whether something is an interior node, whether we have a
1913 /// non-pattern node in between two pattern nodes (which prevent folding because
1914 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1915 /// between pattern nodes (in which case the TF becomes part of the pattern).
1917 /// The walk we do here is guaranteed to be small because we quickly get down to
1918 /// already selected nodes "below" us.
1920 WalkChainUsers(const SDNode *ChainedNode,
1921 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1922 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1923 ChainResult Result = CR_Simple;
1925 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1926 E = ChainedNode->use_end(); UI != E; ++UI) {
1927 // Make sure the use is of the chain, not some other value we produce.
1928 if (UI.getUse().getValueType() != MVT::Other) continue;
1932 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1935 // If we see an already-selected machine node, then we've gone beyond the
1936 // pattern that we're selecting down into the already selected chunk of the
1938 unsigned UserOpcode = User->getOpcode();
1939 if (User->isMachineOpcode() ||
1940 UserOpcode == ISD::CopyToReg ||
1941 UserOpcode == ISD::CopyFromReg ||
1942 UserOpcode == ISD::INLINEASM ||
1943 UserOpcode == ISD::EH_LABEL ||
1944 UserOpcode == ISD::LIFETIME_START ||
1945 UserOpcode == ISD::LIFETIME_END) {
1946 // If their node ID got reset to -1 then they've already been selected.
1947 // Treat them like a MachineOpcode.
1948 if (User->getNodeId() == -1)
1952 // If we have a TokenFactor, we handle it specially.
1953 if (User->getOpcode() != ISD::TokenFactor) {
1954 // If the node isn't a token factor and isn't part of our pattern, then it
1955 // must be a random chained node in between two nodes we're selecting.
1956 // This happens when we have something like:
1961 // Because we structurally match the load/store as a read/modify/write,
1962 // but the call is chained between them. We cannot fold in this case
1963 // because it would induce a cycle in the graph.
1964 if (!std::count(ChainedNodesInPattern.begin(),
1965 ChainedNodesInPattern.end(), User))
1966 return CR_InducesCycle;
1968 // Otherwise we found a node that is part of our pattern. For example in:
1972 // This would happen when we're scanning down from the load and see the
1973 // store as a user. Record that there is a use of ChainedNode that is
1974 // part of the pattern and keep scanning uses.
1975 Result = CR_LeadsToInteriorNode;
1976 InteriorChainedNodes.push_back(User);
1980 // If we found a TokenFactor, there are two cases to consider: first if the
1981 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1982 // uses of the TF are in our pattern) we just want to ignore it. Second,
1983 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1989 // | \ DAG's like cheese
1992 // [TokenFactor] [Op]
1999 // In this case, the TokenFactor becomes part of our match and we rewrite it
2000 // as a new TokenFactor.
2002 // To distinguish these two cases, do a recursive walk down the uses.
2003 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2005 // If the uses of the TokenFactor are just already-selected nodes, ignore
2006 // it, it is "below" our pattern.
2008 case CR_InducesCycle:
2009 // If the uses of the TokenFactor lead to nodes that are not part of our
2010 // pattern that are not selected, folding would turn this into a cycle,
2012 return CR_InducesCycle;
2013 case CR_LeadsToInteriorNode:
2014 break; // Otherwise, keep processing.
2017 // Okay, we know we're in the interesting interior case. The TokenFactor
2018 // is now going to be considered part of the pattern so that we rewrite its
2019 // uses (it may have uses that are not part of the pattern) with the
2020 // ultimate chain result of the generated code. We will also add its chain
2021 // inputs as inputs to the ultimate TokenFactor we create.
2022 Result = CR_LeadsToInteriorNode;
2023 ChainedNodesInPattern.push_back(User);
2024 InteriorChainedNodes.push_back(User);
2031 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2032 /// operation for when the pattern matched at least one node with a chains. The
2033 /// input vector contains a list of all of the chained nodes that we match. We
2034 /// must determine if this is a valid thing to cover (i.e. matching it won't
2035 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2036 /// be used as the input node chain for the generated nodes.
2038 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2039 SelectionDAG *CurDAG) {
2040 // Walk all of the chained nodes we've matched, recursively scanning down the
2041 // users of the chain result. This adds any TokenFactor nodes that are caught
2042 // in between chained nodes to the chained and interior nodes list.
2043 SmallVector<SDNode*, 3> InteriorChainedNodes;
2044 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2045 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2046 InteriorChainedNodes) == CR_InducesCycle)
2047 return SDValue(); // Would induce a cycle.
2050 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2051 // that we are interested in. Form our input TokenFactor node.
2052 SmallVector<SDValue, 3> InputChains;
2053 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2054 // Add the input chain of this node to the InputChains list (which will be
2055 // the operands of the generated TokenFactor) if it's not an interior node.
2056 SDNode *N = ChainNodesMatched[i];
2057 if (N->getOpcode() != ISD::TokenFactor) {
2058 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2061 // Otherwise, add the input chain.
2062 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2063 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2064 InputChains.push_back(InChain);
2068 // If we have a token factor, we want to add all inputs of the token factor
2069 // that are not part of the pattern we're matching.
2070 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2071 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2072 N->getOperand(op).getNode()))
2073 InputChains.push_back(N->getOperand(op));
2077 if (InputChains.size() == 1)
2078 return InputChains[0];
2079 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2080 MVT::Other, &InputChains[0], InputChains.size());
2083 /// MorphNode - Handle morphing a node in place for the selector.
2084 SDNode *SelectionDAGISel::
2085 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2086 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
2087 // It is possible we're using MorphNodeTo to replace a node with no
2088 // normal results with one that has a normal result (or we could be
2089 // adding a chain) and the input could have glue and chains as well.
2090 // In this case we need to shift the operands down.
2091 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2092 // than the old isel though.
2093 int OldGlueResultNo = -1, OldChainResultNo = -1;
2095 unsigned NTMNumResults = Node->getNumValues();
2096 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2097 OldGlueResultNo = NTMNumResults-1;
2098 if (NTMNumResults != 1 &&
2099 Node->getValueType(NTMNumResults-2) == MVT::Other)
2100 OldChainResultNo = NTMNumResults-2;
2101 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2102 OldChainResultNo = NTMNumResults-1;
2104 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2105 // that this deletes operands of the old node that become dead.
2106 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
2108 // MorphNodeTo can operate in two ways: if an existing node with the
2109 // specified operands exists, it can just return it. Otherwise, it
2110 // updates the node in place to have the requested operands.
2112 // If we updated the node in place, reset the node ID. To the isel,
2113 // this should be just like a newly allocated machine node.
2117 unsigned ResNumResults = Res->getNumValues();
2118 // Move the glue if needed.
2119 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2120 (unsigned)OldGlueResultNo != ResNumResults-1)
2121 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2122 SDValue(Res, ResNumResults-1));
2124 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2127 // Move the chain reference if needed.
2128 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2129 (unsigned)OldChainResultNo != ResNumResults-1)
2130 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2131 SDValue(Res, ResNumResults-1));
2133 // Otherwise, no replacement happened because the node already exists. Replace
2134 // Uses of the old node with the new one.
2136 CurDAG->ReplaceAllUsesWith(Node, Res);
2141 /// CheckSame - Implements OP_CheckSame.
2142 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2143 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2145 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2146 // Accept if it is exactly the same as a previously recorded node.
2147 unsigned RecNo = MatcherTable[MatcherIndex++];
2148 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2149 return N == RecordedNodes[RecNo].first;
2152 /// CheckChildSame - Implements OP_CheckChildXSame.
2153 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2154 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2156 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2158 if (ChildNo >= N.getNumOperands())
2159 return false; // Match fails if out of range child #.
2160 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2164 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2165 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2166 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2167 const SelectionDAGISel &SDISel) {
2168 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2171 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2172 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2173 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2174 const SelectionDAGISel &SDISel, SDNode *N) {
2175 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2178 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2179 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2181 uint16_t Opc = MatcherTable[MatcherIndex++];
2182 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2183 return N->getOpcode() == Opc;
2186 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2187 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2188 SDValue N, const TargetLowering *TLI) {
2189 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2190 if (N.getValueType() == VT) return true;
2192 // Handle the case when VT is iPTR.
2193 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2196 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2197 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2198 SDValue N, const TargetLowering *TLI,
2200 if (ChildNo >= N.getNumOperands())
2201 return false; // Match fails if out of range child #.
2202 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2205 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2206 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2208 return cast<CondCodeSDNode>(N)->get() ==
2209 (ISD::CondCode)MatcherTable[MatcherIndex++];
2212 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2213 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2214 SDValue N, const TargetLowering *TLI) {
2215 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2216 if (cast<VTSDNode>(N)->getVT() == VT)
2219 // Handle the case when VT is iPTR.
2220 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2223 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2224 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2226 int64_t Val = MatcherTable[MatcherIndex++];
2228 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2230 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2231 return C != 0 && C->getSExtValue() == Val;
2234 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2235 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2236 SDValue N, const SelectionDAGISel &SDISel) {
2237 int64_t Val = MatcherTable[MatcherIndex++];
2239 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2241 if (N->getOpcode() != ISD::AND) return false;
2243 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2244 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2247 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2248 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2249 SDValue N, const SelectionDAGISel &SDISel) {
2250 int64_t Val = MatcherTable[MatcherIndex++];
2252 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2254 if (N->getOpcode() != ISD::OR) return false;
2256 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2257 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2260 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2261 /// scope, evaluate the current node. If the current predicate is known to
2262 /// fail, set Result=true and return anything. If the current predicate is
2263 /// known to pass, set Result=false and return the MatcherIndex to continue
2264 /// with. If the current predicate is unknown, set Result=false and return the
2265 /// MatcherIndex to continue with.
2266 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2267 unsigned Index, SDValue N,
2269 const SelectionDAGISel &SDISel,
2270 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2271 switch (Table[Index++]) {
2274 return Index-1; // Could not evaluate this predicate.
2275 case SelectionDAGISel::OPC_CheckSame:
2276 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2278 case SelectionDAGISel::OPC_CheckChild0Same:
2279 case SelectionDAGISel::OPC_CheckChild1Same:
2280 case SelectionDAGISel::OPC_CheckChild2Same:
2281 case SelectionDAGISel::OPC_CheckChild3Same:
2282 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2283 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2285 case SelectionDAGISel::OPC_CheckPatternPredicate:
2286 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2288 case SelectionDAGISel::OPC_CheckPredicate:
2289 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2291 case SelectionDAGISel::OPC_CheckOpcode:
2292 Result = !::CheckOpcode(Table, Index, N.getNode());
2294 case SelectionDAGISel::OPC_CheckType:
2295 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2297 case SelectionDAGISel::OPC_CheckChild0Type:
2298 case SelectionDAGISel::OPC_CheckChild1Type:
2299 case SelectionDAGISel::OPC_CheckChild2Type:
2300 case SelectionDAGISel::OPC_CheckChild3Type:
2301 case SelectionDAGISel::OPC_CheckChild4Type:
2302 case SelectionDAGISel::OPC_CheckChild5Type:
2303 case SelectionDAGISel::OPC_CheckChild6Type:
2304 case SelectionDAGISel::OPC_CheckChild7Type:
2305 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2306 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2308 case SelectionDAGISel::OPC_CheckCondCode:
2309 Result = !::CheckCondCode(Table, Index, N);
2311 case SelectionDAGISel::OPC_CheckValueType:
2312 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2314 case SelectionDAGISel::OPC_CheckInteger:
2315 Result = !::CheckInteger(Table, Index, N);
2317 case SelectionDAGISel::OPC_CheckAndImm:
2318 Result = !::CheckAndImm(Table, Index, N, SDISel);
2320 case SelectionDAGISel::OPC_CheckOrImm:
2321 Result = !::CheckOrImm(Table, Index, N, SDISel);
2329 /// FailIndex - If this match fails, this is the index to continue with.
2332 /// NodeStack - The node stack when the scope was formed.
2333 SmallVector<SDValue, 4> NodeStack;
2335 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2336 unsigned NumRecordedNodes;
2338 /// NumMatchedMemRefs - The number of matched memref entries.
2339 unsigned NumMatchedMemRefs;
2341 /// InputChain/InputGlue - The current chain/glue
2342 SDValue InputChain, InputGlue;
2344 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2345 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2350 SDNode *SelectionDAGISel::
2351 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2352 unsigned TableSize) {
2353 // FIXME: Should these even be selected? Handle these cases in the caller?
2354 switch (NodeToMatch->getOpcode()) {
2357 case ISD::EntryToken: // These nodes remain the same.
2358 case ISD::BasicBlock:
2360 case ISD::RegisterMask:
2361 //case ISD::VALUETYPE:
2362 //case ISD::CONDCODE:
2363 case ISD::HANDLENODE:
2364 case ISD::MDNODE_SDNODE:
2365 case ISD::TargetConstant:
2366 case ISD::TargetConstantFP:
2367 case ISD::TargetConstantPool:
2368 case ISD::TargetFrameIndex:
2369 case ISD::TargetExternalSymbol:
2370 case ISD::TargetBlockAddress:
2371 case ISD::TargetJumpTable:
2372 case ISD::TargetGlobalTLSAddress:
2373 case ISD::TargetGlobalAddress:
2374 case ISD::TokenFactor:
2375 case ISD::CopyFromReg:
2376 case ISD::CopyToReg:
2378 case ISD::LIFETIME_START:
2379 case ISD::LIFETIME_END:
2380 NodeToMatch->setNodeId(-1); // Mark selected.
2382 case ISD::AssertSext:
2383 case ISD::AssertZext:
2384 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2385 NodeToMatch->getOperand(0));
2387 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2388 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2391 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2393 // Set up the node stack with NodeToMatch as the only node on the stack.
2394 SmallVector<SDValue, 8> NodeStack;
2395 SDValue N = SDValue(NodeToMatch, 0);
2396 NodeStack.push_back(N);
2398 // MatchScopes - Scopes used when matching, if a match failure happens, this
2399 // indicates where to continue checking.
2400 SmallVector<MatchScope, 8> MatchScopes;
2402 // RecordedNodes - This is the set of nodes that have been recorded by the
2403 // state machine. The second value is the parent of the node, or null if the
2404 // root is recorded.
2405 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2407 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2409 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2411 // These are the current input chain and glue for use when generating nodes.
2412 // Various Emit operations change these. For example, emitting a copytoreg
2413 // uses and updates these.
2414 SDValue InputChain, InputGlue;
2416 // ChainNodesMatched - If a pattern matches nodes that have input/output
2417 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2418 // which ones they are. The result is captured into this list so that we can
2419 // update the chain results when the pattern is complete.
2420 SmallVector<SDNode*, 3> ChainNodesMatched;
2421 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2423 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2424 NodeToMatch->dump(CurDAG);
2427 // Determine where to start the interpreter. Normally we start at opcode #0,
2428 // but if the state machine starts with an OPC_SwitchOpcode, then we
2429 // accelerate the first lookup (which is guaranteed to be hot) with the
2430 // OpcodeOffset table.
2431 unsigned MatcherIndex = 0;
2433 if (!OpcodeOffset.empty()) {
2434 // Already computed the OpcodeOffset table, just index into it.
2435 if (N.getOpcode() < OpcodeOffset.size())
2436 MatcherIndex = OpcodeOffset[N.getOpcode()];
2437 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2439 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2440 // Otherwise, the table isn't computed, but the state machine does start
2441 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2442 // is the first time we're selecting an instruction.
2445 // Get the size of this case.
2446 unsigned CaseSize = MatcherTable[Idx++];
2448 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2449 if (CaseSize == 0) break;
2451 // Get the opcode, add the index to the table.
2452 uint16_t Opc = MatcherTable[Idx++];
2453 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2454 if (Opc >= OpcodeOffset.size())
2455 OpcodeOffset.resize((Opc+1)*2);
2456 OpcodeOffset[Opc] = Idx;
2460 // Okay, do the lookup for the first opcode.
2461 if (N.getOpcode() < OpcodeOffset.size())
2462 MatcherIndex = OpcodeOffset[N.getOpcode()];
2466 assert(MatcherIndex < TableSize && "Invalid index");
2468 unsigned CurrentOpcodeIndex = MatcherIndex;
2470 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2473 // Okay, the semantics of this operation are that we should push a scope
2474 // then evaluate the first child. However, pushing a scope only to have
2475 // the first check fail (which then pops it) is inefficient. If we can
2476 // determine immediately that the first check (or first several) will
2477 // immediately fail, don't even bother pushing a scope for them.
2481 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2482 if (NumToSkip & 128)
2483 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2484 // Found the end of the scope with no match.
2485 if (NumToSkip == 0) {
2490 FailIndex = MatcherIndex+NumToSkip;
2492 unsigned MatcherIndexOfPredicate = MatcherIndex;
2493 (void)MatcherIndexOfPredicate; // silence warning.
2495 // If we can't evaluate this predicate without pushing a scope (e.g. if
2496 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2497 // push the scope and evaluate the full predicate chain.
2499 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2500 Result, *this, RecordedNodes);
2504 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2505 << "index " << MatcherIndexOfPredicate
2506 << ", continuing at " << FailIndex << "\n");
2507 ++NumDAGIselRetries;
2509 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2510 // move to the next case.
2511 MatcherIndex = FailIndex;
2514 // If the whole scope failed to match, bail.
2515 if (FailIndex == 0) break;
2517 // Push a MatchScope which indicates where to go if the first child fails
2519 MatchScope NewEntry;
2520 NewEntry.FailIndex = FailIndex;
2521 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2522 NewEntry.NumRecordedNodes = RecordedNodes.size();
2523 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2524 NewEntry.InputChain = InputChain;
2525 NewEntry.InputGlue = InputGlue;
2526 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2527 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2528 MatchScopes.push_back(NewEntry);
2531 case OPC_RecordNode: {
2532 // Remember this node, it may end up being an operand in the pattern.
2534 if (NodeStack.size() > 1)
2535 Parent = NodeStack[NodeStack.size()-2].getNode();
2536 RecordedNodes.push_back(std::make_pair(N, Parent));
2540 case OPC_RecordChild0: case OPC_RecordChild1:
2541 case OPC_RecordChild2: case OPC_RecordChild3:
2542 case OPC_RecordChild4: case OPC_RecordChild5:
2543 case OPC_RecordChild6: case OPC_RecordChild7: {
2544 unsigned ChildNo = Opcode-OPC_RecordChild0;
2545 if (ChildNo >= N.getNumOperands())
2546 break; // Match fails if out of range child #.
2548 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2552 case OPC_RecordMemRef:
2553 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2556 case OPC_CaptureGlueInput:
2557 // If the current node has an input glue, capture it in InputGlue.
2558 if (N->getNumOperands() != 0 &&
2559 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2560 InputGlue = N->getOperand(N->getNumOperands()-1);
2563 case OPC_MoveChild: {
2564 unsigned ChildNo = MatcherTable[MatcherIndex++];
2565 if (ChildNo >= N.getNumOperands())
2566 break; // Match fails if out of range child #.
2567 N = N.getOperand(ChildNo);
2568 NodeStack.push_back(N);
2572 case OPC_MoveParent:
2573 // Pop the current node off the NodeStack.
2574 NodeStack.pop_back();
2575 assert(!NodeStack.empty() && "Node stack imbalance!");
2576 N = NodeStack.back();
2580 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2583 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2584 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2585 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2586 Opcode-OPC_CheckChild0Same))
2590 case OPC_CheckPatternPredicate:
2591 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2593 case OPC_CheckPredicate:
2594 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2598 case OPC_CheckComplexPat: {
2599 unsigned CPNum = MatcherTable[MatcherIndex++];
2600 unsigned RecNo = MatcherTable[MatcherIndex++];
2601 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2602 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2603 RecordedNodes[RecNo].first, CPNum,
2608 case OPC_CheckOpcode:
2609 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2613 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2617 case OPC_SwitchOpcode: {
2618 unsigned CurNodeOpcode = N.getOpcode();
2619 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2622 // Get the size of this case.
2623 CaseSize = MatcherTable[MatcherIndex++];
2625 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2626 if (CaseSize == 0) break;
2628 uint16_t Opc = MatcherTable[MatcherIndex++];
2629 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2631 // If the opcode matches, then we will execute this case.
2632 if (CurNodeOpcode == Opc)
2635 // Otherwise, skip over this case.
2636 MatcherIndex += CaseSize;
2639 // If no cases matched, bail out.
2640 if (CaseSize == 0) break;
2642 // Otherwise, execute the case we found.
2643 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2644 << " to " << MatcherIndex << "\n");
2648 case OPC_SwitchType: {
2649 MVT CurNodeVT = N.getSimpleValueType();
2650 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2653 // Get the size of this case.
2654 CaseSize = MatcherTable[MatcherIndex++];
2656 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2657 if (CaseSize == 0) break;
2659 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2660 if (CaseVT == MVT::iPTR)
2661 CaseVT = getTargetLowering()->getPointerTy();
2663 // If the VT matches, then we will execute this case.
2664 if (CurNodeVT == CaseVT)
2667 // Otherwise, skip over this case.
2668 MatcherIndex += CaseSize;
2671 // If no cases matched, bail out.
2672 if (CaseSize == 0) break;
2674 // Otherwise, execute the case we found.
2675 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2676 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2679 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2680 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2681 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2682 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2683 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2684 Opcode-OPC_CheckChild0Type))
2687 case OPC_CheckCondCode:
2688 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2690 case OPC_CheckValueType:
2691 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2694 case OPC_CheckInteger:
2695 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2697 case OPC_CheckAndImm:
2698 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2700 case OPC_CheckOrImm:
2701 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2704 case OPC_CheckFoldableChainNode: {
2705 assert(NodeStack.size() != 1 && "No parent node");
2706 // Verify that all intermediate nodes between the root and this one have
2708 bool HasMultipleUses = false;
2709 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2710 if (!NodeStack[i].hasOneUse()) {
2711 HasMultipleUses = true;
2714 if (HasMultipleUses) break;
2716 // Check to see that the target thinks this is profitable to fold and that
2717 // we can fold it without inducing cycles in the graph.
2718 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2720 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2721 NodeToMatch, OptLevel,
2722 true/*We validate our own chains*/))
2727 case OPC_EmitInteger: {
2728 MVT::SimpleValueType VT =
2729 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2730 int64_t Val = MatcherTable[MatcherIndex++];
2732 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2733 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2734 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2737 case OPC_EmitRegister: {
2738 MVT::SimpleValueType VT =
2739 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2740 unsigned RegNo = MatcherTable[MatcherIndex++];
2741 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2742 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2745 case OPC_EmitRegister2: {
2746 // For targets w/ more than 256 register names, the register enum
2747 // values are stored in two bytes in the matcher table (just like
2749 MVT::SimpleValueType VT =
2750 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2751 unsigned RegNo = MatcherTable[MatcherIndex++];
2752 RegNo |= MatcherTable[MatcherIndex++] << 8;
2753 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2754 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2758 case OPC_EmitConvertToTarget: {
2759 // Convert from IMM/FPIMM to target version.
2760 unsigned RecNo = MatcherTable[MatcherIndex++];
2761 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2762 SDValue Imm = RecordedNodes[RecNo].first;
2764 if (Imm->getOpcode() == ISD::Constant) {
2765 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2766 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2767 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2768 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2769 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2772 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2776 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2777 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2778 // These are space-optimized forms of OPC_EmitMergeInputChains.
2779 assert(InputChain.getNode() == 0 &&
2780 "EmitMergeInputChains should be the first chain producing node");
2781 assert(ChainNodesMatched.empty() &&
2782 "Should only have one EmitMergeInputChains per match");
2784 // Read all of the chained nodes.
2785 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2786 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2787 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2789 // FIXME: What if other value results of the node have uses not matched
2791 if (ChainNodesMatched.back() != NodeToMatch &&
2792 !RecordedNodes[RecNo].first.hasOneUse()) {
2793 ChainNodesMatched.clear();
2797 // Merge the input chains if they are not intra-pattern references.
2798 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2800 if (InputChain.getNode() == 0)
2801 break; // Failed to merge.
2805 case OPC_EmitMergeInputChains: {
2806 assert(InputChain.getNode() == 0 &&
2807 "EmitMergeInputChains should be the first chain producing node");
2808 // This node gets a list of nodes we matched in the input that have
2809 // chains. We want to token factor all of the input chains to these nodes
2810 // together. However, if any of the input chains is actually one of the
2811 // nodes matched in this pattern, then we have an intra-match reference.
2812 // Ignore these because the newly token factored chain should not refer to
2814 unsigned NumChains = MatcherTable[MatcherIndex++];
2815 assert(NumChains != 0 && "Can't TF zero chains");
2817 assert(ChainNodesMatched.empty() &&
2818 "Should only have one EmitMergeInputChains per match");
2820 // Read all of the chained nodes.
2821 for (unsigned i = 0; i != NumChains; ++i) {
2822 unsigned RecNo = MatcherTable[MatcherIndex++];
2823 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2824 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2826 // FIXME: What if other value results of the node have uses not matched
2828 if (ChainNodesMatched.back() != NodeToMatch &&
2829 !RecordedNodes[RecNo].first.hasOneUse()) {
2830 ChainNodesMatched.clear();
2835 // If the inner loop broke out, the match fails.
2836 if (ChainNodesMatched.empty())
2839 // Merge the input chains if they are not intra-pattern references.
2840 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2842 if (InputChain.getNode() == 0)
2843 break; // Failed to merge.
2848 case OPC_EmitCopyToReg: {
2849 unsigned RecNo = MatcherTable[MatcherIndex++];
2850 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
2851 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2853 if (InputChain.getNode() == 0)
2854 InputChain = CurDAG->getEntryNode();
2856 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2857 DestPhysReg, RecordedNodes[RecNo].first,
2860 InputGlue = InputChain.getValue(1);
2864 case OPC_EmitNodeXForm: {
2865 unsigned XFormNo = MatcherTable[MatcherIndex++];
2866 unsigned RecNo = MatcherTable[MatcherIndex++];
2867 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
2868 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2869 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2874 case OPC_MorphNodeTo: {
2875 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2876 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2877 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2878 // Get the result VT list.
2879 unsigned NumVTs = MatcherTable[MatcherIndex++];
2880 SmallVector<EVT, 4> VTs;
2881 for (unsigned i = 0; i != NumVTs; ++i) {
2882 MVT::SimpleValueType VT =
2883 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2884 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2888 if (EmitNodeInfo & OPFL_Chain)
2889 VTs.push_back(MVT::Other);
2890 if (EmitNodeInfo & OPFL_GlueOutput)
2891 VTs.push_back(MVT::Glue);
2893 // This is hot code, so optimize the two most common cases of 1 and 2
2896 if (VTs.size() == 1)
2897 VTList = CurDAG->getVTList(VTs[0]);
2898 else if (VTs.size() == 2)
2899 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2901 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2903 // Get the operand list.
2904 unsigned NumOps = MatcherTable[MatcherIndex++];
2905 SmallVector<SDValue, 8> Ops;
2906 for (unsigned i = 0; i != NumOps; ++i) {
2907 unsigned RecNo = MatcherTable[MatcherIndex++];
2909 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2911 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2912 Ops.push_back(RecordedNodes[RecNo].first);
2915 // If there are variadic operands to add, handle them now.
2916 if (EmitNodeInfo & OPFL_VariadicInfo) {
2917 // Determine the start index to copy from.
2918 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2919 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2920 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2921 "Invalid variadic node");
2922 // Copy all of the variadic operands, not including a potential glue
2924 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2926 SDValue V = NodeToMatch->getOperand(i);
2927 if (V.getValueType() == MVT::Glue) break;
2932 // If this has chain/glue inputs, add them.
2933 if (EmitNodeInfo & OPFL_Chain)
2934 Ops.push_back(InputChain);
2935 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2936 Ops.push_back(InputGlue);
2940 if (Opcode != OPC_MorphNodeTo) {
2941 // If this is a normal EmitNode command, just create the new node and
2942 // add the results to the RecordedNodes list.
2943 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2946 // Add all the non-glue/non-chain results to the RecordedNodes list.
2947 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2948 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2949 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2953 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2954 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2957 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2958 // We will visit the equivalent node later.
2959 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2963 // If the node had chain/glue results, update our notion of the current
2965 if (EmitNodeInfo & OPFL_GlueOutput) {
2966 InputGlue = SDValue(Res, VTs.size()-1);
2967 if (EmitNodeInfo & OPFL_Chain)
2968 InputChain = SDValue(Res, VTs.size()-2);
2969 } else if (EmitNodeInfo & OPFL_Chain)
2970 InputChain = SDValue(Res, VTs.size()-1);
2972 // If the OPFL_MemRefs glue is set on this node, slap all of the
2973 // accumulated memrefs onto it.
2975 // FIXME: This is vastly incorrect for patterns with multiple outputs
2976 // instructions that access memory and for ComplexPatterns that match
2978 if (EmitNodeInfo & OPFL_MemRefs) {
2979 // Only attach load or store memory operands if the generated
2980 // instruction may load or store.
2981 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2982 bool mayLoad = MCID.mayLoad();
2983 bool mayStore = MCID.mayStore();
2985 unsigned NumMemRefs = 0;
2986 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2987 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2988 if ((*I)->isLoad()) {
2991 } else if ((*I)->isStore()) {
2999 MachineSDNode::mmo_iterator MemRefs =
3000 MF->allocateMemRefsArray(NumMemRefs);
3002 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3003 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3004 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3005 if ((*I)->isLoad()) {
3008 } else if ((*I)->isStore()) {
3016 cast<MachineSDNode>(Res)
3017 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3021 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3022 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3024 // If this was a MorphNodeTo then we're completely done!
3025 if (Opcode == OPC_MorphNodeTo) {
3026 // Update chain and glue uses.
3027 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3028 InputGlue, GlueResultNodesMatched, true);
3035 case OPC_MarkGlueResults: {
3036 unsigned NumNodes = MatcherTable[MatcherIndex++];
3038 // Read and remember all the glue-result nodes.
3039 for (unsigned i = 0; i != NumNodes; ++i) {
3040 unsigned RecNo = MatcherTable[MatcherIndex++];
3042 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3044 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3045 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3050 case OPC_CompleteMatch: {
3051 // The match has been completed, and any new nodes (if any) have been
3052 // created. Patch up references to the matched dag to use the newly
3054 unsigned NumResults = MatcherTable[MatcherIndex++];
3056 for (unsigned i = 0; i != NumResults; ++i) {
3057 unsigned ResSlot = MatcherTable[MatcherIndex++];
3059 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3061 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3062 SDValue Res = RecordedNodes[ResSlot].first;
3064 assert(i < NodeToMatch->getNumValues() &&
3065 NodeToMatch->getValueType(i) != MVT::Other &&
3066 NodeToMatch->getValueType(i) != MVT::Glue &&
3067 "Invalid number of results to complete!");
3068 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3069 NodeToMatch->getValueType(i) == MVT::iPTR ||
3070 Res.getValueType() == MVT::iPTR ||
3071 NodeToMatch->getValueType(i).getSizeInBits() ==
3072 Res.getValueType().getSizeInBits()) &&
3073 "invalid replacement");
3074 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3077 // If the root node defines glue, add it to the glue nodes to update list.
3078 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3079 GlueResultNodesMatched.push_back(NodeToMatch);
3081 // Update chain and glue uses.
3082 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3083 InputGlue, GlueResultNodesMatched, false);
3085 assert(NodeToMatch->use_empty() &&
3086 "Didn't replace all uses of the node?");
3088 // FIXME: We just return here, which interacts correctly with SelectRoot
3089 // above. We should fix this to not return an SDNode* anymore.
3094 // If the code reached this point, then the match failed. See if there is
3095 // another child to try in the current 'Scope', otherwise pop it until we
3096 // find a case to check.
3097 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3098 ++NumDAGIselRetries;
3100 if (MatchScopes.empty()) {
3101 CannotYetSelect(NodeToMatch);
3105 // Restore the interpreter state back to the point where the scope was
3107 MatchScope &LastScope = MatchScopes.back();
3108 RecordedNodes.resize(LastScope.NumRecordedNodes);
3110 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3111 N = NodeStack.back();
3113 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3114 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3115 MatcherIndex = LastScope.FailIndex;
3117 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3119 InputChain = LastScope.InputChain;
3120 InputGlue = LastScope.InputGlue;
3121 if (!LastScope.HasChainNodesMatched)
3122 ChainNodesMatched.clear();
3123 if (!LastScope.HasGlueResultNodesMatched)
3124 GlueResultNodesMatched.clear();
3126 // Check to see what the offset is at the new MatcherIndex. If it is zero
3127 // we have reached the end of this scope, otherwise we have another child
3128 // in the current scope to try.
3129 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3130 if (NumToSkip & 128)
3131 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3133 // If we have another child in this scope to match, update FailIndex and
3135 if (NumToSkip != 0) {
3136 LastScope.FailIndex = MatcherIndex+NumToSkip;
3140 // End of this scope, pop it and try the next child in the containing
3142 MatchScopes.pop_back();
3149 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3151 raw_string_ostream Msg(msg);
3152 Msg << "Cannot select: ";
3154 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3155 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3156 N->getOpcode() != ISD::INTRINSIC_VOID) {
3157 N->printrFull(Msg, CurDAG);
3158 Msg << "\nIn function: " << MF->getName();
3160 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3162 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3163 if (iid < Intrinsic::num_intrinsics)
3164 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3165 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3166 Msg << "target intrinsic %" << TII->getName(iid);
3168 Msg << "unknown intrinsic #" << iid;
3170 report_fatal_error(Msg.str());
3173 char SelectionDAGISel::ID = 0;