1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/Timer.h"
53 EnableValueProp("enable-value-prop", cl::Hidden);
55 EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
60 ViewISelDAGs("view-isel-dags", cl::Hidden,
61 cl::desc("Pop up a window to show isel dags as they are selected"));
63 ViewSchedDAGs("view-sched-dags", cl::Hidden,
64 cl::desc("Pop up a window to show sched dags as they are processed"));
66 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
67 cl::desc("Pop up a window to show SUnit dags after they are processed"));
69 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
72 //===---------------------------------------------------------------------===//
74 /// RegisterScheduler class - Track the registration of instruction schedulers.
76 //===---------------------------------------------------------------------===//
77 MachinePassRegistry RegisterScheduler::Registry;
79 //===---------------------------------------------------------------------===//
81 /// ISHeuristic command line option for instruction schedulers.
83 //===---------------------------------------------------------------------===//
84 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
85 RegisterPassParser<RegisterScheduler> >
86 ISHeuristic("pre-RA-sched",
87 cl::init(&createDefaultScheduler),
88 cl::desc("Instruction schedulers available (before register"
91 static RegisterScheduler
92 defaultListDAGScheduler("default", " Best scheduler for the target",
93 createDefaultScheduler);
95 namespace { struct SDISelAsmOperandInfo; }
97 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
98 /// insertvalue or extractvalue indices that identify a member, return
99 /// the linearized index of the start of the member.
101 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
102 const unsigned *Indices,
103 const unsigned *IndicesEnd,
104 unsigned CurIndex = 0) {
105 // Base case: We're done.
106 if (Indices && Indices == IndicesEnd)
109 // Given a struct type, recursively traverse the elements.
110 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
111 for (StructType::element_iterator EB = STy->element_begin(),
113 EE = STy->element_end();
115 if (Indices && *Indices == unsigned(EI - EB))
116 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
117 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
120 // Given an array type, recursively traverse the elements.
121 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
122 const Type *EltTy = ATy->getElementType();
123 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
124 if (Indices && *Indices == i)
125 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
126 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
129 // We haven't found the type we're looking for, so keep searching.
133 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
134 /// MVTs that represent all the individual underlying
135 /// non-aggregate types that comprise it.
137 /// If Offsets is non-null, it points to a vector to be filled in
138 /// with the in-memory offsets of each of the individual values.
140 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
141 SmallVectorImpl<MVT> &ValueVTs,
142 SmallVectorImpl<uint64_t> *Offsets = 0,
143 uint64_t StartingOffset = 0) {
144 // Given a struct type, recursively traverse the elements.
145 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
146 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
147 for (StructType::element_iterator EB = STy->element_begin(),
149 EE = STy->element_end();
151 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
152 StartingOffset + SL->getElementOffset(EI - EB));
155 // Given an array type, recursively traverse the elements.
156 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
157 const Type *EltTy = ATy->getElementType();
158 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
159 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
160 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
161 StartingOffset + i * EltSize);
164 // Base case: we can get an MVT for this LLVM IR type.
165 ValueVTs.push_back(TLI.getValueType(Ty));
167 Offsets->push_back(StartingOffset);
171 /// RegsForValue - This struct represents the registers (physical or virtual)
172 /// that a particular set of values is assigned, and the type information about
173 /// the value. The most common situation is to represent one value at a time,
174 /// but struct or array values are handled element-wise as multiple values.
175 /// The splitting of aggregates is performed recursively, so that we never
176 /// have aggregate-typed registers. The values at this point do not necessarily
177 /// have legal types, so each value may require one or more registers of some
180 struct VISIBILITY_HIDDEN RegsForValue {
181 /// TLI - The TargetLowering object.
183 const TargetLowering *TLI;
185 /// ValueVTs - The value types of the values, which may not be legal, and
186 /// may need be promoted or synthesized from one or more registers.
188 SmallVector<MVT, 4> ValueVTs;
190 /// RegVTs - The value types of the registers. This is the same size as
191 /// ValueVTs and it records, for each value, what the type of the assigned
192 /// register or registers are. (Individual values are never synthesized
193 /// from more than one type of register.)
195 /// With virtual registers, the contents of RegVTs is redundant with TLI's
196 /// getRegisterType member function, however when with physical registers
197 /// it is necessary to have a separate record of the types.
199 SmallVector<MVT, 4> RegVTs;
201 /// Regs - This list holds the registers assigned to the values.
202 /// Each legal or promoted value requires one register, and each
203 /// expanded value requires multiple registers.
205 SmallVector<unsigned, 4> Regs;
207 RegsForValue() : TLI(0) {}
209 RegsForValue(const TargetLowering &tli,
210 const SmallVector<unsigned, 4> ®s,
211 MVT regvt, MVT valuevt)
212 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
213 RegsForValue(const TargetLowering &tli,
214 const SmallVector<unsigned, 4> ®s,
215 const SmallVector<MVT, 4> ®vts,
216 const SmallVector<MVT, 4> &valuevts)
217 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
218 RegsForValue(const TargetLowering &tli,
219 unsigned Reg, const Type *Ty) : TLI(&tli) {
220 ComputeValueVTs(tli, Ty, ValueVTs);
222 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
223 MVT ValueVT = ValueVTs[Value];
224 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
225 MVT RegisterVT = TLI->getRegisterType(ValueVT);
226 for (unsigned i = 0; i != NumRegs; ++i)
227 Regs.push_back(Reg + i);
228 RegVTs.push_back(RegisterVT);
233 /// append - Add the specified values to this one.
234 void append(const RegsForValue &RHS) {
236 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
237 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
238 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
242 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
243 /// this value and returns the result as a ValueVTs value. This uses
244 /// Chain/Flag as the input and updates them for the output Chain/Flag.
245 /// If the Flag pointer is NULL, no flag is used.
246 SDOperand getCopyFromRegs(SelectionDAG &DAG,
247 SDOperand &Chain, SDOperand *Flag) const;
249 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
250 /// specified value into the registers specified by this object. This uses
251 /// Chain/Flag as the input and updates them for the output Chain/Flag.
252 /// If the Flag pointer is NULL, no flag is used.
253 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
254 SDOperand &Chain, SDOperand *Flag) const;
256 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
257 /// operand list. This adds the code marker and includes the number of
258 /// values added into it.
259 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
260 std::vector<SDOperand> &Ops) const;
265 //===--------------------------------------------------------------------===//
266 /// createDefaultScheduler - This creates an instruction scheduler appropriate
268 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
270 MachineBasicBlock *BB,
272 TargetLowering &TLI = IS->getTargetLowering();
274 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
275 return createTDListDAGScheduler(IS, DAG, BB, Fast);
277 assert(TLI.getSchedulingPreference() ==
278 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
279 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
284 //===--------------------------------------------------------------------===//
285 /// FunctionLoweringInfo - This contains information that is global to a
286 /// function that is used when lowering a region of the function.
287 class FunctionLoweringInfo {
292 MachineRegisterInfo &RegInfo;
294 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
296 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
297 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
299 /// ValueMap - Since we emit code for the function a basic block at a time,
300 /// we must remember which virtual registers hold the values for
301 /// cross-basic-block values.
302 DenseMap<const Value*, unsigned> ValueMap;
304 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
305 /// the entry block. This allows the allocas to be efficiently referenced
306 /// anywhere in the function.
307 std::map<const AllocaInst*, int> StaticAllocaMap;
310 SmallSet<Instruction*, 8> CatchInfoLost;
311 SmallSet<Instruction*, 8> CatchInfoFound;
314 unsigned MakeReg(MVT VT) {
315 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
318 /// isExportedInst - Return true if the specified value is an instruction
319 /// exported from its block.
320 bool isExportedInst(const Value *V) {
321 return ValueMap.count(V);
324 unsigned CreateRegForValue(const Value *V);
326 unsigned InitializeRegForValue(const Value *V) {
327 unsigned &R = ValueMap[V];
328 assert(R == 0 && "Already initialized this value register!");
329 return R = CreateRegForValue(V);
333 unsigned NumSignBits;
334 APInt KnownOne, KnownZero;
335 LiveOutInfo() : NumSignBits(0) {}
338 /// LiveOutRegInfo - Information about live out vregs, indexed by their
339 /// register number offset by 'FirstVirtualRegister'.
340 std::vector<LiveOutInfo> LiveOutRegInfo;
344 /// isSelector - Return true if this instruction is a call to the
345 /// eh.selector intrinsic.
346 static bool isSelector(Instruction *I) {
347 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
348 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
349 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
353 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
354 /// PHI nodes or outside of the basic block that defines it, or used by a
355 /// switch or atomic instruction, which may expand to multiple basic blocks.
356 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
357 if (isa<PHINode>(I)) return true;
358 BasicBlock *BB = I->getParent();
359 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
360 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
361 // FIXME: Remove switchinst special case.
362 isa<SwitchInst>(*UI))
367 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
368 /// entry block, return true. This includes arguments used by switches, since
369 /// the switch may expand into multiple basic blocks.
370 static bool isOnlyUsedInEntryBlock(Argument *A) {
371 BasicBlock *Entry = A->getParent()->begin();
372 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
373 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
374 return false; // Use not in entry block.
378 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
379 Function &fn, MachineFunction &mf)
380 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
382 // Create a vreg for each argument register that is not dead and is used
383 // outside of the entry block for the function.
384 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
386 if (!isOnlyUsedInEntryBlock(AI))
387 InitializeRegForValue(AI);
389 // Initialize the mapping of values to registers. This is only set up for
390 // instruction values that are used outside of the block that defines
392 Function::iterator BB = Fn.begin(), EB = Fn.end();
393 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
394 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
395 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
396 const Type *Ty = AI->getAllocatedType();
397 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
399 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
402 TySize *= CUI->getZExtValue(); // Get total allocated size.
403 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
404 StaticAllocaMap[AI] =
405 MF.getFrameInfo()->CreateStackObject(TySize, Align);
408 for (; BB != EB; ++BB)
409 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
410 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
411 if (!isa<AllocaInst>(I) ||
412 !StaticAllocaMap.count(cast<AllocaInst>(I)))
413 InitializeRegForValue(I);
415 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
416 // also creates the initial PHI MachineInstrs, though none of the input
417 // operands are populated.
418 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
419 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
423 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
426 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
427 if (PN->use_empty()) continue;
429 MVT VT = TLI.getValueType(PN->getType());
430 unsigned NumRegisters = TLI.getNumRegisters(VT);
431 unsigned PHIReg = ValueMap[PN];
432 assert(PHIReg && "PHI node does not have an assigned virtual register!");
433 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
434 for (unsigned i = 0; i != NumRegisters; ++i)
435 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
440 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
441 /// the correctly promoted or expanded types. Assign these registers
442 /// consecutive vreg numbers and return the first assigned number.
444 /// In the case that the given value has struct or array type, this function
445 /// will assign registers for each member or element.
447 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
448 SmallVector<MVT, 4> ValueVTs;
449 ComputeValueVTs(TLI, V->getType(), ValueVTs);
451 unsigned FirstReg = 0;
452 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
453 MVT ValueVT = ValueVTs[Value];
454 MVT RegisterVT = TLI.getRegisterType(ValueVT);
456 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
457 for (unsigned i = 0; i != NumRegs; ++i) {
458 unsigned R = MakeReg(RegisterVT);
459 if (!FirstReg) FirstReg = R;
465 //===----------------------------------------------------------------------===//
466 /// SelectionDAGLowering - This is the common target-independent lowering
467 /// implementation that is parameterized by a TargetLowering object.
468 /// Also, targets can overload any lowering method.
471 class SelectionDAGLowering {
472 MachineBasicBlock *CurMBB;
474 DenseMap<const Value*, SDOperand> NodeMap;
476 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
477 /// them up and then emit token factor nodes when possible. This allows us to
478 /// get simple disambiguation between loads without worrying about alias
480 SmallVector<SDOperand, 8> PendingLoads;
482 /// PendingExports - CopyToReg nodes that copy values to virtual registers
483 /// for export to other blocks need to be emitted before any terminator
484 /// instruction, but they have no other ordering requirements. We bunch them
485 /// up and the emit a single tokenfactor for them just before terminator
487 std::vector<SDOperand> PendingExports;
489 /// Case - A struct to record the Value for a switch case, and the
490 /// case's target basic block.
494 MachineBasicBlock* BB;
496 Case() : Low(0), High(0), BB(0) { }
497 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
498 Low(low), High(high), BB(bb) { }
499 uint64_t size() const {
500 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
501 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
502 return (rHigh - rLow + 1ULL);
508 MachineBasicBlock* BB;
511 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
512 Mask(mask), BB(bb), Bits(bits) { }
515 typedef std::vector<Case> CaseVector;
516 typedef std::vector<CaseBits> CaseBitsVector;
517 typedef CaseVector::iterator CaseItr;
518 typedef std::pair<CaseItr, CaseItr> CaseRange;
520 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
521 /// of conditional branches.
523 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
524 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
526 /// CaseBB - The MBB in which to emit the compare and branch
527 MachineBasicBlock *CaseBB;
528 /// LT, GE - If nonzero, we know the current case value must be less-than or
529 /// greater-than-or-equal-to these Constants.
532 /// Range - A pair of iterators representing the range of case values to be
533 /// processed at this point in the binary search tree.
537 typedef std::vector<CaseRec> CaseRecVector;
539 /// The comparison function for sorting the switch case values in the vector.
540 /// WARNING: Case ranges should be disjoint!
542 bool operator () (const Case& C1, const Case& C2) {
543 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
544 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
545 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
546 return CI1->getValue().slt(CI2->getValue());
551 bool operator () (const CaseBits& C1, const CaseBits& C2) {
552 return C1.Bits > C2.Bits;
556 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
559 // TLI - This is information that describes the available target features we
560 // need for lowering. This indicates when operations are unavailable,
561 // implemented with a libcall, etc.
564 const TargetData *TD;
567 /// SwitchCases - Vector of CaseBlock structures used to communicate
568 /// SwitchInst code generation information.
569 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
570 /// JTCases - Vector of JumpTable structures used to communicate
571 /// SwitchInst code generation information.
572 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
573 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
575 /// FuncInfo - Information about the function as a whole.
577 FunctionLoweringInfo &FuncInfo;
579 /// GCI - Garbage collection metadata for the function.
580 CollectorMetadata *GCI;
582 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
584 FunctionLoweringInfo &funcinfo,
585 CollectorMetadata *gci)
586 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
587 FuncInfo(funcinfo), GCI(gci) {
590 /// getRoot - Return the current virtual root of the Selection DAG,
591 /// flushing any PendingLoad items. This must be done before emitting
592 /// a store or any other node that may need to be ordered after any
593 /// prior load instructions.
595 SDOperand getRoot() {
596 if (PendingLoads.empty())
597 return DAG.getRoot();
599 if (PendingLoads.size() == 1) {
600 SDOperand Root = PendingLoads[0];
602 PendingLoads.clear();
606 // Otherwise, we have to make a token factor node.
607 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
608 &PendingLoads[0], PendingLoads.size());
609 PendingLoads.clear();
614 /// getControlRoot - Similar to getRoot, but instead of flushing all the
615 /// PendingLoad items, flush all the PendingExports items. It is necessary
616 /// to do this before emitting a terminator instruction.
618 SDOperand getControlRoot() {
619 SDOperand Root = DAG.getRoot();
621 if (PendingExports.empty())
624 // Turn all of the CopyToReg chains into one factored node.
625 if (Root.getOpcode() != ISD::EntryToken) {
626 unsigned i = 0, e = PendingExports.size();
627 for (; i != e; ++i) {
628 assert(PendingExports[i].Val->getNumOperands() > 1);
629 if (PendingExports[i].Val->getOperand(0) == Root)
630 break; // Don't add the root if we already indirectly depend on it.
634 PendingExports.push_back(Root);
637 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
639 PendingExports.size());
640 PendingExports.clear();
645 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
647 void visit(Instruction &I) { visit(I.getOpcode(), I); }
649 void visit(unsigned Opcode, User &I) {
650 // Note: this doesn't use InstVisitor, because it has to work with
651 // ConstantExpr's in addition to instructions.
653 default: assert(0 && "Unknown instruction type encountered!");
655 // Build the switch statement using the Instruction.def file.
656 #define HANDLE_INST(NUM, OPCODE, CLASS) \
657 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
658 #include "llvm/Instruction.def"
662 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
664 SDOperand getValue(const Value *V);
666 void setValue(const Value *V, SDOperand NewN) {
667 SDOperand &N = NodeMap[V];
668 assert(N.Val == 0 && "Already set a value for this node!");
672 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
673 std::set<unsigned> &OutputRegs,
674 std::set<unsigned> &InputRegs);
676 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
677 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
679 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
680 void ExportFromCurrentBlock(Value *V);
681 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
682 MachineBasicBlock *LandingPad = NULL);
684 // Terminator instructions.
685 void visitRet(ReturnInst &I);
686 void visitBr(BranchInst &I);
687 void visitSwitch(SwitchInst &I);
688 void visitUnreachable(UnreachableInst &I) { /* noop */ }
690 // Helpers for visitSwitch
691 bool handleSmallSwitchRange(CaseRec& CR,
692 CaseRecVector& WorkList,
694 MachineBasicBlock* Default);
695 bool handleJTSwitchCase(CaseRec& CR,
696 CaseRecVector& WorkList,
698 MachineBasicBlock* Default);
699 bool handleBTSplitSwitchCase(CaseRec& CR,
700 CaseRecVector& WorkList,
702 MachineBasicBlock* Default);
703 bool handleBitTestsSwitchCase(CaseRec& CR,
704 CaseRecVector& WorkList,
706 MachineBasicBlock* Default);
707 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
708 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
709 void visitBitTestCase(MachineBasicBlock* NextMBB,
711 SelectionDAGISel::BitTestCase &B);
712 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
713 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
714 SelectionDAGISel::JumpTableHeader &JTH);
716 // These all get lowered before this pass.
717 void visitInvoke(InvokeInst &I);
718 void visitUnwind(UnwindInst &I);
720 void visitBinary(User &I, unsigned OpCode);
721 void visitShift(User &I, unsigned Opcode);
722 void visitAdd(User &I) {
723 if (I.getType()->isFPOrFPVector())
724 visitBinary(I, ISD::FADD);
726 visitBinary(I, ISD::ADD);
728 void visitSub(User &I);
729 void visitMul(User &I) {
730 if (I.getType()->isFPOrFPVector())
731 visitBinary(I, ISD::FMUL);
733 visitBinary(I, ISD::MUL);
735 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
736 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
737 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
738 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
739 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
740 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
741 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
742 void visitOr (User &I) { visitBinary(I, ISD::OR); }
743 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
744 void visitShl (User &I) { visitShift(I, ISD::SHL); }
745 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
746 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
747 void visitICmp(User &I);
748 void visitFCmp(User &I);
749 void visitVICmp(User &I);
750 void visitVFCmp(User &I);
751 // Visit the conversion instructions
752 void visitTrunc(User &I);
753 void visitZExt(User &I);
754 void visitSExt(User &I);
755 void visitFPTrunc(User &I);
756 void visitFPExt(User &I);
757 void visitFPToUI(User &I);
758 void visitFPToSI(User &I);
759 void visitUIToFP(User &I);
760 void visitSIToFP(User &I);
761 void visitPtrToInt(User &I);
762 void visitIntToPtr(User &I);
763 void visitBitCast(User &I);
765 void visitExtractElement(User &I);
766 void visitInsertElement(User &I);
767 void visitShuffleVector(User &I);
769 void visitExtractValue(ExtractValueInst &I);
770 void visitInsertValue(InsertValueInst &I);
772 void visitGetElementPtr(User &I);
773 void visitSelect(User &I);
775 void visitMalloc(MallocInst &I);
776 void visitFree(FreeInst &I);
777 void visitAlloca(AllocaInst &I);
778 void visitLoad(LoadInst &I);
779 void visitStore(StoreInst &I);
780 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
781 void visitCall(CallInst &I);
782 void visitInlineAsm(CallSite CS);
783 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
784 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
786 void visitVAStart(CallInst &I);
787 void visitVAArg(VAArgInst &I);
788 void visitVAEnd(CallInst &I);
789 void visitVACopy(CallInst &I);
791 void visitGetResult(GetResultInst &I);
793 void visitUserOp1(Instruction &I) {
794 assert(0 && "UserOp1 should not exist at instruction selection time!");
797 void visitUserOp2(Instruction &I) {
798 assert(0 && "UserOp2 should not exist at instruction selection time!");
803 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
806 } // end namespace llvm
809 /// getCopyFromParts - Create a value that contains the specified legal parts
810 /// combined into the value they represent. If the parts combine to a type
811 /// larger then ValueVT then AssertOp can be used to specify whether the extra
812 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
813 /// (ISD::AssertSext).
814 static SDOperand getCopyFromParts(SelectionDAG &DAG,
815 const SDOperand *Parts,
819 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
820 assert(NumParts > 0 && "No parts to assemble!");
821 TargetLowering &TLI = DAG.getTargetLoweringInfo();
822 SDOperand Val = Parts[0];
825 // Assemble the value from multiple parts.
826 if (!ValueVT.isVector()) {
827 unsigned PartBits = PartVT.getSizeInBits();
828 unsigned ValueBits = ValueVT.getSizeInBits();
830 // Assemble the power of 2 part.
831 unsigned RoundParts = NumParts & (NumParts - 1) ?
832 1 << Log2_32(NumParts) : NumParts;
833 unsigned RoundBits = PartBits * RoundParts;
834 MVT RoundVT = RoundBits == ValueBits ?
835 ValueVT : MVT::getIntegerVT(RoundBits);
838 if (RoundParts > 2) {
839 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
840 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
841 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
847 if (TLI.isBigEndian())
849 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
851 if (RoundParts < NumParts) {
852 // Assemble the trailing non-power-of-2 part.
853 unsigned OddParts = NumParts - RoundParts;
854 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
855 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
857 // Combine the round and odd parts.
859 if (TLI.isBigEndian())
861 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
862 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
863 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
864 DAG.getConstant(Lo.getValueType().getSizeInBits(),
865 TLI.getShiftAmountTy()));
866 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
867 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
870 // Handle a multi-element vector.
871 MVT IntermediateVT, RegisterVT;
872 unsigned NumIntermediates;
874 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
876 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
877 NumParts = NumRegs; // Silence a compiler warning.
878 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
879 assert(RegisterVT == Parts[0].getValueType() &&
880 "Part type doesn't match part!");
882 // Assemble the parts into intermediate operands.
883 SmallVector<SDOperand, 8> Ops(NumIntermediates);
884 if (NumIntermediates == NumParts) {
885 // If the register was not expanded, truncate or copy the value,
887 for (unsigned i = 0; i != NumParts; ++i)
888 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
889 PartVT, IntermediateVT);
890 } else if (NumParts > 0) {
891 // If the intermediate type was expanded, build the intermediate operands
893 assert(NumParts % NumIntermediates == 0 &&
894 "Must expand into a divisible number of parts!");
895 unsigned Factor = NumParts / NumIntermediates;
896 for (unsigned i = 0; i != NumIntermediates; ++i)
897 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
898 PartVT, IntermediateVT);
901 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
903 Val = DAG.getNode(IntermediateVT.isVector() ?
904 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
905 ValueVT, &Ops[0], NumIntermediates);
909 // There is now one part, held in Val. Correct it to match ValueVT.
910 PartVT = Val.getValueType();
912 if (PartVT == ValueVT)
915 if (PartVT.isVector()) {
916 assert(ValueVT.isVector() && "Unknown vector conversion!");
917 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
920 if (ValueVT.isVector()) {
921 assert(ValueVT.getVectorElementType() == PartVT &&
922 ValueVT.getVectorNumElements() == 1 &&
923 "Only trivial scalar-to-vector conversions should get here!");
924 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
927 if (PartVT.isInteger() &&
928 ValueVT.isInteger()) {
929 if (ValueVT.bitsLT(PartVT)) {
930 // For a truncate, see if we have any information to
931 // indicate whether the truncated bits will always be
932 // zero or sign-extension.
933 if (AssertOp != ISD::DELETED_NODE)
934 Val = DAG.getNode(AssertOp, PartVT, Val,
935 DAG.getValueType(ValueVT));
936 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
938 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
942 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
943 if (ValueVT.bitsLT(Val.getValueType()))
944 // FP_ROUND's are always exact here.
945 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
946 DAG.getIntPtrConstant(1));
947 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
950 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
951 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
953 assert(0 && "Unknown mismatch!");
957 /// getCopyToParts - Create a series of nodes that contain the specified value
958 /// split into legal parts. If the parts contain more bits than Val, then, for
959 /// integers, ExtendKind can be used to specify how to generate the extra bits.
960 static void getCopyToParts(SelectionDAG &DAG,
965 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
966 TargetLowering &TLI = DAG.getTargetLoweringInfo();
967 MVT PtrVT = TLI.getPointerTy();
968 MVT ValueVT = Val.getValueType();
969 unsigned PartBits = PartVT.getSizeInBits();
970 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
975 if (!ValueVT.isVector()) {
976 if (PartVT == ValueVT) {
977 assert(NumParts == 1 && "No-op copy with multiple parts!");
982 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
983 // If the parts cover more bits than the value has, promote the value.
984 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
985 assert(NumParts == 1 && "Do not know what to promote to!");
986 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
987 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
988 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
989 Val = DAG.getNode(ExtendKind, ValueVT, Val);
991 assert(0 && "Unknown mismatch!");
993 } else if (PartBits == ValueVT.getSizeInBits()) {
994 // Different types of the same size.
995 assert(NumParts == 1 && PartVT != ValueVT);
996 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
997 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
998 // If the parts cover less bits than value has, truncate the value.
999 if (PartVT.isInteger() && ValueVT.isInteger()) {
1000 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1001 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1003 assert(0 && "Unknown mismatch!");
1007 // The value may have changed - recompute ValueVT.
1008 ValueVT = Val.getValueType();
1009 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1010 "Failed to tile the value with PartVT!");
1012 if (NumParts == 1) {
1013 assert(PartVT == ValueVT && "Type conversion failed!");
1018 // Expand the value into multiple parts.
1019 if (NumParts & (NumParts - 1)) {
1020 // The number of parts is not a power of 2. Split off and copy the tail.
1021 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1022 "Do not know what to expand to!");
1023 unsigned RoundParts = 1 << Log2_32(NumParts);
1024 unsigned RoundBits = RoundParts * PartBits;
1025 unsigned OddParts = NumParts - RoundParts;
1026 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1027 DAG.getConstant(RoundBits,
1028 TLI.getShiftAmountTy()));
1029 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1030 if (TLI.isBigEndian())
1031 // The odd parts were reversed by getCopyToParts - unreverse them.
1032 std::reverse(Parts + RoundParts, Parts + NumParts);
1033 NumParts = RoundParts;
1034 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1035 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1038 // The number of parts is a power of 2. Repeatedly bisect the value using
1040 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1041 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1043 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1044 for (unsigned i = 0; i < NumParts; i += StepSize) {
1045 unsigned ThisBits = StepSize * PartBits / 2;
1046 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1047 SDOperand &Part0 = Parts[i];
1048 SDOperand &Part1 = Parts[i+StepSize/2];
1050 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1051 DAG.getConstant(1, PtrVT));
1052 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1053 DAG.getConstant(0, PtrVT));
1055 if (ThisBits == PartBits && ThisVT != PartVT) {
1056 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1057 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1062 if (TLI.isBigEndian())
1063 std::reverse(Parts, Parts + NumParts);
1069 if (NumParts == 1) {
1070 if (PartVT != ValueVT) {
1071 if (PartVT.isVector()) {
1072 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1074 assert(ValueVT.getVectorElementType() == PartVT &&
1075 ValueVT.getVectorNumElements() == 1 &&
1076 "Only trivial vector-to-scalar conversions should get here!");
1077 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1078 DAG.getConstant(0, PtrVT));
1086 // Handle a multi-element vector.
1087 MVT IntermediateVT, RegisterVT;
1088 unsigned NumIntermediates;
1090 DAG.getTargetLoweringInfo()
1091 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1093 unsigned NumElements = ValueVT.getVectorNumElements();
1095 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1096 NumParts = NumRegs; // Silence a compiler warning.
1097 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1099 // Split the vector into intermediate operands.
1100 SmallVector<SDOperand, 8> Ops(NumIntermediates);
1101 for (unsigned i = 0; i != NumIntermediates; ++i)
1102 if (IntermediateVT.isVector())
1103 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1104 IntermediateVT, Val,
1105 DAG.getConstant(i * (NumElements / NumIntermediates),
1108 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1109 IntermediateVT, Val,
1110 DAG.getConstant(i, PtrVT));
1112 // Split the intermediate operands into legal parts.
1113 if (NumParts == NumIntermediates) {
1114 // If the register was not expanded, promote or copy the value,
1116 for (unsigned i = 0; i != NumParts; ++i)
1117 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1118 } else if (NumParts > 0) {
1119 // If the intermediate type was expanded, split each the value into
1121 assert(NumParts % NumIntermediates == 0 &&
1122 "Must expand into a divisible number of parts!");
1123 unsigned Factor = NumParts / NumIntermediates;
1124 for (unsigned i = 0; i != NumIntermediates; ++i)
1125 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1130 SDOperand SelectionDAGLowering::getValue(const Value *V) {
1131 SDOperand &N = NodeMap[V];
1132 if (N.Val) return N;
1134 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1135 MVT VT = TLI.getValueType(V->getType(), true);
1137 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1138 return N = DAG.getConstant(CI->getValue(), VT);
1140 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1141 return N = DAG.getGlobalAddress(GV, VT);
1143 if (isa<ConstantPointerNull>(C))
1144 return N = DAG.getConstant(0, TLI.getPointerTy());
1146 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1147 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1149 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1150 !V->getType()->isAggregateType())
1151 return N = DAG.getNode(ISD::UNDEF, VT);
1153 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1154 visit(CE->getOpcode(), *CE);
1155 SDOperand N1 = NodeMap[V];
1156 assert(N1.Val && "visit didn't populate the ValueMap!");
1160 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1161 SmallVector<SDOperand, 4> Constants;
1162 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1164 SDNode *Val = getValue(*OI).Val;
1165 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1166 Constants.push_back(SDOperand(Val, i));
1168 return DAG.getMergeValues(&Constants[0], Constants.size());
1171 if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) {
1172 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1173 "Unknown array constant!");
1174 unsigned NumElts = ATy->getNumElements();
1176 return SDOperand(); // empty array
1177 MVT EltVT = TLI.getValueType(ATy->getElementType());
1178 SmallVector<SDOperand, 4> Constants(NumElts);
1179 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1180 if (isa<UndefValue>(C))
1181 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1182 else if (EltVT.isFloatingPoint())
1183 Constants[i] = DAG.getConstantFP(0, EltVT);
1185 Constants[i] = DAG.getConstant(0, EltVT);
1187 return DAG.getMergeValues(&Constants[0], Constants.size());
1190 if (const StructType *STy = dyn_cast<StructType>(C->getType())) {
1191 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1192 "Unknown struct constant!");
1193 unsigned NumElts = STy->getNumElements();
1195 return SDOperand(); // empty struct
1196 SmallVector<SDOperand, 4> Constants(NumElts);
1197 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1198 MVT EltVT = TLI.getValueType(STy->getElementType(i));
1199 if (isa<UndefValue>(C))
1200 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1201 else if (EltVT.isFloatingPoint())
1202 Constants[i] = DAG.getConstantFP(0, EltVT);
1204 Constants[i] = DAG.getConstant(0, EltVT);
1206 return DAG.getMergeValues(&Constants[0], Constants.size());
1209 const VectorType *VecTy = cast<VectorType>(V->getType());
1210 unsigned NumElements = VecTy->getNumElements();
1212 // Now that we know the number and type of the elements, get that number of
1213 // elements into the Ops array based on what kind of constant it is.
1214 SmallVector<SDOperand, 16> Ops;
1215 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1216 for (unsigned i = 0; i != NumElements; ++i)
1217 Ops.push_back(getValue(CP->getOperand(i)));
1219 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1220 "Unknown vector constant!");
1221 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1224 if (isa<UndefValue>(C))
1225 Op = DAG.getNode(ISD::UNDEF, EltVT);
1226 else if (EltVT.isFloatingPoint())
1227 Op = DAG.getConstantFP(0, EltVT);
1229 Op = DAG.getConstant(0, EltVT);
1230 Ops.assign(NumElements, Op);
1233 // Create a BUILD_VECTOR node.
1234 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1237 // If this is a static alloca, generate it as the frameindex instead of
1239 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1240 std::map<const AllocaInst*, int>::iterator SI =
1241 FuncInfo.StaticAllocaMap.find(AI);
1242 if (SI != FuncInfo.StaticAllocaMap.end())
1243 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1246 unsigned InReg = FuncInfo.ValueMap[V];
1247 assert(InReg && "Value not in map!");
1249 RegsForValue RFV(TLI, InReg, V->getType());
1250 SDOperand Chain = DAG.getEntryNode();
1251 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1255 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1256 if (I.getNumOperands() == 0) {
1257 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1261 SmallVector<SDOperand, 8> NewValues;
1262 NewValues.push_back(getControlRoot());
1263 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1264 SDOperand RetOp = getValue(I.getOperand(i));
1266 SmallVector<MVT, 4> ValueVTs;
1267 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1268 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1269 MVT VT = ValueVTs[j];
1271 // FIXME: C calling convention requires the return type to be promoted to
1272 // at least 32-bit. But this is not necessary for non-C calling conventions.
1273 if (VT.isInteger()) {
1274 MVT MinVT = TLI.getRegisterType(MVT::i32);
1275 if (VT.bitsLT(MinVT))
1279 unsigned NumParts = TLI.getNumRegisters(VT);
1280 MVT PartVT = TLI.getRegisterType(VT);
1281 SmallVector<SDOperand, 4> Parts(NumParts);
1282 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1284 const Function *F = I.getParent()->getParent();
1285 if (F->paramHasAttr(0, ParamAttr::SExt))
1286 ExtendKind = ISD::SIGN_EXTEND;
1287 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1288 ExtendKind = ISD::ZERO_EXTEND;
1290 getCopyToParts(DAG, SDOperand(RetOp.Val, RetOp.ResNo + j),
1291 &Parts[0], NumParts, PartVT, ExtendKind);
1293 for (unsigned i = 0; i < NumParts; ++i) {
1294 NewValues.push_back(Parts[i]);
1295 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1299 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1300 &NewValues[0], NewValues.size()));
1303 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1304 /// the current basic block, add it to ValueMap now so that we'll get a
1306 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1307 // No need to export constants.
1308 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1310 // Already exported?
1311 if (FuncInfo.isExportedInst(V)) return;
1313 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1314 CopyValueToVirtualRegister(V, Reg);
1317 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1318 const BasicBlock *FromBB) {
1319 // The operands of the setcc have to be in this block. We don't know
1320 // how to export them from some other block.
1321 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1322 // Can export from current BB.
1323 if (VI->getParent() == FromBB)
1326 // Is already exported, noop.
1327 return FuncInfo.isExportedInst(V);
1330 // If this is an argument, we can export it if the BB is the entry block or
1331 // if it is already exported.
1332 if (isa<Argument>(V)) {
1333 if (FromBB == &FromBB->getParent()->getEntryBlock())
1336 // Otherwise, can only export this if it is already exported.
1337 return FuncInfo.isExportedInst(V);
1340 // Otherwise, constants can always be exported.
1344 static bool InBlock(const Value *V, const BasicBlock *BB) {
1345 if (const Instruction *I = dyn_cast<Instruction>(V))
1346 return I->getParent() == BB;
1350 /// FindMergedConditions - If Cond is an expression like
1351 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1352 MachineBasicBlock *TBB,
1353 MachineBasicBlock *FBB,
1354 MachineBasicBlock *CurBB,
1356 // If this node is not part of the or/and tree, emit it as a branch.
1357 Instruction *BOp = dyn_cast<Instruction>(Cond);
1359 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1360 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1361 BOp->getParent() != CurBB->getBasicBlock() ||
1362 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1363 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1364 const BasicBlock *BB = CurBB->getBasicBlock();
1366 // If the leaf of the tree is a comparison, merge the condition into
1368 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1369 // The operands of the cmp have to be in this block. We don't know
1370 // how to export them from some other block. If this is the first block
1371 // of the sequence, no exporting is needed.
1373 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1374 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1375 BOp = cast<Instruction>(Cond);
1376 ISD::CondCode Condition;
1377 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1378 switch (IC->getPredicate()) {
1379 default: assert(0 && "Unknown icmp predicate opcode!");
1380 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1381 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1382 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1383 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1384 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1385 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1386 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1387 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1388 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1389 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1391 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1392 ISD::CondCode FPC, FOC;
1393 switch (FC->getPredicate()) {
1394 default: assert(0 && "Unknown fcmp predicate opcode!");
1395 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1396 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1397 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1398 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1399 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1400 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1401 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1402 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1403 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1404 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1405 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1406 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1407 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1408 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1409 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1410 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1412 if (FiniteOnlyFPMath())
1417 Condition = ISD::SETEQ; // silence warning.
1418 assert(0 && "Unknown compare instruction");
1421 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1422 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1423 SwitchCases.push_back(CB);
1427 // Create a CaseBlock record representing this branch.
1428 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1429 NULL, TBB, FBB, CurBB);
1430 SwitchCases.push_back(CB);
1435 // Create TmpBB after CurBB.
1436 MachineFunction::iterator BBI = CurBB;
1437 MachineFunction &MF = DAG.getMachineFunction();
1438 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1439 CurBB->getParent()->insert(++BBI, TmpBB);
1441 if (Opc == Instruction::Or) {
1442 // Codegen X | Y as:
1450 // Emit the LHS condition.
1451 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1453 // Emit the RHS condition into TmpBB.
1454 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1456 assert(Opc == Instruction::And && "Unknown merge op!");
1457 // Codegen X & Y as:
1464 // This requires creation of TmpBB after CurBB.
1466 // Emit the LHS condition.
1467 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1469 // Emit the RHS condition into TmpBB.
1470 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1474 /// If the set of cases should be emitted as a series of branches, return true.
1475 /// If we should emit this as a bunch of and/or'd together conditions, return
1478 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1479 if (Cases.size() != 2) return true;
1481 // If this is two comparisons of the same values or'd or and'd together, they
1482 // will get folded into a single comparison, so don't emit two blocks.
1483 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1484 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1485 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1486 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1493 void SelectionDAGLowering::visitBr(BranchInst &I) {
1494 // Update machine-CFG edges.
1495 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1497 // Figure out which block is immediately after the current one.
1498 MachineBasicBlock *NextBlock = 0;
1499 MachineFunction::iterator BBI = CurMBB;
1500 if (++BBI != CurMBB->getParent()->end())
1503 if (I.isUnconditional()) {
1504 // Update machine-CFG edges.
1505 CurMBB->addSuccessor(Succ0MBB);
1507 // If this is not a fall-through branch, emit the branch.
1508 if (Succ0MBB != NextBlock)
1509 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1510 DAG.getBasicBlock(Succ0MBB)));
1514 // If this condition is one of the special cases we handle, do special stuff
1516 Value *CondVal = I.getCondition();
1517 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1519 // If this is a series of conditions that are or'd or and'd together, emit
1520 // this as a sequence of branches instead of setcc's with and/or operations.
1521 // For example, instead of something like:
1534 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1535 if (BOp->hasOneUse() &&
1536 (BOp->getOpcode() == Instruction::And ||
1537 BOp->getOpcode() == Instruction::Or)) {
1538 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1539 // If the compares in later blocks need to use values not currently
1540 // exported from this block, export them now. This block should always
1541 // be the first entry.
1542 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1544 // Allow some cases to be rejected.
1545 if (ShouldEmitAsBranches(SwitchCases)) {
1546 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1547 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1548 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1551 // Emit the branch for this block.
1552 visitSwitchCase(SwitchCases[0]);
1553 SwitchCases.erase(SwitchCases.begin());
1557 // Okay, we decided not to do this, remove any inserted MBB's and clear
1559 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1560 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1562 SwitchCases.clear();
1566 // Create a CaseBlock record representing this branch.
1567 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1568 NULL, Succ0MBB, Succ1MBB, CurMBB);
1569 // Use visitSwitchCase to actually insert the fast branch sequence for this
1571 visitSwitchCase(CB);
1574 /// visitSwitchCase - Emits the necessary code to represent a single node in
1575 /// the binary search tree resulting from lowering a switch instruction.
1576 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1578 SDOperand CondLHS = getValue(CB.CmpLHS);
1580 // Build the setcc now.
1581 if (CB.CmpMHS == NULL) {
1582 // Fold "(X == true)" to X and "(X == false)" to !X to
1583 // handle common cases produced by branch lowering.
1584 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1586 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1587 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1588 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1590 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1592 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1594 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1595 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1597 SDOperand CmpOp = getValue(CB.CmpMHS);
1598 MVT VT = CmpOp.getValueType();
1600 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1601 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1603 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1604 Cond = DAG.getSetCC(MVT::i1, SUB,
1605 DAG.getConstant(High-Low, VT), ISD::SETULE);
1609 // Update successor info
1610 CurMBB->addSuccessor(CB.TrueBB);
1611 CurMBB->addSuccessor(CB.FalseBB);
1613 // Set NextBlock to be the MBB immediately after the current one, if any.
1614 // This is used to avoid emitting unnecessary branches to the next block.
1615 MachineBasicBlock *NextBlock = 0;
1616 MachineFunction::iterator BBI = CurMBB;
1617 if (++BBI != CurMBB->getParent()->end())
1620 // If the lhs block is the next block, invert the condition so that we can
1621 // fall through to the lhs instead of the rhs block.
1622 if (CB.TrueBB == NextBlock) {
1623 std::swap(CB.TrueBB, CB.FalseBB);
1624 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1625 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1627 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1628 DAG.getBasicBlock(CB.TrueBB));
1629 if (CB.FalseBB == NextBlock)
1630 DAG.setRoot(BrCond);
1632 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1633 DAG.getBasicBlock(CB.FalseBB)));
1636 /// visitJumpTable - Emit JumpTable node in the current MBB
1637 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1638 // Emit the code for the jump table
1639 assert(JT.Reg != -1U && "Should lower JT Header first!");
1640 MVT PTy = TLI.getPointerTy();
1641 SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1642 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1643 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1648 /// visitJumpTableHeader - This function emits necessary code to produce index
1649 /// in the JumpTable from switch case.
1650 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1651 SelectionDAGISel::JumpTableHeader &JTH) {
1652 // Subtract the lowest switch case value from the value being switched on
1653 // and conditional branch to default mbb if the result is greater than the
1654 // difference between smallest and largest cases.
1655 SDOperand SwitchOp = getValue(JTH.SValue);
1656 MVT VT = SwitchOp.getValueType();
1657 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1658 DAG.getConstant(JTH.First, VT));
1660 // The SDNode we just created, which holds the value being switched on
1661 // minus the the smallest case value, needs to be copied to a virtual
1662 // register so it can be used as an index into the jump table in a
1663 // subsequent basic block. This value may be smaller or larger than the
1664 // target's pointer type, and therefore require extension or truncating.
1665 if (VT.bitsGT(TLI.getPointerTy()))
1666 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1668 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1670 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1671 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1672 JT.Reg = JumpTableReg;
1674 // Emit the range check for the jump table, and branch to the default
1675 // block for the switch statement if the value being switched on exceeds
1676 // the largest case in the switch.
1677 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1678 DAG.getConstant(JTH.Last-JTH.First,VT),
1681 // Set NextBlock to be the MBB immediately after the current one, if any.
1682 // This is used to avoid emitting unnecessary branches to the next block.
1683 MachineBasicBlock *NextBlock = 0;
1684 MachineFunction::iterator BBI = CurMBB;
1685 if (++BBI != CurMBB->getParent()->end())
1688 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1689 DAG.getBasicBlock(JT.Default));
1691 if (JT.MBB == NextBlock)
1692 DAG.setRoot(BrCond);
1694 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1695 DAG.getBasicBlock(JT.MBB)));
1700 /// visitBitTestHeader - This function emits necessary code to produce value
1701 /// suitable for "bit tests"
1702 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1703 // Subtract the minimum value
1704 SDOperand SwitchOp = getValue(B.SValue);
1705 MVT VT = SwitchOp.getValueType();
1706 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1707 DAG.getConstant(B.First, VT));
1710 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1711 DAG.getConstant(B.Range, VT),
1715 if (VT.bitsGT(TLI.getShiftAmountTy()))
1716 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1718 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1720 // Make desired shift
1721 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1722 DAG.getConstant(1, TLI.getPointerTy()),
1725 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1726 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1729 // Set NextBlock to be the MBB immediately after the current one, if any.
1730 // This is used to avoid emitting unnecessary branches to the next block.
1731 MachineBasicBlock *NextBlock = 0;
1732 MachineFunction::iterator BBI = CurMBB;
1733 if (++BBI != CurMBB->getParent()->end())
1736 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1738 CurMBB->addSuccessor(B.Default);
1739 CurMBB->addSuccessor(MBB);
1741 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1742 DAG.getBasicBlock(B.Default));
1744 if (MBB == NextBlock)
1745 DAG.setRoot(BrRange);
1747 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1748 DAG.getBasicBlock(MBB)));
1753 /// visitBitTestCase - this function produces one "bit test"
1754 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1756 SelectionDAGISel::BitTestCase &B) {
1757 // Emit bit tests and jumps
1758 SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1759 TLI.getPointerTy());
1761 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1762 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1763 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1764 DAG.getConstant(0, TLI.getPointerTy()),
1767 CurMBB->addSuccessor(B.TargetBB);
1768 CurMBB->addSuccessor(NextMBB);
1770 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1771 AndCmp, DAG.getBasicBlock(B.TargetBB));
1773 // Set NextBlock to be the MBB immediately after the current one, if any.
1774 // This is used to avoid emitting unnecessary branches to the next block.
1775 MachineBasicBlock *NextBlock = 0;
1776 MachineFunction::iterator BBI = CurMBB;
1777 if (++BBI != CurMBB->getParent()->end())
1780 if (NextMBB == NextBlock)
1783 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1784 DAG.getBasicBlock(NextMBB)));
1789 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1790 // Retrieve successors.
1791 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1792 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1794 if (isa<InlineAsm>(I.getCalledValue()))
1797 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1799 // If the value of the invoke is used outside of its defining block, make it
1800 // available as a virtual register.
1801 if (!I.use_empty()) {
1802 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1803 if (VMI != FuncInfo.ValueMap.end())
1804 CopyValueToVirtualRegister(&I, VMI->second);
1807 // Update successor info
1808 CurMBB->addSuccessor(Return);
1809 CurMBB->addSuccessor(LandingPad);
1811 // Drop into normal successor.
1812 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1813 DAG.getBasicBlock(Return)));
1816 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1819 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1820 /// small case ranges).
1821 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1822 CaseRecVector& WorkList,
1824 MachineBasicBlock* Default) {
1825 Case& BackCase = *(CR.Range.second-1);
1827 // Size is the number of Cases represented by this range.
1828 unsigned Size = CR.Range.second - CR.Range.first;
1832 // Get the MachineFunction which holds the current MBB. This is used when
1833 // inserting any additional MBBs necessary to represent the switch.
1834 MachineFunction *CurMF = CurMBB->getParent();
1836 // Figure out which block is immediately after the current one.
1837 MachineBasicBlock *NextBlock = 0;
1838 MachineFunction::iterator BBI = CR.CaseBB;
1840 if (++BBI != CurMBB->getParent()->end())
1843 // TODO: If any two of the cases has the same destination, and if one value
1844 // is the same as the other, but has one bit unset that the other has set,
1845 // use bit manipulation to do two compares at once. For example:
1846 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1848 // Rearrange the case blocks so that the last one falls through if possible.
1849 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1850 // The last case block won't fall through into 'NextBlock' if we emit the
1851 // branches in this order. See if rearranging a case value would help.
1852 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1853 if (I->BB == NextBlock) {
1854 std::swap(*I, BackCase);
1860 // Create a CaseBlock record representing a conditional branch to
1861 // the Case's target mbb if the value being switched on SV is equal
1863 MachineBasicBlock *CurBlock = CR.CaseBB;
1864 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1865 MachineBasicBlock *FallThrough;
1867 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1868 CurMF->insert(BBI, FallThrough);
1870 // If the last case doesn't match, go to the default block.
1871 FallThrough = Default;
1874 Value *RHS, *LHS, *MHS;
1876 if (I->High == I->Low) {
1877 // This is just small small case range :) containing exactly 1 case
1879 LHS = SV; RHS = I->High; MHS = NULL;
1882 LHS = I->Low; MHS = SV; RHS = I->High;
1884 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1885 I->BB, FallThrough, CurBlock);
1887 // If emitting the first comparison, just call visitSwitchCase to emit the
1888 // code into the current block. Otherwise, push the CaseBlock onto the
1889 // vector to be later processed by SDISel, and insert the node's MBB
1890 // before the next MBB.
1891 if (CurBlock == CurMBB)
1892 visitSwitchCase(CB);
1894 SwitchCases.push_back(CB);
1896 CurBlock = FallThrough;
1902 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1903 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1904 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1907 /// handleJTSwitchCase - Emit jumptable for current switch case range
1908 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1909 CaseRecVector& WorkList,
1911 MachineBasicBlock* Default) {
1912 Case& FrontCase = *CR.Range.first;
1913 Case& BackCase = *(CR.Range.second-1);
1915 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1916 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1919 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1923 if (!areJTsAllowed(TLI) || TSize <= 3)
1926 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1930 DOUT << "Lowering jump table\n"
1931 << "First entry: " << First << ". Last entry: " << Last << "\n"
1932 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1934 // Get the MachineFunction which holds the current MBB. This is used when
1935 // inserting any additional MBBs necessary to represent the switch.
1936 MachineFunction *CurMF = CurMBB->getParent();
1938 // Figure out which block is immediately after the current one.
1939 MachineBasicBlock *NextBlock = 0;
1940 MachineFunction::iterator BBI = CR.CaseBB;
1942 if (++BBI != CurMBB->getParent()->end())
1945 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1947 // Create a new basic block to hold the code for loading the address
1948 // of the jump table, and jumping to it. Update successor information;
1949 // we will either branch to the default case for the switch, or the jump
1951 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1952 CurMF->insert(BBI, JumpTableBB);
1953 CR.CaseBB->addSuccessor(Default);
1954 CR.CaseBB->addSuccessor(JumpTableBB);
1956 // Build a vector of destination BBs, corresponding to each target
1957 // of the jump table. If the value of the jump table slot corresponds to
1958 // a case statement, push the case's BB onto the vector, otherwise, push
1960 std::vector<MachineBasicBlock*> DestBBs;
1961 int64_t TEI = First;
1962 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1963 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1964 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1966 if ((Low <= TEI) && (TEI <= High)) {
1967 DestBBs.push_back(I->BB);
1971 DestBBs.push_back(Default);
1975 // Update successor info. Add one edge to each unique successor.
1976 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1977 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1978 E = DestBBs.end(); I != E; ++I) {
1979 if (!SuccsHandled[(*I)->getNumber()]) {
1980 SuccsHandled[(*I)->getNumber()] = true;
1981 JumpTableBB->addSuccessor(*I);
1985 // Create a jump table index for this jump table, or return an existing
1987 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1989 // Set the jump table information so that we can codegen it as a second
1990 // MachineBasicBlock
1991 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1992 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1993 (CR.CaseBB == CurMBB));
1994 if (CR.CaseBB == CurMBB)
1995 visitJumpTableHeader(JT, JTH);
1997 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2002 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2004 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2005 CaseRecVector& WorkList,
2007 MachineBasicBlock* Default) {
2008 // Get the MachineFunction which holds the current MBB. This is used when
2009 // inserting any additional MBBs necessary to represent the switch.
2010 MachineFunction *CurMF = CurMBB->getParent();
2012 // Figure out which block is immediately after the current one.
2013 MachineBasicBlock *NextBlock = 0;
2014 MachineFunction::iterator BBI = CR.CaseBB;
2016 if (++BBI != CurMBB->getParent()->end())
2019 Case& FrontCase = *CR.Range.first;
2020 Case& BackCase = *(CR.Range.second-1);
2021 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2023 // Size is the number of Cases represented by this range.
2024 unsigned Size = CR.Range.second - CR.Range.first;
2026 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2027 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2029 CaseItr Pivot = CR.Range.first + Size/2;
2031 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2032 // (heuristically) allow us to emit JumpTable's later.
2034 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2038 uint64_t LSize = FrontCase.size();
2039 uint64_t RSize = TSize-LSize;
2040 DOUT << "Selecting best pivot: \n"
2041 << "First: " << First << ", Last: " << Last <<"\n"
2042 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2043 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2045 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2046 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2047 assert((RBegin-LEnd>=1) && "Invalid case distance");
2048 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2049 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2050 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2051 // Should always split in some non-trivial place
2053 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2054 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2055 << "Metric: " << Metric << "\n";
2056 if (FMetric < Metric) {
2059 DOUT << "Current metric set to: " << FMetric << "\n";
2065 if (areJTsAllowed(TLI)) {
2066 // If our case is dense we *really* should handle it earlier!
2067 assert((FMetric > 0) && "Should handle dense range earlier!");
2069 Pivot = CR.Range.first + Size/2;
2072 CaseRange LHSR(CR.Range.first, Pivot);
2073 CaseRange RHSR(Pivot, CR.Range.second);
2074 Constant *C = Pivot->Low;
2075 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2077 // We know that we branch to the LHS if the Value being switched on is
2078 // less than the Pivot value, C. We use this to optimize our binary
2079 // tree a bit, by recognizing that if SV is greater than or equal to the
2080 // LHS's Case Value, and that Case Value is exactly one less than the
2081 // Pivot's Value, then we can branch directly to the LHS's Target,
2082 // rather than creating a leaf node for it.
2083 if ((LHSR.second - LHSR.first) == 1 &&
2084 LHSR.first->High == CR.GE &&
2085 cast<ConstantInt>(C)->getSExtValue() ==
2086 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2087 TrueBB = LHSR.first->BB;
2089 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2090 CurMF->insert(BBI, TrueBB);
2091 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2094 // Similar to the optimization above, if the Value being switched on is
2095 // known to be less than the Constant CR.LT, and the current Case Value
2096 // is CR.LT - 1, then we can branch directly to the target block for
2097 // the current Case Value, rather than emitting a RHS leaf node for it.
2098 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2099 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2100 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2101 FalseBB = RHSR.first->BB;
2103 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2104 CurMF->insert(BBI, FalseBB);
2105 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2108 // Create a CaseBlock record representing a conditional branch to
2109 // the LHS node if the value being switched on SV is less than C.
2110 // Otherwise, branch to LHS.
2111 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2112 TrueBB, FalseBB, CR.CaseBB);
2114 if (CR.CaseBB == CurMBB)
2115 visitSwitchCase(CB);
2117 SwitchCases.push_back(CB);
2122 /// handleBitTestsSwitchCase - if current case range has few destination and
2123 /// range span less, than machine word bitwidth, encode case range into series
2124 /// of masks and emit bit tests with these masks.
2125 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2126 CaseRecVector& WorkList,
2128 MachineBasicBlock* Default){
2129 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2131 Case& FrontCase = *CR.Range.first;
2132 Case& BackCase = *(CR.Range.second-1);
2134 // Get the MachineFunction which holds the current MBB. This is used when
2135 // inserting any additional MBBs necessary to represent the switch.
2136 MachineFunction *CurMF = CurMBB->getParent();
2138 unsigned numCmps = 0;
2139 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2141 // Single case counts one, case range - two.
2142 if (I->Low == I->High)
2148 // Count unique destinations
2149 SmallSet<MachineBasicBlock*, 4> Dests;
2150 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2151 Dests.insert(I->BB);
2152 if (Dests.size() > 3)
2153 // Don't bother the code below, if there are too much unique destinations
2156 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2157 << "Total number of comparisons: " << numCmps << "\n";
2159 // Compute span of values.
2160 Constant* minValue = FrontCase.Low;
2161 Constant* maxValue = BackCase.High;
2162 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2163 cast<ConstantInt>(minValue)->getSExtValue();
2164 DOUT << "Compare range: " << range << "\n"
2165 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2166 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2168 if (range>=IntPtrBits ||
2169 (!(Dests.size() == 1 && numCmps >= 3) &&
2170 !(Dests.size() == 2 && numCmps >= 5) &&
2171 !(Dests.size() >= 3 && numCmps >= 6)))
2174 DOUT << "Emitting bit tests\n";
2175 int64_t lowBound = 0;
2177 // Optimize the case where all the case values fit in a
2178 // word without having to subtract minValue. In this case,
2179 // we can optimize away the subtraction.
2180 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2181 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2182 range = cast<ConstantInt>(maxValue)->getSExtValue();
2184 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2187 CaseBitsVector CasesBits;
2188 unsigned i, count = 0;
2190 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2191 MachineBasicBlock* Dest = I->BB;
2192 for (i = 0; i < count; ++i)
2193 if (Dest == CasesBits[i].BB)
2197 assert((count < 3) && "Too much destinations to test!");
2198 CasesBits.push_back(CaseBits(0, Dest, 0));
2202 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2203 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2205 for (uint64_t j = lo; j <= hi; j++) {
2206 CasesBits[i].Mask |= 1ULL << j;
2207 CasesBits[i].Bits++;
2211 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2213 SelectionDAGISel::BitTestInfo BTC;
2215 // Figure out which block is immediately after the current one.
2216 MachineFunction::iterator BBI = CR.CaseBB;
2219 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2222 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2223 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2224 << ", BB: " << CasesBits[i].BB << "\n";
2226 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2227 CurMF->insert(BBI, CaseBB);
2228 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2233 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2234 -1U, (CR.CaseBB == CurMBB),
2235 CR.CaseBB, Default, BTC);
2237 if (CR.CaseBB == CurMBB)
2238 visitBitTestHeader(BTB);
2240 BitTestCases.push_back(BTB);
2246 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2247 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2248 const SwitchInst& SI) {
2249 unsigned numCmps = 0;
2251 // Start with "simple" cases
2252 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2253 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2254 Cases.push_back(Case(SI.getSuccessorValue(i),
2255 SI.getSuccessorValue(i),
2258 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2260 // Merge case into clusters
2261 if (Cases.size()>=2)
2262 // Must recompute end() each iteration because it may be
2263 // invalidated by erase if we hold on to it
2264 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2265 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2266 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2267 MachineBasicBlock* nextBB = J->BB;
2268 MachineBasicBlock* currentBB = I->BB;
2270 // If the two neighboring cases go to the same destination, merge them
2271 // into a single case.
2272 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2280 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2281 if (I->Low != I->High)
2282 // A range counts double, since it requires two compares.
2289 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2290 // Figure out which block is immediately after the current one.
2291 MachineBasicBlock *NextBlock = 0;
2292 MachineFunction::iterator BBI = CurMBB;
2294 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2296 // If there is only the default destination, branch to it if it is not the
2297 // next basic block. Otherwise, just fall through.
2298 if (SI.getNumOperands() == 2) {
2299 // Update machine-CFG edges.
2301 // If this is not a fall-through branch, emit the branch.
2302 CurMBB->addSuccessor(Default);
2303 if (Default != NextBlock)
2304 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2305 DAG.getBasicBlock(Default)));
2310 // If there are any non-default case statements, create a vector of Cases
2311 // representing each one, and sort the vector so that we can efficiently
2312 // create a binary search tree from them.
2314 unsigned numCmps = Clusterify(Cases, SI);
2315 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2316 << ". Total compares: " << numCmps << "\n";
2318 // Get the Value to be switched on and default basic blocks, which will be
2319 // inserted into CaseBlock records, representing basic blocks in the binary
2321 Value *SV = SI.getOperand(0);
2323 // Push the initial CaseRec onto the worklist
2324 CaseRecVector WorkList;
2325 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2327 while (!WorkList.empty()) {
2328 // Grab a record representing a case range to process off the worklist
2329 CaseRec CR = WorkList.back();
2330 WorkList.pop_back();
2332 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2335 // If the range has few cases (two or less) emit a series of specific
2337 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2340 // If the switch has more than 5 blocks, and at least 40% dense, and the
2341 // target supports indirect branches, then emit a jump table rather than
2342 // lowering the switch to a binary tree of conditional branches.
2343 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2346 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2347 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2348 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2353 void SelectionDAGLowering::visitSub(User &I) {
2354 // -0.0 - X --> fneg
2355 const Type *Ty = I.getType();
2356 if (isa<VectorType>(Ty)) {
2357 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2358 const VectorType *DestTy = cast<VectorType>(I.getType());
2359 const Type *ElTy = DestTy->getElementType();
2360 if (ElTy->isFloatingPoint()) {
2361 unsigned VL = DestTy->getNumElements();
2362 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2363 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2365 SDOperand Op2 = getValue(I.getOperand(1));
2366 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2372 if (Ty->isFloatingPoint()) {
2373 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2374 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2375 SDOperand Op2 = getValue(I.getOperand(1));
2376 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2381 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2384 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2385 SDOperand Op1 = getValue(I.getOperand(0));
2386 SDOperand Op2 = getValue(I.getOperand(1));
2388 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2391 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2392 SDOperand Op1 = getValue(I.getOperand(0));
2393 SDOperand Op2 = getValue(I.getOperand(1));
2395 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2396 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2397 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2398 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2400 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2403 void SelectionDAGLowering::visitICmp(User &I) {
2404 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2405 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2406 predicate = IC->getPredicate();
2407 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2408 predicate = ICmpInst::Predicate(IC->getPredicate());
2409 SDOperand Op1 = getValue(I.getOperand(0));
2410 SDOperand Op2 = getValue(I.getOperand(1));
2411 ISD::CondCode Opcode;
2412 switch (predicate) {
2413 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2414 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2415 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2416 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2417 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2418 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2419 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2420 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2421 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2422 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2424 assert(!"Invalid ICmp predicate value");
2425 Opcode = ISD::SETEQ;
2428 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2431 void SelectionDAGLowering::visitFCmp(User &I) {
2432 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2433 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2434 predicate = FC->getPredicate();
2435 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2436 predicate = FCmpInst::Predicate(FC->getPredicate());
2437 SDOperand Op1 = getValue(I.getOperand(0));
2438 SDOperand Op2 = getValue(I.getOperand(1));
2439 ISD::CondCode Condition, FOC, FPC;
2440 switch (predicate) {
2441 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2442 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2443 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2444 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2445 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2446 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2447 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2448 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2449 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2450 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2451 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2452 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2453 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2454 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2455 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2456 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2458 assert(!"Invalid FCmp predicate value");
2459 FOC = FPC = ISD::SETFALSE;
2462 if (FiniteOnlyFPMath())
2466 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2469 void SelectionDAGLowering::visitVICmp(User &I) {
2470 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2471 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2472 predicate = IC->getPredicate();
2473 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2474 predicate = ICmpInst::Predicate(IC->getPredicate());
2475 SDOperand Op1 = getValue(I.getOperand(0));
2476 SDOperand Op2 = getValue(I.getOperand(1));
2477 ISD::CondCode Opcode;
2478 switch (predicate) {
2479 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2480 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2481 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2482 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2483 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2484 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2485 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2486 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2487 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2488 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2490 assert(!"Invalid ICmp predicate value");
2491 Opcode = ISD::SETEQ;
2494 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2497 void SelectionDAGLowering::visitVFCmp(User &I) {
2498 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2499 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2500 predicate = FC->getPredicate();
2501 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2502 predicate = FCmpInst::Predicate(FC->getPredicate());
2503 SDOperand Op1 = getValue(I.getOperand(0));
2504 SDOperand Op2 = getValue(I.getOperand(1));
2505 ISD::CondCode Condition, FOC, FPC;
2506 switch (predicate) {
2507 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2508 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2509 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2510 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2511 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2512 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2513 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2514 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2515 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2516 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2517 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2518 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2519 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2520 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2521 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2522 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2524 assert(!"Invalid VFCmp predicate value");
2525 FOC = FPC = ISD::SETFALSE;
2528 if (FiniteOnlyFPMath())
2533 MVT DestVT = TLI.getValueType(I.getType());
2535 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2538 void SelectionDAGLowering::visitSelect(User &I) {
2539 SDOperand Cond = getValue(I.getOperand(0));
2540 SDOperand TrueVal = getValue(I.getOperand(1));
2541 SDOperand FalseVal = getValue(I.getOperand(2));
2542 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2543 TrueVal, FalseVal));
2547 void SelectionDAGLowering::visitTrunc(User &I) {
2548 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2549 SDOperand N = getValue(I.getOperand(0));
2550 MVT DestVT = TLI.getValueType(I.getType());
2551 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2554 void SelectionDAGLowering::visitZExt(User &I) {
2555 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2556 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2557 SDOperand N = getValue(I.getOperand(0));
2558 MVT DestVT = TLI.getValueType(I.getType());
2559 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2562 void SelectionDAGLowering::visitSExt(User &I) {
2563 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2564 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2565 SDOperand N = getValue(I.getOperand(0));
2566 MVT DestVT = TLI.getValueType(I.getType());
2567 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2570 void SelectionDAGLowering::visitFPTrunc(User &I) {
2571 // FPTrunc is never a no-op cast, no need to check
2572 SDOperand N = getValue(I.getOperand(0));
2573 MVT DestVT = TLI.getValueType(I.getType());
2574 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2577 void SelectionDAGLowering::visitFPExt(User &I){
2578 // FPTrunc is never a no-op cast, no need to check
2579 SDOperand N = getValue(I.getOperand(0));
2580 MVT DestVT = TLI.getValueType(I.getType());
2581 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2584 void SelectionDAGLowering::visitFPToUI(User &I) {
2585 // FPToUI is never a no-op cast, no need to check
2586 SDOperand N = getValue(I.getOperand(0));
2587 MVT DestVT = TLI.getValueType(I.getType());
2588 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2591 void SelectionDAGLowering::visitFPToSI(User &I) {
2592 // FPToSI is never a no-op cast, no need to check
2593 SDOperand N = getValue(I.getOperand(0));
2594 MVT DestVT = TLI.getValueType(I.getType());
2595 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2598 void SelectionDAGLowering::visitUIToFP(User &I) {
2599 // UIToFP is never a no-op cast, no need to check
2600 SDOperand N = getValue(I.getOperand(0));
2601 MVT DestVT = TLI.getValueType(I.getType());
2602 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2605 void SelectionDAGLowering::visitSIToFP(User &I){
2606 // UIToFP is never a no-op cast, no need to check
2607 SDOperand N = getValue(I.getOperand(0));
2608 MVT DestVT = TLI.getValueType(I.getType());
2609 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2612 void SelectionDAGLowering::visitPtrToInt(User &I) {
2613 // What to do depends on the size of the integer and the size of the pointer.
2614 // We can either truncate, zero extend, or no-op, accordingly.
2615 SDOperand N = getValue(I.getOperand(0));
2616 MVT SrcVT = N.getValueType();
2617 MVT DestVT = TLI.getValueType(I.getType());
2619 if (DestVT.bitsLT(SrcVT))
2620 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2622 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2623 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2624 setValue(&I, Result);
2627 void SelectionDAGLowering::visitIntToPtr(User &I) {
2628 // What to do depends on the size of the integer and the size of the pointer.
2629 // We can either truncate, zero extend, or no-op, accordingly.
2630 SDOperand N = getValue(I.getOperand(0));
2631 MVT SrcVT = N.getValueType();
2632 MVT DestVT = TLI.getValueType(I.getType());
2633 if (DestVT.bitsLT(SrcVT))
2634 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2636 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2637 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2640 void SelectionDAGLowering::visitBitCast(User &I) {
2641 SDOperand N = getValue(I.getOperand(0));
2642 MVT DestVT = TLI.getValueType(I.getType());
2644 // BitCast assures us that source and destination are the same size so this
2645 // is either a BIT_CONVERT or a no-op.
2646 if (DestVT != N.getValueType())
2647 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2649 setValue(&I, N); // noop cast.
2652 void SelectionDAGLowering::visitInsertElement(User &I) {
2653 SDOperand InVec = getValue(I.getOperand(0));
2654 SDOperand InVal = getValue(I.getOperand(1));
2655 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2656 getValue(I.getOperand(2)));
2658 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2659 TLI.getValueType(I.getType()),
2660 InVec, InVal, InIdx));
2663 void SelectionDAGLowering::visitExtractElement(User &I) {
2664 SDOperand InVec = getValue(I.getOperand(0));
2665 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2666 getValue(I.getOperand(1)));
2667 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2668 TLI.getValueType(I.getType()), InVec, InIdx));
2671 void SelectionDAGLowering::visitShuffleVector(User &I) {
2672 SDOperand V1 = getValue(I.getOperand(0));
2673 SDOperand V2 = getValue(I.getOperand(1));
2674 SDOperand Mask = getValue(I.getOperand(2));
2676 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2677 TLI.getValueType(I.getType()),
2681 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2682 const Value *Op0 = I.getOperand(0);
2683 const Value *Op1 = I.getOperand(1);
2684 const Type *AggTy = I.getType();
2685 const Type *ValTy = Op1->getType();
2686 bool IntoUndef = isa<UndefValue>(Op0);
2687 bool FromUndef = isa<UndefValue>(Op1);
2689 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2690 I.idx_begin(), I.idx_end());
2692 SmallVector<MVT, 4> AggValueVTs;
2693 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2694 SmallVector<MVT, 4> ValValueVTs;
2695 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2697 unsigned NumAggValues = AggValueVTs.size();
2698 unsigned NumValValues = ValValueVTs.size();
2699 SmallVector<SDOperand, 4> Values(NumAggValues);
2701 SDOperand Agg = getValue(Op0);
2702 SDOperand Val = getValue(Op1);
2704 // Copy the beginning value(s) from the original aggregate.
2705 for (; i != LinearIndex; ++i)
2706 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2707 SDOperand(Agg.Val, Agg.ResNo + i);
2708 // Copy values from the inserted value(s).
2709 for (; i != LinearIndex + NumValValues; ++i)
2710 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2711 SDOperand(Val.Val, Val.ResNo + i - LinearIndex);
2712 // Copy remaining value(s) from the original aggregate.
2713 for (; i != NumAggValues; ++i)
2714 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2715 SDOperand(Agg.Val, Agg.ResNo + i);
2717 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2718 &Values[0], NumAggValues));
2721 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2722 const Value *Op0 = I.getOperand(0);
2723 const Type *AggTy = Op0->getType();
2724 const Type *ValTy = I.getType();
2725 bool OutOfUndef = isa<UndefValue>(Op0);
2727 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2728 I.idx_begin(), I.idx_end());
2730 SmallVector<MVT, 4> ValValueVTs;
2731 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2733 unsigned NumValValues = ValValueVTs.size();
2734 SmallVector<SDOperand, 4> Values(NumValValues);
2736 SDOperand Agg = getValue(Op0);
2737 // Copy out the selected value(s).
2738 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2739 Values[i - LinearIndex] =
2740 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2741 SDOperand(Agg.Val, Agg.ResNo + i);
2743 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2744 &Values[0], NumValValues));
2748 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2749 SDOperand N = getValue(I.getOperand(0));
2750 const Type *Ty = I.getOperand(0)->getType();
2752 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2755 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2756 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2759 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2760 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2761 DAG.getIntPtrConstant(Offset));
2763 Ty = StTy->getElementType(Field);
2765 Ty = cast<SequentialType>(Ty)->getElementType();
2767 // If this is a constant subscript, handle it quickly.
2768 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2769 if (CI->getZExtValue() == 0) continue;
2771 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2772 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2773 DAG.getIntPtrConstant(Offs));
2777 // N = N + Idx * ElementSize;
2778 uint64_t ElementSize = TD->getABITypeSize(Ty);
2779 SDOperand IdxN = getValue(Idx);
2781 // If the index is smaller or larger than intptr_t, truncate or extend
2783 if (IdxN.getValueType().bitsLT(N.getValueType())) {
2784 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2785 } else if (IdxN.getValueType().bitsGT(N.getValueType()))
2786 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2788 // If this is a multiply by a power of two, turn it into a shl
2789 // immediately. This is a very common case.
2790 if (isPowerOf2_64(ElementSize)) {
2791 unsigned Amt = Log2_64(ElementSize);
2792 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2793 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2794 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2798 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2799 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2800 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2806 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2807 // If this is a fixed sized alloca in the entry block of the function,
2808 // allocate it statically on the stack.
2809 if (FuncInfo.StaticAllocaMap.count(&I))
2810 return; // getValue will auto-populate this.
2812 const Type *Ty = I.getAllocatedType();
2813 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2815 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2818 SDOperand AllocSize = getValue(I.getArraySize());
2819 MVT IntPtr = TLI.getPointerTy();
2820 if (IntPtr.bitsLT(AllocSize.getValueType()))
2821 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2822 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2823 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2825 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2826 DAG.getIntPtrConstant(TySize));
2828 // Handle alignment. If the requested alignment is less than or equal to
2829 // the stack alignment, ignore it. If the size is greater than or equal to
2830 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2831 unsigned StackAlign =
2832 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2833 if (Align <= StackAlign)
2836 // Round the size of the allocation up to the stack alignment size
2837 // by add SA-1 to the size.
2838 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2839 DAG.getIntPtrConstant(StackAlign-1));
2840 // Mask out the low bits for alignment purposes.
2841 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2842 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2844 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2845 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2847 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2849 DAG.setRoot(DSA.getValue(1));
2851 // Inform the Frame Information that we have just allocated a variable-sized
2853 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2856 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2857 const Value *SV = I.getOperand(0);
2858 SDOperand Ptr = getValue(SV);
2860 const Type *Ty = I.getType();
2861 bool isVolatile = I.isVolatile();
2862 unsigned Alignment = I.getAlignment();
2864 SmallVector<MVT, 4> ValueVTs;
2865 SmallVector<uint64_t, 4> Offsets;
2866 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2867 unsigned NumValues = ValueVTs.size();
2875 // Do not serialize non-volatile loads against each other.
2876 Root = DAG.getRoot();
2879 SmallVector<SDOperand, 4> Values(NumValues);
2880 SmallVector<SDOperand, 4> Chains(NumValues);
2881 MVT PtrVT = Ptr.getValueType();
2882 for (unsigned i = 0; i != NumValues; ++i) {
2883 SDOperand L = DAG.getLoad(ValueVTs[i], Root,
2884 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2885 DAG.getConstant(Offsets[i], PtrVT)),
2887 isVolatile, Alignment);
2889 Chains[i] = L.getValue(1);
2892 SDOperand Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2893 &Chains[0], NumValues);
2897 PendingLoads.push_back(Chain);
2899 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2900 &Values[0], NumValues));
2904 void SelectionDAGLowering::visitStore(StoreInst &I) {
2905 Value *SrcV = I.getOperand(0);
2906 SDOperand Src = getValue(SrcV);
2907 Value *PtrV = I.getOperand(1);
2908 SDOperand Ptr = getValue(PtrV);
2910 SmallVector<MVT, 4> ValueVTs;
2911 SmallVector<uint64_t, 4> Offsets;
2912 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2913 unsigned NumValues = ValueVTs.size();
2917 SDOperand Root = getRoot();
2918 SmallVector<SDOperand, 4> Chains(NumValues);
2919 MVT PtrVT = Ptr.getValueType();
2920 bool isVolatile = I.isVolatile();
2921 unsigned Alignment = I.getAlignment();
2922 for (unsigned i = 0; i != NumValues; ++i)
2923 Chains[i] = DAG.getStore(Root, SDOperand(Src.Val, Src.ResNo + i),
2924 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2925 DAG.getConstant(Offsets[i], PtrVT)),
2927 isVolatile, Alignment);
2929 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2932 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2934 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2935 unsigned Intrinsic) {
2936 bool HasChain = !I.doesNotAccessMemory();
2937 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2939 // Build the operand list.
2940 SmallVector<SDOperand, 8> Ops;
2941 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2943 // We don't need to serialize loads against other loads.
2944 Ops.push_back(DAG.getRoot());
2946 Ops.push_back(getRoot());
2950 // Add the intrinsic ID as an integer operand.
2951 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2953 // Add all operands of the call to the operand list.
2954 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2955 SDOperand Op = getValue(I.getOperand(i));
2956 assert(TLI.isTypeLegal(Op.getValueType()) &&
2957 "Intrinsic uses a non-legal type?");
2961 std::vector<MVT> VTs;
2962 if (I.getType() != Type::VoidTy) {
2963 MVT VT = TLI.getValueType(I.getType());
2964 if (VT.isVector()) {
2965 const VectorType *DestTy = cast<VectorType>(I.getType());
2966 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2968 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2969 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2972 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2976 VTs.push_back(MVT::Other);
2978 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2983 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2984 &Ops[0], Ops.size());
2985 else if (I.getType() != Type::VoidTy)
2986 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2987 &Ops[0], Ops.size());
2989 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2990 &Ops[0], Ops.size());
2993 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2995 PendingLoads.push_back(Chain);
2999 if (I.getType() != Type::VoidTy) {
3000 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3001 MVT VT = TLI.getValueType(PTy);
3002 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3004 setValue(&I, Result);
3008 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3009 static GlobalVariable *ExtractTypeInfo (Value *V) {
3010 V = V->stripPointerCasts();
3011 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3012 assert ((GV || isa<ConstantPointerNull>(V)) &&
3013 "TypeInfo must be a global variable or NULL");
3017 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3018 /// call, and add them to the specified machine basic block.
3019 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3020 MachineBasicBlock *MBB) {
3021 // Inform the MachineModuleInfo of the personality for this landing pad.
3022 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3023 assert(CE->getOpcode() == Instruction::BitCast &&
3024 isa<Function>(CE->getOperand(0)) &&
3025 "Personality should be a function");
3026 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3028 // Gather all the type infos for this landing pad and pass them along to
3029 // MachineModuleInfo.
3030 std::vector<GlobalVariable *> TyInfo;
3031 unsigned N = I.getNumOperands();
3033 for (unsigned i = N - 1; i > 2; --i) {
3034 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3035 unsigned FilterLength = CI->getZExtValue();
3036 unsigned FirstCatch = i + FilterLength + !FilterLength;
3037 assert (FirstCatch <= N && "Invalid filter length");
3039 if (FirstCatch < N) {
3040 TyInfo.reserve(N - FirstCatch);
3041 for (unsigned j = FirstCatch; j < N; ++j)
3042 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3043 MMI->addCatchTypeInfo(MBB, TyInfo);
3047 if (!FilterLength) {
3049 MMI->addCleanup(MBB);
3052 TyInfo.reserve(FilterLength - 1);
3053 for (unsigned j = i + 1; j < FirstCatch; ++j)
3054 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3055 MMI->addFilterTypeInfo(MBB, TyInfo);
3064 TyInfo.reserve(N - 3);
3065 for (unsigned j = 3; j < N; ++j)
3066 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3067 MMI->addCatchTypeInfo(MBB, TyInfo);
3072 /// Inlined utility function to implement binary input atomic intrinsics for
3073 // visitIntrinsicCall: I is a call instruction
3074 // Op is the associated NodeType for I
3076 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3077 SDOperand Root = getRoot();
3078 SDOperand L = DAG.getAtomic(Op, Root,
3079 getValue(I.getOperand(1)),
3080 getValue(I.getOperand(2)),
3083 DAG.setRoot(L.getValue(1));
3087 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3088 /// we want to emit this as a call to a named external function, return the name
3089 /// otherwise lower it and return null.
3091 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3092 switch (Intrinsic) {
3094 // By default, turn this into a target intrinsic node.
3095 visitTargetIntrinsic(I, Intrinsic);
3097 case Intrinsic::vastart: visitVAStart(I); return 0;
3098 case Intrinsic::vaend: visitVAEnd(I); return 0;
3099 case Intrinsic::vacopy: visitVACopy(I); return 0;
3100 case Intrinsic::returnaddress:
3101 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3102 getValue(I.getOperand(1))));
3104 case Intrinsic::frameaddress:
3105 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3106 getValue(I.getOperand(1))));
3108 case Intrinsic::setjmp:
3109 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3111 case Intrinsic::longjmp:
3112 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3114 case Intrinsic::memcpy_i32:
3115 case Intrinsic::memcpy_i64: {
3116 SDOperand Op1 = getValue(I.getOperand(1));
3117 SDOperand Op2 = getValue(I.getOperand(2));
3118 SDOperand Op3 = getValue(I.getOperand(3));
3119 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3120 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3121 I.getOperand(1), 0, I.getOperand(2), 0));
3124 case Intrinsic::memset_i32:
3125 case Intrinsic::memset_i64: {
3126 SDOperand Op1 = getValue(I.getOperand(1));
3127 SDOperand Op2 = getValue(I.getOperand(2));
3128 SDOperand Op3 = getValue(I.getOperand(3));
3129 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3130 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3131 I.getOperand(1), 0));
3134 case Intrinsic::memmove_i32:
3135 case Intrinsic::memmove_i64: {
3136 SDOperand Op1 = getValue(I.getOperand(1));
3137 SDOperand Op2 = getValue(I.getOperand(2));
3138 SDOperand Op3 = getValue(I.getOperand(3));
3139 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3141 // If the source and destination are known to not be aliases, we can
3142 // lower memmove as memcpy.
3143 uint64_t Size = -1ULL;
3144 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3145 Size = C->getValue();
3146 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3147 AliasAnalysis::NoAlias) {
3148 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3149 I.getOperand(1), 0, I.getOperand(2), 0));
3153 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3154 I.getOperand(1), 0, I.getOperand(2), 0));
3157 case Intrinsic::dbg_stoppoint: {
3158 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3159 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3160 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3161 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3162 assert(DD && "Not a debug information descriptor");
3163 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3166 cast<CompileUnitDesc>(DD)));
3171 case Intrinsic::dbg_region_start: {
3172 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3173 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3174 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3175 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3176 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3181 case Intrinsic::dbg_region_end: {
3182 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3183 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3184 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3185 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3186 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3191 case Intrinsic::dbg_func_start: {
3192 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3194 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3195 Value *SP = FSI.getSubprogram();
3196 if (SP && MMI->Verify(SP)) {
3197 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3198 // what (most?) gdb expects.
3199 DebugInfoDesc *DD = MMI->getDescFor(SP);
3200 assert(DD && "Not a debug information descriptor");
3201 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3202 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3203 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3204 // Record the source line but does create a label. It will be emitted
3205 // at asm emission time.
3206 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3211 case Intrinsic::dbg_declare: {
3212 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3213 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3214 Value *Variable = DI.getVariable();
3215 if (MMI && Variable && MMI->Verify(Variable))
3216 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3217 getValue(DI.getAddress()), getValue(Variable)));
3221 case Intrinsic::eh_exception: {
3222 if (!CurMBB->isLandingPad()) {
3223 // FIXME: Mark exception register as live in. Hack for PR1508.
3224 unsigned Reg = TLI.getExceptionAddressRegister();
3225 if (Reg) CurMBB->addLiveIn(Reg);
3227 // Insert the EXCEPTIONADDR instruction.
3228 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3230 Ops[0] = DAG.getRoot();
3231 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3233 DAG.setRoot(Op.getValue(1));
3237 case Intrinsic::eh_selector_i32:
3238 case Intrinsic::eh_selector_i64: {
3239 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3240 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3241 MVT::i32 : MVT::i64);
3244 if (CurMBB->isLandingPad())
3245 addCatchInfo(I, MMI, CurMBB);
3248 FuncInfo.CatchInfoLost.insert(&I);
3250 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3251 unsigned Reg = TLI.getExceptionSelectorRegister();
3252 if (Reg) CurMBB->addLiveIn(Reg);
3255 // Insert the EHSELECTION instruction.
3256 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3258 Ops[0] = getValue(I.getOperand(1));
3260 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3262 DAG.setRoot(Op.getValue(1));
3264 setValue(&I, DAG.getConstant(0, VT));
3270 case Intrinsic::eh_typeid_for_i32:
3271 case Intrinsic::eh_typeid_for_i64: {
3272 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3273 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3274 MVT::i32 : MVT::i64);
3277 // Find the type id for the given typeinfo.
3278 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3280 unsigned TypeID = MMI->getTypeIDFor(GV);
3281 setValue(&I, DAG.getConstant(TypeID, VT));
3283 // Return something different to eh_selector.
3284 setValue(&I, DAG.getConstant(1, VT));
3290 case Intrinsic::eh_return: {
3291 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3294 MMI->setCallsEHReturn(true);
3295 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3298 getValue(I.getOperand(1)),
3299 getValue(I.getOperand(2))));
3301 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3307 case Intrinsic::eh_unwind_init: {
3308 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3309 MMI->setCallsUnwindInit(true);
3315 case Intrinsic::eh_dwarf_cfa: {
3316 MVT VT = getValue(I.getOperand(1)).getValueType();
3318 if (VT.bitsGT(TLI.getPointerTy()))
3319 CfaArg = DAG.getNode(ISD::TRUNCATE,
3320 TLI.getPointerTy(), getValue(I.getOperand(1)));
3322 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3323 TLI.getPointerTy(), getValue(I.getOperand(1)));
3325 SDOperand Offset = DAG.getNode(ISD::ADD,
3327 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3328 TLI.getPointerTy()),
3330 setValue(&I, DAG.getNode(ISD::ADD,
3332 DAG.getNode(ISD::FRAMEADDR,
3335 TLI.getPointerTy())),
3340 case Intrinsic::sqrt:
3341 setValue(&I, DAG.getNode(ISD::FSQRT,
3342 getValue(I.getOperand(1)).getValueType(),
3343 getValue(I.getOperand(1))));
3345 case Intrinsic::powi:
3346 setValue(&I, DAG.getNode(ISD::FPOWI,
3347 getValue(I.getOperand(1)).getValueType(),
3348 getValue(I.getOperand(1)),
3349 getValue(I.getOperand(2))));
3351 case Intrinsic::sin:
3352 setValue(&I, DAG.getNode(ISD::FSIN,
3353 getValue(I.getOperand(1)).getValueType(),
3354 getValue(I.getOperand(1))));
3356 case Intrinsic::cos:
3357 setValue(&I, DAG.getNode(ISD::FCOS,
3358 getValue(I.getOperand(1)).getValueType(),
3359 getValue(I.getOperand(1))));
3361 case Intrinsic::pow:
3362 setValue(&I, DAG.getNode(ISD::FPOW,
3363 getValue(I.getOperand(1)).getValueType(),
3364 getValue(I.getOperand(1)),
3365 getValue(I.getOperand(2))));
3367 case Intrinsic::pcmarker: {
3368 SDOperand Tmp = getValue(I.getOperand(1));
3369 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3372 case Intrinsic::readcyclecounter: {
3373 SDOperand Op = getRoot();
3374 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3375 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3378 DAG.setRoot(Tmp.getValue(1));
3381 case Intrinsic::part_select: {
3382 // Currently not implemented: just abort
3383 assert(0 && "part_select intrinsic not implemented");
3386 case Intrinsic::part_set: {
3387 // Currently not implemented: just abort
3388 assert(0 && "part_set intrinsic not implemented");
3391 case Intrinsic::bswap:
3392 setValue(&I, DAG.getNode(ISD::BSWAP,
3393 getValue(I.getOperand(1)).getValueType(),
3394 getValue(I.getOperand(1))));
3396 case Intrinsic::cttz: {
3397 SDOperand Arg = getValue(I.getOperand(1));
3398 MVT Ty = Arg.getValueType();
3399 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3400 setValue(&I, result);
3403 case Intrinsic::ctlz: {
3404 SDOperand Arg = getValue(I.getOperand(1));
3405 MVT Ty = Arg.getValueType();
3406 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3407 setValue(&I, result);
3410 case Intrinsic::ctpop: {
3411 SDOperand Arg = getValue(I.getOperand(1));
3412 MVT Ty = Arg.getValueType();
3413 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3414 setValue(&I, result);
3417 case Intrinsic::stacksave: {
3418 SDOperand Op = getRoot();
3419 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
3420 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3422 DAG.setRoot(Tmp.getValue(1));
3425 case Intrinsic::stackrestore: {
3426 SDOperand Tmp = getValue(I.getOperand(1));
3427 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3430 case Intrinsic::var_annotation:
3431 // Discard annotate attributes
3434 case Intrinsic::init_trampoline: {
3435 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3439 Ops[1] = getValue(I.getOperand(1));
3440 Ops[2] = getValue(I.getOperand(2));
3441 Ops[3] = getValue(I.getOperand(3));
3442 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3443 Ops[5] = DAG.getSrcValue(F);
3445 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3446 DAG.getNodeValueTypes(TLI.getPointerTy(),
3451 DAG.setRoot(Tmp.getValue(1));
3455 case Intrinsic::gcroot:
3457 Value *Alloca = I.getOperand(1);
3458 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3460 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3461 GCI->addStackRoot(FI->getIndex(), TypeMap);
3465 case Intrinsic::gcread:
3466 case Intrinsic::gcwrite:
3467 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3470 case Intrinsic::flt_rounds: {
3471 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3475 case Intrinsic::trap: {
3476 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3479 case Intrinsic::prefetch: {
3482 Ops[1] = getValue(I.getOperand(1));
3483 Ops[2] = getValue(I.getOperand(2));
3484 Ops[3] = getValue(I.getOperand(3));
3485 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3489 case Intrinsic::memory_barrier: {
3492 for (int x = 1; x < 6; ++x)
3493 Ops[x] = getValue(I.getOperand(x));
3495 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3498 case Intrinsic::atomic_cmp_swap: {
3499 SDOperand Root = getRoot();
3500 SDOperand L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
3501 getValue(I.getOperand(1)),
3502 getValue(I.getOperand(2)),
3503 getValue(I.getOperand(3)),
3506 DAG.setRoot(L.getValue(1));
3509 case Intrinsic::atomic_load_add:
3510 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3511 case Intrinsic::atomic_load_sub:
3512 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
3513 case Intrinsic::atomic_load_and:
3514 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3515 case Intrinsic::atomic_load_or:
3516 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3517 case Intrinsic::atomic_load_xor:
3518 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3519 case Intrinsic::atomic_load_nand:
3520 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3521 case Intrinsic::atomic_load_min:
3522 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3523 case Intrinsic::atomic_load_max:
3524 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3525 case Intrinsic::atomic_load_umin:
3526 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3527 case Intrinsic::atomic_load_umax:
3528 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3529 case Intrinsic::atomic_swap:
3530 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3535 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3537 MachineBasicBlock *LandingPad) {
3538 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3539 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3540 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3541 unsigned BeginLabel = 0, EndLabel = 0;
3543 TargetLowering::ArgListTy Args;
3544 TargetLowering::ArgListEntry Entry;
3545 Args.reserve(CS.arg_size());
3546 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3548 SDOperand ArgNode = getValue(*i);
3549 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3551 unsigned attrInd = i - CS.arg_begin() + 1;
3552 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3553 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3554 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3555 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3556 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3557 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3558 Entry.Alignment = CS.getParamAlignment(attrInd);
3559 Args.push_back(Entry);
3562 if (LandingPad && MMI) {
3563 // Insert a label before the invoke call to mark the try range. This can be
3564 // used to detect deletion of the invoke via the MachineModuleInfo.
3565 BeginLabel = MMI->NextLabelID();
3566 // Both PendingLoads and PendingExports must be flushed here;
3567 // this call might not return.
3569 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
3572 std::pair<SDOperand,SDOperand> Result =
3573 TLI.LowerCallTo(getRoot(), CS.getType(),
3574 CS.paramHasAttr(0, ParamAttr::SExt),
3575 CS.paramHasAttr(0, ParamAttr::ZExt),
3576 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3578 if (CS.getType() != Type::VoidTy)
3579 setValue(CS.getInstruction(), Result.first);
3580 DAG.setRoot(Result.second);
3582 if (LandingPad && MMI) {
3583 // Insert a label at the end of the invoke call to mark the try range. This
3584 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3585 EndLabel = MMI->NextLabelID();
3586 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
3588 // Inform MachineModuleInfo of range.
3589 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3594 void SelectionDAGLowering::visitCall(CallInst &I) {
3595 const char *RenameFn = 0;
3596 if (Function *F = I.getCalledFunction()) {
3597 if (F->isDeclaration()) {
3598 if (unsigned IID = F->getIntrinsicID()) {
3599 RenameFn = visitIntrinsicCall(I, IID);
3605 // Check for well-known libc/libm calls. If the function is internal, it
3606 // can't be a library call.
3607 unsigned NameLen = F->getNameLen();
3608 if (!F->hasInternalLinkage() && NameLen) {
3609 const char *NameStr = F->getNameStart();
3610 if (NameStr[0] == 'c' &&
3611 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3612 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3613 if (I.getNumOperands() == 3 && // Basic sanity checks.
3614 I.getOperand(1)->getType()->isFloatingPoint() &&
3615 I.getType() == I.getOperand(1)->getType() &&
3616 I.getType() == I.getOperand(2)->getType()) {
3617 SDOperand LHS = getValue(I.getOperand(1));
3618 SDOperand RHS = getValue(I.getOperand(2));
3619 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3623 } else if (NameStr[0] == 'f' &&
3624 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3625 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3626 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3627 if (I.getNumOperands() == 2 && // Basic sanity checks.
3628 I.getOperand(1)->getType()->isFloatingPoint() &&
3629 I.getType() == I.getOperand(1)->getType()) {
3630 SDOperand Tmp = getValue(I.getOperand(1));
3631 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3634 } else if (NameStr[0] == 's' &&
3635 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3636 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3637 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3638 if (I.getNumOperands() == 2 && // Basic sanity checks.
3639 I.getOperand(1)->getType()->isFloatingPoint() &&
3640 I.getType() == I.getOperand(1)->getType()) {
3641 SDOperand Tmp = getValue(I.getOperand(1));
3642 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3645 } else if (NameStr[0] == 'c' &&
3646 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3647 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3648 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3649 if (I.getNumOperands() == 2 && // Basic sanity checks.
3650 I.getOperand(1)->getType()->isFloatingPoint() &&
3651 I.getType() == I.getOperand(1)->getType()) {
3652 SDOperand Tmp = getValue(I.getOperand(1));
3653 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3658 } else if (isa<InlineAsm>(I.getOperand(0))) {
3665 Callee = getValue(I.getOperand(0));
3667 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3669 LowerCallTo(&I, Callee, I.isTailCall());
3673 void SelectionDAGLowering::visitGetResult(GetResultInst &I) {
3674 if (isa<UndefValue>(I.getOperand(0))) {
3675 SDOperand Undef = DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType()));
3676 setValue(&I, Undef);
3680 // To add support for individual return values with aggregate types,
3681 // we'd need a way to take a getresult index and determine which
3682 // values of the Call SDNode are associated with it.
3683 assert(TLI.getValueType(I.getType(), true) != MVT::Other &&
3684 "Individual return values must not be aggregates!");
3686 SDOperand Call = getValue(I.getOperand(0));
3687 setValue(&I, SDOperand(Call.Val, I.getIndex()));
3691 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3692 /// this value and returns the result as a ValueVT value. This uses
3693 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3694 /// If the Flag pointer is NULL, no flag is used.
3695 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3697 SDOperand *Flag) const {
3698 // Assemble the legal parts into the final values.
3699 SmallVector<SDOperand, 4> Values(ValueVTs.size());
3700 SmallVector<SDOperand, 8> Parts;
3701 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3702 // Copy the legal parts from the registers.
3703 MVT ValueVT = ValueVTs[Value];
3704 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3705 MVT RegisterVT = RegVTs[Value];
3707 Parts.resize(NumRegs);
3708 for (unsigned i = 0; i != NumRegs; ++i) {
3711 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3713 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3714 *Flag = P.getValue(2);
3716 Chain = P.getValue(1);
3718 // If the source register was virtual and if we know something about it,
3719 // add an assert node.
3720 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3721 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3722 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3723 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3724 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3725 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3727 unsigned RegSize = RegisterVT.getSizeInBits();
3728 unsigned NumSignBits = LOI.NumSignBits;
3729 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3731 // FIXME: We capture more information than the dag can represent. For
3732 // now, just use the tightest assertzext/assertsext possible.
3734 MVT FromVT(MVT::Other);
3735 if (NumSignBits == RegSize)
3736 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3737 else if (NumZeroBits >= RegSize-1)
3738 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3739 else if (NumSignBits > RegSize-8)
3740 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3741 else if (NumZeroBits >= RegSize-9)
3742 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3743 else if (NumSignBits > RegSize-16)
3744 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3745 else if (NumZeroBits >= RegSize-17)
3746 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3747 else if (NumSignBits > RegSize-32)
3748 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3749 else if (NumZeroBits >= RegSize-33)
3750 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3752 if (FromVT != MVT::Other) {
3753 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3754 RegisterVT, P, DAG.getValueType(FromVT));
3763 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3768 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3769 &Values[0], ValueVTs.size());
3772 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3773 /// specified value into the registers specified by this object. This uses
3774 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3775 /// If the Flag pointer is NULL, no flag is used.
3776 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3777 SDOperand &Chain, SDOperand *Flag) const {
3778 // Get the list of the values's legal parts.
3779 unsigned NumRegs = Regs.size();
3780 SmallVector<SDOperand, 8> Parts(NumRegs);
3781 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3782 MVT ValueVT = ValueVTs[Value];
3783 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3784 MVT RegisterVT = RegVTs[Value];
3786 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3787 &Parts[Part], NumParts, RegisterVT);
3791 // Copy the parts into the registers.
3792 SmallVector<SDOperand, 8> Chains(NumRegs);
3793 for (unsigned i = 0; i != NumRegs; ++i) {
3796 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3798 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3799 *Flag = Part.getValue(1);
3801 Chains[i] = Part.getValue(0);
3804 if (NumRegs == 1 || Flag)
3805 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3806 // flagged to it. That is the CopyToReg nodes and the user are considered
3807 // a single scheduling unit. If we create a TokenFactor and return it as
3808 // chain, then the TokenFactor is both a predecessor (operand) of the
3809 // user as well as a successor (the TF operands are flagged to the user).
3810 // c1, f1 = CopyToReg
3811 // c2, f2 = CopyToReg
3812 // c3 = TokenFactor c1, c2
3815 Chain = Chains[NumRegs-1];
3817 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3820 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3821 /// operand list. This adds the code marker and includes the number of
3822 /// values added into it.
3823 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3824 std::vector<SDOperand> &Ops) const {
3825 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3826 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3827 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3828 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3829 MVT RegisterVT = RegVTs[Value];
3830 for (unsigned i = 0; i != NumRegs; ++i)
3831 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3835 /// isAllocatableRegister - If the specified register is safe to allocate,
3836 /// i.e. it isn't a stack pointer or some other special register, return the
3837 /// register class for the register. Otherwise, return null.
3838 static const TargetRegisterClass *
3839 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3840 const TargetLowering &TLI,
3841 const TargetRegisterInfo *TRI) {
3842 MVT FoundVT = MVT::Other;
3843 const TargetRegisterClass *FoundRC = 0;
3844 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3845 E = TRI->regclass_end(); RCI != E; ++RCI) {
3846 MVT ThisVT = MVT::Other;
3848 const TargetRegisterClass *RC = *RCI;
3849 // If none of the the value types for this register class are valid, we
3850 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3851 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3853 if (TLI.isTypeLegal(*I)) {
3854 // If we have already found this register in a different register class,
3855 // choose the one with the largest VT specified. For example, on
3856 // PowerPC, we favor f64 register classes over f32.
3857 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3864 if (ThisVT == MVT::Other) continue;
3866 // NOTE: This isn't ideal. In particular, this might allocate the
3867 // frame pointer in functions that need it (due to them not being taken
3868 // out of allocation, because a variable sized allocation hasn't been seen
3869 // yet). This is a slight code pessimization, but should still work.
3870 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3871 E = RC->allocation_order_end(MF); I != E; ++I)
3873 // We found a matching register class. Keep looking at others in case
3874 // we find one with larger registers that this physreg is also in.
3885 /// AsmOperandInfo - This contains information for each constraint that we are
3887 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3888 /// CallOperand - If this is the result output operand or a clobber
3889 /// this is null, otherwise it is the incoming operand to the CallInst.
3890 /// This gets modified as the asm is processed.
3891 SDOperand CallOperand;
3893 /// AssignedRegs - If this is a register or register class operand, this
3894 /// contains the set of register corresponding to the operand.
3895 RegsForValue AssignedRegs;
3897 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3898 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3901 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3902 /// busy in OutputRegs/InputRegs.
3903 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3904 std::set<unsigned> &OutputRegs,
3905 std::set<unsigned> &InputRegs,
3906 const TargetRegisterInfo &TRI) const {
3908 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3909 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3912 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3913 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3918 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3920 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3921 const TargetRegisterInfo &TRI) {
3922 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3924 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3925 for (; *Aliases; ++Aliases)
3926 Regs.insert(*Aliases);
3929 } // end anon namespace.
3932 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3933 /// specified operand. We prefer to assign virtual registers, to allow the
3934 /// register allocator handle the assignment process. However, if the asm uses
3935 /// features that we can't model on machineinstrs, we have SDISel do the
3936 /// allocation. This produces generally horrible, but correct, code.
3938 /// OpInfo describes the operand.
3939 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3940 /// or any explicitly clobbered registers.
3941 /// Input and OutputRegs are the set of already allocated physical registers.
3943 void SelectionDAGLowering::
3944 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3945 std::set<unsigned> &OutputRegs,
3946 std::set<unsigned> &InputRegs) {
3947 // Compute whether this value requires an input register, an output register,
3949 bool isOutReg = false;
3950 bool isInReg = false;
3951 switch (OpInfo.Type) {
3952 case InlineAsm::isOutput:
3955 // If this is an early-clobber output, or if there is an input
3956 // constraint that matches this, we need to reserve the input register
3957 // so no other inputs allocate to it.
3958 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3960 case InlineAsm::isInput:
3964 case InlineAsm::isClobber:
3971 MachineFunction &MF = DAG.getMachineFunction();
3972 SmallVector<unsigned, 4> Regs;
3974 // If this is a constraint for a single physreg, or a constraint for a
3975 // register class, find it.
3976 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3977 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3978 OpInfo.ConstraintVT);
3980 unsigned NumRegs = 1;
3981 if (OpInfo.ConstraintVT != MVT::Other)
3982 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3984 MVT ValueVT = OpInfo.ConstraintVT;
3987 // If this is a constraint for a specific physical register, like {r17},
3989 if (PhysReg.first) {
3990 if (OpInfo.ConstraintVT == MVT::Other)
3991 ValueVT = *PhysReg.second->vt_begin();
3993 // Get the actual register value type. This is important, because the user
3994 // may have asked for (e.g.) the AX register in i32 type. We need to
3995 // remember that AX is actually i16 to get the right extension.
3996 RegVT = *PhysReg.second->vt_begin();
3998 // This is a explicit reference to a physical register.
3999 Regs.push_back(PhysReg.first);
4001 // If this is an expanded reference, add the rest of the regs to Regs.
4003 TargetRegisterClass::iterator I = PhysReg.second->begin();
4004 for (; *I != PhysReg.first; ++I)
4005 assert(I != PhysReg.second->end() && "Didn't find reg!");
4007 // Already added the first reg.
4009 for (; NumRegs; --NumRegs, ++I) {
4010 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4014 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4015 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4016 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4020 // Otherwise, if this was a reference to an LLVM register class, create vregs
4021 // for this reference.
4022 std::vector<unsigned> RegClassRegs;
4023 const TargetRegisterClass *RC = PhysReg.second;
4025 // If this is an early clobber or tied register, our regalloc doesn't know
4026 // how to maintain the constraint. If it isn't, go ahead and create vreg
4027 // and let the regalloc do the right thing.
4028 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4029 // If there is some other early clobber and this is an input register,
4030 // then we are forced to pre-allocate the input reg so it doesn't
4031 // conflict with the earlyclobber.
4032 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4033 RegVT = *PhysReg.second->vt_begin();
4035 if (OpInfo.ConstraintVT == MVT::Other)
4038 // Create the appropriate number of virtual registers.
4039 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4040 for (; NumRegs; --NumRegs)
4041 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4043 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4047 // Otherwise, we can't allocate it. Let the code below figure out how to
4048 // maintain these constraints.
4049 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4052 // This is a reference to a register class that doesn't directly correspond
4053 // to an LLVM register class. Allocate NumRegs consecutive, available,
4054 // registers from the class.
4055 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4056 OpInfo.ConstraintVT);
4059 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4060 unsigned NumAllocated = 0;
4061 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4062 unsigned Reg = RegClassRegs[i];
4063 // See if this register is available.
4064 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4065 (isInReg && InputRegs.count(Reg))) { // Already used.
4066 // Make sure we find consecutive registers.
4071 // Check to see if this register is allocatable (i.e. don't give out the
4074 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4075 if (!RC) { // Couldn't allocate this register.
4076 // Reset NumAllocated to make sure we return consecutive registers.
4082 // Okay, this register is good, we can use it.
4085 // If we allocated enough consecutive registers, succeed.
4086 if (NumAllocated == NumRegs) {
4087 unsigned RegStart = (i-NumAllocated)+1;
4088 unsigned RegEnd = i+1;
4089 // Mark all of the allocated registers used.
4090 for (unsigned i = RegStart; i != RegEnd; ++i)
4091 Regs.push_back(RegClassRegs[i]);
4093 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4094 OpInfo.ConstraintVT);
4095 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4100 // Otherwise, we couldn't allocate enough registers for this.
4104 /// visitInlineAsm - Handle a call to an InlineAsm object.
4106 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4107 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4109 /// ConstraintOperands - Information about all of the constraints.
4110 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4112 SDOperand Chain = getRoot();
4115 std::set<unsigned> OutputRegs, InputRegs;
4117 // Do a prepass over the constraints, canonicalizing them, and building up the
4118 // ConstraintOperands list.
4119 std::vector<InlineAsm::ConstraintInfo>
4120 ConstraintInfos = IA->ParseConstraints();
4122 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4123 // constraint. If so, we can't let the register allocator allocate any input
4124 // registers, because it will not know to avoid the earlyclobbered output reg.
4125 bool SawEarlyClobber = false;
4127 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4128 unsigned ResNo = 0; // ResNo - The result number of the next output.
4129 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4130 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4131 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4133 MVT OpVT = MVT::Other;
4135 // Compute the value type for each operand.
4136 switch (OpInfo.Type) {
4137 case InlineAsm::isOutput:
4138 // Indirect outputs just consume an argument.
4139 if (OpInfo.isIndirect) {
4140 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4143 // The return value of the call is this value. As such, there is no
4144 // corresponding argument.
4145 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4146 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4147 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4149 assert(ResNo == 0 && "Asm only has one result!");
4150 OpVT = TLI.getValueType(CS.getType());
4154 case InlineAsm::isInput:
4155 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4157 case InlineAsm::isClobber:
4162 // If this is an input or an indirect output, process the call argument.
4163 // BasicBlocks are labels, currently appearing only in asm's.
4164 if (OpInfo.CallOperandVal) {
4165 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4166 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4168 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4169 const Type *OpTy = OpInfo.CallOperandVal->getType();
4170 // If this is an indirect operand, the operand is a pointer to the
4172 if (OpInfo.isIndirect)
4173 OpTy = cast<PointerType>(OpTy)->getElementType();
4175 // If OpTy is not a single value, it may be a struct/union that we
4176 // can tile with integers.
4177 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4178 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4186 OpTy = IntegerType::get(BitSize);
4191 OpVT = TLI.getValueType(OpTy, true);
4195 OpInfo.ConstraintVT = OpVT;
4197 // Compute the constraint code and ConstraintType to use.
4198 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4200 // Keep track of whether we see an earlyclobber.
4201 SawEarlyClobber |= OpInfo.isEarlyClobber;
4203 // If we see a clobber of a register, it is an early clobber.
4204 if (!SawEarlyClobber &&
4205 OpInfo.Type == InlineAsm::isClobber &&
4206 OpInfo.ConstraintType == TargetLowering::C_Register) {
4207 // Note that we want to ignore things that we don't trick here, like
4208 // dirflag, fpsr, flags, etc.
4209 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4210 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4211 OpInfo.ConstraintVT);
4212 if (PhysReg.first || PhysReg.second) {
4213 // This is a register we know of.
4214 SawEarlyClobber = true;
4218 // If this is a memory input, and if the operand is not indirect, do what we
4219 // need to to provide an address for the memory input.
4220 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4221 !OpInfo.isIndirect) {
4222 assert(OpInfo.Type == InlineAsm::isInput &&
4223 "Can only indirectify direct input operands!");
4225 // Memory operands really want the address of the value. If we don't have
4226 // an indirect input, put it in the constpool if we can, otherwise spill
4227 // it to a stack slot.
4229 // If the operand is a float, integer, or vector constant, spill to a
4230 // constant pool entry to get its address.
4231 Value *OpVal = OpInfo.CallOperandVal;
4232 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4233 isa<ConstantVector>(OpVal)) {
4234 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4235 TLI.getPointerTy());
4237 // Otherwise, create a stack slot and emit a store to it before the
4239 const Type *Ty = OpVal->getType();
4240 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4241 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4242 MachineFunction &MF = DAG.getMachineFunction();
4243 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4244 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4245 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4246 OpInfo.CallOperand = StackSlot;
4249 // There is no longer a Value* corresponding to this operand.
4250 OpInfo.CallOperandVal = 0;
4251 // It is now an indirect operand.
4252 OpInfo.isIndirect = true;
4255 // If this constraint is for a specific register, allocate it before
4257 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4258 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4260 ConstraintInfos.clear();
4263 // Second pass - Loop over all of the operands, assigning virtual or physregs
4264 // to registerclass operands.
4265 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4266 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4268 // C_Register operands have already been allocated, Other/Memory don't need
4270 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4271 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4274 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4275 std::vector<SDOperand> AsmNodeOperands;
4276 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
4277 AsmNodeOperands.push_back(
4278 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4281 // Loop over all of the inputs, copying the operand values into the
4282 // appropriate registers and processing the output regs.
4283 RegsForValue RetValRegs;
4285 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4286 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4288 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4289 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4291 switch (OpInfo.Type) {
4292 case InlineAsm::isOutput: {
4293 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4294 OpInfo.ConstraintType != TargetLowering::C_Register) {
4295 // Memory output, or 'other' output (e.g. 'X' constraint).
4296 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4298 // Add information to the INLINEASM node to know about this output.
4299 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4300 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4301 TLI.getPointerTy()));
4302 AsmNodeOperands.push_back(OpInfo.CallOperand);
4306 // Otherwise, this is a register or register class output.
4308 // Copy the output from the appropriate register. Find a register that
4310 if (OpInfo.AssignedRegs.Regs.empty()) {
4311 cerr << "Couldn't allocate output reg for constraint '"
4312 << OpInfo.ConstraintCode << "'!\n";
4316 // If this is an indirect operand, store through the pointer after the
4318 if (OpInfo.isIndirect) {
4319 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4320 OpInfo.CallOperandVal));
4322 // This is the result value of the call.
4323 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4324 // Concatenate this output onto the outputs list.
4325 RetValRegs.append(OpInfo.AssignedRegs);
4328 // Add information to the INLINEASM node to know that this register is
4330 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4334 case InlineAsm::isInput: {
4335 SDOperand InOperandVal = OpInfo.CallOperand;
4337 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4338 // If this is required to match an output register we have already set,
4339 // just use its register.
4340 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4342 // Scan until we find the definition we already emitted of this operand.
4343 // When we find it, create a RegsForValue operand.
4344 unsigned CurOp = 2; // The first operand.
4345 for (; OperandNo; --OperandNo) {
4346 // Advance to the next operand.
4348 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4349 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4350 (NumOps & 7) == 4 /*MEM*/) &&
4351 "Skipped past definitions?");
4352 CurOp += (NumOps>>3)+1;
4356 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4357 if ((NumOps & 7) == 2 /*REGDEF*/) {
4358 // Add NumOps>>3 registers to MatchedRegs.
4359 RegsForValue MatchedRegs;
4360 MatchedRegs.TLI = &TLI;
4361 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4362 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4363 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4365 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4366 MatchedRegs.Regs.push_back(Reg);
4369 // Use the produced MatchedRegs object to
4370 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4371 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4374 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4375 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4376 // Add information to the INLINEASM node to know about this input.
4377 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4378 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4379 TLI.getPointerTy()));
4380 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4385 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4386 assert(!OpInfo.isIndirect &&
4387 "Don't know how to handle indirect other inputs yet!");
4389 std::vector<SDOperand> Ops;
4390 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4393 cerr << "Invalid operand for inline asm constraint '"
4394 << OpInfo.ConstraintCode << "'!\n";
4398 // Add information to the INLINEASM node to know about this input.
4399 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4400 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4401 TLI.getPointerTy()));
4402 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4404 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4405 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4406 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4407 "Memory operands expect pointer values");
4409 // Add information to the INLINEASM node to know about this input.
4410 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4411 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4412 TLI.getPointerTy()));
4413 AsmNodeOperands.push_back(InOperandVal);
4417 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4418 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4419 "Unknown constraint type!");
4420 assert(!OpInfo.isIndirect &&
4421 "Don't know how to handle indirect register inputs yet!");
4423 // Copy the input into the appropriate registers.
4424 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4425 "Couldn't allocate input reg!");
4427 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4429 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4433 case InlineAsm::isClobber: {
4434 // Add the clobbered value to the operand list, so that the register
4435 // allocator is aware that the physreg got clobbered.
4436 if (!OpInfo.AssignedRegs.Regs.empty())
4437 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4444 // Finish up input operands.
4445 AsmNodeOperands[0] = Chain;
4446 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4448 Chain = DAG.getNode(ISD::INLINEASM,
4449 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4450 &AsmNodeOperands[0], AsmNodeOperands.size());
4451 Flag = Chain.getValue(1);
4453 // If this asm returns a register value, copy the result from that register
4454 // and set it as the value of the call.
4455 if (!RetValRegs.Regs.empty()) {
4456 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4458 // If any of the results of the inline asm is a vector, it may have the
4459 // wrong width/num elts. This can happen for register classes that can
4460 // contain multiple different value types. The preg or vreg allocated may
4461 // not have the same VT as was expected. Convert it to the right type with
4463 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4464 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4465 if (Val.Val->getValueType(i).isVector())
4466 Val = DAG.getNode(ISD::BIT_CONVERT,
4467 TLI.getValueType(ResSTy->getElementType(i)), Val);
4470 if (Val.getValueType().isVector())
4471 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4475 setValue(CS.getInstruction(), Val);
4478 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
4480 // Process indirect outputs, first output all of the flagged copies out of
4482 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4483 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4484 Value *Ptr = IndirectStoresToEmit[i].second;
4485 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4486 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4489 // Emit the non-flagged stores from the physregs.
4490 SmallVector<SDOperand, 8> OutChains;
4491 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4492 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4493 getValue(StoresToEmit[i].second),
4494 StoresToEmit[i].second, 0));
4495 if (!OutChains.empty())
4496 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4497 &OutChains[0], OutChains.size());
4502 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4503 SDOperand Src = getValue(I.getOperand(0));
4505 MVT IntPtr = TLI.getPointerTy();
4507 if (IntPtr.bitsLT(Src.getValueType()))
4508 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4509 else if (IntPtr.bitsGT(Src.getValueType()))
4510 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4512 // Scale the source by the type size.
4513 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4514 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4515 Src, DAG.getIntPtrConstant(ElementSize));
4517 TargetLowering::ArgListTy Args;
4518 TargetLowering::ArgListEntry Entry;
4520 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4521 Args.push_back(Entry);
4523 std::pair<SDOperand,SDOperand> Result =
4524 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4525 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4526 setValue(&I, Result.first); // Pointers always fit in registers
4527 DAG.setRoot(Result.second);
4530 void SelectionDAGLowering::visitFree(FreeInst &I) {
4531 TargetLowering::ArgListTy Args;
4532 TargetLowering::ArgListEntry Entry;
4533 Entry.Node = getValue(I.getOperand(0));
4534 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4535 Args.push_back(Entry);
4536 MVT IntPtr = TLI.getPointerTy();
4537 std::pair<SDOperand,SDOperand> Result =
4538 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4539 CallingConv::C, true,
4540 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4541 DAG.setRoot(Result.second);
4544 // EmitInstrWithCustomInserter - This method should be implemented by targets
4545 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4546 // instructions are special in various ways, which require special support to
4547 // insert. The specified MachineInstr is created but not inserted into any
4548 // basic blocks, and the scheduler passes ownership of it to this method.
4549 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4550 MachineBasicBlock *MBB) {
4551 cerr << "If a target marks an instruction with "
4552 << "'usesCustomDAGSchedInserter', it must implement "
4553 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4558 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4559 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4560 getValue(I.getOperand(1)),
4561 DAG.getSrcValue(I.getOperand(1))));
4564 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4565 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4566 getValue(I.getOperand(0)),
4567 DAG.getSrcValue(I.getOperand(0)));
4569 DAG.setRoot(V.getValue(1));
4572 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4573 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4574 getValue(I.getOperand(1)),
4575 DAG.getSrcValue(I.getOperand(1))));
4578 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4579 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4580 getValue(I.getOperand(1)),
4581 getValue(I.getOperand(2)),
4582 DAG.getSrcValue(I.getOperand(1)),
4583 DAG.getSrcValue(I.getOperand(2))));
4586 /// TargetLowering::LowerArguments - This is the default LowerArguments
4587 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4588 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4589 /// integrated into SDISel.
4590 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4591 SmallVectorImpl<SDOperand> &ArgValues) {
4592 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4593 SmallVector<SDOperand, 3+16> Ops;
4594 Ops.push_back(DAG.getRoot());
4595 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4596 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4598 // Add one result value for each formal argument.
4599 SmallVector<MVT, 16> RetVals;
4601 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4603 SmallVector<MVT, 4> ValueVTs;
4604 ComputeValueVTs(*this, I->getType(), ValueVTs);
4605 for (unsigned Value = 0, NumValues = ValueVTs.size();
4606 Value != NumValues; ++Value) {
4607 MVT VT = ValueVTs[Value];
4608 const Type *ArgTy = VT.getTypeForMVT();
4609 ISD::ArgFlagsTy Flags;
4610 unsigned OriginalAlignment =
4611 getTargetData()->getABITypeAlignment(ArgTy);
4613 if (F.paramHasAttr(j, ParamAttr::ZExt))
4615 if (F.paramHasAttr(j, ParamAttr::SExt))
4617 if (F.paramHasAttr(j, ParamAttr::InReg))
4619 if (F.paramHasAttr(j, ParamAttr::StructRet))
4621 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4623 const PointerType *Ty = cast<PointerType>(I->getType());
4624 const Type *ElementTy = Ty->getElementType();
4625 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4626 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4627 // For ByVal, alignment should be passed from FE. BE will guess if
4628 // this info is not there but there are cases it cannot get right.
4629 if (F.getParamAlignment(j))
4630 FrameAlign = F.getParamAlignment(j);
4631 Flags.setByValAlign(FrameAlign);
4632 Flags.setByValSize(FrameSize);
4634 if (F.paramHasAttr(j, ParamAttr::Nest))
4636 Flags.setOrigAlign(OriginalAlignment);
4638 MVT RegisterVT = getRegisterType(VT);
4639 unsigned NumRegs = getNumRegisters(VT);
4640 for (unsigned i = 0; i != NumRegs; ++i) {
4641 RetVals.push_back(RegisterVT);
4642 ISD::ArgFlagsTy MyFlags = Flags;
4643 if (NumRegs > 1 && i == 0)
4645 // if it isn't first piece, alignment must be 1
4647 MyFlags.setOrigAlign(1);
4648 Ops.push_back(DAG.getArgFlags(MyFlags));
4653 RetVals.push_back(MVT::Other);
4656 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4657 DAG.getVTList(&RetVals[0], RetVals.size()),
4658 &Ops[0], Ops.size()).Val;
4660 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4661 // allows exposing the loads that may be part of the argument access to the
4662 // first DAGCombiner pass.
4663 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4665 // The number of results should match up, except that the lowered one may have
4666 // an extra flag result.
4667 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4668 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4669 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4670 && "Lowering produced unexpected number of results!");
4671 Result = TmpRes.Val;
4673 unsigned NumArgRegs = Result->getNumValues() - 1;
4674 DAG.setRoot(SDOperand(Result, NumArgRegs));
4676 // Set up the return result vector.
4679 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4681 SmallVector<MVT, 4> ValueVTs;
4682 ComputeValueVTs(*this, I->getType(), ValueVTs);
4683 for (unsigned Value = 0, NumValues = ValueVTs.size();
4684 Value != NumValues; ++Value) {
4685 MVT VT = ValueVTs[Value];
4686 MVT PartVT = getRegisterType(VT);
4688 unsigned NumParts = getNumRegisters(VT);
4689 SmallVector<SDOperand, 4> Parts(NumParts);
4690 for (unsigned j = 0; j != NumParts; ++j)
4691 Parts[j] = SDOperand(Result, i++);
4693 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4694 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4695 AssertOp = ISD::AssertSext;
4696 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4697 AssertOp = ISD::AssertZext;
4699 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4703 assert(i == NumArgRegs && "Argument register count mismatch!");
4707 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4708 /// implementation, which just inserts an ISD::CALL node, which is later custom
4709 /// lowered by the target to something concrete. FIXME: When all targets are
4710 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4711 std::pair<SDOperand, SDOperand>
4712 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4713 bool RetSExt, bool RetZExt, bool isVarArg,
4714 unsigned CallingConv, bool isTailCall,
4716 ArgListTy &Args, SelectionDAG &DAG) {
4717 SmallVector<SDOperand, 32> Ops;
4718 Ops.push_back(Chain); // Op#0 - Chain
4719 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4720 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4721 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4722 Ops.push_back(Callee);
4724 // Handle all of the outgoing arguments.
4725 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4726 SmallVector<MVT, 4> ValueVTs;
4727 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4728 for (unsigned Value = 0, NumValues = ValueVTs.size();
4729 Value != NumValues; ++Value) {
4730 MVT VT = ValueVTs[Value];
4731 const Type *ArgTy = VT.getTypeForMVT();
4732 SDOperand Op = SDOperand(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4733 ISD::ArgFlagsTy Flags;
4734 unsigned OriginalAlignment =
4735 getTargetData()->getABITypeAlignment(ArgTy);
4741 if (Args[i].isInReg)
4745 if (Args[i].isByVal) {
4747 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4748 const Type *ElementTy = Ty->getElementType();
4749 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4750 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4751 // For ByVal, alignment should come from FE. BE will guess if this
4752 // info is not there but there are cases it cannot get right.
4753 if (Args[i].Alignment)
4754 FrameAlign = Args[i].Alignment;
4755 Flags.setByValAlign(FrameAlign);
4756 Flags.setByValSize(FrameSize);
4760 Flags.setOrigAlign(OriginalAlignment);
4762 MVT PartVT = getRegisterType(VT);
4763 unsigned NumParts = getNumRegisters(VT);
4764 SmallVector<SDOperand, 4> Parts(NumParts);
4765 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4768 ExtendKind = ISD::SIGN_EXTEND;
4769 else if (Args[i].isZExt)
4770 ExtendKind = ISD::ZERO_EXTEND;
4772 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4774 for (unsigned i = 0; i != NumParts; ++i) {
4775 // if it isn't first piece, alignment must be 1
4776 ISD::ArgFlagsTy MyFlags = Flags;
4777 if (NumParts > 1 && i == 0)
4780 MyFlags.setOrigAlign(1);
4782 Ops.push_back(Parts[i]);
4783 Ops.push_back(DAG.getArgFlags(MyFlags));
4788 // Figure out the result value types. We start by making a list of
4789 // the potentially illegal return value types.
4790 SmallVector<MVT, 4> LoweredRetTys;
4791 SmallVector<MVT, 4> RetTys;
4792 ComputeValueVTs(*this, RetTy, RetTys);
4794 // Then we translate that to a list of legal types.
4795 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4797 MVT RegisterVT = getRegisterType(VT);
4798 unsigned NumRegs = getNumRegisters(VT);
4799 for (unsigned i = 0; i != NumRegs; ++i)
4800 LoweredRetTys.push_back(RegisterVT);
4803 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4805 // Create the CALL node.
4806 SDOperand Res = DAG.getNode(ISD::CALL,
4807 DAG.getVTList(&LoweredRetTys[0],
4808 LoweredRetTys.size()),
4809 &Ops[0], Ops.size());
4810 Chain = Res.getValue(LoweredRetTys.size() - 1);
4812 // Gather up the call result into a single value.
4813 if (RetTy != Type::VoidTy) {
4814 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4817 AssertOp = ISD::AssertSext;
4819 AssertOp = ISD::AssertZext;
4821 SmallVector<SDOperand, 4> ReturnValues;
4823 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4825 MVT RegisterVT = getRegisterType(VT);
4826 unsigned NumRegs = getNumRegisters(VT);
4827 unsigned RegNoEnd = NumRegs + RegNo;
4828 SmallVector<SDOperand, 4> Results;
4829 for (; RegNo != RegNoEnd; ++RegNo)
4830 Results.push_back(Res.getValue(RegNo));
4831 SDOperand ReturnValue =
4832 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4834 ReturnValues.push_back(ReturnValue);
4836 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4837 &ReturnValues[0], ReturnValues.size());
4840 return std::make_pair(Res, Chain);
4843 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4844 assert(0 && "LowerOperation not implemented for this target!");
4850 //===----------------------------------------------------------------------===//
4851 // SelectionDAGISel code
4852 //===----------------------------------------------------------------------===//
4854 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4855 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4858 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4859 AU.addRequired<AliasAnalysis>();
4860 AU.addRequired<CollectorModuleMetadata>();
4861 AU.setPreservesAll();
4864 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4865 // Get alias analysis for load/store combining.
4866 AA = &getAnalysis<AliasAnalysis>();
4868 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4869 if (MF.getFunction()->hasCollector())
4870 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4873 RegInfo = &MF.getRegInfo();
4874 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4876 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4878 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4879 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4880 // Mark landing pad.
4881 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4883 SelectAllBasicBlocks(Fn, MF, FuncInfo);
4885 // Add function live-ins to entry block live-in set.
4886 BasicBlock *EntryBB = &Fn.getEntryBlock();
4887 BB = FuncInfo.MBBMap[EntryBB];
4888 if (!RegInfo->livein_empty())
4889 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4890 E = RegInfo->livein_end(); I != E; ++I)
4891 BB->addLiveIn(I->first);
4894 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4895 "Not all catch info was assigned to a landing pad!");
4901 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4902 SDOperand Op = getValue(V);
4903 assert((Op.getOpcode() != ISD::CopyFromReg ||
4904 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4905 "Copy from a reg to the same reg!");
4906 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4908 RegsForValue RFV(TLI, Reg, V->getType());
4909 SDOperand Chain = DAG.getEntryNode();
4910 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4911 PendingExports.push_back(Chain);
4914 void SelectionDAGISel::
4915 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4916 // If this is the entry block, emit arguments.
4917 Function &F = *LLVMBB->getParent();
4918 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4919 SDOperand OldRoot = SDL.DAG.getRoot();
4920 SmallVector<SDOperand, 16> Args;
4921 TLI.LowerArguments(F, SDL.DAG, Args);
4924 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4926 SmallVector<MVT, 4> ValueVTs;
4927 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4928 unsigned NumValues = ValueVTs.size();
4929 if (!AI->use_empty()) {
4930 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
4931 // If this argument is live outside of the entry block, insert a copy from
4932 // whereever we got it to the vreg that other BB's will reference it as.
4933 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4934 if (VMI != FuncInfo.ValueMap.end()) {
4935 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4941 // Finally, if the target has anything special to do, allow it to do so.
4942 // FIXME: this should insert code into the DAG!
4943 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4946 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4947 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4948 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4949 if (isSelector(I)) {
4950 // Apply the catch info to DestBB.
4951 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4953 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4954 FLI.CatchInfoFound.insert(I);
4959 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4960 /// whether object offset >= 0.
4962 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDOperand Op) {
4963 if (!isa<FrameIndexSDNode>(Op)) return false;
4965 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4966 int FrameIdx = FrameIdxNode->getIndex();
4967 return MFI->isFixedObjectIndex(FrameIdx) &&
4968 MFI->getObjectOffset(FrameIdx) >= 0;
4971 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
4972 /// possibly be overwritten when lowering the outgoing arguments in a tail
4973 /// call. Currently the implementation of this call is very conservative and
4974 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
4975 /// virtual registers would be overwritten by direct lowering.
4976 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
4977 MachineFrameInfo * MFI) {
4978 RegisterSDNode * OpReg = NULL;
4979 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
4980 (Op.getOpcode()== ISD::CopyFromReg &&
4981 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
4982 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
4983 (Op.getOpcode() == ISD::LOAD &&
4984 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
4985 (Op.getOpcode() == ISD::MERGE_VALUES &&
4986 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
4987 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
4993 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4994 /// DAG and fixes their tailcall attribute operand.
4995 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4996 TargetLowering& TLI) {
4997 SDNode * Ret = NULL;
4998 SDOperand Terminator = DAG.getRoot();
5001 if (Terminator.getOpcode() == ISD::RET) {
5002 Ret = Terminator.Val;
5005 // Fix tail call attribute of CALL nodes.
5006 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5007 BI = DAG.allnodes_end(); BI != BE; ) {
5009 if (BI->getOpcode() == ISD::CALL) {
5010 SDOperand OpRet(Ret, 0);
5011 SDOperand OpCall(BI, 0);
5012 bool isMarkedTailCall =
5013 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5014 // If CALL node has tail call attribute set to true and the call is not
5015 // eligible (no RET or the target rejects) the attribute is fixed to
5016 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5017 // must correctly identify tail call optimizable calls.
5018 if (!isMarkedTailCall) continue;
5020 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5021 // Not eligible. Mark CALL node as non tail call.
5022 SmallVector<SDOperand, 32> Ops;
5024 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5025 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5029 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5031 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5033 // Look for tail call clobbered arguments. Emit a series of
5034 // copyto/copyfrom virtual register nodes to protect them.
5035 SmallVector<SDOperand, 32> Ops;
5036 SDOperand Chain = OpCall.getOperand(0), InFlag;
5038 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5039 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5041 if (idx > 4 && (idx % 2)) {
5042 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5043 getArgFlags().isByVal();
5044 MachineFunction &MF = DAG.getMachineFunction();
5045 MachineFrameInfo *MFI = MF.getFrameInfo();
5047 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5048 MVT VT = Arg.getValueType();
5049 unsigned VReg = MF.getRegInfo().
5050 createVirtualRegister(TLI.getRegClassFor(VT));
5051 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5052 InFlag = Chain.getValue(1);
5053 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5054 Chain = Arg.getValue(1);
5055 InFlag = Arg.getValue(2);
5060 // Link in chain of CopyTo/CopyFromReg.
5062 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5068 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5069 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5070 FunctionLoweringInfo &FuncInfo) {
5071 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
5073 // Lower any arguments needed in this block if this is the entry block.
5074 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5075 LowerArguments(LLVMBB, SDL);
5077 BB = FuncInfo.MBBMap[LLVMBB];
5078 SDL.setCurrentBasicBlock(BB);
5080 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5082 if (MMI && BB->isLandingPad()) {
5083 // Add a label to mark the beginning of the landing pad. Deletion of the
5084 // landing pad can thus be detected via the MachineModuleInfo.
5085 unsigned LabelID = MMI->addLandingPad(BB);
5086 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
5088 // Mark exception register as live in.
5089 unsigned Reg = TLI.getExceptionAddressRegister();
5090 if (Reg) BB->addLiveIn(Reg);
5092 // Mark exception selector register as live in.
5093 Reg = TLI.getExceptionSelectorRegister();
5094 if (Reg) BB->addLiveIn(Reg);
5096 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5097 // function and list of typeids logically belong to the invoke (or, if you
5098 // like, the basic block containing the invoke), and need to be associated
5099 // with it in the dwarf exception handling tables. Currently however the
5100 // information is provided by an intrinsic (eh.selector) that can be moved
5101 // to unexpected places by the optimizers: if the unwind edge is critical,
5102 // then breaking it can result in the intrinsics being in the successor of
5103 // the landing pad, not the landing pad itself. This results in exceptions
5104 // not being caught because no typeids are associated with the invoke.
5105 // This may not be the only way things can go wrong, but it is the only way
5106 // we try to work around for the moment.
5107 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5109 if (Br && Br->isUnconditional()) { // Critical edge?
5110 BasicBlock::iterator I, E;
5111 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5116 // No catch info found - try to extract some from the successor.
5117 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5121 // Lower all of the non-terminator instructions.
5122 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
5126 // Ensure that all instructions which are used outside of their defining
5127 // blocks are available as virtual registers. Invoke is handled elsewhere.
5128 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
5129 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5130 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5131 if (VMI != FuncInfo.ValueMap.end())
5132 SDL.CopyValueToVirtualRegister(I, VMI->second);
5135 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5136 // ensure constants are generated when needed. Remember the virtual registers
5137 // that need to be added to the Machine PHI nodes as input. We cannot just
5138 // directly add them, because expansion might result in multiple MBB's for one
5139 // BB. As such, the start of the BB might correspond to a different MBB than
5142 TerminatorInst *TI = LLVMBB->getTerminator();
5144 // Emit constants only once even if used by multiple PHI nodes.
5145 std::map<Constant*, unsigned> ConstantsOut;
5147 // Vector bool would be better, but vector<bool> is really slow.
5148 std::vector<unsigned char> SuccsHandled;
5149 if (TI->getNumSuccessors())
5150 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5152 // Check successor nodes' PHI nodes that expect a constant to be available
5154 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5155 BasicBlock *SuccBB = TI->getSuccessor(succ);
5156 if (!isa<PHINode>(SuccBB->begin())) continue;
5157 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5159 // If this terminator has multiple identical successors (common for
5160 // switches), only handle each succ once.
5161 unsigned SuccMBBNo = SuccMBB->getNumber();
5162 if (SuccsHandled[SuccMBBNo]) continue;
5163 SuccsHandled[SuccMBBNo] = true;
5165 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5168 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5169 // nodes and Machine PHI nodes, but the incoming operands have not been
5171 for (BasicBlock::iterator I = SuccBB->begin();
5172 (PN = dyn_cast<PHINode>(I)); ++I) {
5173 // Ignore dead phi's.
5174 if (PN->use_empty()) continue;
5177 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5179 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5180 unsigned &RegOut = ConstantsOut[C];
5182 RegOut = FuncInfo.CreateRegForValue(C);
5183 SDL.CopyValueToVirtualRegister(C, RegOut);
5187 Reg = FuncInfo.ValueMap[PHIOp];
5189 assert(isa<AllocaInst>(PHIOp) &&
5190 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5191 "Didn't codegen value into a register!??");
5192 Reg = FuncInfo.CreateRegForValue(PHIOp);
5193 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5197 // Remember that this register needs to added to the machine PHI node as
5198 // the input for this MBB.
5199 MVT VT = TLI.getValueType(PN->getType());
5200 unsigned NumRegisters = TLI.getNumRegisters(VT);
5201 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5202 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5205 ConstantsOut.clear();
5207 // Lower the terminator after the copies are emitted.
5208 SDL.visit(*LLVMBB->getTerminator());
5210 // Copy over any CaseBlock records that may now exist due to SwitchInst
5211 // lowering, as well as any jump table information.
5212 SwitchCases.clear();
5213 SwitchCases = SDL.SwitchCases;
5215 JTCases = SDL.JTCases;
5216 BitTestCases.clear();
5217 BitTestCases = SDL.BitTestCases;
5219 // Make sure the root of the DAG is up-to-date.
5220 DAG.setRoot(SDL.getControlRoot());
5222 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5223 // with correct tailcall attribute so that the target can rely on the tailcall
5224 // attribute indicating whether the call is really eligible for tail call
5226 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5229 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5230 SmallPtrSet<SDNode*, 128> VisitedNodes;
5231 SmallVector<SDNode*, 128> Worklist;
5233 Worklist.push_back(DAG.getRoot().Val);
5239 while (!Worklist.empty()) {
5240 SDNode *N = Worklist.back();
5241 Worklist.pop_back();
5243 // If we've already seen this node, ignore it.
5244 if (!VisitedNodes.insert(N))
5247 // Otherwise, add all chain operands to the worklist.
5248 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5249 if (N->getOperand(i).getValueType() == MVT::Other)
5250 Worklist.push_back(N->getOperand(i).Val);
5252 // If this is a CopyToReg with a vreg dest, process it.
5253 if (N->getOpcode() != ISD::CopyToReg)
5256 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5257 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5260 // Ignore non-scalar or non-integer values.
5261 SDOperand Src = N->getOperand(2);
5262 MVT SrcVT = Src.getValueType();
5263 if (!SrcVT.isInteger() || SrcVT.isVector())
5266 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5267 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5268 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5270 // Only install this information if it tells us something.
5271 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5272 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5273 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5274 if (DestReg >= FLI.LiveOutRegInfo.size())
5275 FLI.LiveOutRegInfo.resize(DestReg+1);
5276 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5277 LOI.NumSignBits = NumSignBits;
5278 LOI.KnownOne = NumSignBits;
5279 LOI.KnownZero = NumSignBits;
5284 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5285 DOUT << "Lowered selection DAG:\n";
5287 std::string GroupName = "Instruction Selection and Scheduling";
5289 // Run the DAG combiner in pre-legalize mode.
5290 if (TimePassesIsEnabled) {
5291 NamedRegionTimer T("DAG Combining 1", GroupName);
5292 DAG.Combine(false, *AA);
5294 DAG.Combine(false, *AA);
5297 DOUT << "Optimized lowered selection DAG:\n";
5300 // Second step, hack on the DAG until it only uses operations and types that
5301 // the target supports.
5302 if (EnableLegalizeTypes) {// Enable this some day.
5303 DAG.LegalizeTypes();
5304 // TODO: enable a dag combine pass here.
5307 if (TimePassesIsEnabled) {
5308 NamedRegionTimer T("DAG Legalization", GroupName);
5314 DOUT << "Legalized selection DAG:\n";
5317 // Run the DAG combiner in post-legalize mode.
5318 if (TimePassesIsEnabled) {
5319 NamedRegionTimer T("DAG Combining 2", GroupName);
5320 DAG.Combine(true, *AA);
5322 DAG.Combine(true, *AA);
5325 DOUT << "Optimized legalized selection DAG:\n";
5328 if (ViewISelDAGs) DAG.viewGraph();
5330 if (!FastISel && EnableValueProp)
5331 ComputeLiveOutVRegInfo(DAG);
5333 // Third, instruction select all of the operations to machine code, adding the
5334 // code to the MachineBasicBlock.
5335 if (TimePassesIsEnabled) {
5336 NamedRegionTimer T("Instruction Selection", GroupName);
5337 InstructionSelect(DAG);
5339 InstructionSelect(DAG);
5342 // Schedule machine code.
5343 ScheduleDAG *Scheduler;
5344 if (TimePassesIsEnabled) {
5345 NamedRegionTimer T("Instruction Scheduling", GroupName);
5346 Scheduler = Schedule(DAG);
5348 Scheduler = Schedule(DAG);
5351 // Emit machine code to BB. This can change 'BB' to the last block being
5353 if (TimePassesIsEnabled) {
5354 NamedRegionTimer T("Instruction Creation", GroupName);
5355 BB = Scheduler->EmitSchedule();
5357 BB = Scheduler->EmitSchedule();
5360 // Free the scheduler state.
5361 if (TimePassesIsEnabled) {
5362 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
5368 // Perform target specific isel post processing.
5369 if (TimePassesIsEnabled) {
5370 NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
5371 InstructionSelectPostProcessing(DAG);
5373 InstructionSelectPostProcessing(DAG);
5376 DOUT << "Selected machine code:\n";
5380 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
5381 FunctionLoweringInfo &FuncInfo) {
5382 // Define AllNodes here so that memory allocation is reused for
5383 // each basic block.
5384 alist<SDNode, LargestSDNode> AllNodes;
5386 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
5387 SelectBasicBlock(I, MF, FuncInfo, AllNodes);
5392 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5393 FunctionLoweringInfo &FuncInfo,
5394 alist<SDNode, LargestSDNode> &AllNodes) {
5395 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5397 SelectionDAG DAG(TLI, MF, FuncInfo,
5398 getAnalysisToUpdate<MachineModuleInfo>(),
5402 // First step, lower LLVM code to some DAG. This DAG may use operations and
5403 // types that are not supported by the target.
5404 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5406 // Second step, emit the lowered DAG as machine code.
5407 CodeGenAndEmitDAG(DAG);
5410 DOUT << "Total amount of phi nodes to update: "
5411 << PHINodesToUpdate.size() << "\n";
5412 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5413 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5414 << ", " << PHINodesToUpdate[i].second << ")\n";);
5416 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5417 // PHI nodes in successors.
5418 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5419 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5420 MachineInstr *PHI = PHINodesToUpdate[i].first;
5421 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5422 "This is not a machine PHI node that we are updating!");
5423 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5425 PHI->addOperand(MachineOperand::CreateMBB(BB));
5430 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5431 // Lower header first, if it wasn't already lowered
5432 if (!BitTestCases[i].Emitted) {
5433 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5434 getAnalysisToUpdate<MachineModuleInfo>(),
5437 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5438 // Set the current basic block to the mbb we wish to insert the code into
5439 BB = BitTestCases[i].Parent;
5440 HSDL.setCurrentBasicBlock(BB);
5442 HSDL.visitBitTestHeader(BitTestCases[i]);
5443 HSDAG.setRoot(HSDL.getRoot());
5444 CodeGenAndEmitDAG(HSDAG);
5447 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5448 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5449 getAnalysisToUpdate<MachineModuleInfo>(),
5452 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5453 // Set the current basic block to the mbb we wish to insert the code into
5454 BB = BitTestCases[i].Cases[j].ThisBB;
5455 BSDL.setCurrentBasicBlock(BB);
5458 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5459 BitTestCases[i].Reg,
5460 BitTestCases[i].Cases[j]);
5462 BSDL.visitBitTestCase(BitTestCases[i].Default,
5463 BitTestCases[i].Reg,
5464 BitTestCases[i].Cases[j]);
5467 BSDAG.setRoot(BSDL.getRoot());
5468 CodeGenAndEmitDAG(BSDAG);
5472 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5473 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5474 MachineBasicBlock *PHIBB = PHI->getParent();
5475 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5476 "This is not a machine PHI node that we are updating!");
5477 // This is "default" BB. We have two jumps to it. From "header" BB and
5478 // from last "case" BB.
5479 if (PHIBB == BitTestCases[i].Default) {
5480 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5482 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5483 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5485 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5488 // One of "cases" BB.
5489 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5490 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5491 if (cBB->succ_end() !=
5492 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5493 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5495 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5501 // If the JumpTable record is filled in, then we need to emit a jump table.
5502 // Updating the PHI nodes is tricky in this case, since we need to determine
5503 // whether the PHI is a successor of the range check MBB or the jump table MBB
5504 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5505 // Lower header first, if it wasn't already lowered
5506 if (!JTCases[i].first.Emitted) {
5507 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5508 getAnalysisToUpdate<MachineModuleInfo>(),
5511 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5512 // Set the current basic block to the mbb we wish to insert the code into
5513 BB = JTCases[i].first.HeaderBB;
5514 HSDL.setCurrentBasicBlock(BB);
5516 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5517 HSDAG.setRoot(HSDL.getRoot());
5518 CodeGenAndEmitDAG(HSDAG);
5521 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5522 getAnalysisToUpdate<MachineModuleInfo>(),
5525 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5526 // Set the current basic block to the mbb we wish to insert the code into
5527 BB = JTCases[i].second.MBB;
5528 JSDL.setCurrentBasicBlock(BB);
5530 JSDL.visitJumpTable(JTCases[i].second);
5531 JSDAG.setRoot(JSDL.getRoot());
5532 CodeGenAndEmitDAG(JSDAG);
5535 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5536 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5537 MachineBasicBlock *PHIBB = PHI->getParent();
5538 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5539 "This is not a machine PHI node that we are updating!");
5540 // "default" BB. We can go there only from header BB.
5541 if (PHIBB == JTCases[i].second.Default) {
5542 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5544 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5546 // JT BB. Just iterate over successors here
5547 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5548 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5550 PHI->addOperand(MachineOperand::CreateMBB(BB));
5555 // If the switch block involved a branch to one of the actual successors, we
5556 // need to update PHI nodes in that block.
5557 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5558 MachineInstr *PHI = PHINodesToUpdate[i].first;
5559 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5560 "This is not a machine PHI node that we are updating!");
5561 if (BB->isSuccessor(PHI->getParent())) {
5562 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5564 PHI->addOperand(MachineOperand::CreateMBB(BB));
5568 // If we generated any switch lowering information, build and codegen any
5569 // additional DAGs necessary.
5570 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5571 SelectionDAG SDAG(TLI, MF, FuncInfo,
5572 getAnalysisToUpdate<MachineModuleInfo>(),
5575 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5577 // Set the current basic block to the mbb we wish to insert the code into
5578 BB = SwitchCases[i].ThisBB;
5579 SDL.setCurrentBasicBlock(BB);
5582 SDL.visitSwitchCase(SwitchCases[i]);
5583 SDAG.setRoot(SDL.getRoot());
5584 CodeGenAndEmitDAG(SDAG);
5586 // Handle any PHI nodes in successors of this chunk, as if we were coming
5587 // from the original BB before switch expansion. Note that PHI nodes can
5588 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5589 // handle them the right number of times.
5590 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5591 for (MachineBasicBlock::iterator Phi = BB->begin();
5592 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5593 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5594 for (unsigned pn = 0; ; ++pn) {
5595 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5596 if (PHINodesToUpdate[pn].first == Phi) {
5597 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5599 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5605 // Don't process RHS if same block as LHS.
5606 if (BB == SwitchCases[i].FalseBB)
5607 SwitchCases[i].FalseBB = 0;
5609 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5610 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5611 SwitchCases[i].FalseBB = 0;
5613 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5618 /// Schedule - Pick a safe ordering for instructions for each
5619 /// target node in the graph.
5621 ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
5622 if (ViewSchedDAGs) DAG.viewGraph();
5624 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5628 RegisterScheduler::setDefault(Ctor);
5631 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
5634 if (ViewSUnitDAGs) Scheduler->viewGraph();
5639 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5640 return new HazardRecognizer();
5643 //===----------------------------------------------------------------------===//
5644 // Helper functions used by the generated instruction selector.
5645 //===----------------------------------------------------------------------===//
5646 // Calls to these methods are generated by tblgen.
5648 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5649 /// the dag combiner simplified the 255, we still want to match. RHS is the
5650 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5651 /// specified in the .td file (e.g. 255).
5652 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5653 int64_t DesiredMaskS) const {
5654 const APInt &ActualMask = RHS->getAPIntValue();
5655 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5657 // If the actual mask exactly matches, success!
5658 if (ActualMask == DesiredMask)
5661 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5662 if (ActualMask.intersects(~DesiredMask))
5665 // Otherwise, the DAG Combiner may have proven that the value coming in is
5666 // either already zero or is not demanded. Check for known zero input bits.
5667 APInt NeededMask = DesiredMask & ~ActualMask;
5668 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5671 // TODO: check to see if missing bits are just not demanded.
5673 // Otherwise, this pattern doesn't match.
5677 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5678 /// the dag combiner simplified the 255, we still want to match. RHS is the
5679 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5680 /// specified in the .td file (e.g. 255).
5681 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5682 int64_t DesiredMaskS) const {
5683 const APInt &ActualMask = RHS->getAPIntValue();
5684 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5686 // If the actual mask exactly matches, success!
5687 if (ActualMask == DesiredMask)
5690 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5691 if (ActualMask.intersects(~DesiredMask))
5694 // Otherwise, the DAG Combiner may have proven that the value coming in is
5695 // either already zero or is not demanded. Check for known zero input bits.
5696 APInt NeededMask = DesiredMask & ~ActualMask;
5698 APInt KnownZero, KnownOne;
5699 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5701 // If all the missing bits in the or are already known to be set, match!
5702 if ((NeededMask & KnownOne) == NeededMask)
5705 // TODO: check to see if missing bits are just not demanded.
5707 // Otherwise, this pattern doesn't match.
5712 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5713 /// by tblgen. Others should not call it.
5714 void SelectionDAGISel::
5715 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5716 std::vector<SDOperand> InOps;
5717 std::swap(InOps, Ops);
5719 Ops.push_back(InOps[0]); // input chain.
5720 Ops.push_back(InOps[1]); // input asm string.
5722 unsigned i = 2, e = InOps.size();
5723 if (InOps[e-1].getValueType() == MVT::Flag)
5724 --e; // Don't process a flag operand if it is here.
5727 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5728 if ((Flags & 7) != 4 /*MEM*/) {
5729 // Just skip over this operand, copying the operands verbatim.
5730 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5731 i += (Flags >> 3) + 1;
5733 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5734 // Otherwise, this is a memory operand. Ask the target to select it.
5735 std::vector<SDOperand> SelOps;
5736 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5737 cerr << "Could not match memory address. Inline asm failure!\n";
5741 // Add this to the output node.
5742 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5743 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5745 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5750 // Add the flag input back if present.
5751 if (e != InOps.size())
5752 Ops.push_back(InOps.back());
5755 char SelectionDAGISel::ID = 0;