1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/Analysis/AliasAnalysis.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/CodeGen/ScheduleDAG.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/CodeGen/SSARegMap.h"
35 #include "llvm/Target/MRegisterInfo.h"
36 #include "llvm/Target/TargetAsmInfo.h"
37 #include "llvm/Target/TargetData.h"
38 #include "llvm/Target/TargetFrameInfo.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
52 ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
55 ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
62 //===---------------------------------------------------------------------===//
64 /// RegisterScheduler class - Track the registration of instruction schedulers.
66 //===---------------------------------------------------------------------===//
67 MachinePassRegistry RegisterScheduler::Registry;
69 //===---------------------------------------------------------------------===//
71 /// ISHeuristic command line option for instruction schedulers.
73 //===---------------------------------------------------------------------===//
75 cl::opt<RegisterScheduler::FunctionPassCtor, false,
76 RegisterPassParser<RegisterScheduler> >
78 cl::init(&createDefaultScheduler),
79 cl::desc("Instruction schedulers available:"));
81 static RegisterScheduler
82 defaultListDAGScheduler("default", " Best scheduler for the target",
83 createDefaultScheduler);
87 /// RegsForValue - This struct represents the physical registers that a
88 /// particular value is assigned and the type information about the value.
89 /// This is needed because values can be promoted into larger registers and
90 /// expanded into multiple smaller registers than the value.
91 struct VISIBILITY_HIDDEN RegsForValue {
92 /// Regs - This list hold the register (for legal and promoted values)
93 /// or register set (for expanded values) that the value should be assigned
95 std::vector<unsigned> Regs;
97 /// RegVT - The value type of each register.
101 /// ValueVT - The value type of the LLVM value, which may be promoted from
102 /// RegVT or made from merging the two expanded parts.
103 MVT::ValueType ValueVT;
105 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
107 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
108 : RegVT(regvt), ValueVT(valuevt) {
111 RegsForValue(const std::vector<unsigned> ®s,
112 MVT::ValueType regvt, MVT::ValueType valuevt)
113 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
116 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
117 /// this value and returns the result as a ValueVT value. This uses
118 /// Chain/Flag as the input and updates them for the output Chain/Flag.
119 SDOperand getCopyFromRegs(SelectionDAG &DAG,
120 SDOperand &Chain, SDOperand &Flag) const;
122 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
123 /// specified value into the registers specified by this object. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
125 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
126 SDOperand &Chain, SDOperand &Flag,
127 MVT::ValueType PtrVT) const;
129 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
130 /// operand list. This adds the code marker and includes the number of
131 /// values added into it.
132 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
133 std::vector<SDOperand> &Ops) const;
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
143 MachineBasicBlock *BB) {
144 TargetLowering &TLI = IS->getTargetLowering();
146 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
147 return createTDListDAGScheduler(IS, DAG, BB);
149 assert(TLI.getSchedulingPreference() ==
150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
151 return createBURRListDAGScheduler(IS, DAG, BB);
156 //===--------------------------------------------------------------------===//
157 /// FunctionLoweringInfo - This contains information that is global to a
158 /// function that is used when lowering a region of the function.
159 class FunctionLoweringInfo {
166 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
168 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
169 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
171 /// ValueMap - Since we emit code for the function a basic block at a time,
172 /// we must remember which virtual registers hold the values for
173 /// cross-basic-block values.
174 std::map<const Value*, unsigned> ValueMap;
176 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
177 /// the entry block. This allows the allocas to be efficiently referenced
178 /// anywhere in the function.
179 std::map<const AllocaInst*, int> StaticAllocaMap;
181 unsigned MakeReg(MVT::ValueType VT) {
182 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
185 /// isExportedInst - Return true if the specified value is an instruction
186 /// exported from its block.
187 bool isExportedInst(const Value *V) {
188 return ValueMap.count(V);
191 unsigned CreateRegForValue(const Value *V);
193 unsigned InitializeRegForValue(const Value *V) {
194 unsigned &R = ValueMap[V];
195 assert(R == 0 && "Already initialized this value register!");
196 return R = CreateRegForValue(V);
201 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
202 /// PHI nodes or outside of the basic block that defines it, or used by a
203 /// switch instruction, which may expand to multiple basic blocks.
204 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
205 if (isa<PHINode>(I)) return true;
206 BasicBlock *BB = I->getParent();
207 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
208 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
209 // FIXME: Remove switchinst special case.
210 isa<SwitchInst>(*UI))
215 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
216 /// entry block, return true. This includes arguments used by switches, since
217 /// the switch may expand into multiple basic blocks.
218 static bool isOnlyUsedInEntryBlock(Argument *A) {
219 BasicBlock *Entry = A->getParent()->begin();
220 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
221 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
222 return false; // Use not in entry block.
226 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
227 Function &fn, MachineFunction &mf)
228 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
230 // Create a vreg for each argument register that is not dead and is used
231 // outside of the entry block for the function.
232 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
234 if (!isOnlyUsedInEntryBlock(AI))
235 InitializeRegForValue(AI);
237 // Initialize the mapping of values to registers. This is only set up for
238 // instruction values that are used outside of the block that defines
240 Function::iterator BB = Fn.begin(), EB = Fn.end();
241 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
242 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
243 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
244 const Type *Ty = AI->getAllocatedType();
245 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
247 std::max((unsigned)TLI.getTargetData()->getTypeAlignmentPref(Ty),
250 TySize *= CUI->getZExtValue(); // Get total allocated size.
251 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
252 StaticAllocaMap[AI] =
253 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
256 for (; BB != EB; ++BB)
257 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
258 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
259 if (!isa<AllocaInst>(I) ||
260 !StaticAllocaMap.count(cast<AllocaInst>(I)))
261 InitializeRegForValue(I);
263 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
264 // also creates the initial PHI MachineInstrs, though none of the input
265 // operands are populated.
266 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
267 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
269 MF.getBasicBlockList().push_back(MBB);
271 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
274 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
275 if (PN->use_empty()) continue;
277 MVT::ValueType VT = TLI.getValueType(PN->getType());
278 unsigned NumElements;
279 if (VT != MVT::Vector)
280 NumElements = TLI.getNumElements(VT);
282 MVT::ValueType VT1,VT2;
284 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
287 unsigned PHIReg = ValueMap[PN];
288 assert(PHIReg && "PHI node does not have an assigned virtual register!");
289 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
290 for (unsigned i = 0; i != NumElements; ++i)
291 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
296 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
297 /// the correctly promoted or expanded types. Assign these registers
298 /// consecutive vreg numbers and return the first assigned number.
299 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
300 MVT::ValueType VT = TLI.getValueType(V->getType());
302 // The number of multiples of registers that we need, to, e.g., split up
303 // a <2 x int64> -> 4 x i32 registers.
304 unsigned NumVectorRegs = 1;
306 // If this is a packed type, figure out what type it will decompose into
307 // and how many of the elements it will use.
308 if (VT == MVT::Vector) {
309 const PackedType *PTy = cast<PackedType>(V->getType());
310 unsigned NumElts = PTy->getNumElements();
311 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
313 // Divide the input until we get to a supported size. This will always
314 // end with a scalar if the target doesn't support vectors.
315 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
322 VT = getVectorType(EltTy, NumElts);
325 // The common case is that we will only create one register for this
326 // value. If we have that case, create and return the virtual register.
327 unsigned NV = TLI.getNumElements(VT);
329 // If we are promoting this value, pick the next largest supported type.
330 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
331 unsigned Reg = MakeReg(PromotedType);
332 // If this is a vector of supported or promoted types (e.g. 4 x i16),
333 // create all of the registers.
334 for (unsigned i = 1; i != NumVectorRegs; ++i)
335 MakeReg(PromotedType);
339 // If this value is represented with multiple target registers, make sure
340 // to create enough consecutive registers of the right (smaller) type.
341 VT = TLI.getTypeToExpandTo(VT);
342 unsigned R = MakeReg(VT);
343 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
348 //===----------------------------------------------------------------------===//
349 /// SelectionDAGLowering - This is the common target-independent lowering
350 /// implementation that is parameterized by a TargetLowering object.
351 /// Also, targets can overload any lowering method.
354 class SelectionDAGLowering {
355 MachineBasicBlock *CurMBB;
357 std::map<const Value*, SDOperand> NodeMap;
359 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
360 /// them up and then emit token factor nodes when possible. This allows us to
361 /// get simple disambiguation between loads without worrying about alias
363 std::vector<SDOperand> PendingLoads;
365 /// Case - A pair of values to record the Value for a switch case, and the
366 /// case's target basic block.
367 typedef std::pair<Constant*, MachineBasicBlock*> Case;
368 typedef std::vector<Case>::iterator CaseItr;
369 typedef std::pair<CaseItr, CaseItr> CaseRange;
371 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
372 /// of conditional branches.
374 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
375 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
377 /// CaseBB - The MBB in which to emit the compare and branch
378 MachineBasicBlock *CaseBB;
379 /// LT, GE - If nonzero, we know the current case value must be less-than or
380 /// greater-than-or-equal-to these Constants.
383 /// Range - A pair of iterators representing the range of case values to be
384 /// processed at this point in the binary search tree.
388 /// The comparison function for sorting Case values.
390 bool operator () (const Case& C1, const Case& C2) {
391 assert(isa<ConstantInt>(C1.first) && isa<ConstantInt>(C2.first));
392 return cast<const ConstantInt>(C1.first)->getSExtValue() <
393 cast<const ConstantInt>(C2.first)->getSExtValue();
398 // TLI - This is information that describes the available target features we
399 // need for lowering. This indicates when operations are unavailable,
400 // implemented with a libcall, etc.
403 const TargetData *TD;
405 /// SwitchCases - Vector of CaseBlock structures used to communicate
406 /// SwitchInst code generation information.
407 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
408 SelectionDAGISel::JumpTable JT;
410 /// FuncInfo - Information about the function as a whole.
412 FunctionLoweringInfo &FuncInfo;
414 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
415 FunctionLoweringInfo &funcinfo)
416 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
417 JT(0,0,0,0), FuncInfo(funcinfo) {
420 /// getRoot - Return the current virtual root of the Selection DAG.
422 SDOperand getRoot() {
423 if (PendingLoads.empty())
424 return DAG.getRoot();
426 if (PendingLoads.size() == 1) {
427 SDOperand Root = PendingLoads[0];
429 PendingLoads.clear();
433 // Otherwise, we have to make a token factor node.
434 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
435 &PendingLoads[0], PendingLoads.size());
436 PendingLoads.clear();
441 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
443 void visit(Instruction &I) { visit(I.getOpcode(), I); }
445 void visit(unsigned Opcode, User &I) {
446 // Note: this doesn't use InstVisitor, because it has to work with
447 // ConstantExpr's in addition to instructions.
449 default: assert(0 && "Unknown instruction type encountered!");
451 // Build the switch statement using the Instruction.def file.
452 #define HANDLE_INST(NUM, OPCODE, CLASS) \
453 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
454 #include "llvm/Instruction.def"
458 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
460 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
461 const Value *SV, SDOperand Root,
464 SDOperand getIntPtrConstant(uint64_t Val) {
465 return DAG.getConstant(Val, TLI.getPointerTy());
468 SDOperand getValue(const Value *V);
470 const SDOperand &setValue(const Value *V, SDOperand NewN) {
471 SDOperand &N = NodeMap[V];
472 assert(N.Val == 0 && "Already set a value for this node!");
476 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
478 bool OutReg, bool InReg,
479 std::set<unsigned> &OutputRegs,
480 std::set<unsigned> &InputRegs);
482 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
483 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
485 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
486 void ExportFromCurrentBlock(Value *V);
488 // Terminator instructions.
489 void visitRet(ReturnInst &I);
490 void visitBr(BranchInst &I);
491 void visitSwitch(SwitchInst &I);
492 void visitUnreachable(UnreachableInst &I) { /* noop */ }
494 // Helper for visitSwitch
495 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
496 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
498 // These all get lowered before this pass.
499 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
500 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
502 void visitScalarBinary(User &I, unsigned OpCode);
503 void visitVectorBinary(User &I, unsigned OpCode);
504 void visitEitherBinary(User &I, unsigned ScalarOp, unsigned VectorOp);
505 void visitShift(User &I, unsigned Opcode);
506 void visitAdd(User &I) {
507 if (isa<PackedType>(I.getType()))
508 visitVectorBinary(I, ISD::VADD);
509 else if (I.getType()->isFloatingPoint())
510 visitScalarBinary(I, ISD::FADD);
512 visitScalarBinary(I, ISD::ADD);
514 void visitSub(User &I);
515 void visitMul(User &I) {
516 if (isa<PackedType>(I.getType()))
517 visitVectorBinary(I, ISD::VMUL);
518 else if (I.getType()->isFloatingPoint())
519 visitScalarBinary(I, ISD::FMUL);
521 visitScalarBinary(I, ISD::MUL);
523 void visitURem(User &I) { visitScalarBinary(I, ISD::UREM); }
524 void visitSRem(User &I) { visitScalarBinary(I, ISD::SREM); }
525 void visitFRem(User &I) { visitScalarBinary(I, ISD::FREM); }
526 void visitUDiv(User &I) { visitEitherBinary(I, ISD::UDIV, ISD::VUDIV); }
527 void visitSDiv(User &I) { visitEitherBinary(I, ISD::SDIV, ISD::VSDIV); }
528 void visitFDiv(User &I) { visitEitherBinary(I, ISD::FDIV, ISD::VSDIV); }
529 void visitAnd (User &I) { visitEitherBinary(I, ISD::AND, ISD::VAND ); }
530 void visitOr (User &I) { visitEitherBinary(I, ISD::OR, ISD::VOR ); }
531 void visitXor (User &I) { visitEitherBinary(I, ISD::XOR, ISD::VXOR ); }
532 void visitShl (User &I) { visitShift(I, ISD::SHL); }
533 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
534 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
535 void visitICmp(User &I);
536 void visitFCmp(User &I);
537 // Visit the conversion instructions
538 void visitTrunc(User &I);
539 void visitZExt(User &I);
540 void visitSExt(User &I);
541 void visitFPTrunc(User &I);
542 void visitFPExt(User &I);
543 void visitFPToUI(User &I);
544 void visitFPToSI(User &I);
545 void visitUIToFP(User &I);
546 void visitSIToFP(User &I);
547 void visitPtrToInt(User &I);
548 void visitIntToPtr(User &I);
549 void visitBitCast(User &I);
551 void visitExtractElement(User &I);
552 void visitInsertElement(User &I);
553 void visitShuffleVector(User &I);
555 void visitGetElementPtr(User &I);
556 void visitSelect(User &I);
558 void visitMalloc(MallocInst &I);
559 void visitFree(FreeInst &I);
560 void visitAlloca(AllocaInst &I);
561 void visitLoad(LoadInst &I);
562 void visitStore(StoreInst &I);
563 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
564 void visitCall(CallInst &I);
565 void visitInlineAsm(CallInst &I);
566 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
567 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
569 void visitVAStart(CallInst &I);
570 void visitVAArg(VAArgInst &I);
571 void visitVAEnd(CallInst &I);
572 void visitVACopy(CallInst &I);
573 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
575 void visitMemIntrinsic(CallInst &I, unsigned Op);
577 void visitUserOp1(Instruction &I) {
578 assert(0 && "UserOp1 should not exist at instruction selection time!");
581 void visitUserOp2(Instruction &I) {
582 assert(0 && "UserOp2 should not exist at instruction selection time!");
586 } // end namespace llvm
588 SDOperand SelectionDAGLowering::getValue(const Value *V) {
589 SDOperand &N = NodeMap[V];
592 const Type *VTy = V->getType();
593 MVT::ValueType VT = TLI.getValueType(VTy);
594 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
595 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
596 visit(CE->getOpcode(), *CE);
597 assert(N.Val && "visit didn't populate the ValueMap!");
599 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
600 return N = DAG.getGlobalAddress(GV, VT);
601 } else if (isa<ConstantPointerNull>(C)) {
602 return N = DAG.getConstant(0, TLI.getPointerTy());
603 } else if (isa<UndefValue>(C)) {
604 if (!isa<PackedType>(VTy))
605 return N = DAG.getNode(ISD::UNDEF, VT);
607 // Create a VBUILD_VECTOR of undef nodes.
608 const PackedType *PTy = cast<PackedType>(VTy);
609 unsigned NumElements = PTy->getNumElements();
610 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
612 SmallVector<SDOperand, 8> Ops;
613 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
615 // Create a VConstant node with generic Vector type.
616 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
617 Ops.push_back(DAG.getValueType(PVT));
618 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
619 &Ops[0], Ops.size());
620 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
621 return N = DAG.getConstantFP(CFP->getValue(), VT);
622 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
623 unsigned NumElements = PTy->getNumElements();
624 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
626 // Now that we know the number and type of the elements, push a
627 // Constant or ConstantFP node onto the ops list for each element of
628 // the packed constant.
629 SmallVector<SDOperand, 8> Ops;
630 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
631 for (unsigned i = 0; i != NumElements; ++i)
632 Ops.push_back(getValue(CP->getOperand(i)));
634 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
636 if (MVT::isFloatingPoint(PVT))
637 Op = DAG.getConstantFP(0, PVT);
639 Op = DAG.getConstant(0, PVT);
640 Ops.assign(NumElements, Op);
643 // Create a VBUILD_VECTOR node with generic Vector type.
644 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
645 Ops.push_back(DAG.getValueType(PVT));
646 return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
648 // Canonicalize all constant ints to be unsigned.
649 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
653 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
654 std::map<const AllocaInst*, int>::iterator SI =
655 FuncInfo.StaticAllocaMap.find(AI);
656 if (SI != FuncInfo.StaticAllocaMap.end())
657 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
660 std::map<const Value*, unsigned>::const_iterator VMI =
661 FuncInfo.ValueMap.find(V);
662 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
664 unsigned InReg = VMI->second;
666 // If this type is not legal, make it so now.
667 if (VT != MVT::Vector) {
668 if (TLI.getTypeAction(VT) == TargetLowering::Expand) {
669 // Source must be expanded. This input value is actually coming from the
670 // register pair VMI->second and VMI->second+1.
671 MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
672 unsigned NumVals = TLI.getNumElements(VT);
673 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
675 N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
677 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
678 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
679 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
682 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
683 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
684 if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case
685 N = MVT::isFloatingPoint(VT)
686 ? DAG.getNode(ISD::FP_ROUND, VT, N)
687 : DAG.getNode(ISD::TRUNCATE, VT, N);
690 // Otherwise, if this is a vector, make it available as a generic vector
692 MVT::ValueType PTyElementVT, PTyLegalElementVT;
693 const PackedType *PTy = cast<PackedType>(VTy);
694 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
697 // Build a VBUILD_VECTOR with the input registers.
698 SmallVector<SDOperand, 8> Ops;
699 if (PTyElementVT == PTyLegalElementVT) {
700 // If the value types are legal, just VBUILD the CopyFromReg nodes.
701 for (unsigned i = 0; i != NE; ++i)
702 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
704 } else if (PTyElementVT < PTyLegalElementVT) {
705 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
706 for (unsigned i = 0; i != NE; ++i) {
707 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
709 if (MVT::isFloatingPoint(PTyElementVT))
710 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
712 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
716 // If the register was expanded, use BUILD_PAIR.
717 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
718 for (unsigned i = 0; i != NE/2; ++i) {
719 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
721 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
723 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
727 Ops.push_back(DAG.getConstant(NE, MVT::i32));
728 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
729 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
731 // Finally, use a VBIT_CONVERT to make this available as the appropriate
733 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
734 DAG.getConstant(PTy->getNumElements(),
736 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
743 void SelectionDAGLowering::visitRet(ReturnInst &I) {
744 if (I.getNumOperands() == 0) {
745 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
748 SmallVector<SDOperand, 8> NewValues;
749 NewValues.push_back(getRoot());
750 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
751 SDOperand RetOp = getValue(I.getOperand(i));
753 // If this is an integer return value, we need to promote it ourselves to
754 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
756 // FIXME: C calling convention requires the return type to be promoted to
757 // at least 32-bit. But this is not necessary for non-C calling conventions.
758 if (MVT::isInteger(RetOp.getValueType()) &&
759 RetOp.getValueType() < MVT::i64) {
760 MVT::ValueType TmpVT;
761 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
762 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
765 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType();
766 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
767 if (FTy->paramHasAttr(0, FunctionType::SExtAttribute))
768 ExtendKind = ISD::SIGN_EXTEND;
769 if (FTy->paramHasAttr(0, FunctionType::ZExtAttribute))
770 ExtendKind = ISD::ZERO_EXTEND;
771 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
773 NewValues.push_back(RetOp);
774 NewValues.push_back(DAG.getConstant(false, MVT::i32));
776 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
777 &NewValues[0], NewValues.size()));
780 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
781 /// the current basic block, add it to ValueMap now so that we'll get a
783 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
784 // No need to export constants.
785 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
788 if (FuncInfo.isExportedInst(V)) return;
790 unsigned Reg = FuncInfo.InitializeRegForValue(V);
791 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
794 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
795 const BasicBlock *FromBB) {
796 // The operands of the setcc have to be in this block. We don't know
797 // how to export them from some other block.
798 if (Instruction *VI = dyn_cast<Instruction>(V)) {
799 // Can export from current BB.
800 if (VI->getParent() == FromBB)
803 // Is already exported, noop.
804 return FuncInfo.isExportedInst(V);
807 // If this is an argument, we can export it if the BB is the entry block or
808 // if it is already exported.
809 if (isa<Argument>(V)) {
810 if (FromBB == &FromBB->getParent()->getEntryBlock())
813 // Otherwise, can only export this if it is already exported.
814 return FuncInfo.isExportedInst(V);
817 // Otherwise, constants can always be exported.
821 static bool InBlock(const Value *V, const BasicBlock *BB) {
822 if (const Instruction *I = dyn_cast<Instruction>(V))
823 return I->getParent() == BB;
827 /// FindMergedConditions - If Cond is an expression like
828 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
829 MachineBasicBlock *TBB,
830 MachineBasicBlock *FBB,
831 MachineBasicBlock *CurBB,
833 // If this node is not part of the or/and tree, emit it as a branch.
834 Instruction *BOp = dyn_cast<Instruction>(Cond);
836 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
837 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
838 BOp->getParent() != CurBB->getBasicBlock() ||
839 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
840 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
841 const BasicBlock *BB = CurBB->getBasicBlock();
843 // If the leaf of the tree is a comparison, merge the condition into
845 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
846 // The operands of the cmp have to be in this block. We don't know
847 // how to export them from some other block. If this is the first block
848 // of the sequence, no exporting is needed.
850 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
851 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
852 BOp = cast<Instruction>(Cond);
853 ISD::CondCode Condition;
854 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
855 switch (IC->getPredicate()) {
856 default: assert(0 && "Unknown icmp predicate opcode!");
857 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
858 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
859 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
860 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
861 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
862 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
863 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
864 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
865 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
866 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
868 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
869 ISD::CondCode FPC, FOC;
870 switch (FC->getPredicate()) {
871 default: assert(0 && "Unknown fcmp predicate opcode!");
872 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
873 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
874 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
875 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
876 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
877 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
878 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
879 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
880 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
881 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
882 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
883 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
884 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
885 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
886 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
887 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
889 if (FiniteOnlyFPMath())
894 assert(0 && "Unknown compare instruction");
897 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
898 BOp->getOperand(1), TBB, FBB, CurBB);
899 SwitchCases.push_back(CB);
903 // Create a CaseBlock record representing this branch.
904 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
906 SwitchCases.push_back(CB);
911 // Create TmpBB after CurBB.
912 MachineFunction::iterator BBI = CurBB;
913 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
914 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
916 if (Opc == Instruction::Or) {
925 // Emit the LHS condition.
926 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
928 // Emit the RHS condition into TmpBB.
929 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
931 assert(Opc == Instruction::And && "Unknown merge op!");
939 // This requires creation of TmpBB after CurBB.
941 // Emit the LHS condition.
942 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
944 // Emit the RHS condition into TmpBB.
945 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
949 /// If the set of cases should be emitted as a series of branches, return true.
950 /// If we should emit this as a bunch of and/or'd together conditions, return
953 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
954 if (Cases.size() != 2) return true;
956 // If this is two comparisons of the same values or'd or and'd together, they
957 // will get folded into a single comparison, so don't emit two blocks.
958 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
959 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
960 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
961 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
968 void SelectionDAGLowering::visitBr(BranchInst &I) {
969 // Update machine-CFG edges.
970 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
972 // Figure out which block is immediately after the current one.
973 MachineBasicBlock *NextBlock = 0;
974 MachineFunction::iterator BBI = CurMBB;
975 if (++BBI != CurMBB->getParent()->end())
978 if (I.isUnconditional()) {
979 // If this is not a fall-through branch, emit the branch.
980 if (Succ0MBB != NextBlock)
981 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
982 DAG.getBasicBlock(Succ0MBB)));
984 // Update machine-CFG edges.
985 CurMBB->addSuccessor(Succ0MBB);
990 // If this condition is one of the special cases we handle, do special stuff
992 Value *CondVal = I.getCondition();
993 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
995 // If this is a series of conditions that are or'd or and'd together, emit
996 // this as a sequence of branches instead of setcc's with and/or operations.
997 // For example, instead of something like:
1010 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1011 if (BOp->hasOneUse() &&
1012 (BOp->getOpcode() == Instruction::And ||
1013 BOp->getOpcode() == Instruction::Or)) {
1014 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1015 // If the compares in later blocks need to use values not currently
1016 // exported from this block, export them now. This block should always
1017 // be the first entry.
1018 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1020 // Allow some cases to be rejected.
1021 if (ShouldEmitAsBranches(SwitchCases)) {
1022 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1023 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1024 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1027 // Emit the branch for this block.
1028 visitSwitchCase(SwitchCases[0]);
1029 SwitchCases.erase(SwitchCases.begin());
1033 // Okay, we decided not to do this, remove any inserted MBB's and clear
1035 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1036 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1038 SwitchCases.clear();
1042 // Create a CaseBlock record representing this branch.
1043 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1044 Succ0MBB, Succ1MBB, CurMBB);
1045 // Use visitSwitchCase to actually insert the fast branch sequence for this
1047 visitSwitchCase(CB);
1050 /// visitSwitchCase - Emits the necessary code to represent a single node in
1051 /// the binary search tree resulting from lowering a switch instruction.
1052 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1054 SDOperand CondLHS = getValue(CB.CmpLHS);
1056 // Build the setcc now, fold "(X == true)" to X and "(X == false)" to !X to
1057 // handle common cases produced by branch lowering.
1058 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1060 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1061 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1062 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1064 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1066 // Set NextBlock to be the MBB immediately after the current one, if any.
1067 // This is used to avoid emitting unnecessary branches to the next block.
1068 MachineBasicBlock *NextBlock = 0;
1069 MachineFunction::iterator BBI = CurMBB;
1070 if (++BBI != CurMBB->getParent()->end())
1073 // If the lhs block is the next block, invert the condition so that we can
1074 // fall through to the lhs instead of the rhs block.
1075 if (CB.TrueBB == NextBlock) {
1076 std::swap(CB.TrueBB, CB.FalseBB);
1077 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1078 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1080 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1081 DAG.getBasicBlock(CB.TrueBB));
1082 if (CB.FalseBB == NextBlock)
1083 DAG.setRoot(BrCond);
1085 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1086 DAG.getBasicBlock(CB.FalseBB)));
1087 // Update successor info
1088 CurMBB->addSuccessor(CB.TrueBB);
1089 CurMBB->addSuccessor(CB.FalseBB);
1092 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1093 // Emit the code for the jump table
1094 MVT::ValueType PTy = TLI.getPointerTy();
1095 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1096 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1097 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1102 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
1103 // Figure out which block is immediately after the current one.
1104 MachineBasicBlock *NextBlock = 0;
1105 MachineFunction::iterator BBI = CurMBB;
1107 if (++BBI != CurMBB->getParent()->end())
1110 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
1112 // If there is only the default destination, branch to it if it is not the
1113 // next basic block. Otherwise, just fall through.
1114 if (I.getNumOperands() == 2) {
1115 // Update machine-CFG edges.
1117 // If this is not a fall-through branch, emit the branch.
1118 if (Default != NextBlock)
1119 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1120 DAG.getBasicBlock(Default)));
1122 CurMBB->addSuccessor(Default);
1126 // If there are any non-default case statements, create a vector of Cases
1127 // representing each one, and sort the vector so that we can efficiently
1128 // create a binary search tree from them.
1129 std::vector<Case> Cases;
1131 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
1132 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
1133 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
1136 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1138 // Get the Value to be switched on and default basic blocks, which will be
1139 // inserted into CaseBlock records, representing basic blocks in the binary
1141 Value *SV = I.getOperand(0);
1143 // Get the MachineFunction which holds the current MBB. This is used during
1144 // emission of jump tables, and when inserting any additional MBBs necessary
1145 // to represent the switch.
1146 MachineFunction *CurMF = CurMBB->getParent();
1147 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
1149 // If the switch has few cases (two or less) emit a series of specific
1151 if (Cases.size() < 3) {
1152 // TODO: If any two of the cases has the same destination, and if one value
1153 // is the same as the other, but has one bit unset that the other has set,
1154 // use bit manipulation to do two compares at once. For example:
1155 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1157 // Rearrange the case blocks so that the last one falls through if possible.
1158 if (NextBlock && Default != NextBlock && Cases.back().second != NextBlock) {
1159 // The last case block won't fall through into 'NextBlock' if we emit the
1160 // branches in this order. See if rearranging a case value would help.
1161 for (unsigned i = 0, e = Cases.size()-1; i != e; ++i) {
1162 if (Cases[i].second == NextBlock) {
1163 std::swap(Cases[i], Cases.back());
1169 // Create a CaseBlock record representing a conditional branch to
1170 // the Case's target mbb if the value being switched on SV is equal
1172 MachineBasicBlock *CurBlock = CurMBB;
1173 for (unsigned i = 0, e = Cases.size(); i != e; ++i) {
1174 MachineBasicBlock *FallThrough;
1176 FallThrough = new MachineBasicBlock(CurMBB->getBasicBlock());
1177 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1179 // If the last case doesn't match, go to the default block.
1180 FallThrough = Default;
1183 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, Cases[i].first,
1184 Cases[i].second, FallThrough, CurBlock);
1186 // If emitting the first comparison, just call visitSwitchCase to emit the
1187 // code into the current block. Otherwise, push the CaseBlock onto the
1188 // vector to be later processed by SDISel, and insert the node's MBB
1189 // before the next MBB.
1190 if (CurBlock == CurMBB)
1191 visitSwitchCase(CB);
1193 SwitchCases.push_back(CB);
1195 CurBlock = FallThrough;
1200 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
1201 // target supports indirect branches, then emit a jump table rather than
1202 // lowering the switch to a binary tree of conditional branches.
1203 if ((TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1204 TLI.isOperationLegal(ISD::BRIND, MVT::Other)) &&
1206 uint64_t First =cast<ConstantInt>(Cases.front().first)->getZExtValue();
1207 uint64_t Last = cast<ConstantInt>(Cases.back().first)->getZExtValue();
1208 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
1210 if (Density >= 0.3125) {
1211 // Create a new basic block to hold the code for loading the address
1212 // of the jump table, and jumping to it. Update successor information;
1213 // we will either branch to the default case for the switch, or the jump
1215 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1216 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1217 CurMBB->addSuccessor(Default);
1218 CurMBB->addSuccessor(JumpTableBB);
1220 // Subtract the lowest switch case value from the value being switched on
1221 // and conditional branch to default mbb if the result is greater than the
1222 // difference between smallest and largest cases.
1223 SDOperand SwitchOp = getValue(SV);
1224 MVT::ValueType VT = SwitchOp.getValueType();
1225 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1226 DAG.getConstant(First, VT));
1228 // The SDNode we just created, which holds the value being switched on
1229 // minus the the smallest case value, needs to be copied to a virtual
1230 // register so it can be used as an index into the jump table in a
1231 // subsequent basic block. This value may be smaller or larger than the
1232 // target's pointer type, and therefore require extension or truncating.
1233 if (VT > TLI.getPointerTy())
1234 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1236 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1238 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1239 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1241 // Emit the range check for the jump table, and branch to the default
1242 // block for the switch statement if the value being switched on exceeds
1243 // the largest case in the switch.
1244 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1245 DAG.getConstant(Last-First,VT), ISD::SETUGT);
1246 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1247 DAG.getBasicBlock(Default)));
1249 // Build a vector of destination BBs, corresponding to each target
1250 // of the jump table. If the value of the jump table slot corresponds to
1251 // a case statement, push the case's BB onto the vector, otherwise, push
1253 std::vector<MachineBasicBlock*> DestBBs;
1254 uint64_t TEI = First;
1255 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI)
1256 if (cast<ConstantInt>(ii->first)->getZExtValue() == TEI) {
1257 DestBBs.push_back(ii->second);
1260 DestBBs.push_back(Default);
1263 // Update successor info. Add one edge to each unique successor.
1264 // Vector bool would be better, but vector<bool> is really slow.
1265 std::vector<unsigned char> SuccsHandled;
1266 SuccsHandled.resize(CurMBB->getParent()->getNumBlockIDs());
1268 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1269 E = DestBBs.end(); I != E; ++I) {
1270 if (!SuccsHandled[(*I)->getNumber()]) {
1271 SuccsHandled[(*I)->getNumber()] = true;
1272 JumpTableBB->addSuccessor(*I);
1276 // Create a jump table index for this jump table, or return an existing
1278 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1280 // Set the jump table information so that we can codegen it as a second
1281 // MachineBasicBlock
1282 JT.Reg = JumpTableReg;
1284 JT.MBB = JumpTableBB;
1285 JT.Default = Default;
1290 // Push the initial CaseRec onto the worklist
1291 std::vector<CaseRec> CaseVec;
1292 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1294 while (!CaseVec.empty()) {
1295 // Grab a record representing a case range to process off the worklist
1296 CaseRec CR = CaseVec.back();
1299 // Size is the number of Cases represented by this range. If Size is 1,
1300 // then we are processing a leaf of the binary search tree. Otherwise,
1301 // we need to pick a pivot, and push left and right ranges onto the
1303 unsigned Size = CR.Range.second - CR.Range.first;
1306 // Create a CaseBlock record representing a conditional branch to
1307 // the Case's target mbb if the value being switched on SV is equal
1308 // to C. Otherwise, branch to default.
1309 Constant *C = CR.Range.first->first;
1310 MachineBasicBlock *Target = CR.Range.first->second;
1311 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1314 // If the MBB representing the leaf node is the current MBB, then just
1315 // call visitSwitchCase to emit the code into the current block.
1316 // Otherwise, push the CaseBlock onto the vector to be later processed
1317 // by SDISel, and insert the node's MBB before the next MBB.
1318 if (CR.CaseBB == CurMBB)
1319 visitSwitchCase(CB);
1321 SwitchCases.push_back(CB);
1323 // split case range at pivot
1324 CaseItr Pivot = CR.Range.first + (Size / 2);
1325 CaseRange LHSR(CR.Range.first, Pivot);
1326 CaseRange RHSR(Pivot, CR.Range.second);
1327 Constant *C = Pivot->first;
1328 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1330 // We know that we branch to the LHS if the Value being switched on is
1331 // less than the Pivot value, C. We use this to optimize our binary
1332 // tree a bit, by recognizing that if SV is greater than or equal to the
1333 // LHS's Case Value, and that Case Value is exactly one less than the
1334 // Pivot's Value, then we can branch directly to the LHS's Target,
1335 // rather than creating a leaf node for it.
1336 if ((LHSR.second - LHSR.first) == 1 &&
1337 LHSR.first->first == CR.GE &&
1338 cast<ConstantInt>(C)->getZExtValue() ==
1339 (cast<ConstantInt>(CR.GE)->getZExtValue() + 1ULL)) {
1340 TrueBB = LHSR.first->second;
1342 TrueBB = new MachineBasicBlock(LLVMBB);
1343 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1344 CaseVec.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1347 // Similar to the optimization above, if the Value being switched on is
1348 // known to be less than the Constant CR.LT, and the current Case Value
1349 // is CR.LT - 1, then we can branch directly to the target block for
1350 // the current Case Value, rather than emitting a RHS leaf node for it.
1351 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1352 cast<ConstantInt>(RHSR.first->first)->getZExtValue() ==
1353 (cast<ConstantInt>(CR.LT)->getZExtValue() - 1ULL)) {
1354 FalseBB = RHSR.first->second;
1356 FalseBB = new MachineBasicBlock(LLVMBB);
1357 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1358 CaseVec.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1361 // Create a CaseBlock record representing a conditional branch to
1362 // the LHS node if the value being switched on SV is less than C.
1363 // Otherwise, branch to LHS.
1364 ISD::CondCode CC = ISD::SETLT;
1365 SelectionDAGISel::CaseBlock CB(CC, SV, C, TrueBB, FalseBB, CR.CaseBB);
1367 if (CR.CaseBB == CurMBB)
1368 visitSwitchCase(CB);
1370 SwitchCases.push_back(CB);
1375 void SelectionDAGLowering::visitSub(User &I) {
1376 // -0.0 - X --> fneg
1377 const Type *Ty = I.getType();
1378 if (isa<PackedType>(Ty)) {
1379 visitVectorBinary(I, ISD::VSUB);
1380 } else if (Ty->isFloatingPoint()) {
1381 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1382 if (CFP->isExactlyValue(-0.0)) {
1383 SDOperand Op2 = getValue(I.getOperand(1));
1384 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1387 visitScalarBinary(I, ISD::FSUB);
1389 visitScalarBinary(I, ISD::SUB);
1392 void SelectionDAGLowering::visitScalarBinary(User &I, unsigned OpCode) {
1393 SDOperand Op1 = getValue(I.getOperand(0));
1394 SDOperand Op2 = getValue(I.getOperand(1));
1396 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
1400 SelectionDAGLowering::visitVectorBinary(User &I, unsigned OpCode) {
1401 assert(isa<PackedType>(I.getType()));
1402 const PackedType *Ty = cast<PackedType>(I.getType());
1403 SDOperand Typ = DAG.getValueType(TLI.getValueType(Ty->getElementType()));
1405 setValue(&I, DAG.getNode(OpCode, MVT::Vector,
1406 getValue(I.getOperand(0)),
1407 getValue(I.getOperand(1)),
1408 DAG.getConstant(Ty->getNumElements(), MVT::i32),
1412 void SelectionDAGLowering::visitEitherBinary(User &I, unsigned ScalarOp,
1413 unsigned VectorOp) {
1414 if (isa<PackedType>(I.getType()))
1415 visitVectorBinary(I, VectorOp);
1417 visitScalarBinary(I, ScalarOp);
1420 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1421 SDOperand Op1 = getValue(I.getOperand(0));
1422 SDOperand Op2 = getValue(I.getOperand(1));
1424 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1426 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1429 void SelectionDAGLowering::visitICmp(User &I) {
1430 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
1431 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
1432 predicate = IC->getPredicate();
1433 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
1434 predicate = ICmpInst::Predicate(IC->getPredicate());
1435 SDOperand Op1 = getValue(I.getOperand(0));
1436 SDOperand Op2 = getValue(I.getOperand(1));
1437 ISD::CondCode Opcode;
1438 switch (predicate) {
1439 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
1440 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
1441 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
1442 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
1443 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
1444 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
1445 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
1446 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
1447 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
1448 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
1450 assert(!"Invalid ICmp predicate value");
1451 Opcode = ISD::SETEQ;
1454 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1457 void SelectionDAGLowering::visitFCmp(User &I) {
1458 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
1459 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
1460 predicate = FC->getPredicate();
1461 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
1462 predicate = FCmpInst::Predicate(FC->getPredicate());
1463 SDOperand Op1 = getValue(I.getOperand(0));
1464 SDOperand Op2 = getValue(I.getOperand(1));
1465 ISD::CondCode Condition, FOC, FPC;
1466 switch (predicate) {
1467 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1468 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1469 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1470 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1471 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1472 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1473 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1474 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1475 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1476 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1477 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1478 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1479 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1480 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1481 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1482 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1484 assert(!"Invalid FCmp predicate value");
1485 FOC = FPC = ISD::SETFALSE;
1488 if (FiniteOnlyFPMath())
1492 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
1495 void SelectionDAGLowering::visitSelect(User &I) {
1496 SDOperand Cond = getValue(I.getOperand(0));
1497 SDOperand TrueVal = getValue(I.getOperand(1));
1498 SDOperand FalseVal = getValue(I.getOperand(2));
1499 if (!isa<PackedType>(I.getType())) {
1500 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1501 TrueVal, FalseVal));
1503 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1504 *(TrueVal.Val->op_end()-2),
1505 *(TrueVal.Val->op_end()-1)));
1510 void SelectionDAGLowering::visitTrunc(User &I) {
1511 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
1512 SDOperand N = getValue(I.getOperand(0));
1513 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1514 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1517 void SelectionDAGLowering::visitZExt(User &I) {
1518 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
1519 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
1520 SDOperand N = getValue(I.getOperand(0));
1521 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1522 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1525 void SelectionDAGLowering::visitSExt(User &I) {
1526 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
1527 // SExt also can't be a cast to bool for same reason. So, nothing much to do
1528 SDOperand N = getValue(I.getOperand(0));
1529 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1530 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1533 void SelectionDAGLowering::visitFPTrunc(User &I) {
1534 // FPTrunc is never a no-op cast, no need to check
1535 SDOperand N = getValue(I.getOperand(0));
1536 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1537 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1540 void SelectionDAGLowering::visitFPExt(User &I){
1541 // FPTrunc is never a no-op cast, no need to check
1542 SDOperand N = getValue(I.getOperand(0));
1543 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1544 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1547 void SelectionDAGLowering::visitFPToUI(User &I) {
1548 // FPToUI is never a no-op cast, no need to check
1549 SDOperand N = getValue(I.getOperand(0));
1550 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1551 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1554 void SelectionDAGLowering::visitFPToSI(User &I) {
1555 // FPToSI is never a no-op cast, no need to check
1556 SDOperand N = getValue(I.getOperand(0));
1557 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1558 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1561 void SelectionDAGLowering::visitUIToFP(User &I) {
1562 // UIToFP is never a no-op cast, no need to check
1563 SDOperand N = getValue(I.getOperand(0));
1564 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1565 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1568 void SelectionDAGLowering::visitSIToFP(User &I){
1569 // UIToFP is never a no-op cast, no need to check
1570 SDOperand N = getValue(I.getOperand(0));
1571 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1572 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1575 void SelectionDAGLowering::visitPtrToInt(User &I) {
1576 // What to do depends on the size of the integer and the size of the pointer.
1577 // We can either truncate, zero extend, or no-op, accordingly.
1578 SDOperand N = getValue(I.getOperand(0));
1579 MVT::ValueType SrcVT = N.getValueType();
1580 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1582 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
1583 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
1585 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
1586 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
1587 setValue(&I, Result);
1590 void SelectionDAGLowering::visitIntToPtr(User &I) {
1591 // What to do depends on the size of the integer and the size of the pointer.
1592 // We can either truncate, zero extend, or no-op, accordingly.
1593 SDOperand N = getValue(I.getOperand(0));
1594 MVT::ValueType SrcVT = N.getValueType();
1595 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1596 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
1597 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1599 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
1600 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1603 void SelectionDAGLowering::visitBitCast(User &I) {
1604 SDOperand N = getValue(I.getOperand(0));
1605 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1606 if (DestVT == MVT::Vector) {
1607 // This is a cast to a vector from something else.
1608 // Get information about the output vector.
1609 const PackedType *DestTy = cast<PackedType>(I.getType());
1610 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1611 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1612 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1613 DAG.getValueType(EltVT)));
1616 MVT::ValueType SrcVT = N.getValueType();
1617 if (SrcVT == MVT::Vector) {
1618 // This is a cast from a vctor to something else.
1619 // Get information about the input vector.
1620 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1624 // BitCast assures us that source and destination are the same size so this
1625 // is either a BIT_CONVERT or a no-op.
1626 if (DestVT != N.getValueType())
1627 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
1629 setValue(&I, N); // noop cast.
1632 void SelectionDAGLowering::visitInsertElement(User &I) {
1633 SDOperand InVec = getValue(I.getOperand(0));
1634 SDOperand InVal = getValue(I.getOperand(1));
1635 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1636 getValue(I.getOperand(2)));
1638 SDOperand Num = *(InVec.Val->op_end()-2);
1639 SDOperand Typ = *(InVec.Val->op_end()-1);
1640 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1641 InVec, InVal, InIdx, Num, Typ));
1644 void SelectionDAGLowering::visitExtractElement(User &I) {
1645 SDOperand InVec = getValue(I.getOperand(0));
1646 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1647 getValue(I.getOperand(1)));
1648 SDOperand Typ = *(InVec.Val->op_end()-1);
1649 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1650 TLI.getValueType(I.getType()), InVec, InIdx));
1653 void SelectionDAGLowering::visitShuffleVector(User &I) {
1654 SDOperand V1 = getValue(I.getOperand(0));
1655 SDOperand V2 = getValue(I.getOperand(1));
1656 SDOperand Mask = getValue(I.getOperand(2));
1658 SDOperand Num = *(V1.Val->op_end()-2);
1659 SDOperand Typ = *(V2.Val->op_end()-1);
1660 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1661 V1, V2, Mask, Num, Typ));
1665 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1666 SDOperand N = getValue(I.getOperand(0));
1667 const Type *Ty = I.getOperand(0)->getType();
1669 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1672 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1673 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
1676 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1677 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1678 getIntPtrConstant(Offset));
1680 Ty = StTy->getElementType(Field);
1682 Ty = cast<SequentialType>(Ty)->getElementType();
1684 // If this is a constant subscript, handle it quickly.
1685 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1686 if (CI->getZExtValue() == 0) continue;
1688 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
1689 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1693 // N = N + Idx * ElementSize;
1694 uint64_t ElementSize = TD->getTypeSize(Ty);
1695 SDOperand IdxN = getValue(Idx);
1697 // If the index is smaller or larger than intptr_t, truncate or extend
1699 if (IdxN.getValueType() < N.getValueType()) {
1700 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1701 } else if (IdxN.getValueType() > N.getValueType())
1702 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1704 // If this is a multiply by a power of two, turn it into a shl
1705 // immediately. This is a very common case.
1706 if (isPowerOf2_64(ElementSize)) {
1707 unsigned Amt = Log2_64(ElementSize);
1708 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1709 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1710 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1714 SDOperand Scale = getIntPtrConstant(ElementSize);
1715 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1716 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1722 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1723 // If this is a fixed sized alloca in the entry block of the function,
1724 // allocate it statically on the stack.
1725 if (FuncInfo.StaticAllocaMap.count(&I))
1726 return; // getValue will auto-populate this.
1728 const Type *Ty = I.getAllocatedType();
1729 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1731 std::max((unsigned)TLI.getTargetData()->getTypeAlignmentPref(Ty),
1734 SDOperand AllocSize = getValue(I.getArraySize());
1735 MVT::ValueType IntPtr = TLI.getPointerTy();
1736 if (IntPtr < AllocSize.getValueType())
1737 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1738 else if (IntPtr > AllocSize.getValueType())
1739 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1741 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1742 getIntPtrConstant(TySize));
1744 // Handle alignment. If the requested alignment is less than or equal to the
1745 // stack alignment, ignore it and round the size of the allocation up to the
1746 // stack alignment size. If the size is greater than the stack alignment, we
1747 // note this in the DYNAMIC_STACKALLOC node.
1748 unsigned StackAlign =
1749 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1750 if (Align <= StackAlign) {
1752 // Add SA-1 to the size.
1753 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1754 getIntPtrConstant(StackAlign-1));
1755 // Mask out the low bits for alignment purposes.
1756 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1757 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1760 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
1761 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
1763 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
1764 DAG.setRoot(setValue(&I, DSA).getValue(1));
1766 // Inform the Frame Information that we have just allocated a variable-sized
1768 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1771 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1772 SDOperand Ptr = getValue(I.getOperand(0));
1778 // Do not serialize non-volatile loads against each other.
1779 Root = DAG.getRoot();
1782 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
1783 Root, I.isVolatile()));
1786 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1787 const Value *SV, SDOperand Root,
1790 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1791 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1792 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
1793 DAG.getSrcValue(SV));
1795 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, isVolatile);
1799 DAG.setRoot(L.getValue(1));
1801 PendingLoads.push_back(L.getValue(1));
1807 void SelectionDAGLowering::visitStore(StoreInst &I) {
1808 Value *SrcV = I.getOperand(0);
1809 SDOperand Src = getValue(SrcV);
1810 SDOperand Ptr = getValue(I.getOperand(1));
1811 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
1815 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1816 /// access memory and has no other side effects at all.
1817 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1818 #define GET_NO_MEMORY_INTRINSICS
1819 #include "llvm/Intrinsics.gen"
1820 #undef GET_NO_MEMORY_INTRINSICS
1824 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1825 // have any side-effects or if it only reads memory.
1826 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1827 #define GET_SIDE_EFFECT_INFO
1828 #include "llvm/Intrinsics.gen"
1829 #undef GET_SIDE_EFFECT_INFO
1833 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1835 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1836 unsigned Intrinsic) {
1837 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1838 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1840 // Build the operand list.
1841 SmallVector<SDOperand, 8> Ops;
1842 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1844 // We don't need to serialize loads against other loads.
1845 Ops.push_back(DAG.getRoot());
1847 Ops.push_back(getRoot());
1851 // Add the intrinsic ID as an integer operand.
1852 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1854 // Add all operands of the call to the operand list.
1855 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1856 SDOperand Op = getValue(I.getOperand(i));
1858 // If this is a vector type, force it to the right packed type.
1859 if (Op.getValueType() == MVT::Vector) {
1860 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1861 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1863 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1864 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1865 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1868 assert(TLI.isTypeLegal(Op.getValueType()) &&
1869 "Intrinsic uses a non-legal type?");
1873 std::vector<MVT::ValueType> VTs;
1874 if (I.getType() != Type::VoidTy) {
1875 MVT::ValueType VT = TLI.getValueType(I.getType());
1876 if (VT == MVT::Vector) {
1877 const PackedType *DestTy = cast<PackedType>(I.getType());
1878 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1880 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1881 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1884 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1888 VTs.push_back(MVT::Other);
1890 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
1895 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
1896 &Ops[0], Ops.size());
1897 else if (I.getType() != Type::VoidTy)
1898 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
1899 &Ops[0], Ops.size());
1901 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
1902 &Ops[0], Ops.size());
1905 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1907 PendingLoads.push_back(Chain);
1911 if (I.getType() != Type::VoidTy) {
1912 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1913 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1914 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1915 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1916 DAG.getValueType(EVT));
1918 setValue(&I, Result);
1922 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1923 /// we want to emit this as a call to a named external function, return the name
1924 /// otherwise lower it and return null.
1926 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1927 switch (Intrinsic) {
1929 // By default, turn this into a target intrinsic node.
1930 visitTargetIntrinsic(I, Intrinsic);
1932 case Intrinsic::vastart: visitVAStart(I); return 0;
1933 case Intrinsic::vaend: visitVAEnd(I); return 0;
1934 case Intrinsic::vacopy: visitVACopy(I); return 0;
1935 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1936 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1937 case Intrinsic::setjmp:
1938 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
1940 case Intrinsic::longjmp:
1941 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
1943 case Intrinsic::memcpy_i32:
1944 case Intrinsic::memcpy_i64:
1945 visitMemIntrinsic(I, ISD::MEMCPY);
1947 case Intrinsic::memset_i32:
1948 case Intrinsic::memset_i64:
1949 visitMemIntrinsic(I, ISD::MEMSET);
1951 case Intrinsic::memmove_i32:
1952 case Intrinsic::memmove_i64:
1953 visitMemIntrinsic(I, ISD::MEMMOVE);
1956 case Intrinsic::dbg_stoppoint: {
1957 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1958 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1959 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
1963 Ops[1] = getValue(SPI.getLineValue());
1964 Ops[2] = getValue(SPI.getColumnValue());
1966 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
1967 assert(DD && "Not a debug information descriptor");
1968 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1970 Ops[3] = DAG.getString(CompileUnit->getFileName());
1971 Ops[4] = DAG.getString(CompileUnit->getDirectory());
1973 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
1978 case Intrinsic::dbg_region_start: {
1979 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1980 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1981 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
1982 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
1983 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
1984 DAG.getConstant(LabelID, MVT::i32)));
1989 case Intrinsic::dbg_region_end: {
1990 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1991 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1992 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
1993 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
1994 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
1995 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2000 case Intrinsic::dbg_func_start: {
2001 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2002 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2003 if (MMI && FSI.getSubprogram() &&
2004 MMI->Verify(FSI.getSubprogram())) {
2005 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
2006 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2007 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2012 case Intrinsic::dbg_declare: {
2013 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2014 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2015 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
2016 SDOperand AddressOp = getValue(DI.getAddress());
2017 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2018 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
2024 case Intrinsic::sqrt_f32:
2025 case Intrinsic::sqrt_f64:
2026 setValue(&I, DAG.getNode(ISD::FSQRT,
2027 getValue(I.getOperand(1)).getValueType(),
2028 getValue(I.getOperand(1))));
2030 case Intrinsic::powi_f32:
2031 case Intrinsic::powi_f64:
2032 setValue(&I, DAG.getNode(ISD::FPOWI,
2033 getValue(I.getOperand(1)).getValueType(),
2034 getValue(I.getOperand(1)),
2035 getValue(I.getOperand(2))));
2037 case Intrinsic::pcmarker: {
2038 SDOperand Tmp = getValue(I.getOperand(1));
2039 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2042 case Intrinsic::readcyclecounter: {
2043 SDOperand Op = getRoot();
2044 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2045 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2048 DAG.setRoot(Tmp.getValue(1));
2051 case Intrinsic::bswap_i16:
2052 case Intrinsic::bswap_i32:
2053 case Intrinsic::bswap_i64:
2054 setValue(&I, DAG.getNode(ISD::BSWAP,
2055 getValue(I.getOperand(1)).getValueType(),
2056 getValue(I.getOperand(1))));
2058 case Intrinsic::cttz_i8:
2059 case Intrinsic::cttz_i16:
2060 case Intrinsic::cttz_i32:
2061 case Intrinsic::cttz_i64:
2062 setValue(&I, DAG.getNode(ISD::CTTZ,
2063 getValue(I.getOperand(1)).getValueType(),
2064 getValue(I.getOperand(1))));
2066 case Intrinsic::ctlz_i8:
2067 case Intrinsic::ctlz_i16:
2068 case Intrinsic::ctlz_i32:
2069 case Intrinsic::ctlz_i64:
2070 setValue(&I, DAG.getNode(ISD::CTLZ,
2071 getValue(I.getOperand(1)).getValueType(),
2072 getValue(I.getOperand(1))));
2074 case Intrinsic::ctpop_i8:
2075 case Intrinsic::ctpop_i16:
2076 case Intrinsic::ctpop_i32:
2077 case Intrinsic::ctpop_i64:
2078 setValue(&I, DAG.getNode(ISD::CTPOP,
2079 getValue(I.getOperand(1)).getValueType(),
2080 getValue(I.getOperand(1))));
2082 case Intrinsic::stacksave: {
2083 SDOperand Op = getRoot();
2084 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2085 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2087 DAG.setRoot(Tmp.getValue(1));
2090 case Intrinsic::stackrestore: {
2091 SDOperand Tmp = getValue(I.getOperand(1));
2092 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2095 case Intrinsic::prefetch:
2096 // FIXME: Currently discarding prefetches.
2102 void SelectionDAGLowering::visitCall(CallInst &I) {
2103 const char *RenameFn = 0;
2104 if (Function *F = I.getCalledFunction()) {
2105 if (F->isExternal())
2106 if (unsigned IID = F->getIntrinsicID()) {
2107 RenameFn = visitIntrinsicCall(I, IID);
2110 } else { // Not an LLVM intrinsic.
2111 const std::string &Name = F->getName();
2112 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
2113 if (I.getNumOperands() == 3 && // Basic sanity checks.
2114 I.getOperand(1)->getType()->isFloatingPoint() &&
2115 I.getType() == I.getOperand(1)->getType() &&
2116 I.getType() == I.getOperand(2)->getType()) {
2117 SDOperand LHS = getValue(I.getOperand(1));
2118 SDOperand RHS = getValue(I.getOperand(2));
2119 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
2123 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
2124 if (I.getNumOperands() == 2 && // Basic sanity checks.
2125 I.getOperand(1)->getType()->isFloatingPoint() &&
2126 I.getType() == I.getOperand(1)->getType()) {
2127 SDOperand Tmp = getValue(I.getOperand(1));
2128 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
2131 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
2132 if (I.getNumOperands() == 2 && // Basic sanity checks.
2133 I.getOperand(1)->getType()->isFloatingPoint() &&
2134 I.getType() == I.getOperand(1)->getType()) {
2135 SDOperand Tmp = getValue(I.getOperand(1));
2136 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
2139 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
2140 if (I.getNumOperands() == 2 && // Basic sanity checks.
2141 I.getOperand(1)->getType()->isFloatingPoint() &&
2142 I.getType() == I.getOperand(1)->getType()) {
2143 SDOperand Tmp = getValue(I.getOperand(1));
2144 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
2149 } else if (isa<InlineAsm>(I.getOperand(0))) {
2154 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
2155 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2159 Callee = getValue(I.getOperand(0));
2161 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
2162 TargetLowering::ArgListTy Args;
2163 TargetLowering::ArgListEntry Entry;
2164 Args.reserve(I.getNumOperands());
2165 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2166 Value *Arg = I.getOperand(i);
2167 SDOperand ArgNode = getValue(Arg);
2168 Entry.Node = ArgNode; Entry.Ty = Arg->getType();
2169 Entry.isSigned = FTy->paramHasAttr(i, FunctionType::SExtAttribute);
2170 Entry.isInReg = FTy->paramHasAttr(i, FunctionType::InRegAttribute);
2171 Entry.isSRet = FTy->paramHasAttr(i, FunctionType::StructRetAttribute);
2172 Args.push_back(Entry);
2175 std::pair<SDOperand,SDOperand> Result =
2176 TLI.LowerCallTo(getRoot(), I.getType(),
2177 FTy->paramHasAttr(0,FunctionType::SExtAttribute),
2178 FTy->isVarArg(), I.getCallingConv(), I.isTailCall(),
2180 if (I.getType() != Type::VoidTy)
2181 setValue(&I, Result.first);
2182 DAG.setRoot(Result.second);
2185 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
2186 SDOperand &Chain, SDOperand &Flag)const{
2187 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
2188 Chain = Val.getValue(1);
2189 Flag = Val.getValue(2);
2191 // If the result was expanded, copy from the top part.
2192 if (Regs.size() > 1) {
2193 assert(Regs.size() == 2 &&
2194 "Cannot expand to more than 2 elts yet!");
2195 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
2196 Chain = Hi.getValue(1);
2197 Flag = Hi.getValue(2);
2198 if (DAG.getTargetLoweringInfo().isLittleEndian())
2199 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
2201 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
2204 // Otherwise, if the return value was promoted or extended, truncate it to the
2205 // appropriate type.
2206 if (RegVT == ValueVT)
2209 if (MVT::isInteger(RegVT)) {
2210 if (ValueVT < RegVT)
2211 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
2213 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
2215 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
2219 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
2220 /// specified value into the registers specified by this object. This uses
2221 /// Chain/Flag as the input and updates them for the output Chain/Flag.
2222 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
2223 SDOperand &Chain, SDOperand &Flag,
2224 MVT::ValueType PtrVT) const {
2225 if (Regs.size() == 1) {
2226 // If there is a single register and the types differ, this must be
2228 if (RegVT != ValueVT) {
2229 if (MVT::isInteger(RegVT)) {
2230 if (RegVT < ValueVT)
2231 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
2233 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
2235 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
2237 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
2238 Flag = Chain.getValue(1);
2240 std::vector<unsigned> R(Regs);
2241 if (!DAG.getTargetLoweringInfo().isLittleEndian())
2242 std::reverse(R.begin(), R.end());
2244 for (unsigned i = 0, e = R.size(); i != e; ++i) {
2245 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
2246 DAG.getConstant(i, PtrVT));
2247 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
2248 Flag = Chain.getValue(1);
2253 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
2254 /// operand list. This adds the code marker and includes the number of
2255 /// values added into it.
2256 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
2257 std::vector<SDOperand> &Ops) const {
2258 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
2259 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
2260 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
2263 /// isAllocatableRegister - If the specified register is safe to allocate,
2264 /// i.e. it isn't a stack pointer or some other special register, return the
2265 /// register class for the register. Otherwise, return null.
2266 static const TargetRegisterClass *
2267 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
2268 const TargetLowering &TLI, const MRegisterInfo *MRI) {
2269 MVT::ValueType FoundVT = MVT::Other;
2270 const TargetRegisterClass *FoundRC = 0;
2271 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
2272 E = MRI->regclass_end(); RCI != E; ++RCI) {
2273 MVT::ValueType ThisVT = MVT::Other;
2275 const TargetRegisterClass *RC = *RCI;
2276 // If none of the the value types for this register class are valid, we
2277 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2278 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2280 if (TLI.isTypeLegal(*I)) {
2281 // If we have already found this register in a different register class,
2282 // choose the one with the largest VT specified. For example, on
2283 // PowerPC, we favor f64 register classes over f32.
2284 if (FoundVT == MVT::Other ||
2285 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
2292 if (ThisVT == MVT::Other) continue;
2294 // NOTE: This isn't ideal. In particular, this might allocate the
2295 // frame pointer in functions that need it (due to them not being taken
2296 // out of allocation, because a variable sized allocation hasn't been seen
2297 // yet). This is a slight code pessimization, but should still work.
2298 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
2299 E = RC->allocation_order_end(MF); I != E; ++I)
2301 // We found a matching register class. Keep looking at others in case
2302 // we find one with larger registers that this physreg is also in.
2311 RegsForValue SelectionDAGLowering::
2312 GetRegistersForValue(const std::string &ConstrCode,
2313 MVT::ValueType VT, bool isOutReg, bool isInReg,
2314 std::set<unsigned> &OutputRegs,
2315 std::set<unsigned> &InputRegs) {
2316 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
2317 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
2318 std::vector<unsigned> Regs;
2320 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
2321 MVT::ValueType RegVT;
2322 MVT::ValueType ValueVT = VT;
2324 // If this is a constraint for a specific physical register, like {r17},
2326 if (PhysReg.first) {
2327 if (VT == MVT::Other)
2328 ValueVT = *PhysReg.second->vt_begin();
2330 // Get the actual register value type. This is important, because the user
2331 // may have asked for (e.g.) the AX register in i32 type. We need to
2332 // remember that AX is actually i16 to get the right extension.
2333 RegVT = *PhysReg.second->vt_begin();
2335 // This is a explicit reference to a physical register.
2336 Regs.push_back(PhysReg.first);
2338 // If this is an expanded reference, add the rest of the regs to Regs.
2340 TargetRegisterClass::iterator I = PhysReg.second->begin();
2341 TargetRegisterClass::iterator E = PhysReg.second->end();
2342 for (; *I != PhysReg.first; ++I)
2343 assert(I != E && "Didn't find reg!");
2345 // Already added the first reg.
2347 for (; NumRegs; --NumRegs, ++I) {
2348 assert(I != E && "Ran out of registers to allocate!");
2352 return RegsForValue(Regs, RegVT, ValueVT);
2355 // Otherwise, if this was a reference to an LLVM register class, create vregs
2356 // for this reference.
2357 std::vector<unsigned> RegClassRegs;
2358 if (PhysReg.second) {
2359 // If this is an early clobber or tied register, our regalloc doesn't know
2360 // how to maintain the constraint. If it isn't, go ahead and create vreg
2361 // and let the regalloc do the right thing.
2362 if (!isOutReg || !isInReg) {
2363 if (VT == MVT::Other)
2364 ValueVT = *PhysReg.second->vt_begin();
2365 RegVT = *PhysReg.second->vt_begin();
2367 // Create the appropriate number of virtual registers.
2368 SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
2369 for (; NumRegs; --NumRegs)
2370 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
2372 return RegsForValue(Regs, RegVT, ValueVT);
2375 // Otherwise, we can't allocate it. Let the code below figure out how to
2376 // maintain these constraints.
2377 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
2380 // This is a reference to a register class that doesn't directly correspond
2381 // to an LLVM register class. Allocate NumRegs consecutive, available,
2382 // registers from the class.
2383 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
2386 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
2387 MachineFunction &MF = *CurMBB->getParent();
2388 unsigned NumAllocated = 0;
2389 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
2390 unsigned Reg = RegClassRegs[i];
2391 // See if this register is available.
2392 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
2393 (isInReg && InputRegs.count(Reg))) { // Already used.
2394 // Make sure we find consecutive registers.
2399 // Check to see if this register is allocatable (i.e. don't give out the
2401 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
2403 // Make sure we find consecutive registers.
2408 // Okay, this register is good, we can use it.
2411 // If we allocated enough consecutive
2412 if (NumAllocated == NumRegs) {
2413 unsigned RegStart = (i-NumAllocated)+1;
2414 unsigned RegEnd = i+1;
2415 // Mark all of the allocated registers used.
2416 for (unsigned i = RegStart; i != RegEnd; ++i) {
2417 unsigned Reg = RegClassRegs[i];
2418 Regs.push_back(Reg);
2419 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
2420 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
2423 return RegsForValue(Regs, *RC->vt_begin(), VT);
2427 // Otherwise, we couldn't allocate enough registers for this.
2428 return RegsForValue();
2432 /// visitInlineAsm - Handle a call to an InlineAsm object.
2434 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
2435 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
2437 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
2440 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
2441 std::vector<MVT::ValueType> ConstraintVTs;
2443 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2444 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2445 /// if it is a def of that register.
2446 std::vector<SDOperand> AsmNodeOperands;
2447 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2448 AsmNodeOperands.push_back(AsmStr);
2450 SDOperand Chain = getRoot();
2453 // We fully assign registers here at isel time. This is not optimal, but
2454 // should work. For register classes that correspond to LLVM classes, we
2455 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2456 // over the constraints, collecting fixed registers that we know we can't use.
2457 std::set<unsigned> OutputRegs, InputRegs;
2459 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2460 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2461 std::string &ConstraintCode = Constraints[i].Codes[0];
2463 MVT::ValueType OpVT;
2465 // Compute the value type for each operand and add it to ConstraintVTs.
2466 switch (Constraints[i].Type) {
2467 case InlineAsm::isOutput:
2468 if (!Constraints[i].isIndirectOutput) {
2469 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2470 OpVT = TLI.getValueType(I.getType());
2472 const Type *OpTy = I.getOperand(OpNum)->getType();
2473 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2474 OpNum++; // Consumes a call operand.
2477 case InlineAsm::isInput:
2478 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2479 OpNum++; // Consumes a call operand.
2481 case InlineAsm::isClobber:
2486 ConstraintVTs.push_back(OpVT);
2488 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2489 continue; // Not assigned a fixed reg.
2491 // Build a list of regs that this operand uses. This always has a single
2492 // element for promoted/expanded operands.
2493 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2495 OutputRegs, InputRegs);
2497 switch (Constraints[i].Type) {
2498 case InlineAsm::isOutput:
2499 // We can't assign any other output to this register.
2500 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2501 // If this is an early-clobber output, it cannot be assigned to the same
2502 // value as the input reg.
2503 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2504 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2506 case InlineAsm::isInput:
2507 // We can't assign any other input to this register.
2508 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2510 case InlineAsm::isClobber:
2511 // Clobbered regs cannot be used as inputs or outputs.
2512 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2513 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2518 // Loop over all of the inputs, copying the operand values into the
2519 // appropriate registers and processing the output regs.
2520 RegsForValue RetValRegs;
2521 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2524 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2525 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2526 std::string &ConstraintCode = Constraints[i].Codes[0];
2528 switch (Constraints[i].Type) {
2529 case InlineAsm::isOutput: {
2530 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2531 if (ConstraintCode.size() == 1) // not a physreg name.
2532 CTy = TLI.getConstraintType(ConstraintCode[0]);
2534 if (CTy == TargetLowering::C_Memory) {
2536 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2538 // Check that the operand (the address to store to) isn't a float.
2539 if (!MVT::isInteger(InOperandVal.getValueType()))
2540 assert(0 && "MATCH FAIL!");
2542 if (!Constraints[i].isIndirectOutput)
2543 assert(0 && "MATCH FAIL!");
2545 OpNum++; // Consumes a call operand.
2547 // Extend/truncate to the right pointer type if needed.
2548 MVT::ValueType PtrType = TLI.getPointerTy();
2549 if (InOperandVal.getValueType() < PtrType)
2550 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2551 else if (InOperandVal.getValueType() > PtrType)
2552 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2554 // Add information to the INLINEASM node to know about this output.
2555 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2556 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2557 AsmNodeOperands.push_back(InOperandVal);
2561 // Otherwise, this is a register output.
2562 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2564 // If this is an early-clobber output, or if there is an input
2565 // constraint that matches this, we need to reserve the input register
2566 // so no other inputs allocate to it.
2567 bool UsesInputRegister = false;
2568 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2569 UsesInputRegister = true;
2571 // Copy the output from the appropriate register. Find a register that
2574 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2575 true, UsesInputRegister,
2576 OutputRegs, InputRegs);
2577 if (Regs.Regs.empty()) {
2578 cerr << "Couldn't allocate output reg for contraint '"
2579 << ConstraintCode << "'!\n";
2583 if (!Constraints[i].isIndirectOutput) {
2584 assert(RetValRegs.Regs.empty() &&
2585 "Cannot have multiple output constraints yet!");
2586 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2589 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2590 I.getOperand(OpNum)));
2591 OpNum++; // Consumes a call operand.
2594 // Add information to the INLINEASM node to know that this register is
2596 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2599 case InlineAsm::isInput: {
2600 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2601 OpNum++; // Consumes a call operand.
2603 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2604 // If this is required to match an output register we have already set,
2605 // just use its register.
2606 unsigned OperandNo = atoi(ConstraintCode.c_str());
2608 // Scan until we find the definition we already emitted of this operand.
2609 // When we find it, create a RegsForValue operand.
2610 unsigned CurOp = 2; // The first operand.
2611 for (; OperandNo; --OperandNo) {
2612 // Advance to the next operand.
2614 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2615 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2616 (NumOps & 7) == 4 /*MEM*/) &&
2617 "Skipped past definitions?");
2618 CurOp += (NumOps>>3)+1;
2622 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2623 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2624 "Skipped past definitions?");
2626 // Add NumOps>>3 registers to MatchedRegs.
2627 RegsForValue MatchedRegs;
2628 MatchedRegs.ValueVT = InOperandVal.getValueType();
2629 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2630 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2631 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2632 MatchedRegs.Regs.push_back(Reg);
2635 // Use the produced MatchedRegs object to
2636 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2637 TLI.getPointerTy());
2638 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2642 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2643 if (ConstraintCode.size() == 1) // not a physreg name.
2644 CTy = TLI.getConstraintType(ConstraintCode[0]);
2646 if (CTy == TargetLowering::C_Other) {
2647 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
2648 ConstraintCode[0], DAG);
2649 if (!InOperandVal.Val) {
2650 cerr << "Invalid operand for inline asm constraint '"
2651 << ConstraintCode << "'!\n";
2655 // Add information to the INLINEASM node to know about this input.
2656 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2657 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2658 AsmNodeOperands.push_back(InOperandVal);
2660 } else if (CTy == TargetLowering::C_Memory) {
2663 // Check that the operand isn't a float.
2664 if (!MVT::isInteger(InOperandVal.getValueType()))
2665 assert(0 && "MATCH FAIL!");
2667 // Extend/truncate to the right pointer type if needed.
2668 MVT::ValueType PtrType = TLI.getPointerTy();
2669 if (InOperandVal.getValueType() < PtrType)
2670 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2671 else if (InOperandVal.getValueType() > PtrType)
2672 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2674 // Add information to the INLINEASM node to know about this input.
2675 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2676 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2677 AsmNodeOperands.push_back(InOperandVal);
2681 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2683 // Copy the input into the appropriate registers.
2684 RegsForValue InRegs =
2685 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2686 false, true, OutputRegs, InputRegs);
2687 // FIXME: should be match fail.
2688 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2690 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
2692 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2695 case InlineAsm::isClobber: {
2696 RegsForValue ClobberedRegs =
2697 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2698 OutputRegs, InputRegs);
2699 // Add the clobbered value to the operand list, so that the register
2700 // allocator is aware that the physreg got clobbered.
2701 if (!ClobberedRegs.Regs.empty())
2702 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2708 // Finish up input operands.
2709 AsmNodeOperands[0] = Chain;
2710 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2712 Chain = DAG.getNode(ISD::INLINEASM,
2713 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
2714 &AsmNodeOperands[0], AsmNodeOperands.size());
2715 Flag = Chain.getValue(1);
2717 // If this asm returns a register value, copy the result from that register
2718 // and set it as the value of the call.
2719 if (!RetValRegs.Regs.empty())
2720 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2722 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2724 // Process indirect outputs, first output all of the flagged copies out of
2726 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2727 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2728 Value *Ptr = IndirectStoresToEmit[i].second;
2729 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2730 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2733 // Emit the non-flagged stores from the physregs.
2734 SmallVector<SDOperand, 8> OutChains;
2735 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2736 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
2737 getValue(StoresToEmit[i].second),
2738 StoresToEmit[i].second, 0));
2739 if (!OutChains.empty())
2740 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2741 &OutChains[0], OutChains.size());
2746 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2747 SDOperand Src = getValue(I.getOperand(0));
2749 MVT::ValueType IntPtr = TLI.getPointerTy();
2751 if (IntPtr < Src.getValueType())
2752 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2753 else if (IntPtr > Src.getValueType())
2754 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2756 // Scale the source by the type size.
2757 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2758 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2759 Src, getIntPtrConstant(ElementSize));
2761 TargetLowering::ArgListTy Args;
2762 TargetLowering::ArgListEntry Entry;
2764 Entry.Ty = TLI.getTargetData()->getIntPtrType();
2765 Entry.isSigned = false;
2766 Entry.isInReg = false;
2767 Entry.isSRet = false;
2768 Args.push_back(Entry);
2770 std::pair<SDOperand,SDOperand> Result =
2771 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
2772 DAG.getExternalSymbol("malloc", IntPtr),
2774 setValue(&I, Result.first); // Pointers always fit in registers
2775 DAG.setRoot(Result.second);
2778 void SelectionDAGLowering::visitFree(FreeInst &I) {
2779 TargetLowering::ArgListTy Args;
2780 TargetLowering::ArgListEntry Entry;
2781 Entry.Node = getValue(I.getOperand(0));
2782 Entry.Ty = TLI.getTargetData()->getIntPtrType();
2783 Entry.isSigned = false;
2784 Entry.isInReg = false;
2785 Entry.isSRet = false;
2786 Args.push_back(Entry);
2787 MVT::ValueType IntPtr = TLI.getPointerTy();
2788 std::pair<SDOperand,SDOperand> Result =
2789 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
2790 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2791 DAG.setRoot(Result.second);
2794 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2795 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2796 // instructions are special in various ways, which require special support to
2797 // insert. The specified MachineInstr is created but not inserted into any
2798 // basic blocks, and the scheduler passes ownership of it to this method.
2799 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2800 MachineBasicBlock *MBB) {
2801 cerr << "If a target marks an instruction with "
2802 << "'usesCustomDAGSchedInserter', it must implement "
2803 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
2808 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2809 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2810 getValue(I.getOperand(1)),
2811 DAG.getSrcValue(I.getOperand(1))));
2814 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2815 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2816 getValue(I.getOperand(0)),
2817 DAG.getSrcValue(I.getOperand(0)));
2819 DAG.setRoot(V.getValue(1));
2822 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2823 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2824 getValue(I.getOperand(1)),
2825 DAG.getSrcValue(I.getOperand(1))));
2828 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2829 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2830 getValue(I.getOperand(1)),
2831 getValue(I.getOperand(2)),
2832 DAG.getSrcValue(I.getOperand(1)),
2833 DAG.getSrcValue(I.getOperand(2))));
2836 /// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either
2837 /// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate.
2838 static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg,
2839 unsigned &i, SelectionDAG &DAG,
2840 TargetLowering &TLI) {
2841 if (TLI.getTypeAction(VT) != TargetLowering::Expand)
2842 return SDOperand(Arg, i++);
2844 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
2845 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
2847 return DAG.getNode(ISD::BIT_CONVERT, VT,
2848 ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI));
2849 } else if (NumVals == 2) {
2850 SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
2851 SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
2852 if (!TLI.isLittleEndian())
2854 return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
2856 // Value scalarized into many values. Unimp for now.
2857 assert(0 && "Cannot expand i64 -> i16 yet!");
2862 /// TargetLowering::LowerArguments - This is the default LowerArguments
2863 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2864 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2865 /// integrated into SDISel.
2866 std::vector<SDOperand>
2867 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2868 const FunctionType *FTy = F.getFunctionType();
2869 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2870 std::vector<SDOperand> Ops;
2871 Ops.push_back(DAG.getRoot());
2872 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2873 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2875 // Add one result value for each formal argument.
2876 std::vector<MVT::ValueType> RetVals;
2878 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
2880 MVT::ValueType VT = getValueType(I->getType());
2881 bool isInReg = FTy->paramHasAttr(j, FunctionType::InRegAttribute);
2882 bool isSRet = FTy->paramHasAttr(j, FunctionType::StructRetAttribute);
2883 unsigned Flags = (isInReg << 1) | (isSRet << 2);
2885 switch (getTypeAction(VT)) {
2886 default: assert(0 && "Unknown type action!");
2888 RetVals.push_back(VT);
2889 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
2892 RetVals.push_back(getTypeToTransformTo(VT));
2893 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
2896 if (VT != MVT::Vector) {
2897 // If this is a large integer, it needs to be broken up into small
2898 // integers. Figure out what the destination type is and how many small
2899 // integers it turns into.
2900 MVT::ValueType NVT = getTypeToExpandTo(VT);
2901 unsigned NumVals = getNumElements(VT);
2902 for (unsigned i = 0; i != NumVals; ++i) {
2903 RetVals.push_back(NVT);
2904 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
2907 // Otherwise, this is a vector type. We only support legal vectors
2909 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2910 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2912 // Figure out if there is a Packed type corresponding to this Vector
2913 // type. If so, convert to the packed type.
2914 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2915 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2916 RetVals.push_back(TVT);
2917 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
2919 assert(0 && "Don't support illegal by-val vector arguments yet!");
2926 RetVals.push_back(MVT::Other);
2929 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
2930 DAG.getNodeValueTypes(RetVals), RetVals.size(),
2931 &Ops[0], Ops.size()).Val;
2933 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2935 // Set up the return result vector.
2939 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
2941 MVT::ValueType VT = getValueType(I->getType());
2943 switch (getTypeAction(VT)) {
2944 default: assert(0 && "Unknown type action!");
2946 Ops.push_back(SDOperand(Result, i++));
2949 SDOperand Op(Result, i++);
2950 if (MVT::isInteger(VT)) {
2951 if (FTy->paramHasAttr(Idx, FunctionType::SExtAttribute))
2952 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
2953 DAG.getValueType(VT));
2954 else if (FTy->paramHasAttr(Idx, FunctionType::ZExtAttribute))
2955 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
2956 DAG.getValueType(VT));
2957 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2959 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2960 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2966 if (VT != MVT::Vector) {
2967 // If this is a large integer or a floating point node that needs to be
2968 // expanded, it needs to be reassembled from small integers. Figure out
2969 // what the source elt type is and how many small integers it is.
2970 Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this));
2972 // Otherwise, this is a vector type. We only support legal vectors
2974 const PackedType *PTy = cast<PackedType>(I->getType());
2975 unsigned NumElems = PTy->getNumElements();
2976 const Type *EltTy = PTy->getElementType();
2978 // Figure out if there is a Packed type corresponding to this Vector
2979 // type. If so, convert to the packed type.
2980 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2981 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2982 SDOperand N = SDOperand(Result, i++);
2983 // Handle copies from generic vectors to registers.
2984 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2985 DAG.getConstant(NumElems, MVT::i32),
2986 DAG.getValueType(getValueType(EltTy)));
2989 assert(0 && "Don't support illegal by-val vector arguments yet!");
3000 /// ExpandScalarCallArgs - Recursively expand call argument node by
3001 /// bit_converting it or extract a pair of elements from the larger node.
3002 static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg,
3004 SmallVector<SDOperand, 32> &Ops,
3006 TargetLowering &TLI) {
3007 if (TLI.getTypeAction(VT) != TargetLowering::Expand) {
3009 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3013 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
3014 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
3016 Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg);
3017 ExpandScalarCallArgs(EVT, Arg, Flags, Ops, DAG, TLI);
3018 } else if (NumVals == 2) {
3019 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
3020 DAG.getConstant(0, TLI.getPointerTy()));
3021 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
3022 DAG.getConstant(1, TLI.getPointerTy()));
3023 if (!TLI.isLittleEndian())
3025 ExpandScalarCallArgs(EVT, Lo, Flags, Ops, DAG, TLI);
3026 ExpandScalarCallArgs(EVT, Hi, Flags, Ops, DAG, TLI);
3028 // Value scalarized into many values. Unimp for now.
3029 assert(0 && "Cannot expand i64 -> i16 yet!");
3033 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
3034 /// implementation, which just inserts an ISD::CALL node, which is later custom
3035 /// lowered by the target to something concrete. FIXME: When all targets are
3036 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
3037 std::pair<SDOperand, SDOperand>
3038 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
3039 bool RetTyIsSigned, bool isVarArg,
3040 unsigned CallingConv, bool isTailCall,
3042 ArgListTy &Args, SelectionDAG &DAG) {
3043 SmallVector<SDOperand, 32> Ops;
3044 Ops.push_back(Chain); // Op#0 - Chain
3045 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
3046 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
3047 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
3048 Ops.push_back(Callee);
3050 // Handle all of the outgoing arguments.
3051 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
3052 MVT::ValueType VT = getValueType(Args[i].Ty);
3053 SDOperand Op = Args[i].Node;
3054 bool isSigned = Args[i].isSigned;
3055 bool isInReg = Args[i].isInReg;
3056 bool isSRet = Args[i].isSRet;
3057 unsigned Flags = (isSRet << 2) | (isInReg << 1) | isSigned;
3058 switch (getTypeAction(VT)) {
3059 default: assert(0 && "Unknown type action!");
3062 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3065 if (MVT::isInteger(VT)) {
3066 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3067 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
3069 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3070 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
3073 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3076 if (VT != MVT::Vector) {
3077 // If this is a large integer, it needs to be broken down into small
3078 // integers. Figure out what the source elt type is and how many small
3080 ExpandScalarCallArgs(VT, Op, Flags, Ops, DAG, *this);
3082 // Otherwise, this is a vector type. We only support legal vectors
3084 const PackedType *PTy = cast<PackedType>(Args[i].Ty);
3085 unsigned NumElems = PTy->getNumElements();
3086 const Type *EltTy = PTy->getElementType();
3088 // Figure out if there is a Packed type corresponding to this Vector
3089 // type. If so, convert to the packed type.
3090 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3091 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3092 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
3093 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
3095 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3097 assert(0 && "Don't support illegal by-val vector call args yet!");
3105 // Figure out the result value types.
3106 SmallVector<MVT::ValueType, 4> RetTys;
3108 if (RetTy != Type::VoidTy) {
3109 MVT::ValueType VT = getValueType(RetTy);
3110 switch (getTypeAction(VT)) {
3111 default: assert(0 && "Unknown type action!");
3113 RetTys.push_back(VT);
3116 RetTys.push_back(getTypeToTransformTo(VT));
3119 if (VT != MVT::Vector) {
3120 // If this is a large integer, it needs to be reassembled from small
3121 // integers. Figure out what the source elt type is and how many small
3123 MVT::ValueType NVT = getTypeToExpandTo(VT);
3124 unsigned NumVals = getNumElements(VT);
3125 for (unsigned i = 0; i != NumVals; ++i)
3126 RetTys.push_back(NVT);
3128 // Otherwise, this is a vector type. We only support legal vectors
3130 const PackedType *PTy = cast<PackedType>(RetTy);
3131 unsigned NumElems = PTy->getNumElements();
3132 const Type *EltTy = PTy->getElementType();
3134 // Figure out if there is a Packed type corresponding to this Vector
3135 // type. If so, convert to the packed type.
3136 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3137 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3138 RetTys.push_back(TVT);
3140 assert(0 && "Don't support illegal by-val vector call results yet!");
3147 RetTys.push_back(MVT::Other); // Always has a chain.
3149 // Finally, create the CALL node.
3150 SDOperand Res = DAG.getNode(ISD::CALL,
3151 DAG.getVTList(&RetTys[0], RetTys.size()),
3152 &Ops[0], Ops.size());
3154 // This returns a pair of operands. The first element is the
3155 // return value for the function (if RetTy is not VoidTy). The second
3156 // element is the outgoing token chain.
3158 if (RetTys.size() != 1) {
3159 MVT::ValueType VT = getValueType(RetTy);
3160 if (RetTys.size() == 2) {
3163 // If this value was promoted, truncate it down.
3164 if (ResVal.getValueType() != VT) {
3165 if (VT == MVT::Vector) {
3166 // Insert a VBITCONVERT to convert from the packed result type to the
3167 // MVT::Vector type.
3168 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
3169 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
3171 // Figure out if there is a Packed type corresponding to this Vector
3172 // type. If so, convert to the packed type.
3173 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3174 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3175 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
3176 // "N x PTyElementVT" MVT::Vector type.
3177 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
3178 DAG.getConstant(NumElems, MVT::i32),
3179 DAG.getValueType(getValueType(EltTy)));
3183 } else if (MVT::isInteger(VT)) {
3184 unsigned AssertOp = ISD::AssertSext;
3186 AssertOp = ISD::AssertZext;
3187 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
3188 DAG.getValueType(VT));
3189 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
3191 assert(MVT::isFloatingPoint(VT));
3192 if (getTypeAction(VT) == Expand)
3193 ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal);
3195 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
3198 } else if (RetTys.size() == 3) {
3199 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
3200 Res.getValue(0), Res.getValue(1));
3203 assert(0 && "Case not handled yet!");
3207 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
3212 // It is always conservatively correct for llvm.returnaddress and
3213 // llvm.frameaddress to return 0.
3215 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
3216 // expanded to 0 if the target wants.
3217 std::pair<SDOperand, SDOperand>
3218 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
3219 unsigned Depth, SelectionDAG &DAG) {
3220 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
3223 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3224 assert(0 && "LowerOperation not implemented for this target!");
3229 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
3230 SelectionDAG &DAG) {
3231 assert(0 && "CustomPromoteOperation not implemented for this target!");
3236 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
3237 unsigned Depth = (unsigned)cast<ConstantInt>(I.getOperand(1))->getZExtValue();
3238 std::pair<SDOperand,SDOperand> Result =
3239 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
3240 setValue(&I, Result.first);
3241 DAG.setRoot(Result.second);
3244 /// getMemsetValue - Vectorized representation of the memset value
3246 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
3247 SelectionDAG &DAG) {
3248 MVT::ValueType CurVT = VT;
3249 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
3250 uint64_t Val = C->getValue() & 255;
3252 while (CurVT != MVT::i8) {
3253 Val = (Val << Shift) | Val;
3255 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
3257 return DAG.getConstant(Val, VT);
3259 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
3261 while (CurVT != MVT::i8) {
3263 DAG.getNode(ISD::OR, VT,
3264 DAG.getNode(ISD::SHL, VT, Value,
3265 DAG.getConstant(Shift, MVT::i8)), Value);
3267 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
3274 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
3275 /// used when a memcpy is turned into a memset when the source is a constant
3277 static SDOperand getMemsetStringVal(MVT::ValueType VT,
3278 SelectionDAG &DAG, TargetLowering &TLI,
3279 std::string &Str, unsigned Offset) {
3281 unsigned MSB = getSizeInBits(VT) / 8;
3282 if (TLI.isLittleEndian())
3283 Offset = Offset + MSB - 1;
3284 for (unsigned i = 0; i != MSB; ++i) {
3285 Val = (Val << 8) | (unsigned char)Str[Offset];
3286 Offset += TLI.isLittleEndian() ? -1 : 1;
3288 return DAG.getConstant(Val, VT);
3291 /// getMemBasePlusOffset - Returns base and offset node for the
3292 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
3293 SelectionDAG &DAG, TargetLowering &TLI) {
3294 MVT::ValueType VT = Base.getValueType();
3295 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
3298 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
3299 /// to replace the memset / memcpy is below the threshold. It also returns the
3300 /// types of the sequence of memory ops to perform memset / memcpy.
3301 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
3302 unsigned Limit, uint64_t Size,
3303 unsigned Align, TargetLowering &TLI) {
3306 if (TLI.allowsUnalignedMemoryAccesses()) {
3309 switch (Align & 7) {
3325 MVT::ValueType LVT = MVT::i64;
3326 while (!TLI.isTypeLegal(LVT))
3327 LVT = (MVT::ValueType)((unsigned)LVT - 1);
3328 assert(MVT::isInteger(LVT));
3333 unsigned NumMemOps = 0;
3335 unsigned VTSize = getSizeInBits(VT) / 8;
3336 while (VTSize > Size) {
3337 VT = (MVT::ValueType)((unsigned)VT - 1);
3340 assert(MVT::isInteger(VT));
3342 if (++NumMemOps > Limit)
3344 MemOps.push_back(VT);
3351 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
3352 SDOperand Op1 = getValue(I.getOperand(1));
3353 SDOperand Op2 = getValue(I.getOperand(2));
3354 SDOperand Op3 = getValue(I.getOperand(3));
3355 SDOperand Op4 = getValue(I.getOperand(4));
3356 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
3357 if (Align == 0) Align = 1;
3359 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
3360 std::vector<MVT::ValueType> MemOps;
3362 // Expand memset / memcpy to a series of load / store ops
3363 // if the size operand falls below a certain threshold.
3364 SmallVector<SDOperand, 8> OutChains;
3366 default: break; // Do nothing for now.
3368 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
3369 Size->getValue(), Align, TLI)) {
3370 unsigned NumMemOps = MemOps.size();
3371 unsigned Offset = 0;
3372 for (unsigned i = 0; i < NumMemOps; i++) {
3373 MVT::ValueType VT = MemOps[i];
3374 unsigned VTSize = getSizeInBits(VT) / 8;
3375 SDOperand Value = getMemsetValue(Op2, VT, DAG);
3376 SDOperand Store = DAG.getStore(getRoot(), Value,
3377 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
3378 I.getOperand(1), Offset);
3379 OutChains.push_back(Store);
3386 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
3387 Size->getValue(), Align, TLI)) {
3388 unsigned NumMemOps = MemOps.size();
3389 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
3390 GlobalAddressSDNode *G = NULL;
3392 bool CopyFromStr = false;
3394 if (Op2.getOpcode() == ISD::GlobalAddress)
3395 G = cast<GlobalAddressSDNode>(Op2);
3396 else if (Op2.getOpcode() == ISD::ADD &&
3397 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3398 Op2.getOperand(1).getOpcode() == ISD::Constant) {
3399 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
3400 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
3403 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
3404 if (GV && GV->isConstant()) {
3405 Str = GV->getStringValue(false);
3413 for (unsigned i = 0; i < NumMemOps; i++) {
3414 MVT::ValueType VT = MemOps[i];
3415 unsigned VTSize = getSizeInBits(VT) / 8;
3416 SDOperand Value, Chain, Store;
3419 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
3422 DAG.getStore(Chain, Value,
3423 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
3424 I.getOperand(1), DstOff);
3426 Value = DAG.getLoad(VT, getRoot(),
3427 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
3428 I.getOperand(2), SrcOff);
3429 Chain = Value.getValue(1);
3431 DAG.getStore(Chain, Value,
3432 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
3433 I.getOperand(1), DstOff);
3435 OutChains.push_back(Store);
3444 if (!OutChains.empty()) {
3445 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3446 &OutChains[0], OutChains.size()));
3451 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
3454 //===----------------------------------------------------------------------===//
3455 // SelectionDAGISel code
3456 //===----------------------------------------------------------------------===//
3458 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
3459 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
3462 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
3463 // FIXME: we only modify the CFG to split critical edges. This
3464 // updates dom and loop info.
3465 AU.addRequired<AliasAnalysis>();
3469 /// OptimizeNoopCopyExpression - We have determined that the specified cast
3470 /// instruction is a noop copy (e.g. it's casting from one pointer type to
3471 /// another, int->uint, or int->sbyte on PPC.
3473 /// Return true if any changes are made.
3474 static bool OptimizeNoopCopyExpression(CastInst *CI) {
3475 BasicBlock *DefBB = CI->getParent();
3477 /// InsertedCasts - Only insert a cast in each block once.
3478 std::map<BasicBlock*, CastInst*> InsertedCasts;
3480 bool MadeChange = false;
3481 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
3483 Use &TheUse = UI.getUse();
3484 Instruction *User = cast<Instruction>(*UI);
3486 // Figure out which BB this cast is used in. For PHI's this is the
3487 // appropriate predecessor block.
3488 BasicBlock *UserBB = User->getParent();
3489 if (PHINode *PN = dyn_cast<PHINode>(User)) {
3490 unsigned OpVal = UI.getOperandNo()/2;
3491 UserBB = PN->getIncomingBlock(OpVal);
3494 // Preincrement use iterator so we don't invalidate it.
3497 // If this user is in the same block as the cast, don't change the cast.
3498 if (UserBB == DefBB) continue;
3500 // If we have already inserted a cast into this block, use it.
3501 CastInst *&InsertedCast = InsertedCasts[UserBB];
3503 if (!InsertedCast) {
3504 BasicBlock::iterator InsertPt = UserBB->begin();
3505 while (isa<PHINode>(InsertPt)) ++InsertPt;
3508 CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "",
3513 // Replace a use of the cast with a use of the new casat.
3514 TheUse = InsertedCast;
3517 // If we removed all uses, nuke the cast.
3518 if (CI->use_empty())
3519 CI->eraseFromParent();
3524 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3525 /// casting to the type of GEPI.
3526 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3527 Instruction *GEPI, Value *Ptr,
3529 if (V) return V; // Already computed.
3531 // Figure out the insertion point
3532 BasicBlock::iterator InsertPt;
3533 if (BB == GEPI->getParent()) {
3534 // If GEP is already inserted into BB, insert right after the GEP.
3538 // Otherwise, insert at the top of BB, after any PHI nodes
3539 InsertPt = BB->begin();
3540 while (isa<PHINode>(InsertPt)) ++InsertPt;
3543 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3544 // BB so that there is only one value live across basic blocks (the cast
3546 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3547 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3548 Ptr = CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(),
3551 // Add the offset, cast it to the right type.
3552 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3553 // Ptr is an integer type, GEPI is pointer type ==> IntToPtr
3554 return V = CastInst::create(Instruction::IntToPtr, Ptr, GEPI->getType(),
3558 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3559 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3560 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3561 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3562 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3563 /// the constant add into a load or store instruction. Additionally, if a user
3564 /// is a pointer-pointer cast, we look through it to find its users.
3565 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3566 Constant *PtrOffset, BasicBlock *DefBB,
3567 GetElementPtrInst *GEPI,
3568 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3569 while (!RepPtr->use_empty()) {
3570 Instruction *User = cast<Instruction>(RepPtr->use_back());
3572 // If the user is a Pointer-Pointer cast, recurse. Only BitCast can be
3573 // used for a Pointer-Pointer cast.
3574 if (isa<BitCastInst>(User)) {
3575 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3577 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3578 // could invalidate an iterator.
3579 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3583 // If this is a load of the pointer, or a store through the pointer, emit
3584 // the increment into the load/store block.
3585 Instruction *NewVal;
3586 if (isa<LoadInst>(User) ||
3587 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3588 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3589 User->getParent(), GEPI,
3592 // If this use is not foldable into the addressing mode, use a version
3593 // emitted in the GEP block.
3594 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3598 if (GEPI->getType() != RepPtr->getType()) {
3599 BasicBlock::iterator IP = NewVal;
3601 // NewVal must be a GEP which must be pointer type, so BitCast
3602 NewVal = new BitCastInst(NewVal, RepPtr->getType(), "", IP);
3604 User->replaceUsesOfWith(RepPtr, NewVal);
3609 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3610 /// selection, we want to be a bit careful about some things. In particular, if
3611 /// we have a GEP instruction that is used in a different block than it is
3612 /// defined, the addressing expression of the GEP cannot be folded into loads or
3613 /// stores that use it. In this case, decompose the GEP and move constant
3614 /// indices into blocks that use it.
3615 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3616 const TargetData *TD) {
3617 // If this GEP is only used inside the block it is defined in, there is no
3618 // need to rewrite it.
3619 bool isUsedOutsideDefBB = false;
3620 BasicBlock *DefBB = GEPI->getParent();
3621 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3623 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3624 isUsedOutsideDefBB = true;
3628 if (!isUsedOutsideDefBB) return false;
3630 // If this GEP has no non-zero constant indices, there is nothing we can do,
3632 bool hasConstantIndex = false;
3633 bool hasVariableIndex = false;
3634 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3635 E = GEPI->op_end(); OI != E; ++OI) {
3636 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3637 if (CI->getZExtValue()) {
3638 hasConstantIndex = true;
3642 hasVariableIndex = true;
3646 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3647 if (!hasConstantIndex && !hasVariableIndex) {
3648 /// The GEP operand must be a pointer, so must its result -> BitCast
3649 Value *NC = new BitCastInst(GEPI->getOperand(0), GEPI->getType(),
3650 GEPI->getName(), GEPI);
3651 GEPI->replaceAllUsesWith(NC);
3652 GEPI->eraseFromParent();
3656 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3657 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3660 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3661 // constant offset (which we now know is non-zero) and deal with it later.
3662 uint64_t ConstantOffset = 0;
3663 const Type *UIntPtrTy = TD->getIntPtrType();
3664 Value *Ptr = new PtrToIntInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3665 const Type *Ty = GEPI->getOperand(0)->getType();
3667 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3668 E = GEPI->op_end(); OI != E; ++OI) {
3670 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3671 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3673 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3674 Ty = StTy->getElementType(Field);
3676 Ty = cast<SequentialType>(Ty)->getElementType();
3678 // Handle constant subscripts.
3679 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3680 if (CI->getZExtValue() == 0) continue;
3681 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CI->getSExtValue();
3685 // Ptr = Ptr + Idx * ElementSize;
3687 // Cast Idx to UIntPtrTy if needed.
3688 Idx = CastInst::createIntegerCast(Idx, UIntPtrTy, true/*SExt*/, "", GEPI);
3690 uint64_t ElementSize = TD->getTypeSize(Ty);
3691 // Mask off bits that should not be set.
3692 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3693 Constant *SizeCst = ConstantInt::get(UIntPtrTy, ElementSize);
3695 // Multiply by the element size and add to the base.
3696 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3697 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3701 // Make sure that the offset fits in uintptr_t.
3702 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3703 Constant *PtrOffset = ConstantInt::get(UIntPtrTy, ConstantOffset);
3705 // Okay, we have now emitted all of the variable index parts to the BB that
3706 // the GEP is defined in. Loop over all of the using instructions, inserting
3707 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3708 // instruction to use the newly computed value, making GEPI dead. When the
3709 // user is a load or store instruction address, we emit the add into the user
3710 // block, otherwise we use a canonical version right next to the gep (these
3711 // won't be foldable as addresses, so we might as well share the computation).
3713 std::map<BasicBlock*,Instruction*> InsertedExprs;
3714 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3716 // Finally, the GEP is dead, remove it.
3717 GEPI->eraseFromParent();
3723 /// SplitEdgeNicely - Split the critical edge from TI to it's specified
3724 /// successor if it will improve codegen. We only do this if the successor has
3725 /// phi nodes (otherwise critical edges are ok). If there is already another
3726 /// predecessor of the succ that is empty (and thus has no phi nodes), use it
3727 /// instead of introducing a new block.
3728 static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum, Pass *P) {
3729 BasicBlock *TIBB = TI->getParent();
3730 BasicBlock *Dest = TI->getSuccessor(SuccNum);
3731 assert(isa<PHINode>(Dest->begin()) &&
3732 "This should only be called if Dest has a PHI!");
3734 /// TIPHIValues - This array is lazily computed to determine the values of
3735 /// PHIs in Dest that TI would provide.
3736 std::vector<Value*> TIPHIValues;
3738 // Check to see if Dest has any blocks that can be used as a split edge for
3740 for (pred_iterator PI = pred_begin(Dest), E = pred_end(Dest); PI != E; ++PI) {
3741 BasicBlock *Pred = *PI;
3742 // To be usable, the pred has to end with an uncond branch to the dest.
3743 BranchInst *PredBr = dyn_cast<BranchInst>(Pred->getTerminator());
3744 if (!PredBr || !PredBr->isUnconditional() ||
3745 // Must be empty other than the branch.
3746 &Pred->front() != PredBr)
3749 // Finally, since we know that Dest has phi nodes in it, we have to make
3750 // sure that jumping to Pred will have the same affect as going to Dest in
3751 // terms of PHI values.
3754 bool FoundMatch = true;
3755 for (BasicBlock::iterator I = Dest->begin();
3756 (PN = dyn_cast<PHINode>(I)); ++I, ++PHINo) {
3757 if (PHINo == TIPHIValues.size())
3758 TIPHIValues.push_back(PN->getIncomingValueForBlock(TIBB));
3760 // If the PHI entry doesn't work, we can't use this pred.
3761 if (TIPHIValues[PHINo] != PN->getIncomingValueForBlock(Pred)) {
3767 // If we found a workable predecessor, change TI to branch to Succ.
3769 Dest->removePredecessor(TIBB);
3770 TI->setSuccessor(SuccNum, Pred);
3775 SplitCriticalEdge(TI, SuccNum, P, true);
3779 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3780 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3781 RegMap = MF.getSSARegMap();
3782 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
3784 // First, split all critical edges.
3786 // In this pass we also look for GEP and cast instructions that are used
3787 // across basic blocks and rewrite them to improve basic-block-at-a-time
3790 bool MadeChange = true;
3791 while (MadeChange) {
3793 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3794 // Split all critical edges where the dest block has a PHI.
3795 TerminatorInst *BBTI = BB->getTerminator();
3796 if (BBTI->getNumSuccessors() > 1) {
3797 for (unsigned i = 0, e = BBTI->getNumSuccessors(); i != e; ++i)
3798 if (isa<PHINode>(BBTI->getSuccessor(i)->begin()) &&
3799 isCriticalEdge(BBTI, i, true))
3800 SplitEdgeNicely(BBTI, i, this);
3804 for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) {
3805 Instruction *I = BBI++;
3807 if (CallInst *CI = dyn_cast<CallInst>(I)) {
3808 // If we found an inline asm expession, and if the target knows how to
3809 // lower it to normal LLVM code, do so now.
3810 if (isa<InlineAsm>(CI->getCalledValue()))
3811 if (const TargetAsmInfo *TAI =
3812 TLI.getTargetMachine().getTargetAsmInfo()) {
3813 if (TAI->ExpandInlineAsm(CI))
3816 } else if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3817 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3818 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3819 // If the source of the cast is a constant, then this should have
3820 // already been constant folded. The only reason NOT to constant fold
3821 // it is if something (e.g. LSR) was careful to place the constant
3822 // evaluation in a block other than then one that uses it (e.g. to hoist
3823 // the address of globals out of a loop). If this is the case, we don't
3824 // want to forward-subst the cast.
3825 if (isa<Constant>(CI->getOperand(0)))
3828 // If this is a noop copy, sink it into user blocks to reduce the number
3829 // of virtual registers that must be created and coallesced.
3830 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3831 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3833 // This is an fp<->int conversion?
3834 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3837 // If this is an extension, it will be a zero or sign extension, which
3839 if (SrcVT < DstVT) continue;
3841 // If these values will be promoted, find out what they will be promoted
3842 // to. This helps us consider truncates on PPC as noop copies when they
3844 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3845 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3846 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3847 DstVT = TLI.getTypeToTransformTo(DstVT);
3849 // If, after promotion, these are the same types, this is a noop copy.
3851 MadeChange |= OptimizeNoopCopyExpression(CI);
3857 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3859 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3860 SelectBasicBlock(I, MF, FuncInfo);
3865 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
3867 SDOperand Op = getValue(V);
3868 assert((Op.getOpcode() != ISD::CopyFromReg ||
3869 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3870 "Copy from a reg to the same reg!");
3872 // If this type is not legal, we must make sure to not create an invalid
3874 MVT::ValueType SrcVT = Op.getValueType();
3875 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3876 if (SrcVT == DestVT) {
3877 return DAG.getCopyToReg(getRoot(), Reg, Op);
3878 } else if (SrcVT == MVT::Vector) {
3879 // Handle copies from generic vectors to registers.
3880 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3881 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3882 PTyElementVT, PTyLegalElementVT);
3884 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3885 // MVT::Vector type.
3886 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3887 DAG.getConstant(NE, MVT::i32),
3888 DAG.getValueType(PTyElementVT));
3890 // Loop over all of the elements of the resultant vector,
3891 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3892 // copying them into output registers.
3893 SmallVector<SDOperand, 8> OutChains;
3894 SDOperand Root = getRoot();
3895 for (unsigned i = 0; i != NE; ++i) {
3896 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3897 Op, DAG.getConstant(i, TLI.getPointerTy()));
3898 if (PTyElementVT == PTyLegalElementVT) {
3899 // Elements are legal.
3900 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3901 } else if (PTyLegalElementVT > PTyElementVT) {
3902 // Elements are promoted.
3903 if (MVT::isFloatingPoint(PTyLegalElementVT))
3904 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3906 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3907 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3909 // Elements are expanded.
3910 // The src value is expanded into multiple registers.
3911 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3912 Elt, DAG.getConstant(0, TLI.getPointerTy()));
3913 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3914 Elt, DAG.getConstant(1, TLI.getPointerTy()));
3915 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3916 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3919 return DAG.getNode(ISD::TokenFactor, MVT::Other,
3920 &OutChains[0], OutChains.size());
3921 } else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) {
3922 // The src value is promoted to the register.
3923 if (MVT::isFloatingPoint(SrcVT))
3924 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3926 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3927 return DAG.getCopyToReg(getRoot(), Reg, Op);
3929 DestVT = TLI.getTypeToExpandTo(SrcVT);
3930 unsigned NumVals = TLI.getNumElements(SrcVT);
3932 return DAG.getCopyToReg(getRoot(), Reg,
3933 DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
3934 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
3935 // The src value is expanded into multiple registers.
3936 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3937 Op, DAG.getConstant(0, TLI.getPointerTy()));
3938 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3939 Op, DAG.getConstant(1, TLI.getPointerTy()));
3940 Op = DAG.getCopyToReg(getRoot(), Reg, Lo);
3941 return DAG.getCopyToReg(Op, Reg+1, Hi);
3945 void SelectionDAGISel::
3946 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3947 std::vector<SDOperand> &UnorderedChains) {
3948 // If this is the entry block, emit arguments.
3949 Function &F = *BB->getParent();
3950 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3951 SDOperand OldRoot = SDL.DAG.getRoot();
3952 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3955 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3957 if (!AI->use_empty()) {
3958 SDL.setValue(AI, Args[a]);
3960 // If this argument is live outside of the entry block, insert a copy from
3961 // whereever we got it to the vreg that other BB's will reference it as.
3962 if (FuncInfo.ValueMap.count(AI)) {
3964 SDL.CopyValueToVirtualRegister(AI, FuncInfo.ValueMap[AI]);
3965 UnorderedChains.push_back(Copy);
3969 // Finally, if the target has anything special to do, allow it to do so.
3970 // FIXME: this should insert code into the DAG!
3971 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3974 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3975 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3976 FunctionLoweringInfo &FuncInfo) {
3977 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3979 std::vector<SDOperand> UnorderedChains;
3981 // Lower any arguments needed in this block if this is the entry block.
3982 if (LLVMBB == &LLVMBB->getParent()->front())
3983 LowerArguments(LLVMBB, SDL, UnorderedChains);
3985 BB = FuncInfo.MBBMap[LLVMBB];
3986 SDL.setCurrentBasicBlock(BB);
3988 // Lower all of the non-terminator instructions.
3989 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3993 // Ensure that all instructions which are used outside of their defining
3994 // blocks are available as virtual registers.
3995 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3996 if (!I->use_empty() && !isa<PHINode>(I)) {
3997 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3998 if (VMI != FuncInfo.ValueMap.end())
3999 UnorderedChains.push_back(
4000 SDL.CopyValueToVirtualRegister(I, VMI->second));
4003 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4004 // ensure constants are generated when needed. Remember the virtual registers
4005 // that need to be added to the Machine PHI nodes as input. We cannot just
4006 // directly add them, because expansion might result in multiple MBB's for one
4007 // BB. As such, the start of the BB might correspond to a different MBB than
4010 TerminatorInst *TI = LLVMBB->getTerminator();
4012 // Emit constants only once even if used by multiple PHI nodes.
4013 std::map<Constant*, unsigned> ConstantsOut;
4015 // Vector bool would be better, but vector<bool> is really slow.
4016 std::vector<unsigned char> SuccsHandled;
4017 if (TI->getNumSuccessors())
4018 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4020 // Check successor nodes PHI nodes that expect a constant to be available from
4022 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4023 BasicBlock *SuccBB = TI->getSuccessor(succ);
4024 if (!isa<PHINode>(SuccBB->begin())) continue;
4025 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4027 // If this terminator has multiple identical successors (common for
4028 // switches), only handle each succ once.
4029 unsigned SuccMBBNo = SuccMBB->getNumber();
4030 if (SuccsHandled[SuccMBBNo]) continue;
4031 SuccsHandled[SuccMBBNo] = true;
4033 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4036 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4037 // nodes and Machine PHI nodes, but the incoming operands have not been
4039 for (BasicBlock::iterator I = SuccBB->begin();
4040 (PN = dyn_cast<PHINode>(I)); ++I) {
4041 // Ignore dead phi's.
4042 if (PN->use_empty()) continue;
4045 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4047 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4048 unsigned &RegOut = ConstantsOut[C];
4050 RegOut = FuncInfo.CreateRegForValue(C);
4051 UnorderedChains.push_back(
4052 SDL.CopyValueToVirtualRegister(C, RegOut));
4056 Reg = FuncInfo.ValueMap[PHIOp];
4058 assert(isa<AllocaInst>(PHIOp) &&
4059 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4060 "Didn't codegen value into a register!??");
4061 Reg = FuncInfo.CreateRegForValue(PHIOp);
4062 UnorderedChains.push_back(
4063 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4067 // Remember that this register needs to added to the machine PHI node as
4068 // the input for this MBB.
4069 MVT::ValueType VT = TLI.getValueType(PN->getType());
4070 unsigned NumElements;
4071 if (VT != MVT::Vector)
4072 NumElements = TLI.getNumElements(VT);
4074 MVT::ValueType VT1,VT2;
4076 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
4079 for (unsigned i = 0, e = NumElements; i != e; ++i)
4080 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4083 ConstantsOut.clear();
4085 // Turn all of the unordered chains into one factored node.
4086 if (!UnorderedChains.empty()) {
4087 SDOperand Root = SDL.getRoot();
4088 if (Root.getOpcode() != ISD::EntryToken) {
4089 unsigned i = 0, e = UnorderedChains.size();
4090 for (; i != e; ++i) {
4091 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4092 if (UnorderedChains[i].Val->getOperand(0) == Root)
4093 break; // Don't add the root if we already indirectly depend on it.
4097 UnorderedChains.push_back(Root);
4099 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4100 &UnorderedChains[0], UnorderedChains.size()));
4103 // Lower the terminator after the copies are emitted.
4104 SDL.visit(*LLVMBB->getTerminator());
4106 // Copy over any CaseBlock records that may now exist due to SwitchInst
4107 // lowering, as well as any jump table information.
4108 SwitchCases.clear();
4109 SwitchCases = SDL.SwitchCases;
4112 // Make sure the root of the DAG is up-to-date.
4113 DAG.setRoot(SDL.getRoot());
4116 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4117 // Get alias analysis for load/store combining.
4118 AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
4120 // Run the DAG combiner in pre-legalize mode.
4121 DAG.Combine(false, AA);
4123 DOUT << "Lowered selection DAG:\n";
4126 // Second step, hack on the DAG until it only uses operations and types that
4127 // the target supports.
4130 DOUT << "Legalized selection DAG:\n";
4133 // Run the DAG combiner in post-legalize mode.
4134 DAG.Combine(true, AA);
4136 if (ViewISelDAGs) DAG.viewGraph();
4138 // Third, instruction select all of the operations to machine code, adding the
4139 // code to the MachineBasicBlock.
4140 InstructionSelectBasicBlock(DAG);
4142 DOUT << "Selected machine code:\n";
4146 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4147 FunctionLoweringInfo &FuncInfo) {
4148 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4150 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4153 // First step, lower LLVM code to some DAG. This DAG may use operations and
4154 // types that are not supported by the target.
4155 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4157 // Second step, emit the lowered DAG as machine code.
4158 CodeGenAndEmitDAG(DAG);
4161 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4162 // PHI nodes in successors.
4163 if (SwitchCases.empty() && JT.Reg == 0) {
4164 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4165 MachineInstr *PHI = PHINodesToUpdate[i].first;
4166 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4167 "This is not a machine PHI node that we are updating!");
4168 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4169 PHI->addMachineBasicBlockOperand(BB);
4174 // If the JumpTable record is filled in, then we need to emit a jump table.
4175 // Updating the PHI nodes is tricky in this case, since we need to determine
4176 // whether the PHI is a successor of the range check MBB or the jump table MBB
4178 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
4179 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4181 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4182 MachineBasicBlock *RangeBB = BB;
4183 // Set the current basic block to the mbb we wish to insert the code into
4185 SDL.setCurrentBasicBlock(BB);
4187 SDL.visitJumpTable(JT);
4188 SDAG.setRoot(SDL.getRoot());
4189 CodeGenAndEmitDAG(SDAG);
4191 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4192 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4193 MachineBasicBlock *PHIBB = PHI->getParent();
4194 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4195 "This is not a machine PHI node that we are updating!");
4196 if (PHIBB == JT.Default) {
4197 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4198 PHI->addMachineBasicBlockOperand(RangeBB);
4200 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4201 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4202 PHI->addMachineBasicBlockOperand(BB);
4208 // If the switch block involved a branch to one of the actual successors, we
4209 // need to update PHI nodes in that block.
4210 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4211 MachineInstr *PHI = PHINodesToUpdate[i].first;
4212 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4213 "This is not a machine PHI node that we are updating!");
4214 if (BB->isSuccessor(PHI->getParent())) {
4215 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4216 PHI->addMachineBasicBlockOperand(BB);
4220 // If we generated any switch lowering information, build and codegen any
4221 // additional DAGs necessary.
4222 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4223 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4225 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4227 // Set the current basic block to the mbb we wish to insert the code into
4228 BB = SwitchCases[i].ThisBB;
4229 SDL.setCurrentBasicBlock(BB);
4232 SDL.visitSwitchCase(SwitchCases[i]);
4233 SDAG.setRoot(SDL.getRoot());
4234 CodeGenAndEmitDAG(SDAG);
4236 // Handle any PHI nodes in successors of this chunk, as if we were coming
4237 // from the original BB before switch expansion. Note that PHI nodes can
4238 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4239 // handle them the right number of times.
4240 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4241 for (MachineBasicBlock::iterator Phi = BB->begin();
4242 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4243 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4244 for (unsigned pn = 0; ; ++pn) {
4245 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4246 if (PHINodesToUpdate[pn].first == Phi) {
4247 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4248 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4254 // Don't process RHS if same block as LHS.
4255 if (BB == SwitchCases[i].FalseBB)
4256 SwitchCases[i].FalseBB = 0;
4258 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4259 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4260 SwitchCases[i].FalseBB = 0;
4262 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4267 //===----------------------------------------------------------------------===//
4268 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4269 /// target node in the graph.
4270 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4271 if (ViewSchedDAGs) DAG.viewGraph();
4273 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4277 RegisterScheduler::setDefault(Ctor);
4280 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4286 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4287 return new HazardRecognizer();
4290 //===----------------------------------------------------------------------===//
4291 // Helper functions used by the generated instruction selector.
4292 //===----------------------------------------------------------------------===//
4293 // Calls to these methods are generated by tblgen.
4295 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4296 /// the dag combiner simplified the 255, we still want to match. RHS is the
4297 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4298 /// specified in the .td file (e.g. 255).
4299 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4300 int64_t DesiredMaskS) {
4301 uint64_t ActualMask = RHS->getValue();
4302 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4304 // If the actual mask exactly matches, success!
4305 if (ActualMask == DesiredMask)
4308 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4309 if (ActualMask & ~DesiredMask)
4312 // Otherwise, the DAG Combiner may have proven that the value coming in is
4313 // either already zero or is not demanded. Check for known zero input bits.
4314 uint64_t NeededMask = DesiredMask & ~ActualMask;
4315 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask))
4318 // TODO: check to see if missing bits are just not demanded.
4320 // Otherwise, this pattern doesn't match.
4324 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
4325 /// the dag combiner simplified the 255, we still want to match. RHS is the
4326 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
4327 /// specified in the .td file (e.g. 255).
4328 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
4329 int64_t DesiredMaskS) {
4330 uint64_t ActualMask = RHS->getValue();
4331 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4333 // If the actual mask exactly matches, success!
4334 if (ActualMask == DesiredMask)
4337 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4338 if (ActualMask & ~DesiredMask)
4341 // Otherwise, the DAG Combiner may have proven that the value coming in is
4342 // either already zero or is not demanded. Check for known zero input bits.
4343 uint64_t NeededMask = DesiredMask & ~ActualMask;
4345 uint64_t KnownZero, KnownOne;
4346 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
4348 // If all the missing bits in the or are already known to be set, match!
4349 if ((NeededMask & KnownOne) == NeededMask)
4352 // TODO: check to see if missing bits are just not demanded.
4354 // Otherwise, this pattern doesn't match.
4359 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
4360 /// by tblgen. Others should not call it.
4361 void SelectionDAGISel::
4362 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
4363 std::vector<SDOperand> InOps;
4364 std::swap(InOps, Ops);
4366 Ops.push_back(InOps[0]); // input chain.
4367 Ops.push_back(InOps[1]); // input asm string.
4369 unsigned i = 2, e = InOps.size();
4370 if (InOps[e-1].getValueType() == MVT::Flag)
4371 --e; // Don't process a flag operand if it is here.
4374 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
4375 if ((Flags & 7) != 4 /*MEM*/) {
4376 // Just skip over this operand, copying the operands verbatim.
4377 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
4378 i += (Flags >> 3) + 1;
4380 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
4381 // Otherwise, this is a memory operand. Ask the target to select it.
4382 std::vector<SDOperand> SelOps;
4383 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
4384 cerr << "Could not match memory address. Inline asm failure!\n";
4388 // Add this to the output node.
4389 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
4391 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
4396 // Add the flag input back if present.
4397 if (e != InOps.size())
4398 Ops.push_back(InOps.back());