1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register"
85 static RegisterScheduler
86 defaultListDAGScheduler("default", " Best scheduler for the target",
87 createDefaultScheduler);
90 namespace { struct SDISelAsmOperandInfo; }
92 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
93 /// MVT::ValueTypes that represent all the individual underlying
94 /// non-aggregate types that comprise it.
95 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
96 SmallVectorImpl<MVT::ValueType> &ValueVTs) {
97 // Given a struct type, recursively traverse the elements.
98 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
99 for (StructType::element_iterator EI = STy->element_begin(),
100 EB = STy->element_end();
102 ComputeValueVTs(TLI, *EI, ValueVTs);
105 // Given an array type, recursively traverse the elements.
106 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
107 const Type *EltTy = ATy->getElementType();
108 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
109 ComputeValueVTs(TLI, EltTy, ValueVTs);
112 // Base case: we can get an MVT::ValueType for this LLVM IR type.
113 ValueVTs.push_back(TLI.getValueType(Ty));
117 /// RegsForValue - This struct represents the registers (physical or virtual)
118 /// that a particular set of values is assigned, and the type information about
119 /// the value. The most common situation is to represent one value at a time,
120 /// but struct or array values are handled element-wise as multiple values.
121 /// The splitting of aggregates is performed recursively, so that we never
122 /// have aggregate-typed registers. The values at this point do not necessarily
123 /// have legal types, so each value may require one or more registers of some
126 struct VISIBILITY_HIDDEN RegsForValue {
127 /// TLI - The TargetLowering object.
129 const TargetLowering *TLI;
131 /// ValueVTs - The value types of the values, which may not be legal, and
132 /// may need be promoted or synthesized from one or more registers.
134 SmallVector<MVT::ValueType, 4> ValueVTs;
136 /// RegVTs - The value types of the registers. This is the same size as
137 /// ValueVTs and it records, for each value, what the type of the assigned
138 /// register or registers are. (Individual values are never synthesized
139 /// from more than one type of register.)
141 /// With virtual registers, the contents of RegVTs is redundant with TLI's
142 /// getRegisterType member function, however when with physical registers
143 /// it is necessary to have a separate record of the types.
145 SmallVector<MVT::ValueType, 4> RegVTs;
147 /// Regs - This list holds the registers assigned to the values.
148 /// Each legal or promoted value requires one register, and each
149 /// expanded value requires multiple registers.
151 SmallVector<unsigned, 4> Regs;
153 RegsForValue() : TLI(0) {}
155 RegsForValue(const TargetLowering &tli,
156 const SmallVector<unsigned, 4> ®s,
157 MVT::ValueType regvt, MVT::ValueType valuevt)
158 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
159 RegsForValue(const TargetLowering &tli,
160 const SmallVector<unsigned, 4> ®s,
161 const SmallVector<MVT::ValueType, 4> ®vts,
162 const SmallVector<MVT::ValueType, 4> &valuevts)
163 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
164 RegsForValue(const TargetLowering &tli,
165 unsigned Reg, const Type *Ty) : TLI(&tli) {
166 ComputeValueVTs(tli, Ty, ValueVTs);
168 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
169 MVT::ValueType ValueVT = ValueVTs[Value];
170 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
171 MVT::ValueType RegisterVT = TLI->getRegisterType(ValueVT);
172 for (unsigned i = 0; i != NumRegs; ++i)
173 Regs.push_back(Reg + i);
174 RegVTs.push_back(RegisterVT);
179 /// append - Add the specified values to this one.
180 void append(const RegsForValue &RHS) {
182 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
183 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
184 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
188 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
189 /// this value and returns the result as a ValueVTs value. This uses
190 /// Chain/Flag as the input and updates them for the output Chain/Flag.
191 /// If the Flag pointer is NULL, no flag is used.
192 SDOperand getCopyFromRegs(SelectionDAG &DAG,
193 SDOperand &Chain, SDOperand *Flag) const;
195 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
196 /// specified value into the registers specified by this object. This uses
197 /// Chain/Flag as the input and updates them for the output Chain/Flag.
198 /// If the Flag pointer is NULL, no flag is used.
199 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
200 SDOperand &Chain, SDOperand *Flag) const;
202 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
203 /// operand list. This adds the code marker and includes the number of
204 /// values added into it.
205 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
206 std::vector<SDOperand> &Ops) const;
211 //===--------------------------------------------------------------------===//
212 /// createDefaultScheduler - This creates an instruction scheduler appropriate
214 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
216 MachineBasicBlock *BB) {
217 TargetLowering &TLI = IS->getTargetLowering();
219 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
220 return createTDListDAGScheduler(IS, DAG, BB);
222 assert(TLI.getSchedulingPreference() ==
223 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
224 return createBURRListDAGScheduler(IS, DAG, BB);
229 //===--------------------------------------------------------------------===//
230 /// FunctionLoweringInfo - This contains information that is global to a
231 /// function that is used when lowering a region of the function.
232 class FunctionLoweringInfo {
237 MachineRegisterInfo &RegInfo;
239 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
241 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
242 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
244 /// ValueMap - Since we emit code for the function a basic block at a time,
245 /// we must remember which virtual registers hold the values for
246 /// cross-basic-block values.
247 DenseMap<const Value*, unsigned> ValueMap;
249 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
250 /// the entry block. This allows the allocas to be efficiently referenced
251 /// anywhere in the function.
252 std::map<const AllocaInst*, int> StaticAllocaMap;
255 SmallSet<Instruction*, 8> CatchInfoLost;
256 SmallSet<Instruction*, 8> CatchInfoFound;
259 unsigned MakeReg(MVT::ValueType VT) {
260 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
263 /// isExportedInst - Return true if the specified value is an instruction
264 /// exported from its block.
265 bool isExportedInst(const Value *V) {
266 return ValueMap.count(V);
269 unsigned CreateRegForValue(const Value *V);
271 unsigned InitializeRegForValue(const Value *V) {
272 unsigned &R = ValueMap[V];
273 assert(R == 0 && "Already initialized this value register!");
274 return R = CreateRegForValue(V);
279 /// isSelector - Return true if this instruction is a call to the
280 /// eh.selector intrinsic.
281 static bool isSelector(Instruction *I) {
282 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
283 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
284 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
288 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
289 /// PHI nodes or outside of the basic block that defines it, or used by a
290 /// switch or atomic instruction, which may expand to multiple basic blocks.
291 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
292 if (isa<PHINode>(I)) return true;
293 BasicBlock *BB = I->getParent();
294 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
295 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
296 // FIXME: Remove switchinst special case.
297 isa<SwitchInst>(*UI))
302 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
303 /// entry block, return true. This includes arguments used by switches, since
304 /// the switch may expand into multiple basic blocks.
305 static bool isOnlyUsedInEntryBlock(Argument *A) {
306 BasicBlock *Entry = A->getParent()->begin();
307 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
308 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
309 return false; // Use not in entry block.
313 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
314 Function &fn, MachineFunction &mf)
315 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
317 // Create a vreg for each argument register that is not dead and is used
318 // outside of the entry block for the function.
319 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
321 if (!isOnlyUsedInEntryBlock(AI))
322 InitializeRegForValue(AI);
324 // Initialize the mapping of values to registers. This is only set up for
325 // instruction values that are used outside of the block that defines
327 Function::iterator BB = Fn.begin(), EB = Fn.end();
328 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
329 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
330 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
331 const Type *Ty = AI->getAllocatedType();
332 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
334 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
337 TySize *= CUI->getZExtValue(); // Get total allocated size.
338 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
339 StaticAllocaMap[AI] =
340 MF.getFrameInfo()->CreateStackObject(TySize, Align);
343 for (; BB != EB; ++BB)
344 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
345 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
346 if (!isa<AllocaInst>(I) ||
347 !StaticAllocaMap.count(cast<AllocaInst>(I)))
348 InitializeRegForValue(I);
350 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
351 // also creates the initial PHI MachineInstrs, though none of the input
352 // operands are populated.
353 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
354 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
356 MF.getBasicBlockList().push_back(MBB);
358 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
361 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
362 if (PN->use_empty()) continue;
364 MVT::ValueType VT = TLI.getValueType(PN->getType());
365 unsigned NumRegisters = TLI.getNumRegisters(VT);
366 unsigned PHIReg = ValueMap[PN];
367 assert(PHIReg && "PHI node does not have an assigned virtual register!");
368 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
369 for (unsigned i = 0; i != NumRegisters; ++i)
370 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
375 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
376 /// the correctly promoted or expanded types. Assign these registers
377 /// consecutive vreg numbers and return the first assigned number.
379 /// In the case that the given value has struct or array type, this function
380 /// will assign registers for each member or element.
382 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
383 SmallVector<MVT::ValueType, 4> ValueVTs;
384 ComputeValueVTs(TLI, V->getType(), ValueVTs);
386 unsigned FirstReg = 0;
387 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
388 MVT::ValueType ValueVT = ValueVTs[Value];
389 MVT::ValueType RegisterVT = TLI.getRegisterType(ValueVT);
391 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
392 for (unsigned i = 0; i != NumRegs; ++i) {
393 unsigned R = MakeReg(RegisterVT);
394 if (!FirstReg) FirstReg = R;
400 //===----------------------------------------------------------------------===//
401 /// SelectionDAGLowering - This is the common target-independent lowering
402 /// implementation that is parameterized by a TargetLowering object.
403 /// Also, targets can overload any lowering method.
406 class SelectionDAGLowering {
407 MachineBasicBlock *CurMBB;
409 DenseMap<const Value*, SDOperand> NodeMap;
411 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
412 /// them up and then emit token factor nodes when possible. This allows us to
413 /// get simple disambiguation between loads without worrying about alias
415 std::vector<SDOperand> PendingLoads;
417 /// PendingExports - CopyToReg nodes that copy values to virtual registers
418 /// for export to other blocks need to be emitted before any terminator
419 /// instruction, but they have no other ordering requirements. We bunch them
420 /// up and the emit a single tokenfactor for them just before terminator
422 std::vector<SDOperand> PendingExports;
424 /// Case - A struct to record the Value for a switch case, and the
425 /// case's target basic block.
429 MachineBasicBlock* BB;
431 Case() : Low(0), High(0), BB(0) { }
432 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
433 Low(low), High(high), BB(bb) { }
434 uint64_t size() const {
435 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
436 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
437 return (rHigh - rLow + 1ULL);
443 MachineBasicBlock* BB;
446 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
447 Mask(mask), BB(bb), Bits(bits) { }
450 typedef std::vector<Case> CaseVector;
451 typedef std::vector<CaseBits> CaseBitsVector;
452 typedef CaseVector::iterator CaseItr;
453 typedef std::pair<CaseItr, CaseItr> CaseRange;
455 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
456 /// of conditional branches.
458 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
459 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
461 /// CaseBB - The MBB in which to emit the compare and branch
462 MachineBasicBlock *CaseBB;
463 /// LT, GE - If nonzero, we know the current case value must be less-than or
464 /// greater-than-or-equal-to these Constants.
467 /// Range - A pair of iterators representing the range of case values to be
468 /// processed at this point in the binary search tree.
472 typedef std::vector<CaseRec> CaseRecVector;
474 /// The comparison function for sorting the switch case values in the vector.
475 /// WARNING: Case ranges should be disjoint!
477 bool operator () (const Case& C1, const Case& C2) {
478 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
479 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
480 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
481 return CI1->getValue().slt(CI2->getValue());
486 bool operator () (const CaseBits& C1, const CaseBits& C2) {
487 return C1.Bits > C2.Bits;
491 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
494 // TLI - This is information that describes the available target features we
495 // need for lowering. This indicates when operations are unavailable,
496 // implemented with a libcall, etc.
499 const TargetData *TD;
502 /// SwitchCases - Vector of CaseBlock structures used to communicate
503 /// SwitchInst code generation information.
504 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
505 /// JTCases - Vector of JumpTable structures used to communicate
506 /// SwitchInst code generation information.
507 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
508 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
510 /// FuncInfo - Information about the function as a whole.
512 FunctionLoweringInfo &FuncInfo;
514 /// GCI - Garbage collection metadata for the function.
515 CollectorMetadata *GCI;
517 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
519 FunctionLoweringInfo &funcinfo,
520 CollectorMetadata *gci)
521 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
522 FuncInfo(funcinfo), GCI(gci) {
525 /// getRoot - Return the current virtual root of the Selection DAG,
526 /// flushing any PendingLoad items. This must be done before emitting
527 /// a store or any other node that may need to be ordered after any
528 /// prior load instructions.
530 SDOperand getRoot() {
531 if (PendingLoads.empty())
532 return DAG.getRoot();
534 if (PendingLoads.size() == 1) {
535 SDOperand Root = PendingLoads[0];
537 PendingLoads.clear();
541 // Otherwise, we have to make a token factor node.
542 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
543 &PendingLoads[0], PendingLoads.size());
544 PendingLoads.clear();
549 /// getControlRoot - Similar to getRoot, but instead of flushing all the
550 /// PendingLoad items, flush all the PendingExports items. It is necessary
551 /// to do this before emitting a terminator instruction.
553 SDOperand getControlRoot() {
554 SDOperand Root = DAG.getRoot();
556 if (PendingExports.empty())
559 // Turn all of the CopyToReg chains into one factored node.
560 if (Root.getOpcode() != ISD::EntryToken) {
561 unsigned i = 0, e = PendingExports.size();
562 for (; i != e; ++i) {
563 assert(PendingExports[i].Val->getNumOperands() > 1);
564 if (PendingExports[i].Val->getOperand(0) == Root)
565 break; // Don't add the root if we already indirectly depend on it.
569 PendingExports.push_back(Root);
572 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
574 PendingExports.size());
575 PendingExports.clear();
580 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
582 void visit(Instruction &I) { visit(I.getOpcode(), I); }
584 void visit(unsigned Opcode, User &I) {
585 // Note: this doesn't use InstVisitor, because it has to work with
586 // ConstantExpr's in addition to instructions.
588 default: assert(0 && "Unknown instruction type encountered!");
590 // Build the switch statement using the Instruction.def file.
591 #define HANDLE_INST(NUM, OPCODE, CLASS) \
592 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
593 #include "llvm/Instruction.def"
597 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
599 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
600 const Value *SV, SDOperand Root,
601 bool isVolatile, unsigned Alignment);
603 SDOperand getValue(const Value *V);
605 void setValue(const Value *V, SDOperand NewN) {
606 SDOperand &N = NodeMap[V];
607 assert(N.Val == 0 && "Already set a value for this node!");
611 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
612 std::set<unsigned> &OutputRegs,
613 std::set<unsigned> &InputRegs);
615 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
616 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
618 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
619 void ExportFromCurrentBlock(Value *V);
620 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
621 MachineBasicBlock *LandingPad = NULL);
623 // Terminator instructions.
624 void visitRet(ReturnInst &I);
625 void visitBr(BranchInst &I);
626 void visitSwitch(SwitchInst &I);
627 void visitUnreachable(UnreachableInst &I) { /* noop */ }
629 // Helpers for visitSwitch
630 bool handleSmallSwitchRange(CaseRec& CR,
631 CaseRecVector& WorkList,
633 MachineBasicBlock* Default);
634 bool handleJTSwitchCase(CaseRec& CR,
635 CaseRecVector& WorkList,
637 MachineBasicBlock* Default);
638 bool handleBTSplitSwitchCase(CaseRec& CR,
639 CaseRecVector& WorkList,
641 MachineBasicBlock* Default);
642 bool handleBitTestsSwitchCase(CaseRec& CR,
643 CaseRecVector& WorkList,
645 MachineBasicBlock* Default);
646 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
647 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
648 void visitBitTestCase(MachineBasicBlock* NextMBB,
650 SelectionDAGISel::BitTestCase &B);
651 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
652 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
653 SelectionDAGISel::JumpTableHeader &JTH);
655 // These all get lowered before this pass.
656 void visitInvoke(InvokeInst &I);
657 void visitUnwind(UnwindInst &I);
659 void visitBinary(User &I, unsigned OpCode);
660 void visitShift(User &I, unsigned Opcode);
661 void visitAdd(User &I) {
662 if (I.getType()->isFPOrFPVector())
663 visitBinary(I, ISD::FADD);
665 visitBinary(I, ISD::ADD);
667 void visitSub(User &I);
668 void visitMul(User &I) {
669 if (I.getType()->isFPOrFPVector())
670 visitBinary(I, ISD::FMUL);
672 visitBinary(I, ISD::MUL);
674 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
675 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
676 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
677 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
678 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
679 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
680 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
681 void visitOr (User &I) { visitBinary(I, ISD::OR); }
682 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
683 void visitShl (User &I) { visitShift(I, ISD::SHL); }
684 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
685 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
686 void visitICmp(User &I);
687 void visitFCmp(User &I);
688 // Visit the conversion instructions
689 void visitTrunc(User &I);
690 void visitZExt(User &I);
691 void visitSExt(User &I);
692 void visitFPTrunc(User &I);
693 void visitFPExt(User &I);
694 void visitFPToUI(User &I);
695 void visitFPToSI(User &I);
696 void visitUIToFP(User &I);
697 void visitSIToFP(User &I);
698 void visitPtrToInt(User &I);
699 void visitIntToPtr(User &I);
700 void visitBitCast(User &I);
702 void visitExtractElement(User &I);
703 void visitInsertElement(User &I);
704 void visitShuffleVector(User &I);
706 void visitGetElementPtr(User &I);
707 void visitSelect(User &I);
709 void visitMalloc(MallocInst &I);
710 void visitFree(FreeInst &I);
711 void visitAlloca(AllocaInst &I);
712 void visitLoad(LoadInst &I);
713 void visitStore(StoreInst &I);
714 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
715 void visitCall(CallInst &I);
716 void visitInlineAsm(CallSite CS);
717 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
718 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
720 void visitVAStart(CallInst &I);
721 void visitVAArg(VAArgInst &I);
722 void visitVAEnd(CallInst &I);
723 void visitVACopy(CallInst &I);
725 void visitGetResult(GetResultInst &I);
727 void visitUserOp1(Instruction &I) {
728 assert(0 && "UserOp1 should not exist at instruction selection time!");
731 void visitUserOp2(Instruction &I) {
732 assert(0 && "UserOp2 should not exist at instruction selection time!");
736 } // end namespace llvm
739 /// getCopyFromParts - Create a value that contains the specified legal parts
740 /// combined into the value they represent. If the parts combine to a type
741 /// larger then ValueVT then AssertOp can be used to specify whether the extra
742 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
743 /// (ISD::AssertSext).
744 static SDOperand getCopyFromParts(SelectionDAG &DAG,
745 const SDOperand *Parts,
747 MVT::ValueType PartVT,
748 MVT::ValueType ValueVT,
749 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
750 assert(NumParts > 0 && "No parts to assemble!");
751 TargetLowering &TLI = DAG.getTargetLoweringInfo();
752 SDOperand Val = Parts[0];
755 // Assemble the value from multiple parts.
756 if (!MVT::isVector(ValueVT)) {
757 unsigned PartBits = MVT::getSizeInBits(PartVT);
758 unsigned ValueBits = MVT::getSizeInBits(ValueVT);
760 // Assemble the power of 2 part.
761 unsigned RoundParts = NumParts & (NumParts - 1) ?
762 1 << Log2_32(NumParts) : NumParts;
763 unsigned RoundBits = PartBits * RoundParts;
764 MVT::ValueType RoundVT = RoundBits == ValueBits ?
765 ValueVT : MVT::getIntegerType(RoundBits);
768 if (RoundParts > 2) {
769 MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2);
770 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
771 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
777 if (TLI.isBigEndian())
779 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
781 if (RoundParts < NumParts) {
782 // Assemble the trailing non-power-of-2 part.
783 unsigned OddParts = NumParts - RoundParts;
784 MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits);
785 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
787 // Combine the round and odd parts.
789 if (TLI.isBigEndian())
791 MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits);
792 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
793 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
794 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
795 TLI.getShiftAmountTy()));
796 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
797 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
800 // Handle a multi-element vector.
801 MVT::ValueType IntermediateVT, RegisterVT;
802 unsigned NumIntermediates;
804 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
807 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
808 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
809 assert(RegisterVT == Parts[0].getValueType() &&
810 "Part type doesn't match part!");
812 // Assemble the parts into intermediate operands.
813 SmallVector<SDOperand, 8> Ops(NumIntermediates);
814 if (NumIntermediates == NumParts) {
815 // If the register was not expanded, truncate or copy the value,
817 for (unsigned i = 0; i != NumParts; ++i)
818 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
819 PartVT, IntermediateVT);
820 } else if (NumParts > 0) {
821 // If the intermediate type was expanded, build the intermediate operands
823 assert(NumParts % NumIntermediates == 0 &&
824 "Must expand into a divisible number of parts!");
825 unsigned Factor = NumParts / NumIntermediates;
826 for (unsigned i = 0; i != NumIntermediates; ++i)
827 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
828 PartVT, IntermediateVT);
831 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
833 Val = DAG.getNode(MVT::isVector(IntermediateVT) ?
834 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
835 ValueVT, &Ops[0], NumIntermediates);
839 // There is now one part, held in Val. Correct it to match ValueVT.
840 PartVT = Val.getValueType();
842 if (PartVT == ValueVT)
845 if (MVT::isVector(PartVT)) {
846 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
847 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
850 if (MVT::isVector(ValueVT)) {
851 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
852 MVT::getVectorNumElements(ValueVT) == 1 &&
853 "Only trivial scalar-to-vector conversions should get here!");
854 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
857 if (MVT::isInteger(PartVT) &&
858 MVT::isInteger(ValueVT)) {
859 if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) {
860 // For a truncate, see if we have any information to
861 // indicate whether the truncated bits will always be
862 // zero or sign-extension.
863 if (AssertOp != ISD::DELETED_NODE)
864 Val = DAG.getNode(AssertOp, PartVT, Val,
865 DAG.getValueType(ValueVT));
866 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
868 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
872 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
873 if (ValueVT < Val.getValueType())
874 // FP_ROUND's are always exact here.
875 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
876 DAG.getIntPtrConstant(1));
877 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
880 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
881 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
883 assert(0 && "Unknown mismatch!");
887 /// getCopyToParts - Create a series of nodes that contain the specified value
888 /// split into legal parts. If the parts contain more bits than Val, then, for
889 /// integers, ExtendKind can be used to specify how to generate the extra bits.
890 static void getCopyToParts(SelectionDAG &DAG,
894 MVT::ValueType PartVT,
895 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
896 TargetLowering &TLI = DAG.getTargetLoweringInfo();
897 MVT::ValueType PtrVT = TLI.getPointerTy();
898 MVT::ValueType ValueVT = Val.getValueType();
899 unsigned PartBits = MVT::getSizeInBits(PartVT);
900 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
905 if (!MVT::isVector(ValueVT)) {
906 if (PartVT == ValueVT) {
907 assert(NumParts == 1 && "No-op copy with multiple parts!");
912 if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) {
913 // If the parts cover more bits than the value has, promote the value.
914 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
915 assert(NumParts == 1 && "Do not know what to promote to!");
916 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
917 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
918 ValueVT = MVT::getIntegerType(NumParts * PartBits);
919 Val = DAG.getNode(ExtendKind, ValueVT, Val);
921 assert(0 && "Unknown mismatch!");
923 } else if (PartBits == MVT::getSizeInBits(ValueVT)) {
924 // Different types of the same size.
925 assert(NumParts == 1 && PartVT != ValueVT);
926 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
927 } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) {
928 // If the parts cover less bits than value has, truncate the value.
929 if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
930 ValueVT = MVT::getIntegerType(NumParts * PartBits);
931 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
933 assert(0 && "Unknown mismatch!");
937 // The value may have changed - recompute ValueVT.
938 ValueVT = Val.getValueType();
939 assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) &&
940 "Failed to tile the value with PartVT!");
943 assert(PartVT == ValueVT && "Type conversion failed!");
948 // Expand the value into multiple parts.
949 if (NumParts & (NumParts - 1)) {
950 // The number of parts is not a power of 2. Split off and copy the tail.
951 assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) &&
952 "Do not know what to expand to!");
953 unsigned RoundParts = 1 << Log2_32(NumParts);
954 unsigned RoundBits = RoundParts * PartBits;
955 unsigned OddParts = NumParts - RoundParts;
956 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
957 DAG.getConstant(RoundBits,
958 TLI.getShiftAmountTy()));
959 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
960 if (TLI.isBigEndian())
961 // The odd parts were reversed by getCopyToParts - unreverse them.
962 std::reverse(Parts + RoundParts, Parts + NumParts);
963 NumParts = RoundParts;
964 ValueVT = MVT::getIntegerType(NumParts * PartBits);
965 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
968 // The number of parts is a power of 2. Repeatedly bisect the value using
970 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
971 MVT::getIntegerType(MVT::getSizeInBits(ValueVT)),
973 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
974 for (unsigned i = 0; i < NumParts; i += StepSize) {
975 unsigned ThisBits = StepSize * PartBits / 2;
976 MVT::ValueType ThisVT = MVT::getIntegerType (ThisBits);
977 SDOperand &Part0 = Parts[i];
978 SDOperand &Part1 = Parts[i+StepSize/2];
980 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
981 DAG.getConstant(1, PtrVT));
982 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
983 DAG.getConstant(0, PtrVT));
985 if (ThisBits == PartBits && ThisVT != PartVT) {
986 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
987 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
992 if (TLI.isBigEndian())
993 std::reverse(Parts, Parts + NumParts);
1000 if (PartVT != ValueVT) {
1001 if (MVT::isVector(PartVT)) {
1002 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1004 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
1005 MVT::getVectorNumElements(ValueVT) == 1 &&
1006 "Only trivial vector-to-scalar conversions should get here!");
1007 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1008 DAG.getConstant(0, PtrVT));
1016 // Handle a multi-element vector.
1017 MVT::ValueType IntermediateVT, RegisterVT;
1018 unsigned NumIntermediates;
1020 DAG.getTargetLoweringInfo()
1021 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1023 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
1025 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1026 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1028 // Split the vector into intermediate operands.
1029 SmallVector<SDOperand, 8> Ops(NumIntermediates);
1030 for (unsigned i = 0; i != NumIntermediates; ++i)
1031 if (MVT::isVector(IntermediateVT))
1032 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1033 IntermediateVT, Val,
1034 DAG.getConstant(i * (NumElements / NumIntermediates),
1037 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1038 IntermediateVT, Val,
1039 DAG.getConstant(i, PtrVT));
1041 // Split the intermediate operands into legal parts.
1042 if (NumParts == NumIntermediates) {
1043 // If the register was not expanded, promote or copy the value,
1045 for (unsigned i = 0; i != NumParts; ++i)
1046 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1047 } else if (NumParts > 0) {
1048 // If the intermediate type was expanded, split each the value into
1050 assert(NumParts % NumIntermediates == 0 &&
1051 "Must expand into a divisible number of parts!");
1052 unsigned Factor = NumParts / NumIntermediates;
1053 for (unsigned i = 0; i != NumIntermediates; ++i)
1054 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1059 SDOperand SelectionDAGLowering::getValue(const Value *V) {
1060 SDOperand &N = NodeMap[V];
1061 if (N.Val) return N;
1063 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1064 MVT::ValueType VT = TLI.getValueType(V->getType(), true);
1066 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1067 return N = DAG.getConstant(CI->getValue(), VT);
1069 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1070 return N = DAG.getGlobalAddress(GV, VT);
1072 if (isa<ConstantPointerNull>(C))
1073 return N = DAG.getConstant(0, TLI.getPointerTy());
1075 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1076 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1078 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()))
1079 return N = DAG.getNode(ISD::UNDEF, VT);
1081 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1082 visit(CE->getOpcode(), *CE);
1083 SDOperand N1 = NodeMap[V];
1084 assert(N1.Val && "visit didn't populate the ValueMap!");
1088 const VectorType *VecTy = cast<VectorType>(V->getType());
1089 unsigned NumElements = VecTy->getNumElements();
1091 // Now that we know the number and type of the elements, get that number of
1092 // elements into the Ops array based on what kind of constant it is.
1093 SmallVector<SDOperand, 16> Ops;
1094 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1095 for (unsigned i = 0; i != NumElements; ++i)
1096 Ops.push_back(getValue(CP->getOperand(i)));
1098 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1099 "Unknown vector constant!");
1100 MVT::ValueType EltVT = TLI.getValueType(VecTy->getElementType());
1103 if (isa<UndefValue>(C))
1104 Op = DAG.getNode(ISD::UNDEF, EltVT);
1105 else if (MVT::isFloatingPoint(EltVT))
1106 Op = DAG.getConstantFP(0, EltVT);
1108 Op = DAG.getConstant(0, EltVT);
1109 Ops.assign(NumElements, Op);
1112 // Create a BUILD_VECTOR node.
1113 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1116 // If this is a static alloca, generate it as the frameindex instead of
1118 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1119 std::map<const AllocaInst*, int>::iterator SI =
1120 FuncInfo.StaticAllocaMap.find(AI);
1121 if (SI != FuncInfo.StaticAllocaMap.end())
1122 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1125 unsigned InReg = FuncInfo.ValueMap[V];
1126 assert(InReg && "Value not in map!");
1128 RegsForValue RFV(TLI, InReg, V->getType());
1129 SDOperand Chain = DAG.getEntryNode();
1130 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1134 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1135 if (I.getNumOperands() == 0) {
1136 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1140 SmallVector<SDOperand, 8> NewValues;
1141 NewValues.push_back(getControlRoot());
1142 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1143 SDOperand RetOp = getValue(I.getOperand(i));
1144 MVT::ValueType VT = RetOp.getValueType();
1146 // FIXME: C calling convention requires the return type to be promoted to
1147 // at least 32-bit. But this is not necessary for non-C calling conventions.
1148 if (MVT::isInteger(VT)) {
1149 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32);
1150 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT))
1154 unsigned NumParts = TLI.getNumRegisters(VT);
1155 MVT::ValueType PartVT = TLI.getRegisterType(VT);
1156 SmallVector<SDOperand, 4> Parts(NumParts);
1157 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1159 const Function *F = I.getParent()->getParent();
1160 if (F->paramHasAttr(0, ParamAttr::SExt))
1161 ExtendKind = ISD::SIGN_EXTEND;
1162 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1163 ExtendKind = ISD::ZERO_EXTEND;
1165 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
1167 for (unsigned i = 0; i < NumParts; ++i) {
1168 NewValues.push_back(Parts[i]);
1169 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1172 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1173 &NewValues[0], NewValues.size()));
1176 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1177 /// the current basic block, add it to ValueMap now so that we'll get a
1179 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1180 // No need to export constants.
1181 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1183 // Already exported?
1184 if (FuncInfo.isExportedInst(V)) return;
1186 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1187 CopyValueToVirtualRegister(V, Reg);
1190 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1191 const BasicBlock *FromBB) {
1192 // The operands of the setcc have to be in this block. We don't know
1193 // how to export them from some other block.
1194 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1195 // Can export from current BB.
1196 if (VI->getParent() == FromBB)
1199 // Is already exported, noop.
1200 return FuncInfo.isExportedInst(V);
1203 // If this is an argument, we can export it if the BB is the entry block or
1204 // if it is already exported.
1205 if (isa<Argument>(V)) {
1206 if (FromBB == &FromBB->getParent()->getEntryBlock())
1209 // Otherwise, can only export this if it is already exported.
1210 return FuncInfo.isExportedInst(V);
1213 // Otherwise, constants can always be exported.
1217 static bool InBlock(const Value *V, const BasicBlock *BB) {
1218 if (const Instruction *I = dyn_cast<Instruction>(V))
1219 return I->getParent() == BB;
1223 /// FindMergedConditions - If Cond is an expression like
1224 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1225 MachineBasicBlock *TBB,
1226 MachineBasicBlock *FBB,
1227 MachineBasicBlock *CurBB,
1229 // If this node is not part of the or/and tree, emit it as a branch.
1230 Instruction *BOp = dyn_cast<Instruction>(Cond);
1232 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1233 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1234 BOp->getParent() != CurBB->getBasicBlock() ||
1235 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1236 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1237 const BasicBlock *BB = CurBB->getBasicBlock();
1239 // If the leaf of the tree is a comparison, merge the condition into
1241 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1242 // The operands of the cmp have to be in this block. We don't know
1243 // how to export them from some other block. If this is the first block
1244 // of the sequence, no exporting is needed.
1246 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1247 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1248 BOp = cast<Instruction>(Cond);
1249 ISD::CondCode Condition;
1250 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1251 switch (IC->getPredicate()) {
1252 default: assert(0 && "Unknown icmp predicate opcode!");
1253 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1254 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1255 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1256 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1257 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1258 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1259 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1260 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1261 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1262 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1264 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1265 ISD::CondCode FPC, FOC;
1266 switch (FC->getPredicate()) {
1267 default: assert(0 && "Unknown fcmp predicate opcode!");
1268 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1269 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1270 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1271 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1272 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1273 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1274 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1275 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1276 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1277 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1278 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1279 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1280 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1281 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1282 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1283 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1285 if (FiniteOnlyFPMath())
1290 Condition = ISD::SETEQ; // silence warning.
1291 assert(0 && "Unknown compare instruction");
1294 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1295 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1296 SwitchCases.push_back(CB);
1300 // Create a CaseBlock record representing this branch.
1301 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1302 NULL, TBB, FBB, CurBB);
1303 SwitchCases.push_back(CB);
1308 // Create TmpBB after CurBB.
1309 MachineFunction::iterator BBI = CurBB;
1310 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1311 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1313 if (Opc == Instruction::Or) {
1314 // Codegen X | Y as:
1322 // Emit the LHS condition.
1323 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1325 // Emit the RHS condition into TmpBB.
1326 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1328 assert(Opc == Instruction::And && "Unknown merge op!");
1329 // Codegen X & Y as:
1336 // This requires creation of TmpBB after CurBB.
1338 // Emit the LHS condition.
1339 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1341 // Emit the RHS condition into TmpBB.
1342 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1346 /// If the set of cases should be emitted as a series of branches, return true.
1347 /// If we should emit this as a bunch of and/or'd together conditions, return
1350 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1351 if (Cases.size() != 2) return true;
1353 // If this is two comparisons of the same values or'd or and'd together, they
1354 // will get folded into a single comparison, so don't emit two blocks.
1355 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1356 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1357 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1358 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1365 void SelectionDAGLowering::visitBr(BranchInst &I) {
1366 // Update machine-CFG edges.
1367 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1369 // Figure out which block is immediately after the current one.
1370 MachineBasicBlock *NextBlock = 0;
1371 MachineFunction::iterator BBI = CurMBB;
1372 if (++BBI != CurMBB->getParent()->end())
1375 if (I.isUnconditional()) {
1376 // If this is not a fall-through branch, emit the branch.
1377 if (Succ0MBB != NextBlock)
1378 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1379 DAG.getBasicBlock(Succ0MBB)));
1381 // Update machine-CFG edges.
1382 CurMBB->addSuccessor(Succ0MBB);
1386 // If this condition is one of the special cases we handle, do special stuff
1388 Value *CondVal = I.getCondition();
1389 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1391 // If this is a series of conditions that are or'd or and'd together, emit
1392 // this as a sequence of branches instead of setcc's with and/or operations.
1393 // For example, instead of something like:
1406 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1407 if (BOp->hasOneUse() &&
1408 (BOp->getOpcode() == Instruction::And ||
1409 BOp->getOpcode() == Instruction::Or)) {
1410 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1411 // If the compares in later blocks need to use values not currently
1412 // exported from this block, export them now. This block should always
1413 // be the first entry.
1414 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1416 // Allow some cases to be rejected.
1417 if (ShouldEmitAsBranches(SwitchCases)) {
1418 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1419 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1420 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1423 // Emit the branch for this block.
1424 visitSwitchCase(SwitchCases[0]);
1425 SwitchCases.erase(SwitchCases.begin());
1429 // Okay, we decided not to do this, remove any inserted MBB's and clear
1431 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1432 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1434 SwitchCases.clear();
1438 // Create a CaseBlock record representing this branch.
1439 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1440 NULL, Succ0MBB, Succ1MBB, CurMBB);
1441 // Use visitSwitchCase to actually insert the fast branch sequence for this
1443 visitSwitchCase(CB);
1446 /// visitSwitchCase - Emits the necessary code to represent a single node in
1447 /// the binary search tree resulting from lowering a switch instruction.
1448 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1450 SDOperand CondLHS = getValue(CB.CmpLHS);
1452 // Build the setcc now.
1453 if (CB.CmpMHS == NULL) {
1454 // Fold "(X == true)" to X and "(X == false)" to !X to
1455 // handle common cases produced by branch lowering.
1456 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1458 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1459 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1460 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1462 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1464 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1466 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1467 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1469 SDOperand CmpOp = getValue(CB.CmpMHS);
1470 MVT::ValueType VT = CmpOp.getValueType();
1472 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1473 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1475 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1476 Cond = DAG.getSetCC(MVT::i1, SUB,
1477 DAG.getConstant(High-Low, VT), ISD::SETULE);
1482 // Set NextBlock to be the MBB immediately after the current one, if any.
1483 // This is used to avoid emitting unnecessary branches to the next block.
1484 MachineBasicBlock *NextBlock = 0;
1485 MachineFunction::iterator BBI = CurMBB;
1486 if (++BBI != CurMBB->getParent()->end())
1489 // If the lhs block is the next block, invert the condition so that we can
1490 // fall through to the lhs instead of the rhs block.
1491 if (CB.TrueBB == NextBlock) {
1492 std::swap(CB.TrueBB, CB.FalseBB);
1493 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1494 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1496 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1497 DAG.getBasicBlock(CB.TrueBB));
1498 if (CB.FalseBB == NextBlock)
1499 DAG.setRoot(BrCond);
1501 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1502 DAG.getBasicBlock(CB.FalseBB)));
1503 // Update successor info
1504 CurMBB->addSuccessor(CB.TrueBB);
1505 CurMBB->addSuccessor(CB.FalseBB);
1508 /// visitJumpTable - Emit JumpTable node in the current MBB
1509 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1510 // Emit the code for the jump table
1511 assert(JT.Reg != -1U && "Should lower JT Header first!");
1512 MVT::ValueType PTy = TLI.getPointerTy();
1513 SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1514 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1515 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1520 /// visitJumpTableHeader - This function emits necessary code to produce index
1521 /// in the JumpTable from switch case.
1522 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1523 SelectionDAGISel::JumpTableHeader &JTH) {
1524 // Subtract the lowest switch case value from the value being switched on
1525 // and conditional branch to default mbb if the result is greater than the
1526 // difference between smallest and largest cases.
1527 SDOperand SwitchOp = getValue(JTH.SValue);
1528 MVT::ValueType VT = SwitchOp.getValueType();
1529 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1530 DAG.getConstant(JTH.First, VT));
1532 // The SDNode we just created, which holds the value being switched on
1533 // minus the the smallest case value, needs to be copied to a virtual
1534 // register so it can be used as an index into the jump table in a
1535 // subsequent basic block. This value may be smaller or larger than the
1536 // target's pointer type, and therefore require extension or truncating.
1537 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1538 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1540 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1542 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1543 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1544 JT.Reg = JumpTableReg;
1546 // Emit the range check for the jump table, and branch to the default
1547 // block for the switch statement if the value being switched on exceeds
1548 // the largest case in the switch.
1549 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1550 DAG.getConstant(JTH.Last-JTH.First,VT),
1553 // Set NextBlock to be the MBB immediately after the current one, if any.
1554 // This is used to avoid emitting unnecessary branches to the next block.
1555 MachineBasicBlock *NextBlock = 0;
1556 MachineFunction::iterator BBI = CurMBB;
1557 if (++BBI != CurMBB->getParent()->end())
1560 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1561 DAG.getBasicBlock(JT.Default));
1563 if (JT.MBB == NextBlock)
1564 DAG.setRoot(BrCond);
1566 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1567 DAG.getBasicBlock(JT.MBB)));
1572 /// visitBitTestHeader - This function emits necessary code to produce value
1573 /// suitable for "bit tests"
1574 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1575 // Subtract the minimum value
1576 SDOperand SwitchOp = getValue(B.SValue);
1577 MVT::ValueType VT = SwitchOp.getValueType();
1578 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1579 DAG.getConstant(B.First, VT));
1582 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1583 DAG.getConstant(B.Range, VT),
1587 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1588 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1590 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1592 // Make desired shift
1593 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1594 DAG.getConstant(1, TLI.getPointerTy()),
1597 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1598 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1601 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1602 DAG.getBasicBlock(B.Default));
1604 // Set NextBlock to be the MBB immediately after the current one, if any.
1605 // This is used to avoid emitting unnecessary branches to the next block.
1606 MachineBasicBlock *NextBlock = 0;
1607 MachineFunction::iterator BBI = CurMBB;
1608 if (++BBI != CurMBB->getParent()->end())
1611 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1612 if (MBB == NextBlock)
1613 DAG.setRoot(BrRange);
1615 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1616 DAG.getBasicBlock(MBB)));
1618 CurMBB->addSuccessor(B.Default);
1619 CurMBB->addSuccessor(MBB);
1624 /// visitBitTestCase - this function produces one "bit test"
1625 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1627 SelectionDAGISel::BitTestCase &B) {
1628 // Emit bit tests and jumps
1629 SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, TLI.getPointerTy());
1631 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1633 DAG.getConstant(B.Mask,
1634 TLI.getPointerTy()));
1635 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1636 DAG.getConstant(0, TLI.getPointerTy()),
1638 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1639 AndCmp, DAG.getBasicBlock(B.TargetBB));
1641 // Set NextBlock to be the MBB immediately after the current one, if any.
1642 // This is used to avoid emitting unnecessary branches to the next block.
1643 MachineBasicBlock *NextBlock = 0;
1644 MachineFunction::iterator BBI = CurMBB;
1645 if (++BBI != CurMBB->getParent()->end())
1648 if (NextMBB == NextBlock)
1651 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1652 DAG.getBasicBlock(NextMBB)));
1654 CurMBB->addSuccessor(B.TargetBB);
1655 CurMBB->addSuccessor(NextMBB);
1660 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1661 // Retrieve successors.
1662 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1663 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1665 if (isa<InlineAsm>(I.getCalledValue()))
1668 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1670 // If the value of the invoke is used outside of its defining block, make it
1671 // available as a virtual register.
1672 if (!I.use_empty()) {
1673 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1674 if (VMI != FuncInfo.ValueMap.end())
1675 CopyValueToVirtualRegister(&I, VMI->second);
1678 // Drop into normal successor.
1679 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1680 DAG.getBasicBlock(Return)));
1682 // Update successor info
1683 CurMBB->addSuccessor(Return);
1684 CurMBB->addSuccessor(LandingPad);
1687 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1690 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1691 /// small case ranges).
1692 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1693 CaseRecVector& WorkList,
1695 MachineBasicBlock* Default) {
1696 Case& BackCase = *(CR.Range.second-1);
1698 // Size is the number of Cases represented by this range.
1699 unsigned Size = CR.Range.second - CR.Range.first;
1703 // Get the MachineFunction which holds the current MBB. This is used when
1704 // inserting any additional MBBs necessary to represent the switch.
1705 MachineFunction *CurMF = CurMBB->getParent();
1707 // Figure out which block is immediately after the current one.
1708 MachineBasicBlock *NextBlock = 0;
1709 MachineFunction::iterator BBI = CR.CaseBB;
1711 if (++BBI != CurMBB->getParent()->end())
1714 // TODO: If any two of the cases has the same destination, and if one value
1715 // is the same as the other, but has one bit unset that the other has set,
1716 // use bit manipulation to do two compares at once. For example:
1717 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1719 // Rearrange the case blocks so that the last one falls through if possible.
1720 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1721 // The last case block won't fall through into 'NextBlock' if we emit the
1722 // branches in this order. See if rearranging a case value would help.
1723 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1724 if (I->BB == NextBlock) {
1725 std::swap(*I, BackCase);
1731 // Create a CaseBlock record representing a conditional branch to
1732 // the Case's target mbb if the value being switched on SV is equal
1734 MachineBasicBlock *CurBlock = CR.CaseBB;
1735 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1736 MachineBasicBlock *FallThrough;
1738 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1739 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1741 // If the last case doesn't match, go to the default block.
1742 FallThrough = Default;
1745 Value *RHS, *LHS, *MHS;
1747 if (I->High == I->Low) {
1748 // This is just small small case range :) containing exactly 1 case
1750 LHS = SV; RHS = I->High; MHS = NULL;
1753 LHS = I->Low; MHS = SV; RHS = I->High;
1755 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1756 I->BB, FallThrough, CurBlock);
1758 // If emitting the first comparison, just call visitSwitchCase to emit the
1759 // code into the current block. Otherwise, push the CaseBlock onto the
1760 // vector to be later processed by SDISel, and insert the node's MBB
1761 // before the next MBB.
1762 if (CurBlock == CurMBB)
1763 visitSwitchCase(CB);
1765 SwitchCases.push_back(CB);
1767 CurBlock = FallThrough;
1773 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1774 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1775 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1778 /// handleJTSwitchCase - Emit jumptable for current switch case range
1779 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1780 CaseRecVector& WorkList,
1782 MachineBasicBlock* Default) {
1783 Case& FrontCase = *CR.Range.first;
1784 Case& BackCase = *(CR.Range.second-1);
1786 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1787 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1790 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1794 if (!areJTsAllowed(TLI) || TSize <= 3)
1797 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1801 DOUT << "Lowering jump table\n"
1802 << "First entry: " << First << ". Last entry: " << Last << "\n"
1803 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1805 // Get the MachineFunction which holds the current MBB. This is used when
1806 // inserting any additional MBBs necessary to represent the switch.
1807 MachineFunction *CurMF = CurMBB->getParent();
1809 // Figure out which block is immediately after the current one.
1810 MachineBasicBlock *NextBlock = 0;
1811 MachineFunction::iterator BBI = CR.CaseBB;
1813 if (++BBI != CurMBB->getParent()->end())
1816 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1818 // Create a new basic block to hold the code for loading the address
1819 // of the jump table, and jumping to it. Update successor information;
1820 // we will either branch to the default case for the switch, or the jump
1822 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1823 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1824 CR.CaseBB->addSuccessor(Default);
1825 CR.CaseBB->addSuccessor(JumpTableBB);
1827 // Build a vector of destination BBs, corresponding to each target
1828 // of the jump table. If the value of the jump table slot corresponds to
1829 // a case statement, push the case's BB onto the vector, otherwise, push
1831 std::vector<MachineBasicBlock*> DestBBs;
1832 int64_t TEI = First;
1833 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1834 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1835 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1837 if ((Low <= TEI) && (TEI <= High)) {
1838 DestBBs.push_back(I->BB);
1842 DestBBs.push_back(Default);
1846 // Update successor info. Add one edge to each unique successor.
1847 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1848 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1849 E = DestBBs.end(); I != E; ++I) {
1850 if (!SuccsHandled[(*I)->getNumber()]) {
1851 SuccsHandled[(*I)->getNumber()] = true;
1852 JumpTableBB->addSuccessor(*I);
1856 // Create a jump table index for this jump table, or return an existing
1858 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1860 // Set the jump table information so that we can codegen it as a second
1861 // MachineBasicBlock
1862 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1863 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1864 (CR.CaseBB == CurMBB));
1865 if (CR.CaseBB == CurMBB)
1866 visitJumpTableHeader(JT, JTH);
1868 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1873 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1875 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1876 CaseRecVector& WorkList,
1878 MachineBasicBlock* Default) {
1879 // Get the MachineFunction which holds the current MBB. This is used when
1880 // inserting any additional MBBs necessary to represent the switch.
1881 MachineFunction *CurMF = CurMBB->getParent();
1883 // Figure out which block is immediately after the current one.
1884 MachineBasicBlock *NextBlock = 0;
1885 MachineFunction::iterator BBI = CR.CaseBB;
1887 if (++BBI != CurMBB->getParent()->end())
1890 Case& FrontCase = *CR.Range.first;
1891 Case& BackCase = *(CR.Range.second-1);
1892 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1894 // Size is the number of Cases represented by this range.
1895 unsigned Size = CR.Range.second - CR.Range.first;
1897 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1898 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1900 CaseItr Pivot = CR.Range.first + Size/2;
1902 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1903 // (heuristically) allow us to emit JumpTable's later.
1905 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1909 uint64_t LSize = FrontCase.size();
1910 uint64_t RSize = TSize-LSize;
1911 DOUT << "Selecting best pivot: \n"
1912 << "First: " << First << ", Last: " << Last <<"\n"
1913 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1914 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1916 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1917 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1918 assert((RBegin-LEnd>=1) && "Invalid case distance");
1919 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1920 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1921 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1922 // Should always split in some non-trivial place
1924 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1925 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1926 << "Metric: " << Metric << "\n";
1927 if (FMetric < Metric) {
1930 DOUT << "Current metric set to: " << FMetric << "\n";
1936 if (areJTsAllowed(TLI)) {
1937 // If our case is dense we *really* should handle it earlier!
1938 assert((FMetric > 0) && "Should handle dense range earlier!");
1940 Pivot = CR.Range.first + Size/2;
1943 CaseRange LHSR(CR.Range.first, Pivot);
1944 CaseRange RHSR(Pivot, CR.Range.second);
1945 Constant *C = Pivot->Low;
1946 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1948 // We know that we branch to the LHS if the Value being switched on is
1949 // less than the Pivot value, C. We use this to optimize our binary
1950 // tree a bit, by recognizing that if SV is greater than or equal to the
1951 // LHS's Case Value, and that Case Value is exactly one less than the
1952 // Pivot's Value, then we can branch directly to the LHS's Target,
1953 // rather than creating a leaf node for it.
1954 if ((LHSR.second - LHSR.first) == 1 &&
1955 LHSR.first->High == CR.GE &&
1956 cast<ConstantInt>(C)->getSExtValue() ==
1957 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1958 TrueBB = LHSR.first->BB;
1960 TrueBB = new MachineBasicBlock(LLVMBB);
1961 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1962 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1965 // Similar to the optimization above, if the Value being switched on is
1966 // known to be less than the Constant CR.LT, and the current Case Value
1967 // is CR.LT - 1, then we can branch directly to the target block for
1968 // the current Case Value, rather than emitting a RHS leaf node for it.
1969 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1970 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1971 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1972 FalseBB = RHSR.first->BB;
1974 FalseBB = new MachineBasicBlock(LLVMBB);
1975 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1976 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1979 // Create a CaseBlock record representing a conditional branch to
1980 // the LHS node if the value being switched on SV is less than C.
1981 // Otherwise, branch to LHS.
1982 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1983 TrueBB, FalseBB, CR.CaseBB);
1985 if (CR.CaseBB == CurMBB)
1986 visitSwitchCase(CB);
1988 SwitchCases.push_back(CB);
1993 /// handleBitTestsSwitchCase - if current case range has few destination and
1994 /// range span less, than machine word bitwidth, encode case range into series
1995 /// of masks and emit bit tests with these masks.
1996 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1997 CaseRecVector& WorkList,
1999 MachineBasicBlock* Default){
2000 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
2002 Case& FrontCase = *CR.Range.first;
2003 Case& BackCase = *(CR.Range.second-1);
2005 // Get the MachineFunction which holds the current MBB. This is used when
2006 // inserting any additional MBBs necessary to represent the switch.
2007 MachineFunction *CurMF = CurMBB->getParent();
2009 unsigned numCmps = 0;
2010 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2012 // Single case counts one, case range - two.
2013 if (I->Low == I->High)
2019 // Count unique destinations
2020 SmallSet<MachineBasicBlock*, 4> Dests;
2021 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2022 Dests.insert(I->BB);
2023 if (Dests.size() > 3)
2024 // Don't bother the code below, if there are too much unique destinations
2027 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2028 << "Total number of comparisons: " << numCmps << "\n";
2030 // Compute span of values.
2031 Constant* minValue = FrontCase.Low;
2032 Constant* maxValue = BackCase.High;
2033 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2034 cast<ConstantInt>(minValue)->getSExtValue();
2035 DOUT << "Compare range: " << range << "\n"
2036 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2037 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2039 if (range>=IntPtrBits ||
2040 (!(Dests.size() == 1 && numCmps >= 3) &&
2041 !(Dests.size() == 2 && numCmps >= 5) &&
2042 !(Dests.size() >= 3 && numCmps >= 6)))
2045 DOUT << "Emitting bit tests\n";
2046 int64_t lowBound = 0;
2048 // Optimize the case where all the case values fit in a
2049 // word without having to subtract minValue. In this case,
2050 // we can optimize away the subtraction.
2051 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2052 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2053 range = cast<ConstantInt>(maxValue)->getSExtValue();
2055 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2058 CaseBitsVector CasesBits;
2059 unsigned i, count = 0;
2061 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2062 MachineBasicBlock* Dest = I->BB;
2063 for (i = 0; i < count; ++i)
2064 if (Dest == CasesBits[i].BB)
2068 assert((count < 3) && "Too much destinations to test!");
2069 CasesBits.push_back(CaseBits(0, Dest, 0));
2073 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2074 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2076 for (uint64_t j = lo; j <= hi; j++) {
2077 CasesBits[i].Mask |= 1ULL << j;
2078 CasesBits[i].Bits++;
2082 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2084 SelectionDAGISel::BitTestInfo BTC;
2086 // Figure out which block is immediately after the current one.
2087 MachineFunction::iterator BBI = CR.CaseBB;
2090 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2093 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2094 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2095 << ", BB: " << CasesBits[i].BB << "\n";
2097 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
2098 CurMF->getBasicBlockList().insert(BBI, CaseBB);
2099 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2104 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2105 -1U, (CR.CaseBB == CurMBB),
2106 CR.CaseBB, Default, BTC);
2108 if (CR.CaseBB == CurMBB)
2109 visitBitTestHeader(BTB);
2111 BitTestCases.push_back(BTB);
2117 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2118 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2119 const SwitchInst& SI) {
2120 unsigned numCmps = 0;
2122 // Start with "simple" cases
2123 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2124 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2125 Cases.push_back(Case(SI.getSuccessorValue(i),
2126 SI.getSuccessorValue(i),
2129 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2131 // Merge case into clusters
2132 if (Cases.size()>=2)
2133 // Must recompute end() each iteration because it may be
2134 // invalidated by erase if we hold on to it
2135 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2136 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2137 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2138 MachineBasicBlock* nextBB = J->BB;
2139 MachineBasicBlock* currentBB = I->BB;
2141 // If the two neighboring cases go to the same destination, merge them
2142 // into a single case.
2143 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2151 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2152 if (I->Low != I->High)
2153 // A range counts double, since it requires two compares.
2160 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2161 // Figure out which block is immediately after the current one.
2162 MachineBasicBlock *NextBlock = 0;
2163 MachineFunction::iterator BBI = CurMBB;
2165 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2167 // If there is only the default destination, branch to it if it is not the
2168 // next basic block. Otherwise, just fall through.
2169 if (SI.getNumOperands() == 2) {
2170 // Update machine-CFG edges.
2172 // If this is not a fall-through branch, emit the branch.
2173 if (Default != NextBlock)
2174 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2175 DAG.getBasicBlock(Default)));
2177 CurMBB->addSuccessor(Default);
2181 // If there are any non-default case statements, create a vector of Cases
2182 // representing each one, and sort the vector so that we can efficiently
2183 // create a binary search tree from them.
2185 unsigned numCmps = Clusterify(Cases, SI);
2186 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2187 << ". Total compares: " << numCmps << "\n";
2189 // Get the Value to be switched on and default basic blocks, which will be
2190 // inserted into CaseBlock records, representing basic blocks in the binary
2192 Value *SV = SI.getOperand(0);
2194 // Push the initial CaseRec onto the worklist
2195 CaseRecVector WorkList;
2196 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2198 while (!WorkList.empty()) {
2199 // Grab a record representing a case range to process off the worklist
2200 CaseRec CR = WorkList.back();
2201 WorkList.pop_back();
2203 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2206 // If the range has few cases (two or less) emit a series of specific
2208 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2211 // If the switch has more than 5 blocks, and at least 40% dense, and the
2212 // target supports indirect branches, then emit a jump table rather than
2213 // lowering the switch to a binary tree of conditional branches.
2214 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2217 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2218 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2219 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2224 void SelectionDAGLowering::visitSub(User &I) {
2225 // -0.0 - X --> fneg
2226 const Type *Ty = I.getType();
2227 if (isa<VectorType>(Ty)) {
2228 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2229 const VectorType *DestTy = cast<VectorType>(I.getType());
2230 const Type *ElTy = DestTy->getElementType();
2231 if (ElTy->isFloatingPoint()) {
2232 unsigned VL = DestTy->getNumElements();
2233 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2234 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2236 SDOperand Op2 = getValue(I.getOperand(1));
2237 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2243 if (Ty->isFloatingPoint()) {
2244 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2245 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2246 SDOperand Op2 = getValue(I.getOperand(1));
2247 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2252 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2255 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2256 SDOperand Op1 = getValue(I.getOperand(0));
2257 SDOperand Op2 = getValue(I.getOperand(1));
2259 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2262 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2263 SDOperand Op1 = getValue(I.getOperand(0));
2264 SDOperand Op2 = getValue(I.getOperand(1));
2266 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2267 MVT::getSizeInBits(Op2.getValueType()))
2268 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2269 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2270 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2272 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2275 void SelectionDAGLowering::visitICmp(User &I) {
2276 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2277 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2278 predicate = IC->getPredicate();
2279 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2280 predicate = ICmpInst::Predicate(IC->getPredicate());
2281 SDOperand Op1 = getValue(I.getOperand(0));
2282 SDOperand Op2 = getValue(I.getOperand(1));
2283 ISD::CondCode Opcode;
2284 switch (predicate) {
2285 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2286 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2287 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2288 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2289 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2290 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2291 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2292 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2293 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2294 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2296 assert(!"Invalid ICmp predicate value");
2297 Opcode = ISD::SETEQ;
2300 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2303 void SelectionDAGLowering::visitFCmp(User &I) {
2304 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2305 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2306 predicate = FC->getPredicate();
2307 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2308 predicate = FCmpInst::Predicate(FC->getPredicate());
2309 SDOperand Op1 = getValue(I.getOperand(0));
2310 SDOperand Op2 = getValue(I.getOperand(1));
2311 ISD::CondCode Condition, FOC, FPC;
2312 switch (predicate) {
2313 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2314 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2315 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2316 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2317 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2318 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2319 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2320 case FCmpInst::FCMP_ORD: FOC = ISD::SETO; break;
2321 case FCmpInst::FCMP_UNO: FOC = ISD::SETUO; break;
2322 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2323 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2324 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2325 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2326 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2327 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2328 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2330 assert(!"Invalid FCmp predicate value");
2331 FOC = FPC = ISD::SETFALSE;
2334 if (FiniteOnlyFPMath())
2338 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2341 void SelectionDAGLowering::visitSelect(User &I) {
2342 SDOperand Cond = getValue(I.getOperand(0));
2343 SDOperand TrueVal = getValue(I.getOperand(1));
2344 SDOperand FalseVal = getValue(I.getOperand(2));
2345 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2346 TrueVal, FalseVal));
2350 void SelectionDAGLowering::visitTrunc(User &I) {
2351 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2352 SDOperand N = getValue(I.getOperand(0));
2353 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2354 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2357 void SelectionDAGLowering::visitZExt(User &I) {
2358 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2359 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2360 SDOperand N = getValue(I.getOperand(0));
2361 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2362 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2365 void SelectionDAGLowering::visitSExt(User &I) {
2366 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2367 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2368 SDOperand N = getValue(I.getOperand(0));
2369 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2370 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2373 void SelectionDAGLowering::visitFPTrunc(User &I) {
2374 // FPTrunc is never a no-op cast, no need to check
2375 SDOperand N = getValue(I.getOperand(0));
2376 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2377 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2380 void SelectionDAGLowering::visitFPExt(User &I){
2381 // FPTrunc is never a no-op cast, no need to check
2382 SDOperand N = getValue(I.getOperand(0));
2383 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2384 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2387 void SelectionDAGLowering::visitFPToUI(User &I) {
2388 // FPToUI is never a no-op cast, no need to check
2389 SDOperand N = getValue(I.getOperand(0));
2390 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2391 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2394 void SelectionDAGLowering::visitFPToSI(User &I) {
2395 // FPToSI is never a no-op cast, no need to check
2396 SDOperand N = getValue(I.getOperand(0));
2397 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2398 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2401 void SelectionDAGLowering::visitUIToFP(User &I) {
2402 // UIToFP is never a no-op cast, no need to check
2403 SDOperand N = getValue(I.getOperand(0));
2404 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2405 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2408 void SelectionDAGLowering::visitSIToFP(User &I){
2409 // UIToFP is never a no-op cast, no need to check
2410 SDOperand N = getValue(I.getOperand(0));
2411 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2412 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2415 void SelectionDAGLowering::visitPtrToInt(User &I) {
2416 // What to do depends on the size of the integer and the size of the pointer.
2417 // We can either truncate, zero extend, or no-op, accordingly.
2418 SDOperand N = getValue(I.getOperand(0));
2419 MVT::ValueType SrcVT = N.getValueType();
2420 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2422 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2423 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2425 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2426 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2427 setValue(&I, Result);
2430 void SelectionDAGLowering::visitIntToPtr(User &I) {
2431 // What to do depends on the size of the integer and the size of the pointer.
2432 // We can either truncate, zero extend, or no-op, accordingly.
2433 SDOperand N = getValue(I.getOperand(0));
2434 MVT::ValueType SrcVT = N.getValueType();
2435 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2436 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2437 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2439 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2440 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2443 void SelectionDAGLowering::visitBitCast(User &I) {
2444 SDOperand N = getValue(I.getOperand(0));
2445 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2447 // BitCast assures us that source and destination are the same size so this
2448 // is either a BIT_CONVERT or a no-op.
2449 if (DestVT != N.getValueType())
2450 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2452 setValue(&I, N); // noop cast.
2455 void SelectionDAGLowering::visitInsertElement(User &I) {
2456 SDOperand InVec = getValue(I.getOperand(0));
2457 SDOperand InVal = getValue(I.getOperand(1));
2458 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2459 getValue(I.getOperand(2)));
2461 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2462 TLI.getValueType(I.getType()),
2463 InVec, InVal, InIdx));
2466 void SelectionDAGLowering::visitExtractElement(User &I) {
2467 SDOperand InVec = getValue(I.getOperand(0));
2468 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2469 getValue(I.getOperand(1)));
2470 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2471 TLI.getValueType(I.getType()), InVec, InIdx));
2474 void SelectionDAGLowering::visitShuffleVector(User &I) {
2475 SDOperand V1 = getValue(I.getOperand(0));
2476 SDOperand V2 = getValue(I.getOperand(1));
2477 SDOperand Mask = getValue(I.getOperand(2));
2479 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2480 TLI.getValueType(I.getType()),
2485 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2486 SDOperand N = getValue(I.getOperand(0));
2487 const Type *Ty = I.getOperand(0)->getType();
2489 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2492 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2493 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2496 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2497 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2498 DAG.getIntPtrConstant(Offset));
2500 Ty = StTy->getElementType(Field);
2502 Ty = cast<SequentialType>(Ty)->getElementType();
2504 // If this is a constant subscript, handle it quickly.
2505 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2506 if (CI->getZExtValue() == 0) continue;
2508 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2509 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2510 DAG.getIntPtrConstant(Offs));
2514 // N = N + Idx * ElementSize;
2515 uint64_t ElementSize = TD->getABITypeSize(Ty);
2516 SDOperand IdxN = getValue(Idx);
2518 // If the index is smaller or larger than intptr_t, truncate or extend
2520 if (IdxN.getValueType() < N.getValueType()) {
2521 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2522 } else if (IdxN.getValueType() > N.getValueType())
2523 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2525 // If this is a multiply by a power of two, turn it into a shl
2526 // immediately. This is a very common case.
2527 if (isPowerOf2_64(ElementSize)) {
2528 unsigned Amt = Log2_64(ElementSize);
2529 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2530 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2531 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2535 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2536 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2537 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2543 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2544 // If this is a fixed sized alloca in the entry block of the function,
2545 // allocate it statically on the stack.
2546 if (FuncInfo.StaticAllocaMap.count(&I))
2547 return; // getValue will auto-populate this.
2549 const Type *Ty = I.getAllocatedType();
2550 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2552 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2555 SDOperand AllocSize = getValue(I.getArraySize());
2556 MVT::ValueType IntPtr = TLI.getPointerTy();
2557 if (IntPtr < AllocSize.getValueType())
2558 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2559 else if (IntPtr > AllocSize.getValueType())
2560 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2562 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2563 DAG.getIntPtrConstant(TySize));
2565 // Handle alignment. If the requested alignment is less than or equal to
2566 // the stack alignment, ignore it. If the size is greater than or equal to
2567 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2568 unsigned StackAlign =
2569 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2570 if (Align <= StackAlign)
2573 // Round the size of the allocation up to the stack alignment size
2574 // by add SA-1 to the size.
2575 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2576 DAG.getIntPtrConstant(StackAlign-1));
2577 // Mask out the low bits for alignment purposes.
2578 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2579 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2581 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2582 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2584 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2586 DAG.setRoot(DSA.getValue(1));
2588 // Inform the Frame Information that we have just allocated a variable-sized
2590 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2593 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2594 SDOperand Ptr = getValue(I.getOperand(0));
2600 // Do not serialize non-volatile loads against each other.
2601 Root = DAG.getRoot();
2604 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2605 Root, I.isVolatile(), I.getAlignment()));
2608 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2609 const Value *SV, SDOperand Root,
2611 unsigned Alignment) {
2613 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2614 isVolatile, Alignment);
2617 DAG.setRoot(L.getValue(1));
2619 PendingLoads.push_back(L.getValue(1));
2625 void SelectionDAGLowering::visitStore(StoreInst &I) {
2626 Value *SrcV = I.getOperand(0);
2627 SDOperand Src = getValue(SrcV);
2628 SDOperand Ptr = getValue(I.getOperand(1));
2629 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2630 I.isVolatile(), I.getAlignment()));
2633 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2635 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2636 unsigned Intrinsic) {
2637 bool HasChain = !I.doesNotAccessMemory();
2638 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2640 // Build the operand list.
2641 SmallVector<SDOperand, 8> Ops;
2642 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2644 // We don't need to serialize loads against other loads.
2645 Ops.push_back(DAG.getRoot());
2647 Ops.push_back(getRoot());
2651 // Add the intrinsic ID as an integer operand.
2652 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2654 // Add all operands of the call to the operand list.
2655 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2656 SDOperand Op = getValue(I.getOperand(i));
2657 assert(TLI.isTypeLegal(Op.getValueType()) &&
2658 "Intrinsic uses a non-legal type?");
2662 std::vector<MVT::ValueType> VTs;
2663 if (I.getType() != Type::VoidTy) {
2664 MVT::ValueType VT = TLI.getValueType(I.getType());
2665 if (MVT::isVector(VT)) {
2666 const VectorType *DestTy = cast<VectorType>(I.getType());
2667 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2669 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2670 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2673 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2677 VTs.push_back(MVT::Other);
2679 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2684 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2685 &Ops[0], Ops.size());
2686 else if (I.getType() != Type::VoidTy)
2687 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2688 &Ops[0], Ops.size());
2690 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2691 &Ops[0], Ops.size());
2694 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2696 PendingLoads.push_back(Chain);
2700 if (I.getType() != Type::VoidTy) {
2701 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2702 MVT::ValueType VT = TLI.getValueType(PTy);
2703 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2705 setValue(&I, Result);
2709 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2710 static GlobalVariable *ExtractTypeInfo (Value *V) {
2711 V = IntrinsicInst::StripPointerCasts(V);
2712 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2713 assert ((GV || isa<ConstantPointerNull>(V)) &&
2714 "TypeInfo must be a global variable or NULL");
2718 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2719 /// call, and add them to the specified machine basic block.
2720 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2721 MachineBasicBlock *MBB) {
2722 // Inform the MachineModuleInfo of the personality for this landing pad.
2723 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2724 assert(CE->getOpcode() == Instruction::BitCast &&
2725 isa<Function>(CE->getOperand(0)) &&
2726 "Personality should be a function");
2727 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2729 // Gather all the type infos for this landing pad and pass them along to
2730 // MachineModuleInfo.
2731 std::vector<GlobalVariable *> TyInfo;
2732 unsigned N = I.getNumOperands();
2734 for (unsigned i = N - 1; i > 2; --i) {
2735 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2736 unsigned FilterLength = CI->getZExtValue();
2737 unsigned FirstCatch = i + FilterLength + !FilterLength;
2738 assert (FirstCatch <= N && "Invalid filter length");
2740 if (FirstCatch < N) {
2741 TyInfo.reserve(N - FirstCatch);
2742 for (unsigned j = FirstCatch; j < N; ++j)
2743 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2744 MMI->addCatchTypeInfo(MBB, TyInfo);
2748 if (!FilterLength) {
2750 MMI->addCleanup(MBB);
2753 TyInfo.reserve(FilterLength - 1);
2754 for (unsigned j = i + 1; j < FirstCatch; ++j)
2755 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2756 MMI->addFilterTypeInfo(MBB, TyInfo);
2765 TyInfo.reserve(N - 3);
2766 for (unsigned j = 3; j < N; ++j)
2767 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2768 MMI->addCatchTypeInfo(MBB, TyInfo);
2772 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2773 /// we want to emit this as a call to a named external function, return the name
2774 /// otherwise lower it and return null.
2776 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2777 switch (Intrinsic) {
2779 // By default, turn this into a target intrinsic node.
2780 visitTargetIntrinsic(I, Intrinsic);
2782 case Intrinsic::vastart: visitVAStart(I); return 0;
2783 case Intrinsic::vaend: visitVAEnd(I); return 0;
2784 case Intrinsic::vacopy: visitVACopy(I); return 0;
2785 case Intrinsic::returnaddress:
2786 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2787 getValue(I.getOperand(1))));
2789 case Intrinsic::frameaddress:
2790 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2791 getValue(I.getOperand(1))));
2793 case Intrinsic::setjmp:
2794 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2796 case Intrinsic::longjmp:
2797 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2799 case Intrinsic::memcpy_i32:
2800 case Intrinsic::memcpy_i64: {
2801 SDOperand Op1 = getValue(I.getOperand(1));
2802 SDOperand Op2 = getValue(I.getOperand(2));
2803 SDOperand Op3 = getValue(I.getOperand(3));
2804 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
2805 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
2806 I.getOperand(1), 0, I.getOperand(2), 0));
2809 case Intrinsic::memset_i32:
2810 case Intrinsic::memset_i64: {
2811 SDOperand Op1 = getValue(I.getOperand(1));
2812 SDOperand Op2 = getValue(I.getOperand(2));
2813 SDOperand Op3 = getValue(I.getOperand(3));
2814 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
2815 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
2816 I.getOperand(1), 0));
2819 case Intrinsic::memmove_i32:
2820 case Intrinsic::memmove_i64: {
2821 SDOperand Op1 = getValue(I.getOperand(1));
2822 SDOperand Op2 = getValue(I.getOperand(2));
2823 SDOperand Op3 = getValue(I.getOperand(3));
2824 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
2826 // If the source and destination are known to not be aliases, we can
2827 // lower memmove as memcpy.
2828 uint64_t Size = -1ULL;
2829 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
2830 Size = C->getValue();
2831 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
2832 AliasAnalysis::NoAlias) {
2833 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
2834 I.getOperand(1), 0, I.getOperand(2), 0));
2838 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
2839 I.getOperand(1), 0, I.getOperand(2), 0));
2842 case Intrinsic::dbg_stoppoint: {
2843 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2844 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2845 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2849 Ops[1] = getValue(SPI.getLineValue());
2850 Ops[2] = getValue(SPI.getColumnValue());
2852 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2853 assert(DD && "Not a debug information descriptor");
2854 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2856 Ops[3] = DAG.getString(CompileUnit->getFileName());
2857 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2859 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2864 case Intrinsic::dbg_region_start: {
2865 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2866 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2867 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2868 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2869 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2870 DAG.getConstant(LabelID, MVT::i32),
2871 DAG.getConstant(0, MVT::i32)));
2876 case Intrinsic::dbg_region_end: {
2877 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2878 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2879 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2880 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2881 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2882 DAG.getConstant(LabelID, MVT::i32),
2883 DAG.getConstant(0, MVT::i32)));
2888 case Intrinsic::dbg_func_start: {
2889 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2891 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2892 Value *SP = FSI.getSubprogram();
2893 if (SP && MMI->Verify(SP)) {
2894 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
2895 // what (most?) gdb expects.
2896 DebugInfoDesc *DD = MMI->getDescFor(SP);
2897 assert(DD && "Not a debug information descriptor");
2898 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
2899 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
2900 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
2901 CompileUnit->getFileName());
2902 // Record the source line but does create a label. It will be emitted
2903 // at asm emission time.
2904 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
2909 case Intrinsic::dbg_declare: {
2910 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2911 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2912 Value *Variable = DI.getVariable();
2913 if (MMI && Variable && MMI->Verify(Variable))
2914 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
2915 getValue(DI.getAddress()), getValue(Variable)));
2919 case Intrinsic::eh_exception: {
2920 if (!CurMBB->isLandingPad()) {
2921 // FIXME: Mark exception register as live in. Hack for PR1508.
2922 unsigned Reg = TLI.getExceptionAddressRegister();
2923 if (Reg) CurMBB->addLiveIn(Reg);
2925 // Insert the EXCEPTIONADDR instruction.
2926 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2928 Ops[0] = DAG.getRoot();
2929 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2931 DAG.setRoot(Op.getValue(1));
2935 case Intrinsic::eh_selector_i32:
2936 case Intrinsic::eh_selector_i64: {
2937 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2938 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2939 MVT::i32 : MVT::i64);
2942 if (CurMBB->isLandingPad())
2943 addCatchInfo(I, MMI, CurMBB);
2946 FuncInfo.CatchInfoLost.insert(&I);
2948 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2949 unsigned Reg = TLI.getExceptionSelectorRegister();
2950 if (Reg) CurMBB->addLiveIn(Reg);
2953 // Insert the EHSELECTION instruction.
2954 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2956 Ops[0] = getValue(I.getOperand(1));
2958 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2960 DAG.setRoot(Op.getValue(1));
2962 setValue(&I, DAG.getConstant(0, VT));
2968 case Intrinsic::eh_typeid_for_i32:
2969 case Intrinsic::eh_typeid_for_i64: {
2970 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2971 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2972 MVT::i32 : MVT::i64);
2975 // Find the type id for the given typeinfo.
2976 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2978 unsigned TypeID = MMI->getTypeIDFor(GV);
2979 setValue(&I, DAG.getConstant(TypeID, VT));
2981 // Return something different to eh_selector.
2982 setValue(&I, DAG.getConstant(1, VT));
2988 case Intrinsic::eh_return: {
2989 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2992 MMI->setCallsEHReturn(true);
2993 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2996 getValue(I.getOperand(1)),
2997 getValue(I.getOperand(2))));
2999 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3005 case Intrinsic::eh_unwind_init: {
3006 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3007 MMI->setCallsUnwindInit(true);
3013 case Intrinsic::eh_dwarf_cfa: {
3014 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
3016 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
3017 CfaArg = DAG.getNode(ISD::TRUNCATE,
3018 TLI.getPointerTy(), getValue(I.getOperand(1)));
3020 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3021 TLI.getPointerTy(), getValue(I.getOperand(1)));
3023 SDOperand Offset = DAG.getNode(ISD::ADD,
3025 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3026 TLI.getPointerTy()),
3028 setValue(&I, DAG.getNode(ISD::ADD,
3030 DAG.getNode(ISD::FRAMEADDR,
3033 TLI.getPointerTy())),
3038 case Intrinsic::sqrt:
3039 setValue(&I, DAG.getNode(ISD::FSQRT,
3040 getValue(I.getOperand(1)).getValueType(),
3041 getValue(I.getOperand(1))));
3043 case Intrinsic::powi:
3044 setValue(&I, DAG.getNode(ISD::FPOWI,
3045 getValue(I.getOperand(1)).getValueType(),
3046 getValue(I.getOperand(1)),
3047 getValue(I.getOperand(2))));
3049 case Intrinsic::sin:
3050 setValue(&I, DAG.getNode(ISD::FSIN,
3051 getValue(I.getOperand(1)).getValueType(),
3052 getValue(I.getOperand(1))));
3054 case Intrinsic::cos:
3055 setValue(&I, DAG.getNode(ISD::FCOS,
3056 getValue(I.getOperand(1)).getValueType(),
3057 getValue(I.getOperand(1))));
3059 case Intrinsic::pow:
3060 setValue(&I, DAG.getNode(ISD::FPOW,
3061 getValue(I.getOperand(1)).getValueType(),
3062 getValue(I.getOperand(1)),
3063 getValue(I.getOperand(2))));
3065 case Intrinsic::pcmarker: {
3066 SDOperand Tmp = getValue(I.getOperand(1));
3067 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3070 case Intrinsic::readcyclecounter: {
3071 SDOperand Op = getRoot();
3072 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3073 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3076 DAG.setRoot(Tmp.getValue(1));
3079 case Intrinsic::part_select: {
3080 // Currently not implemented: just abort
3081 assert(0 && "part_select intrinsic not implemented");
3084 case Intrinsic::part_set: {
3085 // Currently not implemented: just abort
3086 assert(0 && "part_set intrinsic not implemented");
3089 case Intrinsic::bswap:
3090 setValue(&I, DAG.getNode(ISD::BSWAP,
3091 getValue(I.getOperand(1)).getValueType(),
3092 getValue(I.getOperand(1))));
3094 case Intrinsic::cttz: {
3095 SDOperand Arg = getValue(I.getOperand(1));
3096 MVT::ValueType Ty = Arg.getValueType();
3097 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3098 setValue(&I, result);
3101 case Intrinsic::ctlz: {
3102 SDOperand Arg = getValue(I.getOperand(1));
3103 MVT::ValueType Ty = Arg.getValueType();
3104 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3105 setValue(&I, result);
3108 case Intrinsic::ctpop: {
3109 SDOperand Arg = getValue(I.getOperand(1));
3110 MVT::ValueType Ty = Arg.getValueType();
3111 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3112 setValue(&I, result);
3115 case Intrinsic::stacksave: {
3116 SDOperand Op = getRoot();
3117 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
3118 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3120 DAG.setRoot(Tmp.getValue(1));
3123 case Intrinsic::stackrestore: {
3124 SDOperand Tmp = getValue(I.getOperand(1));
3125 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3128 case Intrinsic::var_annotation:
3129 // Discard annotate attributes
3132 case Intrinsic::init_trampoline: {
3134 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
3138 Ops[1] = getValue(I.getOperand(1));
3139 Ops[2] = getValue(I.getOperand(2));
3140 Ops[3] = getValue(I.getOperand(3));
3141 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3142 Ops[5] = DAG.getSrcValue(F);
3144 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3145 DAG.getNodeValueTypes(TLI.getPointerTy(),
3150 DAG.setRoot(Tmp.getValue(1));
3154 case Intrinsic::gcroot:
3156 Value *Alloca = I.getOperand(1);
3157 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3159 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3160 GCI->addStackRoot(FI->getIndex(), TypeMap);
3164 case Intrinsic::gcread:
3165 case Intrinsic::gcwrite:
3166 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3169 case Intrinsic::flt_rounds: {
3170 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3174 case Intrinsic::trap: {
3175 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3178 case Intrinsic::prefetch: {
3181 Ops[1] = getValue(I.getOperand(1));
3182 Ops[2] = getValue(I.getOperand(2));
3183 Ops[3] = getValue(I.getOperand(3));
3184 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3188 case Intrinsic::memory_barrier: {
3191 for (int x = 1; x < 6; ++x)
3192 Ops[x] = getValue(I.getOperand(x));
3194 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3197 case Intrinsic::atomic_lcs: {
3198 SDOperand Root = getRoot();
3199 SDOperand O3 = getValue(I.getOperand(3));
3200 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root,
3201 getValue(I.getOperand(1)),
3202 getValue(I.getOperand(2)),
3203 O3, O3.getValueType());
3205 DAG.setRoot(L.getValue(1));
3208 case Intrinsic::atomic_las: {
3209 SDOperand Root = getRoot();
3210 SDOperand O2 = getValue(I.getOperand(2));
3211 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LAS, Root,
3212 getValue(I.getOperand(1)),
3213 O2, O2.getValueType());
3215 DAG.setRoot(L.getValue(1));
3218 case Intrinsic::atomic_swap: {
3219 SDOperand Root = getRoot();
3220 SDOperand O2 = getValue(I.getOperand(2));
3221 SDOperand L = DAG.getAtomic(ISD::ATOMIC_SWAP, Root,
3222 getValue(I.getOperand(1)),
3223 O2, O2.getValueType());
3225 DAG.setRoot(L.getValue(1));
3233 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3235 MachineBasicBlock *LandingPad) {
3236 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3237 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3238 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3239 unsigned BeginLabel = 0, EndLabel = 0;
3241 TargetLowering::ArgListTy Args;
3242 TargetLowering::ArgListEntry Entry;
3243 Args.reserve(CS.arg_size());
3244 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3246 SDOperand ArgNode = getValue(*i);
3247 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3249 unsigned attrInd = i - CS.arg_begin() + 1;
3250 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3251 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3252 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3253 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3254 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3255 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3256 Entry.Alignment = CS.getParamAlignment(attrInd);
3257 Args.push_back(Entry);
3260 if (LandingPad && MMI) {
3261 // Insert a label before the invoke call to mark the try range. This can be
3262 // used to detect deletion of the invoke via the MachineModuleInfo.
3263 BeginLabel = MMI->NextLabelID();
3264 // Both PendingLoads and PendingExports must be flushed here;
3265 // this call might not return.
3267 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getControlRoot(),
3268 DAG.getConstant(BeginLabel, MVT::i32),
3269 DAG.getConstant(1, MVT::i32)));
3272 std::pair<SDOperand,SDOperand> Result =
3273 TLI.LowerCallTo(getRoot(), CS.getType(),
3274 CS.paramHasAttr(0, ParamAttr::SExt),
3275 CS.paramHasAttr(0, ParamAttr::ZExt),
3276 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3278 if (CS.getType() != Type::VoidTy)
3279 setValue(CS.getInstruction(), Result.first);
3280 DAG.setRoot(Result.second);
3282 if (LandingPad && MMI) {
3283 // Insert a label at the end of the invoke call to mark the try range. This
3284 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3285 EndLabel = MMI->NextLabelID();
3286 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3287 DAG.getConstant(EndLabel, MVT::i32),
3288 DAG.getConstant(1, MVT::i32)));
3290 // Inform MachineModuleInfo of range.
3291 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3296 void SelectionDAGLowering::visitCall(CallInst &I) {
3297 const char *RenameFn = 0;
3298 if (Function *F = I.getCalledFunction()) {
3299 if (F->isDeclaration()) {
3300 if (unsigned IID = F->getIntrinsicID()) {
3301 RenameFn = visitIntrinsicCall(I, IID);
3307 // Check for well-known libc/libm calls. If the function is internal, it
3308 // can't be a library call.
3309 unsigned NameLen = F->getNameLen();
3310 if (!F->hasInternalLinkage() && NameLen) {
3311 const char *NameStr = F->getNameStart();
3312 if (NameStr[0] == 'c' &&
3313 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3314 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3315 if (I.getNumOperands() == 3 && // Basic sanity checks.
3316 I.getOperand(1)->getType()->isFloatingPoint() &&
3317 I.getType() == I.getOperand(1)->getType() &&
3318 I.getType() == I.getOperand(2)->getType()) {
3319 SDOperand LHS = getValue(I.getOperand(1));
3320 SDOperand RHS = getValue(I.getOperand(2));
3321 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3325 } else if (NameStr[0] == 'f' &&
3326 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3327 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3328 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3329 if (I.getNumOperands() == 2 && // Basic sanity checks.
3330 I.getOperand(1)->getType()->isFloatingPoint() &&
3331 I.getType() == I.getOperand(1)->getType()) {
3332 SDOperand Tmp = getValue(I.getOperand(1));
3333 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3336 } else if (NameStr[0] == 's' &&
3337 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3338 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3339 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3340 if (I.getNumOperands() == 2 && // Basic sanity checks.
3341 I.getOperand(1)->getType()->isFloatingPoint() &&
3342 I.getType() == I.getOperand(1)->getType()) {
3343 SDOperand Tmp = getValue(I.getOperand(1));
3344 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3347 } else if (NameStr[0] == 'c' &&
3348 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3349 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3350 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3351 if (I.getNumOperands() == 2 && // Basic sanity checks.
3352 I.getOperand(1)->getType()->isFloatingPoint() &&
3353 I.getType() == I.getOperand(1)->getType()) {
3354 SDOperand Tmp = getValue(I.getOperand(1));
3355 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3360 } else if (isa<InlineAsm>(I.getOperand(0))) {
3367 Callee = getValue(I.getOperand(0));
3369 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3371 LowerCallTo(&I, Callee, I.isTailCall());
3375 void SelectionDAGLowering::visitGetResult(GetResultInst &I) {
3376 if (isa<UndefValue>(I.getOperand(0))) {
3377 SDOperand Undef = DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType()));
3378 setValue(&I, Undef);
3382 // To add support for individual return values with aggregate types,
3383 // we'd need a way to take a getresult index and determine which
3384 // values of the Call SDNode are associated with it.
3385 assert(TLI.getValueType(I.getType(), true) != MVT::Other &&
3386 "Individual return values must not be aggregates!");
3388 SDOperand Call = getValue(I.getOperand(0));
3389 setValue(&I, SDOperand(Call.Val, I.getIndex()));
3393 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3394 /// this value and returns the result as a ValueVT value. This uses
3395 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3396 /// If the Flag pointer is NULL, no flag is used.
3397 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3399 SDOperand *Flag) const {
3400 // Assemble the legal parts into the final values.
3401 SmallVector<SDOperand, 4> Values(ValueVTs.size());
3402 SmallVector<SDOperand, 8> Parts;
3403 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3404 // Copy the legal parts from the registers.
3405 MVT::ValueType ValueVT = ValueVTs[Value];
3406 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3407 MVT::ValueType RegisterVT = RegVTs[Value];
3409 Parts.resize(NumRegs);
3410 for (unsigned i = 0; i != NumRegs; ++i) {
3413 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3415 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3416 *Flag = P.getValue(2);
3418 Chain = P.getValue(1);
3422 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3427 if (ValueVTs.size() == 1)
3430 return DAG.getNode(ISD::MERGE_VALUES,
3431 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3432 &Values[0], ValueVTs.size());
3435 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3436 /// specified value into the registers specified by this object. This uses
3437 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3438 /// If the Flag pointer is NULL, no flag is used.
3439 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3440 SDOperand &Chain, SDOperand *Flag) const {
3441 // Get the list of the values's legal parts.
3442 unsigned NumRegs = Regs.size();
3443 SmallVector<SDOperand, 8> Parts(NumRegs);
3444 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3445 MVT::ValueType ValueVT = ValueVTs[Value];
3446 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3447 MVT::ValueType RegisterVT = RegVTs[Value];
3449 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3450 &Parts[Part], NumParts, RegisterVT);
3454 // Copy the parts into the registers.
3455 SmallVector<SDOperand, 8> Chains(NumRegs);
3456 for (unsigned i = 0; i != NumRegs; ++i) {
3459 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3461 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3462 *Flag = Part.getValue(1);
3464 Chains[i] = Part.getValue(0);
3467 if (NumRegs == 1 || Flag)
3468 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3469 // flagged to it. That is the CopyToReg nodes and the user are considered
3470 // a single scheduling unit. If we create a TokenFactor and return it as
3471 // chain, then the TokenFactor is both a predecessor (operand) of the
3472 // user as well as a successor (the TF operands are flagged to the user).
3473 // c1, f1 = CopyToReg
3474 // c2, f2 = CopyToReg
3475 // c3 = TokenFactor c1, c2
3478 Chain = Chains[NumRegs-1];
3480 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3483 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3484 /// operand list. This adds the code marker and includes the number of
3485 /// values added into it.
3486 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3487 std::vector<SDOperand> &Ops) const {
3488 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3489 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3490 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3491 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3492 MVT::ValueType RegisterVT = RegVTs[Value];
3493 for (unsigned i = 0; i != NumRegs; ++i)
3494 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3498 /// isAllocatableRegister - If the specified register is safe to allocate,
3499 /// i.e. it isn't a stack pointer or some other special register, return the
3500 /// register class for the register. Otherwise, return null.
3501 static const TargetRegisterClass *
3502 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3503 const TargetLowering &TLI,
3504 const TargetRegisterInfo *TRI) {
3505 MVT::ValueType FoundVT = MVT::Other;
3506 const TargetRegisterClass *FoundRC = 0;
3507 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3508 E = TRI->regclass_end(); RCI != E; ++RCI) {
3509 MVT::ValueType ThisVT = MVT::Other;
3511 const TargetRegisterClass *RC = *RCI;
3512 // If none of the the value types for this register class are valid, we
3513 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3514 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3516 if (TLI.isTypeLegal(*I)) {
3517 // If we have already found this register in a different register class,
3518 // choose the one with the largest VT specified. For example, on
3519 // PowerPC, we favor f64 register classes over f32.
3520 if (FoundVT == MVT::Other ||
3521 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3528 if (ThisVT == MVT::Other) continue;
3530 // NOTE: This isn't ideal. In particular, this might allocate the
3531 // frame pointer in functions that need it (due to them not being taken
3532 // out of allocation, because a variable sized allocation hasn't been seen
3533 // yet). This is a slight code pessimization, but should still work.
3534 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3535 E = RC->allocation_order_end(MF); I != E; ++I)
3537 // We found a matching register class. Keep looking at others in case
3538 // we find one with larger registers that this physreg is also in.
3549 /// AsmOperandInfo - This contains information for each constraint that we are
3551 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3552 /// CallOperand - If this is the result output operand or a clobber
3553 /// this is null, otherwise it is the incoming operand to the CallInst.
3554 /// This gets modified as the asm is processed.
3555 SDOperand CallOperand;
3557 /// AssignedRegs - If this is a register or register class operand, this
3558 /// contains the set of register corresponding to the operand.
3559 RegsForValue AssignedRegs;
3561 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3562 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3565 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3566 /// busy in OutputRegs/InputRegs.
3567 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3568 std::set<unsigned> &OutputRegs,
3569 std::set<unsigned> &InputRegs,
3570 const TargetRegisterInfo &TRI) const {
3572 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3573 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3576 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3577 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3582 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3584 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3585 const TargetRegisterInfo &TRI) {
3586 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3588 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3589 for (; *Aliases; ++Aliases)
3590 Regs.insert(*Aliases);
3593 } // end anon namespace.
3596 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3597 /// specified operand. We prefer to assign virtual registers, to allow the
3598 /// register allocator handle the assignment process. However, if the asm uses
3599 /// features that we can't model on machineinstrs, we have SDISel do the
3600 /// allocation. This produces generally horrible, but correct, code.
3602 /// OpInfo describes the operand.
3603 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3604 /// or any explicitly clobbered registers.
3605 /// Input and OutputRegs are the set of already allocated physical registers.
3607 void SelectionDAGLowering::
3608 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3609 std::set<unsigned> &OutputRegs,
3610 std::set<unsigned> &InputRegs) {
3611 // Compute whether this value requires an input register, an output register,
3613 bool isOutReg = false;
3614 bool isInReg = false;
3615 switch (OpInfo.Type) {
3616 case InlineAsm::isOutput:
3619 // If this is an early-clobber output, or if there is an input
3620 // constraint that matches this, we need to reserve the input register
3621 // so no other inputs allocate to it.
3622 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3624 case InlineAsm::isInput:
3628 case InlineAsm::isClobber:
3635 MachineFunction &MF = DAG.getMachineFunction();
3636 SmallVector<unsigned, 4> Regs;
3638 // If this is a constraint for a single physreg, or a constraint for a
3639 // register class, find it.
3640 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3641 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3642 OpInfo.ConstraintVT);
3644 unsigned NumRegs = 1;
3645 if (OpInfo.ConstraintVT != MVT::Other)
3646 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3647 MVT::ValueType RegVT;
3648 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3651 // If this is a constraint for a specific physical register, like {r17},
3653 if (PhysReg.first) {
3654 if (OpInfo.ConstraintVT == MVT::Other)
3655 ValueVT = *PhysReg.second->vt_begin();
3657 // Get the actual register value type. This is important, because the user
3658 // may have asked for (e.g.) the AX register in i32 type. We need to
3659 // remember that AX is actually i16 to get the right extension.
3660 RegVT = *PhysReg.second->vt_begin();
3662 // This is a explicit reference to a physical register.
3663 Regs.push_back(PhysReg.first);
3665 // If this is an expanded reference, add the rest of the regs to Regs.
3667 TargetRegisterClass::iterator I = PhysReg.second->begin();
3668 TargetRegisterClass::iterator E = PhysReg.second->end();
3669 for (; *I != PhysReg.first; ++I)
3670 assert(I != E && "Didn't find reg!");
3672 // Already added the first reg.
3674 for (; NumRegs; --NumRegs, ++I) {
3675 assert(I != E && "Ran out of registers to allocate!");
3679 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
3680 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3681 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3685 // Otherwise, if this was a reference to an LLVM register class, create vregs
3686 // for this reference.
3687 std::vector<unsigned> RegClassRegs;
3688 const TargetRegisterClass *RC = PhysReg.second;
3690 // If this is an early clobber or tied register, our regalloc doesn't know
3691 // how to maintain the constraint. If it isn't, go ahead and create vreg
3692 // and let the regalloc do the right thing.
3693 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3694 // If there is some other early clobber and this is an input register,
3695 // then we are forced to pre-allocate the input reg so it doesn't
3696 // conflict with the earlyclobber.
3697 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3698 RegVT = *PhysReg.second->vt_begin();
3700 if (OpInfo.ConstraintVT == MVT::Other)
3703 // Create the appropriate number of virtual registers.
3704 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3705 for (; NumRegs; --NumRegs)
3706 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3708 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
3712 // Otherwise, we can't allocate it. Let the code below figure out how to
3713 // maintain these constraints.
3714 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3717 // This is a reference to a register class that doesn't directly correspond
3718 // to an LLVM register class. Allocate NumRegs consecutive, available,
3719 // registers from the class.
3720 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3721 OpInfo.ConstraintVT);
3724 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3725 unsigned NumAllocated = 0;
3726 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3727 unsigned Reg = RegClassRegs[i];
3728 // See if this register is available.
3729 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3730 (isInReg && InputRegs.count(Reg))) { // Already used.
3731 // Make sure we find consecutive registers.
3736 // Check to see if this register is allocatable (i.e. don't give out the
3739 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
3740 if (!RC) { // Couldn't allocate this register.
3741 // Reset NumAllocated to make sure we return consecutive registers.
3747 // Okay, this register is good, we can use it.
3750 // If we allocated enough consecutive registers, succeed.
3751 if (NumAllocated == NumRegs) {
3752 unsigned RegStart = (i-NumAllocated)+1;
3753 unsigned RegEnd = i+1;
3754 // Mark all of the allocated registers used.
3755 for (unsigned i = RegStart; i != RegEnd; ++i)
3756 Regs.push_back(RegClassRegs[i]);
3758 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
3759 OpInfo.ConstraintVT);
3760 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3765 // Otherwise, we couldn't allocate enough registers for this.
3769 /// visitInlineAsm - Handle a call to an InlineAsm object.
3771 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3772 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3774 /// ConstraintOperands - Information about all of the constraints.
3775 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
3777 SDOperand Chain = getRoot();
3780 std::set<unsigned> OutputRegs, InputRegs;
3782 // Do a prepass over the constraints, canonicalizing them, and building up the
3783 // ConstraintOperands list.
3784 std::vector<InlineAsm::ConstraintInfo>
3785 ConstraintInfos = IA->ParseConstraints();
3787 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3788 // constraint. If so, we can't let the register allocator allocate any input
3789 // registers, because it will not know to avoid the earlyclobbered output reg.
3790 bool SawEarlyClobber = false;
3792 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3793 unsigned ResNo = 0; // ResNo - The result number of the next output.
3794 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3795 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
3796 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
3798 MVT::ValueType OpVT = MVT::Other;
3800 // Compute the value type for each operand.
3801 switch (OpInfo.Type) {
3802 case InlineAsm::isOutput:
3803 // Indirect outputs just consume an argument.
3804 if (OpInfo.isIndirect) {
3805 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3808 // The return value of the call is this value. As such, there is no
3809 // corresponding argument.
3810 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3811 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
3812 OpVT = TLI.getValueType(STy->getElementType(ResNo));
3814 assert(ResNo == 0 && "Asm only has one result!");
3815 OpVT = TLI.getValueType(CS.getType());
3819 case InlineAsm::isInput:
3820 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3822 case InlineAsm::isClobber:
3827 // If this is an input or an indirect output, process the call argument.
3828 // BasicBlocks are labels, currently appearing only in asm's.
3829 if (OpInfo.CallOperandVal) {
3830 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
3831 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
3833 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3834 const Type *OpTy = OpInfo.CallOperandVal->getType();
3835 // If this is an indirect operand, the operand is a pointer to the
3837 if (OpInfo.isIndirect)
3838 OpTy = cast<PointerType>(OpTy)->getElementType();
3840 // If OpTy is not a first-class value, it may be a struct/union that we
3841 // can tile with integers.
3842 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3843 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3851 OpTy = IntegerType::get(BitSize);
3856 OpVT = TLI.getValueType(OpTy, true);
3860 OpInfo.ConstraintVT = OpVT;
3862 // Compute the constraint code and ConstraintType to use.
3863 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
3865 // Keep track of whether we see an earlyclobber.
3866 SawEarlyClobber |= OpInfo.isEarlyClobber;
3868 // If we see a clobber of a register, it is an early clobber.
3869 if (!SawEarlyClobber &&
3870 OpInfo.Type == InlineAsm::isClobber &&
3871 OpInfo.ConstraintType == TargetLowering::C_Register) {
3872 // Note that we want to ignore things that we don't trick here, like
3873 // dirflag, fpsr, flags, etc.
3874 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3875 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3876 OpInfo.ConstraintVT);
3877 if (PhysReg.first || PhysReg.second) {
3878 // This is a register we know of.
3879 SawEarlyClobber = true;
3883 // If this is a memory input, and if the operand is not indirect, do what we
3884 // need to to provide an address for the memory input.
3885 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3886 !OpInfo.isIndirect) {
3887 assert(OpInfo.Type == InlineAsm::isInput &&
3888 "Can only indirectify direct input operands!");
3890 // Memory operands really want the address of the value. If we don't have
3891 // an indirect input, put it in the constpool if we can, otherwise spill
3892 // it to a stack slot.
3894 // If the operand is a float, integer, or vector constant, spill to a
3895 // constant pool entry to get its address.
3896 Value *OpVal = OpInfo.CallOperandVal;
3897 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3898 isa<ConstantVector>(OpVal)) {
3899 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3900 TLI.getPointerTy());
3902 // Otherwise, create a stack slot and emit a store to it before the
3904 const Type *Ty = OpVal->getType();
3905 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3906 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3907 MachineFunction &MF = DAG.getMachineFunction();
3908 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3909 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3910 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3911 OpInfo.CallOperand = StackSlot;
3914 // There is no longer a Value* corresponding to this operand.
3915 OpInfo.CallOperandVal = 0;
3916 // It is now an indirect operand.
3917 OpInfo.isIndirect = true;
3920 // If this constraint is for a specific register, allocate it before
3922 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3923 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3925 ConstraintInfos.clear();
3928 // Second pass - Loop over all of the operands, assigning virtual or physregs
3929 // to registerclass operands.
3930 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3931 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
3933 // C_Register operands have already been allocated, Other/Memory don't need
3935 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3936 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3939 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3940 std::vector<SDOperand> AsmNodeOperands;
3941 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3942 AsmNodeOperands.push_back(
3943 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3946 // Loop over all of the inputs, copying the operand values into the
3947 // appropriate registers and processing the output regs.
3948 RegsForValue RetValRegs;
3950 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3951 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3953 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3954 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
3956 switch (OpInfo.Type) {
3957 case InlineAsm::isOutput: {
3958 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3959 OpInfo.ConstraintType != TargetLowering::C_Register) {
3960 // Memory output, or 'other' output (e.g. 'X' constraint).
3961 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3963 // Add information to the INLINEASM node to know about this output.
3964 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3965 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3966 TLI.getPointerTy()));
3967 AsmNodeOperands.push_back(OpInfo.CallOperand);
3971 // Otherwise, this is a register or register class output.
3973 // Copy the output from the appropriate register. Find a register that
3975 if (OpInfo.AssignedRegs.Regs.empty()) {
3976 cerr << "Couldn't allocate output reg for contraint '"
3977 << OpInfo.ConstraintCode << "'!\n";
3981 // If this is an indirect operand, store through the pointer after the
3983 if (OpInfo.isIndirect) {
3984 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3985 OpInfo.CallOperandVal));
3987 // This is the result value of the call.
3988 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3989 // Concatenate this output onto the outputs list.
3990 RetValRegs.append(OpInfo.AssignedRegs);
3993 // Add information to the INLINEASM node to know that this register is
3995 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3999 case InlineAsm::isInput: {
4000 SDOperand InOperandVal = OpInfo.CallOperand;
4002 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4003 // If this is required to match an output register we have already set,
4004 // just use its register.
4005 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4007 // Scan until we find the definition we already emitted of this operand.
4008 // When we find it, create a RegsForValue operand.
4009 unsigned CurOp = 2; // The first operand.
4010 for (; OperandNo; --OperandNo) {
4011 // Advance to the next operand.
4013 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4014 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4015 (NumOps & 7) == 4 /*MEM*/) &&
4016 "Skipped past definitions?");
4017 CurOp += (NumOps>>3)+1;
4021 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4022 if ((NumOps & 7) == 2 /*REGDEF*/) {
4023 // Add NumOps>>3 registers to MatchedRegs.
4024 RegsForValue MatchedRegs;
4025 MatchedRegs.TLI = &TLI;
4026 MatchedRegs.ValueVTs.resize(1, InOperandVal.getValueType());
4027 MatchedRegs.RegVTs.resize(1, AsmNodeOperands[CurOp+1].getValueType());
4028 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4030 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4031 MatchedRegs.Regs.push_back(Reg);
4034 // Use the produced MatchedRegs object to
4035 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4036 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4039 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4040 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4041 // Add information to the INLINEASM node to know about this input.
4042 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4043 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4044 TLI.getPointerTy()));
4045 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4050 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4051 assert(!OpInfo.isIndirect &&
4052 "Don't know how to handle indirect other inputs yet!");
4054 std::vector<SDOperand> Ops;
4055 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4058 cerr << "Invalid operand for inline asm constraint '"
4059 << OpInfo.ConstraintCode << "'!\n";
4063 // Add information to the INLINEASM node to know about this input.
4064 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4065 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4066 TLI.getPointerTy()));
4067 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4069 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4070 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4071 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4072 "Memory operands expect pointer values");
4074 // Add information to the INLINEASM node to know about this input.
4075 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4076 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4077 TLI.getPointerTy()));
4078 AsmNodeOperands.push_back(InOperandVal);
4082 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4083 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4084 "Unknown constraint type!");
4085 assert(!OpInfo.isIndirect &&
4086 "Don't know how to handle indirect register inputs yet!");
4088 // Copy the input into the appropriate registers.
4089 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4090 "Couldn't allocate input reg!");
4092 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4094 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4098 case InlineAsm::isClobber: {
4099 // Add the clobbered value to the operand list, so that the register
4100 // allocator is aware that the physreg got clobbered.
4101 if (!OpInfo.AssignedRegs.Regs.empty())
4102 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4109 // Finish up input operands.
4110 AsmNodeOperands[0] = Chain;
4111 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4113 Chain = DAG.getNode(ISD::INLINEASM,
4114 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4115 &AsmNodeOperands[0], AsmNodeOperands.size());
4116 Flag = Chain.getValue(1);
4118 // If this asm returns a register value, copy the result from that register
4119 // and set it as the value of the call.
4120 if (!RetValRegs.Regs.empty()) {
4121 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4123 // If any of the results of the inline asm is a vector, it may have the
4124 // wrong width/num elts. This can happen for register classes that can
4125 // contain multiple different value types. The preg or vreg allocated may
4126 // not have the same VT as was expected. Convert it to the right type with
4128 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4129 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4130 if (MVT::isVector(Val.Val->getValueType(i)))
4131 Val = DAG.getNode(ISD::BIT_CONVERT,
4132 TLI.getValueType(ResSTy->getElementType(i)), Val);
4135 if (MVT::isVector(Val.getValueType()))
4136 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4140 setValue(CS.getInstruction(), Val);
4143 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
4145 // Process indirect outputs, first output all of the flagged copies out of
4147 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4148 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4149 Value *Ptr = IndirectStoresToEmit[i].second;
4150 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4151 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4154 // Emit the non-flagged stores from the physregs.
4155 SmallVector<SDOperand, 8> OutChains;
4156 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4157 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4158 getValue(StoresToEmit[i].second),
4159 StoresToEmit[i].second, 0));
4160 if (!OutChains.empty())
4161 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4162 &OutChains[0], OutChains.size());
4167 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4168 SDOperand Src = getValue(I.getOperand(0));
4170 MVT::ValueType IntPtr = TLI.getPointerTy();
4172 if (IntPtr < Src.getValueType())
4173 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4174 else if (IntPtr > Src.getValueType())
4175 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4177 // Scale the source by the type size.
4178 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4179 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4180 Src, DAG.getIntPtrConstant(ElementSize));
4182 TargetLowering::ArgListTy Args;
4183 TargetLowering::ArgListEntry Entry;
4185 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4186 Args.push_back(Entry);
4188 std::pair<SDOperand,SDOperand> Result =
4189 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4190 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4191 setValue(&I, Result.first); // Pointers always fit in registers
4192 DAG.setRoot(Result.second);
4195 void SelectionDAGLowering::visitFree(FreeInst &I) {
4196 TargetLowering::ArgListTy Args;
4197 TargetLowering::ArgListEntry Entry;
4198 Entry.Node = getValue(I.getOperand(0));
4199 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4200 Args.push_back(Entry);
4201 MVT::ValueType IntPtr = TLI.getPointerTy();
4202 std::pair<SDOperand,SDOperand> Result =
4203 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4204 CallingConv::C, true,
4205 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4206 DAG.setRoot(Result.second);
4209 // EmitInstrWithCustomInserter - This method should be implemented by targets
4210 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4211 // instructions are special in various ways, which require special support to
4212 // insert. The specified MachineInstr is created but not inserted into any
4213 // basic blocks, and the scheduler passes ownership of it to this method.
4214 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4215 MachineBasicBlock *MBB) {
4216 cerr << "If a target marks an instruction with "
4217 << "'usesCustomDAGSchedInserter', it must implement "
4218 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4223 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4224 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4225 getValue(I.getOperand(1)),
4226 DAG.getSrcValue(I.getOperand(1))));
4229 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4230 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4231 getValue(I.getOperand(0)),
4232 DAG.getSrcValue(I.getOperand(0)));
4234 DAG.setRoot(V.getValue(1));
4237 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4238 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4239 getValue(I.getOperand(1)),
4240 DAG.getSrcValue(I.getOperand(1))));
4243 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4244 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4245 getValue(I.getOperand(1)),
4246 getValue(I.getOperand(2)),
4247 DAG.getSrcValue(I.getOperand(1)),
4248 DAG.getSrcValue(I.getOperand(2))));
4251 /// TargetLowering::LowerArguments - This is the default LowerArguments
4252 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4253 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4254 /// integrated into SDISel.
4255 std::vector<SDOperand>
4256 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
4257 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4258 std::vector<SDOperand> Ops;
4259 Ops.push_back(DAG.getRoot());
4260 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4261 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4263 // Add one result value for each formal argument.
4264 std::vector<MVT::ValueType> RetVals;
4266 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4268 MVT::ValueType VT = getValueType(I->getType());
4269 ISD::ArgFlagsTy Flags;
4270 unsigned OriginalAlignment =
4271 getTargetData()->getABITypeAlignment(I->getType());
4273 if (F.paramHasAttr(j, ParamAttr::ZExt))
4275 if (F.paramHasAttr(j, ParamAttr::SExt))
4277 if (F.paramHasAttr(j, ParamAttr::InReg))
4279 if (F.paramHasAttr(j, ParamAttr::StructRet))
4281 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4283 const PointerType *Ty = cast<PointerType>(I->getType());
4284 const Type *ElementTy = Ty->getElementType();
4285 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4286 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4287 // For ByVal, alignment should be passed from FE. BE will guess if
4288 // this info is not there but there are cases it cannot get right.
4289 if (F.getParamAlignment(j))
4290 FrameAlign = F.getParamAlignment(j);
4291 Flags.setByValAlign(FrameAlign);
4292 Flags.setByValSize(FrameSize);
4294 if (F.paramHasAttr(j, ParamAttr::Nest))
4296 Flags.setOrigAlign(OriginalAlignment);
4298 MVT::ValueType RegisterVT = getRegisterType(VT);
4299 unsigned NumRegs = getNumRegisters(VT);
4300 for (unsigned i = 0; i != NumRegs; ++i) {
4301 RetVals.push_back(RegisterVT);
4302 ISD::ArgFlagsTy MyFlags = Flags;
4303 if (NumRegs > 1 && i == 0)
4305 // if it isn't first piece, alignment must be 1
4307 MyFlags.setOrigAlign(1);
4308 Ops.push_back(DAG.getArgFlags(MyFlags));
4312 RetVals.push_back(MVT::Other);
4315 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4316 DAG.getVTList(&RetVals[0], RetVals.size()),
4317 &Ops[0], Ops.size()).Val;
4319 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4320 // allows exposing the loads that may be part of the argument access to the
4321 // first DAGCombiner pass.
4322 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4324 // The number of results should match up, except that the lowered one may have
4325 // an extra flag result.
4326 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4327 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4328 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4329 && "Lowering produced unexpected number of results!");
4330 Result = TmpRes.Val;
4332 unsigned NumArgRegs = Result->getNumValues() - 1;
4333 DAG.setRoot(SDOperand(Result, NumArgRegs));
4335 // Set up the return result vector.
4339 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4341 MVT::ValueType VT = getValueType(I->getType());
4342 MVT::ValueType PartVT = getRegisterType(VT);
4344 unsigned NumParts = getNumRegisters(VT);
4345 SmallVector<SDOperand, 4> Parts(NumParts);
4346 for (unsigned j = 0; j != NumParts; ++j)
4347 Parts[j] = SDOperand(Result, i++);
4349 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4350 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4351 AssertOp = ISD::AssertSext;
4352 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4353 AssertOp = ISD::AssertZext;
4355 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4358 assert(i == NumArgRegs && "Argument register count mismatch!");
4363 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4364 /// implementation, which just inserts an ISD::CALL node, which is later custom
4365 /// lowered by the target to something concrete. FIXME: When all targets are
4366 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4367 std::pair<SDOperand, SDOperand>
4368 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4369 bool RetSExt, bool RetZExt, bool isVarArg,
4370 unsigned CallingConv, bool isTailCall,
4372 ArgListTy &Args, SelectionDAG &DAG) {
4373 SmallVector<SDOperand, 32> Ops;
4374 Ops.push_back(Chain); // Op#0 - Chain
4375 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4376 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4377 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4378 Ops.push_back(Callee);
4380 // Handle all of the outgoing arguments.
4381 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4382 MVT::ValueType VT = getValueType(Args[i].Ty);
4383 SDOperand Op = Args[i].Node;
4384 ISD::ArgFlagsTy Flags;
4385 unsigned OriginalAlignment =
4386 getTargetData()->getABITypeAlignment(Args[i].Ty);
4392 if (Args[i].isInReg)
4396 if (Args[i].isByVal) {
4398 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4399 const Type *ElementTy = Ty->getElementType();
4400 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4401 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4402 // For ByVal, alignment should come from FE. BE will guess if this
4403 // info is not there but there are cases it cannot get right.
4404 if (Args[i].Alignment)
4405 FrameAlign = Args[i].Alignment;
4406 Flags.setByValAlign(FrameAlign);
4407 Flags.setByValSize(FrameSize);
4411 Flags.setOrigAlign(OriginalAlignment);
4413 MVT::ValueType PartVT = getRegisterType(VT);
4414 unsigned NumParts = getNumRegisters(VT);
4415 SmallVector<SDOperand, 4> Parts(NumParts);
4416 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4419 ExtendKind = ISD::SIGN_EXTEND;
4420 else if (Args[i].isZExt)
4421 ExtendKind = ISD::ZERO_EXTEND;
4423 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4425 for (unsigned i = 0; i != NumParts; ++i) {
4426 // if it isn't first piece, alignment must be 1
4427 ISD::ArgFlagsTy MyFlags = Flags;
4428 if (NumParts > 1 && i == 0)
4431 MyFlags.setOrigAlign(1);
4433 Ops.push_back(Parts[i]);
4434 Ops.push_back(DAG.getArgFlags(MyFlags));
4438 // Figure out the result value types. We start by making a list of
4439 // the potentially illegal return value types.
4440 SmallVector<MVT::ValueType, 4> LoweredRetTys;
4441 SmallVector<MVT::ValueType, 4> RetTys;
4442 ComputeValueVTs(*this, RetTy, RetTys);
4444 // Then we translate that to a list of legal types.
4445 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4446 MVT::ValueType VT = RetTys[I];
4447 MVT::ValueType RegisterVT = getRegisterType(VT);
4448 unsigned NumRegs = getNumRegisters(VT);
4449 for (unsigned i = 0; i != NumRegs; ++i)
4450 LoweredRetTys.push_back(RegisterVT);
4453 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4455 // Create the CALL node.
4456 SDOperand Res = DAG.getNode(ISD::CALL,
4457 DAG.getVTList(&LoweredRetTys[0],
4458 LoweredRetTys.size()),
4459 &Ops[0], Ops.size());
4460 Chain = Res.getValue(LoweredRetTys.size() - 1);
4462 // Gather up the call result into a single value.
4463 if (RetTy != Type::VoidTy) {
4464 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4467 AssertOp = ISD::AssertSext;
4469 AssertOp = ISD::AssertZext;
4471 SmallVector<SDOperand, 4> ReturnValues;
4473 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4474 MVT::ValueType VT = RetTys[I];
4475 MVT::ValueType RegisterVT = getRegisterType(VT);
4476 unsigned NumRegs = getNumRegisters(VT);
4477 unsigned RegNoEnd = NumRegs + RegNo;
4478 SmallVector<SDOperand, 4> Results;
4479 for (; RegNo != RegNoEnd; ++RegNo)
4480 Results.push_back(Res.getValue(RegNo));
4481 SDOperand ReturnValue =
4482 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4484 ReturnValues.push_back(ReturnValue);
4486 Res = ReturnValues.size() == 1 ? ReturnValues.front() :
4487 DAG.getNode(ISD::MERGE_VALUES,
4488 DAG.getVTList(&RetTys[0], RetTys.size()),
4489 &ReturnValues[0], ReturnValues.size());
4492 return std::make_pair(Res, Chain);
4495 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4496 assert(0 && "LowerOperation not implemented for this target!");
4501 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4502 SelectionDAG &DAG) {
4503 assert(0 && "CustomPromoteOperation not implemented for this target!");
4508 //===----------------------------------------------------------------------===//
4509 // SelectionDAGISel code
4510 //===----------------------------------------------------------------------===//
4512 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4513 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4516 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4517 AU.addRequired<AliasAnalysis>();
4518 AU.addRequired<CollectorModuleMetadata>();
4519 AU.setPreservesAll();
4524 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4525 // Get alias analysis for load/store combining.
4526 AA = &getAnalysis<AliasAnalysis>();
4528 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4529 if (MF.getFunction()->hasCollector())
4530 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4533 RegInfo = &MF.getRegInfo();
4534 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4536 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4538 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4539 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4540 // Mark landing pad.
4541 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4543 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4544 SelectBasicBlock(I, MF, FuncInfo);
4546 // Add function live-ins to entry block live-in set.
4547 BasicBlock *EntryBB = &Fn.getEntryBlock();
4548 BB = FuncInfo.MBBMap[EntryBB];
4549 if (!RegInfo->livein_empty())
4550 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4551 E = RegInfo->livein_end(); I != E; ++I)
4552 BB->addLiveIn(I->first);
4555 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4556 "Not all catch info was assigned to a landing pad!");
4562 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4563 SDOperand Op = getValue(V);
4564 assert((Op.getOpcode() != ISD::CopyFromReg ||
4565 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4566 "Copy from a reg to the same reg!");
4567 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4569 RegsForValue RFV(TLI, Reg, V->getType());
4570 SDOperand Chain = DAG.getEntryNode();
4571 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4572 PendingExports.push_back(Chain);
4575 void SelectionDAGISel::
4576 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4577 // If this is the entry block, emit arguments.
4578 Function &F = *LLVMBB->getParent();
4579 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4580 SDOperand OldRoot = SDL.DAG.getRoot();
4581 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4584 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4586 if (!AI->use_empty()) {
4587 SDL.setValue(AI, Args[a]);
4589 // If this argument is live outside of the entry block, insert a copy from
4590 // whereever we got it to the vreg that other BB's will reference it as.
4591 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4592 if (VMI != FuncInfo.ValueMap.end()) {
4593 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4597 // Finally, if the target has anything special to do, allow it to do so.
4598 // FIXME: this should insert code into the DAG!
4599 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4602 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4603 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4604 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4605 if (isSelector(I)) {
4606 // Apply the catch info to DestBB.
4607 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4609 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4610 FLI.CatchInfoFound.insert(I);
4615 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4616 /// whether object offset >= 0.
4618 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDOperand Op) {
4619 if (!isa<FrameIndexSDNode>(Op)) return false;
4621 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4622 int FrameIdx = FrameIdxNode->getIndex();
4623 return MFI->isFixedObjectIndex(FrameIdx) &&
4624 MFI->getObjectOffset(FrameIdx) >= 0;
4627 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
4628 /// possibly be overwritten when lowering the outgoing arguments in a tail
4629 /// call. Currently the implementation of this call is very conservative and
4630 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
4631 /// virtual registers would be overwritten by direct lowering.
4632 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
4633 MachineFrameInfo * MFI) {
4634 RegisterSDNode * OpReg = NULL;
4635 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
4636 (Op.getOpcode()== ISD::CopyFromReg &&
4637 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
4638 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
4639 (Op.getOpcode() == ISD::LOAD &&
4640 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
4641 (Op.getOpcode() == ISD::MERGE_VALUES &&
4642 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
4643 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
4649 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4650 /// DAG and fixes their tailcall attribute operand.
4651 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4652 TargetLowering& TLI) {
4653 SDNode * Ret = NULL;
4654 SDOperand Terminator = DAG.getRoot();
4657 if (Terminator.getOpcode() == ISD::RET) {
4658 Ret = Terminator.Val;
4661 // Fix tail call attribute of CALL nodes.
4662 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4663 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4664 if (BI->getOpcode() == ISD::CALL) {
4665 SDOperand OpRet(Ret, 0);
4666 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4667 bool isMarkedTailCall =
4668 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4669 // If CALL node has tail call attribute set to true and the call is not
4670 // eligible (no RET or the target rejects) the attribute is fixed to
4671 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4672 // must correctly identify tail call optimizable calls.
4673 if (!isMarkedTailCall) continue;
4675 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
4676 // Not eligible. Mark CALL node as non tail call.
4677 SmallVector<SDOperand, 32> Ops;
4679 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4680 E = OpCall.Val->op_end(); I != E; I++, idx++) {
4684 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4686 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4688 // Look for tail call clobbered arguments. Emit a series of
4689 // copyto/copyfrom virtual register nodes to protect them.
4690 SmallVector<SDOperand, 32> Ops;
4691 SDOperand Chain = OpCall.getOperand(0), InFlag;
4693 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
4694 E = OpCall.Val->op_end(); I != E; I++, idx++) {
4696 if (idx > 4 && (idx % 2)) {
4697 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
4698 getArgFlags().isByVal();
4699 MachineFunction &MF = DAG.getMachineFunction();
4700 MachineFrameInfo *MFI = MF.getFrameInfo();
4702 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
4703 MVT::ValueType VT = Arg.getValueType();
4704 unsigned VReg = MF.getRegInfo().
4705 createVirtualRegister(TLI.getRegClassFor(VT));
4706 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
4707 InFlag = Chain.getValue(1);
4708 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
4709 Chain = Arg.getValue(1);
4710 InFlag = Arg.getValue(2);
4715 // Link in chain of CopyTo/CopyFromReg.
4717 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4723 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4724 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4725 FunctionLoweringInfo &FuncInfo) {
4726 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4728 // Lower any arguments needed in this block if this is the entry block.
4729 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4730 LowerArguments(LLVMBB, SDL);
4732 BB = FuncInfo.MBBMap[LLVMBB];
4733 SDL.setCurrentBasicBlock(BB);
4735 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4737 if (MMI && BB->isLandingPad()) {
4738 // Add a label to mark the beginning of the landing pad. Deletion of the
4739 // landing pad can thus be detected via the MachineModuleInfo.
4740 unsigned LabelID = MMI->addLandingPad(BB);
4741 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4742 DAG.getConstant(LabelID, MVT::i32),
4743 DAG.getConstant(1, MVT::i32)));
4745 // Mark exception register as live in.
4746 unsigned Reg = TLI.getExceptionAddressRegister();
4747 if (Reg) BB->addLiveIn(Reg);
4749 // Mark exception selector register as live in.
4750 Reg = TLI.getExceptionSelectorRegister();
4751 if (Reg) BB->addLiveIn(Reg);
4753 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4754 // function and list of typeids logically belong to the invoke (or, if you
4755 // like, the basic block containing the invoke), and need to be associated
4756 // with it in the dwarf exception handling tables. Currently however the
4757 // information is provided by an intrinsic (eh.selector) that can be moved
4758 // to unexpected places by the optimizers: if the unwind edge is critical,
4759 // then breaking it can result in the intrinsics being in the successor of
4760 // the landing pad, not the landing pad itself. This results in exceptions
4761 // not being caught because no typeids are associated with the invoke.
4762 // This may not be the only way things can go wrong, but it is the only way
4763 // we try to work around for the moment.
4764 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4766 if (Br && Br->isUnconditional()) { // Critical edge?
4767 BasicBlock::iterator I, E;
4768 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4773 // No catch info found - try to extract some from the successor.
4774 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4778 // Lower all of the non-terminator instructions.
4779 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4783 // Ensure that all instructions which are used outside of their defining
4784 // blocks are available as virtual registers. Invoke is handled elsewhere.
4785 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4786 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4787 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4788 if (VMI != FuncInfo.ValueMap.end())
4789 SDL.CopyValueToVirtualRegister(I, VMI->second);
4792 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4793 // ensure constants are generated when needed. Remember the virtual registers
4794 // that need to be added to the Machine PHI nodes as input. We cannot just
4795 // directly add them, because expansion might result in multiple MBB's for one
4796 // BB. As such, the start of the BB might correspond to a different MBB than
4799 TerminatorInst *TI = LLVMBB->getTerminator();
4801 // Emit constants only once even if used by multiple PHI nodes.
4802 std::map<Constant*, unsigned> ConstantsOut;
4804 // Vector bool would be better, but vector<bool> is really slow.
4805 std::vector<unsigned char> SuccsHandled;
4806 if (TI->getNumSuccessors())
4807 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4809 // Check successor nodes' PHI nodes that expect a constant to be available
4811 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4812 BasicBlock *SuccBB = TI->getSuccessor(succ);
4813 if (!isa<PHINode>(SuccBB->begin())) continue;
4814 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4816 // If this terminator has multiple identical successors (common for
4817 // switches), only handle each succ once.
4818 unsigned SuccMBBNo = SuccMBB->getNumber();
4819 if (SuccsHandled[SuccMBBNo]) continue;
4820 SuccsHandled[SuccMBBNo] = true;
4822 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4825 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4826 // nodes and Machine PHI nodes, but the incoming operands have not been
4828 for (BasicBlock::iterator I = SuccBB->begin();
4829 (PN = dyn_cast<PHINode>(I)); ++I) {
4830 // Ignore dead phi's.
4831 if (PN->use_empty()) continue;
4834 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4836 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4837 unsigned &RegOut = ConstantsOut[C];
4839 RegOut = FuncInfo.CreateRegForValue(C);
4840 SDL.CopyValueToVirtualRegister(C, RegOut);
4844 Reg = FuncInfo.ValueMap[PHIOp];
4846 assert(isa<AllocaInst>(PHIOp) &&
4847 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4848 "Didn't codegen value into a register!??");
4849 Reg = FuncInfo.CreateRegForValue(PHIOp);
4850 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
4854 // Remember that this register needs to added to the machine PHI node as
4855 // the input for this MBB.
4856 MVT::ValueType VT = TLI.getValueType(PN->getType());
4857 unsigned NumRegisters = TLI.getNumRegisters(VT);
4858 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4859 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4862 ConstantsOut.clear();
4864 // Lower the terminator after the copies are emitted.
4865 SDL.visit(*LLVMBB->getTerminator());
4867 // Copy over any CaseBlock records that may now exist due to SwitchInst
4868 // lowering, as well as any jump table information.
4869 SwitchCases.clear();
4870 SwitchCases = SDL.SwitchCases;
4872 JTCases = SDL.JTCases;
4873 BitTestCases.clear();
4874 BitTestCases = SDL.BitTestCases;
4876 // Make sure the root of the DAG is up-to-date.
4877 DAG.setRoot(SDL.getControlRoot());
4879 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4880 // with correct tailcall attribute so that the target can rely on the tailcall
4881 // attribute indicating whether the call is really eligible for tail call
4883 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4886 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4887 DOUT << "Lowered selection DAG:\n";
4890 // Run the DAG combiner in pre-legalize mode.
4891 DAG.Combine(false, *AA);
4893 DOUT << "Optimized lowered selection DAG:\n";
4896 // Second step, hack on the DAG until it only uses operations and types that
4897 // the target supports.
4898 #if 0 // Enable this some day.
4899 DAG.LegalizeTypes();
4900 // Someday even later, enable a dag combine pass here.
4904 DOUT << "Legalized selection DAG:\n";
4907 // Run the DAG combiner in post-legalize mode.
4908 DAG.Combine(true, *AA);
4910 DOUT << "Optimized legalized selection DAG:\n";
4913 if (ViewISelDAGs) DAG.viewGraph();
4915 // Third, instruction select all of the operations to machine code, adding the
4916 // code to the MachineBasicBlock.
4917 InstructionSelectBasicBlock(DAG);
4919 DOUT << "Selected machine code:\n";
4923 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4924 FunctionLoweringInfo &FuncInfo) {
4925 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4927 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4930 // First step, lower LLVM code to some DAG. This DAG may use operations and
4931 // types that are not supported by the target.
4932 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4934 // Second step, emit the lowered DAG as machine code.
4935 CodeGenAndEmitDAG(DAG);
4938 DOUT << "Total amount of phi nodes to update: "
4939 << PHINodesToUpdate.size() << "\n";
4940 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4941 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4942 << ", " << PHINodesToUpdate[i].second << ")\n";);
4944 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4945 // PHI nodes in successors.
4946 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4947 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4948 MachineInstr *PHI = PHINodesToUpdate[i].first;
4949 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4950 "This is not a machine PHI node that we are updating!");
4951 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4953 PHI->addOperand(MachineOperand::CreateMBB(BB));
4958 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4959 // Lower header first, if it wasn't already lowered
4960 if (!BitTestCases[i].Emitted) {
4961 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4963 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4964 // Set the current basic block to the mbb we wish to insert the code into
4965 BB = BitTestCases[i].Parent;
4966 HSDL.setCurrentBasicBlock(BB);
4968 HSDL.visitBitTestHeader(BitTestCases[i]);
4969 HSDAG.setRoot(HSDL.getRoot());
4970 CodeGenAndEmitDAG(HSDAG);
4973 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4974 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4976 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
4977 // Set the current basic block to the mbb we wish to insert the code into
4978 BB = BitTestCases[i].Cases[j].ThisBB;
4979 BSDL.setCurrentBasicBlock(BB);
4982 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4983 BitTestCases[i].Reg,
4984 BitTestCases[i].Cases[j]);
4986 BSDL.visitBitTestCase(BitTestCases[i].Default,
4987 BitTestCases[i].Reg,
4988 BitTestCases[i].Cases[j]);
4991 BSDAG.setRoot(BSDL.getRoot());
4992 CodeGenAndEmitDAG(BSDAG);
4996 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4997 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4998 MachineBasicBlock *PHIBB = PHI->getParent();
4999 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5000 "This is not a machine PHI node that we are updating!");
5001 // This is "default" BB. We have two jumps to it. From "header" BB and
5002 // from last "case" BB.
5003 if (PHIBB == BitTestCases[i].Default) {
5004 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5006 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5007 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5009 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5012 // One of "cases" BB.
5013 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5014 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5015 if (cBB->succ_end() !=
5016 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5017 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5019 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5025 // If the JumpTable record is filled in, then we need to emit a jump table.
5026 // Updating the PHI nodes is tricky in this case, since we need to determine
5027 // whether the PHI is a successor of the range check MBB or the jump table MBB
5028 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5029 // Lower header first, if it wasn't already lowered
5030 if (!JTCases[i].first.Emitted) {
5031 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5033 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5034 // Set the current basic block to the mbb we wish to insert the code into
5035 BB = JTCases[i].first.HeaderBB;
5036 HSDL.setCurrentBasicBlock(BB);
5038 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5039 HSDAG.setRoot(HSDL.getRoot());
5040 CodeGenAndEmitDAG(HSDAG);
5043 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5045 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5046 // Set the current basic block to the mbb we wish to insert the code into
5047 BB = JTCases[i].second.MBB;
5048 JSDL.setCurrentBasicBlock(BB);
5050 JSDL.visitJumpTable(JTCases[i].second);
5051 JSDAG.setRoot(JSDL.getRoot());
5052 CodeGenAndEmitDAG(JSDAG);
5055 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5056 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5057 MachineBasicBlock *PHIBB = PHI->getParent();
5058 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5059 "This is not a machine PHI node that we are updating!");
5060 // "default" BB. We can go there only from header BB.
5061 if (PHIBB == JTCases[i].second.Default) {
5062 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5064 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5066 // JT BB. Just iterate over successors here
5067 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5068 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5070 PHI->addOperand(MachineOperand::CreateMBB(BB));
5075 // If the switch block involved a branch to one of the actual successors, we
5076 // need to update PHI nodes in that block.
5077 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5078 MachineInstr *PHI = PHINodesToUpdate[i].first;
5079 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5080 "This is not a machine PHI node that we are updating!");
5081 if (BB->isSuccessor(PHI->getParent())) {
5082 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5084 PHI->addOperand(MachineOperand::CreateMBB(BB));
5088 // If we generated any switch lowering information, build and codegen any
5089 // additional DAGs necessary.
5090 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5091 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5093 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5095 // Set the current basic block to the mbb we wish to insert the code into
5096 BB = SwitchCases[i].ThisBB;
5097 SDL.setCurrentBasicBlock(BB);
5100 SDL.visitSwitchCase(SwitchCases[i]);
5101 SDAG.setRoot(SDL.getRoot());
5102 CodeGenAndEmitDAG(SDAG);
5104 // Handle any PHI nodes in successors of this chunk, as if we were coming
5105 // from the original BB before switch expansion. Note that PHI nodes can
5106 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5107 // handle them the right number of times.
5108 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5109 for (MachineBasicBlock::iterator Phi = BB->begin();
5110 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5111 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5112 for (unsigned pn = 0; ; ++pn) {
5113 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5114 if (PHINodesToUpdate[pn].first == Phi) {
5115 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5117 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5123 // Don't process RHS if same block as LHS.
5124 if (BB == SwitchCases[i].FalseBB)
5125 SwitchCases[i].FalseBB = 0;
5127 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5128 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5129 SwitchCases[i].FalseBB = 0;
5131 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5136 //===----------------------------------------------------------------------===//
5137 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5138 /// target node in the graph.
5139 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5140 if (ViewSchedDAGs) DAG.viewGraph();
5142 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5146 RegisterScheduler::setDefault(Ctor);
5149 ScheduleDAG *SL = Ctor(this, &DAG, BB);
5152 if (ViewSUnitDAGs) SL->viewGraph();
5158 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5159 return new HazardRecognizer();
5162 //===----------------------------------------------------------------------===//
5163 // Helper functions used by the generated instruction selector.
5164 //===----------------------------------------------------------------------===//
5165 // Calls to these methods are generated by tblgen.
5167 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5168 /// the dag combiner simplified the 255, we still want to match. RHS is the
5169 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5170 /// specified in the .td file (e.g. 255).
5171 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5172 int64_t DesiredMaskS) const {
5173 const APInt &ActualMask = RHS->getAPIntValue();
5174 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5176 // If the actual mask exactly matches, success!
5177 if (ActualMask == DesiredMask)
5180 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5181 if (ActualMask.intersects(~DesiredMask))
5184 // Otherwise, the DAG Combiner may have proven that the value coming in is
5185 // either already zero or is not demanded. Check for known zero input bits.
5186 APInt NeededMask = DesiredMask & ~ActualMask;
5187 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5190 // TODO: check to see if missing bits are just not demanded.
5192 // Otherwise, this pattern doesn't match.
5196 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5197 /// the dag combiner simplified the 255, we still want to match. RHS is the
5198 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5199 /// specified in the .td file (e.g. 255).
5200 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5201 int64_t DesiredMaskS) const {
5202 const APInt &ActualMask = RHS->getAPIntValue();
5203 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5205 // If the actual mask exactly matches, success!
5206 if (ActualMask == DesiredMask)
5209 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5210 if (ActualMask.intersects(~DesiredMask))
5213 // Otherwise, the DAG Combiner may have proven that the value coming in is
5214 // either already zero or is not demanded. Check for known zero input bits.
5215 APInt NeededMask = DesiredMask & ~ActualMask;
5217 APInt KnownZero, KnownOne;
5218 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5220 // If all the missing bits in the or are already known to be set, match!
5221 if ((NeededMask & KnownOne) == NeededMask)
5224 // TODO: check to see if missing bits are just not demanded.
5226 // Otherwise, this pattern doesn't match.
5231 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5232 /// by tblgen. Others should not call it.
5233 void SelectionDAGISel::
5234 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5235 std::vector<SDOperand> InOps;
5236 std::swap(InOps, Ops);
5238 Ops.push_back(InOps[0]); // input chain.
5239 Ops.push_back(InOps[1]); // input asm string.
5241 unsigned i = 2, e = InOps.size();
5242 if (InOps[e-1].getValueType() == MVT::Flag)
5243 --e; // Don't process a flag operand if it is here.
5246 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5247 if ((Flags & 7) != 4 /*MEM*/) {
5248 // Just skip over this operand, copying the operands verbatim.
5249 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5250 i += (Flags >> 3) + 1;
5252 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5253 // Otherwise, this is a memory operand. Ask the target to select it.
5254 std::vector<SDOperand> SelOps;
5255 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5256 cerr << "Could not match memory address. Inline asm failure!\n";
5260 // Add this to the output node.
5261 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5262 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5264 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5269 // Add the flag input back if present.
5270 if (e != InOps.size())
5271 Ops.push_back(InOps.back());
5274 char SelectionDAGISel::ID = 0;