1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/Timer.h"
53 EnableValueProp("enable-value-prop", cl::Hidden);
55 EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
60 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
61 cl::desc("Pop up a window to show dags before the first "
64 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
65 cl::desc("Pop up a window to show dags before legalize types"));
67 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
68 cl::desc("Pop up a window to show dags before legalize"));
70 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before the second "
74 ViewISelDAGs("view-isel-dags", cl::Hidden,
75 cl::desc("Pop up a window to show isel dags as they are selected"));
77 ViewSchedDAGs("view-sched-dags", cl::Hidden,
78 cl::desc("Pop up a window to show sched dags as they are processed"));
80 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
81 cl::desc("Pop up a window to show SUnit dags after they are processed"));
83 static const bool ViewDAGCombine1 = false,
84 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
85 ViewDAGCombine2 = false,
86 ViewISelDAGs = false, ViewSchedDAGs = false,
87 ViewSUnitDAGs = false;
90 //===---------------------------------------------------------------------===//
92 /// RegisterScheduler class - Track the registration of instruction schedulers.
94 //===---------------------------------------------------------------------===//
95 MachinePassRegistry RegisterScheduler::Registry;
97 //===---------------------------------------------------------------------===//
99 /// ISHeuristic command line option for instruction schedulers.
101 //===---------------------------------------------------------------------===//
102 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
103 RegisterPassParser<RegisterScheduler> >
104 ISHeuristic("pre-RA-sched",
105 cl::init(&createDefaultScheduler),
106 cl::desc("Instruction schedulers available (before register"
109 static RegisterScheduler
110 defaultListDAGScheduler("default", " Best scheduler for the target",
111 createDefaultScheduler);
113 namespace { struct SDISelAsmOperandInfo; }
115 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
116 /// insertvalue or extractvalue indices that identify a member, return
117 /// the linearized index of the start of the member.
119 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
120 const unsigned *Indices,
121 const unsigned *IndicesEnd,
122 unsigned CurIndex = 0) {
123 // Base case: We're done.
124 if (Indices && Indices == IndicesEnd)
127 // Given a struct type, recursively traverse the elements.
128 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
129 for (StructType::element_iterator EB = STy->element_begin(),
131 EE = STy->element_end();
133 if (Indices && *Indices == unsigned(EI - EB))
134 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
135 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
138 // Given an array type, recursively traverse the elements.
139 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
140 const Type *EltTy = ATy->getElementType();
141 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
142 if (Indices && *Indices == i)
143 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
144 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
147 // We haven't found the type we're looking for, so keep searching.
151 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
152 /// MVTs that represent all the individual underlying
153 /// non-aggregate types that comprise it.
155 /// If Offsets is non-null, it points to a vector to be filled in
156 /// with the in-memory offsets of each of the individual values.
158 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
159 SmallVectorImpl<MVT> &ValueVTs,
160 SmallVectorImpl<uint64_t> *Offsets = 0,
161 uint64_t StartingOffset = 0) {
162 // Given a struct type, recursively traverse the elements.
163 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
164 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
165 for (StructType::element_iterator EB = STy->element_begin(),
167 EE = STy->element_end();
169 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
170 StartingOffset + SL->getElementOffset(EI - EB));
173 // Given an array type, recursively traverse the elements.
174 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
175 const Type *EltTy = ATy->getElementType();
176 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
177 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
178 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
179 StartingOffset + i * EltSize);
182 // Base case: we can get an MVT for this LLVM IR type.
183 ValueVTs.push_back(TLI.getValueType(Ty));
185 Offsets->push_back(StartingOffset);
189 /// RegsForValue - This struct represents the registers (physical or virtual)
190 /// that a particular set of values is assigned, and the type information about
191 /// the value. The most common situation is to represent one value at a time,
192 /// but struct or array values are handled element-wise as multiple values.
193 /// The splitting of aggregates is performed recursively, so that we never
194 /// have aggregate-typed registers. The values at this point do not necessarily
195 /// have legal types, so each value may require one or more registers of some
198 struct VISIBILITY_HIDDEN RegsForValue {
199 /// TLI - The TargetLowering object.
201 const TargetLowering *TLI;
203 /// ValueVTs - The value types of the values, which may not be legal, and
204 /// may need be promoted or synthesized from one or more registers.
206 SmallVector<MVT, 4> ValueVTs;
208 /// RegVTs - The value types of the registers. This is the same size as
209 /// ValueVTs and it records, for each value, what the type of the assigned
210 /// register or registers are. (Individual values are never synthesized
211 /// from more than one type of register.)
213 /// With virtual registers, the contents of RegVTs is redundant with TLI's
214 /// getRegisterType member function, however when with physical registers
215 /// it is necessary to have a separate record of the types.
217 SmallVector<MVT, 4> RegVTs;
219 /// Regs - This list holds the registers assigned to the values.
220 /// Each legal or promoted value requires one register, and each
221 /// expanded value requires multiple registers.
223 SmallVector<unsigned, 4> Regs;
225 RegsForValue() : TLI(0) {}
227 RegsForValue(const TargetLowering &tli,
228 const SmallVector<unsigned, 4> ®s,
229 MVT regvt, MVT valuevt)
230 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
231 RegsForValue(const TargetLowering &tli,
232 const SmallVector<unsigned, 4> ®s,
233 const SmallVector<MVT, 4> ®vts,
234 const SmallVector<MVT, 4> &valuevts)
235 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
236 RegsForValue(const TargetLowering &tli,
237 unsigned Reg, const Type *Ty) : TLI(&tli) {
238 ComputeValueVTs(tli, Ty, ValueVTs);
240 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
241 MVT ValueVT = ValueVTs[Value];
242 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
243 MVT RegisterVT = TLI->getRegisterType(ValueVT);
244 for (unsigned i = 0; i != NumRegs; ++i)
245 Regs.push_back(Reg + i);
246 RegVTs.push_back(RegisterVT);
251 /// append - Add the specified values to this one.
252 void append(const RegsForValue &RHS) {
254 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
255 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
256 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
260 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
261 /// this value and returns the result as a ValueVTs value. This uses
262 /// Chain/Flag as the input and updates them for the output Chain/Flag.
263 /// If the Flag pointer is NULL, no flag is used.
264 SDValue getCopyFromRegs(SelectionDAG &DAG,
265 SDValue &Chain, SDValue *Flag) const;
267 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
268 /// specified value into the registers specified by this object. This uses
269 /// Chain/Flag as the input and updates them for the output Chain/Flag.
270 /// If the Flag pointer is NULL, no flag is used.
271 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
272 SDValue &Chain, SDValue *Flag) const;
274 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
275 /// operand list. This adds the code marker and includes the number of
276 /// values added into it.
277 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
278 std::vector<SDValue> &Ops) const;
283 //===--------------------------------------------------------------------===//
284 /// createDefaultScheduler - This creates an instruction scheduler appropriate
286 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
288 MachineBasicBlock *BB,
290 TargetLowering &TLI = IS->getTargetLowering();
292 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
293 return createTDListDAGScheduler(IS, DAG, BB, Fast);
295 assert(TLI.getSchedulingPreference() ==
296 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
297 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
302 //===--------------------------------------------------------------------===//
303 /// FunctionLoweringInfo - This contains information that is global to a
304 /// function that is used when lowering a region of the function.
305 class FunctionLoweringInfo {
310 MachineRegisterInfo &RegInfo;
312 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
314 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
315 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
317 /// ValueMap - Since we emit code for the function a basic block at a time,
318 /// we must remember which virtual registers hold the values for
319 /// cross-basic-block values.
320 DenseMap<const Value*, unsigned> ValueMap;
322 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
323 /// the entry block. This allows the allocas to be efficiently referenced
324 /// anywhere in the function.
325 std::map<const AllocaInst*, int> StaticAllocaMap;
328 SmallSet<Instruction*, 8> CatchInfoLost;
329 SmallSet<Instruction*, 8> CatchInfoFound;
332 unsigned MakeReg(MVT VT) {
333 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
336 /// isExportedInst - Return true if the specified value is an instruction
337 /// exported from its block.
338 bool isExportedInst(const Value *V) {
339 return ValueMap.count(V);
342 unsigned CreateRegForValue(const Value *V);
344 unsigned InitializeRegForValue(const Value *V) {
345 unsigned &R = ValueMap[V];
346 assert(R == 0 && "Already initialized this value register!");
347 return R = CreateRegForValue(V);
351 unsigned NumSignBits;
352 APInt KnownOne, KnownZero;
353 LiveOutInfo() : NumSignBits(0) {}
356 /// LiveOutRegInfo - Information about live out vregs, indexed by their
357 /// register number offset by 'FirstVirtualRegister'.
358 std::vector<LiveOutInfo> LiveOutRegInfo;
362 /// isSelector - Return true if this instruction is a call to the
363 /// eh.selector intrinsic.
364 static bool isSelector(Instruction *I) {
365 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
366 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
367 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
371 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
372 /// PHI nodes or outside of the basic block that defines it, or used by a
373 /// switch or atomic instruction, which may expand to multiple basic blocks.
374 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
375 if (isa<PHINode>(I)) return true;
376 BasicBlock *BB = I->getParent();
377 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
378 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
379 // FIXME: Remove switchinst special case.
380 isa<SwitchInst>(*UI))
385 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
386 /// entry block, return true. This includes arguments used by switches, since
387 /// the switch may expand into multiple basic blocks.
388 static bool isOnlyUsedInEntryBlock(Argument *A) {
389 BasicBlock *Entry = A->getParent()->begin();
390 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
391 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
392 return false; // Use not in entry block.
396 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
397 Function &fn, MachineFunction &mf)
398 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
400 // Create a vreg for each argument register that is not dead and is used
401 // outside of the entry block for the function.
402 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
404 if (!isOnlyUsedInEntryBlock(AI))
405 InitializeRegForValue(AI);
407 // Initialize the mapping of values to registers. This is only set up for
408 // instruction values that are used outside of the block that defines
410 Function::iterator BB = Fn.begin(), EB = Fn.end();
411 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
412 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
413 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
414 const Type *Ty = AI->getAllocatedType();
415 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
417 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
420 TySize *= CUI->getZExtValue(); // Get total allocated size.
421 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
422 StaticAllocaMap[AI] =
423 MF.getFrameInfo()->CreateStackObject(TySize, Align);
426 for (; BB != EB; ++BB)
427 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
428 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
429 if (!isa<AllocaInst>(I) ||
430 !StaticAllocaMap.count(cast<AllocaInst>(I)))
431 InitializeRegForValue(I);
433 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
434 // also creates the initial PHI MachineInstrs, though none of the input
435 // operands are populated.
436 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
437 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
441 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
444 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
445 if (PN->use_empty()) continue;
447 MVT VT = TLI.getValueType(PN->getType());
448 unsigned NumRegisters = TLI.getNumRegisters(VT);
449 unsigned PHIReg = ValueMap[PN];
450 assert(PHIReg && "PHI node does not have an assigned virtual register!");
451 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
452 for (unsigned i = 0; i != NumRegisters; ++i)
453 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
458 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
459 /// the correctly promoted or expanded types. Assign these registers
460 /// consecutive vreg numbers and return the first assigned number.
462 /// In the case that the given value has struct or array type, this function
463 /// will assign registers for each member or element.
465 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
466 SmallVector<MVT, 4> ValueVTs;
467 ComputeValueVTs(TLI, V->getType(), ValueVTs);
469 unsigned FirstReg = 0;
470 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
471 MVT ValueVT = ValueVTs[Value];
472 MVT RegisterVT = TLI.getRegisterType(ValueVT);
474 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
475 for (unsigned i = 0; i != NumRegs; ++i) {
476 unsigned R = MakeReg(RegisterVT);
477 if (!FirstReg) FirstReg = R;
483 //===----------------------------------------------------------------------===//
484 /// SelectionDAGLowering - This is the common target-independent lowering
485 /// implementation that is parameterized by a TargetLowering object.
486 /// Also, targets can overload any lowering method.
489 class SelectionDAGLowering {
490 MachineBasicBlock *CurMBB;
492 DenseMap<const Value*, SDValue> NodeMap;
494 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
495 /// them up and then emit token factor nodes when possible. This allows us to
496 /// get simple disambiguation between loads without worrying about alias
498 SmallVector<SDValue, 8> PendingLoads;
500 /// PendingExports - CopyToReg nodes that copy values to virtual registers
501 /// for export to other blocks need to be emitted before any terminator
502 /// instruction, but they have no other ordering requirements. We bunch them
503 /// up and the emit a single tokenfactor for them just before terminator
505 std::vector<SDValue> PendingExports;
507 /// Case - A struct to record the Value for a switch case, and the
508 /// case's target basic block.
512 MachineBasicBlock* BB;
514 Case() : Low(0), High(0), BB(0) { }
515 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
516 Low(low), High(high), BB(bb) { }
517 uint64_t size() const {
518 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
519 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
520 return (rHigh - rLow + 1ULL);
526 MachineBasicBlock* BB;
529 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
530 Mask(mask), BB(bb), Bits(bits) { }
533 typedef std::vector<Case> CaseVector;
534 typedef std::vector<CaseBits> CaseBitsVector;
535 typedef CaseVector::iterator CaseItr;
536 typedef std::pair<CaseItr, CaseItr> CaseRange;
538 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
539 /// of conditional branches.
541 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
542 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
544 /// CaseBB - The MBB in which to emit the compare and branch
545 MachineBasicBlock *CaseBB;
546 /// LT, GE - If nonzero, we know the current case value must be less-than or
547 /// greater-than-or-equal-to these Constants.
550 /// Range - A pair of iterators representing the range of case values to be
551 /// processed at this point in the binary search tree.
555 typedef std::vector<CaseRec> CaseRecVector;
557 /// The comparison function for sorting the switch case values in the vector.
558 /// WARNING: Case ranges should be disjoint!
560 bool operator () (const Case& C1, const Case& C2) {
561 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
562 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
563 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
564 return CI1->getValue().slt(CI2->getValue());
569 bool operator () (const CaseBits& C1, const CaseBits& C2) {
570 return C1.Bits > C2.Bits;
574 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
577 // TLI - This is information that describes the available target features we
578 // need for lowering. This indicates when operations are unavailable,
579 // implemented with a libcall, etc.
582 const TargetData *TD;
585 /// SwitchCases - Vector of CaseBlock structures used to communicate
586 /// SwitchInst code generation information.
587 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
588 /// JTCases - Vector of JumpTable structures used to communicate
589 /// SwitchInst code generation information.
590 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
591 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
593 /// FuncInfo - Information about the function as a whole.
595 FunctionLoweringInfo &FuncInfo;
597 /// GCI - Garbage collection metadata for the function.
598 CollectorMetadata *GCI;
600 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
602 FunctionLoweringInfo &funcinfo,
603 CollectorMetadata *gci)
604 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
605 FuncInfo(funcinfo), GCI(gci) {
608 /// getRoot - Return the current virtual root of the Selection DAG,
609 /// flushing any PendingLoad items. This must be done before emitting
610 /// a store or any other node that may need to be ordered after any
611 /// prior load instructions.
614 if (PendingLoads.empty())
615 return DAG.getRoot();
617 if (PendingLoads.size() == 1) {
618 SDValue Root = PendingLoads[0];
620 PendingLoads.clear();
624 // Otherwise, we have to make a token factor node.
625 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
626 &PendingLoads[0], PendingLoads.size());
627 PendingLoads.clear();
632 /// getControlRoot - Similar to getRoot, but instead of flushing all the
633 /// PendingLoad items, flush all the PendingExports items. It is necessary
634 /// to do this before emitting a terminator instruction.
636 SDValue getControlRoot() {
637 SDValue Root = DAG.getRoot();
639 if (PendingExports.empty())
642 // Turn all of the CopyToReg chains into one factored node.
643 if (Root.getOpcode() != ISD::EntryToken) {
644 unsigned i = 0, e = PendingExports.size();
645 for (; i != e; ++i) {
646 assert(PendingExports[i].Val->getNumOperands() > 1);
647 if (PendingExports[i].Val->getOperand(0) == Root)
648 break; // Don't add the root if we already indirectly depend on it.
652 PendingExports.push_back(Root);
655 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
657 PendingExports.size());
658 PendingExports.clear();
663 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
665 void visit(Instruction &I) { visit(I.getOpcode(), I); }
667 void visit(unsigned Opcode, User &I) {
668 // Note: this doesn't use InstVisitor, because it has to work with
669 // ConstantExpr's in addition to instructions.
671 default: assert(0 && "Unknown instruction type encountered!");
673 // Build the switch statement using the Instruction.def file.
674 #define HANDLE_INST(NUM, OPCODE, CLASS) \
675 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
676 #include "llvm/Instruction.def"
680 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
682 SDValue getValue(const Value *V);
684 void setValue(const Value *V, SDValue NewN) {
685 SDValue &N = NodeMap[V];
686 assert(N.Val == 0 && "Already set a value for this node!");
690 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
691 std::set<unsigned> &OutputRegs,
692 std::set<unsigned> &InputRegs);
694 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
695 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
697 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
698 void ExportFromCurrentBlock(Value *V);
699 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
700 MachineBasicBlock *LandingPad = NULL);
702 // Terminator instructions.
703 void visitRet(ReturnInst &I);
704 void visitBr(BranchInst &I);
705 void visitSwitch(SwitchInst &I);
706 void visitUnreachable(UnreachableInst &I) { /* noop */ }
708 // Helpers for visitSwitch
709 bool handleSmallSwitchRange(CaseRec& CR,
710 CaseRecVector& WorkList,
712 MachineBasicBlock* Default);
713 bool handleJTSwitchCase(CaseRec& CR,
714 CaseRecVector& WorkList,
716 MachineBasicBlock* Default);
717 bool handleBTSplitSwitchCase(CaseRec& CR,
718 CaseRecVector& WorkList,
720 MachineBasicBlock* Default);
721 bool handleBitTestsSwitchCase(CaseRec& CR,
722 CaseRecVector& WorkList,
724 MachineBasicBlock* Default);
725 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
726 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
727 void visitBitTestCase(MachineBasicBlock* NextMBB,
729 SelectionDAGISel::BitTestCase &B);
730 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
731 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
732 SelectionDAGISel::JumpTableHeader &JTH);
734 // These all get lowered before this pass.
735 void visitInvoke(InvokeInst &I);
736 void visitUnwind(UnwindInst &I);
738 void visitBinary(User &I, unsigned OpCode);
739 void visitShift(User &I, unsigned Opcode);
740 void visitAdd(User &I) {
741 if (I.getType()->isFPOrFPVector())
742 visitBinary(I, ISD::FADD);
744 visitBinary(I, ISD::ADD);
746 void visitSub(User &I);
747 void visitMul(User &I) {
748 if (I.getType()->isFPOrFPVector())
749 visitBinary(I, ISD::FMUL);
751 visitBinary(I, ISD::MUL);
753 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
754 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
755 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
756 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
757 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
758 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
759 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
760 void visitOr (User &I) { visitBinary(I, ISD::OR); }
761 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
762 void visitShl (User &I) { visitShift(I, ISD::SHL); }
763 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
764 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
765 void visitICmp(User &I);
766 void visitFCmp(User &I);
767 void visitVICmp(User &I);
768 void visitVFCmp(User &I);
769 // Visit the conversion instructions
770 void visitTrunc(User &I);
771 void visitZExt(User &I);
772 void visitSExt(User &I);
773 void visitFPTrunc(User &I);
774 void visitFPExt(User &I);
775 void visitFPToUI(User &I);
776 void visitFPToSI(User &I);
777 void visitUIToFP(User &I);
778 void visitSIToFP(User &I);
779 void visitPtrToInt(User &I);
780 void visitIntToPtr(User &I);
781 void visitBitCast(User &I);
783 void visitExtractElement(User &I);
784 void visitInsertElement(User &I);
785 void visitShuffleVector(User &I);
787 void visitExtractValue(ExtractValueInst &I);
788 void visitInsertValue(InsertValueInst &I);
790 void visitGetElementPtr(User &I);
791 void visitSelect(User &I);
793 void visitMalloc(MallocInst &I);
794 void visitFree(FreeInst &I);
795 void visitAlloca(AllocaInst &I);
796 void visitLoad(LoadInst &I);
797 void visitStore(StoreInst &I);
798 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
799 void visitCall(CallInst &I);
800 void visitInlineAsm(CallSite CS);
801 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
802 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
804 void visitVAStart(CallInst &I);
805 void visitVAArg(VAArgInst &I);
806 void visitVAEnd(CallInst &I);
807 void visitVACopy(CallInst &I);
809 void visitUserOp1(Instruction &I) {
810 assert(0 && "UserOp1 should not exist at instruction selection time!");
813 void visitUserOp2(Instruction &I) {
814 assert(0 && "UserOp2 should not exist at instruction selection time!");
819 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
822 } // end namespace llvm
825 /// getCopyFromParts - Create a value that contains the specified legal parts
826 /// combined into the value they represent. If the parts combine to a type
827 /// larger then ValueVT then AssertOp can be used to specify whether the extra
828 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
829 /// (ISD::AssertSext).
830 static SDValue getCopyFromParts(SelectionDAG &DAG,
831 const SDValue *Parts,
835 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
836 assert(NumParts > 0 && "No parts to assemble!");
837 TargetLowering &TLI = DAG.getTargetLoweringInfo();
838 SDValue Val = Parts[0];
841 // Assemble the value from multiple parts.
842 if (!ValueVT.isVector()) {
843 unsigned PartBits = PartVT.getSizeInBits();
844 unsigned ValueBits = ValueVT.getSizeInBits();
846 // Assemble the power of 2 part.
847 unsigned RoundParts = NumParts & (NumParts - 1) ?
848 1 << Log2_32(NumParts) : NumParts;
849 unsigned RoundBits = PartBits * RoundParts;
850 MVT RoundVT = RoundBits == ValueBits ?
851 ValueVT : MVT::getIntegerVT(RoundBits);
854 if (RoundParts > 2) {
855 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
856 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
857 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
863 if (TLI.isBigEndian())
865 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
867 if (RoundParts < NumParts) {
868 // Assemble the trailing non-power-of-2 part.
869 unsigned OddParts = NumParts - RoundParts;
870 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
871 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
873 // Combine the round and odd parts.
875 if (TLI.isBigEndian())
877 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
878 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
879 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
880 DAG.getConstant(Lo.getValueType().getSizeInBits(),
881 TLI.getShiftAmountTy()));
882 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
883 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
886 // Handle a multi-element vector.
887 MVT IntermediateVT, RegisterVT;
888 unsigned NumIntermediates;
890 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
892 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
893 NumParts = NumRegs; // Silence a compiler warning.
894 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
895 assert(RegisterVT == Parts[0].getValueType() &&
896 "Part type doesn't match part!");
898 // Assemble the parts into intermediate operands.
899 SmallVector<SDValue, 8> Ops(NumIntermediates);
900 if (NumIntermediates == NumParts) {
901 // If the register was not expanded, truncate or copy the value,
903 for (unsigned i = 0; i != NumParts; ++i)
904 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
905 PartVT, IntermediateVT);
906 } else if (NumParts > 0) {
907 // If the intermediate type was expanded, build the intermediate operands
909 assert(NumParts % NumIntermediates == 0 &&
910 "Must expand into a divisible number of parts!");
911 unsigned Factor = NumParts / NumIntermediates;
912 for (unsigned i = 0; i != NumIntermediates; ++i)
913 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
914 PartVT, IntermediateVT);
917 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
919 Val = DAG.getNode(IntermediateVT.isVector() ?
920 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
921 ValueVT, &Ops[0], NumIntermediates);
925 // There is now one part, held in Val. Correct it to match ValueVT.
926 PartVT = Val.getValueType();
928 if (PartVT == ValueVT)
931 if (PartVT.isVector()) {
932 assert(ValueVT.isVector() && "Unknown vector conversion!");
933 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
936 if (ValueVT.isVector()) {
937 assert(ValueVT.getVectorElementType() == PartVT &&
938 ValueVT.getVectorNumElements() == 1 &&
939 "Only trivial scalar-to-vector conversions should get here!");
940 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
943 if (PartVT.isInteger() &&
944 ValueVT.isInteger()) {
945 if (ValueVT.bitsLT(PartVT)) {
946 // For a truncate, see if we have any information to
947 // indicate whether the truncated bits will always be
948 // zero or sign-extension.
949 if (AssertOp != ISD::DELETED_NODE)
950 Val = DAG.getNode(AssertOp, PartVT, Val,
951 DAG.getValueType(ValueVT));
952 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
954 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
958 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
959 if (ValueVT.bitsLT(Val.getValueType()))
960 // FP_ROUND's are always exact here.
961 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
962 DAG.getIntPtrConstant(1));
963 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
966 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
967 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
969 assert(0 && "Unknown mismatch!");
973 /// getCopyToParts - Create a series of nodes that contain the specified value
974 /// split into legal parts. If the parts contain more bits than Val, then, for
975 /// integers, ExtendKind can be used to specify how to generate the extra bits.
976 static void getCopyToParts(SelectionDAG &DAG,
981 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
982 TargetLowering &TLI = DAG.getTargetLoweringInfo();
983 MVT PtrVT = TLI.getPointerTy();
984 MVT ValueVT = Val.getValueType();
985 unsigned PartBits = PartVT.getSizeInBits();
986 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
991 if (!ValueVT.isVector()) {
992 if (PartVT == ValueVT) {
993 assert(NumParts == 1 && "No-op copy with multiple parts!");
998 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
999 // If the parts cover more bits than the value has, promote the value.
1000 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
1001 assert(NumParts == 1 && "Do not know what to promote to!");
1002 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
1003 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
1004 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1005 Val = DAG.getNode(ExtendKind, ValueVT, Val);
1007 assert(0 && "Unknown mismatch!");
1009 } else if (PartBits == ValueVT.getSizeInBits()) {
1010 // Different types of the same size.
1011 assert(NumParts == 1 && PartVT != ValueVT);
1012 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1013 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
1014 // If the parts cover less bits than value has, truncate the value.
1015 if (PartVT.isInteger() && ValueVT.isInteger()) {
1016 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1017 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1019 assert(0 && "Unknown mismatch!");
1023 // The value may have changed - recompute ValueVT.
1024 ValueVT = Val.getValueType();
1025 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1026 "Failed to tile the value with PartVT!");
1028 if (NumParts == 1) {
1029 assert(PartVT == ValueVT && "Type conversion failed!");
1034 // Expand the value into multiple parts.
1035 if (NumParts & (NumParts - 1)) {
1036 // The number of parts is not a power of 2. Split off and copy the tail.
1037 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1038 "Do not know what to expand to!");
1039 unsigned RoundParts = 1 << Log2_32(NumParts);
1040 unsigned RoundBits = RoundParts * PartBits;
1041 unsigned OddParts = NumParts - RoundParts;
1042 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1043 DAG.getConstant(RoundBits,
1044 TLI.getShiftAmountTy()));
1045 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1046 if (TLI.isBigEndian())
1047 // The odd parts were reversed by getCopyToParts - unreverse them.
1048 std::reverse(Parts + RoundParts, Parts + NumParts);
1049 NumParts = RoundParts;
1050 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1051 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1054 // The number of parts is a power of 2. Repeatedly bisect the value using
1056 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1057 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1059 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1060 for (unsigned i = 0; i < NumParts; i += StepSize) {
1061 unsigned ThisBits = StepSize * PartBits / 2;
1062 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1063 SDValue &Part0 = Parts[i];
1064 SDValue &Part1 = Parts[i+StepSize/2];
1066 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1067 DAG.getConstant(1, PtrVT));
1068 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1069 DAG.getConstant(0, PtrVT));
1071 if (ThisBits == PartBits && ThisVT != PartVT) {
1072 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1073 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1078 if (TLI.isBigEndian())
1079 std::reverse(Parts, Parts + NumParts);
1085 if (NumParts == 1) {
1086 if (PartVT != ValueVT) {
1087 if (PartVT.isVector()) {
1088 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1090 assert(ValueVT.getVectorElementType() == PartVT &&
1091 ValueVT.getVectorNumElements() == 1 &&
1092 "Only trivial vector-to-scalar conversions should get here!");
1093 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1094 DAG.getConstant(0, PtrVT));
1102 // Handle a multi-element vector.
1103 MVT IntermediateVT, RegisterVT;
1104 unsigned NumIntermediates;
1106 DAG.getTargetLoweringInfo()
1107 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1109 unsigned NumElements = ValueVT.getVectorNumElements();
1111 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1112 NumParts = NumRegs; // Silence a compiler warning.
1113 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1115 // Split the vector into intermediate operands.
1116 SmallVector<SDValue, 8> Ops(NumIntermediates);
1117 for (unsigned i = 0; i != NumIntermediates; ++i)
1118 if (IntermediateVT.isVector())
1119 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1120 IntermediateVT, Val,
1121 DAG.getConstant(i * (NumElements / NumIntermediates),
1124 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1125 IntermediateVT, Val,
1126 DAG.getConstant(i, PtrVT));
1128 // Split the intermediate operands into legal parts.
1129 if (NumParts == NumIntermediates) {
1130 // If the register was not expanded, promote or copy the value,
1132 for (unsigned i = 0; i != NumParts; ++i)
1133 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1134 } else if (NumParts > 0) {
1135 // If the intermediate type was expanded, split each the value into
1137 assert(NumParts % NumIntermediates == 0 &&
1138 "Must expand into a divisible number of parts!");
1139 unsigned Factor = NumParts / NumIntermediates;
1140 for (unsigned i = 0; i != NumIntermediates; ++i)
1141 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1146 SDValue SelectionDAGLowering::getValue(const Value *V) {
1147 SDValue &N = NodeMap[V];
1148 if (N.Val) return N;
1150 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1151 MVT VT = TLI.getValueType(V->getType(), true);
1153 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1154 return N = DAG.getConstant(CI->getValue(), VT);
1156 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1157 return N = DAG.getGlobalAddress(GV, VT);
1159 if (isa<ConstantPointerNull>(C))
1160 return N = DAG.getConstant(0, TLI.getPointerTy());
1162 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1163 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1165 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1166 !V->getType()->isAggregateType())
1167 return N = DAG.getNode(ISD::UNDEF, VT);
1169 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1170 visit(CE->getOpcode(), *CE);
1171 SDValue N1 = NodeMap[V];
1172 assert(N1.Val && "visit didn't populate the ValueMap!");
1176 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1177 SmallVector<SDValue, 4> Constants;
1178 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1180 SDNode *Val = getValue(*OI).Val;
1181 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1182 Constants.push_back(SDValue(Val, i));
1184 return DAG.getMergeValues(&Constants[0], Constants.size());
1187 if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) {
1188 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1189 "Unknown array constant!");
1190 unsigned NumElts = ATy->getNumElements();
1192 return SDValue(); // empty array
1193 MVT EltVT = TLI.getValueType(ATy->getElementType());
1194 SmallVector<SDValue, 4> Constants(NumElts);
1195 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1196 if (isa<UndefValue>(C))
1197 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1198 else if (EltVT.isFloatingPoint())
1199 Constants[i] = DAG.getConstantFP(0, EltVT);
1201 Constants[i] = DAG.getConstant(0, EltVT);
1203 return DAG.getMergeValues(&Constants[0], Constants.size());
1206 if (const StructType *STy = dyn_cast<StructType>(C->getType())) {
1207 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1208 "Unknown struct constant!");
1209 unsigned NumElts = STy->getNumElements();
1211 return SDValue(); // empty struct
1212 SmallVector<SDValue, 4> Constants(NumElts);
1213 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1214 MVT EltVT = TLI.getValueType(STy->getElementType(i));
1215 if (isa<UndefValue>(C))
1216 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1217 else if (EltVT.isFloatingPoint())
1218 Constants[i] = DAG.getConstantFP(0, EltVT);
1220 Constants[i] = DAG.getConstant(0, EltVT);
1222 return DAG.getMergeValues(&Constants[0], Constants.size());
1225 const VectorType *VecTy = cast<VectorType>(V->getType());
1226 unsigned NumElements = VecTy->getNumElements();
1228 // Now that we know the number and type of the elements, get that number of
1229 // elements into the Ops array based on what kind of constant it is.
1230 SmallVector<SDValue, 16> Ops;
1231 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1232 for (unsigned i = 0; i != NumElements; ++i)
1233 Ops.push_back(getValue(CP->getOperand(i)));
1235 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1236 "Unknown vector constant!");
1237 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1240 if (isa<UndefValue>(C))
1241 Op = DAG.getNode(ISD::UNDEF, EltVT);
1242 else if (EltVT.isFloatingPoint())
1243 Op = DAG.getConstantFP(0, EltVT);
1245 Op = DAG.getConstant(0, EltVT);
1246 Ops.assign(NumElements, Op);
1249 // Create a BUILD_VECTOR node.
1250 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1253 // If this is a static alloca, generate it as the frameindex instead of
1255 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1256 std::map<const AllocaInst*, int>::iterator SI =
1257 FuncInfo.StaticAllocaMap.find(AI);
1258 if (SI != FuncInfo.StaticAllocaMap.end())
1259 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1262 unsigned InReg = FuncInfo.ValueMap[V];
1263 assert(InReg && "Value not in map!");
1265 RegsForValue RFV(TLI, InReg, V->getType());
1266 SDValue Chain = DAG.getEntryNode();
1267 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1271 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1272 if (I.getNumOperands() == 0) {
1273 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1277 SmallVector<SDValue, 8> NewValues;
1278 NewValues.push_back(getControlRoot());
1279 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1280 SDValue RetOp = getValue(I.getOperand(i));
1282 SmallVector<MVT, 4> ValueVTs;
1283 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1284 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1285 MVT VT = ValueVTs[j];
1287 // FIXME: C calling convention requires the return type to be promoted to
1288 // at least 32-bit. But this is not necessary for non-C calling conventions.
1289 if (VT.isInteger()) {
1290 MVT MinVT = TLI.getRegisterType(MVT::i32);
1291 if (VT.bitsLT(MinVT))
1295 unsigned NumParts = TLI.getNumRegisters(VT);
1296 MVT PartVT = TLI.getRegisterType(VT);
1297 SmallVector<SDValue, 4> Parts(NumParts);
1298 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1300 const Function *F = I.getParent()->getParent();
1301 if (F->paramHasAttr(0, ParamAttr::SExt))
1302 ExtendKind = ISD::SIGN_EXTEND;
1303 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1304 ExtendKind = ISD::ZERO_EXTEND;
1306 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
1307 &Parts[0], NumParts, PartVT, ExtendKind);
1309 for (unsigned i = 0; i < NumParts; ++i) {
1310 NewValues.push_back(Parts[i]);
1311 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1315 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1316 &NewValues[0], NewValues.size()));
1319 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1320 /// the current basic block, add it to ValueMap now so that we'll get a
1322 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1323 // No need to export constants.
1324 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1326 // Already exported?
1327 if (FuncInfo.isExportedInst(V)) return;
1329 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1330 CopyValueToVirtualRegister(V, Reg);
1333 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1334 const BasicBlock *FromBB) {
1335 // The operands of the setcc have to be in this block. We don't know
1336 // how to export them from some other block.
1337 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1338 // Can export from current BB.
1339 if (VI->getParent() == FromBB)
1342 // Is already exported, noop.
1343 return FuncInfo.isExportedInst(V);
1346 // If this is an argument, we can export it if the BB is the entry block or
1347 // if it is already exported.
1348 if (isa<Argument>(V)) {
1349 if (FromBB == &FromBB->getParent()->getEntryBlock())
1352 // Otherwise, can only export this if it is already exported.
1353 return FuncInfo.isExportedInst(V);
1356 // Otherwise, constants can always be exported.
1360 static bool InBlock(const Value *V, const BasicBlock *BB) {
1361 if (const Instruction *I = dyn_cast<Instruction>(V))
1362 return I->getParent() == BB;
1366 /// FindMergedConditions - If Cond is an expression like
1367 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1368 MachineBasicBlock *TBB,
1369 MachineBasicBlock *FBB,
1370 MachineBasicBlock *CurBB,
1372 // If this node is not part of the or/and tree, emit it as a branch.
1373 Instruction *BOp = dyn_cast<Instruction>(Cond);
1375 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1376 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1377 BOp->getParent() != CurBB->getBasicBlock() ||
1378 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1379 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1380 const BasicBlock *BB = CurBB->getBasicBlock();
1382 // If the leaf of the tree is a comparison, merge the condition into
1384 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1385 // The operands of the cmp have to be in this block. We don't know
1386 // how to export them from some other block. If this is the first block
1387 // of the sequence, no exporting is needed.
1389 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1390 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1391 BOp = cast<Instruction>(Cond);
1392 ISD::CondCode Condition;
1393 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1394 switch (IC->getPredicate()) {
1395 default: assert(0 && "Unknown icmp predicate opcode!");
1396 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1397 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1398 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1399 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1400 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1401 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1402 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1403 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1404 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1405 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1407 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1408 ISD::CondCode FPC, FOC;
1409 switch (FC->getPredicate()) {
1410 default: assert(0 && "Unknown fcmp predicate opcode!");
1411 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1412 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1413 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1414 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1415 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1416 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1417 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1418 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1419 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1420 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1421 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1422 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1423 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1424 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1425 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1426 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1428 if (FiniteOnlyFPMath())
1433 Condition = ISD::SETEQ; // silence warning.
1434 assert(0 && "Unknown compare instruction");
1437 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1438 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1439 SwitchCases.push_back(CB);
1443 // Create a CaseBlock record representing this branch.
1444 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1445 NULL, TBB, FBB, CurBB);
1446 SwitchCases.push_back(CB);
1451 // Create TmpBB after CurBB.
1452 MachineFunction::iterator BBI = CurBB;
1453 MachineFunction &MF = DAG.getMachineFunction();
1454 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1455 CurBB->getParent()->insert(++BBI, TmpBB);
1457 if (Opc == Instruction::Or) {
1458 // Codegen X | Y as:
1466 // Emit the LHS condition.
1467 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1469 // Emit the RHS condition into TmpBB.
1470 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1472 assert(Opc == Instruction::And && "Unknown merge op!");
1473 // Codegen X & Y as:
1480 // This requires creation of TmpBB after CurBB.
1482 // Emit the LHS condition.
1483 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1485 // Emit the RHS condition into TmpBB.
1486 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1490 /// If the set of cases should be emitted as a series of branches, return true.
1491 /// If we should emit this as a bunch of and/or'd together conditions, return
1494 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1495 if (Cases.size() != 2) return true;
1497 // If this is two comparisons of the same values or'd or and'd together, they
1498 // will get folded into a single comparison, so don't emit two blocks.
1499 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1500 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1501 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1502 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1509 void SelectionDAGLowering::visitBr(BranchInst &I) {
1510 // Update machine-CFG edges.
1511 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1513 // Figure out which block is immediately after the current one.
1514 MachineBasicBlock *NextBlock = 0;
1515 MachineFunction::iterator BBI = CurMBB;
1516 if (++BBI != CurMBB->getParent()->end())
1519 if (I.isUnconditional()) {
1520 // Update machine-CFG edges.
1521 CurMBB->addSuccessor(Succ0MBB);
1523 // If this is not a fall-through branch, emit the branch.
1524 if (Succ0MBB != NextBlock)
1525 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1526 DAG.getBasicBlock(Succ0MBB)));
1530 // If this condition is one of the special cases we handle, do special stuff
1532 Value *CondVal = I.getCondition();
1533 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1535 // If this is a series of conditions that are or'd or and'd together, emit
1536 // this as a sequence of branches instead of setcc's with and/or operations.
1537 // For example, instead of something like:
1550 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1551 if (BOp->hasOneUse() &&
1552 (BOp->getOpcode() == Instruction::And ||
1553 BOp->getOpcode() == Instruction::Or)) {
1554 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1555 // If the compares in later blocks need to use values not currently
1556 // exported from this block, export them now. This block should always
1557 // be the first entry.
1558 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1560 // Allow some cases to be rejected.
1561 if (ShouldEmitAsBranches(SwitchCases)) {
1562 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1563 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1564 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1567 // Emit the branch for this block.
1568 visitSwitchCase(SwitchCases[0]);
1569 SwitchCases.erase(SwitchCases.begin());
1573 // Okay, we decided not to do this, remove any inserted MBB's and clear
1575 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1576 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1578 SwitchCases.clear();
1582 // Create a CaseBlock record representing this branch.
1583 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1584 NULL, Succ0MBB, Succ1MBB, CurMBB);
1585 // Use visitSwitchCase to actually insert the fast branch sequence for this
1587 visitSwitchCase(CB);
1590 /// visitSwitchCase - Emits the necessary code to represent a single node in
1591 /// the binary search tree resulting from lowering a switch instruction.
1592 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1594 SDValue CondLHS = getValue(CB.CmpLHS);
1596 // Build the setcc now.
1597 if (CB.CmpMHS == NULL) {
1598 // Fold "(X == true)" to X and "(X == false)" to !X to
1599 // handle common cases produced by branch lowering.
1600 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1602 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1603 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1604 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1606 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1608 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1610 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1611 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1613 SDValue CmpOp = getValue(CB.CmpMHS);
1614 MVT VT = CmpOp.getValueType();
1616 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1617 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1619 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1620 Cond = DAG.getSetCC(MVT::i1, SUB,
1621 DAG.getConstant(High-Low, VT), ISD::SETULE);
1625 // Update successor info
1626 CurMBB->addSuccessor(CB.TrueBB);
1627 CurMBB->addSuccessor(CB.FalseBB);
1629 // Set NextBlock to be the MBB immediately after the current one, if any.
1630 // This is used to avoid emitting unnecessary branches to the next block.
1631 MachineBasicBlock *NextBlock = 0;
1632 MachineFunction::iterator BBI = CurMBB;
1633 if (++BBI != CurMBB->getParent()->end())
1636 // If the lhs block is the next block, invert the condition so that we can
1637 // fall through to the lhs instead of the rhs block.
1638 if (CB.TrueBB == NextBlock) {
1639 std::swap(CB.TrueBB, CB.FalseBB);
1640 SDValue True = DAG.getConstant(1, Cond.getValueType());
1641 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1643 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1644 DAG.getBasicBlock(CB.TrueBB));
1645 if (CB.FalseBB == NextBlock)
1646 DAG.setRoot(BrCond);
1648 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1649 DAG.getBasicBlock(CB.FalseBB)));
1652 /// visitJumpTable - Emit JumpTable node in the current MBB
1653 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1654 // Emit the code for the jump table
1655 assert(JT.Reg != -1U && "Should lower JT Header first!");
1656 MVT PTy = TLI.getPointerTy();
1657 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1658 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1659 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1664 /// visitJumpTableHeader - This function emits necessary code to produce index
1665 /// in the JumpTable from switch case.
1666 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1667 SelectionDAGISel::JumpTableHeader &JTH) {
1668 // Subtract the lowest switch case value from the value being switched on
1669 // and conditional branch to default mbb if the result is greater than the
1670 // difference between smallest and largest cases.
1671 SDValue SwitchOp = getValue(JTH.SValue);
1672 MVT VT = SwitchOp.getValueType();
1673 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1674 DAG.getConstant(JTH.First, VT));
1676 // The SDNode we just created, which holds the value being switched on
1677 // minus the the smallest case value, needs to be copied to a virtual
1678 // register so it can be used as an index into the jump table in a
1679 // subsequent basic block. This value may be smaller or larger than the
1680 // target's pointer type, and therefore require extension or truncating.
1681 if (VT.bitsGT(TLI.getPointerTy()))
1682 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1684 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1686 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1687 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1688 JT.Reg = JumpTableReg;
1690 // Emit the range check for the jump table, and branch to the default
1691 // block for the switch statement if the value being switched on exceeds
1692 // the largest case in the switch.
1693 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1694 DAG.getConstant(JTH.Last-JTH.First,VT),
1697 // Set NextBlock to be the MBB immediately after the current one, if any.
1698 // This is used to avoid emitting unnecessary branches to the next block.
1699 MachineBasicBlock *NextBlock = 0;
1700 MachineFunction::iterator BBI = CurMBB;
1701 if (++BBI != CurMBB->getParent()->end())
1704 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1705 DAG.getBasicBlock(JT.Default));
1707 if (JT.MBB == NextBlock)
1708 DAG.setRoot(BrCond);
1710 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1711 DAG.getBasicBlock(JT.MBB)));
1716 /// visitBitTestHeader - This function emits necessary code to produce value
1717 /// suitable for "bit tests"
1718 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1719 // Subtract the minimum value
1720 SDValue SwitchOp = getValue(B.SValue);
1721 MVT VT = SwitchOp.getValueType();
1722 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1723 DAG.getConstant(B.First, VT));
1726 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1727 DAG.getConstant(B.Range, VT),
1731 if (VT.bitsGT(TLI.getShiftAmountTy()))
1732 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1734 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1736 // Make desired shift
1737 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1738 DAG.getConstant(1, TLI.getPointerTy()),
1741 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1742 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1745 // Set NextBlock to be the MBB immediately after the current one, if any.
1746 // This is used to avoid emitting unnecessary branches to the next block.
1747 MachineBasicBlock *NextBlock = 0;
1748 MachineFunction::iterator BBI = CurMBB;
1749 if (++BBI != CurMBB->getParent()->end())
1752 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1754 CurMBB->addSuccessor(B.Default);
1755 CurMBB->addSuccessor(MBB);
1757 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1758 DAG.getBasicBlock(B.Default));
1760 if (MBB == NextBlock)
1761 DAG.setRoot(BrRange);
1763 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1764 DAG.getBasicBlock(MBB)));
1769 /// visitBitTestCase - this function produces one "bit test"
1770 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1772 SelectionDAGISel::BitTestCase &B) {
1773 // Emit bit tests and jumps
1774 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1775 TLI.getPointerTy());
1777 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1778 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1779 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1780 DAG.getConstant(0, TLI.getPointerTy()),
1783 CurMBB->addSuccessor(B.TargetBB);
1784 CurMBB->addSuccessor(NextMBB);
1786 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1787 AndCmp, DAG.getBasicBlock(B.TargetBB));
1789 // Set NextBlock to be the MBB immediately after the current one, if any.
1790 // This is used to avoid emitting unnecessary branches to the next block.
1791 MachineBasicBlock *NextBlock = 0;
1792 MachineFunction::iterator BBI = CurMBB;
1793 if (++BBI != CurMBB->getParent()->end())
1796 if (NextMBB == NextBlock)
1799 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1800 DAG.getBasicBlock(NextMBB)));
1805 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1806 // Retrieve successors.
1807 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1808 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1810 if (isa<InlineAsm>(I.getCalledValue()))
1813 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1815 // If the value of the invoke is used outside of its defining block, make it
1816 // available as a virtual register.
1817 if (!I.use_empty()) {
1818 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1819 if (VMI != FuncInfo.ValueMap.end())
1820 CopyValueToVirtualRegister(&I, VMI->second);
1823 // Update successor info
1824 CurMBB->addSuccessor(Return);
1825 CurMBB->addSuccessor(LandingPad);
1827 // Drop into normal successor.
1828 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1829 DAG.getBasicBlock(Return)));
1832 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1835 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1836 /// small case ranges).
1837 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1838 CaseRecVector& WorkList,
1840 MachineBasicBlock* Default) {
1841 Case& BackCase = *(CR.Range.second-1);
1843 // Size is the number of Cases represented by this range.
1844 unsigned Size = CR.Range.second - CR.Range.first;
1848 // Get the MachineFunction which holds the current MBB. This is used when
1849 // inserting any additional MBBs necessary to represent the switch.
1850 MachineFunction *CurMF = CurMBB->getParent();
1852 // Figure out which block is immediately after the current one.
1853 MachineBasicBlock *NextBlock = 0;
1854 MachineFunction::iterator BBI = CR.CaseBB;
1856 if (++BBI != CurMBB->getParent()->end())
1859 // TODO: If any two of the cases has the same destination, and if one value
1860 // is the same as the other, but has one bit unset that the other has set,
1861 // use bit manipulation to do two compares at once. For example:
1862 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1864 // Rearrange the case blocks so that the last one falls through if possible.
1865 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1866 // The last case block won't fall through into 'NextBlock' if we emit the
1867 // branches in this order. See if rearranging a case value would help.
1868 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1869 if (I->BB == NextBlock) {
1870 std::swap(*I, BackCase);
1876 // Create a CaseBlock record representing a conditional branch to
1877 // the Case's target mbb if the value being switched on SV is equal
1879 MachineBasicBlock *CurBlock = CR.CaseBB;
1880 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1881 MachineBasicBlock *FallThrough;
1883 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1884 CurMF->insert(BBI, FallThrough);
1886 // If the last case doesn't match, go to the default block.
1887 FallThrough = Default;
1890 Value *RHS, *LHS, *MHS;
1892 if (I->High == I->Low) {
1893 // This is just small small case range :) containing exactly 1 case
1895 LHS = SV; RHS = I->High; MHS = NULL;
1898 LHS = I->Low; MHS = SV; RHS = I->High;
1900 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1901 I->BB, FallThrough, CurBlock);
1903 // If emitting the first comparison, just call visitSwitchCase to emit the
1904 // code into the current block. Otherwise, push the CaseBlock onto the
1905 // vector to be later processed by SDISel, and insert the node's MBB
1906 // before the next MBB.
1907 if (CurBlock == CurMBB)
1908 visitSwitchCase(CB);
1910 SwitchCases.push_back(CB);
1912 CurBlock = FallThrough;
1918 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1919 return !DisableJumpTables &&
1920 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1921 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1924 /// handleJTSwitchCase - Emit jumptable for current switch case range
1925 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1926 CaseRecVector& WorkList,
1928 MachineBasicBlock* Default) {
1929 Case& FrontCase = *CR.Range.first;
1930 Case& BackCase = *(CR.Range.second-1);
1932 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1933 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1936 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1940 if (!areJTsAllowed(TLI) || TSize <= 3)
1943 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1947 DOUT << "Lowering jump table\n"
1948 << "First entry: " << First << ". Last entry: " << Last << "\n"
1949 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1951 // Get the MachineFunction which holds the current MBB. This is used when
1952 // inserting any additional MBBs necessary to represent the switch.
1953 MachineFunction *CurMF = CurMBB->getParent();
1955 // Figure out which block is immediately after the current one.
1956 MachineBasicBlock *NextBlock = 0;
1957 MachineFunction::iterator BBI = CR.CaseBB;
1959 if (++BBI != CurMBB->getParent()->end())
1962 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1964 // Create a new basic block to hold the code for loading the address
1965 // of the jump table, and jumping to it. Update successor information;
1966 // we will either branch to the default case for the switch, or the jump
1968 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1969 CurMF->insert(BBI, JumpTableBB);
1970 CR.CaseBB->addSuccessor(Default);
1971 CR.CaseBB->addSuccessor(JumpTableBB);
1973 // Build a vector of destination BBs, corresponding to each target
1974 // of the jump table. If the value of the jump table slot corresponds to
1975 // a case statement, push the case's BB onto the vector, otherwise, push
1977 std::vector<MachineBasicBlock*> DestBBs;
1978 int64_t TEI = First;
1979 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1980 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1981 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1983 if ((Low <= TEI) && (TEI <= High)) {
1984 DestBBs.push_back(I->BB);
1988 DestBBs.push_back(Default);
1992 // Update successor info. Add one edge to each unique successor.
1993 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1994 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1995 E = DestBBs.end(); I != E; ++I) {
1996 if (!SuccsHandled[(*I)->getNumber()]) {
1997 SuccsHandled[(*I)->getNumber()] = true;
1998 JumpTableBB->addSuccessor(*I);
2002 // Create a jump table index for this jump table, or return an existing
2004 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
2006 // Set the jump table information so that we can codegen it as a second
2007 // MachineBasicBlock
2008 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
2009 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
2010 (CR.CaseBB == CurMBB));
2011 if (CR.CaseBB == CurMBB)
2012 visitJumpTableHeader(JT, JTH);
2014 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2019 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2021 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2022 CaseRecVector& WorkList,
2024 MachineBasicBlock* Default) {
2025 // Get the MachineFunction which holds the current MBB. This is used when
2026 // inserting any additional MBBs necessary to represent the switch.
2027 MachineFunction *CurMF = CurMBB->getParent();
2029 // Figure out which block is immediately after the current one.
2030 MachineBasicBlock *NextBlock = 0;
2031 MachineFunction::iterator BBI = CR.CaseBB;
2033 if (++BBI != CurMBB->getParent()->end())
2036 Case& FrontCase = *CR.Range.first;
2037 Case& BackCase = *(CR.Range.second-1);
2038 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2040 // Size is the number of Cases represented by this range.
2041 unsigned Size = CR.Range.second - CR.Range.first;
2043 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2044 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2046 CaseItr Pivot = CR.Range.first + Size/2;
2048 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2049 // (heuristically) allow us to emit JumpTable's later.
2051 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2055 uint64_t LSize = FrontCase.size();
2056 uint64_t RSize = TSize-LSize;
2057 DOUT << "Selecting best pivot: \n"
2058 << "First: " << First << ", Last: " << Last <<"\n"
2059 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2060 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2062 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2063 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2064 assert((RBegin-LEnd>=1) && "Invalid case distance");
2065 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2066 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2067 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2068 // Should always split in some non-trivial place
2070 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2071 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2072 << "Metric: " << Metric << "\n";
2073 if (FMetric < Metric) {
2076 DOUT << "Current metric set to: " << FMetric << "\n";
2082 if (areJTsAllowed(TLI)) {
2083 // If our case is dense we *really* should handle it earlier!
2084 assert((FMetric > 0) && "Should handle dense range earlier!");
2086 Pivot = CR.Range.first + Size/2;
2089 CaseRange LHSR(CR.Range.first, Pivot);
2090 CaseRange RHSR(Pivot, CR.Range.second);
2091 Constant *C = Pivot->Low;
2092 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2094 // We know that we branch to the LHS if the Value being switched on is
2095 // less than the Pivot value, C. We use this to optimize our binary
2096 // tree a bit, by recognizing that if SV is greater than or equal to the
2097 // LHS's Case Value, and that Case Value is exactly one less than the
2098 // Pivot's Value, then we can branch directly to the LHS's Target,
2099 // rather than creating a leaf node for it.
2100 if ((LHSR.second - LHSR.first) == 1 &&
2101 LHSR.first->High == CR.GE &&
2102 cast<ConstantInt>(C)->getSExtValue() ==
2103 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2104 TrueBB = LHSR.first->BB;
2106 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2107 CurMF->insert(BBI, TrueBB);
2108 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2111 // Similar to the optimization above, if the Value being switched on is
2112 // known to be less than the Constant CR.LT, and the current Case Value
2113 // is CR.LT - 1, then we can branch directly to the target block for
2114 // the current Case Value, rather than emitting a RHS leaf node for it.
2115 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2116 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2117 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2118 FalseBB = RHSR.first->BB;
2120 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2121 CurMF->insert(BBI, FalseBB);
2122 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2125 // Create a CaseBlock record representing a conditional branch to
2126 // the LHS node if the value being switched on SV is less than C.
2127 // Otherwise, branch to LHS.
2128 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2129 TrueBB, FalseBB, CR.CaseBB);
2131 if (CR.CaseBB == CurMBB)
2132 visitSwitchCase(CB);
2134 SwitchCases.push_back(CB);
2139 /// handleBitTestsSwitchCase - if current case range has few destination and
2140 /// range span less, than machine word bitwidth, encode case range into series
2141 /// of masks and emit bit tests with these masks.
2142 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2143 CaseRecVector& WorkList,
2145 MachineBasicBlock* Default){
2146 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2148 Case& FrontCase = *CR.Range.first;
2149 Case& BackCase = *(CR.Range.second-1);
2151 // Get the MachineFunction which holds the current MBB. This is used when
2152 // inserting any additional MBBs necessary to represent the switch.
2153 MachineFunction *CurMF = CurMBB->getParent();
2155 unsigned numCmps = 0;
2156 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2158 // Single case counts one, case range - two.
2159 if (I->Low == I->High)
2165 // Count unique destinations
2166 SmallSet<MachineBasicBlock*, 4> Dests;
2167 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2168 Dests.insert(I->BB);
2169 if (Dests.size() > 3)
2170 // Don't bother the code below, if there are too much unique destinations
2173 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2174 << "Total number of comparisons: " << numCmps << "\n";
2176 // Compute span of values.
2177 Constant* minValue = FrontCase.Low;
2178 Constant* maxValue = BackCase.High;
2179 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2180 cast<ConstantInt>(minValue)->getSExtValue();
2181 DOUT << "Compare range: " << range << "\n"
2182 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2183 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2185 if (range>=IntPtrBits ||
2186 (!(Dests.size() == 1 && numCmps >= 3) &&
2187 !(Dests.size() == 2 && numCmps >= 5) &&
2188 !(Dests.size() >= 3 && numCmps >= 6)))
2191 DOUT << "Emitting bit tests\n";
2192 int64_t lowBound = 0;
2194 // Optimize the case where all the case values fit in a
2195 // word without having to subtract minValue. In this case,
2196 // we can optimize away the subtraction.
2197 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2198 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2199 range = cast<ConstantInt>(maxValue)->getSExtValue();
2201 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2204 CaseBitsVector CasesBits;
2205 unsigned i, count = 0;
2207 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2208 MachineBasicBlock* Dest = I->BB;
2209 for (i = 0; i < count; ++i)
2210 if (Dest == CasesBits[i].BB)
2214 assert((count < 3) && "Too much destinations to test!");
2215 CasesBits.push_back(CaseBits(0, Dest, 0));
2219 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2220 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2222 for (uint64_t j = lo; j <= hi; j++) {
2223 CasesBits[i].Mask |= 1ULL << j;
2224 CasesBits[i].Bits++;
2228 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2230 SelectionDAGISel::BitTestInfo BTC;
2232 // Figure out which block is immediately after the current one.
2233 MachineFunction::iterator BBI = CR.CaseBB;
2236 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2239 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2240 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2241 << ", BB: " << CasesBits[i].BB << "\n";
2243 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2244 CurMF->insert(BBI, CaseBB);
2245 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2250 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2251 -1U, (CR.CaseBB == CurMBB),
2252 CR.CaseBB, Default, BTC);
2254 if (CR.CaseBB == CurMBB)
2255 visitBitTestHeader(BTB);
2257 BitTestCases.push_back(BTB);
2263 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2264 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2265 const SwitchInst& SI) {
2266 unsigned numCmps = 0;
2268 // Start with "simple" cases
2269 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2270 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2271 Cases.push_back(Case(SI.getSuccessorValue(i),
2272 SI.getSuccessorValue(i),
2275 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2277 // Merge case into clusters
2278 if (Cases.size()>=2)
2279 // Must recompute end() each iteration because it may be
2280 // invalidated by erase if we hold on to it
2281 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2282 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2283 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2284 MachineBasicBlock* nextBB = J->BB;
2285 MachineBasicBlock* currentBB = I->BB;
2287 // If the two neighboring cases go to the same destination, merge them
2288 // into a single case.
2289 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2297 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2298 if (I->Low != I->High)
2299 // A range counts double, since it requires two compares.
2306 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2307 // Figure out which block is immediately after the current one.
2308 MachineBasicBlock *NextBlock = 0;
2309 MachineFunction::iterator BBI = CurMBB;
2311 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2313 // If there is only the default destination, branch to it if it is not the
2314 // next basic block. Otherwise, just fall through.
2315 if (SI.getNumOperands() == 2) {
2316 // Update machine-CFG edges.
2318 // If this is not a fall-through branch, emit the branch.
2319 CurMBB->addSuccessor(Default);
2320 if (Default != NextBlock)
2321 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2322 DAG.getBasicBlock(Default)));
2327 // If there are any non-default case statements, create a vector of Cases
2328 // representing each one, and sort the vector so that we can efficiently
2329 // create a binary search tree from them.
2331 unsigned numCmps = Clusterify(Cases, SI);
2332 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2333 << ". Total compares: " << numCmps << "\n";
2335 // Get the Value to be switched on and default basic blocks, which will be
2336 // inserted into CaseBlock records, representing basic blocks in the binary
2338 Value *SV = SI.getOperand(0);
2340 // Push the initial CaseRec onto the worklist
2341 CaseRecVector WorkList;
2342 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2344 while (!WorkList.empty()) {
2345 // Grab a record representing a case range to process off the worklist
2346 CaseRec CR = WorkList.back();
2347 WorkList.pop_back();
2349 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2352 // If the range has few cases (two or less) emit a series of specific
2354 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2357 // If the switch has more than 5 blocks, and at least 40% dense, and the
2358 // target supports indirect branches, then emit a jump table rather than
2359 // lowering the switch to a binary tree of conditional branches.
2360 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2363 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2364 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2365 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2370 void SelectionDAGLowering::visitSub(User &I) {
2371 // -0.0 - X --> fneg
2372 const Type *Ty = I.getType();
2373 if (isa<VectorType>(Ty)) {
2374 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2375 const VectorType *DestTy = cast<VectorType>(I.getType());
2376 const Type *ElTy = DestTy->getElementType();
2377 if (ElTy->isFloatingPoint()) {
2378 unsigned VL = DestTy->getNumElements();
2379 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2380 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2382 SDValue Op2 = getValue(I.getOperand(1));
2383 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2389 if (Ty->isFloatingPoint()) {
2390 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2391 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2392 SDValue Op2 = getValue(I.getOperand(1));
2393 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2398 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2401 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2402 SDValue Op1 = getValue(I.getOperand(0));
2403 SDValue Op2 = getValue(I.getOperand(1));
2405 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2408 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2409 SDValue Op1 = getValue(I.getOperand(0));
2410 SDValue Op2 = getValue(I.getOperand(1));
2411 if (!isa<VectorType>(I.getType())) {
2412 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2413 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2414 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2415 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2418 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2421 void SelectionDAGLowering::visitICmp(User &I) {
2422 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2423 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2424 predicate = IC->getPredicate();
2425 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2426 predicate = ICmpInst::Predicate(IC->getPredicate());
2427 SDValue Op1 = getValue(I.getOperand(0));
2428 SDValue Op2 = getValue(I.getOperand(1));
2429 ISD::CondCode Opcode;
2430 switch (predicate) {
2431 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2432 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2433 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2434 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2435 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2436 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2437 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2438 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2439 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2440 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2442 assert(!"Invalid ICmp predicate value");
2443 Opcode = ISD::SETEQ;
2446 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2449 void SelectionDAGLowering::visitFCmp(User &I) {
2450 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2451 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2452 predicate = FC->getPredicate();
2453 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2454 predicate = FCmpInst::Predicate(FC->getPredicate());
2455 SDValue Op1 = getValue(I.getOperand(0));
2456 SDValue Op2 = getValue(I.getOperand(1));
2457 ISD::CondCode Condition, FOC, FPC;
2458 switch (predicate) {
2459 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2460 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2461 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2462 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2463 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2464 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2465 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2466 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2467 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2468 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2469 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2470 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2471 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2472 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2473 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2474 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2476 assert(!"Invalid FCmp predicate value");
2477 FOC = FPC = ISD::SETFALSE;
2480 if (FiniteOnlyFPMath())
2484 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2487 void SelectionDAGLowering::visitVICmp(User &I) {
2488 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2489 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2490 predicate = IC->getPredicate();
2491 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2492 predicate = ICmpInst::Predicate(IC->getPredicate());
2493 SDValue Op1 = getValue(I.getOperand(0));
2494 SDValue Op2 = getValue(I.getOperand(1));
2495 ISD::CondCode Opcode;
2496 switch (predicate) {
2497 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2498 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2499 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2500 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2501 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2502 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2503 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2504 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2505 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2506 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2508 assert(!"Invalid ICmp predicate value");
2509 Opcode = ISD::SETEQ;
2512 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2515 void SelectionDAGLowering::visitVFCmp(User &I) {
2516 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2517 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2518 predicate = FC->getPredicate();
2519 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2520 predicate = FCmpInst::Predicate(FC->getPredicate());
2521 SDValue Op1 = getValue(I.getOperand(0));
2522 SDValue Op2 = getValue(I.getOperand(1));
2523 ISD::CondCode Condition, FOC, FPC;
2524 switch (predicate) {
2525 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2526 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2527 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2528 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2529 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2530 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2531 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2532 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2533 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2534 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2535 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2536 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2537 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2538 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2539 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2540 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2542 assert(!"Invalid VFCmp predicate value");
2543 FOC = FPC = ISD::SETFALSE;
2546 if (FiniteOnlyFPMath())
2551 MVT DestVT = TLI.getValueType(I.getType());
2553 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2556 void SelectionDAGLowering::visitSelect(User &I) {
2557 SDValue Cond = getValue(I.getOperand(0));
2558 SDValue TrueVal = getValue(I.getOperand(1));
2559 SDValue FalseVal = getValue(I.getOperand(2));
2560 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2561 TrueVal, FalseVal));
2565 void SelectionDAGLowering::visitTrunc(User &I) {
2566 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2567 SDValue N = getValue(I.getOperand(0));
2568 MVT DestVT = TLI.getValueType(I.getType());
2569 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2572 void SelectionDAGLowering::visitZExt(User &I) {
2573 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2574 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2575 SDValue N = getValue(I.getOperand(0));
2576 MVT DestVT = TLI.getValueType(I.getType());
2577 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2580 void SelectionDAGLowering::visitSExt(User &I) {
2581 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2582 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2583 SDValue N = getValue(I.getOperand(0));
2584 MVT DestVT = TLI.getValueType(I.getType());
2585 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2588 void SelectionDAGLowering::visitFPTrunc(User &I) {
2589 // FPTrunc is never a no-op cast, no need to check
2590 SDValue N = getValue(I.getOperand(0));
2591 MVT DestVT = TLI.getValueType(I.getType());
2592 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2595 void SelectionDAGLowering::visitFPExt(User &I){
2596 // FPTrunc is never a no-op cast, no need to check
2597 SDValue N = getValue(I.getOperand(0));
2598 MVT DestVT = TLI.getValueType(I.getType());
2599 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2602 void SelectionDAGLowering::visitFPToUI(User &I) {
2603 // FPToUI is never a no-op cast, no need to check
2604 SDValue N = getValue(I.getOperand(0));
2605 MVT DestVT = TLI.getValueType(I.getType());
2606 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2609 void SelectionDAGLowering::visitFPToSI(User &I) {
2610 // FPToSI is never a no-op cast, no need to check
2611 SDValue N = getValue(I.getOperand(0));
2612 MVT DestVT = TLI.getValueType(I.getType());
2613 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2616 void SelectionDAGLowering::visitUIToFP(User &I) {
2617 // UIToFP is never a no-op cast, no need to check
2618 SDValue N = getValue(I.getOperand(0));
2619 MVT DestVT = TLI.getValueType(I.getType());
2620 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2623 void SelectionDAGLowering::visitSIToFP(User &I){
2624 // UIToFP is never a no-op cast, no need to check
2625 SDValue N = getValue(I.getOperand(0));
2626 MVT DestVT = TLI.getValueType(I.getType());
2627 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2630 void SelectionDAGLowering::visitPtrToInt(User &I) {
2631 // What to do depends on the size of the integer and the size of the pointer.
2632 // We can either truncate, zero extend, or no-op, accordingly.
2633 SDValue N = getValue(I.getOperand(0));
2634 MVT SrcVT = N.getValueType();
2635 MVT DestVT = TLI.getValueType(I.getType());
2637 if (DestVT.bitsLT(SrcVT))
2638 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2640 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2641 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2642 setValue(&I, Result);
2645 void SelectionDAGLowering::visitIntToPtr(User &I) {
2646 // What to do depends on the size of the integer and the size of the pointer.
2647 // We can either truncate, zero extend, or no-op, accordingly.
2648 SDValue N = getValue(I.getOperand(0));
2649 MVT SrcVT = N.getValueType();
2650 MVT DestVT = TLI.getValueType(I.getType());
2651 if (DestVT.bitsLT(SrcVT))
2652 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2654 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2655 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2658 void SelectionDAGLowering::visitBitCast(User &I) {
2659 SDValue N = getValue(I.getOperand(0));
2660 MVT DestVT = TLI.getValueType(I.getType());
2662 // BitCast assures us that source and destination are the same size so this
2663 // is either a BIT_CONVERT or a no-op.
2664 if (DestVT != N.getValueType())
2665 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2667 setValue(&I, N); // noop cast.
2670 void SelectionDAGLowering::visitInsertElement(User &I) {
2671 SDValue InVec = getValue(I.getOperand(0));
2672 SDValue InVal = getValue(I.getOperand(1));
2673 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2674 getValue(I.getOperand(2)));
2676 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2677 TLI.getValueType(I.getType()),
2678 InVec, InVal, InIdx));
2681 void SelectionDAGLowering::visitExtractElement(User &I) {
2682 SDValue InVec = getValue(I.getOperand(0));
2683 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2684 getValue(I.getOperand(1)));
2685 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2686 TLI.getValueType(I.getType()), InVec, InIdx));
2689 void SelectionDAGLowering::visitShuffleVector(User &I) {
2690 SDValue V1 = getValue(I.getOperand(0));
2691 SDValue V2 = getValue(I.getOperand(1));
2692 SDValue Mask = getValue(I.getOperand(2));
2694 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2695 TLI.getValueType(I.getType()),
2699 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2700 const Value *Op0 = I.getOperand(0);
2701 const Value *Op1 = I.getOperand(1);
2702 const Type *AggTy = I.getType();
2703 const Type *ValTy = Op1->getType();
2704 bool IntoUndef = isa<UndefValue>(Op0);
2705 bool FromUndef = isa<UndefValue>(Op1);
2707 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2708 I.idx_begin(), I.idx_end());
2710 SmallVector<MVT, 4> AggValueVTs;
2711 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2712 SmallVector<MVT, 4> ValValueVTs;
2713 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2715 unsigned NumAggValues = AggValueVTs.size();
2716 unsigned NumValValues = ValValueVTs.size();
2717 SmallVector<SDValue, 4> Values(NumAggValues);
2719 SDValue Agg = getValue(Op0);
2720 SDValue Val = getValue(Op1);
2722 // Copy the beginning value(s) from the original aggregate.
2723 for (; i != LinearIndex; ++i)
2724 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2725 SDValue(Agg.Val, Agg.ResNo + i);
2726 // Copy values from the inserted value(s).
2727 for (; i != LinearIndex + NumValValues; ++i)
2728 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2729 SDValue(Val.Val, Val.ResNo + i - LinearIndex);
2730 // Copy remaining value(s) from the original aggregate.
2731 for (; i != NumAggValues; ++i)
2732 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2733 SDValue(Agg.Val, Agg.ResNo + i);
2735 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2736 &Values[0], NumAggValues));
2739 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2740 const Value *Op0 = I.getOperand(0);
2741 const Type *AggTy = Op0->getType();
2742 const Type *ValTy = I.getType();
2743 bool OutOfUndef = isa<UndefValue>(Op0);
2745 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2746 I.idx_begin(), I.idx_end());
2748 SmallVector<MVT, 4> ValValueVTs;
2749 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2751 unsigned NumValValues = ValValueVTs.size();
2752 SmallVector<SDValue, 4> Values(NumValValues);
2754 SDValue Agg = getValue(Op0);
2755 // Copy out the selected value(s).
2756 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2757 Values[i - LinearIndex] =
2758 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2759 SDValue(Agg.Val, Agg.ResNo + i);
2761 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2762 &Values[0], NumValValues));
2766 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2767 SDValue N = getValue(I.getOperand(0));
2768 const Type *Ty = I.getOperand(0)->getType();
2770 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2773 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2774 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2777 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2778 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2779 DAG.getIntPtrConstant(Offset));
2781 Ty = StTy->getElementType(Field);
2783 Ty = cast<SequentialType>(Ty)->getElementType();
2785 // If this is a constant subscript, handle it quickly.
2786 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2787 if (CI->getZExtValue() == 0) continue;
2789 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2790 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2791 DAG.getIntPtrConstant(Offs));
2795 // N = N + Idx * ElementSize;
2796 uint64_t ElementSize = TD->getABITypeSize(Ty);
2797 SDValue IdxN = getValue(Idx);
2799 // If the index is smaller or larger than intptr_t, truncate or extend
2801 if (IdxN.getValueType().bitsLT(N.getValueType())) {
2802 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2803 } else if (IdxN.getValueType().bitsGT(N.getValueType()))
2804 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2806 // If this is a multiply by a power of two, turn it into a shl
2807 // immediately. This is a very common case.
2808 if (isPowerOf2_64(ElementSize)) {
2809 unsigned Amt = Log2_64(ElementSize);
2810 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2811 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2812 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2816 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2817 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2818 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2824 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2825 // If this is a fixed sized alloca in the entry block of the function,
2826 // allocate it statically on the stack.
2827 if (FuncInfo.StaticAllocaMap.count(&I))
2828 return; // getValue will auto-populate this.
2830 const Type *Ty = I.getAllocatedType();
2831 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2833 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2836 SDValue AllocSize = getValue(I.getArraySize());
2837 MVT IntPtr = TLI.getPointerTy();
2838 if (IntPtr.bitsLT(AllocSize.getValueType()))
2839 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2840 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2841 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2843 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2844 DAG.getIntPtrConstant(TySize));
2846 // Handle alignment. If the requested alignment is less than or equal to
2847 // the stack alignment, ignore it. If the size is greater than or equal to
2848 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2849 unsigned StackAlign =
2850 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2851 if (Align <= StackAlign)
2854 // Round the size of the allocation up to the stack alignment size
2855 // by add SA-1 to the size.
2856 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2857 DAG.getIntPtrConstant(StackAlign-1));
2858 // Mask out the low bits for alignment purposes.
2859 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2860 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2862 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2863 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2865 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2867 DAG.setRoot(DSA.getValue(1));
2869 // Inform the Frame Information that we have just allocated a variable-sized
2871 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2874 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2875 const Value *SV = I.getOperand(0);
2876 SDValue Ptr = getValue(SV);
2878 const Type *Ty = I.getType();
2879 bool isVolatile = I.isVolatile();
2880 unsigned Alignment = I.getAlignment();
2882 SmallVector<MVT, 4> ValueVTs;
2883 SmallVector<uint64_t, 4> Offsets;
2884 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2885 unsigned NumValues = ValueVTs.size();
2890 bool ConstantMemory = false;
2892 // Serialize volatile loads with other side effects.
2894 else if (AA.pointsToConstantMemory(SV)) {
2895 // Do not serialize (non-volatile) loads of constant memory with anything.
2896 Root = DAG.getEntryNode();
2897 ConstantMemory = true;
2899 // Do not serialize non-volatile loads against each other.
2900 Root = DAG.getRoot();
2903 SmallVector<SDValue, 4> Values(NumValues);
2904 SmallVector<SDValue, 4> Chains(NumValues);
2905 MVT PtrVT = Ptr.getValueType();
2906 for (unsigned i = 0; i != NumValues; ++i) {
2907 SDValue L = DAG.getLoad(ValueVTs[i], Root,
2908 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2909 DAG.getConstant(Offsets[i], PtrVT)),
2911 isVolatile, Alignment);
2913 Chains[i] = L.getValue(1);
2916 if (!ConstantMemory) {
2917 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2918 &Chains[0], NumValues);
2922 PendingLoads.push_back(Chain);
2925 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2926 &Values[0], NumValues));
2930 void SelectionDAGLowering::visitStore(StoreInst &I) {
2931 Value *SrcV = I.getOperand(0);
2932 Value *PtrV = I.getOperand(1);
2934 SmallVector<MVT, 4> ValueVTs;
2935 SmallVector<uint64_t, 4> Offsets;
2936 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2937 unsigned NumValues = ValueVTs.size();
2941 // Get the lowered operands. Note that we do this after
2942 // checking if NumResults is zero, because with zero results
2943 // the operands won't have values in the map.
2944 SDValue Src = getValue(SrcV);
2945 SDValue Ptr = getValue(PtrV);
2947 SDValue Root = getRoot();
2948 SmallVector<SDValue, 4> Chains(NumValues);
2949 MVT PtrVT = Ptr.getValueType();
2950 bool isVolatile = I.isVolatile();
2951 unsigned Alignment = I.getAlignment();
2952 for (unsigned i = 0; i != NumValues; ++i)
2953 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
2954 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2955 DAG.getConstant(Offsets[i], PtrVT)),
2957 isVolatile, Alignment);
2959 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2962 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2964 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2965 unsigned Intrinsic) {
2966 bool HasChain = !I.doesNotAccessMemory();
2967 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2969 // Build the operand list.
2970 SmallVector<SDValue, 8> Ops;
2971 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2973 // We don't need to serialize loads against other loads.
2974 Ops.push_back(DAG.getRoot());
2976 Ops.push_back(getRoot());
2980 // Add the intrinsic ID as an integer operand.
2981 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2983 // Add all operands of the call to the operand list.
2984 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2985 SDValue Op = getValue(I.getOperand(i));
2986 assert(TLI.isTypeLegal(Op.getValueType()) &&
2987 "Intrinsic uses a non-legal type?");
2991 std::vector<MVT> VTs;
2992 if (I.getType() != Type::VoidTy) {
2993 MVT VT = TLI.getValueType(I.getType());
2994 if (VT.isVector()) {
2995 const VectorType *DestTy = cast<VectorType>(I.getType());
2996 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2998 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2999 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
3002 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
3006 VTs.push_back(MVT::Other);
3008 const MVT *VTList = DAG.getNodeValueTypes(VTs);
3013 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
3014 &Ops[0], Ops.size());
3015 else if (I.getType() != Type::VoidTy)
3016 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
3017 &Ops[0], Ops.size());
3019 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
3020 &Ops[0], Ops.size());
3023 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
3025 PendingLoads.push_back(Chain);
3029 if (I.getType() != Type::VoidTy) {
3030 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3031 MVT VT = TLI.getValueType(PTy);
3032 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3034 setValue(&I, Result);
3038 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3039 static GlobalVariable *ExtractTypeInfo (Value *V) {
3040 V = V->stripPointerCasts();
3041 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3042 assert ((GV || isa<ConstantPointerNull>(V)) &&
3043 "TypeInfo must be a global variable or NULL");
3047 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3048 /// call, and add them to the specified machine basic block.
3049 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3050 MachineBasicBlock *MBB) {
3051 // Inform the MachineModuleInfo of the personality for this landing pad.
3052 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3053 assert(CE->getOpcode() == Instruction::BitCast &&
3054 isa<Function>(CE->getOperand(0)) &&
3055 "Personality should be a function");
3056 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3058 // Gather all the type infos for this landing pad and pass them along to
3059 // MachineModuleInfo.
3060 std::vector<GlobalVariable *> TyInfo;
3061 unsigned N = I.getNumOperands();
3063 for (unsigned i = N - 1; i > 2; --i) {
3064 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3065 unsigned FilterLength = CI->getZExtValue();
3066 unsigned FirstCatch = i + FilterLength + !FilterLength;
3067 assert (FirstCatch <= N && "Invalid filter length");
3069 if (FirstCatch < N) {
3070 TyInfo.reserve(N - FirstCatch);
3071 for (unsigned j = FirstCatch; j < N; ++j)
3072 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3073 MMI->addCatchTypeInfo(MBB, TyInfo);
3077 if (!FilterLength) {
3079 MMI->addCleanup(MBB);
3082 TyInfo.reserve(FilterLength - 1);
3083 for (unsigned j = i + 1; j < FirstCatch; ++j)
3084 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3085 MMI->addFilterTypeInfo(MBB, TyInfo);
3094 TyInfo.reserve(N - 3);
3095 for (unsigned j = 3; j < N; ++j)
3096 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3097 MMI->addCatchTypeInfo(MBB, TyInfo);
3102 /// Inlined utility function to implement binary input atomic intrinsics for
3103 // visitIntrinsicCall: I is a call instruction
3104 // Op is the associated NodeType for I
3106 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3107 SDValue Root = getRoot();
3108 SDValue L = DAG.getAtomic(Op, Root,
3109 getValue(I.getOperand(1)),
3110 getValue(I.getOperand(2)),
3113 DAG.setRoot(L.getValue(1));
3117 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3118 /// we want to emit this as a call to a named external function, return the name
3119 /// otherwise lower it and return null.
3121 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3122 switch (Intrinsic) {
3124 // By default, turn this into a target intrinsic node.
3125 visitTargetIntrinsic(I, Intrinsic);
3127 case Intrinsic::vastart: visitVAStart(I); return 0;
3128 case Intrinsic::vaend: visitVAEnd(I); return 0;
3129 case Intrinsic::vacopy: visitVACopy(I); return 0;
3130 case Intrinsic::returnaddress:
3131 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3132 getValue(I.getOperand(1))));
3134 case Intrinsic::frameaddress:
3135 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3136 getValue(I.getOperand(1))));
3138 case Intrinsic::setjmp:
3139 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3141 case Intrinsic::longjmp:
3142 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3144 case Intrinsic::memcpy_i32:
3145 case Intrinsic::memcpy_i64: {
3146 SDValue Op1 = getValue(I.getOperand(1));
3147 SDValue Op2 = getValue(I.getOperand(2));
3148 SDValue Op3 = getValue(I.getOperand(3));
3149 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3150 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3151 I.getOperand(1), 0, I.getOperand(2), 0));
3154 case Intrinsic::memset_i32:
3155 case Intrinsic::memset_i64: {
3156 SDValue Op1 = getValue(I.getOperand(1));
3157 SDValue Op2 = getValue(I.getOperand(2));
3158 SDValue Op3 = getValue(I.getOperand(3));
3159 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3160 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3161 I.getOperand(1), 0));
3164 case Intrinsic::memmove_i32:
3165 case Intrinsic::memmove_i64: {
3166 SDValue Op1 = getValue(I.getOperand(1));
3167 SDValue Op2 = getValue(I.getOperand(2));
3168 SDValue Op3 = getValue(I.getOperand(3));
3169 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3171 // If the source and destination are known to not be aliases, we can
3172 // lower memmove as memcpy.
3173 uint64_t Size = -1ULL;
3174 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3175 Size = C->getValue();
3176 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3177 AliasAnalysis::NoAlias) {
3178 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3179 I.getOperand(1), 0, I.getOperand(2), 0));
3183 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3184 I.getOperand(1), 0, I.getOperand(2), 0));
3187 case Intrinsic::dbg_stoppoint: {
3188 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3189 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3190 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3191 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3192 assert(DD && "Not a debug information descriptor");
3193 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3196 cast<CompileUnitDesc>(DD)));
3201 case Intrinsic::dbg_region_start: {
3202 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3203 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3204 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3205 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3206 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3211 case Intrinsic::dbg_region_end: {
3212 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3213 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3214 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3215 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3216 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3221 case Intrinsic::dbg_func_start: {
3222 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3224 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3225 Value *SP = FSI.getSubprogram();
3226 if (SP && MMI->Verify(SP)) {
3227 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3228 // what (most?) gdb expects.
3229 DebugInfoDesc *DD = MMI->getDescFor(SP);
3230 assert(DD && "Not a debug information descriptor");
3231 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3232 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3233 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3234 // Record the source line but does create a label. It will be emitted
3235 // at asm emission time.
3236 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3241 case Intrinsic::dbg_declare: {
3242 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3243 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3244 Value *Variable = DI.getVariable();
3245 if (MMI && Variable && MMI->Verify(Variable))
3246 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3247 getValue(DI.getAddress()), getValue(Variable)));
3251 case Intrinsic::eh_exception: {
3252 if (!CurMBB->isLandingPad()) {
3253 // FIXME: Mark exception register as live in. Hack for PR1508.
3254 unsigned Reg = TLI.getExceptionAddressRegister();
3255 if (Reg) CurMBB->addLiveIn(Reg);
3257 // Insert the EXCEPTIONADDR instruction.
3258 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3260 Ops[0] = DAG.getRoot();
3261 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3263 DAG.setRoot(Op.getValue(1));
3267 case Intrinsic::eh_selector_i32:
3268 case Intrinsic::eh_selector_i64: {
3269 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3270 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3271 MVT::i32 : MVT::i64);
3274 if (CurMBB->isLandingPad())
3275 addCatchInfo(I, MMI, CurMBB);
3278 FuncInfo.CatchInfoLost.insert(&I);
3280 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3281 unsigned Reg = TLI.getExceptionSelectorRegister();
3282 if (Reg) CurMBB->addLiveIn(Reg);
3285 // Insert the EHSELECTION instruction.
3286 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3288 Ops[0] = getValue(I.getOperand(1));
3290 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3292 DAG.setRoot(Op.getValue(1));
3294 setValue(&I, DAG.getConstant(0, VT));
3300 case Intrinsic::eh_typeid_for_i32:
3301 case Intrinsic::eh_typeid_for_i64: {
3302 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3303 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3304 MVT::i32 : MVT::i64);
3307 // Find the type id for the given typeinfo.
3308 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3310 unsigned TypeID = MMI->getTypeIDFor(GV);
3311 setValue(&I, DAG.getConstant(TypeID, VT));
3313 // Return something different to eh_selector.
3314 setValue(&I, DAG.getConstant(1, VT));
3320 case Intrinsic::eh_return: {
3321 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3324 MMI->setCallsEHReturn(true);
3325 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3328 getValue(I.getOperand(1)),
3329 getValue(I.getOperand(2))));
3331 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3337 case Intrinsic::eh_unwind_init: {
3338 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3339 MMI->setCallsUnwindInit(true);
3345 case Intrinsic::eh_dwarf_cfa: {
3346 MVT VT = getValue(I.getOperand(1)).getValueType();
3348 if (VT.bitsGT(TLI.getPointerTy()))
3349 CfaArg = DAG.getNode(ISD::TRUNCATE,
3350 TLI.getPointerTy(), getValue(I.getOperand(1)));
3352 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3353 TLI.getPointerTy(), getValue(I.getOperand(1)));
3355 SDValue Offset = DAG.getNode(ISD::ADD,
3357 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3358 TLI.getPointerTy()),
3360 setValue(&I, DAG.getNode(ISD::ADD,
3362 DAG.getNode(ISD::FRAMEADDR,
3365 TLI.getPointerTy())),
3370 case Intrinsic::sqrt:
3371 setValue(&I, DAG.getNode(ISD::FSQRT,
3372 getValue(I.getOperand(1)).getValueType(),
3373 getValue(I.getOperand(1))));
3375 case Intrinsic::powi:
3376 setValue(&I, DAG.getNode(ISD::FPOWI,
3377 getValue(I.getOperand(1)).getValueType(),
3378 getValue(I.getOperand(1)),
3379 getValue(I.getOperand(2))));
3381 case Intrinsic::sin:
3382 setValue(&I, DAG.getNode(ISD::FSIN,
3383 getValue(I.getOperand(1)).getValueType(),
3384 getValue(I.getOperand(1))));
3386 case Intrinsic::cos:
3387 setValue(&I, DAG.getNode(ISD::FCOS,
3388 getValue(I.getOperand(1)).getValueType(),
3389 getValue(I.getOperand(1))));
3391 case Intrinsic::pow:
3392 setValue(&I, DAG.getNode(ISD::FPOW,
3393 getValue(I.getOperand(1)).getValueType(),
3394 getValue(I.getOperand(1)),
3395 getValue(I.getOperand(2))));
3397 case Intrinsic::pcmarker: {
3398 SDValue Tmp = getValue(I.getOperand(1));
3399 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3402 case Intrinsic::readcyclecounter: {
3403 SDValue Op = getRoot();
3404 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3405 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3408 DAG.setRoot(Tmp.getValue(1));
3411 case Intrinsic::part_select: {
3412 // Currently not implemented: just abort
3413 assert(0 && "part_select intrinsic not implemented");
3416 case Intrinsic::part_set: {
3417 // Currently not implemented: just abort
3418 assert(0 && "part_set intrinsic not implemented");
3421 case Intrinsic::bswap:
3422 setValue(&I, DAG.getNode(ISD::BSWAP,
3423 getValue(I.getOperand(1)).getValueType(),
3424 getValue(I.getOperand(1))));
3426 case Intrinsic::cttz: {
3427 SDValue Arg = getValue(I.getOperand(1));
3428 MVT Ty = Arg.getValueType();
3429 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3430 setValue(&I, result);
3433 case Intrinsic::ctlz: {
3434 SDValue Arg = getValue(I.getOperand(1));
3435 MVT Ty = Arg.getValueType();
3436 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3437 setValue(&I, result);
3440 case Intrinsic::ctpop: {
3441 SDValue Arg = getValue(I.getOperand(1));
3442 MVT Ty = Arg.getValueType();
3443 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3444 setValue(&I, result);
3447 case Intrinsic::stacksave: {
3448 SDValue Op = getRoot();
3449 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
3450 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3452 DAG.setRoot(Tmp.getValue(1));
3455 case Intrinsic::stackrestore: {
3456 SDValue Tmp = getValue(I.getOperand(1));
3457 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3460 case Intrinsic::var_annotation:
3461 // Discard annotate attributes
3464 case Intrinsic::init_trampoline: {
3465 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3469 Ops[1] = getValue(I.getOperand(1));
3470 Ops[2] = getValue(I.getOperand(2));
3471 Ops[3] = getValue(I.getOperand(3));
3472 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3473 Ops[5] = DAG.getSrcValue(F);
3475 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
3476 DAG.getNodeValueTypes(TLI.getPointerTy(),
3481 DAG.setRoot(Tmp.getValue(1));
3485 case Intrinsic::gcroot:
3487 Value *Alloca = I.getOperand(1);
3488 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3490 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3491 GCI->addStackRoot(FI->getIndex(), TypeMap);
3495 case Intrinsic::gcread:
3496 case Intrinsic::gcwrite:
3497 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3500 case Intrinsic::flt_rounds: {
3501 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3505 case Intrinsic::trap: {
3506 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3509 case Intrinsic::prefetch: {
3512 Ops[1] = getValue(I.getOperand(1));
3513 Ops[2] = getValue(I.getOperand(2));
3514 Ops[3] = getValue(I.getOperand(3));
3515 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3519 case Intrinsic::memory_barrier: {
3522 for (int x = 1; x < 6; ++x)
3523 Ops[x] = getValue(I.getOperand(x));
3525 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3528 case Intrinsic::atomic_cmp_swap: {
3529 SDValue Root = getRoot();
3530 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
3531 getValue(I.getOperand(1)),
3532 getValue(I.getOperand(2)),
3533 getValue(I.getOperand(3)),
3536 DAG.setRoot(L.getValue(1));
3539 case Intrinsic::atomic_load_add:
3540 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3541 case Intrinsic::atomic_load_sub:
3542 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
3543 case Intrinsic::atomic_load_and:
3544 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3545 case Intrinsic::atomic_load_or:
3546 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3547 case Intrinsic::atomic_load_xor:
3548 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3549 case Intrinsic::atomic_load_nand:
3550 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3551 case Intrinsic::atomic_load_min:
3552 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3553 case Intrinsic::atomic_load_max:
3554 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3555 case Intrinsic::atomic_load_umin:
3556 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3557 case Intrinsic::atomic_load_umax:
3558 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3559 case Intrinsic::atomic_swap:
3560 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3565 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
3567 MachineBasicBlock *LandingPad) {
3568 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3569 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3570 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3571 unsigned BeginLabel = 0, EndLabel = 0;
3573 TargetLowering::ArgListTy Args;
3574 TargetLowering::ArgListEntry Entry;
3575 Args.reserve(CS.arg_size());
3576 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3578 SDValue ArgNode = getValue(*i);
3579 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3581 unsigned attrInd = i - CS.arg_begin() + 1;
3582 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3583 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3584 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3585 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3586 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3587 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3588 Entry.Alignment = CS.getParamAlignment(attrInd);
3589 Args.push_back(Entry);
3592 if (LandingPad && MMI) {
3593 // Insert a label before the invoke call to mark the try range. This can be
3594 // used to detect deletion of the invoke via the MachineModuleInfo.
3595 BeginLabel = MMI->NextLabelID();
3596 // Both PendingLoads and PendingExports must be flushed here;
3597 // this call might not return.
3599 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
3602 std::pair<SDValue,SDValue> Result =
3603 TLI.LowerCallTo(getRoot(), CS.getType(),
3604 CS.paramHasAttr(0, ParamAttr::SExt),
3605 CS.paramHasAttr(0, ParamAttr::ZExt),
3606 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3608 if (CS.getType() != Type::VoidTy)
3609 setValue(CS.getInstruction(), Result.first);
3610 DAG.setRoot(Result.second);
3612 if (LandingPad && MMI) {
3613 // Insert a label at the end of the invoke call to mark the try range. This
3614 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3615 EndLabel = MMI->NextLabelID();
3616 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
3618 // Inform MachineModuleInfo of range.
3619 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3624 void SelectionDAGLowering::visitCall(CallInst &I) {
3625 const char *RenameFn = 0;
3626 if (Function *F = I.getCalledFunction()) {
3627 if (F->isDeclaration()) {
3628 if (unsigned IID = F->getIntrinsicID()) {
3629 RenameFn = visitIntrinsicCall(I, IID);
3635 // Check for well-known libc/libm calls. If the function is internal, it
3636 // can't be a library call.
3637 unsigned NameLen = F->getNameLen();
3638 if (!F->hasInternalLinkage() && NameLen) {
3639 const char *NameStr = F->getNameStart();
3640 if (NameStr[0] == 'c' &&
3641 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3642 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3643 if (I.getNumOperands() == 3 && // Basic sanity checks.
3644 I.getOperand(1)->getType()->isFloatingPoint() &&
3645 I.getType() == I.getOperand(1)->getType() &&
3646 I.getType() == I.getOperand(2)->getType()) {
3647 SDValue LHS = getValue(I.getOperand(1));
3648 SDValue RHS = getValue(I.getOperand(2));
3649 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3653 } else if (NameStr[0] == 'f' &&
3654 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3655 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3656 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3657 if (I.getNumOperands() == 2 && // Basic sanity checks.
3658 I.getOperand(1)->getType()->isFloatingPoint() &&
3659 I.getType() == I.getOperand(1)->getType()) {
3660 SDValue Tmp = getValue(I.getOperand(1));
3661 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3664 } else if (NameStr[0] == 's' &&
3665 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3666 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3667 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3668 if (I.getNumOperands() == 2 && // Basic sanity checks.
3669 I.getOperand(1)->getType()->isFloatingPoint() &&
3670 I.getType() == I.getOperand(1)->getType()) {
3671 SDValue Tmp = getValue(I.getOperand(1));
3672 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3675 } else if (NameStr[0] == 'c' &&
3676 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3677 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3678 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3679 if (I.getNumOperands() == 2 && // Basic sanity checks.
3680 I.getOperand(1)->getType()->isFloatingPoint() &&
3681 I.getType() == I.getOperand(1)->getType()) {
3682 SDValue Tmp = getValue(I.getOperand(1));
3683 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3688 } else if (isa<InlineAsm>(I.getOperand(0))) {
3695 Callee = getValue(I.getOperand(0));
3697 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3699 LowerCallTo(&I, Callee, I.isTailCall());
3703 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3704 /// this value and returns the result as a ValueVT value. This uses
3705 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3706 /// If the Flag pointer is NULL, no flag is used.
3707 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3709 SDValue *Flag) const {
3710 // Assemble the legal parts into the final values.
3711 SmallVector<SDValue, 4> Values(ValueVTs.size());
3712 SmallVector<SDValue, 8> Parts;
3713 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3714 // Copy the legal parts from the registers.
3715 MVT ValueVT = ValueVTs[Value];
3716 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3717 MVT RegisterVT = RegVTs[Value];
3719 Parts.resize(NumRegs);
3720 for (unsigned i = 0; i != NumRegs; ++i) {
3723 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3725 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3726 *Flag = P.getValue(2);
3728 Chain = P.getValue(1);
3730 // If the source register was virtual and if we know something about it,
3731 // add an assert node.
3732 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3733 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3734 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3735 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3736 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3737 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3739 unsigned RegSize = RegisterVT.getSizeInBits();
3740 unsigned NumSignBits = LOI.NumSignBits;
3741 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3743 // FIXME: We capture more information than the dag can represent. For
3744 // now, just use the tightest assertzext/assertsext possible.
3746 MVT FromVT(MVT::Other);
3747 if (NumSignBits == RegSize)
3748 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3749 else if (NumZeroBits >= RegSize-1)
3750 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3751 else if (NumSignBits > RegSize-8)
3752 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3753 else if (NumZeroBits >= RegSize-9)
3754 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3755 else if (NumSignBits > RegSize-16)
3756 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3757 else if (NumZeroBits >= RegSize-17)
3758 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3759 else if (NumSignBits > RegSize-32)
3760 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3761 else if (NumZeroBits >= RegSize-33)
3762 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3764 if (FromVT != MVT::Other) {
3765 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3766 RegisterVT, P, DAG.getValueType(FromVT));
3775 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3780 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3781 &Values[0], ValueVTs.size());
3784 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3785 /// specified value into the registers specified by this object. This uses
3786 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3787 /// If the Flag pointer is NULL, no flag is used.
3788 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
3789 SDValue &Chain, SDValue *Flag) const {
3790 // Get the list of the values's legal parts.
3791 unsigned NumRegs = Regs.size();
3792 SmallVector<SDValue, 8> Parts(NumRegs);
3793 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3794 MVT ValueVT = ValueVTs[Value];
3795 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3796 MVT RegisterVT = RegVTs[Value];
3798 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3799 &Parts[Part], NumParts, RegisterVT);
3803 // Copy the parts into the registers.
3804 SmallVector<SDValue, 8> Chains(NumRegs);
3805 for (unsigned i = 0; i != NumRegs; ++i) {
3808 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3810 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3811 *Flag = Part.getValue(1);
3813 Chains[i] = Part.getValue(0);
3816 if (NumRegs == 1 || Flag)
3817 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3818 // flagged to it. That is the CopyToReg nodes and the user are considered
3819 // a single scheduling unit. If we create a TokenFactor and return it as
3820 // chain, then the TokenFactor is both a predecessor (operand) of the
3821 // user as well as a successor (the TF operands are flagged to the user).
3822 // c1, f1 = CopyToReg
3823 // c2, f2 = CopyToReg
3824 // c3 = TokenFactor c1, c2
3827 Chain = Chains[NumRegs-1];
3829 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3832 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3833 /// operand list. This adds the code marker and includes the number of
3834 /// values added into it.
3835 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3836 std::vector<SDValue> &Ops) const {
3837 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3838 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3839 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3840 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3841 MVT RegisterVT = RegVTs[Value];
3842 for (unsigned i = 0; i != NumRegs; ++i)
3843 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3847 /// isAllocatableRegister - If the specified register is safe to allocate,
3848 /// i.e. it isn't a stack pointer or some other special register, return the
3849 /// register class for the register. Otherwise, return null.
3850 static const TargetRegisterClass *
3851 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3852 const TargetLowering &TLI,
3853 const TargetRegisterInfo *TRI) {
3854 MVT FoundVT = MVT::Other;
3855 const TargetRegisterClass *FoundRC = 0;
3856 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3857 E = TRI->regclass_end(); RCI != E; ++RCI) {
3858 MVT ThisVT = MVT::Other;
3860 const TargetRegisterClass *RC = *RCI;
3861 // If none of the the value types for this register class are valid, we
3862 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3863 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3865 if (TLI.isTypeLegal(*I)) {
3866 // If we have already found this register in a different register class,
3867 // choose the one with the largest VT specified. For example, on
3868 // PowerPC, we favor f64 register classes over f32.
3869 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3876 if (ThisVT == MVT::Other) continue;
3878 // NOTE: This isn't ideal. In particular, this might allocate the
3879 // frame pointer in functions that need it (due to them not being taken
3880 // out of allocation, because a variable sized allocation hasn't been seen
3881 // yet). This is a slight code pessimization, but should still work.
3882 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3883 E = RC->allocation_order_end(MF); I != E; ++I)
3885 // We found a matching register class. Keep looking at others in case
3886 // we find one with larger registers that this physreg is also in.
3897 /// AsmOperandInfo - This contains information for each constraint that we are
3899 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3900 /// CallOperand - If this is the result output operand or a clobber
3901 /// this is null, otherwise it is the incoming operand to the CallInst.
3902 /// This gets modified as the asm is processed.
3903 SDValue CallOperand;
3905 /// AssignedRegs - If this is a register or register class operand, this
3906 /// contains the set of register corresponding to the operand.
3907 RegsForValue AssignedRegs;
3909 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3910 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3913 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3914 /// busy in OutputRegs/InputRegs.
3915 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3916 std::set<unsigned> &OutputRegs,
3917 std::set<unsigned> &InputRegs,
3918 const TargetRegisterInfo &TRI) const {
3920 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3921 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3924 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3925 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3930 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3932 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3933 const TargetRegisterInfo &TRI) {
3934 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3936 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3937 for (; *Aliases; ++Aliases)
3938 Regs.insert(*Aliases);
3941 } // end anon namespace.
3944 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3945 /// specified operand. We prefer to assign virtual registers, to allow the
3946 /// register allocator handle the assignment process. However, if the asm uses
3947 /// features that we can't model on machineinstrs, we have SDISel do the
3948 /// allocation. This produces generally horrible, but correct, code.
3950 /// OpInfo describes the operand.
3951 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3952 /// or any explicitly clobbered registers.
3953 /// Input and OutputRegs are the set of already allocated physical registers.
3955 void SelectionDAGLowering::
3956 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3957 std::set<unsigned> &OutputRegs,
3958 std::set<unsigned> &InputRegs) {
3959 // Compute whether this value requires an input register, an output register,
3961 bool isOutReg = false;
3962 bool isInReg = false;
3963 switch (OpInfo.Type) {
3964 case InlineAsm::isOutput:
3967 // If this is an early-clobber output, or if there is an input
3968 // constraint that matches this, we need to reserve the input register
3969 // so no other inputs allocate to it.
3970 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3972 case InlineAsm::isInput:
3976 case InlineAsm::isClobber:
3983 MachineFunction &MF = DAG.getMachineFunction();
3984 SmallVector<unsigned, 4> Regs;
3986 // If this is a constraint for a single physreg, or a constraint for a
3987 // register class, find it.
3988 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3989 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3990 OpInfo.ConstraintVT);
3992 unsigned NumRegs = 1;
3993 if (OpInfo.ConstraintVT != MVT::Other)
3994 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3996 MVT ValueVT = OpInfo.ConstraintVT;
3999 // If this is a constraint for a specific physical register, like {r17},
4001 if (PhysReg.first) {
4002 if (OpInfo.ConstraintVT == MVT::Other)
4003 ValueVT = *PhysReg.second->vt_begin();
4005 // Get the actual register value type. This is important, because the user
4006 // may have asked for (e.g.) the AX register in i32 type. We need to
4007 // remember that AX is actually i16 to get the right extension.
4008 RegVT = *PhysReg.second->vt_begin();
4010 // This is a explicit reference to a physical register.
4011 Regs.push_back(PhysReg.first);
4013 // If this is an expanded reference, add the rest of the regs to Regs.
4015 TargetRegisterClass::iterator I = PhysReg.second->begin();
4016 for (; *I != PhysReg.first; ++I)
4017 assert(I != PhysReg.second->end() && "Didn't find reg!");
4019 // Already added the first reg.
4021 for (; NumRegs; --NumRegs, ++I) {
4022 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4026 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4027 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4028 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4032 // Otherwise, if this was a reference to an LLVM register class, create vregs
4033 // for this reference.
4034 std::vector<unsigned> RegClassRegs;
4035 const TargetRegisterClass *RC = PhysReg.second;
4037 // If this is an early clobber or tied register, our regalloc doesn't know
4038 // how to maintain the constraint. If it isn't, go ahead and create vreg
4039 // and let the regalloc do the right thing.
4040 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4041 // If there is some other early clobber and this is an input register,
4042 // then we are forced to pre-allocate the input reg so it doesn't
4043 // conflict with the earlyclobber.
4044 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4045 RegVT = *PhysReg.second->vt_begin();
4047 if (OpInfo.ConstraintVT == MVT::Other)
4050 // Create the appropriate number of virtual registers.
4051 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4052 for (; NumRegs; --NumRegs)
4053 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4055 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4059 // Otherwise, we can't allocate it. Let the code below figure out how to
4060 // maintain these constraints.
4061 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4064 // This is a reference to a register class that doesn't directly correspond
4065 // to an LLVM register class. Allocate NumRegs consecutive, available,
4066 // registers from the class.
4067 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4068 OpInfo.ConstraintVT);
4071 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4072 unsigned NumAllocated = 0;
4073 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4074 unsigned Reg = RegClassRegs[i];
4075 // See if this register is available.
4076 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4077 (isInReg && InputRegs.count(Reg))) { // Already used.
4078 // Make sure we find consecutive registers.
4083 // Check to see if this register is allocatable (i.e. don't give out the
4086 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4087 if (!RC) { // Couldn't allocate this register.
4088 // Reset NumAllocated to make sure we return consecutive registers.
4094 // Okay, this register is good, we can use it.
4097 // If we allocated enough consecutive registers, succeed.
4098 if (NumAllocated == NumRegs) {
4099 unsigned RegStart = (i-NumAllocated)+1;
4100 unsigned RegEnd = i+1;
4101 // Mark all of the allocated registers used.
4102 for (unsigned i = RegStart; i != RegEnd; ++i)
4103 Regs.push_back(RegClassRegs[i]);
4105 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4106 OpInfo.ConstraintVT);
4107 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4112 // Otherwise, we couldn't allocate enough registers for this.
4116 /// visitInlineAsm - Handle a call to an InlineAsm object.
4118 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4119 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4121 /// ConstraintOperands - Information about all of the constraints.
4122 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4124 SDValue Chain = getRoot();
4127 std::set<unsigned> OutputRegs, InputRegs;
4129 // Do a prepass over the constraints, canonicalizing them, and building up the
4130 // ConstraintOperands list.
4131 std::vector<InlineAsm::ConstraintInfo>
4132 ConstraintInfos = IA->ParseConstraints();
4134 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4135 // constraint. If so, we can't let the register allocator allocate any input
4136 // registers, because it will not know to avoid the earlyclobbered output reg.
4137 bool SawEarlyClobber = false;
4139 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4140 unsigned ResNo = 0; // ResNo - The result number of the next output.
4141 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4142 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4143 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4145 MVT OpVT = MVT::Other;
4147 // Compute the value type for each operand.
4148 switch (OpInfo.Type) {
4149 case InlineAsm::isOutput:
4150 // Indirect outputs just consume an argument.
4151 if (OpInfo.isIndirect) {
4152 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4155 // The return value of the call is this value. As such, there is no
4156 // corresponding argument.
4157 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4158 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4159 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4161 assert(ResNo == 0 && "Asm only has one result!");
4162 OpVT = TLI.getValueType(CS.getType());
4166 case InlineAsm::isInput:
4167 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4169 case InlineAsm::isClobber:
4174 // If this is an input or an indirect output, process the call argument.
4175 // BasicBlocks are labels, currently appearing only in asm's.
4176 if (OpInfo.CallOperandVal) {
4177 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4178 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4180 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4181 const Type *OpTy = OpInfo.CallOperandVal->getType();
4182 // If this is an indirect operand, the operand is a pointer to the
4184 if (OpInfo.isIndirect)
4185 OpTy = cast<PointerType>(OpTy)->getElementType();
4187 // If OpTy is not a single value, it may be a struct/union that we
4188 // can tile with integers.
4189 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4190 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4198 OpTy = IntegerType::get(BitSize);
4203 OpVT = TLI.getValueType(OpTy, true);
4207 OpInfo.ConstraintVT = OpVT;
4209 // Compute the constraint code and ConstraintType to use.
4210 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4212 // Keep track of whether we see an earlyclobber.
4213 SawEarlyClobber |= OpInfo.isEarlyClobber;
4215 // If we see a clobber of a register, it is an early clobber.
4216 if (!SawEarlyClobber &&
4217 OpInfo.Type == InlineAsm::isClobber &&
4218 OpInfo.ConstraintType == TargetLowering::C_Register) {
4219 // Note that we want to ignore things that we don't trick here, like
4220 // dirflag, fpsr, flags, etc.
4221 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4222 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4223 OpInfo.ConstraintVT);
4224 if (PhysReg.first || PhysReg.second) {
4225 // This is a register we know of.
4226 SawEarlyClobber = true;
4230 // If this is a memory input, and if the operand is not indirect, do what we
4231 // need to to provide an address for the memory input.
4232 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4233 !OpInfo.isIndirect) {
4234 assert(OpInfo.Type == InlineAsm::isInput &&
4235 "Can only indirectify direct input operands!");
4237 // Memory operands really want the address of the value. If we don't have
4238 // an indirect input, put it in the constpool if we can, otherwise spill
4239 // it to a stack slot.
4241 // If the operand is a float, integer, or vector constant, spill to a
4242 // constant pool entry to get its address.
4243 Value *OpVal = OpInfo.CallOperandVal;
4244 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4245 isa<ConstantVector>(OpVal)) {
4246 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4247 TLI.getPointerTy());
4249 // Otherwise, create a stack slot and emit a store to it before the
4251 const Type *Ty = OpVal->getType();
4252 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4253 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4254 MachineFunction &MF = DAG.getMachineFunction();
4255 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4256 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4257 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4258 OpInfo.CallOperand = StackSlot;
4261 // There is no longer a Value* corresponding to this operand.
4262 OpInfo.CallOperandVal = 0;
4263 // It is now an indirect operand.
4264 OpInfo.isIndirect = true;
4267 // If this constraint is for a specific register, allocate it before
4269 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4270 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4272 ConstraintInfos.clear();
4275 // Second pass - Loop over all of the operands, assigning virtual or physregs
4276 // to registerclass operands.
4277 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4278 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4280 // C_Register operands have already been allocated, Other/Memory don't need
4282 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4283 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4286 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4287 std::vector<SDValue> AsmNodeOperands;
4288 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
4289 AsmNodeOperands.push_back(
4290 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4293 // Loop over all of the inputs, copying the operand values into the
4294 // appropriate registers and processing the output regs.
4295 RegsForValue RetValRegs;
4297 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4298 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4300 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4301 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4303 switch (OpInfo.Type) {
4304 case InlineAsm::isOutput: {
4305 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4306 OpInfo.ConstraintType != TargetLowering::C_Register) {
4307 // Memory output, or 'other' output (e.g. 'X' constraint).
4308 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4310 // Add information to the INLINEASM node to know about this output.
4311 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4312 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4313 TLI.getPointerTy()));
4314 AsmNodeOperands.push_back(OpInfo.CallOperand);
4318 // Otherwise, this is a register or register class output.
4320 // Copy the output from the appropriate register. Find a register that
4322 if (OpInfo.AssignedRegs.Regs.empty()) {
4323 cerr << "Couldn't allocate output reg for constraint '"
4324 << OpInfo.ConstraintCode << "'!\n";
4328 // If this is an indirect operand, store through the pointer after the
4330 if (OpInfo.isIndirect) {
4331 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4332 OpInfo.CallOperandVal));
4334 // This is the result value of the call.
4335 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4336 // Concatenate this output onto the outputs list.
4337 RetValRegs.append(OpInfo.AssignedRegs);
4340 // Add information to the INLINEASM node to know that this register is
4342 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4346 case InlineAsm::isInput: {
4347 SDValue InOperandVal = OpInfo.CallOperand;
4349 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4350 // If this is required to match an output register we have already set,
4351 // just use its register.
4352 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4354 // Scan until we find the definition we already emitted of this operand.
4355 // When we find it, create a RegsForValue operand.
4356 unsigned CurOp = 2; // The first operand.
4357 for (; OperandNo; --OperandNo) {
4358 // Advance to the next operand.
4360 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4361 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4362 (NumOps & 7) == 4 /*MEM*/) &&
4363 "Skipped past definitions?");
4364 CurOp += (NumOps>>3)+1;
4368 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4369 if ((NumOps & 7) == 2 /*REGDEF*/) {
4370 // Add NumOps>>3 registers to MatchedRegs.
4371 RegsForValue MatchedRegs;
4372 MatchedRegs.TLI = &TLI;
4373 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4374 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4375 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4377 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4378 MatchedRegs.Regs.push_back(Reg);
4381 // Use the produced MatchedRegs object to
4382 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4383 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4386 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4387 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4388 // Add information to the INLINEASM node to know about this input.
4389 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4390 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4391 TLI.getPointerTy()));
4392 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4397 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4398 assert(!OpInfo.isIndirect &&
4399 "Don't know how to handle indirect other inputs yet!");
4401 std::vector<SDValue> Ops;
4402 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4405 cerr << "Invalid operand for inline asm constraint '"
4406 << OpInfo.ConstraintCode << "'!\n";
4410 // Add information to the INLINEASM node to know about this input.
4411 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4412 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4413 TLI.getPointerTy()));
4414 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4416 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4417 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4418 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4419 "Memory operands expect pointer values");
4421 // Add information to the INLINEASM node to know about this input.
4422 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4423 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4424 TLI.getPointerTy()));
4425 AsmNodeOperands.push_back(InOperandVal);
4429 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4430 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4431 "Unknown constraint type!");
4432 assert(!OpInfo.isIndirect &&
4433 "Don't know how to handle indirect register inputs yet!");
4435 // Copy the input into the appropriate registers.
4436 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4437 "Couldn't allocate input reg!");
4439 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4441 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4445 case InlineAsm::isClobber: {
4446 // Add the clobbered value to the operand list, so that the register
4447 // allocator is aware that the physreg got clobbered.
4448 if (!OpInfo.AssignedRegs.Regs.empty())
4449 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4456 // Finish up input operands.
4457 AsmNodeOperands[0] = Chain;
4458 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4460 Chain = DAG.getNode(ISD::INLINEASM,
4461 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4462 &AsmNodeOperands[0], AsmNodeOperands.size());
4463 Flag = Chain.getValue(1);
4465 // If this asm returns a register value, copy the result from that register
4466 // and set it as the value of the call.
4467 if (!RetValRegs.Regs.empty()) {
4468 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4470 // If any of the results of the inline asm is a vector, it may have the
4471 // wrong width/num elts. This can happen for register classes that can
4472 // contain multiple different value types. The preg or vreg allocated may
4473 // not have the same VT as was expected. Convert it to the right type with
4475 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4476 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4477 if (Val.Val->getValueType(i).isVector())
4478 Val = DAG.getNode(ISD::BIT_CONVERT,
4479 TLI.getValueType(ResSTy->getElementType(i)), Val);
4482 if (Val.getValueType().isVector())
4483 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4487 setValue(CS.getInstruction(), Val);
4490 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
4492 // Process indirect outputs, first output all of the flagged copies out of
4494 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4495 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4496 Value *Ptr = IndirectStoresToEmit[i].second;
4497 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4498 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4501 // Emit the non-flagged stores from the physregs.
4502 SmallVector<SDValue, 8> OutChains;
4503 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4504 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4505 getValue(StoresToEmit[i].second),
4506 StoresToEmit[i].second, 0));
4507 if (!OutChains.empty())
4508 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4509 &OutChains[0], OutChains.size());
4514 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4515 SDValue Src = getValue(I.getOperand(0));
4517 MVT IntPtr = TLI.getPointerTy();
4519 if (IntPtr.bitsLT(Src.getValueType()))
4520 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4521 else if (IntPtr.bitsGT(Src.getValueType()))
4522 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4524 // Scale the source by the type size.
4525 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4526 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4527 Src, DAG.getIntPtrConstant(ElementSize));
4529 TargetLowering::ArgListTy Args;
4530 TargetLowering::ArgListEntry Entry;
4532 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4533 Args.push_back(Entry);
4535 std::pair<SDValue,SDValue> Result =
4536 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4537 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4538 setValue(&I, Result.first); // Pointers always fit in registers
4539 DAG.setRoot(Result.second);
4542 void SelectionDAGLowering::visitFree(FreeInst &I) {
4543 TargetLowering::ArgListTy Args;
4544 TargetLowering::ArgListEntry Entry;
4545 Entry.Node = getValue(I.getOperand(0));
4546 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4547 Args.push_back(Entry);
4548 MVT IntPtr = TLI.getPointerTy();
4549 std::pair<SDValue,SDValue> Result =
4550 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4551 CallingConv::C, true,
4552 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4553 DAG.setRoot(Result.second);
4556 // EmitInstrWithCustomInserter - This method should be implemented by targets
4557 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4558 // instructions are special in various ways, which require special support to
4559 // insert. The specified MachineInstr is created but not inserted into any
4560 // basic blocks, and the scheduler passes ownership of it to this method.
4561 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4562 MachineBasicBlock *MBB) {
4563 cerr << "If a target marks an instruction with "
4564 << "'usesCustomDAGSchedInserter', it must implement "
4565 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4570 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4571 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4572 getValue(I.getOperand(1)),
4573 DAG.getSrcValue(I.getOperand(1))));
4576 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4577 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4578 getValue(I.getOperand(0)),
4579 DAG.getSrcValue(I.getOperand(0)));
4581 DAG.setRoot(V.getValue(1));
4584 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4585 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4586 getValue(I.getOperand(1)),
4587 DAG.getSrcValue(I.getOperand(1))));
4590 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4591 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4592 getValue(I.getOperand(1)),
4593 getValue(I.getOperand(2)),
4594 DAG.getSrcValue(I.getOperand(1)),
4595 DAG.getSrcValue(I.getOperand(2))));
4598 /// TargetLowering::LowerArguments - This is the default LowerArguments
4599 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4600 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4601 /// integrated into SDISel.
4602 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4603 SmallVectorImpl<SDValue> &ArgValues) {
4604 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4605 SmallVector<SDValue, 3+16> Ops;
4606 Ops.push_back(DAG.getRoot());
4607 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4608 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4610 // Add one result value for each formal argument.
4611 SmallVector<MVT, 16> RetVals;
4613 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4615 SmallVector<MVT, 4> ValueVTs;
4616 ComputeValueVTs(*this, I->getType(), ValueVTs);
4617 for (unsigned Value = 0, NumValues = ValueVTs.size();
4618 Value != NumValues; ++Value) {
4619 MVT VT = ValueVTs[Value];
4620 const Type *ArgTy = VT.getTypeForMVT();
4621 ISD::ArgFlagsTy Flags;
4622 unsigned OriginalAlignment =
4623 getTargetData()->getABITypeAlignment(ArgTy);
4625 if (F.paramHasAttr(j, ParamAttr::ZExt))
4627 if (F.paramHasAttr(j, ParamAttr::SExt))
4629 if (F.paramHasAttr(j, ParamAttr::InReg))
4631 if (F.paramHasAttr(j, ParamAttr::StructRet))
4633 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4635 const PointerType *Ty = cast<PointerType>(I->getType());
4636 const Type *ElementTy = Ty->getElementType();
4637 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4638 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4639 // For ByVal, alignment should be passed from FE. BE will guess if
4640 // this info is not there but there are cases it cannot get right.
4641 if (F.getParamAlignment(j))
4642 FrameAlign = F.getParamAlignment(j);
4643 Flags.setByValAlign(FrameAlign);
4644 Flags.setByValSize(FrameSize);
4646 if (F.paramHasAttr(j, ParamAttr::Nest))
4648 Flags.setOrigAlign(OriginalAlignment);
4650 MVT RegisterVT = getRegisterType(VT);
4651 unsigned NumRegs = getNumRegisters(VT);
4652 for (unsigned i = 0; i != NumRegs; ++i) {
4653 RetVals.push_back(RegisterVT);
4654 ISD::ArgFlagsTy MyFlags = Flags;
4655 if (NumRegs > 1 && i == 0)
4657 // if it isn't first piece, alignment must be 1
4659 MyFlags.setOrigAlign(1);
4660 Ops.push_back(DAG.getArgFlags(MyFlags));
4665 RetVals.push_back(MVT::Other);
4668 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4669 DAG.getVTList(&RetVals[0], RetVals.size()),
4670 &Ops[0], Ops.size()).Val;
4672 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4673 // allows exposing the loads that may be part of the argument access to the
4674 // first DAGCombiner pass.
4675 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
4677 // The number of results should match up, except that the lowered one may have
4678 // an extra flag result.
4679 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4680 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4681 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4682 && "Lowering produced unexpected number of results!");
4684 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
4685 if (Result != TmpRes.Val && Result->use_empty()) {
4686 HandleSDNode Dummy(DAG.getRoot());
4687 DAG.RemoveDeadNode(Result);
4690 Result = TmpRes.Val;
4692 unsigned NumArgRegs = Result->getNumValues() - 1;
4693 DAG.setRoot(SDValue(Result, NumArgRegs));
4695 // Set up the return result vector.
4698 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4700 SmallVector<MVT, 4> ValueVTs;
4701 ComputeValueVTs(*this, I->getType(), ValueVTs);
4702 for (unsigned Value = 0, NumValues = ValueVTs.size();
4703 Value != NumValues; ++Value) {
4704 MVT VT = ValueVTs[Value];
4705 MVT PartVT = getRegisterType(VT);
4707 unsigned NumParts = getNumRegisters(VT);
4708 SmallVector<SDValue, 4> Parts(NumParts);
4709 for (unsigned j = 0; j != NumParts; ++j)
4710 Parts[j] = SDValue(Result, i++);
4712 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4713 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4714 AssertOp = ISD::AssertSext;
4715 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4716 AssertOp = ISD::AssertZext;
4718 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4722 assert(i == NumArgRegs && "Argument register count mismatch!");
4726 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4727 /// implementation, which just inserts an ISD::CALL node, which is later custom
4728 /// lowered by the target to something concrete. FIXME: When all targets are
4729 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4730 std::pair<SDValue, SDValue>
4731 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
4732 bool RetSExt, bool RetZExt, bool isVarArg,
4733 unsigned CallingConv, bool isTailCall,
4735 ArgListTy &Args, SelectionDAG &DAG) {
4736 SmallVector<SDValue, 32> Ops;
4737 Ops.push_back(Chain); // Op#0 - Chain
4738 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4739 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4740 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4741 Ops.push_back(Callee);
4743 // Handle all of the outgoing arguments.
4744 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4745 SmallVector<MVT, 4> ValueVTs;
4746 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4747 for (unsigned Value = 0, NumValues = ValueVTs.size();
4748 Value != NumValues; ++Value) {
4749 MVT VT = ValueVTs[Value];
4750 const Type *ArgTy = VT.getTypeForMVT();
4751 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4752 ISD::ArgFlagsTy Flags;
4753 unsigned OriginalAlignment =
4754 getTargetData()->getABITypeAlignment(ArgTy);
4760 if (Args[i].isInReg)
4764 if (Args[i].isByVal) {
4766 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4767 const Type *ElementTy = Ty->getElementType();
4768 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4769 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4770 // For ByVal, alignment should come from FE. BE will guess if this
4771 // info is not there but there are cases it cannot get right.
4772 if (Args[i].Alignment)
4773 FrameAlign = Args[i].Alignment;
4774 Flags.setByValAlign(FrameAlign);
4775 Flags.setByValSize(FrameSize);
4779 Flags.setOrigAlign(OriginalAlignment);
4781 MVT PartVT = getRegisterType(VT);
4782 unsigned NumParts = getNumRegisters(VT);
4783 SmallVector<SDValue, 4> Parts(NumParts);
4784 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4787 ExtendKind = ISD::SIGN_EXTEND;
4788 else if (Args[i].isZExt)
4789 ExtendKind = ISD::ZERO_EXTEND;
4791 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4793 for (unsigned i = 0; i != NumParts; ++i) {
4794 // if it isn't first piece, alignment must be 1
4795 ISD::ArgFlagsTy MyFlags = Flags;
4796 if (NumParts > 1 && i == 0)
4799 MyFlags.setOrigAlign(1);
4801 Ops.push_back(Parts[i]);
4802 Ops.push_back(DAG.getArgFlags(MyFlags));
4807 // Figure out the result value types. We start by making a list of
4808 // the potentially illegal return value types.
4809 SmallVector<MVT, 4> LoweredRetTys;
4810 SmallVector<MVT, 4> RetTys;
4811 ComputeValueVTs(*this, RetTy, RetTys);
4813 // Then we translate that to a list of legal types.
4814 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4816 MVT RegisterVT = getRegisterType(VT);
4817 unsigned NumRegs = getNumRegisters(VT);
4818 for (unsigned i = 0; i != NumRegs; ++i)
4819 LoweredRetTys.push_back(RegisterVT);
4822 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4824 // Create the CALL node.
4825 SDValue Res = DAG.getNode(ISD::CALL,
4826 DAG.getVTList(&LoweredRetTys[0],
4827 LoweredRetTys.size()),
4828 &Ops[0], Ops.size());
4829 Chain = Res.getValue(LoweredRetTys.size() - 1);
4831 // Gather up the call result into a single value.
4832 if (RetTy != Type::VoidTy) {
4833 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4836 AssertOp = ISD::AssertSext;
4838 AssertOp = ISD::AssertZext;
4840 SmallVector<SDValue, 4> ReturnValues;
4842 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4844 MVT RegisterVT = getRegisterType(VT);
4845 unsigned NumRegs = getNumRegisters(VT);
4846 unsigned RegNoEnd = NumRegs + RegNo;
4847 SmallVector<SDValue, 4> Results;
4848 for (; RegNo != RegNoEnd; ++RegNo)
4849 Results.push_back(Res.getValue(RegNo));
4850 SDValue ReturnValue =
4851 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4853 ReturnValues.push_back(ReturnValue);
4855 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4856 &ReturnValues[0], ReturnValues.size());
4859 return std::make_pair(Res, Chain);
4862 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4863 assert(0 && "LowerOperation not implemented for this target!");
4869 //===----------------------------------------------------------------------===//
4870 // SelectionDAGISel code
4871 //===----------------------------------------------------------------------===//
4873 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4874 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4877 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4878 AU.addRequired<AliasAnalysis>();
4879 AU.addRequired<CollectorModuleMetadata>();
4880 AU.setPreservesAll();
4883 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4884 // Get alias analysis for load/store combining.
4885 AA = &getAnalysis<AliasAnalysis>();
4887 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4888 if (MF.getFunction()->hasCollector())
4889 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4892 RegInfo = &MF.getRegInfo();
4893 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4895 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4897 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4898 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4899 // Mark landing pad.
4900 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4902 SelectAllBasicBlocks(Fn, MF, FuncInfo);
4904 // Add function live-ins to entry block live-in set.
4905 BasicBlock *EntryBB = &Fn.getEntryBlock();
4906 BB = FuncInfo.MBBMap[EntryBB];
4907 if (!RegInfo->livein_empty())
4908 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4909 E = RegInfo->livein_end(); I != E; ++I)
4910 BB->addLiveIn(I->first);
4913 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4914 "Not all catch info was assigned to a landing pad!");
4920 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4921 SDValue Op = getValue(V);
4922 assert((Op.getOpcode() != ISD::CopyFromReg ||
4923 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4924 "Copy from a reg to the same reg!");
4925 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4927 RegsForValue RFV(TLI, Reg, V->getType());
4928 SDValue Chain = DAG.getEntryNode();
4929 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4930 PendingExports.push_back(Chain);
4933 void SelectionDAGISel::
4934 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4935 // If this is the entry block, emit arguments.
4936 Function &F = *LLVMBB->getParent();
4937 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4938 SDValue OldRoot = SDL.DAG.getRoot();
4939 SmallVector<SDValue, 16> Args;
4940 TLI.LowerArguments(F, SDL.DAG, Args);
4943 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4945 SmallVector<MVT, 4> ValueVTs;
4946 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4947 unsigned NumValues = ValueVTs.size();
4948 if (!AI->use_empty()) {
4949 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
4950 // If this argument is live outside of the entry block, insert a copy from
4951 // whereever we got it to the vreg that other BB's will reference it as.
4952 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4953 if (VMI != FuncInfo.ValueMap.end()) {
4954 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4960 // Finally, if the target has anything special to do, allow it to do so.
4961 // FIXME: this should insert code into the DAG!
4962 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4965 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4966 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4967 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4968 if (isSelector(I)) {
4969 // Apply the catch info to DestBB.
4970 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4972 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4973 FLI.CatchInfoFound.insert(I);
4978 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4979 /// whether object offset >= 0.
4981 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
4982 if (!isa<FrameIndexSDNode>(Op)) return false;
4984 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4985 int FrameIdx = FrameIdxNode->getIndex();
4986 return MFI->isFixedObjectIndex(FrameIdx) &&
4987 MFI->getObjectOffset(FrameIdx) >= 0;
4990 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
4991 /// possibly be overwritten when lowering the outgoing arguments in a tail
4992 /// call. Currently the implementation of this call is very conservative and
4993 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
4994 /// virtual registers would be overwritten by direct lowering.
4995 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
4996 MachineFrameInfo * MFI) {
4997 RegisterSDNode * OpReg = NULL;
4998 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
4999 (Op.getOpcode()== ISD::CopyFromReg &&
5000 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
5001 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
5002 (Op.getOpcode() == ISD::LOAD &&
5003 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
5004 (Op.getOpcode() == ISD::MERGE_VALUES &&
5005 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
5006 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
5012 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
5013 /// DAG and fixes their tailcall attribute operand.
5014 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
5015 TargetLowering& TLI) {
5016 SDNode * Ret = NULL;
5017 SDValue Terminator = DAG.getRoot();
5020 if (Terminator.getOpcode() == ISD::RET) {
5021 Ret = Terminator.Val;
5024 // Fix tail call attribute of CALL nodes.
5025 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5026 BI = DAG.allnodes_end(); BI != BE; ) {
5028 if (BI->getOpcode() == ISD::CALL) {
5029 SDValue OpRet(Ret, 0);
5030 SDValue OpCall(BI, 0);
5031 bool isMarkedTailCall =
5032 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5033 // If CALL node has tail call attribute set to true and the call is not
5034 // eligible (no RET or the target rejects) the attribute is fixed to
5035 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5036 // must correctly identify tail call optimizable calls.
5037 if (!isMarkedTailCall) continue;
5039 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5040 // Not eligible. Mark CALL node as non tail call.
5041 SmallVector<SDValue, 32> Ops;
5043 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5044 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5048 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5050 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5052 // Look for tail call clobbered arguments. Emit a series of
5053 // copyto/copyfrom virtual register nodes to protect them.
5054 SmallVector<SDValue, 32> Ops;
5055 SDValue Chain = OpCall.getOperand(0), InFlag;
5057 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5058 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5060 if (idx > 4 && (idx % 2)) {
5061 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5062 getArgFlags().isByVal();
5063 MachineFunction &MF = DAG.getMachineFunction();
5064 MachineFrameInfo *MFI = MF.getFrameInfo();
5066 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5067 MVT VT = Arg.getValueType();
5068 unsigned VReg = MF.getRegInfo().
5069 createVirtualRegister(TLI.getRegClassFor(VT));
5070 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5071 InFlag = Chain.getValue(1);
5072 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5073 Chain = Arg.getValue(1);
5074 InFlag = Arg.getValue(2);
5079 // Link in chain of CopyTo/CopyFromReg.
5081 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5087 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5088 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5089 FunctionLoweringInfo &FuncInfo) {
5090 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
5092 // Lower any arguments needed in this block if this is the entry block.
5093 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5094 LowerArguments(LLVMBB, SDL);
5096 BB = FuncInfo.MBBMap[LLVMBB];
5097 SDL.setCurrentBasicBlock(BB);
5099 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5101 if (MMI && BB->isLandingPad()) {
5102 // Add a label to mark the beginning of the landing pad. Deletion of the
5103 // landing pad can thus be detected via the MachineModuleInfo.
5104 unsigned LabelID = MMI->addLandingPad(BB);
5105 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
5107 // Mark exception register as live in.
5108 unsigned Reg = TLI.getExceptionAddressRegister();
5109 if (Reg) BB->addLiveIn(Reg);
5111 // Mark exception selector register as live in.
5112 Reg = TLI.getExceptionSelectorRegister();
5113 if (Reg) BB->addLiveIn(Reg);
5115 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5116 // function and list of typeids logically belong to the invoke (or, if you
5117 // like, the basic block containing the invoke), and need to be associated
5118 // with it in the dwarf exception handling tables. Currently however the
5119 // information is provided by an intrinsic (eh.selector) that can be moved
5120 // to unexpected places by the optimizers: if the unwind edge is critical,
5121 // then breaking it can result in the intrinsics being in the successor of
5122 // the landing pad, not the landing pad itself. This results in exceptions
5123 // not being caught because no typeids are associated with the invoke.
5124 // This may not be the only way things can go wrong, but it is the only way
5125 // we try to work around for the moment.
5126 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5128 if (Br && Br->isUnconditional()) { // Critical edge?
5129 BasicBlock::iterator I, E;
5130 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5135 // No catch info found - try to extract some from the successor.
5136 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5140 // Lower all of the non-terminator instructions.
5141 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
5145 // Ensure that all instructions which are used outside of their defining
5146 // blocks are available as virtual registers. Invoke is handled elsewhere.
5147 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
5148 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5149 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5150 if (VMI != FuncInfo.ValueMap.end())
5151 SDL.CopyValueToVirtualRegister(I, VMI->second);
5154 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5155 // ensure constants are generated when needed. Remember the virtual registers
5156 // that need to be added to the Machine PHI nodes as input. We cannot just
5157 // directly add them, because expansion might result in multiple MBB's for one
5158 // BB. As such, the start of the BB might correspond to a different MBB than
5161 TerminatorInst *TI = LLVMBB->getTerminator();
5163 // Emit constants only once even if used by multiple PHI nodes.
5164 std::map<Constant*, unsigned> ConstantsOut;
5166 // Vector bool would be better, but vector<bool> is really slow.
5167 std::vector<unsigned char> SuccsHandled;
5168 if (TI->getNumSuccessors())
5169 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5171 // Check successor nodes' PHI nodes that expect a constant to be available
5173 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5174 BasicBlock *SuccBB = TI->getSuccessor(succ);
5175 if (!isa<PHINode>(SuccBB->begin())) continue;
5176 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5178 // If this terminator has multiple identical successors (common for
5179 // switches), only handle each succ once.
5180 unsigned SuccMBBNo = SuccMBB->getNumber();
5181 if (SuccsHandled[SuccMBBNo]) continue;
5182 SuccsHandled[SuccMBBNo] = true;
5184 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5187 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5188 // nodes and Machine PHI nodes, but the incoming operands have not been
5190 for (BasicBlock::iterator I = SuccBB->begin();
5191 (PN = dyn_cast<PHINode>(I)); ++I) {
5192 // Ignore dead phi's.
5193 if (PN->use_empty()) continue;
5196 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5198 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5199 unsigned &RegOut = ConstantsOut[C];
5201 RegOut = FuncInfo.CreateRegForValue(C);
5202 SDL.CopyValueToVirtualRegister(C, RegOut);
5206 Reg = FuncInfo.ValueMap[PHIOp];
5208 assert(isa<AllocaInst>(PHIOp) &&
5209 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5210 "Didn't codegen value into a register!??");
5211 Reg = FuncInfo.CreateRegForValue(PHIOp);
5212 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5216 // Remember that this register needs to added to the machine PHI node as
5217 // the input for this MBB.
5218 MVT VT = TLI.getValueType(PN->getType());
5219 unsigned NumRegisters = TLI.getNumRegisters(VT);
5220 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5221 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5224 ConstantsOut.clear();
5226 // Lower the terminator after the copies are emitted.
5227 SDL.visit(*LLVMBB->getTerminator());
5229 // Copy over any CaseBlock records that may now exist due to SwitchInst
5230 // lowering, as well as any jump table information.
5231 SwitchCases.clear();
5232 SwitchCases = SDL.SwitchCases;
5234 JTCases = SDL.JTCases;
5235 BitTestCases.clear();
5236 BitTestCases = SDL.BitTestCases;
5238 // Make sure the root of the DAG is up-to-date.
5239 DAG.setRoot(SDL.getControlRoot());
5241 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5242 // with correct tailcall attribute so that the target can rely on the tailcall
5243 // attribute indicating whether the call is really eligible for tail call
5245 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5248 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5249 SmallPtrSet<SDNode*, 128> VisitedNodes;
5250 SmallVector<SDNode*, 128> Worklist;
5252 Worklist.push_back(DAG.getRoot().Val);
5258 while (!Worklist.empty()) {
5259 SDNode *N = Worklist.back();
5260 Worklist.pop_back();
5262 // If we've already seen this node, ignore it.
5263 if (!VisitedNodes.insert(N))
5266 // Otherwise, add all chain operands to the worklist.
5267 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5268 if (N->getOperand(i).getValueType() == MVT::Other)
5269 Worklist.push_back(N->getOperand(i).Val);
5271 // If this is a CopyToReg with a vreg dest, process it.
5272 if (N->getOpcode() != ISD::CopyToReg)
5275 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5276 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5279 // Ignore non-scalar or non-integer values.
5280 SDValue Src = N->getOperand(2);
5281 MVT SrcVT = Src.getValueType();
5282 if (!SrcVT.isInteger() || SrcVT.isVector())
5285 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5286 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5287 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5289 // Only install this information if it tells us something.
5290 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5291 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5292 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5293 if (DestReg >= FLI.LiveOutRegInfo.size())
5294 FLI.LiveOutRegInfo.resize(DestReg+1);
5295 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5296 LOI.NumSignBits = NumSignBits;
5297 LOI.KnownOne = NumSignBits;
5298 LOI.KnownZero = NumSignBits;
5303 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5304 std::string GroupName;
5305 if (TimePassesIsEnabled)
5306 GroupName = "Instruction Selection and Scheduling";
5307 std::string BlockName;
5308 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
5309 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
5310 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' +
5311 BB->getBasicBlock()->getName();
5313 DOUT << "Initial selection DAG:\n";
5316 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName);
5318 // Run the DAG combiner in pre-legalize mode.
5319 if (TimePassesIsEnabled) {
5320 NamedRegionTimer T("DAG Combining 1", GroupName);
5321 DAG.Combine(false, *AA);
5323 DAG.Combine(false, *AA);
5326 DOUT << "Optimized lowered selection DAG:\n";
5329 // Second step, hack on the DAG until it only uses operations and types that
5330 // the target supports.
5331 if (EnableLegalizeTypes) {// Enable this some day.
5332 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " +
5335 if (TimePassesIsEnabled) {
5336 NamedRegionTimer T("Type Legalization", GroupName);
5337 DAG.LegalizeTypes();
5339 DAG.LegalizeTypes();
5342 DOUT << "Type-legalized selection DAG:\n";
5345 // TODO: enable a dag combine pass here.
5348 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName);
5350 if (TimePassesIsEnabled) {
5351 NamedRegionTimer T("DAG Legalization", GroupName);
5357 DOUT << "Legalized selection DAG:\n";
5360 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName);
5362 // Run the DAG combiner in post-legalize mode.
5363 if (TimePassesIsEnabled) {
5364 NamedRegionTimer T("DAG Combining 2", GroupName);
5365 DAG.Combine(true, *AA);
5367 DAG.Combine(true, *AA);
5370 DOUT << "Optimized legalized selection DAG:\n";
5373 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
5375 if (!FastISel && EnableValueProp)
5376 ComputeLiveOutVRegInfo(DAG);
5378 // Third, instruction select all of the operations to machine code, adding the
5379 // code to the MachineBasicBlock.
5380 if (TimePassesIsEnabled) {
5381 NamedRegionTimer T("Instruction Selection", GroupName);
5382 InstructionSelect(DAG);
5384 InstructionSelect(DAG);
5387 DOUT << "Selected selection DAG:\n";
5390 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName);
5392 // Schedule machine code.
5393 ScheduleDAG *Scheduler;
5394 if (TimePassesIsEnabled) {
5395 NamedRegionTimer T("Instruction Scheduling", GroupName);
5396 Scheduler = Schedule(DAG);
5398 Scheduler = Schedule(DAG);
5401 if (ViewSUnitDAGs) Scheduler->viewGraph();
5403 // Emit machine code to BB. This can change 'BB' to the last block being
5405 if (TimePassesIsEnabled) {
5406 NamedRegionTimer T("Instruction Creation", GroupName);
5407 BB = Scheduler->EmitSchedule();
5409 BB = Scheduler->EmitSchedule();
5412 // Free the scheduler state.
5413 if (TimePassesIsEnabled) {
5414 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
5420 // Perform target specific isel post processing.
5421 if (TimePassesIsEnabled) {
5422 NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
5423 InstructionSelectPostProcessing();
5425 InstructionSelectPostProcessing();
5428 DOUT << "Selected machine code:\n";
5432 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
5433 FunctionLoweringInfo &FuncInfo) {
5434 // Define NodeAllocator here so that memory allocation is reused for
5435 // each basic block.
5436 NodeAllocatorType NodeAllocator;
5438 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
5439 SelectBasicBlock(I, MF, FuncInfo, NodeAllocator);
5443 SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5444 FunctionLoweringInfo &FuncInfo,
5445 NodeAllocatorType &NodeAllocator) {
5446 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5448 SelectionDAG DAG(TLI, MF, FuncInfo,
5449 getAnalysisToUpdate<MachineModuleInfo>(),
5453 // First step, lower LLVM code to some DAG. This DAG may use operations and
5454 // types that are not supported by the target.
5455 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5457 // Second step, emit the lowered DAG as machine code.
5458 CodeGenAndEmitDAG(DAG);
5461 DOUT << "Total amount of phi nodes to update: "
5462 << PHINodesToUpdate.size() << "\n";
5463 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5464 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5465 << ", " << PHINodesToUpdate[i].second << ")\n";);
5467 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5468 // PHI nodes in successors.
5469 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5470 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5471 MachineInstr *PHI = PHINodesToUpdate[i].first;
5472 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5473 "This is not a machine PHI node that we are updating!");
5474 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5476 PHI->addOperand(MachineOperand::CreateMBB(BB));
5481 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5482 // Lower header first, if it wasn't already lowered
5483 if (!BitTestCases[i].Emitted) {
5484 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5485 getAnalysisToUpdate<MachineModuleInfo>(),
5488 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5489 // Set the current basic block to the mbb we wish to insert the code into
5490 BB = BitTestCases[i].Parent;
5491 HSDL.setCurrentBasicBlock(BB);
5493 HSDL.visitBitTestHeader(BitTestCases[i]);
5494 HSDAG.setRoot(HSDL.getRoot());
5495 CodeGenAndEmitDAG(HSDAG);
5498 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5499 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5500 getAnalysisToUpdate<MachineModuleInfo>(),
5503 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5504 // Set the current basic block to the mbb we wish to insert the code into
5505 BB = BitTestCases[i].Cases[j].ThisBB;
5506 BSDL.setCurrentBasicBlock(BB);
5509 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5510 BitTestCases[i].Reg,
5511 BitTestCases[i].Cases[j]);
5513 BSDL.visitBitTestCase(BitTestCases[i].Default,
5514 BitTestCases[i].Reg,
5515 BitTestCases[i].Cases[j]);
5518 BSDAG.setRoot(BSDL.getRoot());
5519 CodeGenAndEmitDAG(BSDAG);
5523 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5524 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5525 MachineBasicBlock *PHIBB = PHI->getParent();
5526 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5527 "This is not a machine PHI node that we are updating!");
5528 // This is "default" BB. We have two jumps to it. From "header" BB and
5529 // from last "case" BB.
5530 if (PHIBB == BitTestCases[i].Default) {
5531 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5533 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5534 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5536 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5539 // One of "cases" BB.
5540 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5541 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5542 if (cBB->succ_end() !=
5543 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5544 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5546 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5552 // If the JumpTable record is filled in, then we need to emit a jump table.
5553 // Updating the PHI nodes is tricky in this case, since we need to determine
5554 // whether the PHI is a successor of the range check MBB or the jump table MBB
5555 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5556 // Lower header first, if it wasn't already lowered
5557 if (!JTCases[i].first.Emitted) {
5558 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5559 getAnalysisToUpdate<MachineModuleInfo>(),
5562 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5563 // Set the current basic block to the mbb we wish to insert the code into
5564 BB = JTCases[i].first.HeaderBB;
5565 HSDL.setCurrentBasicBlock(BB);
5567 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5568 HSDAG.setRoot(HSDL.getRoot());
5569 CodeGenAndEmitDAG(HSDAG);
5572 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5573 getAnalysisToUpdate<MachineModuleInfo>(),
5576 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5577 // Set the current basic block to the mbb we wish to insert the code into
5578 BB = JTCases[i].second.MBB;
5579 JSDL.setCurrentBasicBlock(BB);
5581 JSDL.visitJumpTable(JTCases[i].second);
5582 JSDAG.setRoot(JSDL.getRoot());
5583 CodeGenAndEmitDAG(JSDAG);
5586 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5587 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5588 MachineBasicBlock *PHIBB = PHI->getParent();
5589 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5590 "This is not a machine PHI node that we are updating!");
5591 // "default" BB. We can go there only from header BB.
5592 if (PHIBB == JTCases[i].second.Default) {
5593 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5595 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5597 // JT BB. Just iterate over successors here
5598 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5599 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5601 PHI->addOperand(MachineOperand::CreateMBB(BB));
5606 // If the switch block involved a branch to one of the actual successors, we
5607 // need to update PHI nodes in that block.
5608 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5609 MachineInstr *PHI = PHINodesToUpdate[i].first;
5610 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5611 "This is not a machine PHI node that we are updating!");
5612 if (BB->isSuccessor(PHI->getParent())) {
5613 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5615 PHI->addOperand(MachineOperand::CreateMBB(BB));
5619 // If we generated any switch lowering information, build and codegen any
5620 // additional DAGs necessary.
5621 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5622 SelectionDAG SDAG(TLI, MF, FuncInfo,
5623 getAnalysisToUpdate<MachineModuleInfo>(),
5626 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5628 // Set the current basic block to the mbb we wish to insert the code into
5629 BB = SwitchCases[i].ThisBB;
5630 SDL.setCurrentBasicBlock(BB);
5633 SDL.visitSwitchCase(SwitchCases[i]);
5634 SDAG.setRoot(SDL.getRoot());
5635 CodeGenAndEmitDAG(SDAG);
5637 // Handle any PHI nodes in successors of this chunk, as if we were coming
5638 // from the original BB before switch expansion. Note that PHI nodes can
5639 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5640 // handle them the right number of times.
5641 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5642 for (MachineBasicBlock::iterator Phi = BB->begin();
5643 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5644 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5645 for (unsigned pn = 0; ; ++pn) {
5646 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5647 if (PHINodesToUpdate[pn].first == Phi) {
5648 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5650 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5656 // Don't process RHS if same block as LHS.
5657 if (BB == SwitchCases[i].FalseBB)
5658 SwitchCases[i].FalseBB = 0;
5660 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5661 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5662 SwitchCases[i].FalseBB = 0;
5664 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5669 /// Schedule - Pick a safe ordering for instructions for each
5670 /// target node in the graph.
5672 ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
5673 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5677 RegisterScheduler::setDefault(Ctor);
5680 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
5687 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5688 return new HazardRecognizer();
5691 //===----------------------------------------------------------------------===//
5692 // Helper functions used by the generated instruction selector.
5693 //===----------------------------------------------------------------------===//
5694 // Calls to these methods are generated by tblgen.
5696 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5697 /// the dag combiner simplified the 255, we still want to match. RHS is the
5698 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5699 /// specified in the .td file (e.g. 255).
5700 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
5701 int64_t DesiredMaskS) const {
5702 const APInt &ActualMask = RHS->getAPIntValue();
5703 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5705 // If the actual mask exactly matches, success!
5706 if (ActualMask == DesiredMask)
5709 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5710 if (ActualMask.intersects(~DesiredMask))
5713 // Otherwise, the DAG Combiner may have proven that the value coming in is
5714 // either already zero or is not demanded. Check for known zero input bits.
5715 APInt NeededMask = DesiredMask & ~ActualMask;
5716 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5719 // TODO: check to see if missing bits are just not demanded.
5721 // Otherwise, this pattern doesn't match.
5725 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5726 /// the dag combiner simplified the 255, we still want to match. RHS is the
5727 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5728 /// specified in the .td file (e.g. 255).
5729 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
5730 int64_t DesiredMaskS) const {
5731 const APInt &ActualMask = RHS->getAPIntValue();
5732 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5734 // If the actual mask exactly matches, success!
5735 if (ActualMask == DesiredMask)
5738 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5739 if (ActualMask.intersects(~DesiredMask))
5742 // Otherwise, the DAG Combiner may have proven that the value coming in is
5743 // either already zero or is not demanded. Check for known zero input bits.
5744 APInt NeededMask = DesiredMask & ~ActualMask;
5746 APInt KnownZero, KnownOne;
5747 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5749 // If all the missing bits in the or are already known to be set, match!
5750 if ((NeededMask & KnownOne) == NeededMask)
5753 // TODO: check to see if missing bits are just not demanded.
5755 // Otherwise, this pattern doesn't match.
5760 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5761 /// by tblgen. Others should not call it.
5762 void SelectionDAGISel::
5763 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) {
5764 std::vector<SDValue> InOps;
5765 std::swap(InOps, Ops);
5767 Ops.push_back(InOps[0]); // input chain.
5768 Ops.push_back(InOps[1]); // input asm string.
5770 unsigned i = 2, e = InOps.size();
5771 if (InOps[e-1].getValueType() == MVT::Flag)
5772 --e; // Don't process a flag operand if it is here.
5775 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5776 if ((Flags & 7) != 4 /*MEM*/) {
5777 // Just skip over this operand, copying the operands verbatim.
5778 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5779 i += (Flags >> 3) + 1;
5781 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5782 // Otherwise, this is a memory operand. Ask the target to select it.
5783 std::vector<SDValue> SelOps;
5784 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5785 cerr << "Could not match memory address. Inline asm failure!\n";
5789 // Add this to the output node.
5790 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5791 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5793 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5798 // Add the flag input back if present.
5799 if (e != InOps.size())
5800 Ops.push_back(InOps.back());
5803 char SelectionDAGISel::ID = 0;