1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/Analysis/AliasAnalysis.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/CodeGen/ScheduleDAG.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/CodeGen/SSARegMap.h"
35 #include "llvm/Target/MRegisterInfo.h"
36 #include "llvm/Target/TargetAsmInfo.h"
37 #include "llvm/Target/TargetData.h"
38 #include "llvm/Target/TargetFrameInfo.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
52 ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
55 ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
62 //===---------------------------------------------------------------------===//
64 /// RegisterScheduler class - Track the registration of instruction schedulers.
66 //===---------------------------------------------------------------------===//
67 MachinePassRegistry RegisterScheduler::Registry;
69 //===---------------------------------------------------------------------===//
71 /// ISHeuristic command line option for instruction schedulers.
73 //===---------------------------------------------------------------------===//
75 cl::opt<RegisterScheduler::FunctionPassCtor, false,
76 RegisterPassParser<RegisterScheduler> >
78 cl::init(&createDefaultScheduler),
79 cl::desc("Instruction schedulers available:"));
81 static RegisterScheduler
82 defaultListDAGScheduler("default", " Best scheduler for the target",
83 createDefaultScheduler);
87 /// RegsForValue - This struct represents the physical registers that a
88 /// particular value is assigned and the type information about the value.
89 /// This is needed because values can be promoted into larger registers and
90 /// expanded into multiple smaller registers than the value.
91 struct VISIBILITY_HIDDEN RegsForValue {
92 /// Regs - This list hold the register (for legal and promoted values)
93 /// or register set (for expanded values) that the value should be assigned
95 std::vector<unsigned> Regs;
97 /// RegVT - The value type of each register.
101 /// ValueVT - The value type of the LLVM value, which may be promoted from
102 /// RegVT or made from merging the two expanded parts.
103 MVT::ValueType ValueVT;
105 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
107 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
108 : RegVT(regvt), ValueVT(valuevt) {
111 RegsForValue(const std::vector<unsigned> ®s,
112 MVT::ValueType regvt, MVT::ValueType valuevt)
113 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
116 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
117 /// this value and returns the result as a ValueVT value. This uses
118 /// Chain/Flag as the input and updates them for the output Chain/Flag.
119 SDOperand getCopyFromRegs(SelectionDAG &DAG,
120 SDOperand &Chain, SDOperand &Flag) const;
122 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
123 /// specified value into the registers specified by this object. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
125 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
126 SDOperand &Chain, SDOperand &Flag,
127 MVT::ValueType PtrVT) const;
129 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
130 /// operand list. This adds the code marker and includes the number of
131 /// values added into it.
132 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
133 std::vector<SDOperand> &Ops) const;
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
143 MachineBasicBlock *BB) {
144 TargetLowering &TLI = IS->getTargetLowering();
146 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
147 return createTDListDAGScheduler(IS, DAG, BB);
149 assert(TLI.getSchedulingPreference() ==
150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
151 return createBURRListDAGScheduler(IS, DAG, BB);
156 //===--------------------------------------------------------------------===//
157 /// FunctionLoweringInfo - This contains information that is global to a
158 /// function that is used when lowering a region of the function.
159 class FunctionLoweringInfo {
166 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
168 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
169 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
171 /// ValueMap - Since we emit code for the function a basic block at a time,
172 /// we must remember which virtual registers hold the values for
173 /// cross-basic-block values.
174 DenseMap<const Value*, unsigned> ValueMap;
176 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
177 /// the entry block. This allows the allocas to be efficiently referenced
178 /// anywhere in the function.
179 std::map<const AllocaInst*, int> StaticAllocaMap;
181 unsigned MakeReg(MVT::ValueType VT) {
182 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
185 /// isExportedInst - Return true if the specified value is an instruction
186 /// exported from its block.
187 bool isExportedInst(const Value *V) {
188 return ValueMap.count(V);
191 unsigned CreateRegForValue(const Value *V);
193 unsigned InitializeRegForValue(const Value *V) {
194 unsigned &R = ValueMap[V];
195 assert(R == 0 && "Already initialized this value register!");
196 return R = CreateRegForValue(V);
201 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
202 /// PHI nodes or outside of the basic block that defines it, or used by a
203 /// switch instruction, which may expand to multiple basic blocks.
204 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
205 if (isa<PHINode>(I)) return true;
206 BasicBlock *BB = I->getParent();
207 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
208 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
209 // FIXME: Remove switchinst special case.
210 isa<SwitchInst>(*UI))
215 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
216 /// entry block, return true. This includes arguments used by switches, since
217 /// the switch may expand into multiple basic blocks.
218 static bool isOnlyUsedInEntryBlock(Argument *A) {
219 BasicBlock *Entry = A->getParent()->begin();
220 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
221 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
222 return false; // Use not in entry block.
226 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
227 Function &fn, MachineFunction &mf)
228 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
230 // Create a vreg for each argument register that is not dead and is used
231 // outside of the entry block for the function.
232 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
234 if (!isOnlyUsedInEntryBlock(AI))
235 InitializeRegForValue(AI);
237 // Initialize the mapping of values to registers. This is only set up for
238 // instruction values that are used outside of the block that defines
240 Function::iterator BB = Fn.begin(), EB = Fn.end();
241 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
242 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
243 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
244 const Type *Ty = AI->getAllocatedType();
245 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
247 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
250 TySize *= CUI->getZExtValue(); // Get total allocated size.
251 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
252 StaticAllocaMap[AI] =
253 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
256 for (; BB != EB; ++BB)
257 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
258 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
259 if (!isa<AllocaInst>(I) ||
260 !StaticAllocaMap.count(cast<AllocaInst>(I)))
261 InitializeRegForValue(I);
263 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
264 // also creates the initial PHI MachineInstrs, though none of the input
265 // operands are populated.
266 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
267 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
269 MF.getBasicBlockList().push_back(MBB);
271 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
274 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
275 if (PN->use_empty()) continue;
277 MVT::ValueType VT = TLI.getValueType(PN->getType());
278 unsigned NumElements;
279 if (VT != MVT::Vector)
280 NumElements = TLI.getNumElements(VT);
282 MVT::ValueType VT1,VT2;
284 TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
287 unsigned PHIReg = ValueMap[PN];
288 assert(PHIReg && "PHI node does not have an assigned virtual register!");
289 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
290 for (unsigned i = 0; i != NumElements; ++i)
291 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
296 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
297 /// the correctly promoted or expanded types. Assign these registers
298 /// consecutive vreg numbers and return the first assigned number.
299 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
300 MVT::ValueType VT = TLI.getValueType(V->getType());
302 // The number of multiples of registers that we need, to, e.g., split up
303 // a <2 x int64> -> 4 x i32 registers.
304 unsigned NumVectorRegs = 1;
306 // If this is a vector type, figure out what type it will decompose into
307 // and how many of the elements it will use.
308 if (VT == MVT::Vector) {
309 const VectorType *PTy = cast<VectorType>(V->getType());
310 unsigned NumElts = PTy->getNumElements();
311 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
313 // Divide the input until we get to a supported size. This will always
314 // end with a scalar if the target doesn't support vectors.
315 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
322 VT = getVectorType(EltTy, NumElts);
325 // The common case is that we will only create one register for this
326 // value. If we have that case, create and return the virtual register.
327 unsigned NV = TLI.getNumElements(VT);
329 // If we are promoting this value, pick the next largest supported type.
330 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
331 unsigned Reg = MakeReg(PromotedType);
332 // If this is a vector of supported or promoted types (e.g. 4 x i16),
333 // create all of the registers.
334 for (unsigned i = 1; i != NumVectorRegs; ++i)
335 MakeReg(PromotedType);
339 // If this value is represented with multiple target registers, make sure
340 // to create enough consecutive registers of the right (smaller) type.
341 VT = TLI.getTypeToExpandTo(VT);
342 unsigned R = MakeReg(VT);
343 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
348 //===----------------------------------------------------------------------===//
349 /// SelectionDAGLowering - This is the common target-independent lowering
350 /// implementation that is parameterized by a TargetLowering object.
351 /// Also, targets can overload any lowering method.
354 class SelectionDAGLowering {
355 MachineBasicBlock *CurMBB;
357 DenseMap<const Value*, SDOperand> NodeMap;
359 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
360 /// them up and then emit token factor nodes when possible. This allows us to
361 /// get simple disambiguation between loads without worrying about alias
363 std::vector<SDOperand> PendingLoads;
365 /// Case - A pair of values to record the Value for a switch case, and the
366 /// case's target basic block.
367 typedef std::pair<Constant*, MachineBasicBlock*> Case;
368 typedef std::vector<Case>::iterator CaseItr;
369 typedef std::pair<CaseItr, CaseItr> CaseRange;
371 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
372 /// of conditional branches.
374 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
375 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
377 /// CaseBB - The MBB in which to emit the compare and branch
378 MachineBasicBlock *CaseBB;
379 /// LT, GE - If nonzero, we know the current case value must be less-than or
380 /// greater-than-or-equal-to these Constants.
383 /// Range - A pair of iterators representing the range of case values to be
384 /// processed at this point in the binary search tree.
388 /// The comparison function for sorting Case values.
390 bool operator () (const Case& C1, const Case& C2) {
391 assert(isa<ConstantInt>(C1.first) && isa<ConstantInt>(C2.first));
392 return cast<const ConstantInt>(C1.first)->getSExtValue() <
393 cast<const ConstantInt>(C2.first)->getSExtValue();
398 // TLI - This is information that describes the available target features we
399 // need for lowering. This indicates when operations are unavailable,
400 // implemented with a libcall, etc.
403 const TargetData *TD;
405 /// SwitchCases - Vector of CaseBlock structures used to communicate
406 /// SwitchInst code generation information.
407 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
408 SelectionDAGISel::JumpTable JT;
410 /// FuncInfo - Information about the function as a whole.
412 FunctionLoweringInfo &FuncInfo;
414 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
415 FunctionLoweringInfo &funcinfo)
416 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
417 JT(0,0,0,0), FuncInfo(funcinfo) {
420 /// getRoot - Return the current virtual root of the Selection DAG.
422 SDOperand getRoot() {
423 if (PendingLoads.empty())
424 return DAG.getRoot();
426 if (PendingLoads.size() == 1) {
427 SDOperand Root = PendingLoads[0];
429 PendingLoads.clear();
433 // Otherwise, we have to make a token factor node.
434 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
435 &PendingLoads[0], PendingLoads.size());
436 PendingLoads.clear();
441 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
443 void visit(Instruction &I) { visit(I.getOpcode(), I); }
445 void visit(unsigned Opcode, User &I) {
446 // Note: this doesn't use InstVisitor, because it has to work with
447 // ConstantExpr's in addition to instructions.
449 default: assert(0 && "Unknown instruction type encountered!");
451 // Build the switch statement using the Instruction.def file.
452 #define HANDLE_INST(NUM, OPCODE, CLASS) \
453 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
454 #include "llvm/Instruction.def"
458 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
460 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
461 const Value *SV, SDOperand Root,
464 SDOperand getIntPtrConstant(uint64_t Val) {
465 return DAG.getConstant(Val, TLI.getPointerTy());
468 SDOperand getValue(const Value *V);
470 void setValue(const Value *V, SDOperand NewN) {
471 SDOperand &N = NodeMap[V];
472 assert(N.Val == 0 && "Already set a value for this node!");
476 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
478 bool OutReg, bool InReg,
479 std::set<unsigned> &OutputRegs,
480 std::set<unsigned> &InputRegs);
482 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
483 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
485 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
486 void ExportFromCurrentBlock(Value *V);
487 void LowerCallTo(CallInst &I, SDOperand Callee, unsigned OpIdx);
489 // Terminator instructions.
490 void visitRet(ReturnInst &I);
491 void visitBr(BranchInst &I);
492 void visitSwitch(SwitchInst &I);
493 void visitUnreachable(UnreachableInst &I) { /* noop */ }
495 // Helper for visitSwitch
496 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
497 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
499 // These all get lowered before this pass.
500 void visitInvoke(InvokeInst &I);
501 void visitUnwind(UnwindInst &I);
503 void visitScalarBinary(User &I, unsigned OpCode);
504 void visitVectorBinary(User &I, unsigned OpCode);
505 void visitEitherBinary(User &I, unsigned ScalarOp, unsigned VectorOp);
506 void visitShift(User &I, unsigned Opcode);
507 void visitAdd(User &I) {
508 if (isa<VectorType>(I.getType()))
509 visitVectorBinary(I, ISD::VADD);
510 else if (I.getType()->isFloatingPoint())
511 visitScalarBinary(I, ISD::FADD);
513 visitScalarBinary(I, ISD::ADD);
515 void visitSub(User &I);
516 void visitMul(User &I) {
517 if (isa<VectorType>(I.getType()))
518 visitVectorBinary(I, ISD::VMUL);
519 else if (I.getType()->isFloatingPoint())
520 visitScalarBinary(I, ISD::FMUL);
522 visitScalarBinary(I, ISD::MUL);
524 void visitURem(User &I) { visitScalarBinary(I, ISD::UREM); }
525 void visitSRem(User &I) { visitScalarBinary(I, ISD::SREM); }
526 void visitFRem(User &I) { visitScalarBinary(I, ISD::FREM); }
527 void visitUDiv(User &I) { visitEitherBinary(I, ISD::UDIV, ISD::VUDIV); }
528 void visitSDiv(User &I) { visitEitherBinary(I, ISD::SDIV, ISD::VSDIV); }
529 void visitFDiv(User &I) { visitEitherBinary(I, ISD::FDIV, ISD::VSDIV); }
530 void visitAnd (User &I) { visitEitherBinary(I, ISD::AND, ISD::VAND ); }
531 void visitOr (User &I) { visitEitherBinary(I, ISD::OR, ISD::VOR ); }
532 void visitXor (User &I) { visitEitherBinary(I, ISD::XOR, ISD::VXOR ); }
533 void visitShl (User &I) { visitShift(I, ISD::SHL); }
534 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
535 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
536 void visitICmp(User &I);
537 void visitFCmp(User &I);
538 // Visit the conversion instructions
539 void visitTrunc(User &I);
540 void visitZExt(User &I);
541 void visitSExt(User &I);
542 void visitFPTrunc(User &I);
543 void visitFPExt(User &I);
544 void visitFPToUI(User &I);
545 void visitFPToSI(User &I);
546 void visitUIToFP(User &I);
547 void visitSIToFP(User &I);
548 void visitPtrToInt(User &I);
549 void visitIntToPtr(User &I);
550 void visitBitCast(User &I);
552 void visitExtractElement(User &I);
553 void visitInsertElement(User &I);
554 void visitShuffleVector(User &I);
556 void visitGetElementPtr(User &I);
557 void visitSelect(User &I);
559 void visitMalloc(MallocInst &I);
560 void visitFree(FreeInst &I);
561 void visitAlloca(AllocaInst &I);
562 void visitLoad(LoadInst &I);
563 void visitStore(StoreInst &I);
564 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
565 void visitCall(CallInst &I);
566 void visitInlineAsm(CallInst &I);
567 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
568 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
570 void visitVAStart(CallInst &I);
571 void visitVAArg(VAArgInst &I);
572 void visitVAEnd(CallInst &I);
573 void visitVACopy(CallInst &I);
575 void visitMemIntrinsic(CallInst &I, unsigned Op);
577 void visitUserOp1(Instruction &I) {
578 assert(0 && "UserOp1 should not exist at instruction selection time!");
581 void visitUserOp2(Instruction &I) {
582 assert(0 && "UserOp2 should not exist at instruction selection time!");
586 } // end namespace llvm
588 SDOperand SelectionDAGLowering::getValue(const Value *V) {
589 SDOperand &N = NodeMap[V];
592 const Type *VTy = V->getType();
593 MVT::ValueType VT = TLI.getValueType(VTy);
594 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
595 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
596 visit(CE->getOpcode(), *CE);
597 SDOperand N1 = NodeMap[V];
598 assert(N1.Val && "visit didn't populate the ValueMap!");
600 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
601 return N = DAG.getGlobalAddress(GV, VT);
602 } else if (isa<ConstantPointerNull>(C)) {
603 return N = DAG.getConstant(0, TLI.getPointerTy());
604 } else if (isa<UndefValue>(C)) {
605 if (!isa<VectorType>(VTy))
606 return N = DAG.getNode(ISD::UNDEF, VT);
608 // Create a VBUILD_VECTOR of undef nodes.
609 const VectorType *PTy = cast<VectorType>(VTy);
610 unsigned NumElements = PTy->getNumElements();
611 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
613 SmallVector<SDOperand, 8> Ops;
614 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
616 // Create a VConstant node with generic Vector type.
617 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
618 Ops.push_back(DAG.getValueType(PVT));
619 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
620 &Ops[0], Ops.size());
621 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
622 return N = DAG.getConstantFP(CFP->getValue(), VT);
623 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
624 unsigned NumElements = PTy->getNumElements();
625 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
627 // Now that we know the number and type of the elements, push a
628 // Constant or ConstantFP node onto the ops list for each element of
629 // the packed constant.
630 SmallVector<SDOperand, 8> Ops;
631 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
632 for (unsigned i = 0; i != NumElements; ++i)
633 Ops.push_back(getValue(CP->getOperand(i)));
635 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
637 if (MVT::isFloatingPoint(PVT))
638 Op = DAG.getConstantFP(0, PVT);
640 Op = DAG.getConstant(0, PVT);
641 Ops.assign(NumElements, Op);
644 // Create a VBUILD_VECTOR node with generic Vector type.
645 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
646 Ops.push_back(DAG.getValueType(PVT));
647 return NodeMap[V] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0],
650 // Canonicalize all constant ints to be unsigned.
651 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
655 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
656 std::map<const AllocaInst*, int>::iterator SI =
657 FuncInfo.StaticAllocaMap.find(AI);
658 if (SI != FuncInfo.StaticAllocaMap.end())
659 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
662 DenseMap<const Value*, unsigned>::iterator VMI =
663 FuncInfo.ValueMap.find(V);
664 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
666 unsigned InReg = VMI->second;
668 // If this type is not legal, make it so now.
669 if (VT != MVT::Vector) {
670 if (TLI.getTypeAction(VT) == TargetLowering::Expand) {
671 // Source must be expanded. This input value is actually coming from the
672 // register pair VMI->second and VMI->second+1.
673 MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
674 unsigned NumVals = TLI.getNumElements(VT);
675 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
677 N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
679 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
680 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
681 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
684 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
685 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
686 if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case
687 N = MVT::isFloatingPoint(VT)
688 ? DAG.getNode(ISD::FP_ROUND, VT, N)
689 : DAG.getNode(ISD::TRUNCATE, VT, N);
692 // Otherwise, if this is a vector, make it available as a generic vector
694 MVT::ValueType PTyElementVT, PTyLegalElementVT;
695 const VectorType *PTy = cast<VectorType>(VTy);
696 unsigned NE = TLI.getVectorTypeBreakdown(PTy, PTyElementVT,
699 // Build a VBUILD_VECTOR with the input registers.
700 SmallVector<SDOperand, 8> Ops;
701 if (PTyElementVT == PTyLegalElementVT) {
702 // If the value types are legal, just VBUILD the CopyFromReg nodes.
703 for (unsigned i = 0; i != NE; ++i)
704 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
706 } else if (PTyElementVT < PTyLegalElementVT) {
707 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
708 for (unsigned i = 0; i != NE; ++i) {
709 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
711 if (MVT::isFloatingPoint(PTyElementVT))
712 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
714 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
718 // If the register was expanded, use BUILD_PAIR.
719 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
720 for (unsigned i = 0; i != NE/2; ++i) {
721 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
723 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
725 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
729 Ops.push_back(DAG.getConstant(NE, MVT::i32));
730 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
731 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
733 // Finally, use a VBIT_CONVERT to make this available as the appropriate
735 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
736 DAG.getConstant(PTy->getNumElements(),
738 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
745 void SelectionDAGLowering::visitRet(ReturnInst &I) {
746 if (I.getNumOperands() == 0) {
747 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
750 SmallVector<SDOperand, 8> NewValues;
751 NewValues.push_back(getRoot());
752 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
753 SDOperand RetOp = getValue(I.getOperand(i));
755 // If this is an integer return value, we need to promote it ourselves to
756 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
758 // FIXME: C calling convention requires the return type to be promoted to
759 // at least 32-bit. But this is not necessary for non-C calling conventions.
760 if (MVT::isInteger(RetOp.getValueType()) &&
761 RetOp.getValueType() < MVT::i64) {
762 MVT::ValueType TmpVT;
763 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
764 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
767 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType();
768 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
769 if (FTy->paramHasAttr(0, FunctionType::SExtAttribute))
770 ExtendKind = ISD::SIGN_EXTEND;
771 if (FTy->paramHasAttr(0, FunctionType::ZExtAttribute))
772 ExtendKind = ISD::ZERO_EXTEND;
773 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
775 NewValues.push_back(RetOp);
776 NewValues.push_back(DAG.getConstant(false, MVT::i32));
778 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
779 &NewValues[0], NewValues.size()));
782 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
783 /// the current basic block, add it to ValueMap now so that we'll get a
785 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
786 // No need to export constants.
787 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
790 if (FuncInfo.isExportedInst(V)) return;
792 unsigned Reg = FuncInfo.InitializeRegForValue(V);
793 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
796 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
797 const BasicBlock *FromBB) {
798 // The operands of the setcc have to be in this block. We don't know
799 // how to export them from some other block.
800 if (Instruction *VI = dyn_cast<Instruction>(V)) {
801 // Can export from current BB.
802 if (VI->getParent() == FromBB)
805 // Is already exported, noop.
806 return FuncInfo.isExportedInst(V);
809 // If this is an argument, we can export it if the BB is the entry block or
810 // if it is already exported.
811 if (isa<Argument>(V)) {
812 if (FromBB == &FromBB->getParent()->getEntryBlock())
815 // Otherwise, can only export this if it is already exported.
816 return FuncInfo.isExportedInst(V);
819 // Otherwise, constants can always be exported.
823 static bool InBlock(const Value *V, const BasicBlock *BB) {
824 if (const Instruction *I = dyn_cast<Instruction>(V))
825 return I->getParent() == BB;
829 /// FindMergedConditions - If Cond is an expression like
830 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
831 MachineBasicBlock *TBB,
832 MachineBasicBlock *FBB,
833 MachineBasicBlock *CurBB,
835 // If this node is not part of the or/and tree, emit it as a branch.
836 Instruction *BOp = dyn_cast<Instruction>(Cond);
838 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
839 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
840 BOp->getParent() != CurBB->getBasicBlock() ||
841 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
842 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
843 const BasicBlock *BB = CurBB->getBasicBlock();
845 // If the leaf of the tree is a comparison, merge the condition into
847 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
848 // The operands of the cmp have to be in this block. We don't know
849 // how to export them from some other block. If this is the first block
850 // of the sequence, no exporting is needed.
852 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
853 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
854 BOp = cast<Instruction>(Cond);
855 ISD::CondCode Condition;
856 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
857 switch (IC->getPredicate()) {
858 default: assert(0 && "Unknown icmp predicate opcode!");
859 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
860 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
861 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
862 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
863 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
864 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
865 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
866 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
867 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
868 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
870 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
871 ISD::CondCode FPC, FOC;
872 switch (FC->getPredicate()) {
873 default: assert(0 && "Unknown fcmp predicate opcode!");
874 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
875 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
876 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
877 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
878 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
879 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
880 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
881 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
882 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
883 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
884 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
885 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
886 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
887 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
888 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
889 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
891 if (FiniteOnlyFPMath())
896 Condition = ISD::SETEQ; // silence warning.
897 assert(0 && "Unknown compare instruction");
900 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
901 BOp->getOperand(1), TBB, FBB, CurBB);
902 SwitchCases.push_back(CB);
906 // Create a CaseBlock record representing this branch.
907 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
909 SwitchCases.push_back(CB);
914 // Create TmpBB after CurBB.
915 MachineFunction::iterator BBI = CurBB;
916 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
917 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
919 if (Opc == Instruction::Or) {
928 // Emit the LHS condition.
929 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
931 // Emit the RHS condition into TmpBB.
932 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
934 assert(Opc == Instruction::And && "Unknown merge op!");
942 // This requires creation of TmpBB after CurBB.
944 // Emit the LHS condition.
945 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
947 // Emit the RHS condition into TmpBB.
948 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
952 /// If the set of cases should be emitted as a series of branches, return true.
953 /// If we should emit this as a bunch of and/or'd together conditions, return
956 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
957 if (Cases.size() != 2) return true;
959 // If this is two comparisons of the same values or'd or and'd together, they
960 // will get folded into a single comparison, so don't emit two blocks.
961 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
962 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
963 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
964 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
971 void SelectionDAGLowering::visitBr(BranchInst &I) {
972 // Update machine-CFG edges.
973 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
975 // Figure out which block is immediately after the current one.
976 MachineBasicBlock *NextBlock = 0;
977 MachineFunction::iterator BBI = CurMBB;
978 if (++BBI != CurMBB->getParent()->end())
981 if (I.isUnconditional()) {
982 // If this is not a fall-through branch, emit the branch.
983 if (Succ0MBB != NextBlock)
984 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
985 DAG.getBasicBlock(Succ0MBB)));
987 // Update machine-CFG edges.
988 CurMBB->addSuccessor(Succ0MBB);
993 // If this condition is one of the special cases we handle, do special stuff
995 Value *CondVal = I.getCondition();
996 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
998 // If this is a series of conditions that are or'd or and'd together, emit
999 // this as a sequence of branches instead of setcc's with and/or operations.
1000 // For example, instead of something like:
1013 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1014 if (BOp->hasOneUse() &&
1015 (BOp->getOpcode() == Instruction::And ||
1016 BOp->getOpcode() == Instruction::Or)) {
1017 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1018 // If the compares in later blocks need to use values not currently
1019 // exported from this block, export them now. This block should always
1020 // be the first entry.
1021 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1023 // Allow some cases to be rejected.
1024 if (ShouldEmitAsBranches(SwitchCases)) {
1025 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1026 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1027 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1030 // Emit the branch for this block.
1031 visitSwitchCase(SwitchCases[0]);
1032 SwitchCases.erase(SwitchCases.begin());
1036 // Okay, we decided not to do this, remove any inserted MBB's and clear
1038 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1039 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1041 SwitchCases.clear();
1045 // Create a CaseBlock record representing this branch.
1046 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1047 Succ0MBB, Succ1MBB, CurMBB);
1048 // Use visitSwitchCase to actually insert the fast branch sequence for this
1050 visitSwitchCase(CB);
1053 /// visitSwitchCase - Emits the necessary code to represent a single node in
1054 /// the binary search tree resulting from lowering a switch instruction.
1055 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1057 SDOperand CondLHS = getValue(CB.CmpLHS);
1059 // Build the setcc now, fold "(X == true)" to X and "(X == false)" to !X to
1060 // handle common cases produced by branch lowering.
1061 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1063 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1064 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1065 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1067 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1069 // Set NextBlock to be the MBB immediately after the current one, if any.
1070 // This is used to avoid emitting unnecessary branches to the next block.
1071 MachineBasicBlock *NextBlock = 0;
1072 MachineFunction::iterator BBI = CurMBB;
1073 if (++BBI != CurMBB->getParent()->end())
1076 // If the lhs block is the next block, invert the condition so that we can
1077 // fall through to the lhs instead of the rhs block.
1078 if (CB.TrueBB == NextBlock) {
1079 std::swap(CB.TrueBB, CB.FalseBB);
1080 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1081 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1083 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1084 DAG.getBasicBlock(CB.TrueBB));
1085 if (CB.FalseBB == NextBlock)
1086 DAG.setRoot(BrCond);
1088 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1089 DAG.getBasicBlock(CB.FalseBB)));
1090 // Update successor info
1091 CurMBB->addSuccessor(CB.TrueBB);
1092 CurMBB->addSuccessor(CB.FalseBB);
1095 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1096 // Emit the code for the jump table
1097 MVT::ValueType PTy = TLI.getPointerTy();
1098 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1099 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1100 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1105 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1106 // Retrieve successors.
1107 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1108 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1110 // Mark landing pad so that it doesn't get deleted in branch folding.
1111 LandingPad->setIsLandingPad();
1113 // Insert a label before the invoke call to mark the try range.
1114 // This can be used to detect deletion of the invoke via the
1115 // MachineModuleInfo.
1116 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1117 unsigned BeginLabel = MMI->NextLabelID();
1118 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
1119 DAG.getConstant(BeginLabel, MVT::i32)));
1121 LowerCallTo((CallInst&)I, getValue(I.getOperand(0)), 3);
1123 // Insert a label before the invoke call to mark the try range.
1124 // This can be used to detect deletion of the invoke via the
1125 // MachineModuleInfo.
1126 unsigned EndLabel = MMI->NextLabelID();
1127 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
1128 DAG.getConstant(EndLabel, MVT::i32)));
1130 // Inform MachineModuleInfo of range.
1131 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
1133 // Drop into normal successor.
1134 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1135 DAG.getBasicBlock(Return)));
1137 // Update successor info
1138 CurMBB->addSuccessor(Return);
1139 CurMBB->addSuccessor(LandingPad);
1142 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1145 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
1146 // Figure out which block is immediately after the current one.
1147 MachineBasicBlock *NextBlock = 0;
1148 MachineFunction::iterator BBI = CurMBB;
1150 if (++BBI != CurMBB->getParent()->end())
1153 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
1155 // If there is only the default destination, branch to it if it is not the
1156 // next basic block. Otherwise, just fall through.
1157 if (I.getNumOperands() == 2) {
1158 // Update machine-CFG edges.
1160 // If this is not a fall-through branch, emit the branch.
1161 if (Default != NextBlock)
1162 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1163 DAG.getBasicBlock(Default)));
1165 CurMBB->addSuccessor(Default);
1169 // If there are any non-default case statements, create a vector of Cases
1170 // representing each one, and sort the vector so that we can efficiently
1171 // create a binary search tree from them.
1172 std::vector<Case> Cases;
1174 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
1175 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
1176 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
1179 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1181 // Get the Value to be switched on and default basic blocks, which will be
1182 // inserted into CaseBlock records, representing basic blocks in the binary
1184 Value *SV = I.getOperand(0);
1186 // Get the MachineFunction which holds the current MBB. This is used during
1187 // emission of jump tables, and when inserting any additional MBBs necessary
1188 // to represent the switch.
1189 MachineFunction *CurMF = CurMBB->getParent();
1190 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
1192 // If the switch has few cases (two or less) emit a series of specific
1194 if (Cases.size() < 3) {
1195 // TODO: If any two of the cases has the same destination, and if one value
1196 // is the same as the other, but has one bit unset that the other has set,
1197 // use bit manipulation to do two compares at once. For example:
1198 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1200 // Rearrange the case blocks so that the last one falls through if possible.
1201 if (NextBlock && Default != NextBlock && Cases.back().second != NextBlock) {
1202 // The last case block won't fall through into 'NextBlock' if we emit the
1203 // branches in this order. See if rearranging a case value would help.
1204 for (unsigned i = 0, e = Cases.size()-1; i != e; ++i) {
1205 if (Cases[i].second == NextBlock) {
1206 std::swap(Cases[i], Cases.back());
1212 // Create a CaseBlock record representing a conditional branch to
1213 // the Case's target mbb if the value being switched on SV is equal
1215 MachineBasicBlock *CurBlock = CurMBB;
1216 for (unsigned i = 0, e = Cases.size(); i != e; ++i) {
1217 MachineBasicBlock *FallThrough;
1219 FallThrough = new MachineBasicBlock(CurMBB->getBasicBlock());
1220 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1222 // If the last case doesn't match, go to the default block.
1223 FallThrough = Default;
1226 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, Cases[i].first,
1227 Cases[i].second, FallThrough, CurBlock);
1229 // If emitting the first comparison, just call visitSwitchCase to emit the
1230 // code into the current block. Otherwise, push the CaseBlock onto the
1231 // vector to be later processed by SDISel, and insert the node's MBB
1232 // before the next MBB.
1233 if (CurBlock == CurMBB)
1234 visitSwitchCase(CB);
1236 SwitchCases.push_back(CB);
1238 CurBlock = FallThrough;
1243 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
1244 // target supports indirect branches, then emit a jump table rather than
1245 // lowering the switch to a binary tree of conditional branches.
1246 if ((TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1247 TLI.isOperationLegal(ISD::BRIND, MVT::Other)) &&
1249 uint64_t First =cast<ConstantInt>(Cases.front().first)->getSExtValue();
1250 uint64_t Last = cast<ConstantInt>(Cases.back().first)->getSExtValue();
1251 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
1253 if (Density >= 0.3125) {
1254 // Create a new basic block to hold the code for loading the address
1255 // of the jump table, and jumping to it. Update successor information;
1256 // we will either branch to the default case for the switch, or the jump
1258 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1259 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1260 CurMBB->addSuccessor(Default);
1261 CurMBB->addSuccessor(JumpTableBB);
1263 // Subtract the lowest switch case value from the value being switched on
1264 // and conditional branch to default mbb if the result is greater than the
1265 // difference between smallest and largest cases.
1266 SDOperand SwitchOp = getValue(SV);
1267 MVT::ValueType VT = SwitchOp.getValueType();
1268 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1269 DAG.getConstant(First, VT));
1271 // The SDNode we just created, which holds the value being switched on
1272 // minus the the smallest case value, needs to be copied to a virtual
1273 // register so it can be used as an index into the jump table in a
1274 // subsequent basic block. This value may be smaller or larger than the
1275 // target's pointer type, and therefore require extension or truncating.
1276 if (VT > TLI.getPointerTy())
1277 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1279 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1281 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1282 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1284 // Emit the range check for the jump table, and branch to the default
1285 // block for the switch statement if the value being switched on exceeds
1286 // the largest case in the switch.
1287 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1288 DAG.getConstant(Last-First,VT), ISD::SETUGT);
1289 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1290 DAG.getBasicBlock(Default)));
1292 // Build a vector of destination BBs, corresponding to each target
1293 // of the jump table. If the value of the jump table slot corresponds to
1294 // a case statement, push the case's BB onto the vector, otherwise, push
1296 std::vector<MachineBasicBlock*> DestBBs;
1297 int64_t TEI = First;
1298 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI)
1299 if (cast<ConstantInt>(ii->first)->getSExtValue() == TEI) {
1300 DestBBs.push_back(ii->second);
1303 DestBBs.push_back(Default);
1306 // Update successor info. Add one edge to each unique successor.
1307 // Vector bool would be better, but vector<bool> is really slow.
1308 std::vector<unsigned char> SuccsHandled;
1309 SuccsHandled.resize(CurMBB->getParent()->getNumBlockIDs());
1311 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1312 E = DestBBs.end(); I != E; ++I) {
1313 if (!SuccsHandled[(*I)->getNumber()]) {
1314 SuccsHandled[(*I)->getNumber()] = true;
1315 JumpTableBB->addSuccessor(*I);
1319 // Create a jump table index for this jump table, or return an existing
1321 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1323 // Set the jump table information so that we can codegen it as a second
1324 // MachineBasicBlock
1325 JT.Reg = JumpTableReg;
1327 JT.MBB = JumpTableBB;
1328 JT.Default = Default;
1333 // Push the initial CaseRec onto the worklist
1334 std::vector<CaseRec> CaseVec;
1335 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1337 while (!CaseVec.empty()) {
1338 // Grab a record representing a case range to process off the worklist
1339 CaseRec CR = CaseVec.back();
1342 // Size is the number of Cases represented by this range. If Size is 1,
1343 // then we are processing a leaf of the binary search tree. Otherwise,
1344 // we need to pick a pivot, and push left and right ranges onto the
1346 unsigned Size = CR.Range.second - CR.Range.first;
1349 // Create a CaseBlock record representing a conditional branch to
1350 // the Case's target mbb if the value being switched on SV is equal
1351 // to C. Otherwise, branch to default.
1352 Constant *C = CR.Range.first->first;
1353 MachineBasicBlock *Target = CR.Range.first->second;
1354 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1357 // If the MBB representing the leaf node is the current MBB, then just
1358 // call visitSwitchCase to emit the code into the current block.
1359 // Otherwise, push the CaseBlock onto the vector to be later processed
1360 // by SDISel, and insert the node's MBB before the next MBB.
1361 if (CR.CaseBB == CurMBB)
1362 visitSwitchCase(CB);
1364 SwitchCases.push_back(CB);
1366 // split case range at pivot
1367 CaseItr Pivot = CR.Range.first + (Size / 2);
1368 CaseRange LHSR(CR.Range.first, Pivot);
1369 CaseRange RHSR(Pivot, CR.Range.second);
1370 Constant *C = Pivot->first;
1371 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1373 // We know that we branch to the LHS if the Value being switched on is
1374 // less than the Pivot value, C. We use this to optimize our binary
1375 // tree a bit, by recognizing that if SV is greater than or equal to the
1376 // LHS's Case Value, and that Case Value is exactly one less than the
1377 // Pivot's Value, then we can branch directly to the LHS's Target,
1378 // rather than creating a leaf node for it.
1379 if ((LHSR.second - LHSR.first) == 1 &&
1380 LHSR.first->first == CR.GE &&
1381 cast<ConstantInt>(C)->getZExtValue() ==
1382 (cast<ConstantInt>(CR.GE)->getZExtValue() + 1ULL)) {
1383 TrueBB = LHSR.first->second;
1385 TrueBB = new MachineBasicBlock(LLVMBB);
1386 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1387 CaseVec.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1390 // Similar to the optimization above, if the Value being switched on is
1391 // known to be less than the Constant CR.LT, and the current Case Value
1392 // is CR.LT - 1, then we can branch directly to the target block for
1393 // the current Case Value, rather than emitting a RHS leaf node for it.
1394 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1395 cast<ConstantInt>(RHSR.first->first)->getZExtValue() ==
1396 (cast<ConstantInt>(CR.LT)->getZExtValue() - 1ULL)) {
1397 FalseBB = RHSR.first->second;
1399 FalseBB = new MachineBasicBlock(LLVMBB);
1400 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1401 CaseVec.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1404 // Create a CaseBlock record representing a conditional branch to
1405 // the LHS node if the value being switched on SV is less than C.
1406 // Otherwise, branch to LHS.
1407 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, TrueBB, FalseBB,
1410 if (CR.CaseBB == CurMBB)
1411 visitSwitchCase(CB);
1413 SwitchCases.push_back(CB);
1418 void SelectionDAGLowering::visitSub(User &I) {
1419 // -0.0 - X --> fneg
1420 const Type *Ty = I.getType();
1421 if (isa<VectorType>(Ty)) {
1422 visitVectorBinary(I, ISD::VSUB);
1423 } else if (Ty->isFloatingPoint()) {
1424 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1425 if (CFP->isExactlyValue(-0.0)) {
1426 SDOperand Op2 = getValue(I.getOperand(1));
1427 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1430 visitScalarBinary(I, ISD::FSUB);
1432 visitScalarBinary(I, ISD::SUB);
1435 void SelectionDAGLowering::visitScalarBinary(User &I, unsigned OpCode) {
1436 SDOperand Op1 = getValue(I.getOperand(0));
1437 SDOperand Op2 = getValue(I.getOperand(1));
1439 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
1443 SelectionDAGLowering::visitVectorBinary(User &I, unsigned OpCode) {
1444 assert(isa<VectorType>(I.getType()));
1445 const VectorType *Ty = cast<VectorType>(I.getType());
1446 SDOperand Typ = DAG.getValueType(TLI.getValueType(Ty->getElementType()));
1448 setValue(&I, DAG.getNode(OpCode, MVT::Vector,
1449 getValue(I.getOperand(0)),
1450 getValue(I.getOperand(1)),
1451 DAG.getConstant(Ty->getNumElements(), MVT::i32),
1455 void SelectionDAGLowering::visitEitherBinary(User &I, unsigned ScalarOp,
1456 unsigned VectorOp) {
1457 if (isa<VectorType>(I.getType()))
1458 visitVectorBinary(I, VectorOp);
1460 visitScalarBinary(I, ScalarOp);
1463 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1464 SDOperand Op1 = getValue(I.getOperand(0));
1465 SDOperand Op2 = getValue(I.getOperand(1));
1467 if (TLI.getShiftAmountTy() < Op2.getValueType())
1468 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
1469 else if (TLI.getShiftAmountTy() > Op2.getValueType())
1470 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1472 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1475 void SelectionDAGLowering::visitICmp(User &I) {
1476 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
1477 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
1478 predicate = IC->getPredicate();
1479 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
1480 predicate = ICmpInst::Predicate(IC->getPredicate());
1481 SDOperand Op1 = getValue(I.getOperand(0));
1482 SDOperand Op2 = getValue(I.getOperand(1));
1483 ISD::CondCode Opcode;
1484 switch (predicate) {
1485 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
1486 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
1487 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
1488 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
1489 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
1490 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
1491 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
1492 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
1493 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
1494 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
1496 assert(!"Invalid ICmp predicate value");
1497 Opcode = ISD::SETEQ;
1500 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1503 void SelectionDAGLowering::visitFCmp(User &I) {
1504 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
1505 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
1506 predicate = FC->getPredicate();
1507 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
1508 predicate = FCmpInst::Predicate(FC->getPredicate());
1509 SDOperand Op1 = getValue(I.getOperand(0));
1510 SDOperand Op2 = getValue(I.getOperand(1));
1511 ISD::CondCode Condition, FOC, FPC;
1512 switch (predicate) {
1513 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1514 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1515 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1516 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1517 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1518 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1519 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1520 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1521 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1522 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1523 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1524 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1525 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1526 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1527 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1528 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1530 assert(!"Invalid FCmp predicate value");
1531 FOC = FPC = ISD::SETFALSE;
1534 if (FiniteOnlyFPMath())
1538 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
1541 void SelectionDAGLowering::visitSelect(User &I) {
1542 SDOperand Cond = getValue(I.getOperand(0));
1543 SDOperand TrueVal = getValue(I.getOperand(1));
1544 SDOperand FalseVal = getValue(I.getOperand(2));
1545 if (!isa<VectorType>(I.getType())) {
1546 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1547 TrueVal, FalseVal));
1549 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1550 *(TrueVal.Val->op_end()-2),
1551 *(TrueVal.Val->op_end()-1)));
1556 void SelectionDAGLowering::visitTrunc(User &I) {
1557 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
1558 SDOperand N = getValue(I.getOperand(0));
1559 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1560 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1563 void SelectionDAGLowering::visitZExt(User &I) {
1564 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
1565 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
1566 SDOperand N = getValue(I.getOperand(0));
1567 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1568 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1571 void SelectionDAGLowering::visitSExt(User &I) {
1572 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
1573 // SExt also can't be a cast to bool for same reason. So, nothing much to do
1574 SDOperand N = getValue(I.getOperand(0));
1575 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1576 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1579 void SelectionDAGLowering::visitFPTrunc(User &I) {
1580 // FPTrunc is never a no-op cast, no need to check
1581 SDOperand N = getValue(I.getOperand(0));
1582 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1583 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1586 void SelectionDAGLowering::visitFPExt(User &I){
1587 // FPTrunc is never a no-op cast, no need to check
1588 SDOperand N = getValue(I.getOperand(0));
1589 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1590 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1593 void SelectionDAGLowering::visitFPToUI(User &I) {
1594 // FPToUI is never a no-op cast, no need to check
1595 SDOperand N = getValue(I.getOperand(0));
1596 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1597 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1600 void SelectionDAGLowering::visitFPToSI(User &I) {
1601 // FPToSI is never a no-op cast, no need to check
1602 SDOperand N = getValue(I.getOperand(0));
1603 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1604 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1607 void SelectionDAGLowering::visitUIToFP(User &I) {
1608 // UIToFP is never a no-op cast, no need to check
1609 SDOperand N = getValue(I.getOperand(0));
1610 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1611 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1614 void SelectionDAGLowering::visitSIToFP(User &I){
1615 // UIToFP is never a no-op cast, no need to check
1616 SDOperand N = getValue(I.getOperand(0));
1617 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1618 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1621 void SelectionDAGLowering::visitPtrToInt(User &I) {
1622 // What to do depends on the size of the integer and the size of the pointer.
1623 // We can either truncate, zero extend, or no-op, accordingly.
1624 SDOperand N = getValue(I.getOperand(0));
1625 MVT::ValueType SrcVT = N.getValueType();
1626 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1628 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
1629 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
1631 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
1632 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
1633 setValue(&I, Result);
1636 void SelectionDAGLowering::visitIntToPtr(User &I) {
1637 // What to do depends on the size of the integer and the size of the pointer.
1638 // We can either truncate, zero extend, or no-op, accordingly.
1639 SDOperand N = getValue(I.getOperand(0));
1640 MVT::ValueType SrcVT = N.getValueType();
1641 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1642 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
1643 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1645 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
1646 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1649 void SelectionDAGLowering::visitBitCast(User &I) {
1650 SDOperand N = getValue(I.getOperand(0));
1651 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1652 if (DestVT == MVT::Vector) {
1653 // This is a cast to a vector from something else.
1654 // Get information about the output vector.
1655 const VectorType *DestTy = cast<VectorType>(I.getType());
1656 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1657 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1658 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1659 DAG.getValueType(EltVT)));
1662 MVT::ValueType SrcVT = N.getValueType();
1663 if (SrcVT == MVT::Vector) {
1664 // This is a cast from a vctor to something else.
1665 // Get information about the input vector.
1666 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1670 // BitCast assures us that source and destination are the same size so this
1671 // is either a BIT_CONVERT or a no-op.
1672 if (DestVT != N.getValueType())
1673 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
1675 setValue(&I, N); // noop cast.
1678 void SelectionDAGLowering::visitInsertElement(User &I) {
1679 SDOperand InVec = getValue(I.getOperand(0));
1680 SDOperand InVal = getValue(I.getOperand(1));
1681 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1682 getValue(I.getOperand(2)));
1684 SDOperand Num = *(InVec.Val->op_end()-2);
1685 SDOperand Typ = *(InVec.Val->op_end()-1);
1686 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1687 InVec, InVal, InIdx, Num, Typ));
1690 void SelectionDAGLowering::visitExtractElement(User &I) {
1691 SDOperand InVec = getValue(I.getOperand(0));
1692 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1693 getValue(I.getOperand(1)));
1694 SDOperand Typ = *(InVec.Val->op_end()-1);
1695 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1696 TLI.getValueType(I.getType()), InVec, InIdx));
1699 void SelectionDAGLowering::visitShuffleVector(User &I) {
1700 SDOperand V1 = getValue(I.getOperand(0));
1701 SDOperand V2 = getValue(I.getOperand(1));
1702 SDOperand Mask = getValue(I.getOperand(2));
1704 SDOperand Num = *(V1.Val->op_end()-2);
1705 SDOperand Typ = *(V2.Val->op_end()-1);
1706 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1707 V1, V2, Mask, Num, Typ));
1711 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1712 SDOperand N = getValue(I.getOperand(0));
1713 const Type *Ty = I.getOperand(0)->getType();
1715 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1718 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1719 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
1722 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
1723 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1724 getIntPtrConstant(Offset));
1726 Ty = StTy->getElementType(Field);
1728 Ty = cast<SequentialType>(Ty)->getElementType();
1730 // If this is a constant subscript, handle it quickly.
1731 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1732 if (CI->getZExtValue() == 0) continue;
1734 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
1735 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1739 // N = N + Idx * ElementSize;
1740 uint64_t ElementSize = TD->getTypeSize(Ty);
1741 SDOperand IdxN = getValue(Idx);
1743 // If the index is smaller or larger than intptr_t, truncate or extend
1745 if (IdxN.getValueType() < N.getValueType()) {
1746 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1747 } else if (IdxN.getValueType() > N.getValueType())
1748 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1750 // If this is a multiply by a power of two, turn it into a shl
1751 // immediately. This is a very common case.
1752 if (isPowerOf2_64(ElementSize)) {
1753 unsigned Amt = Log2_64(ElementSize);
1754 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1755 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1756 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1760 SDOperand Scale = getIntPtrConstant(ElementSize);
1761 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1762 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1768 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1769 // If this is a fixed sized alloca in the entry block of the function,
1770 // allocate it statically on the stack.
1771 if (FuncInfo.StaticAllocaMap.count(&I))
1772 return; // getValue will auto-populate this.
1774 const Type *Ty = I.getAllocatedType();
1775 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1777 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
1780 SDOperand AllocSize = getValue(I.getArraySize());
1781 MVT::ValueType IntPtr = TLI.getPointerTy();
1782 if (IntPtr < AllocSize.getValueType())
1783 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1784 else if (IntPtr > AllocSize.getValueType())
1785 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1787 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1788 getIntPtrConstant(TySize));
1790 // Handle alignment. If the requested alignment is less than or equal to the
1791 // stack alignment, ignore it and round the size of the allocation up to the
1792 // stack alignment size. If the size is greater than the stack alignment, we
1793 // note this in the DYNAMIC_STACKALLOC node.
1794 unsigned StackAlign =
1795 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1796 if (Align <= StackAlign) {
1798 // Add SA-1 to the size.
1799 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1800 getIntPtrConstant(StackAlign-1));
1801 // Mask out the low bits for alignment purposes.
1802 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1803 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1806 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
1807 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
1809 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
1811 DAG.setRoot(DSA.getValue(1));
1813 // Inform the Frame Information that we have just allocated a variable-sized
1815 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1818 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1819 SDOperand Ptr = getValue(I.getOperand(0));
1825 // Do not serialize non-volatile loads against each other.
1826 Root = DAG.getRoot();
1829 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
1830 Root, I.isVolatile()));
1833 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1834 const Value *SV, SDOperand Root,
1837 if (const VectorType *PTy = dyn_cast<VectorType>(Ty)) {
1838 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1839 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
1840 DAG.getSrcValue(SV));
1842 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, isVolatile);
1846 DAG.setRoot(L.getValue(1));
1848 PendingLoads.push_back(L.getValue(1));
1854 void SelectionDAGLowering::visitStore(StoreInst &I) {
1855 Value *SrcV = I.getOperand(0);
1856 SDOperand Src = getValue(SrcV);
1857 SDOperand Ptr = getValue(I.getOperand(1));
1858 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
1862 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1863 /// access memory and has no other side effects at all.
1864 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1865 #define GET_NO_MEMORY_INTRINSICS
1866 #include "llvm/Intrinsics.gen"
1867 #undef GET_NO_MEMORY_INTRINSICS
1871 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1872 // have any side-effects or if it only reads memory.
1873 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1874 #define GET_SIDE_EFFECT_INFO
1875 #include "llvm/Intrinsics.gen"
1876 #undef GET_SIDE_EFFECT_INFO
1880 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1882 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1883 unsigned Intrinsic) {
1884 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1885 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1887 // Build the operand list.
1888 SmallVector<SDOperand, 8> Ops;
1889 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1891 // We don't need to serialize loads against other loads.
1892 Ops.push_back(DAG.getRoot());
1894 Ops.push_back(getRoot());
1898 // Add the intrinsic ID as an integer operand.
1899 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1901 // Add all operands of the call to the operand list.
1902 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1903 SDOperand Op = getValue(I.getOperand(i));
1905 // If this is a vector type, force it to the right vector type.
1906 if (Op.getValueType() == MVT::Vector) {
1907 const VectorType *OpTy = cast<VectorType>(I.getOperand(i)->getType());
1908 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1910 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1911 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1912 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1915 assert(TLI.isTypeLegal(Op.getValueType()) &&
1916 "Intrinsic uses a non-legal type?");
1920 std::vector<MVT::ValueType> VTs;
1921 if (I.getType() != Type::VoidTy) {
1922 MVT::ValueType VT = TLI.getValueType(I.getType());
1923 if (VT == MVT::Vector) {
1924 const VectorType *DestTy = cast<VectorType>(I.getType());
1925 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1927 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1928 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1931 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1935 VTs.push_back(MVT::Other);
1937 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
1942 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
1943 &Ops[0], Ops.size());
1944 else if (I.getType() != Type::VoidTy)
1945 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
1946 &Ops[0], Ops.size());
1948 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
1949 &Ops[0], Ops.size());
1952 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1954 PendingLoads.push_back(Chain);
1958 if (I.getType() != Type::VoidTy) {
1959 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
1960 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1961 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1962 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1963 DAG.getValueType(EVT));
1965 setValue(&I, Result);
1969 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1970 /// we want to emit this as a call to a named external function, return the name
1971 /// otherwise lower it and return null.
1973 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1974 switch (Intrinsic) {
1976 // By default, turn this into a target intrinsic node.
1977 visitTargetIntrinsic(I, Intrinsic);
1979 case Intrinsic::vastart: visitVAStart(I); return 0;
1980 case Intrinsic::vaend: visitVAEnd(I); return 0;
1981 case Intrinsic::vacopy: visitVACopy(I); return 0;
1982 case Intrinsic::returnaddress:
1983 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
1984 getValue(I.getOperand(1))));
1986 case Intrinsic::frameaddress:
1987 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
1988 getValue(I.getOperand(1))));
1990 case Intrinsic::setjmp:
1991 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
1993 case Intrinsic::longjmp:
1994 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
1996 case Intrinsic::memcpy_i32:
1997 case Intrinsic::memcpy_i64:
1998 visitMemIntrinsic(I, ISD::MEMCPY);
2000 case Intrinsic::memset_i32:
2001 case Intrinsic::memset_i64:
2002 visitMemIntrinsic(I, ISD::MEMSET);
2004 case Intrinsic::memmove_i32:
2005 case Intrinsic::memmove_i64:
2006 visitMemIntrinsic(I, ISD::MEMMOVE);
2009 case Intrinsic::dbg_stoppoint: {
2010 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2011 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2012 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2016 Ops[1] = getValue(SPI.getLineValue());
2017 Ops[2] = getValue(SPI.getColumnValue());
2019 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2020 assert(DD && "Not a debug information descriptor");
2021 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2023 Ops[3] = DAG.getString(CompileUnit->getFileName());
2024 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2026 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2031 case Intrinsic::dbg_region_start: {
2032 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2033 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2034 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2035 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2036 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2037 DAG.getConstant(LabelID, MVT::i32)));
2042 case Intrinsic::dbg_region_end: {
2043 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2044 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2045 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2046 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2047 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2048 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2053 case Intrinsic::dbg_func_start: {
2054 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2055 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2056 if (MMI && FSI.getSubprogram() &&
2057 MMI->Verify(FSI.getSubprogram())) {
2058 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
2059 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2060 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2065 case Intrinsic::dbg_declare: {
2066 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2067 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2068 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
2069 SDOperand AddressOp = getValue(DI.getAddress());
2070 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2071 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
2077 case Intrinsic::eh_exception: {
2078 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2081 // Add a label to mark the beginning of the landing pad. Deletion of the
2082 // landing pad can thus be detected via the MachineModuleInfo.
2083 unsigned LabelID = MMI->addLandingPad(CurMBB);
2084 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
2085 DAG.getConstant(LabelID, MVT::i32)));
2087 // Mark exception register as live in.
2088 unsigned Reg = TLI.getExceptionAddressRegister();
2089 if (Reg) CurMBB->addLiveIn(Reg);
2091 // Insert the EXCEPTIONADDR instruction.
2092 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2094 Ops[0] = DAG.getRoot();
2095 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2097 DAG.setRoot(Op.getValue(1));
2102 case Intrinsic::eh_handlers: {
2103 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2106 // Inform the MachineModuleInfo of the personality for this landing pad.
2107 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(2))) {
2108 if (CE->getOpcode() == Instruction::BitCast) {
2109 MMI->addPersonality(CurMBB,
2110 cast<Function>(CE->getOperand(0)));
2114 // Gather all the type infos for this landing pad and pass them along to
2115 // MachineModuleInfo.
2116 std::vector<GlobalVariable *> TyInfo;
2117 for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
2118 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(i))) {
2119 if (CE->getOpcode() == Instruction::BitCast) {
2120 TyInfo.push_back(cast<GlobalVariable>(CE->getOperand(0)));
2125 TyInfo.push_back(NULL);
2127 MMI->addCatchTypeInfo(CurMBB, TyInfo);
2129 // Mark exception selector register as live in.
2130 unsigned Reg = TLI.getExceptionSelectorRegister();
2131 if (Reg) CurMBB->addLiveIn(Reg);
2133 // Insert the EHSELECTION instruction.
2134 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2136 Ops[0] = getValue(I.getOperand(1));
2138 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2140 DAG.setRoot(Op.getValue(1));
2146 case Intrinsic::eh_typeid_for: {
2147 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2150 // Find the type id for the given typeinfo.
2151 GlobalVariable *GV = NULL;
2152 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(1))) {
2153 if (CE->getOpcode() == Instruction::BitCast) {
2154 GV = cast<GlobalVariable>(CE->getOperand(0));
2158 unsigned TypeID = MMI->getTypeIDFor(GV);
2159 setValue(&I, DAG.getConstant(TypeID, MVT::i32));
2165 case Intrinsic::sqrt_f32:
2166 case Intrinsic::sqrt_f64:
2167 setValue(&I, DAG.getNode(ISD::FSQRT,
2168 getValue(I.getOperand(1)).getValueType(),
2169 getValue(I.getOperand(1))));
2171 case Intrinsic::powi_f32:
2172 case Intrinsic::powi_f64:
2173 setValue(&I, DAG.getNode(ISD::FPOWI,
2174 getValue(I.getOperand(1)).getValueType(),
2175 getValue(I.getOperand(1)),
2176 getValue(I.getOperand(2))));
2178 case Intrinsic::pcmarker: {
2179 SDOperand Tmp = getValue(I.getOperand(1));
2180 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2183 case Intrinsic::readcyclecounter: {
2184 SDOperand Op = getRoot();
2185 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2186 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2189 DAG.setRoot(Tmp.getValue(1));
2192 case Intrinsic::bswap_i16:
2193 case Intrinsic::bswap_i32:
2194 case Intrinsic::bswap_i64:
2195 setValue(&I, DAG.getNode(ISD::BSWAP,
2196 getValue(I.getOperand(1)).getValueType(),
2197 getValue(I.getOperand(1))));
2199 case Intrinsic::cttz_i8:
2200 case Intrinsic::cttz_i16:
2201 case Intrinsic::cttz_i32:
2202 case Intrinsic::cttz_i64:
2203 setValue(&I, DAG.getNode(ISD::CTTZ,
2204 getValue(I.getOperand(1)).getValueType(),
2205 getValue(I.getOperand(1))));
2207 case Intrinsic::ctlz_i8:
2208 case Intrinsic::ctlz_i16:
2209 case Intrinsic::ctlz_i32:
2210 case Intrinsic::ctlz_i64:
2211 setValue(&I, DAG.getNode(ISD::CTLZ,
2212 getValue(I.getOperand(1)).getValueType(),
2213 getValue(I.getOperand(1))));
2215 case Intrinsic::ctpop_i8:
2216 case Intrinsic::ctpop_i16:
2217 case Intrinsic::ctpop_i32:
2218 case Intrinsic::ctpop_i64:
2219 setValue(&I, DAG.getNode(ISD::CTPOP,
2220 getValue(I.getOperand(1)).getValueType(),
2221 getValue(I.getOperand(1))));
2223 case Intrinsic::stacksave: {
2224 SDOperand Op = getRoot();
2225 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2226 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2228 DAG.setRoot(Tmp.getValue(1));
2231 case Intrinsic::stackrestore: {
2232 SDOperand Tmp = getValue(I.getOperand(1));
2233 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2236 case Intrinsic::prefetch:
2237 // FIXME: Currently discarding prefetches.
2243 void SelectionDAGLowering::LowerCallTo(CallInst &I,
2244 SDOperand Callee, unsigned OpIdx) {
2245 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
2246 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2248 TargetLowering::ArgListTy Args;
2249 TargetLowering::ArgListEntry Entry;
2250 Args.reserve(I.getNumOperands());
2251 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) {
2252 Value *Arg = I.getOperand(i);
2253 SDOperand ArgNode = getValue(Arg);
2254 Entry.Node = ArgNode; Entry.Ty = Arg->getType();
2255 Entry.isSigned = FTy->paramHasAttr(i, FunctionType::SExtAttribute);
2256 Entry.isInReg = FTy->paramHasAttr(i, FunctionType::InRegAttribute);
2257 Entry.isSRet = FTy->paramHasAttr(i, FunctionType::StructRetAttribute);
2258 Args.push_back(Entry);
2261 std::pair<SDOperand,SDOperand> Result =
2262 TLI.LowerCallTo(getRoot(), I.getType(),
2263 FTy->paramHasAttr(0,FunctionType::SExtAttribute),
2264 FTy->isVarArg(), I.getCallingConv(), I.isTailCall(),
2266 if (I.getType() != Type::VoidTy)
2267 setValue(&I, Result.first);
2268 DAG.setRoot(Result.second);
2272 void SelectionDAGLowering::visitCall(CallInst &I) {
2273 const char *RenameFn = 0;
2274 if (Function *F = I.getCalledFunction()) {
2275 if (F->isDeclaration())
2276 if (unsigned IID = F->getIntrinsicID()) {
2277 RenameFn = visitIntrinsicCall(I, IID);
2280 } else { // Not an LLVM intrinsic.
2281 const std::string &Name = F->getName();
2282 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
2283 if (I.getNumOperands() == 3 && // Basic sanity checks.
2284 I.getOperand(1)->getType()->isFloatingPoint() &&
2285 I.getType() == I.getOperand(1)->getType() &&
2286 I.getType() == I.getOperand(2)->getType()) {
2287 SDOperand LHS = getValue(I.getOperand(1));
2288 SDOperand RHS = getValue(I.getOperand(2));
2289 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
2293 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
2294 if (I.getNumOperands() == 2 && // Basic sanity checks.
2295 I.getOperand(1)->getType()->isFloatingPoint() &&
2296 I.getType() == I.getOperand(1)->getType()) {
2297 SDOperand Tmp = getValue(I.getOperand(1));
2298 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
2301 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
2302 if (I.getNumOperands() == 2 && // Basic sanity checks.
2303 I.getOperand(1)->getType()->isFloatingPoint() &&
2304 I.getType() == I.getOperand(1)->getType()) {
2305 SDOperand Tmp = getValue(I.getOperand(1));
2306 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
2309 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
2310 if (I.getNumOperands() == 2 && // Basic sanity checks.
2311 I.getOperand(1)->getType()->isFloatingPoint() &&
2312 I.getType() == I.getOperand(1)->getType()) {
2313 SDOperand Tmp = getValue(I.getOperand(1));
2314 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
2319 } else if (isa<InlineAsm>(I.getOperand(0))) {
2326 Callee = getValue(I.getOperand(0));
2328 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
2330 LowerCallTo(I, Callee, 1);
2334 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
2335 SDOperand &Chain, SDOperand &Flag)const{
2336 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
2337 Chain = Val.getValue(1);
2338 Flag = Val.getValue(2);
2340 // If the result was expanded, copy from the top part.
2341 if (Regs.size() > 1) {
2342 assert(Regs.size() == 2 &&
2343 "Cannot expand to more than 2 elts yet!");
2344 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
2345 Chain = Hi.getValue(1);
2346 Flag = Hi.getValue(2);
2347 if (DAG.getTargetLoweringInfo().isLittleEndian())
2348 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
2350 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
2353 // Otherwise, if the return value was promoted or extended, truncate it to the
2354 // appropriate type.
2355 if (RegVT == ValueVT)
2358 if (MVT::isInteger(RegVT)) {
2359 if (ValueVT < RegVT)
2360 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
2362 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
2364 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
2368 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
2369 /// specified value into the registers specified by this object. This uses
2370 /// Chain/Flag as the input and updates them for the output Chain/Flag.
2371 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
2372 SDOperand &Chain, SDOperand &Flag,
2373 MVT::ValueType PtrVT) const {
2374 if (Regs.size() == 1) {
2375 // If there is a single register and the types differ, this must be
2377 if (RegVT != ValueVT) {
2378 if (MVT::isInteger(RegVT)) {
2379 if (RegVT < ValueVT)
2380 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
2382 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
2384 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
2386 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
2387 Flag = Chain.getValue(1);
2389 std::vector<unsigned> R(Regs);
2390 if (!DAG.getTargetLoweringInfo().isLittleEndian())
2391 std::reverse(R.begin(), R.end());
2393 for (unsigned i = 0, e = R.size(); i != e; ++i) {
2394 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
2395 DAG.getConstant(i, PtrVT));
2396 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
2397 Flag = Chain.getValue(1);
2402 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
2403 /// operand list. This adds the code marker and includes the number of
2404 /// values added into it.
2405 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
2406 std::vector<SDOperand> &Ops) const {
2407 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
2408 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
2409 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
2412 /// isAllocatableRegister - If the specified register is safe to allocate,
2413 /// i.e. it isn't a stack pointer or some other special register, return the
2414 /// register class for the register. Otherwise, return null.
2415 static const TargetRegisterClass *
2416 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
2417 const TargetLowering &TLI, const MRegisterInfo *MRI) {
2418 MVT::ValueType FoundVT = MVT::Other;
2419 const TargetRegisterClass *FoundRC = 0;
2420 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
2421 E = MRI->regclass_end(); RCI != E; ++RCI) {
2422 MVT::ValueType ThisVT = MVT::Other;
2424 const TargetRegisterClass *RC = *RCI;
2425 // If none of the the value types for this register class are valid, we
2426 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2427 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2429 if (TLI.isTypeLegal(*I)) {
2430 // If we have already found this register in a different register class,
2431 // choose the one with the largest VT specified. For example, on
2432 // PowerPC, we favor f64 register classes over f32.
2433 if (FoundVT == MVT::Other ||
2434 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
2441 if (ThisVT == MVT::Other) continue;
2443 // NOTE: This isn't ideal. In particular, this might allocate the
2444 // frame pointer in functions that need it (due to them not being taken
2445 // out of allocation, because a variable sized allocation hasn't been seen
2446 // yet). This is a slight code pessimization, but should still work.
2447 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
2448 E = RC->allocation_order_end(MF); I != E; ++I)
2450 // We found a matching register class. Keep looking at others in case
2451 // we find one with larger registers that this physreg is also in.
2460 RegsForValue SelectionDAGLowering::
2461 GetRegistersForValue(const std::string &ConstrCode,
2462 MVT::ValueType VT, bool isOutReg, bool isInReg,
2463 std::set<unsigned> &OutputRegs,
2464 std::set<unsigned> &InputRegs) {
2465 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
2466 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
2467 std::vector<unsigned> Regs;
2469 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
2470 MVT::ValueType RegVT;
2471 MVT::ValueType ValueVT = VT;
2473 // If this is a constraint for a specific physical register, like {r17},
2475 if (PhysReg.first) {
2476 if (VT == MVT::Other)
2477 ValueVT = *PhysReg.second->vt_begin();
2479 // Get the actual register value type. This is important, because the user
2480 // may have asked for (e.g.) the AX register in i32 type. We need to
2481 // remember that AX is actually i16 to get the right extension.
2482 RegVT = *PhysReg.second->vt_begin();
2484 // This is a explicit reference to a physical register.
2485 Regs.push_back(PhysReg.first);
2487 // If this is an expanded reference, add the rest of the regs to Regs.
2489 TargetRegisterClass::iterator I = PhysReg.second->begin();
2490 TargetRegisterClass::iterator E = PhysReg.second->end();
2491 for (; *I != PhysReg.first; ++I)
2492 assert(I != E && "Didn't find reg!");
2494 // Already added the first reg.
2496 for (; NumRegs; --NumRegs, ++I) {
2497 assert(I != E && "Ran out of registers to allocate!");
2501 return RegsForValue(Regs, RegVT, ValueVT);
2504 // Otherwise, if this was a reference to an LLVM register class, create vregs
2505 // for this reference.
2506 std::vector<unsigned> RegClassRegs;
2507 if (PhysReg.second) {
2508 // If this is an early clobber or tied register, our regalloc doesn't know
2509 // how to maintain the constraint. If it isn't, go ahead and create vreg
2510 // and let the regalloc do the right thing.
2511 if (!isOutReg || !isInReg) {
2512 if (VT == MVT::Other)
2513 ValueVT = *PhysReg.second->vt_begin();
2514 RegVT = *PhysReg.second->vt_begin();
2516 // Create the appropriate number of virtual registers.
2517 SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
2518 for (; NumRegs; --NumRegs)
2519 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
2521 return RegsForValue(Regs, RegVT, ValueVT);
2524 // Otherwise, we can't allocate it. Let the code below figure out how to
2525 // maintain these constraints.
2526 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
2529 // This is a reference to a register class that doesn't directly correspond
2530 // to an LLVM register class. Allocate NumRegs consecutive, available,
2531 // registers from the class.
2532 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
2535 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
2536 MachineFunction &MF = *CurMBB->getParent();
2537 unsigned NumAllocated = 0;
2538 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
2539 unsigned Reg = RegClassRegs[i];
2540 // See if this register is available.
2541 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
2542 (isInReg && InputRegs.count(Reg))) { // Already used.
2543 // Make sure we find consecutive registers.
2548 // Check to see if this register is allocatable (i.e. don't give out the
2550 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
2552 // Make sure we find consecutive registers.
2557 // Okay, this register is good, we can use it.
2560 // If we allocated enough consecutive
2561 if (NumAllocated == NumRegs) {
2562 unsigned RegStart = (i-NumAllocated)+1;
2563 unsigned RegEnd = i+1;
2564 // Mark all of the allocated registers used.
2565 for (unsigned i = RegStart; i != RegEnd; ++i) {
2566 unsigned Reg = RegClassRegs[i];
2567 Regs.push_back(Reg);
2568 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
2569 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
2572 return RegsForValue(Regs, *RC->vt_begin(), VT);
2576 // Otherwise, we couldn't allocate enough registers for this.
2577 return RegsForValue();
2580 /// getConstraintGenerality - Return an integer indicating how general CT is.
2581 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2583 default: assert(0 && "Unknown constraint type!");
2584 case TargetLowering::C_Other:
2585 case TargetLowering::C_Unknown:
2587 case TargetLowering::C_Register:
2589 case TargetLowering::C_RegisterClass:
2591 case TargetLowering::C_Memory:
2596 static std::string GetMostGeneralConstraint(std::vector<std::string> &C,
2597 const TargetLowering &TLI) {
2598 assert(!C.empty() && "Must have at least one constraint");
2599 if (C.size() == 1) return C[0];
2601 std::string *Current = &C[0];
2602 // If we have multiple constraints, try to pick the most general one ahead
2603 // of time. This isn't a wonderful solution, but handles common cases.
2604 TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0][0]);
2605 for (unsigned j = 1, e = C.size(); j != e; ++j) {
2606 TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j][0]);
2607 if (getConstraintGenerality(ThisFlavor) >
2608 getConstraintGenerality(Flavor)) {
2609 // This constraint letter is more general than the previous one,
2611 Flavor = ThisFlavor;
2619 /// visitInlineAsm - Handle a call to an InlineAsm object.
2621 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
2622 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
2624 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
2627 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
2628 std::vector<MVT::ValueType> ConstraintVTs;
2630 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2631 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2632 /// if it is a def of that register.
2633 std::vector<SDOperand> AsmNodeOperands;
2634 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2635 AsmNodeOperands.push_back(AsmStr);
2637 SDOperand Chain = getRoot();
2640 // We fully assign registers here at isel time. This is not optimal, but
2641 // should work. For register classes that correspond to LLVM classes, we
2642 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2643 // over the constraints, collecting fixed registers that we know we can't use.
2644 std::set<unsigned> OutputRegs, InputRegs;
2646 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2647 std::string ConstraintCode =
2648 GetMostGeneralConstraint(Constraints[i].Codes, TLI);
2650 MVT::ValueType OpVT;
2652 // Compute the value type for each operand and add it to ConstraintVTs.
2653 switch (Constraints[i].Type) {
2654 case InlineAsm::isOutput:
2655 if (!Constraints[i].isIndirectOutput) {
2656 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2657 OpVT = TLI.getValueType(I.getType());
2659 const Type *OpTy = I.getOperand(OpNum)->getType();
2660 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2661 OpNum++; // Consumes a call operand.
2664 case InlineAsm::isInput:
2665 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2666 OpNum++; // Consumes a call operand.
2668 case InlineAsm::isClobber:
2673 ConstraintVTs.push_back(OpVT);
2675 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2676 continue; // Not assigned a fixed reg.
2678 // Build a list of regs that this operand uses. This always has a single
2679 // element for promoted/expanded operands.
2680 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2682 OutputRegs, InputRegs);
2684 switch (Constraints[i].Type) {
2685 case InlineAsm::isOutput:
2686 // We can't assign any other output to this register.
2687 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2688 // If this is an early-clobber output, it cannot be assigned to the same
2689 // value as the input reg.
2690 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2691 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2693 case InlineAsm::isInput:
2694 // We can't assign any other input to this register.
2695 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2697 case InlineAsm::isClobber:
2698 // Clobbered regs cannot be used as inputs or outputs.
2699 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2700 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2705 // Loop over all of the inputs, copying the operand values into the
2706 // appropriate registers and processing the output regs.
2707 RegsForValue RetValRegs;
2708 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2711 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2712 std::string ConstraintCode =
2713 GetMostGeneralConstraint(Constraints[i].Codes, TLI);
2715 switch (Constraints[i].Type) {
2716 case InlineAsm::isOutput: {
2717 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2718 if (ConstraintCode.size() == 1) // not a physreg name.
2719 CTy = TLI.getConstraintType(ConstraintCode[0]);
2721 if (CTy == TargetLowering::C_Memory) {
2723 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2725 // Check that the operand (the address to store to) isn't a float.
2726 if (!MVT::isInteger(InOperandVal.getValueType()))
2727 assert(0 && "MATCH FAIL!");
2729 if (!Constraints[i].isIndirectOutput)
2730 assert(0 && "MATCH FAIL!");
2732 OpNum++; // Consumes a call operand.
2734 // Extend/truncate to the right pointer type if needed.
2735 MVT::ValueType PtrType = TLI.getPointerTy();
2736 if (InOperandVal.getValueType() < PtrType)
2737 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2738 else if (InOperandVal.getValueType() > PtrType)
2739 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2741 // Add information to the INLINEASM node to know about this output.
2742 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2743 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2744 AsmNodeOperands.push_back(InOperandVal);
2748 // Otherwise, this is a register output.
2749 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2751 // If this is an early-clobber output, or if there is an input
2752 // constraint that matches this, we need to reserve the input register
2753 // so no other inputs allocate to it.
2754 bool UsesInputRegister = false;
2755 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2756 UsesInputRegister = true;
2758 // Copy the output from the appropriate register. Find a register that
2761 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2762 true, UsesInputRegister,
2763 OutputRegs, InputRegs);
2764 if (Regs.Regs.empty()) {
2765 cerr << "Couldn't allocate output reg for contraint '"
2766 << ConstraintCode << "'!\n";
2770 if (!Constraints[i].isIndirectOutput) {
2771 assert(RetValRegs.Regs.empty() &&
2772 "Cannot have multiple output constraints yet!");
2773 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2776 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2777 I.getOperand(OpNum)));
2778 OpNum++; // Consumes a call operand.
2781 // Add information to the INLINEASM node to know that this register is
2783 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2786 case InlineAsm::isInput: {
2787 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2788 OpNum++; // Consumes a call operand.
2790 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2791 // If this is required to match an output register we have already set,
2792 // just use its register.
2793 unsigned OperandNo = atoi(ConstraintCode.c_str());
2795 // Scan until we find the definition we already emitted of this operand.
2796 // When we find it, create a RegsForValue operand.
2797 unsigned CurOp = 2; // The first operand.
2798 for (; OperandNo; --OperandNo) {
2799 // Advance to the next operand.
2801 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2802 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2803 (NumOps & 7) == 4 /*MEM*/) &&
2804 "Skipped past definitions?");
2805 CurOp += (NumOps>>3)+1;
2809 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2810 if ((NumOps & 7) == 2 /*REGDEF*/) {
2811 // Add NumOps>>3 registers to MatchedRegs.
2812 RegsForValue MatchedRegs;
2813 MatchedRegs.ValueVT = InOperandVal.getValueType();
2814 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2815 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2817 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2818 MatchedRegs.Regs.push_back(Reg);
2821 // Use the produced MatchedRegs object to
2822 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2823 TLI.getPointerTy());
2824 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2827 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
2828 assert(0 && "matching constraints for memory operands unimp");
2832 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2833 if (ConstraintCode.size() == 1) // not a physreg name.
2834 CTy = TLI.getConstraintType(ConstraintCode[0]);
2836 if (CTy == TargetLowering::C_Other) {
2837 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
2838 ConstraintCode[0], DAG);
2839 if (!InOperandVal.Val) {
2840 cerr << "Invalid operand for inline asm constraint '"
2841 << ConstraintCode << "'!\n";
2845 // Add information to the INLINEASM node to know about this input.
2846 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2847 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2848 AsmNodeOperands.push_back(InOperandVal);
2850 } else if (CTy == TargetLowering::C_Memory) {
2853 // Check that the operand isn't a float.
2854 if (!MVT::isInteger(InOperandVal.getValueType()))
2855 assert(0 && "MATCH FAIL!");
2857 // Extend/truncate to the right pointer type if needed.
2858 MVT::ValueType PtrType = TLI.getPointerTy();
2859 if (InOperandVal.getValueType() < PtrType)
2860 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2861 else if (InOperandVal.getValueType() > PtrType)
2862 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2864 // Add information to the INLINEASM node to know about this input.
2865 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2866 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2867 AsmNodeOperands.push_back(InOperandVal);
2871 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2873 // Copy the input into the appropriate registers.
2874 RegsForValue InRegs =
2875 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2876 false, true, OutputRegs, InputRegs);
2877 // FIXME: should be match fail.
2878 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2880 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
2882 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2885 case InlineAsm::isClobber: {
2886 RegsForValue ClobberedRegs =
2887 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2888 OutputRegs, InputRegs);
2889 // Add the clobbered value to the operand list, so that the register
2890 // allocator is aware that the physreg got clobbered.
2891 if (!ClobberedRegs.Regs.empty())
2892 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2898 // Finish up input operands.
2899 AsmNodeOperands[0] = Chain;
2900 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2902 Chain = DAG.getNode(ISD::INLINEASM,
2903 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
2904 &AsmNodeOperands[0], AsmNodeOperands.size());
2905 Flag = Chain.getValue(1);
2907 // If this asm returns a register value, copy the result from that register
2908 // and set it as the value of the call.
2909 if (!RetValRegs.Regs.empty())
2910 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2912 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2914 // Process indirect outputs, first output all of the flagged copies out of
2916 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2917 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2918 Value *Ptr = IndirectStoresToEmit[i].second;
2919 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2920 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2923 // Emit the non-flagged stores from the physregs.
2924 SmallVector<SDOperand, 8> OutChains;
2925 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2926 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
2927 getValue(StoresToEmit[i].second),
2928 StoresToEmit[i].second, 0));
2929 if (!OutChains.empty())
2930 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2931 &OutChains[0], OutChains.size());
2936 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2937 SDOperand Src = getValue(I.getOperand(0));
2939 MVT::ValueType IntPtr = TLI.getPointerTy();
2941 if (IntPtr < Src.getValueType())
2942 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2943 else if (IntPtr > Src.getValueType())
2944 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2946 // Scale the source by the type size.
2947 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2948 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2949 Src, getIntPtrConstant(ElementSize));
2951 TargetLowering::ArgListTy Args;
2952 TargetLowering::ArgListEntry Entry;
2954 Entry.Ty = TLI.getTargetData()->getIntPtrType();
2955 Entry.isSigned = false;
2956 Entry.isInReg = false;
2957 Entry.isSRet = false;
2958 Args.push_back(Entry);
2960 std::pair<SDOperand,SDOperand> Result =
2961 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
2962 DAG.getExternalSymbol("malloc", IntPtr),
2964 setValue(&I, Result.first); // Pointers always fit in registers
2965 DAG.setRoot(Result.second);
2968 void SelectionDAGLowering::visitFree(FreeInst &I) {
2969 TargetLowering::ArgListTy Args;
2970 TargetLowering::ArgListEntry Entry;
2971 Entry.Node = getValue(I.getOperand(0));
2972 Entry.Ty = TLI.getTargetData()->getIntPtrType();
2973 Entry.isSigned = false;
2974 Entry.isInReg = false;
2975 Entry.isSRet = false;
2976 Args.push_back(Entry);
2977 MVT::ValueType IntPtr = TLI.getPointerTy();
2978 std::pair<SDOperand,SDOperand> Result =
2979 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
2980 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2981 DAG.setRoot(Result.second);
2984 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2985 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2986 // instructions are special in various ways, which require special support to
2987 // insert. The specified MachineInstr is created but not inserted into any
2988 // basic blocks, and the scheduler passes ownership of it to this method.
2989 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2990 MachineBasicBlock *MBB) {
2991 cerr << "If a target marks an instruction with "
2992 << "'usesCustomDAGSchedInserter', it must implement "
2993 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
2998 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2999 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3000 getValue(I.getOperand(1)),
3001 DAG.getSrcValue(I.getOperand(1))));
3004 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3005 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3006 getValue(I.getOperand(0)),
3007 DAG.getSrcValue(I.getOperand(0)));
3009 DAG.setRoot(V.getValue(1));
3012 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3013 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3014 getValue(I.getOperand(1)),
3015 DAG.getSrcValue(I.getOperand(1))));
3018 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3019 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3020 getValue(I.getOperand(1)),
3021 getValue(I.getOperand(2)),
3022 DAG.getSrcValue(I.getOperand(1)),
3023 DAG.getSrcValue(I.getOperand(2))));
3026 /// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either
3027 /// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate.
3028 static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg,
3029 unsigned &i, SelectionDAG &DAG,
3030 TargetLowering &TLI) {
3031 if (TLI.getTypeAction(VT) != TargetLowering::Expand)
3032 return SDOperand(Arg, i++);
3034 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
3035 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
3037 return DAG.getNode(ISD::BIT_CONVERT, VT,
3038 ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI));
3039 } else if (NumVals == 2) {
3040 SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
3041 SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
3042 if (!TLI.isLittleEndian())
3044 return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
3046 // Value scalarized into many values. Unimp for now.
3047 assert(0 && "Cannot expand i64 -> i16 yet!");
3052 /// TargetLowering::LowerArguments - This is the default LowerArguments
3053 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3054 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3055 /// integrated into SDISel.
3056 std::vector<SDOperand>
3057 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3058 const FunctionType *FTy = F.getFunctionType();
3059 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3060 std::vector<SDOperand> Ops;
3061 Ops.push_back(DAG.getRoot());
3062 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3063 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3065 // Add one result value for each formal argument.
3066 std::vector<MVT::ValueType> RetVals;
3068 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3070 MVT::ValueType VT = getValueType(I->getType());
3071 bool isInReg = FTy->paramHasAttr(j, FunctionType::InRegAttribute);
3072 bool isSRet = FTy->paramHasAttr(j, FunctionType::StructRetAttribute);
3073 unsigned OriginalAlignment =
3074 getTargetData()->getABITypeAlignment(I->getType());
3075 // Flags[31:27] -> OriginalAlignment
3076 // Flags[2] -> isSRet
3077 // Flags[1] -> isInReg
3078 unsigned Flags = (isInReg << 1) | (isSRet << 2) | (OriginalAlignment << 27);
3080 switch (getTypeAction(VT)) {
3081 default: assert(0 && "Unknown type action!");
3083 RetVals.push_back(VT);
3084 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3087 RetVals.push_back(getTypeToTransformTo(VT));
3088 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3091 if (VT != MVT::Vector) {
3092 // If this is a large integer, it needs to be broken up into small
3093 // integers. Figure out what the destination type is and how many small
3094 // integers it turns into.
3095 MVT::ValueType NVT = getTypeToExpandTo(VT);
3096 unsigned NumVals = getNumElements(VT);
3097 for (unsigned i = 0; i != NumVals; ++i) {
3098 RetVals.push_back(NVT);
3099 // if it isn't first piece, alignment must be 1
3100 if (i == 1) Flags = (Flags & 0x07ffffff) | (1 << 27);
3101 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3104 // Otherwise, this is a vector type. We only support legal vectors
3106 unsigned NumElems = cast<VectorType>(I->getType())->getNumElements();
3107 const Type *EltTy = cast<VectorType>(I->getType())->getElementType();
3109 // Figure out if there is a Packed type corresponding to this Vector
3110 // type. If so, convert to the vector type.
3111 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3112 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3113 RetVals.push_back(TVT);
3114 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3116 assert(0 && "Don't support illegal by-val vector arguments yet!");
3123 RetVals.push_back(MVT::Other);
3126 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3127 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3128 &Ops[0], Ops.size()).Val;
3130 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
3132 // Set up the return result vector.
3136 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3138 MVT::ValueType VT = getValueType(I->getType());
3140 switch (getTypeAction(VT)) {
3141 default: assert(0 && "Unknown type action!");
3143 Ops.push_back(SDOperand(Result, i++));
3146 SDOperand Op(Result, i++);
3147 if (MVT::isInteger(VT)) {
3148 if (FTy->paramHasAttr(Idx, FunctionType::SExtAttribute))
3149 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
3150 DAG.getValueType(VT));
3151 else if (FTy->paramHasAttr(Idx, FunctionType::ZExtAttribute))
3152 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
3153 DAG.getValueType(VT));
3154 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
3156 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3157 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
3163 if (VT != MVT::Vector) {
3164 // If this is a large integer or a floating point node that needs to be
3165 // expanded, it needs to be reassembled from small integers. Figure out
3166 // what the source elt type is and how many small integers it is.
3167 Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this));
3169 // Otherwise, this is a vector type. We only support legal vectors
3171 const VectorType *PTy = cast<VectorType>(I->getType());
3172 unsigned NumElems = PTy->getNumElements();
3173 const Type *EltTy = PTy->getElementType();
3175 // Figure out if there is a Packed type corresponding to this Vector
3176 // type. If so, convert to the vector type.
3177 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3178 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3179 SDOperand N = SDOperand(Result, i++);
3180 // Handle copies from generic vectors to registers.
3181 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
3182 DAG.getConstant(NumElems, MVT::i32),
3183 DAG.getValueType(getValueType(EltTy)));
3186 assert(0 && "Don't support illegal by-val vector arguments yet!");
3197 /// ExpandScalarCallArgs - Recursively expand call argument node by
3198 /// bit_converting it or extract a pair of elements from the larger node.
3199 static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg,
3201 SmallVector<SDOperand, 32> &Ops,
3203 TargetLowering &TLI,
3204 bool isFirst = true) {
3206 if (TLI.getTypeAction(VT) != TargetLowering::Expand) {
3207 // if it isn't first piece, alignment must be 1
3209 Flags = (Flags & 0x07ffffff) | (1 << 27);
3211 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3215 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
3216 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
3218 Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg);
3219 ExpandScalarCallArgs(EVT, Arg, Flags, Ops, DAG, TLI, isFirst);
3220 } else if (NumVals == 2) {
3221 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
3222 DAG.getConstant(0, TLI.getPointerTy()));
3223 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
3224 DAG.getConstant(1, TLI.getPointerTy()));
3225 if (!TLI.isLittleEndian())
3227 ExpandScalarCallArgs(EVT, Lo, Flags, Ops, DAG, TLI, isFirst);
3228 ExpandScalarCallArgs(EVT, Hi, Flags, Ops, DAG, TLI, false);
3230 // Value scalarized into many values. Unimp for now.
3231 assert(0 && "Cannot expand i64 -> i16 yet!");
3235 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
3236 /// implementation, which just inserts an ISD::CALL node, which is later custom
3237 /// lowered by the target to something concrete. FIXME: When all targets are
3238 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
3239 std::pair<SDOperand, SDOperand>
3240 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
3241 bool RetTyIsSigned, bool isVarArg,
3242 unsigned CallingConv, bool isTailCall,
3244 ArgListTy &Args, SelectionDAG &DAG) {
3245 SmallVector<SDOperand, 32> Ops;
3246 Ops.push_back(Chain); // Op#0 - Chain
3247 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
3248 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
3249 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
3250 Ops.push_back(Callee);
3252 // Handle all of the outgoing arguments.
3253 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
3254 MVT::ValueType VT = getValueType(Args[i].Ty);
3255 SDOperand Op = Args[i].Node;
3256 bool isSigned = Args[i].isSigned;
3257 bool isInReg = Args[i].isInReg;
3258 bool isSRet = Args[i].isSRet;
3259 unsigned OriginalAlignment =
3260 getTargetData()->getABITypeAlignment(Args[i].Ty);
3261 // Flags[31:27] -> OriginalAlignment
3262 // Flags[2] -> isSRet
3263 // Flags[1] -> isInReg
3264 // Flags[0] -> isSigned
3265 unsigned Flags = (isSRet << 2) | (isInReg << 1) | isSigned |
3266 (OriginalAlignment << 27);
3268 switch (getTypeAction(VT)) {
3269 default: assert(0 && "Unknown type action!");
3272 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3275 if (MVT::isInteger(VT)) {
3276 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3277 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
3279 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3280 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
3283 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3286 if (VT != MVT::Vector) {
3287 // If this is a large integer, it needs to be broken down into small
3288 // integers. Figure out what the source elt type is and how many small
3290 ExpandScalarCallArgs(VT, Op, Flags, Ops, DAG, *this);
3292 // Otherwise, this is a vector type. We only support legal vectors
3294 const VectorType *PTy = cast<VectorType>(Args[i].Ty);
3295 unsigned NumElems = PTy->getNumElements();
3296 const Type *EltTy = PTy->getElementType();
3298 // Figure out if there is a Packed type corresponding to this Vector
3299 // type. If so, convert to the vector type.
3300 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3301 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3302 // Insert a VBIT_CONVERT of the MVT::Vector type to the vector type.
3303 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
3305 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3307 assert(0 && "Don't support illegal by-val vector call args yet!");
3315 // Figure out the result value types.
3316 SmallVector<MVT::ValueType, 4> RetTys;
3318 if (RetTy != Type::VoidTy) {
3319 MVT::ValueType VT = getValueType(RetTy);
3320 switch (getTypeAction(VT)) {
3321 default: assert(0 && "Unknown type action!");
3323 RetTys.push_back(VT);
3326 RetTys.push_back(getTypeToTransformTo(VT));
3329 if (VT != MVT::Vector) {
3330 // If this is a large integer, it needs to be reassembled from small
3331 // integers. Figure out what the source elt type is and how many small
3333 MVT::ValueType NVT = getTypeToExpandTo(VT);
3334 unsigned NumVals = getNumElements(VT);
3335 for (unsigned i = 0; i != NumVals; ++i)
3336 RetTys.push_back(NVT);
3338 // Otherwise, this is a vector type. We only support legal vectors
3340 const VectorType *PTy = cast<VectorType>(RetTy);
3341 unsigned NumElems = PTy->getNumElements();
3342 const Type *EltTy = PTy->getElementType();
3344 // Figure out if there is a Packed type corresponding to this Vector
3345 // type. If so, convert to the vector type.
3346 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3347 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3348 RetTys.push_back(TVT);
3350 assert(0 && "Don't support illegal by-val vector call results yet!");
3357 RetTys.push_back(MVT::Other); // Always has a chain.
3359 // Finally, create the CALL node.
3360 SDOperand Res = DAG.getNode(ISD::CALL,
3361 DAG.getVTList(&RetTys[0], RetTys.size()),
3362 &Ops[0], Ops.size());
3364 // This returns a pair of operands. The first element is the
3365 // return value for the function (if RetTy is not VoidTy). The second
3366 // element is the outgoing token chain.
3368 if (RetTys.size() != 1) {
3369 MVT::ValueType VT = getValueType(RetTy);
3370 if (RetTys.size() == 2) {
3373 // If this value was promoted, truncate it down.
3374 if (ResVal.getValueType() != VT) {
3375 if (VT == MVT::Vector) {
3376 // Insert a VBITCONVERT to convert from the packed result type to the
3377 // MVT::Vector type.
3378 unsigned NumElems = cast<VectorType>(RetTy)->getNumElements();
3379 const Type *EltTy = cast<VectorType>(RetTy)->getElementType();
3381 // Figure out if there is a Packed type corresponding to this Vector
3382 // type. If so, convert to the vector type.
3383 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy),NumElems);
3384 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3385 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
3386 // "N x PTyElementVT" MVT::Vector type.
3387 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
3388 DAG.getConstant(NumElems, MVT::i32),
3389 DAG.getValueType(getValueType(EltTy)));
3393 } else if (MVT::isInteger(VT)) {
3394 unsigned AssertOp = ISD::AssertSext;
3396 AssertOp = ISD::AssertZext;
3397 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
3398 DAG.getValueType(VT));
3399 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
3401 assert(MVT::isFloatingPoint(VT));
3402 if (getTypeAction(VT) == Expand)
3403 ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal);
3405 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
3408 } else if (RetTys.size() == 3) {
3409 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
3410 Res.getValue(0), Res.getValue(1));
3413 assert(0 && "Case not handled yet!");
3417 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
3420 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3421 assert(0 && "LowerOperation not implemented for this target!");
3426 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
3427 SelectionDAG &DAG) {
3428 assert(0 && "CustomPromoteOperation not implemented for this target!");
3433 /// getMemsetValue - Vectorized representation of the memset value
3435 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
3436 SelectionDAG &DAG) {
3437 MVT::ValueType CurVT = VT;
3438 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
3439 uint64_t Val = C->getValue() & 255;
3441 while (CurVT != MVT::i8) {
3442 Val = (Val << Shift) | Val;
3444 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
3446 return DAG.getConstant(Val, VT);
3448 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
3450 while (CurVT != MVT::i8) {
3452 DAG.getNode(ISD::OR, VT,
3453 DAG.getNode(ISD::SHL, VT, Value,
3454 DAG.getConstant(Shift, MVT::i8)), Value);
3456 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
3463 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
3464 /// used when a memcpy is turned into a memset when the source is a constant
3466 static SDOperand getMemsetStringVal(MVT::ValueType VT,
3467 SelectionDAG &DAG, TargetLowering &TLI,
3468 std::string &Str, unsigned Offset) {
3470 unsigned MSB = getSizeInBits(VT) / 8;
3471 if (TLI.isLittleEndian())
3472 Offset = Offset + MSB - 1;
3473 for (unsigned i = 0; i != MSB; ++i) {
3474 Val = (Val << 8) | (unsigned char)Str[Offset];
3475 Offset += TLI.isLittleEndian() ? -1 : 1;
3477 return DAG.getConstant(Val, VT);
3480 /// getMemBasePlusOffset - Returns base and offset node for the
3481 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
3482 SelectionDAG &DAG, TargetLowering &TLI) {
3483 MVT::ValueType VT = Base.getValueType();
3484 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
3487 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
3488 /// to replace the memset / memcpy is below the threshold. It also returns the
3489 /// types of the sequence of memory ops to perform memset / memcpy.
3490 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
3491 unsigned Limit, uint64_t Size,
3492 unsigned Align, TargetLowering &TLI) {
3495 if (TLI.allowsUnalignedMemoryAccesses()) {
3498 switch (Align & 7) {
3514 MVT::ValueType LVT = MVT::i64;
3515 while (!TLI.isTypeLegal(LVT))
3516 LVT = (MVT::ValueType)((unsigned)LVT - 1);
3517 assert(MVT::isInteger(LVT));
3522 unsigned NumMemOps = 0;
3524 unsigned VTSize = getSizeInBits(VT) / 8;
3525 while (VTSize > Size) {
3526 VT = (MVT::ValueType)((unsigned)VT - 1);
3529 assert(MVT::isInteger(VT));
3531 if (++NumMemOps > Limit)
3533 MemOps.push_back(VT);
3540 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
3541 SDOperand Op1 = getValue(I.getOperand(1));
3542 SDOperand Op2 = getValue(I.getOperand(2));
3543 SDOperand Op3 = getValue(I.getOperand(3));
3544 SDOperand Op4 = getValue(I.getOperand(4));
3545 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
3546 if (Align == 0) Align = 1;
3548 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
3549 std::vector<MVT::ValueType> MemOps;
3551 // Expand memset / memcpy to a series of load / store ops
3552 // if the size operand falls below a certain threshold.
3553 SmallVector<SDOperand, 8> OutChains;
3555 default: break; // Do nothing for now.
3557 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
3558 Size->getValue(), Align, TLI)) {
3559 unsigned NumMemOps = MemOps.size();
3560 unsigned Offset = 0;
3561 for (unsigned i = 0; i < NumMemOps; i++) {
3562 MVT::ValueType VT = MemOps[i];
3563 unsigned VTSize = getSizeInBits(VT) / 8;
3564 SDOperand Value = getMemsetValue(Op2, VT, DAG);
3565 SDOperand Store = DAG.getStore(getRoot(), Value,
3566 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
3567 I.getOperand(1), Offset);
3568 OutChains.push_back(Store);
3575 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
3576 Size->getValue(), Align, TLI)) {
3577 unsigned NumMemOps = MemOps.size();
3578 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
3579 GlobalAddressSDNode *G = NULL;
3581 bool CopyFromStr = false;
3583 if (Op2.getOpcode() == ISD::GlobalAddress)
3584 G = cast<GlobalAddressSDNode>(Op2);
3585 else if (Op2.getOpcode() == ISD::ADD &&
3586 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3587 Op2.getOperand(1).getOpcode() == ISD::Constant) {
3588 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
3589 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
3592 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
3593 if (GV && GV->isConstant()) {
3594 Str = GV->getStringValue(false);
3602 for (unsigned i = 0; i < NumMemOps; i++) {
3603 MVT::ValueType VT = MemOps[i];
3604 unsigned VTSize = getSizeInBits(VT) / 8;
3605 SDOperand Value, Chain, Store;
3608 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
3611 DAG.getStore(Chain, Value,
3612 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
3613 I.getOperand(1), DstOff);
3615 Value = DAG.getLoad(VT, getRoot(),
3616 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
3617 I.getOperand(2), SrcOff);
3618 Chain = Value.getValue(1);
3620 DAG.getStore(Chain, Value,
3621 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
3622 I.getOperand(1), DstOff);
3624 OutChains.push_back(Store);
3633 if (!OutChains.empty()) {
3634 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3635 &OutChains[0], OutChains.size()));
3640 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
3643 //===----------------------------------------------------------------------===//
3644 // SelectionDAGISel code
3645 //===----------------------------------------------------------------------===//
3647 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
3648 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
3651 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
3652 // FIXME: we only modify the CFG to split critical edges. This
3653 // updates dom and loop info.
3654 AU.addRequired<AliasAnalysis>();
3658 /// OptimizeNoopCopyExpression - We have determined that the specified cast
3659 /// instruction is a noop copy (e.g. it's casting from one pointer type to
3660 /// another, int->uint, or int->sbyte on PPC.
3662 /// Return true if any changes are made.
3663 static bool OptimizeNoopCopyExpression(CastInst *CI) {
3664 BasicBlock *DefBB = CI->getParent();
3666 /// InsertedCasts - Only insert a cast in each block once.
3667 std::map<BasicBlock*, CastInst*> InsertedCasts;
3669 bool MadeChange = false;
3670 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
3672 Use &TheUse = UI.getUse();
3673 Instruction *User = cast<Instruction>(*UI);
3675 // Figure out which BB this cast is used in. For PHI's this is the
3676 // appropriate predecessor block.
3677 BasicBlock *UserBB = User->getParent();
3678 if (PHINode *PN = dyn_cast<PHINode>(User)) {
3679 unsigned OpVal = UI.getOperandNo()/2;
3680 UserBB = PN->getIncomingBlock(OpVal);
3683 // Preincrement use iterator so we don't invalidate it.
3686 // If this user is in the same block as the cast, don't change the cast.
3687 if (UserBB == DefBB) continue;
3689 // If we have already inserted a cast into this block, use it.
3690 CastInst *&InsertedCast = InsertedCasts[UserBB];
3692 if (!InsertedCast) {
3693 BasicBlock::iterator InsertPt = UserBB->begin();
3694 while (isa<PHINode>(InsertPt)) ++InsertPt;
3697 CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "",
3702 // Replace a use of the cast with a use of the new casat.
3703 TheUse = InsertedCast;
3706 // If we removed all uses, nuke the cast.
3707 if (CI->use_empty())
3708 CI->eraseFromParent();
3713 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3714 /// casting to the type of GEPI.
3715 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3716 Instruction *GEPI, Value *Ptr,
3718 if (V) return V; // Already computed.
3720 // Figure out the insertion point
3721 BasicBlock::iterator InsertPt;
3722 if (BB == GEPI->getParent()) {
3723 // If GEP is already inserted into BB, insert right after the GEP.
3727 // Otherwise, insert at the top of BB, after any PHI nodes
3728 InsertPt = BB->begin();
3729 while (isa<PHINode>(InsertPt)) ++InsertPt;
3732 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3733 // BB so that there is only one value live across basic blocks (the cast
3735 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3736 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3737 Ptr = CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(),
3740 // Add the offset, cast it to the right type.
3741 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3742 // Ptr is an integer type, GEPI is pointer type ==> IntToPtr
3743 return V = CastInst::create(Instruction::IntToPtr, Ptr, GEPI->getType(),
3747 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3748 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3749 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3750 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3751 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3752 /// the constant add into a load or store instruction. Additionally, if a user
3753 /// is a pointer-pointer cast, we look through it to find its users.
3754 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3755 Constant *PtrOffset, BasicBlock *DefBB,
3756 GetElementPtrInst *GEPI,
3757 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3758 while (!RepPtr->use_empty()) {
3759 Instruction *User = cast<Instruction>(RepPtr->use_back());
3761 // If the user is a Pointer-Pointer cast, recurse. Only BitCast can be
3762 // used for a Pointer-Pointer cast.
3763 if (isa<BitCastInst>(User)) {
3764 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3766 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3767 // could invalidate an iterator.
3768 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3772 // If this is a load of the pointer, or a store through the pointer, emit
3773 // the increment into the load/store block.
3774 Instruction *NewVal;
3775 if (isa<LoadInst>(User) ||
3776 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3777 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3778 User->getParent(), GEPI,
3781 // If this use is not foldable into the addressing mode, use a version
3782 // emitted in the GEP block.
3783 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3787 if (GEPI->getType() != RepPtr->getType()) {
3788 BasicBlock::iterator IP = NewVal;
3790 // NewVal must be a GEP which must be pointer type, so BitCast
3791 NewVal = new BitCastInst(NewVal, RepPtr->getType(), "", IP);
3793 User->replaceUsesOfWith(RepPtr, NewVal);
3798 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3799 /// selection, we want to be a bit careful about some things. In particular, if
3800 /// we have a GEP instruction that is used in a different block than it is
3801 /// defined, the addressing expression of the GEP cannot be folded into loads or
3802 /// stores that use it. In this case, decompose the GEP and move constant
3803 /// indices into blocks that use it.
3804 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3805 const TargetData *TD) {
3806 // If this GEP is only used inside the block it is defined in, there is no
3807 // need to rewrite it.
3808 bool isUsedOutsideDefBB = false;
3809 BasicBlock *DefBB = GEPI->getParent();
3810 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3812 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3813 isUsedOutsideDefBB = true;
3817 if (!isUsedOutsideDefBB) return false;
3819 // If this GEP has no non-zero constant indices, there is nothing we can do,
3821 bool hasConstantIndex = false;
3822 bool hasVariableIndex = false;
3823 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3824 E = GEPI->op_end(); OI != E; ++OI) {
3825 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3826 if (CI->getZExtValue()) {
3827 hasConstantIndex = true;
3831 hasVariableIndex = true;
3835 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3836 if (!hasConstantIndex && !hasVariableIndex) {
3837 /// The GEP operand must be a pointer, so must its result -> BitCast
3838 Value *NC = new BitCastInst(GEPI->getOperand(0), GEPI->getType(),
3839 GEPI->getName(), GEPI);
3840 GEPI->replaceAllUsesWith(NC);
3841 GEPI->eraseFromParent();
3845 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3846 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3849 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3850 // constant offset (which we now know is non-zero) and deal with it later.
3851 uint64_t ConstantOffset = 0;
3852 const Type *UIntPtrTy = TD->getIntPtrType();
3853 Value *Ptr = new PtrToIntInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3854 const Type *Ty = GEPI->getOperand(0)->getType();
3856 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3857 E = GEPI->op_end(); OI != E; ++OI) {
3859 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3860 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3862 ConstantOffset += TD->getStructLayout(StTy)->getElementOffset(Field);
3863 Ty = StTy->getElementType(Field);
3865 Ty = cast<SequentialType>(Ty)->getElementType();
3867 // Handle constant subscripts.
3868 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3869 if (CI->getZExtValue() == 0) continue;
3870 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CI->getSExtValue();
3874 // Ptr = Ptr + Idx * ElementSize;
3876 // Cast Idx to UIntPtrTy if needed.
3877 Idx = CastInst::createIntegerCast(Idx, UIntPtrTy, true/*SExt*/, "", GEPI);
3879 uint64_t ElementSize = TD->getTypeSize(Ty);
3880 // Mask off bits that should not be set.
3881 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3882 Constant *SizeCst = ConstantInt::get(UIntPtrTy, ElementSize);
3884 // Multiply by the element size and add to the base.
3885 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3886 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3890 // Make sure that the offset fits in uintptr_t.
3891 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3892 Constant *PtrOffset = ConstantInt::get(UIntPtrTy, ConstantOffset);
3894 // Okay, we have now emitted all of the variable index parts to the BB that
3895 // the GEP is defined in. Loop over all of the using instructions, inserting
3896 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3897 // instruction to use the newly computed value, making GEPI dead. When the
3898 // user is a load or store instruction address, we emit the add into the user
3899 // block, otherwise we use a canonical version right next to the gep (these
3900 // won't be foldable as addresses, so we might as well share the computation).
3902 std::map<BasicBlock*,Instruction*> InsertedExprs;
3903 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3905 // Finally, the GEP is dead, remove it.
3906 GEPI->eraseFromParent();
3912 /// SplitEdgeNicely - Split the critical edge from TI to it's specified
3913 /// successor if it will improve codegen. We only do this if the successor has
3914 /// phi nodes (otherwise critical edges are ok). If there is already another
3915 /// predecessor of the succ that is empty (and thus has no phi nodes), use it
3916 /// instead of introducing a new block.
3917 static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum, Pass *P) {
3918 BasicBlock *TIBB = TI->getParent();
3919 BasicBlock *Dest = TI->getSuccessor(SuccNum);
3920 assert(isa<PHINode>(Dest->begin()) &&
3921 "This should only be called if Dest has a PHI!");
3923 /// TIPHIValues - This array is lazily computed to determine the values of
3924 /// PHIs in Dest that TI would provide.
3925 std::vector<Value*> TIPHIValues;
3927 // Check to see if Dest has any blocks that can be used as a split edge for
3929 for (pred_iterator PI = pred_begin(Dest), E = pred_end(Dest); PI != E; ++PI) {
3930 BasicBlock *Pred = *PI;
3931 // To be usable, the pred has to end with an uncond branch to the dest.
3932 BranchInst *PredBr = dyn_cast<BranchInst>(Pred->getTerminator());
3933 if (!PredBr || !PredBr->isUnconditional() ||
3934 // Must be empty other than the branch.
3935 &Pred->front() != PredBr)
3938 // Finally, since we know that Dest has phi nodes in it, we have to make
3939 // sure that jumping to Pred will have the same affect as going to Dest in
3940 // terms of PHI values.
3943 bool FoundMatch = true;
3944 for (BasicBlock::iterator I = Dest->begin();
3945 (PN = dyn_cast<PHINode>(I)); ++I, ++PHINo) {
3946 if (PHINo == TIPHIValues.size())
3947 TIPHIValues.push_back(PN->getIncomingValueForBlock(TIBB));
3949 // If the PHI entry doesn't work, we can't use this pred.
3950 if (TIPHIValues[PHINo] != PN->getIncomingValueForBlock(Pred)) {
3956 // If we found a workable predecessor, change TI to branch to Succ.
3958 Dest->removePredecessor(TIBB);
3959 TI->setSuccessor(SuccNum, Pred);
3964 SplitCriticalEdge(TI, SuccNum, P, true);
3968 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3969 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3970 RegMap = MF.getSSARegMap();
3971 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
3973 // First, split all critical edges.
3975 // In this pass we also look for GEP and cast instructions that are used
3976 // across basic blocks and rewrite them to improve basic-block-at-a-time
3979 bool MadeChange = true;
3980 while (MadeChange) {
3982 for (Function::iterator FNI = Fn.begin(), E = Fn.end(); FNI != E; ++FNI) {
3983 // Split all critical edges where the dest block has a PHI.
3984 TerminatorInst *BBTI = FNI->getTerminator();
3985 if (BBTI->getNumSuccessors() > 1) {
3986 for (unsigned i = 0, e = BBTI->getNumSuccessors(); i != e; ++i)
3987 if (isa<PHINode>(BBTI->getSuccessor(i)->begin()) &&
3988 isCriticalEdge(BBTI, i, true))
3989 SplitEdgeNicely(BBTI, i, this);
3993 for (BasicBlock::iterator BBI = FNI->begin(), E = FNI->end(); BBI != E; ) {
3994 Instruction *I = BBI++;
3996 if (CallInst *CI = dyn_cast<CallInst>(I)) {
3997 // If we found an inline asm expession, and if the target knows how to
3998 // lower it to normal LLVM code, do so now.
3999 if (isa<InlineAsm>(CI->getCalledValue()))
4000 if (const TargetAsmInfo *TAI =
4001 TLI.getTargetMachine().getTargetAsmInfo()) {
4002 if (TAI->ExpandInlineAsm(CI))
4005 } else if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
4006 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
4007 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
4008 // If the source of the cast is a constant, then this should have
4009 // already been constant folded. The only reason NOT to constant fold
4010 // it is if something (e.g. LSR) was careful to place the constant
4011 // evaluation in a block other than then one that uses it (e.g. to hoist
4012 // the address of globals out of a loop). If this is the case, we don't
4013 // want to forward-subst the cast.
4014 if (isa<Constant>(CI->getOperand(0)))
4017 // If this is a noop copy, sink it into user blocks to reduce the number
4018 // of virtual registers that must be created and coallesced.
4019 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
4020 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
4022 // This is an fp<->int conversion?
4023 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
4026 // If this is an extension, it will be a zero or sign extension, which
4028 if (SrcVT < DstVT) continue;
4030 // If these values will be promoted, find out what they will be promoted
4031 // to. This helps us consider truncates on PPC as noop copies when they
4033 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
4034 SrcVT = TLI.getTypeToTransformTo(SrcVT);
4035 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
4036 DstVT = TLI.getTypeToTransformTo(DstVT);
4038 // If, after promotion, these are the same types, this is a noop copy.
4040 MadeChange |= OptimizeNoopCopyExpression(CI);
4046 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4048 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4049 SelectBasicBlock(I, MF, FuncInfo);
4051 // Add function live-ins to entry block live-in set.
4052 BasicBlock *EntryBB = &Fn.getEntryBlock();
4053 BB = FuncInfo.MBBMap[EntryBB];
4054 if (!MF.livein_empty())
4055 for (MachineFunction::livein_iterator I = MF.livein_begin(),
4056 E = MF.livein_end(); I != E; ++I)
4057 BB->addLiveIn(I->first);
4062 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4064 SDOperand Op = getValue(V);
4065 assert((Op.getOpcode() != ISD::CopyFromReg ||
4066 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4067 "Copy from a reg to the same reg!");
4069 // If this type is not legal, we must make sure to not create an invalid
4071 MVT::ValueType SrcVT = Op.getValueType();
4072 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
4073 if (SrcVT == DestVT) {
4074 return DAG.getCopyToReg(getRoot(), Reg, Op);
4075 } else if (SrcVT == MVT::Vector) {
4076 // Handle copies from generic vectors to registers.
4077 MVT::ValueType PTyElementVT, PTyLegalElementVT;
4078 unsigned NE = TLI.getVectorTypeBreakdown(cast<VectorType>(V->getType()),
4079 PTyElementVT, PTyLegalElementVT);
4081 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
4082 // MVT::Vector type.
4083 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
4084 DAG.getConstant(NE, MVT::i32),
4085 DAG.getValueType(PTyElementVT));
4087 // Loop over all of the elements of the resultant vector,
4088 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
4089 // copying them into output registers.
4090 SmallVector<SDOperand, 8> OutChains;
4091 SDOperand Root = getRoot();
4092 for (unsigned i = 0; i != NE; ++i) {
4093 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
4094 Op, DAG.getConstant(i, TLI.getPointerTy()));
4095 if (PTyElementVT == PTyLegalElementVT) {
4096 // Elements are legal.
4097 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
4098 } else if (PTyLegalElementVT > PTyElementVT) {
4099 // Elements are promoted.
4100 if (MVT::isFloatingPoint(PTyLegalElementVT))
4101 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
4103 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
4104 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
4106 // Elements are expanded.
4107 // The src value is expanded into multiple registers.
4108 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
4109 Elt, DAG.getConstant(0, TLI.getPointerTy()));
4110 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
4111 Elt, DAG.getConstant(1, TLI.getPointerTy()));
4112 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
4113 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
4116 return DAG.getNode(ISD::TokenFactor, MVT::Other,
4117 &OutChains[0], OutChains.size());
4118 } else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) {
4119 // The src value is promoted to the register.
4120 if (MVT::isFloatingPoint(SrcVT))
4121 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
4123 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
4124 return DAG.getCopyToReg(getRoot(), Reg, Op);
4126 DestVT = TLI.getTypeToExpandTo(SrcVT);
4127 unsigned NumVals = TLI.getNumElements(SrcVT);
4129 return DAG.getCopyToReg(getRoot(), Reg,
4130 DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
4131 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
4132 // The src value is expanded into multiple registers.
4133 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
4134 Op, DAG.getConstant(0, TLI.getPointerTy()));
4135 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
4136 Op, DAG.getConstant(1, TLI.getPointerTy()));
4137 Op = DAG.getCopyToReg(getRoot(), Reg, Lo);
4138 return DAG.getCopyToReg(Op, Reg+1, Hi);
4142 void SelectionDAGISel::
4143 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4144 std::vector<SDOperand> &UnorderedChains) {
4145 // If this is the entry block, emit arguments.
4146 Function &F = *LLVMBB->getParent();
4147 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4148 SDOperand OldRoot = SDL.DAG.getRoot();
4149 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4152 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4154 if (!AI->use_empty()) {
4155 SDL.setValue(AI, Args[a]);
4157 // If this argument is live outside of the entry block, insert a copy from
4158 // whereever we got it to the vreg that other BB's will reference it as.
4159 if (FuncInfo.ValueMap.count(AI)) {
4161 SDL.CopyValueToVirtualRegister(AI, FuncInfo.ValueMap[AI]);
4162 UnorderedChains.push_back(Copy);
4166 // Finally, if the target has anything special to do, allow it to do so.
4167 // FIXME: this should insert code into the DAG!
4168 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4171 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4172 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4173 FunctionLoweringInfo &FuncInfo) {
4174 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
4176 std::vector<SDOperand> UnorderedChains;
4178 // Lower any arguments needed in this block if this is the entry block.
4179 if (LLVMBB == &LLVMBB->getParent()->front())
4180 LowerArguments(LLVMBB, SDL, UnorderedChains);
4182 BB = FuncInfo.MBBMap[LLVMBB];
4183 SDL.setCurrentBasicBlock(BB);
4185 // Lower all of the non-terminator instructions.
4186 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4190 // Ensure that all instructions which are used outside of their defining
4191 // blocks are available as virtual registers.
4192 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4193 if (!I->use_empty() && !isa<PHINode>(I)) {
4194 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4195 if (VMI != FuncInfo.ValueMap.end())
4196 UnorderedChains.push_back(
4197 SDL.CopyValueToVirtualRegister(I, VMI->second));
4200 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4201 // ensure constants are generated when needed. Remember the virtual registers
4202 // that need to be added to the Machine PHI nodes as input. We cannot just
4203 // directly add them, because expansion might result in multiple MBB's for one
4204 // BB. As such, the start of the BB might correspond to a different MBB than
4207 TerminatorInst *TI = LLVMBB->getTerminator();
4209 // Emit constants only once even if used by multiple PHI nodes.
4210 std::map<Constant*, unsigned> ConstantsOut;
4212 // Vector bool would be better, but vector<bool> is really slow.
4213 std::vector<unsigned char> SuccsHandled;
4214 if (TI->getNumSuccessors())
4215 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4217 // Check successor nodes PHI nodes that expect a constant to be available from
4219 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4220 BasicBlock *SuccBB = TI->getSuccessor(succ);
4221 if (!isa<PHINode>(SuccBB->begin())) continue;
4222 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4224 // If this terminator has multiple identical successors (common for
4225 // switches), only handle each succ once.
4226 unsigned SuccMBBNo = SuccMBB->getNumber();
4227 if (SuccsHandled[SuccMBBNo]) continue;
4228 SuccsHandled[SuccMBBNo] = true;
4230 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4233 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4234 // nodes and Machine PHI nodes, but the incoming operands have not been
4236 for (BasicBlock::iterator I = SuccBB->begin();
4237 (PN = dyn_cast<PHINode>(I)); ++I) {
4238 // Ignore dead phi's.
4239 if (PN->use_empty()) continue;
4242 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4244 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4245 unsigned &RegOut = ConstantsOut[C];
4247 RegOut = FuncInfo.CreateRegForValue(C);
4248 UnorderedChains.push_back(
4249 SDL.CopyValueToVirtualRegister(C, RegOut));
4253 Reg = FuncInfo.ValueMap[PHIOp];
4255 assert(isa<AllocaInst>(PHIOp) &&
4256 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4257 "Didn't codegen value into a register!??");
4258 Reg = FuncInfo.CreateRegForValue(PHIOp);
4259 UnorderedChains.push_back(
4260 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4264 // Remember that this register needs to added to the machine PHI node as
4265 // the input for this MBB.
4266 MVT::ValueType VT = TLI.getValueType(PN->getType());
4267 unsigned NumElements;
4268 if (VT != MVT::Vector)
4269 NumElements = TLI.getNumElements(VT);
4271 MVT::ValueType VT1,VT2;
4273 TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
4276 for (unsigned i = 0, e = NumElements; i != e; ++i)
4277 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4280 ConstantsOut.clear();
4282 // Turn all of the unordered chains into one factored node.
4283 if (!UnorderedChains.empty()) {
4284 SDOperand Root = SDL.getRoot();
4285 if (Root.getOpcode() != ISD::EntryToken) {
4286 unsigned i = 0, e = UnorderedChains.size();
4287 for (; i != e; ++i) {
4288 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4289 if (UnorderedChains[i].Val->getOperand(0) == Root)
4290 break; // Don't add the root if we already indirectly depend on it.
4294 UnorderedChains.push_back(Root);
4296 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4297 &UnorderedChains[0], UnorderedChains.size()));
4300 // Lower the terminator after the copies are emitted.
4301 SDL.visit(*LLVMBB->getTerminator());
4303 // Copy over any CaseBlock records that may now exist due to SwitchInst
4304 // lowering, as well as any jump table information.
4305 SwitchCases.clear();
4306 SwitchCases = SDL.SwitchCases;
4309 // Make sure the root of the DAG is up-to-date.
4310 DAG.setRoot(SDL.getRoot());
4313 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4314 // Get alias analysis for load/store combining.
4315 AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
4317 // Run the DAG combiner in pre-legalize mode.
4318 DAG.Combine(false, AA);
4320 DOUT << "Lowered selection DAG:\n";
4323 // Second step, hack on the DAG until it only uses operations and types that
4324 // the target supports.
4327 DOUT << "Legalized selection DAG:\n";
4330 // Run the DAG combiner in post-legalize mode.
4331 DAG.Combine(true, AA);
4333 if (ViewISelDAGs) DAG.viewGraph();
4335 // Third, instruction select all of the operations to machine code, adding the
4336 // code to the MachineBasicBlock.
4337 InstructionSelectBasicBlock(DAG);
4339 DOUT << "Selected machine code:\n";
4343 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4344 FunctionLoweringInfo &FuncInfo) {
4345 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4347 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4350 // First step, lower LLVM code to some DAG. This DAG may use operations and
4351 // types that are not supported by the target.
4352 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4354 // Second step, emit the lowered DAG as machine code.
4355 CodeGenAndEmitDAG(DAG);
4358 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4359 // PHI nodes in successors.
4360 if (SwitchCases.empty() && JT.Reg == 0) {
4361 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4362 MachineInstr *PHI = PHINodesToUpdate[i].first;
4363 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4364 "This is not a machine PHI node that we are updating!");
4365 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4366 PHI->addMachineBasicBlockOperand(BB);
4371 // If the JumpTable record is filled in, then we need to emit a jump table.
4372 // Updating the PHI nodes is tricky in this case, since we need to determine
4373 // whether the PHI is a successor of the range check MBB or the jump table MBB
4375 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
4376 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4378 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4379 MachineBasicBlock *RangeBB = BB;
4380 // Set the current basic block to the mbb we wish to insert the code into
4382 SDL.setCurrentBasicBlock(BB);
4384 SDL.visitJumpTable(JT);
4385 SDAG.setRoot(SDL.getRoot());
4386 CodeGenAndEmitDAG(SDAG);
4388 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4389 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4390 MachineBasicBlock *PHIBB = PHI->getParent();
4391 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4392 "This is not a machine PHI node that we are updating!");
4393 if (PHIBB == JT.Default) {
4394 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4395 PHI->addMachineBasicBlockOperand(RangeBB);
4397 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4398 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4399 PHI->addMachineBasicBlockOperand(BB);
4405 // If the switch block involved a branch to one of the actual successors, we
4406 // need to update PHI nodes in that block.
4407 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4408 MachineInstr *PHI = PHINodesToUpdate[i].first;
4409 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4410 "This is not a machine PHI node that we are updating!");
4411 if (BB->isSuccessor(PHI->getParent())) {
4412 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4413 PHI->addMachineBasicBlockOperand(BB);
4417 // If we generated any switch lowering information, build and codegen any
4418 // additional DAGs necessary.
4419 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4420 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4422 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4424 // Set the current basic block to the mbb we wish to insert the code into
4425 BB = SwitchCases[i].ThisBB;
4426 SDL.setCurrentBasicBlock(BB);
4429 SDL.visitSwitchCase(SwitchCases[i]);
4430 SDAG.setRoot(SDL.getRoot());
4431 CodeGenAndEmitDAG(SDAG);
4433 // Handle any PHI nodes in successors of this chunk, as if we were coming
4434 // from the original BB before switch expansion. Note that PHI nodes can
4435 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4436 // handle them the right number of times.
4437 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4438 for (MachineBasicBlock::iterator Phi = BB->begin();
4439 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4440 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4441 for (unsigned pn = 0; ; ++pn) {
4442 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4443 if (PHINodesToUpdate[pn].first == Phi) {
4444 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4445 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4451 // Don't process RHS if same block as LHS.
4452 if (BB == SwitchCases[i].FalseBB)
4453 SwitchCases[i].FalseBB = 0;
4455 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4456 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4457 SwitchCases[i].FalseBB = 0;
4459 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4464 //===----------------------------------------------------------------------===//
4465 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4466 /// target node in the graph.
4467 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4468 if (ViewSchedDAGs) DAG.viewGraph();
4470 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4474 RegisterScheduler::setDefault(Ctor);
4477 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4483 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4484 return new HazardRecognizer();
4487 //===----------------------------------------------------------------------===//
4488 // Helper functions used by the generated instruction selector.
4489 //===----------------------------------------------------------------------===//
4490 // Calls to these methods are generated by tblgen.
4492 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4493 /// the dag combiner simplified the 255, we still want to match. RHS is the
4494 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4495 /// specified in the .td file (e.g. 255).
4496 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4497 int64_t DesiredMaskS) {
4498 uint64_t ActualMask = RHS->getValue();
4499 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4501 // If the actual mask exactly matches, success!
4502 if (ActualMask == DesiredMask)
4505 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4506 if (ActualMask & ~DesiredMask)
4509 // Otherwise, the DAG Combiner may have proven that the value coming in is
4510 // either already zero or is not demanded. Check for known zero input bits.
4511 uint64_t NeededMask = DesiredMask & ~ActualMask;
4512 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask))
4515 // TODO: check to see if missing bits are just not demanded.
4517 // Otherwise, this pattern doesn't match.
4521 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
4522 /// the dag combiner simplified the 255, we still want to match. RHS is the
4523 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
4524 /// specified in the .td file (e.g. 255).
4525 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
4526 int64_t DesiredMaskS) {
4527 uint64_t ActualMask = RHS->getValue();
4528 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4530 // If the actual mask exactly matches, success!
4531 if (ActualMask == DesiredMask)
4534 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4535 if (ActualMask & ~DesiredMask)
4538 // Otherwise, the DAG Combiner may have proven that the value coming in is
4539 // either already zero or is not demanded. Check for known zero input bits.
4540 uint64_t NeededMask = DesiredMask & ~ActualMask;
4542 uint64_t KnownZero, KnownOne;
4543 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
4545 // If all the missing bits in the or are already known to be set, match!
4546 if ((NeededMask & KnownOne) == NeededMask)
4549 // TODO: check to see if missing bits are just not demanded.
4551 // Otherwise, this pattern doesn't match.
4556 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
4557 /// by tblgen. Others should not call it.
4558 void SelectionDAGISel::
4559 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
4560 std::vector<SDOperand> InOps;
4561 std::swap(InOps, Ops);
4563 Ops.push_back(InOps[0]); // input chain.
4564 Ops.push_back(InOps[1]); // input asm string.
4566 unsigned i = 2, e = InOps.size();
4567 if (InOps[e-1].getValueType() == MVT::Flag)
4568 --e; // Don't process a flag operand if it is here.
4571 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
4572 if ((Flags & 7) != 4 /*MEM*/) {
4573 // Just skip over this operand, copying the operands verbatim.
4574 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
4575 i += (Flags >> 3) + 1;
4577 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
4578 // Otherwise, this is a memory operand. Ask the target to select it.
4579 std::vector<SDOperand> SelOps;
4580 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
4581 cerr << "Could not match memory address. Inline asm failure!\n";
4585 // Add this to the output node.
4586 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
4588 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
4593 // Add the flag input back if present.
4594 if (e != InOps.size())
4595 Ops.push_back(InOps.back());