1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
70 cl::desc("Enable extra verbose messages in the \"fast\" "
71 "instruction selector"));
73 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
74 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
75 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
76 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
77 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
78 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
79 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
81 // Standard binary operators...
82 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
83 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
84 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
85 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
86 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
87 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
88 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
89 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
90 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
91 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
92 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
93 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
95 // Logical operators...
96 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
97 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
98 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
100 // Memory instructions...
101 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
102 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
103 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
104 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
105 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
106 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
107 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
109 // Convert instructions...
110 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
111 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
112 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
113 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
114 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
115 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
116 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
117 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
118 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
119 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
120 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
121 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
123 // Other instructions...
124 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
125 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
126 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
127 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
128 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
129 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
130 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
131 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
132 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
133 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
134 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
135 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
136 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
137 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
138 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
142 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
143 cl::desc("Enable verbose messages in the \"fast\" "
144 "instruction selector"));
146 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
147 cl::desc("Enable abort calls when \"fast\" instruction fails"));
151 cl::desc("use Machine Branch Probability Info"),
152 cl::init(true), cl::Hidden);
156 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
157 cl::desc("Pop up a window to show dags before the first "
158 "dag combine pass"));
160 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
161 cl::desc("Pop up a window to show dags before legalize types"));
163 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
164 cl::desc("Pop up a window to show dags before legalize"));
166 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the second "
168 "dag combine pass"));
170 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before the post legalize types"
172 " dag combine pass"));
174 ViewISelDAGs("view-isel-dags", cl::Hidden,
175 cl::desc("Pop up a window to show isel dags as they are selected"));
177 ViewSchedDAGs("view-sched-dags", cl::Hidden,
178 cl::desc("Pop up a window to show sched dags as they are processed"));
180 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
181 cl::desc("Pop up a window to show SUnit dags after they are processed"));
183 static const bool ViewDAGCombine1 = false,
184 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
185 ViewDAGCombine2 = false,
186 ViewDAGCombineLT = false,
187 ViewISelDAGs = false, ViewSchedDAGs = false,
188 ViewSUnitDAGs = false;
191 //===---------------------------------------------------------------------===//
193 /// RegisterScheduler class - Track the registration of instruction schedulers.
195 //===---------------------------------------------------------------------===//
196 MachinePassRegistry RegisterScheduler::Registry;
198 //===---------------------------------------------------------------------===//
200 /// ISHeuristic command line option for instruction schedulers.
202 //===---------------------------------------------------------------------===//
203 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
204 RegisterPassParser<RegisterScheduler> >
205 ISHeuristic("pre-RA-sched",
206 cl::init(&createDefaultScheduler),
207 cl::desc("Instruction schedulers available (before register"
210 static RegisterScheduler
211 defaultListDAGScheduler("default", "Best scheduler for the target",
212 createDefaultScheduler);
215 //===--------------------------------------------------------------------===//
216 /// createDefaultScheduler - This creates an instruction scheduler appropriate
218 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
219 CodeGenOpt::Level OptLevel) {
220 const TargetLowering &TLI = IS->getTargetLowering();
221 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
223 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
224 TLI.getSchedulingPreference() == Sched::Source)
225 return createSourceListDAGScheduler(IS, OptLevel);
226 if (TLI.getSchedulingPreference() == Sched::RegPressure)
227 return createBURRListDAGScheduler(IS, OptLevel);
228 if (TLI.getSchedulingPreference() == Sched::Hybrid)
229 return createHybridListDAGScheduler(IS, OptLevel);
230 if (TLI.getSchedulingPreference() == Sched::VLIW)
231 return createVLIWDAGScheduler(IS, OptLevel);
232 assert(TLI.getSchedulingPreference() == Sched::ILP &&
233 "Unknown sched type!");
234 return createILPListDAGScheduler(IS, OptLevel);
238 // EmitInstrWithCustomInserter - This method should be implemented by targets
239 // that mark instructions with the 'usesCustomInserter' flag. These
240 // instructions are special in various ways, which require special support to
241 // insert. The specified MachineInstr is created but not inserted into any
242 // basic blocks, and this method is called to expand it into a sequence of
243 // instructions, potentially also creating new basic blocks and control flow.
244 // When new basic blocks are inserted and the edges from MBB to its successors
245 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
248 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
249 MachineBasicBlock *MBB) const {
251 dbgs() << "If a target marks an instruction with "
252 "'usesCustomInserter', it must implement "
253 "TargetLowering::EmitInstrWithCustomInserter!";
258 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
259 SDNode *Node) const {
260 assert(!MI->hasPostISelHook() &&
261 "If a target marks an instruction with 'hasPostISelHook', "
262 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
265 //===----------------------------------------------------------------------===//
266 // SelectionDAGISel code
267 //===----------------------------------------------------------------------===//
269 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
270 CodeGenOpt::Level OL) :
271 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
272 FuncInfo(new FunctionLoweringInfo(TLI)),
273 CurDAG(new SelectionDAG(tm, OL)),
274 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
278 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
279 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
280 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
281 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
284 SelectionDAGISel::~SelectionDAGISel() {
290 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
291 AU.addRequired<AliasAnalysis>();
292 AU.addPreserved<AliasAnalysis>();
293 AU.addRequired<GCModuleInfo>();
294 AU.addPreserved<GCModuleInfo>();
295 AU.addRequired<TargetLibraryInfo>();
296 if (UseMBPI && OptLevel != CodeGenOpt::None)
297 AU.addRequired<BranchProbabilityInfo>();
298 MachineFunctionPass::getAnalysisUsage(AU);
301 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
302 /// may trap on it. In this case we have to split the edge so that the path
303 /// through the predecessor block that doesn't go to the phi block doesn't
304 /// execute the possibly trapping instruction.
306 /// This is required for correctness, so it must be done at -O0.
308 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
309 // Loop for blocks with phi nodes.
310 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
311 PHINode *PN = dyn_cast<PHINode>(BB->begin());
312 if (PN == 0) continue;
315 // For each block with a PHI node, check to see if any of the input values
316 // are potentially trapping constant expressions. Constant expressions are
317 // the only potentially trapping value that can occur as the argument to a
319 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
320 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
321 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
322 if (CE == 0 || !CE->canTrap()) continue;
324 // The only case we have to worry about is when the edge is critical.
325 // Since this block has a PHI Node, we assume it has multiple input
326 // edges: check to see if the pred has multiple successors.
327 BasicBlock *Pred = PN->getIncomingBlock(i);
328 if (Pred->getTerminator()->getNumSuccessors() == 1)
331 // Okay, we have to split this edge.
332 SplitCriticalEdge(Pred->getTerminator(),
333 GetSuccessorNumber(Pred, BB), SDISel, true);
339 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
340 // Do some sanity-checking on the command-line options.
341 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
342 "-fast-isel-verbose requires -fast-isel");
343 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
344 "-fast-isel-abort requires -fast-isel");
346 const Function &Fn = *mf.getFunction();
347 const TargetInstrInfo &TII = *TM.getInstrInfo();
348 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
351 RegInfo = &MF->getRegInfo();
352 AA = &getAnalysis<AliasAnalysis>();
353 LibInfo = &getAnalysis<TargetLibraryInfo>();
354 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
355 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
357 TargetSubtargetInfo &ST =
358 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
359 ST.resetSubtargetFeatures(MF);
361 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
363 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
365 CurDAG->init(*MF, TTI);
366 FuncInfo->set(Fn, *MF);
368 if (UseMBPI && OptLevel != CodeGenOpt::None)
369 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
373 SDB->init(GFI, *AA, LibInfo);
375 SelectAllBasicBlocks(Fn);
377 // If the first basic block in the function has live ins that need to be
378 // copied into vregs, emit the copies into the top of the block before
379 // emitting the code for the block.
380 MachineBasicBlock *EntryMBB = MF->begin();
381 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
383 DenseMap<unsigned, unsigned> LiveInMap;
384 if (!FuncInfo->ArgDbgValues.empty())
385 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
386 E = RegInfo->livein_end(); LI != E; ++LI)
388 LiveInMap.insert(std::make_pair(LI->first, LI->second));
390 // Insert DBG_VALUE instructions for function arguments to the entry block.
391 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
392 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
393 unsigned Reg = MI->getOperand(0).getReg();
394 if (TargetRegisterInfo::isPhysicalRegister(Reg))
395 EntryMBB->insert(EntryMBB->begin(), MI);
397 MachineInstr *Def = RegInfo->getVRegDef(Reg);
398 MachineBasicBlock::iterator InsertPos = Def;
399 // FIXME: VR def may not be in entry block.
400 Def->getParent()->insert(llvm::next(InsertPos), MI);
403 // If Reg is live-in then update debug info to track its copy in a vreg.
404 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
405 if (LDI != LiveInMap.end()) {
406 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
407 MachineBasicBlock::iterator InsertPos = Def;
408 const MDNode *Variable =
409 MI->getOperand(MI->getNumOperands()-1).getMetadata();
410 unsigned Offset = MI->getOperand(1).getImm();
411 // Def is never a terminator here, so it is ok to increment InsertPos.
412 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
413 TII.get(TargetOpcode::DBG_VALUE))
414 .addReg(LDI->second, RegState::Debug)
415 .addImm(Offset).addMetadata(Variable);
417 // If this vreg is directly copied into an exported register then
418 // that COPY instructions also need DBG_VALUE, if it is the only
419 // user of LDI->second.
420 MachineInstr *CopyUseMI = NULL;
421 for (MachineRegisterInfo::use_iterator
422 UI = RegInfo->use_begin(LDI->second);
423 MachineInstr *UseMI = UI.skipInstruction();) {
424 if (UseMI->isDebugValue()) continue;
425 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
426 CopyUseMI = UseMI; continue;
428 // Otherwise this is another use or second copy use.
429 CopyUseMI = NULL; break;
432 MachineInstr *NewMI =
433 BuildMI(*MF, CopyUseMI->getDebugLoc(),
434 TII.get(TargetOpcode::DBG_VALUE))
435 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
436 .addImm(Offset).addMetadata(Variable);
437 MachineBasicBlock::iterator Pos = CopyUseMI;
438 EntryMBB->insertAfter(Pos, NewMI);
443 // Determine if there are any calls in this machine function.
444 MachineFrameInfo *MFI = MF->getFrameInfo();
445 if (!MFI->hasCalls()) {
446 for (MachineFunction::const_iterator
447 I = MF->begin(), E = MF->end(); I != E; ++I) {
448 const MachineBasicBlock *MBB = I;
449 for (MachineBasicBlock::const_iterator
450 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
451 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
453 if ((MCID.isCall() && !MCID.isReturn()) ||
454 II->isStackAligningInlineAsm()) {
455 MFI->setHasCalls(true);
463 // Determine if there is a call to setjmp in the machine function.
464 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
466 // Replace forward-declared registers with the registers containing
467 // the desired value.
468 MachineRegisterInfo &MRI = MF->getRegInfo();
469 for (DenseMap<unsigned, unsigned>::iterator
470 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
472 unsigned From = I->first;
473 unsigned To = I->second;
474 // If To is also scheduled to be replaced, find what its ultimate
477 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
482 MRI.replaceRegWith(From, To);
485 // Freeze the set of reserved registers now that MachineFrameInfo has been
486 // set up. All the information required by getReservedRegs() should be
488 MRI.freezeReservedRegs(*MF);
490 // Release function-specific state. SDB and CurDAG are already cleared
497 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
498 BasicBlock::const_iterator End,
500 // Lower all of the non-terminator instructions. If a call is emitted
501 // as a tail call, cease emitting nodes for this block. Terminators
502 // are handled below.
503 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
506 // Make sure the root of the DAG is up-to-date.
507 CurDAG->setRoot(SDB->getControlRoot());
508 HadTailCall = SDB->HasTailCall;
511 // Final step, emit the lowered DAG as machine code.
515 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
516 SmallPtrSet<SDNode*, 128> VisitedNodes;
517 SmallVector<SDNode*, 128> Worklist;
519 Worklist.push_back(CurDAG->getRoot().getNode());
525 SDNode *N = Worklist.pop_back_val();
527 // If we've already seen this node, ignore it.
528 if (!VisitedNodes.insert(N))
531 // Otherwise, add all chain operands to the worklist.
532 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
533 if (N->getOperand(i).getValueType() == MVT::Other)
534 Worklist.push_back(N->getOperand(i).getNode());
536 // If this is a CopyToReg with a vreg dest, process it.
537 if (N->getOpcode() != ISD::CopyToReg)
540 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
541 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
544 // Ignore non-scalar or non-integer values.
545 SDValue Src = N->getOperand(2);
546 EVT SrcVT = Src.getValueType();
547 if (!SrcVT.isInteger() || SrcVT.isVector())
550 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
551 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
552 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
553 } while (!Worklist.empty());
556 void SelectionDAGISel::CodeGenAndEmitDAG() {
557 std::string GroupName;
558 if (TimePassesIsEnabled)
559 GroupName = "Instruction Selection and Scheduling";
560 std::string BlockName;
561 int BlockNumber = -1;
564 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
565 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
569 BlockNumber = FuncInfo->MBB->getNumber();
570 BlockName = MF->getName().str() + ":" +
571 FuncInfo->MBB->getBasicBlock()->getName().str();
573 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
574 << " '" << BlockName << "'\n"; CurDAG->dump());
576 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
578 // Run the DAG combiner in pre-legalize mode.
580 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
581 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
584 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
585 << " '" << BlockName << "'\n"; CurDAG->dump());
587 // Second step, hack on the DAG until it only uses operations and types that
588 // the target supports.
589 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
594 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
595 Changed = CurDAG->LegalizeTypes();
598 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
599 << " '" << BlockName << "'\n"; CurDAG->dump());
602 if (ViewDAGCombineLT)
603 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
605 // Run the DAG combiner in post-type-legalize mode.
607 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
608 TimePassesIsEnabled);
609 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
612 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
613 << " '" << BlockName << "'\n"; CurDAG->dump());
617 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
618 Changed = CurDAG->LegalizeVectors();
623 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
624 CurDAG->LegalizeTypes();
627 if (ViewDAGCombineLT)
628 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
630 // Run the DAG combiner in post-type-legalize mode.
632 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
633 TimePassesIsEnabled);
634 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
637 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
638 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
641 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
644 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
648 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
649 << " '" << BlockName << "'\n"; CurDAG->dump());
651 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
653 // Run the DAG combiner in post-legalize mode.
655 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
656 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
659 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
660 << " '" << BlockName << "'\n"; CurDAG->dump());
662 if (OptLevel != CodeGenOpt::None)
663 ComputeLiveOutVRegInfo();
665 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
667 // Third, instruction select all of the operations to machine code, adding the
668 // code to the MachineBasicBlock.
670 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
671 DoInstructionSelection();
674 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
675 << " '" << BlockName << "'\n"; CurDAG->dump());
677 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
679 // Schedule machine code.
680 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
682 NamedRegionTimer T("Instruction Scheduling", GroupName,
683 TimePassesIsEnabled);
684 Scheduler->Run(CurDAG, FuncInfo->MBB);
687 if (ViewSUnitDAGs) Scheduler->viewGraph();
689 // Emit machine code to BB. This can change 'BB' to the last block being
691 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
693 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
695 // FuncInfo->InsertPt is passed by reference and set to the end of the
696 // scheduled instructions.
697 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
700 // If the block was split, make sure we update any references that are used to
701 // update PHI nodes later on.
702 if (FirstMBB != LastMBB)
703 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
705 // Free the scheduler state.
707 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
708 TimePassesIsEnabled);
712 // Free the SelectionDAG state, now that we're finished with it.
717 /// ISelUpdater - helper class to handle updates of the instruction selection
719 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
720 SelectionDAG::allnodes_iterator &ISelPosition;
722 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
723 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
725 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
726 /// deleted is the current ISelPosition node, update ISelPosition.
728 virtual void NodeDeleted(SDNode *N, SDNode *E) {
729 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
733 } // end anonymous namespace
735 void SelectionDAGISel::DoInstructionSelection() {
736 DEBUG(errs() << "===== Instruction selection begins: BB#"
737 << FuncInfo->MBB->getNumber()
738 << " '" << FuncInfo->MBB->getName() << "'\n");
742 // Select target instructions for the DAG.
744 // Number all nodes with a topological order and set DAGSize.
745 DAGSize = CurDAG->AssignTopologicalOrder();
747 // Create a dummy node (which is not added to allnodes), that adds
748 // a reference to the root node, preventing it from being deleted,
749 // and tracking any changes of the root.
750 HandleSDNode Dummy(CurDAG->getRoot());
751 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
754 // Make sure that ISelPosition gets properly updated when nodes are deleted
755 // in calls made from this function.
756 ISelUpdater ISU(*CurDAG, ISelPosition);
758 // The AllNodes list is now topological-sorted. Visit the
759 // nodes by starting at the end of the list (the root of the
760 // graph) and preceding back toward the beginning (the entry
762 while (ISelPosition != CurDAG->allnodes_begin()) {
763 SDNode *Node = --ISelPosition;
764 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
765 // but there are currently some corner cases that it misses. Also, this
766 // makes it theoretically possible to disable the DAGCombiner.
767 if (Node->use_empty())
770 SDNode *ResNode = Select(Node);
772 // FIXME: This is pretty gross. 'Select' should be changed to not return
773 // anything at all and this code should be nuked with a tactical strike.
775 // If node should not be replaced, continue with the next one.
776 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
780 ReplaceUses(Node, ResNode);
782 // If after the replacement this node is not used any more,
783 // remove this dead node.
784 if (Node->use_empty()) // Don't delete EntryToken, etc.
785 CurDAG->RemoveDeadNode(Node);
788 CurDAG->setRoot(Dummy.getValue());
791 DEBUG(errs() << "===== Instruction selection ends:\n");
793 PostprocessISelDAG();
796 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
797 /// do other setup for EH landing-pad blocks.
798 void SelectionDAGISel::PrepareEHLandingPad() {
799 MachineBasicBlock *MBB = FuncInfo->MBB;
801 // Add a label to mark the beginning of the landing pad. Deletion of the
802 // landing pad can thus be detected via the MachineModuleInfo.
803 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
805 // Assign the call site to the landing pad's begin label.
806 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
808 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
809 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
812 // Mark exception register as live in.
813 unsigned Reg = TLI.getExceptionPointerRegister();
814 if (Reg) MBB->addLiveIn(Reg);
816 // Mark exception selector register as live in.
817 Reg = TLI.getExceptionSelectorRegister();
818 if (Reg) MBB->addLiveIn(Reg);
821 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
822 /// load into the specified FoldInst. Note that we could have a sequence where
823 /// multiple LLVM IR instructions are folded into the same machineinstr. For
824 /// example we could have:
825 /// A: x = load i32 *P
826 /// B: y = icmp A, 42
829 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
830 /// any other folded instructions) because it is between A and C.
832 /// If we succeed in folding the load into the operation, return true.
834 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
835 const Instruction *FoldInst,
837 // We know that the load has a single use, but don't know what it is. If it
838 // isn't one of the folded instructions, then we can't succeed here. Handle
839 // this by scanning the single-use users of the load until we get to FoldInst.
840 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
842 const Instruction *TheUser = LI->use_back();
843 while (TheUser != FoldInst && // Scan up until we find FoldInst.
844 // Stay in the right block.
845 TheUser->getParent() == FoldInst->getParent() &&
846 --MaxUsers) { // Don't scan too far.
847 // If there are multiple or no uses of this instruction, then bail out.
848 if (!TheUser->hasOneUse())
851 TheUser = TheUser->use_back();
854 // If we didn't find the fold instruction, then we failed to collapse the
856 if (TheUser != FoldInst)
859 // Don't try to fold volatile loads. Target has to deal with alignment
861 if (LI->isVolatile()) return false;
863 // Figure out which vreg this is going into. If there is no assigned vreg yet
864 // then there actually was no reference to it. Perhaps the load is referenced
865 // by a dead instruction.
866 unsigned LoadReg = FastIS->getRegForValue(LI);
870 // Check to see what the uses of this vreg are. If it has no uses, or more
871 // than one use (at the machine instr level) then we can't fold it.
872 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
873 if (RI == RegInfo->reg_end())
876 // See if there is exactly one use of the vreg. If there are multiple uses,
877 // then the instruction got lowered to multiple machine instructions or the
878 // use of the loaded value ended up being multiple operands of the result, in
879 // either case, we can't fold this.
880 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
881 if (PostRI != RegInfo->reg_end())
884 assert(RI.getOperand().isUse() &&
885 "The only use of the vreg must be a use, we haven't emitted the def!");
887 MachineInstr *User = &*RI;
889 // Set the insertion point properly. Folding the load can cause generation of
890 // other random instructions (like sign extends) for addressing modes, make
891 // sure they get inserted in a logical place before the new instruction.
892 FuncInfo->InsertPt = User;
893 FuncInfo->MBB = User->getParent();
895 // Ask the target to try folding the load.
896 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
899 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
900 /// side-effect free and is either dead or folded into a generated instruction.
901 /// Return false if it needs to be emitted.
902 static bool isFoldedOrDeadInstruction(const Instruction *I,
903 FunctionLoweringInfo *FuncInfo) {
904 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
905 !isa<TerminatorInst>(I) && // Terminators aren't folded.
906 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
907 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
908 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
912 // Collect per Instruction statistics for fast-isel misses. Only those
913 // instructions that cause the bail are accounted for. It does not account for
914 // instructions higher in the block. Thus, summing the per instructions stats
915 // will not add up to what is reported by NumFastIselFailures.
916 static void collectFailStats(const Instruction *I) {
917 switch (I->getOpcode()) {
918 default: assert (0 && "<Invalid operator> ");
921 case Instruction::Ret: NumFastIselFailRet++; return;
922 case Instruction::Br: NumFastIselFailBr++; return;
923 case Instruction::Switch: NumFastIselFailSwitch++; return;
924 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
925 case Instruction::Invoke: NumFastIselFailInvoke++; return;
926 case Instruction::Resume: NumFastIselFailResume++; return;
927 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
929 // Standard binary operators...
930 case Instruction::Add: NumFastIselFailAdd++; return;
931 case Instruction::FAdd: NumFastIselFailFAdd++; return;
932 case Instruction::Sub: NumFastIselFailSub++; return;
933 case Instruction::FSub: NumFastIselFailFSub++; return;
934 case Instruction::Mul: NumFastIselFailMul++; return;
935 case Instruction::FMul: NumFastIselFailFMul++; return;
936 case Instruction::UDiv: NumFastIselFailUDiv++; return;
937 case Instruction::SDiv: NumFastIselFailSDiv++; return;
938 case Instruction::FDiv: NumFastIselFailFDiv++; return;
939 case Instruction::URem: NumFastIselFailURem++; return;
940 case Instruction::SRem: NumFastIselFailSRem++; return;
941 case Instruction::FRem: NumFastIselFailFRem++; return;
943 // Logical operators...
944 case Instruction::And: NumFastIselFailAnd++; return;
945 case Instruction::Or: NumFastIselFailOr++; return;
946 case Instruction::Xor: NumFastIselFailXor++; return;
948 // Memory instructions...
949 case Instruction::Alloca: NumFastIselFailAlloca++; return;
950 case Instruction::Load: NumFastIselFailLoad++; return;
951 case Instruction::Store: NumFastIselFailStore++; return;
952 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
953 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
954 case Instruction::Fence: NumFastIselFailFence++; return;
955 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
957 // Convert instructions...
958 case Instruction::Trunc: NumFastIselFailTrunc++; return;
959 case Instruction::ZExt: NumFastIselFailZExt++; return;
960 case Instruction::SExt: NumFastIselFailSExt++; return;
961 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
962 case Instruction::FPExt: NumFastIselFailFPExt++; return;
963 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
964 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
965 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
966 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
967 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
968 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
969 case Instruction::BitCast: NumFastIselFailBitCast++; return;
971 // Other instructions...
972 case Instruction::ICmp: NumFastIselFailICmp++; return;
973 case Instruction::FCmp: NumFastIselFailFCmp++; return;
974 case Instruction::PHI: NumFastIselFailPHI++; return;
975 case Instruction::Select: NumFastIselFailSelect++; return;
976 case Instruction::Call: NumFastIselFailCall++; return;
977 case Instruction::Shl: NumFastIselFailShl++; return;
978 case Instruction::LShr: NumFastIselFailLShr++; return;
979 case Instruction::AShr: NumFastIselFailAShr++; return;
980 case Instruction::VAArg: NumFastIselFailVAArg++; return;
981 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
982 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
983 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
984 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
985 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
986 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
991 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
992 // Initialize the Fast-ISel state, if needed.
993 FastISel *FastIS = 0;
994 if (TM.Options.EnableFastISel)
995 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
997 // Iterate over all basic blocks in the function.
998 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
999 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1000 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1001 const BasicBlock *LLVMBB = *I;
1003 if (OptLevel != CodeGenOpt::None) {
1004 bool AllPredsVisited = true;
1005 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1007 if (!FuncInfo->VisitedBBs.count(*PI)) {
1008 AllPredsVisited = false;
1013 if (AllPredsVisited) {
1014 for (BasicBlock::const_iterator I = LLVMBB->begin();
1015 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1016 FuncInfo->ComputePHILiveOutRegInfo(PN);
1018 for (BasicBlock::const_iterator I = LLVMBB->begin();
1019 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1020 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1023 FuncInfo->VisitedBBs.insert(LLVMBB);
1026 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1027 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1029 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1030 BasicBlock::const_iterator const End = LLVMBB->end();
1031 BasicBlock::const_iterator BI = End;
1033 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1035 // Setup an EH landing-pad block.
1036 if (FuncInfo->MBB->isLandingPad())
1037 PrepareEHLandingPad();
1039 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1041 FastIS->startNewBlock();
1043 // Emit code for any incoming arguments. This must happen before
1044 // beginning FastISel on the entry block.
1045 if (LLVMBB == &Fn.getEntryBlock()) {
1046 // Lower any arguments needed in this block if this is the entry block.
1047 if (!FastIS->LowerArguments()) {
1048 // Call target indepedent SDISel argument lowering code if the target
1049 // specific routine is not successful.
1050 LowerArguments(LLVMBB);
1051 CurDAG->setRoot(SDB->getControlRoot());
1053 CodeGenAndEmitDAG();
1056 // If we inserted any instructions at the beginning, make a note of
1057 // where they are, so we can be sure to emit subsequent instructions
1059 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1060 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1062 FastIS->setLastLocalValue(0);
1065 unsigned NumFastIselRemaining = std::distance(Begin, End);
1066 // Do FastISel on as many instructions as possible.
1067 for (; BI != Begin; --BI) {
1068 const Instruction *Inst = llvm::prior(BI);
1070 // If we no longer require this instruction, skip it.
1071 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1072 --NumFastIselRemaining;
1076 // Bottom-up: reset the insert pos at the top, after any local-value
1078 FastIS->recomputeInsertPt();
1080 // Try to select the instruction with FastISel.
1081 if (FastIS->SelectInstruction(Inst)) {
1082 --NumFastIselRemaining;
1083 ++NumFastIselSuccess;
1084 // If fast isel succeeded, skip over all the folded instructions, and
1085 // then see if there is a load right before the selected instructions.
1086 // Try to fold the load if so.
1087 const Instruction *BeforeInst = Inst;
1088 while (BeforeInst != Begin) {
1089 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1090 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1093 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1094 BeforeInst->hasOneUse() &&
1095 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1096 // If we succeeded, don't re-select the load.
1097 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1098 --NumFastIselRemaining;
1099 ++NumFastIselSuccess;
1105 if (EnableFastISelVerbose2)
1106 collectFailStats(Inst);
1109 // Then handle certain instructions as single-LLVM-Instruction blocks.
1110 if (isa<CallInst>(Inst)) {
1112 if (EnableFastISelVerbose || EnableFastISelAbort) {
1113 dbgs() << "FastISel missed call: ";
1117 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1118 unsigned &R = FuncInfo->ValueMap[Inst];
1120 R = FuncInfo->CreateRegs(Inst->getType());
1123 bool HadTailCall = false;
1124 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1125 SelectBasicBlock(Inst, BI, HadTailCall);
1127 // If the call was emitted as a tail call, we're done with the block.
1128 // We also need to delete any previously emitted instructions.
1130 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1135 // Recompute NumFastIselRemaining as Selection DAG instruction
1136 // selection may have handled the call, input args, etc.
1137 unsigned RemainingNow = std::distance(Begin, BI);
1138 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1139 NumFastIselRemaining = RemainingNow;
1143 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1144 // Don't abort, and use a different message for terminator misses.
1145 NumFastIselFailures += NumFastIselRemaining;
1146 if (EnableFastISelVerbose || EnableFastISelAbort) {
1147 dbgs() << "FastISel missed terminator: ";
1151 NumFastIselFailures += NumFastIselRemaining;
1152 if (EnableFastISelVerbose || EnableFastISelAbort) {
1153 dbgs() << "FastISel miss: ";
1156 if (EnableFastISelAbort)
1157 // The "fast" selector couldn't handle something and bailed.
1158 // For the purpose of debugging, just abort.
1159 llvm_unreachable("FastISel didn't select the entire block");
1164 FastIS->recomputeInsertPt();
1166 // Lower any arguments needed in this block if this is the entry block.
1167 if (LLVMBB == &Fn.getEntryBlock())
1168 LowerArguments(LLVMBB);
1174 ++NumFastIselBlocks;
1177 // Run SelectionDAG instruction selection on the remainder of the block
1178 // not handled by FastISel. If FastISel is not run, this is the entire
1181 SelectBasicBlock(Begin, BI, HadTailCall);
1185 FuncInfo->PHINodesToUpdate.clear();
1189 SDB->clearDanglingDebugInfo();
1193 SelectionDAGISel::FinishBasicBlock() {
1195 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1196 << FuncInfo->PHINodesToUpdate.size() << "\n";
1197 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1198 dbgs() << "Node " << i << " : ("
1199 << FuncInfo->PHINodesToUpdate[i].first
1200 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1202 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1203 // PHI nodes in successors.
1204 if (SDB->SwitchCases.empty() &&
1205 SDB->JTCases.empty() &&
1206 SDB->BitTestCases.empty()) {
1207 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1208 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1209 assert(PHI->isPHI() &&
1210 "This is not a machine PHI node that we are updating!");
1211 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1213 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1218 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1219 // Lower header first, if it wasn't already lowered
1220 if (!SDB->BitTestCases[i].Emitted) {
1221 // Set the current basic block to the mbb we wish to insert the code into
1222 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1223 FuncInfo->InsertPt = FuncInfo->MBB->end();
1225 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1226 CurDAG->setRoot(SDB->getRoot());
1228 CodeGenAndEmitDAG();
1231 uint32_t UnhandledWeight = 0;
1232 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1233 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1235 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1236 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1237 // Set the current basic block to the mbb we wish to insert the code into
1238 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1239 FuncInfo->InsertPt = FuncInfo->MBB->end();
1242 SDB->visitBitTestCase(SDB->BitTestCases[i],
1243 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1245 SDB->BitTestCases[i].Reg,
1246 SDB->BitTestCases[i].Cases[j],
1249 SDB->visitBitTestCase(SDB->BitTestCases[i],
1250 SDB->BitTestCases[i].Default,
1252 SDB->BitTestCases[i].Reg,
1253 SDB->BitTestCases[i].Cases[j],
1257 CurDAG->setRoot(SDB->getRoot());
1259 CodeGenAndEmitDAG();
1263 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1265 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1266 MachineBasicBlock *PHIBB = PHI->getParent();
1267 assert(PHI->isPHI() &&
1268 "This is not a machine PHI node that we are updating!");
1269 // This is "default" BB. We have two jumps to it. From "header" BB and
1270 // from last "case" BB.
1271 if (PHIBB == SDB->BitTestCases[i].Default)
1272 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1273 .addMBB(SDB->BitTestCases[i].Parent)
1274 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1275 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1276 // One of "cases" BB.
1277 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1279 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1280 if (cBB->isSuccessor(PHIBB))
1281 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1285 SDB->BitTestCases.clear();
1287 // If the JumpTable record is filled in, then we need to emit a jump table.
1288 // Updating the PHI nodes is tricky in this case, since we need to determine
1289 // whether the PHI is a successor of the range check MBB or the jump table MBB
1290 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1291 // Lower header first, if it wasn't already lowered
1292 if (!SDB->JTCases[i].first.Emitted) {
1293 // Set the current basic block to the mbb we wish to insert the code into
1294 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1295 FuncInfo->InsertPt = FuncInfo->MBB->end();
1297 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1299 CurDAG->setRoot(SDB->getRoot());
1301 CodeGenAndEmitDAG();
1304 // Set the current basic block to the mbb we wish to insert the code into
1305 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1306 FuncInfo->InsertPt = FuncInfo->MBB->end();
1308 SDB->visitJumpTable(SDB->JTCases[i].second);
1309 CurDAG->setRoot(SDB->getRoot());
1311 CodeGenAndEmitDAG();
1314 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1316 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1317 MachineBasicBlock *PHIBB = PHI->getParent();
1318 assert(PHI->isPHI() &&
1319 "This is not a machine PHI node that we are updating!");
1320 // "default" BB. We can go there only from header BB.
1321 if (PHIBB == SDB->JTCases[i].second.Default)
1322 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1323 .addMBB(SDB->JTCases[i].first.HeaderBB);
1324 // JT BB. Just iterate over successors here
1325 if (FuncInfo->MBB->isSuccessor(PHIBB))
1326 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1329 SDB->JTCases.clear();
1331 // If the switch block involved a branch to one of the actual successors, we
1332 // need to update PHI nodes in that block.
1333 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1334 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1335 assert(PHI->isPHI() &&
1336 "This is not a machine PHI node that we are updating!");
1337 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1338 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1341 // If we generated any switch lowering information, build and codegen any
1342 // additional DAGs necessary.
1343 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1344 // Set the current basic block to the mbb we wish to insert the code into
1345 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1346 FuncInfo->InsertPt = FuncInfo->MBB->end();
1348 // Determine the unique successors.
1349 SmallVector<MachineBasicBlock *, 2> Succs;
1350 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1351 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1352 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1354 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1355 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1356 CurDAG->setRoot(SDB->getRoot());
1358 CodeGenAndEmitDAG();
1360 // Remember the last block, now that any splitting is done, for use in
1361 // populating PHI nodes in successors.
1362 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1364 // Handle any PHI nodes in successors of this chunk, as if we were coming
1365 // from the original BB before switch expansion. Note that PHI nodes can
1366 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1367 // handle them the right number of times.
1368 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1369 FuncInfo->MBB = Succs[i];
1370 FuncInfo->InsertPt = FuncInfo->MBB->end();
1371 // FuncInfo->MBB may have been removed from the CFG if a branch was
1373 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1374 for (MachineBasicBlock::iterator
1375 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1376 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1377 MachineInstrBuilder PHI(*MF, MBBI);
1378 // This value for this PHI node is recorded in PHINodesToUpdate.
1379 for (unsigned pn = 0; ; ++pn) {
1380 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1381 "Didn't find PHI entry!");
1382 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1383 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1391 SDB->SwitchCases.clear();
1395 /// Create the scheduler. If a specific scheduler was specified
1396 /// via the SchedulerRegistry, use it, otherwise select the
1397 /// one preferred by the target.
1399 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1400 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1404 RegisterScheduler::setDefault(Ctor);
1407 return Ctor(this, OptLevel);
1410 //===----------------------------------------------------------------------===//
1411 // Helper functions used by the generated instruction selector.
1412 //===----------------------------------------------------------------------===//
1413 // Calls to these methods are generated by tblgen.
1415 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1416 /// the dag combiner simplified the 255, we still want to match. RHS is the
1417 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1418 /// specified in the .td file (e.g. 255).
1419 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1420 int64_t DesiredMaskS) const {
1421 const APInt &ActualMask = RHS->getAPIntValue();
1422 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1424 // If the actual mask exactly matches, success!
1425 if (ActualMask == DesiredMask)
1428 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1429 if (ActualMask.intersects(~DesiredMask))
1432 // Otherwise, the DAG Combiner may have proven that the value coming in is
1433 // either already zero or is not demanded. Check for known zero input bits.
1434 APInt NeededMask = DesiredMask & ~ActualMask;
1435 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1438 // TODO: check to see if missing bits are just not demanded.
1440 // Otherwise, this pattern doesn't match.
1444 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1445 /// the dag combiner simplified the 255, we still want to match. RHS is the
1446 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1447 /// specified in the .td file (e.g. 255).
1448 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1449 int64_t DesiredMaskS) const {
1450 const APInt &ActualMask = RHS->getAPIntValue();
1451 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1453 // If the actual mask exactly matches, success!
1454 if (ActualMask == DesiredMask)
1457 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1458 if (ActualMask.intersects(~DesiredMask))
1461 // Otherwise, the DAG Combiner may have proven that the value coming in is
1462 // either already zero or is not demanded. Check for known zero input bits.
1463 APInt NeededMask = DesiredMask & ~ActualMask;
1465 APInt KnownZero, KnownOne;
1466 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1468 // If all the missing bits in the or are already known to be set, match!
1469 if ((NeededMask & KnownOne) == NeededMask)
1472 // TODO: check to see if missing bits are just not demanded.
1474 // Otherwise, this pattern doesn't match.
1479 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1480 /// by tblgen. Others should not call it.
1481 void SelectionDAGISel::
1482 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1483 std::vector<SDValue> InOps;
1484 std::swap(InOps, Ops);
1486 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1487 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1488 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1489 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1491 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1492 if (InOps[e-1].getValueType() == MVT::Glue)
1493 --e; // Don't process a glue operand if it is here.
1496 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1497 if (!InlineAsm::isMemKind(Flags)) {
1498 // Just skip over this operand, copying the operands verbatim.
1499 Ops.insert(Ops.end(), InOps.begin()+i,
1500 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1501 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1503 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1504 "Memory operand with multiple values?");
1505 // Otherwise, this is a memory operand. Ask the target to select it.
1506 std::vector<SDValue> SelOps;
1507 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1508 report_fatal_error("Could not match memory address. Inline asm"
1511 // Add this to the output node.
1513 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1514 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1515 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1520 // Add the glue input back if present.
1521 if (e != InOps.size())
1522 Ops.push_back(InOps.back());
1525 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1528 static SDNode *findGlueUse(SDNode *N) {
1529 unsigned FlagResNo = N->getNumValues()-1;
1530 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1531 SDUse &Use = I.getUse();
1532 if (Use.getResNo() == FlagResNo)
1533 return Use.getUser();
1538 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1539 /// This function recursively traverses up the operand chain, ignoring
1541 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1542 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1543 bool IgnoreChains) {
1544 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1545 // greater than all of its (recursive) operands. If we scan to a point where
1546 // 'use' is smaller than the node we're scanning for, then we know we will
1549 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1550 // happen because we scan down to newly selected nodes in the case of glue
1552 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1555 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1556 // won't fail if we scan it again.
1557 if (!Visited.insert(Use))
1560 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1561 // Ignore chain uses, they are validated by HandleMergeInputChains.
1562 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1565 SDNode *N = Use->getOperand(i).getNode();
1567 if (Use == ImmedUse || Use == Root)
1568 continue; // We are not looking for immediate use.
1573 // Traverse up the operand chain.
1574 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1580 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1581 /// operand node N of U during instruction selection that starts at Root.
1582 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1583 SDNode *Root) const {
1584 if (OptLevel == CodeGenOpt::None) return false;
1585 return N.hasOneUse();
1588 /// IsLegalToFold - Returns true if the specific operand node N of
1589 /// U can be folded during instruction selection that starts at Root.
1590 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1591 CodeGenOpt::Level OptLevel,
1592 bool IgnoreChains) {
1593 if (OptLevel == CodeGenOpt::None) return false;
1595 // If Root use can somehow reach N through a path that that doesn't contain
1596 // U then folding N would create a cycle. e.g. In the following
1597 // diagram, Root can reach N through X. If N is folded into into Root, then
1598 // X is both a predecessor and a successor of U.
1609 // * indicates nodes to be folded together.
1611 // If Root produces glue, then it gets (even more) interesting. Since it
1612 // will be "glued" together with its glue use in the scheduler, we need to
1613 // check if it might reach N.
1632 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1633 // (call it Fold), then X is a predecessor of GU and a successor of
1634 // Fold. But since Fold and GU are glued together, this will create
1635 // a cycle in the scheduling graph.
1637 // If the node has glue, walk down the graph to the "lowest" node in the
1639 EVT VT = Root->getValueType(Root->getNumValues()-1);
1640 while (VT == MVT::Glue) {
1641 SDNode *GU = findGlueUse(Root);
1645 VT = Root->getValueType(Root->getNumValues()-1);
1647 // If our query node has a glue result with a use, we've walked up it. If
1648 // the user (which has already been selected) has a chain or indirectly uses
1649 // the chain, our WalkChainUsers predicate will not consider it. Because of
1650 // this, we cannot ignore chains in this predicate.
1651 IgnoreChains = false;
1655 SmallPtrSet<SDNode*, 16> Visited;
1656 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1659 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1660 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1661 SelectInlineAsmMemoryOperands(Ops);
1663 std::vector<EVT> VTs;
1664 VTs.push_back(MVT::Other);
1665 VTs.push_back(MVT::Glue);
1666 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1667 VTs, &Ops[0], Ops.size());
1669 return New.getNode();
1672 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1673 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1676 /// GetVBR - decode a vbr encoding whose top bit is set.
1677 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1678 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1679 assert(Val >= 128 && "Not a VBR");
1680 Val &= 127; // Remove first vbr bit.
1685 NextBits = MatcherTable[Idx++];
1686 Val |= (NextBits&127) << Shift;
1688 } while (NextBits & 128);
1694 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1695 /// interior glue and chain results to use the new glue and chain results.
1696 void SelectionDAGISel::
1697 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1698 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1700 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1701 bool isMorphNodeTo) {
1702 SmallVector<SDNode*, 4> NowDeadNodes;
1704 // Now that all the normal results are replaced, we replace the chain and
1705 // glue results if present.
1706 if (!ChainNodesMatched.empty()) {
1707 assert(InputChain.getNode() != 0 &&
1708 "Matched input chains but didn't produce a chain");
1709 // Loop over all of the nodes we matched that produced a chain result.
1710 // Replace all the chain results with the final chain we ended up with.
1711 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1712 SDNode *ChainNode = ChainNodesMatched[i];
1714 // If this node was already deleted, don't look at it.
1715 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1718 // Don't replace the results of the root node if we're doing a
1720 if (ChainNode == NodeToMatch && isMorphNodeTo)
1723 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1724 if (ChainVal.getValueType() == MVT::Glue)
1725 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1726 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1727 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1729 // If the node became dead and we haven't already seen it, delete it.
1730 if (ChainNode->use_empty() &&
1731 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1732 NowDeadNodes.push_back(ChainNode);
1736 // If the result produces glue, update any glue results in the matched
1737 // pattern with the glue result.
1738 if (InputGlue.getNode() != 0) {
1739 // Handle any interior nodes explicitly marked.
1740 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1741 SDNode *FRN = GlueResultNodesMatched[i];
1743 // If this node was already deleted, don't look at it.
1744 if (FRN->getOpcode() == ISD::DELETED_NODE)
1747 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1748 "Doesn't have a glue result");
1749 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1752 // If the node became dead and we haven't already seen it, delete it.
1753 if (FRN->use_empty() &&
1754 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1755 NowDeadNodes.push_back(FRN);
1759 if (!NowDeadNodes.empty())
1760 CurDAG->RemoveDeadNodes(NowDeadNodes);
1762 DEBUG(errs() << "ISEL: Match complete!\n");
1768 CR_LeadsToInteriorNode
1771 /// WalkChainUsers - Walk down the users of the specified chained node that is
1772 /// part of the pattern we're matching, looking at all of the users we find.
1773 /// This determines whether something is an interior node, whether we have a
1774 /// non-pattern node in between two pattern nodes (which prevent folding because
1775 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1776 /// between pattern nodes (in which case the TF becomes part of the pattern).
1778 /// The walk we do here is guaranteed to be small because we quickly get down to
1779 /// already selected nodes "below" us.
1781 WalkChainUsers(const SDNode *ChainedNode,
1782 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1783 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1784 ChainResult Result = CR_Simple;
1786 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1787 E = ChainedNode->use_end(); UI != E; ++UI) {
1788 // Make sure the use is of the chain, not some other value we produce.
1789 if (UI.getUse().getValueType() != MVT::Other) continue;
1793 // If we see an already-selected machine node, then we've gone beyond the
1794 // pattern that we're selecting down into the already selected chunk of the
1796 if (User->isMachineOpcode() ||
1797 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1800 unsigned UserOpcode = User->getOpcode();
1801 if (UserOpcode == ISD::CopyToReg ||
1802 UserOpcode == ISD::CopyFromReg ||
1803 UserOpcode == ISD::INLINEASM ||
1804 UserOpcode == ISD::EH_LABEL ||
1805 UserOpcode == ISD::LIFETIME_START ||
1806 UserOpcode == ISD::LIFETIME_END) {
1807 // If their node ID got reset to -1 then they've already been selected.
1808 // Treat them like a MachineOpcode.
1809 if (User->getNodeId() == -1)
1813 // If we have a TokenFactor, we handle it specially.
1814 if (User->getOpcode() != ISD::TokenFactor) {
1815 // If the node isn't a token factor and isn't part of our pattern, then it
1816 // must be a random chained node in between two nodes we're selecting.
1817 // This happens when we have something like:
1822 // Because we structurally match the load/store as a read/modify/write,
1823 // but the call is chained between them. We cannot fold in this case
1824 // because it would induce a cycle in the graph.
1825 if (!std::count(ChainedNodesInPattern.begin(),
1826 ChainedNodesInPattern.end(), User))
1827 return CR_InducesCycle;
1829 // Otherwise we found a node that is part of our pattern. For example in:
1833 // This would happen when we're scanning down from the load and see the
1834 // store as a user. Record that there is a use of ChainedNode that is
1835 // part of the pattern and keep scanning uses.
1836 Result = CR_LeadsToInteriorNode;
1837 InteriorChainedNodes.push_back(User);
1841 // If we found a TokenFactor, there are two cases to consider: first if the
1842 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1843 // uses of the TF are in our pattern) we just want to ignore it. Second,
1844 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1850 // | \ DAG's like cheese
1853 // [TokenFactor] [Op]
1860 // In this case, the TokenFactor becomes part of our match and we rewrite it
1861 // as a new TokenFactor.
1863 // To distinguish these two cases, do a recursive walk down the uses.
1864 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1866 // If the uses of the TokenFactor are just already-selected nodes, ignore
1867 // it, it is "below" our pattern.
1869 case CR_InducesCycle:
1870 // If the uses of the TokenFactor lead to nodes that are not part of our
1871 // pattern that are not selected, folding would turn this into a cycle,
1873 return CR_InducesCycle;
1874 case CR_LeadsToInteriorNode:
1875 break; // Otherwise, keep processing.
1878 // Okay, we know we're in the interesting interior case. The TokenFactor
1879 // is now going to be considered part of the pattern so that we rewrite its
1880 // uses (it may have uses that are not part of the pattern) with the
1881 // ultimate chain result of the generated code. We will also add its chain
1882 // inputs as inputs to the ultimate TokenFactor we create.
1883 Result = CR_LeadsToInteriorNode;
1884 ChainedNodesInPattern.push_back(User);
1885 InteriorChainedNodes.push_back(User);
1892 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1893 /// operation for when the pattern matched at least one node with a chains. The
1894 /// input vector contains a list of all of the chained nodes that we match. We
1895 /// must determine if this is a valid thing to cover (i.e. matching it won't
1896 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1897 /// be used as the input node chain for the generated nodes.
1899 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1900 SelectionDAG *CurDAG) {
1901 // Walk all of the chained nodes we've matched, recursively scanning down the
1902 // users of the chain result. This adds any TokenFactor nodes that are caught
1903 // in between chained nodes to the chained and interior nodes list.
1904 SmallVector<SDNode*, 3> InteriorChainedNodes;
1905 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1906 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1907 InteriorChainedNodes) == CR_InducesCycle)
1908 return SDValue(); // Would induce a cycle.
1911 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1912 // that we are interested in. Form our input TokenFactor node.
1913 SmallVector<SDValue, 3> InputChains;
1914 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1915 // Add the input chain of this node to the InputChains list (which will be
1916 // the operands of the generated TokenFactor) if it's not an interior node.
1917 SDNode *N = ChainNodesMatched[i];
1918 if (N->getOpcode() != ISD::TokenFactor) {
1919 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1922 // Otherwise, add the input chain.
1923 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1924 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1925 InputChains.push_back(InChain);
1929 // If we have a token factor, we want to add all inputs of the token factor
1930 // that are not part of the pattern we're matching.
1931 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1932 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1933 N->getOperand(op).getNode()))
1934 InputChains.push_back(N->getOperand(op));
1939 if (InputChains.size() == 1)
1940 return InputChains[0];
1941 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1942 MVT::Other, &InputChains[0], InputChains.size());
1945 /// MorphNode - Handle morphing a node in place for the selector.
1946 SDNode *SelectionDAGISel::
1947 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1948 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1949 // It is possible we're using MorphNodeTo to replace a node with no
1950 // normal results with one that has a normal result (or we could be
1951 // adding a chain) and the input could have glue and chains as well.
1952 // In this case we need to shift the operands down.
1953 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1954 // than the old isel though.
1955 int OldGlueResultNo = -1, OldChainResultNo = -1;
1957 unsigned NTMNumResults = Node->getNumValues();
1958 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1959 OldGlueResultNo = NTMNumResults-1;
1960 if (NTMNumResults != 1 &&
1961 Node->getValueType(NTMNumResults-2) == MVT::Other)
1962 OldChainResultNo = NTMNumResults-2;
1963 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1964 OldChainResultNo = NTMNumResults-1;
1966 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1967 // that this deletes operands of the old node that become dead.
1968 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1970 // MorphNodeTo can operate in two ways: if an existing node with the
1971 // specified operands exists, it can just return it. Otherwise, it
1972 // updates the node in place to have the requested operands.
1974 // If we updated the node in place, reset the node ID. To the isel,
1975 // this should be just like a newly allocated machine node.
1979 unsigned ResNumResults = Res->getNumValues();
1980 // Move the glue if needed.
1981 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1982 (unsigned)OldGlueResultNo != ResNumResults-1)
1983 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1984 SDValue(Res, ResNumResults-1));
1986 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1989 // Move the chain reference if needed.
1990 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1991 (unsigned)OldChainResultNo != ResNumResults-1)
1992 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1993 SDValue(Res, ResNumResults-1));
1995 // Otherwise, no replacement happened because the node already exists. Replace
1996 // Uses of the old node with the new one.
1998 CurDAG->ReplaceAllUsesWith(Node, Res);
2003 /// CheckSame - Implements OP_CheckSame.
2004 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2005 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2007 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2008 // Accept if it is exactly the same as a previously recorded node.
2009 unsigned RecNo = MatcherTable[MatcherIndex++];
2010 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2011 return N == RecordedNodes[RecNo].first;
2014 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2015 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2016 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2017 const SelectionDAGISel &SDISel) {
2018 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2021 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2022 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2023 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2024 const SelectionDAGISel &SDISel, SDNode *N) {
2025 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2028 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2029 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2031 uint16_t Opc = MatcherTable[MatcherIndex++];
2032 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2033 return N->getOpcode() == Opc;
2036 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2037 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2038 SDValue N, const TargetLowering &TLI) {
2039 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2040 if (N.getValueType() == VT) return true;
2042 // Handle the case when VT is iPTR.
2043 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2046 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2047 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2048 SDValue N, const TargetLowering &TLI,
2050 if (ChildNo >= N.getNumOperands())
2051 return false; // Match fails if out of range child #.
2052 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2056 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2057 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2059 return cast<CondCodeSDNode>(N)->get() ==
2060 (ISD::CondCode)MatcherTable[MatcherIndex++];
2063 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2064 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2065 SDValue N, const TargetLowering &TLI) {
2066 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2067 if (cast<VTSDNode>(N)->getVT() == VT)
2070 // Handle the case when VT is iPTR.
2071 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2074 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2075 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2077 int64_t Val = MatcherTable[MatcherIndex++];
2079 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2081 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2082 return C != 0 && C->getSExtValue() == Val;
2085 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2086 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2087 SDValue N, const SelectionDAGISel &SDISel) {
2088 int64_t Val = MatcherTable[MatcherIndex++];
2090 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2092 if (N->getOpcode() != ISD::AND) return false;
2094 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2095 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2098 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2099 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2100 SDValue N, const SelectionDAGISel &SDISel) {
2101 int64_t Val = MatcherTable[MatcherIndex++];
2103 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2105 if (N->getOpcode() != ISD::OR) return false;
2107 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2108 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2111 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2112 /// scope, evaluate the current node. If the current predicate is known to
2113 /// fail, set Result=true and return anything. If the current predicate is
2114 /// known to pass, set Result=false and return the MatcherIndex to continue
2115 /// with. If the current predicate is unknown, set Result=false and return the
2116 /// MatcherIndex to continue with.
2117 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2118 unsigned Index, SDValue N,
2120 const SelectionDAGISel &SDISel,
2121 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2122 switch (Table[Index++]) {
2125 return Index-1; // Could not evaluate this predicate.
2126 case SelectionDAGISel::OPC_CheckSame:
2127 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2129 case SelectionDAGISel::OPC_CheckPatternPredicate:
2130 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2132 case SelectionDAGISel::OPC_CheckPredicate:
2133 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2135 case SelectionDAGISel::OPC_CheckOpcode:
2136 Result = !::CheckOpcode(Table, Index, N.getNode());
2138 case SelectionDAGISel::OPC_CheckType:
2139 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2141 case SelectionDAGISel::OPC_CheckChild0Type:
2142 case SelectionDAGISel::OPC_CheckChild1Type:
2143 case SelectionDAGISel::OPC_CheckChild2Type:
2144 case SelectionDAGISel::OPC_CheckChild3Type:
2145 case SelectionDAGISel::OPC_CheckChild4Type:
2146 case SelectionDAGISel::OPC_CheckChild5Type:
2147 case SelectionDAGISel::OPC_CheckChild6Type:
2148 case SelectionDAGISel::OPC_CheckChild7Type:
2149 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2150 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2152 case SelectionDAGISel::OPC_CheckCondCode:
2153 Result = !::CheckCondCode(Table, Index, N);
2155 case SelectionDAGISel::OPC_CheckValueType:
2156 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2158 case SelectionDAGISel::OPC_CheckInteger:
2159 Result = !::CheckInteger(Table, Index, N);
2161 case SelectionDAGISel::OPC_CheckAndImm:
2162 Result = !::CheckAndImm(Table, Index, N, SDISel);
2164 case SelectionDAGISel::OPC_CheckOrImm:
2165 Result = !::CheckOrImm(Table, Index, N, SDISel);
2173 /// FailIndex - If this match fails, this is the index to continue with.
2176 /// NodeStack - The node stack when the scope was formed.
2177 SmallVector<SDValue, 4> NodeStack;
2179 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2180 unsigned NumRecordedNodes;
2182 /// NumMatchedMemRefs - The number of matched memref entries.
2183 unsigned NumMatchedMemRefs;
2185 /// InputChain/InputGlue - The current chain/glue
2186 SDValue InputChain, InputGlue;
2188 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2189 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2194 SDNode *SelectionDAGISel::
2195 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2196 unsigned TableSize) {
2197 // FIXME: Should these even be selected? Handle these cases in the caller?
2198 switch (NodeToMatch->getOpcode()) {
2201 case ISD::EntryToken: // These nodes remain the same.
2202 case ISD::BasicBlock:
2204 case ISD::RegisterMask:
2205 //case ISD::VALUETYPE:
2206 //case ISD::CONDCODE:
2207 case ISD::HANDLENODE:
2208 case ISD::MDNODE_SDNODE:
2209 case ISD::TargetConstant:
2210 case ISD::TargetConstantFP:
2211 case ISD::TargetConstantPool:
2212 case ISD::TargetFrameIndex:
2213 case ISD::TargetExternalSymbol:
2214 case ISD::TargetBlockAddress:
2215 case ISD::TargetJumpTable:
2216 case ISD::TargetGlobalTLSAddress:
2217 case ISD::TargetGlobalAddress:
2218 case ISD::TokenFactor:
2219 case ISD::CopyFromReg:
2220 case ISD::CopyToReg:
2222 case ISD::LIFETIME_START:
2223 case ISD::LIFETIME_END:
2224 NodeToMatch->setNodeId(-1); // Mark selected.
2226 case ISD::AssertSext:
2227 case ISD::AssertZext:
2228 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2229 NodeToMatch->getOperand(0));
2231 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2232 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2235 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2237 // Set up the node stack with NodeToMatch as the only node on the stack.
2238 SmallVector<SDValue, 8> NodeStack;
2239 SDValue N = SDValue(NodeToMatch, 0);
2240 NodeStack.push_back(N);
2242 // MatchScopes - Scopes used when matching, if a match failure happens, this
2243 // indicates where to continue checking.
2244 SmallVector<MatchScope, 8> MatchScopes;
2246 // RecordedNodes - This is the set of nodes that have been recorded by the
2247 // state machine. The second value is the parent of the node, or null if the
2248 // root is recorded.
2249 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2251 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2253 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2255 // These are the current input chain and glue for use when generating nodes.
2256 // Various Emit operations change these. For example, emitting a copytoreg
2257 // uses and updates these.
2258 SDValue InputChain, InputGlue;
2260 // ChainNodesMatched - If a pattern matches nodes that have input/output
2261 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2262 // which ones they are. The result is captured into this list so that we can
2263 // update the chain results when the pattern is complete.
2264 SmallVector<SDNode*, 3> ChainNodesMatched;
2265 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2267 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2268 NodeToMatch->dump(CurDAG);
2271 // Determine where to start the interpreter. Normally we start at opcode #0,
2272 // but if the state machine starts with an OPC_SwitchOpcode, then we
2273 // accelerate the first lookup (which is guaranteed to be hot) with the
2274 // OpcodeOffset table.
2275 unsigned MatcherIndex = 0;
2277 if (!OpcodeOffset.empty()) {
2278 // Already computed the OpcodeOffset table, just index into it.
2279 if (N.getOpcode() < OpcodeOffset.size())
2280 MatcherIndex = OpcodeOffset[N.getOpcode()];
2281 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2283 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2284 // Otherwise, the table isn't computed, but the state machine does start
2285 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2286 // is the first time we're selecting an instruction.
2289 // Get the size of this case.
2290 unsigned CaseSize = MatcherTable[Idx++];
2292 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2293 if (CaseSize == 0) break;
2295 // Get the opcode, add the index to the table.
2296 uint16_t Opc = MatcherTable[Idx++];
2297 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2298 if (Opc >= OpcodeOffset.size())
2299 OpcodeOffset.resize((Opc+1)*2);
2300 OpcodeOffset[Opc] = Idx;
2304 // Okay, do the lookup for the first opcode.
2305 if (N.getOpcode() < OpcodeOffset.size())
2306 MatcherIndex = OpcodeOffset[N.getOpcode()];
2310 assert(MatcherIndex < TableSize && "Invalid index");
2312 unsigned CurrentOpcodeIndex = MatcherIndex;
2314 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2317 // Okay, the semantics of this operation are that we should push a scope
2318 // then evaluate the first child. However, pushing a scope only to have
2319 // the first check fail (which then pops it) is inefficient. If we can
2320 // determine immediately that the first check (or first several) will
2321 // immediately fail, don't even bother pushing a scope for them.
2325 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2326 if (NumToSkip & 128)
2327 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2328 // Found the end of the scope with no match.
2329 if (NumToSkip == 0) {
2334 FailIndex = MatcherIndex+NumToSkip;
2336 unsigned MatcherIndexOfPredicate = MatcherIndex;
2337 (void)MatcherIndexOfPredicate; // silence warning.
2339 // If we can't evaluate this predicate without pushing a scope (e.g. if
2340 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2341 // push the scope and evaluate the full predicate chain.
2343 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2344 Result, *this, RecordedNodes);
2348 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2349 << "index " << MatcherIndexOfPredicate
2350 << ", continuing at " << FailIndex << "\n");
2351 ++NumDAGIselRetries;
2353 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2354 // move to the next case.
2355 MatcherIndex = FailIndex;
2358 // If the whole scope failed to match, bail.
2359 if (FailIndex == 0) break;
2361 // Push a MatchScope which indicates where to go if the first child fails
2363 MatchScope NewEntry;
2364 NewEntry.FailIndex = FailIndex;
2365 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2366 NewEntry.NumRecordedNodes = RecordedNodes.size();
2367 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2368 NewEntry.InputChain = InputChain;
2369 NewEntry.InputGlue = InputGlue;
2370 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2371 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2372 MatchScopes.push_back(NewEntry);
2375 case OPC_RecordNode: {
2376 // Remember this node, it may end up being an operand in the pattern.
2378 if (NodeStack.size() > 1)
2379 Parent = NodeStack[NodeStack.size()-2].getNode();
2380 RecordedNodes.push_back(std::make_pair(N, Parent));
2384 case OPC_RecordChild0: case OPC_RecordChild1:
2385 case OPC_RecordChild2: case OPC_RecordChild3:
2386 case OPC_RecordChild4: case OPC_RecordChild5:
2387 case OPC_RecordChild6: case OPC_RecordChild7: {
2388 unsigned ChildNo = Opcode-OPC_RecordChild0;
2389 if (ChildNo >= N.getNumOperands())
2390 break; // Match fails if out of range child #.
2392 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2396 case OPC_RecordMemRef:
2397 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2400 case OPC_CaptureGlueInput:
2401 // If the current node has an input glue, capture it in InputGlue.
2402 if (N->getNumOperands() != 0 &&
2403 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2404 InputGlue = N->getOperand(N->getNumOperands()-1);
2407 case OPC_MoveChild: {
2408 unsigned ChildNo = MatcherTable[MatcherIndex++];
2409 if (ChildNo >= N.getNumOperands())
2410 break; // Match fails if out of range child #.
2411 N = N.getOperand(ChildNo);
2412 NodeStack.push_back(N);
2416 case OPC_MoveParent:
2417 // Pop the current node off the NodeStack.
2418 NodeStack.pop_back();
2419 assert(!NodeStack.empty() && "Node stack imbalance!");
2420 N = NodeStack.back();
2424 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2426 case OPC_CheckPatternPredicate:
2427 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2429 case OPC_CheckPredicate:
2430 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2434 case OPC_CheckComplexPat: {
2435 unsigned CPNum = MatcherTable[MatcherIndex++];
2436 unsigned RecNo = MatcherTable[MatcherIndex++];
2437 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2438 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2439 RecordedNodes[RecNo].first, CPNum,
2444 case OPC_CheckOpcode:
2445 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2449 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2452 case OPC_SwitchOpcode: {
2453 unsigned CurNodeOpcode = N.getOpcode();
2454 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2457 // Get the size of this case.
2458 CaseSize = MatcherTable[MatcherIndex++];
2460 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2461 if (CaseSize == 0) break;
2463 uint16_t Opc = MatcherTable[MatcherIndex++];
2464 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2466 // If the opcode matches, then we will execute this case.
2467 if (CurNodeOpcode == Opc)
2470 // Otherwise, skip over this case.
2471 MatcherIndex += CaseSize;
2474 // If no cases matched, bail out.
2475 if (CaseSize == 0) break;
2477 // Otherwise, execute the case we found.
2478 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2479 << " to " << MatcherIndex << "\n");
2483 case OPC_SwitchType: {
2484 MVT CurNodeVT = N.getValueType().getSimpleVT();
2485 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2488 // Get the size of this case.
2489 CaseSize = MatcherTable[MatcherIndex++];
2491 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2492 if (CaseSize == 0) break;
2494 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2495 if (CaseVT == MVT::iPTR)
2496 CaseVT = TLI.getPointerTy();
2498 // If the VT matches, then we will execute this case.
2499 if (CurNodeVT == CaseVT)
2502 // Otherwise, skip over this case.
2503 MatcherIndex += CaseSize;
2506 // If no cases matched, bail out.
2507 if (CaseSize == 0) break;
2509 // Otherwise, execute the case we found.
2510 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2511 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2514 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2515 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2516 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2517 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2518 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2519 Opcode-OPC_CheckChild0Type))
2522 case OPC_CheckCondCode:
2523 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2525 case OPC_CheckValueType:
2526 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2528 case OPC_CheckInteger:
2529 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2531 case OPC_CheckAndImm:
2532 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2534 case OPC_CheckOrImm:
2535 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2538 case OPC_CheckFoldableChainNode: {
2539 assert(NodeStack.size() != 1 && "No parent node");
2540 // Verify that all intermediate nodes between the root and this one have
2542 bool HasMultipleUses = false;
2543 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2544 if (!NodeStack[i].hasOneUse()) {
2545 HasMultipleUses = true;
2548 if (HasMultipleUses) break;
2550 // Check to see that the target thinks this is profitable to fold and that
2551 // we can fold it without inducing cycles in the graph.
2552 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2554 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2555 NodeToMatch, OptLevel,
2556 true/*We validate our own chains*/))
2561 case OPC_EmitInteger: {
2562 MVT::SimpleValueType VT =
2563 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2564 int64_t Val = MatcherTable[MatcherIndex++];
2566 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2567 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2568 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2571 case OPC_EmitRegister: {
2572 MVT::SimpleValueType VT =
2573 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2574 unsigned RegNo = MatcherTable[MatcherIndex++];
2575 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2576 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2579 case OPC_EmitRegister2: {
2580 // For targets w/ more than 256 register names, the register enum
2581 // values are stored in two bytes in the matcher table (just like
2583 MVT::SimpleValueType VT =
2584 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2585 unsigned RegNo = MatcherTable[MatcherIndex++];
2586 RegNo |= MatcherTable[MatcherIndex++] << 8;
2587 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2588 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2592 case OPC_EmitConvertToTarget: {
2593 // Convert from IMM/FPIMM to target version.
2594 unsigned RecNo = MatcherTable[MatcherIndex++];
2595 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2596 SDValue Imm = RecordedNodes[RecNo].first;
2598 if (Imm->getOpcode() == ISD::Constant) {
2599 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2600 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2601 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2602 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2603 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2606 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2610 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2611 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2612 // These are space-optimized forms of OPC_EmitMergeInputChains.
2613 assert(InputChain.getNode() == 0 &&
2614 "EmitMergeInputChains should be the first chain producing node");
2615 assert(ChainNodesMatched.empty() &&
2616 "Should only have one EmitMergeInputChains per match");
2618 // Read all of the chained nodes.
2619 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2620 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2621 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2623 // FIXME: What if other value results of the node have uses not matched
2625 if (ChainNodesMatched.back() != NodeToMatch &&
2626 !RecordedNodes[RecNo].first.hasOneUse()) {
2627 ChainNodesMatched.clear();
2631 // Merge the input chains if they are not intra-pattern references.
2632 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2634 if (InputChain.getNode() == 0)
2635 break; // Failed to merge.
2639 case OPC_EmitMergeInputChains: {
2640 assert(InputChain.getNode() == 0 &&
2641 "EmitMergeInputChains should be the first chain producing node");
2642 // This node gets a list of nodes we matched in the input that have
2643 // chains. We want to token factor all of the input chains to these nodes
2644 // together. However, if any of the input chains is actually one of the
2645 // nodes matched in this pattern, then we have an intra-match reference.
2646 // Ignore these because the newly token factored chain should not refer to
2648 unsigned NumChains = MatcherTable[MatcherIndex++];
2649 assert(NumChains != 0 && "Can't TF zero chains");
2651 assert(ChainNodesMatched.empty() &&
2652 "Should only have one EmitMergeInputChains per match");
2654 // Read all of the chained nodes.
2655 for (unsigned i = 0; i != NumChains; ++i) {
2656 unsigned RecNo = MatcherTable[MatcherIndex++];
2657 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2658 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2660 // FIXME: What if other value results of the node have uses not matched
2662 if (ChainNodesMatched.back() != NodeToMatch &&
2663 !RecordedNodes[RecNo].first.hasOneUse()) {
2664 ChainNodesMatched.clear();
2669 // If the inner loop broke out, the match fails.
2670 if (ChainNodesMatched.empty())
2673 // Merge the input chains if they are not intra-pattern references.
2674 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2676 if (InputChain.getNode() == 0)
2677 break; // Failed to merge.
2682 case OPC_EmitCopyToReg: {
2683 unsigned RecNo = MatcherTable[MatcherIndex++];
2684 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2685 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2687 if (InputChain.getNode() == 0)
2688 InputChain = CurDAG->getEntryNode();
2690 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2691 DestPhysReg, RecordedNodes[RecNo].first,
2694 InputGlue = InputChain.getValue(1);
2698 case OPC_EmitNodeXForm: {
2699 unsigned XFormNo = MatcherTable[MatcherIndex++];
2700 unsigned RecNo = MatcherTable[MatcherIndex++];
2701 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2702 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2703 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2708 case OPC_MorphNodeTo: {
2709 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2710 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2711 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2712 // Get the result VT list.
2713 unsigned NumVTs = MatcherTable[MatcherIndex++];
2714 SmallVector<EVT, 4> VTs;
2715 for (unsigned i = 0; i != NumVTs; ++i) {
2716 MVT::SimpleValueType VT =
2717 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2718 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2722 if (EmitNodeInfo & OPFL_Chain)
2723 VTs.push_back(MVT::Other);
2724 if (EmitNodeInfo & OPFL_GlueOutput)
2725 VTs.push_back(MVT::Glue);
2727 // This is hot code, so optimize the two most common cases of 1 and 2
2730 if (VTs.size() == 1)
2731 VTList = CurDAG->getVTList(VTs[0]);
2732 else if (VTs.size() == 2)
2733 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2735 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2737 // Get the operand list.
2738 unsigned NumOps = MatcherTable[MatcherIndex++];
2739 SmallVector<SDValue, 8> Ops;
2740 for (unsigned i = 0; i != NumOps; ++i) {
2741 unsigned RecNo = MatcherTable[MatcherIndex++];
2743 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2745 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2746 Ops.push_back(RecordedNodes[RecNo].first);
2749 // If there are variadic operands to add, handle them now.
2750 if (EmitNodeInfo & OPFL_VariadicInfo) {
2751 // Determine the start index to copy from.
2752 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2753 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2754 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2755 "Invalid variadic node");
2756 // Copy all of the variadic operands, not including a potential glue
2758 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2760 SDValue V = NodeToMatch->getOperand(i);
2761 if (V.getValueType() == MVT::Glue) break;
2766 // If this has chain/glue inputs, add them.
2767 if (EmitNodeInfo & OPFL_Chain)
2768 Ops.push_back(InputChain);
2769 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2770 Ops.push_back(InputGlue);
2774 if (Opcode != OPC_MorphNodeTo) {
2775 // If this is a normal EmitNode command, just create the new node and
2776 // add the results to the RecordedNodes list.
2777 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2778 VTList, Ops.data(), Ops.size());
2780 // Add all the non-glue/non-chain results to the RecordedNodes list.
2781 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2782 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2783 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2787 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2788 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2791 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2792 // We will visit the equivalent node later.
2793 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2797 // If the node had chain/glue results, update our notion of the current
2799 if (EmitNodeInfo & OPFL_GlueOutput) {
2800 InputGlue = SDValue(Res, VTs.size()-1);
2801 if (EmitNodeInfo & OPFL_Chain)
2802 InputChain = SDValue(Res, VTs.size()-2);
2803 } else if (EmitNodeInfo & OPFL_Chain)
2804 InputChain = SDValue(Res, VTs.size()-1);
2806 // If the OPFL_MemRefs glue is set on this node, slap all of the
2807 // accumulated memrefs onto it.
2809 // FIXME: This is vastly incorrect for patterns with multiple outputs
2810 // instructions that access memory and for ComplexPatterns that match
2812 if (EmitNodeInfo & OPFL_MemRefs) {
2813 // Only attach load or store memory operands if the generated
2814 // instruction may load or store.
2815 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2816 bool mayLoad = MCID.mayLoad();
2817 bool mayStore = MCID.mayStore();
2819 unsigned NumMemRefs = 0;
2820 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2821 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2822 if ((*I)->isLoad()) {
2825 } else if ((*I)->isStore()) {
2833 MachineSDNode::mmo_iterator MemRefs =
2834 MF->allocateMemRefsArray(NumMemRefs);
2836 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2837 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2838 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2839 if ((*I)->isLoad()) {
2842 } else if ((*I)->isStore()) {
2850 cast<MachineSDNode>(Res)
2851 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2855 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2856 << " node: "; Res->dump(CurDAG); errs() << "\n");
2858 // If this was a MorphNodeTo then we're completely done!
2859 if (Opcode == OPC_MorphNodeTo) {
2860 // Update chain and glue uses.
2861 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2862 InputGlue, GlueResultNodesMatched, true);
2869 case OPC_MarkGlueResults: {
2870 unsigned NumNodes = MatcherTable[MatcherIndex++];
2872 // Read and remember all the glue-result nodes.
2873 for (unsigned i = 0; i != NumNodes; ++i) {
2874 unsigned RecNo = MatcherTable[MatcherIndex++];
2876 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2878 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2879 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2884 case OPC_CompleteMatch: {
2885 // The match has been completed, and any new nodes (if any) have been
2886 // created. Patch up references to the matched dag to use the newly
2888 unsigned NumResults = MatcherTable[MatcherIndex++];
2890 for (unsigned i = 0; i != NumResults; ++i) {
2891 unsigned ResSlot = MatcherTable[MatcherIndex++];
2893 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2895 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2896 SDValue Res = RecordedNodes[ResSlot].first;
2898 assert(i < NodeToMatch->getNumValues() &&
2899 NodeToMatch->getValueType(i) != MVT::Other &&
2900 NodeToMatch->getValueType(i) != MVT::Glue &&
2901 "Invalid number of results to complete!");
2902 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2903 NodeToMatch->getValueType(i) == MVT::iPTR ||
2904 Res.getValueType() == MVT::iPTR ||
2905 NodeToMatch->getValueType(i).getSizeInBits() ==
2906 Res.getValueType().getSizeInBits()) &&
2907 "invalid replacement");
2908 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2911 // If the root node defines glue, add it to the glue nodes to update list.
2912 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2913 GlueResultNodesMatched.push_back(NodeToMatch);
2915 // Update chain and glue uses.
2916 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2917 InputGlue, GlueResultNodesMatched, false);
2919 assert(NodeToMatch->use_empty() &&
2920 "Didn't replace all uses of the node?");
2922 // FIXME: We just return here, which interacts correctly with SelectRoot
2923 // above. We should fix this to not return an SDNode* anymore.
2928 // If the code reached this point, then the match failed. See if there is
2929 // another child to try in the current 'Scope', otherwise pop it until we
2930 // find a case to check.
2931 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2932 ++NumDAGIselRetries;
2934 if (MatchScopes.empty()) {
2935 CannotYetSelect(NodeToMatch);
2939 // Restore the interpreter state back to the point where the scope was
2941 MatchScope &LastScope = MatchScopes.back();
2942 RecordedNodes.resize(LastScope.NumRecordedNodes);
2944 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2945 N = NodeStack.back();
2947 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2948 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2949 MatcherIndex = LastScope.FailIndex;
2951 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2953 InputChain = LastScope.InputChain;
2954 InputGlue = LastScope.InputGlue;
2955 if (!LastScope.HasChainNodesMatched)
2956 ChainNodesMatched.clear();
2957 if (!LastScope.HasGlueResultNodesMatched)
2958 GlueResultNodesMatched.clear();
2960 // Check to see what the offset is at the new MatcherIndex. If it is zero
2961 // we have reached the end of this scope, otherwise we have another child
2962 // in the current scope to try.
2963 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2964 if (NumToSkip & 128)
2965 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2967 // If we have another child in this scope to match, update FailIndex and
2969 if (NumToSkip != 0) {
2970 LastScope.FailIndex = MatcherIndex+NumToSkip;
2974 // End of this scope, pop it and try the next child in the containing
2976 MatchScopes.pop_back();
2983 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2985 raw_string_ostream Msg(msg);
2986 Msg << "Cannot select: ";
2988 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2989 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2990 N->getOpcode() != ISD::INTRINSIC_VOID) {
2991 N->printrFull(Msg, CurDAG);
2992 Msg << "\nIn function: " << MF->getName();
2994 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2996 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2997 if (iid < Intrinsic::num_intrinsics)
2998 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2999 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3000 Msg << "target intrinsic %" << TII->getName(iid);
3002 Msg << "unknown intrinsic #" << iid;
3004 report_fatal_error(Msg.str());
3007 char SelectionDAGISel::ID = 0;