1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/CFG.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/DebugInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/LLVMContext.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLibraryInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
64 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
65 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
66 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
68 STATISTIC(NumFastIselFailLowerArguments,
69 "Number of entry blocks where fast isel failed to lower arguments");
73 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
74 cl::desc("Enable extra verbose messages in the \"fast\" "
75 "instruction selector"));
78 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
79 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
80 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
81 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
82 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
83 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
84 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
86 // Standard binary operators...
87 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
88 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
89 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
90 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
91 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
92 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
93 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
94 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
95 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
96 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
97 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
98 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
100 // Logical operators...
101 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
102 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
103 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
105 // Memory instructions...
106 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
107 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
108 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
109 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
110 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
111 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
112 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
114 // Convert instructions...
115 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
116 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
117 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
118 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
119 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
120 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
121 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
122 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
123 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
124 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
125 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
126 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
128 // Other instructions...
129 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
130 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
131 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
132 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
133 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
134 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
135 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
136 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
137 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
138 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
139 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
140 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
141 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
142 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
143 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
148 cl::desc("Enable verbose messages in the \"fast\" "
149 "instruction selector"));
151 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
152 cl::desc("Enable abort calls when \"fast\" instruction selection "
153 "fails to lower an instruction"));
155 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
156 cl::desc("Enable abort calls when \"fast\" instruction selection "
157 "fails to lower a formal argument"));
161 cl::desc("use Machine Branch Probability Info"),
162 cl::init(true), cl::Hidden);
166 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the first "
168 "dag combine pass"));
170 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before legalize types"));
173 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
174 cl::desc("Pop up a window to show dags before legalize"));
176 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
177 cl::desc("Pop up a window to show dags before the second "
178 "dag combine pass"));
180 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
181 cl::desc("Pop up a window to show dags before the post legalize types"
182 " dag combine pass"));
184 ViewISelDAGs("view-isel-dags", cl::Hidden,
185 cl::desc("Pop up a window to show isel dags as they are selected"));
187 ViewSchedDAGs("view-sched-dags", cl::Hidden,
188 cl::desc("Pop up a window to show sched dags as they are processed"));
190 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
191 cl::desc("Pop up a window to show SUnit dags after they are processed"));
193 static const bool ViewDAGCombine1 = false,
194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
195 ViewDAGCombine2 = false,
196 ViewDAGCombineLT = false,
197 ViewISelDAGs = false, ViewSchedDAGs = false,
198 ViewSUnitDAGs = false;
201 //===---------------------------------------------------------------------===//
203 /// RegisterScheduler class - Track the registration of instruction schedulers.
205 //===---------------------------------------------------------------------===//
206 MachinePassRegistry RegisterScheduler::Registry;
208 //===---------------------------------------------------------------------===//
210 /// ISHeuristic command line option for instruction schedulers.
212 //===---------------------------------------------------------------------===//
213 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
214 RegisterPassParser<RegisterScheduler> >
215 ISHeuristic("pre-RA-sched",
216 cl::init(&createDefaultScheduler),
217 cl::desc("Instruction schedulers available (before register"
220 static RegisterScheduler
221 defaultListDAGScheduler("default", "Best scheduler for the target",
222 createDefaultScheduler);
225 //===--------------------------------------------------------------------===//
226 /// createDefaultScheduler - This creates an instruction scheduler appropriate
228 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
229 CodeGenOpt::Level OptLevel) {
230 const TargetLowering *TLI = IS->getTargetLowering();
231 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
233 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
234 TLI->getSchedulingPreference() == Sched::Source)
235 return createSourceListDAGScheduler(IS, OptLevel);
236 if (TLI->getSchedulingPreference() == Sched::RegPressure)
237 return createBURRListDAGScheduler(IS, OptLevel);
238 if (TLI->getSchedulingPreference() == Sched::Hybrid)
239 return createHybridListDAGScheduler(IS, OptLevel);
240 if (TLI->getSchedulingPreference() == Sched::VLIW)
241 return createVLIWDAGScheduler(IS, OptLevel);
242 assert(TLI->getSchedulingPreference() == Sched::ILP &&
243 "Unknown sched type!");
244 return createILPListDAGScheduler(IS, OptLevel);
248 // EmitInstrWithCustomInserter - This method should be implemented by targets
249 // that mark instructions with the 'usesCustomInserter' flag. These
250 // instructions are special in various ways, which require special support to
251 // insert. The specified MachineInstr is created but not inserted into any
252 // basic blocks, and this method is called to expand it into a sequence of
253 // instructions, potentially also creating new basic blocks and control flow.
254 // When new basic blocks are inserted and the edges from MBB to its successors
255 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
258 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
259 MachineBasicBlock *MBB) const {
261 dbgs() << "If a target marks an instruction with "
262 "'usesCustomInserter', it must implement "
263 "TargetLowering::EmitInstrWithCustomInserter!";
268 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
269 SDNode *Node) const {
270 assert(!MI->hasPostISelHook() &&
271 "If a target marks an instruction with 'hasPostISelHook', "
272 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
275 //===----------------------------------------------------------------------===//
276 // SelectionDAGISel code
277 //===----------------------------------------------------------------------===//
279 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
280 CodeGenOpt::Level OL) :
281 MachineFunctionPass(ID), TM(tm),
282 FuncInfo(new FunctionLoweringInfo(TM)),
283 CurDAG(new SelectionDAG(tm, OL)),
284 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
288 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
289 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
290 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
291 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
294 SelectionDAGISel::~SelectionDAGISel() {
300 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
301 AU.addRequired<AliasAnalysis>();
302 AU.addPreserved<AliasAnalysis>();
303 AU.addRequired<GCModuleInfo>();
304 AU.addPreserved<GCModuleInfo>();
305 AU.addRequired<TargetLibraryInfo>();
306 if (UseMBPI && OptLevel != CodeGenOpt::None)
307 AU.addRequired<BranchProbabilityInfo>();
308 MachineFunctionPass::getAnalysisUsage(AU);
311 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
312 /// may trap on it. In this case we have to split the edge so that the path
313 /// through the predecessor block that doesn't go to the phi block doesn't
314 /// execute the possibly trapping instruction.
316 /// This is required for correctness, so it must be done at -O0.
318 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
319 // Loop for blocks with phi nodes.
320 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
321 PHINode *PN = dyn_cast<PHINode>(BB->begin());
322 if (PN == 0) continue;
325 // For each block with a PHI node, check to see if any of the input values
326 // are potentially trapping constant expressions. Constant expressions are
327 // the only potentially trapping value that can occur as the argument to a
329 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
330 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
331 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
332 if (CE == 0 || !CE->canTrap()) continue;
334 // The only case we have to worry about is when the edge is critical.
335 // Since this block has a PHI Node, we assume it has multiple input
336 // edges: check to see if the pred has multiple successors.
337 BasicBlock *Pred = PN->getIncomingBlock(i);
338 if (Pred->getTerminator()->getNumSuccessors() == 1)
341 // Okay, we have to split this edge.
342 SplitCriticalEdge(Pred->getTerminator(),
343 GetSuccessorNumber(Pred, BB), SDISel, true);
349 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
350 // Do some sanity-checking on the command-line options.
351 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
352 "-fast-isel-verbose requires -fast-isel");
353 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
354 "-fast-isel-abort requires -fast-isel");
356 const Function &Fn = *mf.getFunction();
357 const TargetInstrInfo &TII = *TM.getInstrInfo();
358 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
361 RegInfo = &MF->getRegInfo();
362 AA = &getAnalysis<AliasAnalysis>();
363 LibInfo = &getAnalysis<TargetLibraryInfo>();
364 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
365 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
367 TargetSubtargetInfo &ST =
368 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
369 ST.resetSubtargetFeatures(MF);
370 TM.resetTargetOptions(MF);
372 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
374 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
376 CurDAG->init(*MF, TTI);
377 FuncInfo->set(Fn, *MF);
379 if (UseMBPI && OptLevel != CodeGenOpt::None)
380 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
384 SDB->init(GFI, *AA, LibInfo);
386 MF->setHasMSInlineAsm(false);
387 SelectAllBasicBlocks(Fn);
389 // If the first basic block in the function has live ins that need to be
390 // copied into vregs, emit the copies into the top of the block before
391 // emitting the code for the block.
392 MachineBasicBlock *EntryMBB = MF->begin();
393 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
395 DenseMap<unsigned, unsigned> LiveInMap;
396 if (!FuncInfo->ArgDbgValues.empty())
397 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
398 E = RegInfo->livein_end(); LI != E; ++LI)
400 LiveInMap.insert(std::make_pair(LI->first, LI->second));
402 // Insert DBG_VALUE instructions for function arguments to the entry block.
403 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
404 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
405 bool hasFI = MI->getOperand(0).isFI();
406 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
407 if (TargetRegisterInfo::isPhysicalRegister(Reg))
408 EntryMBB->insert(EntryMBB->begin(), MI);
410 MachineInstr *Def = RegInfo->getVRegDef(Reg);
411 MachineBasicBlock::iterator InsertPos = Def;
412 // FIXME: VR def may not be in entry block.
413 Def->getParent()->insert(llvm::next(InsertPos), MI);
416 // If Reg is live-in then update debug info to track its copy in a vreg.
417 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
418 if (LDI != LiveInMap.end()) {
419 assert(!hasFI && "There's no handling of frame pointer updating here yet "
421 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
422 MachineBasicBlock::iterator InsertPos = Def;
423 const MDNode *Variable =
424 MI->getOperand(MI->getNumOperands()-1).getMetadata();
425 bool IsIndirect = MI->getOperand(1).isImm();
426 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
427 // Def is never a terminator here, so it is ok to increment InsertPos.
428 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
429 TII.get(TargetOpcode::DBG_VALUE),
431 LDI->second, Offset, Variable);
433 // If this vreg is directly copied into an exported register then
434 // that COPY instructions also need DBG_VALUE, if it is the only
435 // user of LDI->second.
436 MachineInstr *CopyUseMI = NULL;
437 for (MachineRegisterInfo::use_iterator
438 UI = RegInfo->use_begin(LDI->second);
439 MachineInstr *UseMI = UI.skipInstruction();) {
440 if (UseMI->isDebugValue()) continue;
441 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
442 CopyUseMI = UseMI; continue;
444 // Otherwise this is another use or second copy use.
445 CopyUseMI = NULL; break;
448 MachineInstr *NewMI =
449 BuildMI(*MF, CopyUseMI->getDebugLoc(),
450 TII.get(TargetOpcode::DBG_VALUE),
452 CopyUseMI->getOperand(0).getReg(),
454 MachineBasicBlock::iterator Pos = CopyUseMI;
455 EntryMBB->insertAfter(Pos, NewMI);
460 // Determine if there are any calls in this machine function.
461 MachineFrameInfo *MFI = MF->getFrameInfo();
462 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
465 if (MFI->hasCalls() && MF->hasMSInlineAsm())
468 const MachineBasicBlock *MBB = I;
469 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
471 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
472 if ((MCID.isCall() && !MCID.isReturn()) ||
473 II->isStackAligningInlineAsm()) {
474 MFI->setHasCalls(true);
476 if (II->isMSInlineAsm()) {
477 MF->setHasMSInlineAsm(true);
482 // Determine if there is a call to setjmp in the machine function.
483 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
485 // Replace forward-declared registers with the registers containing
486 // the desired value.
487 MachineRegisterInfo &MRI = MF->getRegInfo();
488 for (DenseMap<unsigned, unsigned>::iterator
489 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
491 unsigned From = I->first;
492 unsigned To = I->second;
493 // If To is also scheduled to be replaced, find what its ultimate
496 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
501 MRI.replaceRegWith(From, To);
504 // Freeze the set of reserved registers now that MachineFrameInfo has been
505 // set up. All the information required by getReservedRegs() should be
507 MRI.freezeReservedRegs(*MF);
509 // Release function-specific state. SDB and CurDAG are already cleared
516 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
517 BasicBlock::const_iterator End,
519 // Lower all of the non-terminator instructions. If a call is emitted
520 // as a tail call, cease emitting nodes for this block. Terminators
521 // are handled below.
522 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
525 // Make sure the root of the DAG is up-to-date.
526 CurDAG->setRoot(SDB->getControlRoot());
527 HadTailCall = SDB->HasTailCall;
530 // Final step, emit the lowered DAG as machine code.
534 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
535 SmallPtrSet<SDNode*, 128> VisitedNodes;
536 SmallVector<SDNode*, 128> Worklist;
538 Worklist.push_back(CurDAG->getRoot().getNode());
544 SDNode *N = Worklist.pop_back_val();
546 // If we've already seen this node, ignore it.
547 if (!VisitedNodes.insert(N))
550 // Otherwise, add all chain operands to the worklist.
551 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
552 if (N->getOperand(i).getValueType() == MVT::Other)
553 Worklist.push_back(N->getOperand(i).getNode());
555 // If this is a CopyToReg with a vreg dest, process it.
556 if (N->getOpcode() != ISD::CopyToReg)
559 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
560 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
563 // Ignore non-scalar or non-integer values.
564 SDValue Src = N->getOperand(2);
565 EVT SrcVT = Src.getValueType();
566 if (!SrcVT.isInteger() || SrcVT.isVector())
569 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
570 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
571 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
572 } while (!Worklist.empty());
575 void SelectionDAGISel::CodeGenAndEmitDAG() {
576 std::string GroupName;
577 if (TimePassesIsEnabled)
578 GroupName = "Instruction Selection and Scheduling";
579 std::string BlockName;
580 int BlockNumber = -1;
583 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
584 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
588 BlockNumber = FuncInfo->MBB->getNumber();
589 BlockName = MF->getName().str() + ":" +
590 FuncInfo->MBB->getBasicBlock()->getName().str();
592 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
593 << " '" << BlockName << "'\n"; CurDAG->dump());
595 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
597 // Run the DAG combiner in pre-legalize mode.
599 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
600 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
603 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
604 << " '" << BlockName << "'\n"; CurDAG->dump());
606 // Second step, hack on the DAG until it only uses operations and types that
607 // the target supports.
608 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
613 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
614 Changed = CurDAG->LegalizeTypes();
617 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
618 << " '" << BlockName << "'\n"; CurDAG->dump());
621 if (ViewDAGCombineLT)
622 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
624 // Run the DAG combiner in post-type-legalize mode.
626 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
627 TimePassesIsEnabled);
628 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
631 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
632 << " '" << BlockName << "'\n"; CurDAG->dump());
637 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
638 Changed = CurDAG->LegalizeVectors();
643 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
644 CurDAG->LegalizeTypes();
647 if (ViewDAGCombineLT)
648 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
650 // Run the DAG combiner in post-type-legalize mode.
652 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
653 TimePassesIsEnabled);
654 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
657 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
658 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
661 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
664 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
668 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
669 << " '" << BlockName << "'\n"; CurDAG->dump());
671 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
673 // Run the DAG combiner in post-legalize mode.
675 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
676 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
679 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
680 << " '" << BlockName << "'\n"; CurDAG->dump());
682 if (OptLevel != CodeGenOpt::None)
683 ComputeLiveOutVRegInfo();
685 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
687 // Third, instruction select all of the operations to machine code, adding the
688 // code to the MachineBasicBlock.
690 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
691 DoInstructionSelection();
694 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
695 << " '" << BlockName << "'\n"; CurDAG->dump());
697 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
699 // Schedule machine code.
700 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
702 NamedRegionTimer T("Instruction Scheduling", GroupName,
703 TimePassesIsEnabled);
704 Scheduler->Run(CurDAG, FuncInfo->MBB);
707 if (ViewSUnitDAGs) Scheduler->viewGraph();
709 // Emit machine code to BB. This can change 'BB' to the last block being
711 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
713 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
715 // FuncInfo->InsertPt is passed by reference and set to the end of the
716 // scheduled instructions.
717 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
720 // If the block was split, make sure we update any references that are used to
721 // update PHI nodes later on.
722 if (FirstMBB != LastMBB)
723 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
725 // Free the scheduler state.
727 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
728 TimePassesIsEnabled);
732 // Free the SelectionDAG state, now that we're finished with it.
737 /// ISelUpdater - helper class to handle updates of the instruction selection
739 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
740 SelectionDAG::allnodes_iterator &ISelPosition;
742 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
743 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
745 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
746 /// deleted is the current ISelPosition node, update ISelPosition.
748 virtual void NodeDeleted(SDNode *N, SDNode *E) {
749 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
753 } // end anonymous namespace
755 void SelectionDAGISel::DoInstructionSelection() {
756 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
757 << FuncInfo->MBB->getNumber()
758 << " '" << FuncInfo->MBB->getName() << "'\n");
762 // Select target instructions for the DAG.
764 // Number all nodes with a topological order and set DAGSize.
765 DAGSize = CurDAG->AssignTopologicalOrder();
767 // Create a dummy node (which is not added to allnodes), that adds
768 // a reference to the root node, preventing it from being deleted,
769 // and tracking any changes of the root.
770 HandleSDNode Dummy(CurDAG->getRoot());
771 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
774 // Make sure that ISelPosition gets properly updated when nodes are deleted
775 // in calls made from this function.
776 ISelUpdater ISU(*CurDAG, ISelPosition);
778 // The AllNodes list is now topological-sorted. Visit the
779 // nodes by starting at the end of the list (the root of the
780 // graph) and preceding back toward the beginning (the entry
782 while (ISelPosition != CurDAG->allnodes_begin()) {
783 SDNode *Node = --ISelPosition;
784 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
785 // but there are currently some corner cases that it misses. Also, this
786 // makes it theoretically possible to disable the DAGCombiner.
787 if (Node->use_empty())
790 SDNode *ResNode = Select(Node);
792 // FIXME: This is pretty gross. 'Select' should be changed to not return
793 // anything at all and this code should be nuked with a tactical strike.
795 // If node should not be replaced, continue with the next one.
796 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
800 ReplaceUses(Node, ResNode);
803 // If after the replacement this node is not used any more,
804 // remove this dead node.
805 if (Node->use_empty()) // Don't delete EntryToken, etc.
806 CurDAG->RemoveDeadNode(Node);
809 CurDAG->setRoot(Dummy.getValue());
812 DEBUG(dbgs() << "===== Instruction selection ends:\n");
814 PostprocessISelDAG();
817 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
818 /// do other setup for EH landing-pad blocks.
819 void SelectionDAGISel::PrepareEHLandingPad() {
820 MachineBasicBlock *MBB = FuncInfo->MBB;
822 // Add a label to mark the beginning of the landing pad. Deletion of the
823 // landing pad can thus be detected via the MachineModuleInfo.
824 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
826 // Assign the call site to the landing pad's begin label.
827 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
829 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
830 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
833 // Mark exception register as live in.
834 const TargetLowering *TLI = getTargetLowering();
835 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
836 if (unsigned Reg = TLI->getExceptionPointerRegister())
837 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
839 // Mark exception selector register as live in.
840 if (unsigned Reg = TLI->getExceptionSelectorRegister())
841 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
844 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
845 /// side-effect free and is either dead or folded into a generated instruction.
846 /// Return false if it needs to be emitted.
847 static bool isFoldedOrDeadInstruction(const Instruction *I,
848 FunctionLoweringInfo *FuncInfo) {
849 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
850 !isa<TerminatorInst>(I) && // Terminators aren't folded.
851 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
852 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
853 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
857 // Collect per Instruction statistics for fast-isel misses. Only those
858 // instructions that cause the bail are accounted for. It does not account for
859 // instructions higher in the block. Thus, summing the per instructions stats
860 // will not add up to what is reported by NumFastIselFailures.
861 static void collectFailStats(const Instruction *I) {
862 switch (I->getOpcode()) {
863 default: assert (0 && "<Invalid operator> ");
866 case Instruction::Ret: NumFastIselFailRet++; return;
867 case Instruction::Br: NumFastIselFailBr++; return;
868 case Instruction::Switch: NumFastIselFailSwitch++; return;
869 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
870 case Instruction::Invoke: NumFastIselFailInvoke++; return;
871 case Instruction::Resume: NumFastIselFailResume++; return;
872 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
874 // Standard binary operators...
875 case Instruction::Add: NumFastIselFailAdd++; return;
876 case Instruction::FAdd: NumFastIselFailFAdd++; return;
877 case Instruction::Sub: NumFastIselFailSub++; return;
878 case Instruction::FSub: NumFastIselFailFSub++; return;
879 case Instruction::Mul: NumFastIselFailMul++; return;
880 case Instruction::FMul: NumFastIselFailFMul++; return;
881 case Instruction::UDiv: NumFastIselFailUDiv++; return;
882 case Instruction::SDiv: NumFastIselFailSDiv++; return;
883 case Instruction::FDiv: NumFastIselFailFDiv++; return;
884 case Instruction::URem: NumFastIselFailURem++; return;
885 case Instruction::SRem: NumFastIselFailSRem++; return;
886 case Instruction::FRem: NumFastIselFailFRem++; return;
888 // Logical operators...
889 case Instruction::And: NumFastIselFailAnd++; return;
890 case Instruction::Or: NumFastIselFailOr++; return;
891 case Instruction::Xor: NumFastIselFailXor++; return;
893 // Memory instructions...
894 case Instruction::Alloca: NumFastIselFailAlloca++; return;
895 case Instruction::Load: NumFastIselFailLoad++; return;
896 case Instruction::Store: NumFastIselFailStore++; return;
897 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
898 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
899 case Instruction::Fence: NumFastIselFailFence++; return;
900 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
902 // Convert instructions...
903 case Instruction::Trunc: NumFastIselFailTrunc++; return;
904 case Instruction::ZExt: NumFastIselFailZExt++; return;
905 case Instruction::SExt: NumFastIselFailSExt++; return;
906 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
907 case Instruction::FPExt: NumFastIselFailFPExt++; return;
908 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
909 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
910 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
911 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
912 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
913 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
914 case Instruction::BitCast: NumFastIselFailBitCast++; return;
916 // Other instructions...
917 case Instruction::ICmp: NumFastIselFailICmp++; return;
918 case Instruction::FCmp: NumFastIselFailFCmp++; return;
919 case Instruction::PHI: NumFastIselFailPHI++; return;
920 case Instruction::Select: NumFastIselFailSelect++; return;
921 case Instruction::Call: NumFastIselFailCall++; return;
922 case Instruction::Shl: NumFastIselFailShl++; return;
923 case Instruction::LShr: NumFastIselFailLShr++; return;
924 case Instruction::AShr: NumFastIselFailAShr++; return;
925 case Instruction::VAArg: NumFastIselFailVAArg++; return;
926 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
927 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
928 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
929 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
930 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
931 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
936 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
937 // Initialize the Fast-ISel state, if needed.
938 FastISel *FastIS = 0;
939 if (TM.Options.EnableFastISel)
940 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
942 // Iterate over all basic blocks in the function.
943 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
944 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
945 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
946 const BasicBlock *LLVMBB = *I;
948 if (OptLevel != CodeGenOpt::None) {
949 bool AllPredsVisited = true;
950 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
952 if (!FuncInfo->VisitedBBs.count(*PI)) {
953 AllPredsVisited = false;
958 if (AllPredsVisited) {
959 for (BasicBlock::const_iterator I = LLVMBB->begin();
960 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
961 FuncInfo->ComputePHILiveOutRegInfo(PN);
963 for (BasicBlock::const_iterator I = LLVMBB->begin();
964 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
965 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
968 FuncInfo->VisitedBBs.insert(LLVMBB);
971 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
972 BasicBlock::const_iterator const End = LLVMBB->end();
973 BasicBlock::const_iterator BI = End;
975 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
976 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
978 // Setup an EH landing-pad block.
979 FuncInfo->ExceptionPointerVirtReg = 0;
980 FuncInfo->ExceptionSelectorVirtReg = 0;
981 if (FuncInfo->MBB->isLandingPad())
982 PrepareEHLandingPad();
984 // Before doing SelectionDAG ISel, see if FastISel has been requested.
986 FastIS->startNewBlock();
988 // Emit code for any incoming arguments. This must happen before
989 // beginning FastISel on the entry block.
990 if (LLVMBB == &Fn.getEntryBlock()) {
993 // Lower any arguments needed in this block if this is the entry block.
994 if (!FastIS->LowerArguments()) {
995 // Fast isel failed to lower these arguments
996 ++NumFastIselFailLowerArguments;
997 if (EnableFastISelAbortArgs)
998 llvm_unreachable("FastISel didn't lower all arguments");
1000 // Use SelectionDAG argument lowering
1002 CurDAG->setRoot(SDB->getControlRoot());
1004 CodeGenAndEmitDAG();
1007 // If we inserted any instructions at the beginning, make a note of
1008 // where they are, so we can be sure to emit subsequent instructions
1010 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1011 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1013 FastIS->setLastLocalValue(0);
1016 unsigned NumFastIselRemaining = std::distance(Begin, End);
1017 // Do FastISel on as many instructions as possible.
1018 for (; BI != Begin; --BI) {
1019 const Instruction *Inst = llvm::prior(BI);
1021 // If we no longer require this instruction, skip it.
1022 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1023 --NumFastIselRemaining;
1027 // Bottom-up: reset the insert pos at the top, after any local-value
1029 FastIS->recomputeInsertPt();
1031 // Try to select the instruction with FastISel.
1032 if (FastIS->SelectInstruction(Inst)) {
1033 --NumFastIselRemaining;
1034 ++NumFastIselSuccess;
1035 // If fast isel succeeded, skip over all the folded instructions, and
1036 // then see if there is a load right before the selected instructions.
1037 // Try to fold the load if so.
1038 const Instruction *BeforeInst = Inst;
1039 while (BeforeInst != Begin) {
1040 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1041 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1044 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1045 BeforeInst->hasOneUse() &&
1046 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1047 // If we succeeded, don't re-select the load.
1048 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1049 --NumFastIselRemaining;
1050 ++NumFastIselSuccess;
1056 if (EnableFastISelVerbose2)
1057 collectFailStats(Inst);
1060 // Then handle certain instructions as single-LLVM-Instruction blocks.
1061 if (isa<CallInst>(Inst)) {
1063 if (EnableFastISelVerbose || EnableFastISelAbort) {
1064 dbgs() << "FastISel missed call: ";
1068 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1069 unsigned &R = FuncInfo->ValueMap[Inst];
1071 R = FuncInfo->CreateRegs(Inst->getType());
1074 bool HadTailCall = false;
1075 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1076 SelectBasicBlock(Inst, BI, HadTailCall);
1078 // If the call was emitted as a tail call, we're done with the block.
1079 // We also need to delete any previously emitted instructions.
1081 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1086 // Recompute NumFastIselRemaining as Selection DAG instruction
1087 // selection may have handled the call, input args, etc.
1088 unsigned RemainingNow = std::distance(Begin, BI);
1089 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1090 NumFastIselRemaining = RemainingNow;
1094 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1095 // Don't abort, and use a different message for terminator misses.
1096 NumFastIselFailures += NumFastIselRemaining;
1097 if (EnableFastISelVerbose || EnableFastISelAbort) {
1098 dbgs() << "FastISel missed terminator: ";
1102 NumFastIselFailures += NumFastIselRemaining;
1103 if (EnableFastISelVerbose || EnableFastISelAbort) {
1104 dbgs() << "FastISel miss: ";
1107 if (EnableFastISelAbort)
1108 // The "fast" selector couldn't handle something and bailed.
1109 // For the purpose of debugging, just abort.
1110 llvm_unreachable("FastISel didn't select the entire block");
1115 FastIS->recomputeInsertPt();
1117 // Lower any arguments needed in this block if this is the entry block.
1118 if (LLVMBB == &Fn.getEntryBlock()) {
1127 ++NumFastIselBlocks;
1130 // Run SelectionDAG instruction selection on the remainder of the block
1131 // not handled by FastISel. If FastISel is not run, this is the entire
1134 SelectBasicBlock(Begin, BI, HadTailCall);
1138 FuncInfo->PHINodesToUpdate.clear();
1142 SDB->clearDanglingDebugInfo();
1146 SelectionDAGISel::FinishBasicBlock() {
1148 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1149 << FuncInfo->PHINodesToUpdate.size() << "\n";
1150 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1151 dbgs() << "Node " << i << " : ("
1152 << FuncInfo->PHINodesToUpdate[i].first
1153 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1155 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1156 // PHI nodes in successors.
1157 if (SDB->SwitchCases.empty() &&
1158 SDB->JTCases.empty() &&
1159 SDB->BitTestCases.empty()) {
1160 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1161 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1162 assert(PHI->isPHI() &&
1163 "This is not a machine PHI node that we are updating!");
1164 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1166 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1171 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1172 // Lower header first, if it wasn't already lowered
1173 if (!SDB->BitTestCases[i].Emitted) {
1174 // Set the current basic block to the mbb we wish to insert the code into
1175 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1176 FuncInfo->InsertPt = FuncInfo->MBB->end();
1178 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1179 CurDAG->setRoot(SDB->getRoot());
1181 CodeGenAndEmitDAG();
1184 uint32_t UnhandledWeight = 0;
1185 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1186 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1188 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1189 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1190 // Set the current basic block to the mbb we wish to insert the code into
1191 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1192 FuncInfo->InsertPt = FuncInfo->MBB->end();
1195 SDB->visitBitTestCase(SDB->BitTestCases[i],
1196 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1198 SDB->BitTestCases[i].Reg,
1199 SDB->BitTestCases[i].Cases[j],
1202 SDB->visitBitTestCase(SDB->BitTestCases[i],
1203 SDB->BitTestCases[i].Default,
1205 SDB->BitTestCases[i].Reg,
1206 SDB->BitTestCases[i].Cases[j],
1210 CurDAG->setRoot(SDB->getRoot());
1212 CodeGenAndEmitDAG();
1216 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1218 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1219 MachineBasicBlock *PHIBB = PHI->getParent();
1220 assert(PHI->isPHI() &&
1221 "This is not a machine PHI node that we are updating!");
1222 // This is "default" BB. We have two jumps to it. From "header" BB and
1223 // from last "case" BB.
1224 if (PHIBB == SDB->BitTestCases[i].Default)
1225 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1226 .addMBB(SDB->BitTestCases[i].Parent)
1227 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1228 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1229 // One of "cases" BB.
1230 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1232 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1233 if (cBB->isSuccessor(PHIBB))
1234 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1238 SDB->BitTestCases.clear();
1240 // If the JumpTable record is filled in, then we need to emit a jump table.
1241 // Updating the PHI nodes is tricky in this case, since we need to determine
1242 // whether the PHI is a successor of the range check MBB or the jump table MBB
1243 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1244 // Lower header first, if it wasn't already lowered
1245 if (!SDB->JTCases[i].first.Emitted) {
1246 // Set the current basic block to the mbb we wish to insert the code into
1247 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1248 FuncInfo->InsertPt = FuncInfo->MBB->end();
1250 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1252 CurDAG->setRoot(SDB->getRoot());
1254 CodeGenAndEmitDAG();
1257 // Set the current basic block to the mbb we wish to insert the code into
1258 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1259 FuncInfo->InsertPt = FuncInfo->MBB->end();
1261 SDB->visitJumpTable(SDB->JTCases[i].second);
1262 CurDAG->setRoot(SDB->getRoot());
1264 CodeGenAndEmitDAG();
1267 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1269 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1270 MachineBasicBlock *PHIBB = PHI->getParent();
1271 assert(PHI->isPHI() &&
1272 "This is not a machine PHI node that we are updating!");
1273 // "default" BB. We can go there only from header BB.
1274 if (PHIBB == SDB->JTCases[i].second.Default)
1275 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1276 .addMBB(SDB->JTCases[i].first.HeaderBB);
1277 // JT BB. Just iterate over successors here
1278 if (FuncInfo->MBB->isSuccessor(PHIBB))
1279 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1282 SDB->JTCases.clear();
1284 // If the switch block involved a branch to one of the actual successors, we
1285 // need to update PHI nodes in that block.
1286 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1287 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1288 assert(PHI->isPHI() &&
1289 "This is not a machine PHI node that we are updating!");
1290 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1291 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1294 // If we generated any switch lowering information, build and codegen any
1295 // additional DAGs necessary.
1296 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1297 // Set the current basic block to the mbb we wish to insert the code into
1298 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1299 FuncInfo->InsertPt = FuncInfo->MBB->end();
1301 // Determine the unique successors.
1302 SmallVector<MachineBasicBlock *, 2> Succs;
1303 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1304 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1305 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1307 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1308 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1309 CurDAG->setRoot(SDB->getRoot());
1311 CodeGenAndEmitDAG();
1313 // Remember the last block, now that any splitting is done, for use in
1314 // populating PHI nodes in successors.
1315 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1317 // Handle any PHI nodes in successors of this chunk, as if we were coming
1318 // from the original BB before switch expansion. Note that PHI nodes can
1319 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1320 // handle them the right number of times.
1321 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1322 FuncInfo->MBB = Succs[i];
1323 FuncInfo->InsertPt = FuncInfo->MBB->end();
1324 // FuncInfo->MBB may have been removed from the CFG if a branch was
1326 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1327 for (MachineBasicBlock::iterator
1328 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1329 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1330 MachineInstrBuilder PHI(*MF, MBBI);
1331 // This value for this PHI node is recorded in PHINodesToUpdate.
1332 for (unsigned pn = 0; ; ++pn) {
1333 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1334 "Didn't find PHI entry!");
1335 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1336 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1344 SDB->SwitchCases.clear();
1348 /// Create the scheduler. If a specific scheduler was specified
1349 /// via the SchedulerRegistry, use it, otherwise select the
1350 /// one preferred by the target.
1352 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1353 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1357 RegisterScheduler::setDefault(Ctor);
1360 return Ctor(this, OptLevel);
1363 //===----------------------------------------------------------------------===//
1364 // Helper functions used by the generated instruction selector.
1365 //===----------------------------------------------------------------------===//
1366 // Calls to these methods are generated by tblgen.
1368 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1369 /// the dag combiner simplified the 255, we still want to match. RHS is the
1370 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1371 /// specified in the .td file (e.g. 255).
1372 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1373 int64_t DesiredMaskS) const {
1374 const APInt &ActualMask = RHS->getAPIntValue();
1375 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1377 // If the actual mask exactly matches, success!
1378 if (ActualMask == DesiredMask)
1381 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1382 if (ActualMask.intersects(~DesiredMask))
1385 // Otherwise, the DAG Combiner may have proven that the value coming in is
1386 // either already zero or is not demanded. Check for known zero input bits.
1387 APInt NeededMask = DesiredMask & ~ActualMask;
1388 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1391 // TODO: check to see if missing bits are just not demanded.
1393 // Otherwise, this pattern doesn't match.
1397 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1398 /// the dag combiner simplified the 255, we still want to match. RHS is the
1399 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1400 /// specified in the .td file (e.g. 255).
1401 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1402 int64_t DesiredMaskS) const {
1403 const APInt &ActualMask = RHS->getAPIntValue();
1404 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1406 // If the actual mask exactly matches, success!
1407 if (ActualMask == DesiredMask)
1410 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1411 if (ActualMask.intersects(~DesiredMask))
1414 // Otherwise, the DAG Combiner may have proven that the value coming in is
1415 // either already zero or is not demanded. Check for known zero input bits.
1416 APInt NeededMask = DesiredMask & ~ActualMask;
1418 APInt KnownZero, KnownOne;
1419 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1421 // If all the missing bits in the or are already known to be set, match!
1422 if ((NeededMask & KnownOne) == NeededMask)
1425 // TODO: check to see if missing bits are just not demanded.
1427 // Otherwise, this pattern doesn't match.
1432 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1433 /// by tblgen. Others should not call it.
1434 void SelectionDAGISel::
1435 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1436 std::vector<SDValue> InOps;
1437 std::swap(InOps, Ops);
1439 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1440 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1441 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1442 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1444 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1445 if (InOps[e-1].getValueType() == MVT::Glue)
1446 --e; // Don't process a glue operand if it is here.
1449 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1450 if (!InlineAsm::isMemKind(Flags)) {
1451 // Just skip over this operand, copying the operands verbatim.
1452 Ops.insert(Ops.end(), InOps.begin()+i,
1453 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1454 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1456 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1457 "Memory operand with multiple values?");
1458 // Otherwise, this is a memory operand. Ask the target to select it.
1459 std::vector<SDValue> SelOps;
1460 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1461 report_fatal_error("Could not match memory address. Inline asm"
1464 // Add this to the output node.
1466 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1467 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1468 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1473 // Add the glue input back if present.
1474 if (e != InOps.size())
1475 Ops.push_back(InOps.back());
1478 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1481 static SDNode *findGlueUse(SDNode *N) {
1482 unsigned FlagResNo = N->getNumValues()-1;
1483 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1484 SDUse &Use = I.getUse();
1485 if (Use.getResNo() == FlagResNo)
1486 return Use.getUser();
1491 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1492 /// This function recursively traverses up the operand chain, ignoring
1494 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1495 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1496 bool IgnoreChains) {
1497 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1498 // greater than all of its (recursive) operands. If we scan to a point where
1499 // 'use' is smaller than the node we're scanning for, then we know we will
1502 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1503 // happen because we scan down to newly selected nodes in the case of glue
1505 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1508 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1509 // won't fail if we scan it again.
1510 if (!Visited.insert(Use))
1513 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1514 // Ignore chain uses, they are validated by HandleMergeInputChains.
1515 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1518 SDNode *N = Use->getOperand(i).getNode();
1520 if (Use == ImmedUse || Use == Root)
1521 continue; // We are not looking for immediate use.
1526 // Traverse up the operand chain.
1527 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1533 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1534 /// operand node N of U during instruction selection that starts at Root.
1535 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1536 SDNode *Root) const {
1537 if (OptLevel == CodeGenOpt::None) return false;
1538 return N.hasOneUse();
1541 /// IsLegalToFold - Returns true if the specific operand node N of
1542 /// U can be folded during instruction selection that starts at Root.
1543 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1544 CodeGenOpt::Level OptLevel,
1545 bool IgnoreChains) {
1546 if (OptLevel == CodeGenOpt::None) return false;
1548 // If Root use can somehow reach N through a path that that doesn't contain
1549 // U then folding N would create a cycle. e.g. In the following
1550 // diagram, Root can reach N through X. If N is folded into into Root, then
1551 // X is both a predecessor and a successor of U.
1562 // * indicates nodes to be folded together.
1564 // If Root produces glue, then it gets (even more) interesting. Since it
1565 // will be "glued" together with its glue use in the scheduler, we need to
1566 // check if it might reach N.
1585 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1586 // (call it Fold), then X is a predecessor of GU and a successor of
1587 // Fold. But since Fold and GU are glued together, this will create
1588 // a cycle in the scheduling graph.
1590 // If the node has glue, walk down the graph to the "lowest" node in the
1592 EVT VT = Root->getValueType(Root->getNumValues()-1);
1593 while (VT == MVT::Glue) {
1594 SDNode *GU = findGlueUse(Root);
1598 VT = Root->getValueType(Root->getNumValues()-1);
1600 // If our query node has a glue result with a use, we've walked up it. If
1601 // the user (which has already been selected) has a chain or indirectly uses
1602 // the chain, our WalkChainUsers predicate will not consider it. Because of
1603 // this, we cannot ignore chains in this predicate.
1604 IgnoreChains = false;
1608 SmallPtrSet<SDNode*, 16> Visited;
1609 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1612 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1613 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1614 SelectInlineAsmMemoryOperands(Ops);
1616 EVT VTs[] = { MVT::Other, MVT::Glue };
1617 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1618 VTs, &Ops[0], Ops.size());
1620 return New.getNode();
1623 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1624 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1627 /// GetVBR - decode a vbr encoding whose top bit is set.
1628 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1629 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1630 assert(Val >= 128 && "Not a VBR");
1631 Val &= 127; // Remove first vbr bit.
1636 NextBits = MatcherTable[Idx++];
1637 Val |= (NextBits&127) << Shift;
1639 } while (NextBits & 128);
1645 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1646 /// interior glue and chain results to use the new glue and chain results.
1647 void SelectionDAGISel::
1648 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1649 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1651 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1652 bool isMorphNodeTo) {
1653 SmallVector<SDNode*, 4> NowDeadNodes;
1655 // Now that all the normal results are replaced, we replace the chain and
1656 // glue results if present.
1657 if (!ChainNodesMatched.empty()) {
1658 assert(InputChain.getNode() != 0 &&
1659 "Matched input chains but didn't produce a chain");
1660 // Loop over all of the nodes we matched that produced a chain result.
1661 // Replace all the chain results with the final chain we ended up with.
1662 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1663 SDNode *ChainNode = ChainNodesMatched[i];
1665 // If this node was already deleted, don't look at it.
1666 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1669 // Don't replace the results of the root node if we're doing a
1671 if (ChainNode == NodeToMatch && isMorphNodeTo)
1674 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1675 if (ChainVal.getValueType() == MVT::Glue)
1676 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1677 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1678 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1680 // If the node became dead and we haven't already seen it, delete it.
1681 if (ChainNode->use_empty() &&
1682 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1683 NowDeadNodes.push_back(ChainNode);
1687 // If the result produces glue, update any glue results in the matched
1688 // pattern with the glue result.
1689 if (InputGlue.getNode() != 0) {
1690 // Handle any interior nodes explicitly marked.
1691 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1692 SDNode *FRN = GlueResultNodesMatched[i];
1694 // If this node was already deleted, don't look at it.
1695 if (FRN->getOpcode() == ISD::DELETED_NODE)
1698 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1699 "Doesn't have a glue result");
1700 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1703 // If the node became dead and we haven't already seen it, delete it.
1704 if (FRN->use_empty() &&
1705 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1706 NowDeadNodes.push_back(FRN);
1710 if (!NowDeadNodes.empty())
1711 CurDAG->RemoveDeadNodes(NowDeadNodes);
1713 DEBUG(dbgs() << "ISEL: Match complete!\n");
1719 CR_LeadsToInteriorNode
1722 /// WalkChainUsers - Walk down the users of the specified chained node that is
1723 /// part of the pattern we're matching, looking at all of the users we find.
1724 /// This determines whether something is an interior node, whether we have a
1725 /// non-pattern node in between two pattern nodes (which prevent folding because
1726 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1727 /// between pattern nodes (in which case the TF becomes part of the pattern).
1729 /// The walk we do here is guaranteed to be small because we quickly get down to
1730 /// already selected nodes "below" us.
1732 WalkChainUsers(const SDNode *ChainedNode,
1733 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1734 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1735 ChainResult Result = CR_Simple;
1737 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1738 E = ChainedNode->use_end(); UI != E; ++UI) {
1739 // Make sure the use is of the chain, not some other value we produce.
1740 if (UI.getUse().getValueType() != MVT::Other) continue;
1744 // If we see an already-selected machine node, then we've gone beyond the
1745 // pattern that we're selecting down into the already selected chunk of the
1747 if (User->isMachineOpcode() ||
1748 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1751 unsigned UserOpcode = User->getOpcode();
1752 if (UserOpcode == ISD::CopyToReg ||
1753 UserOpcode == ISD::CopyFromReg ||
1754 UserOpcode == ISD::INLINEASM ||
1755 UserOpcode == ISD::EH_LABEL ||
1756 UserOpcode == ISD::LIFETIME_START ||
1757 UserOpcode == ISD::LIFETIME_END) {
1758 // If their node ID got reset to -1 then they've already been selected.
1759 // Treat them like a MachineOpcode.
1760 if (User->getNodeId() == -1)
1764 // If we have a TokenFactor, we handle it specially.
1765 if (User->getOpcode() != ISD::TokenFactor) {
1766 // If the node isn't a token factor and isn't part of our pattern, then it
1767 // must be a random chained node in between two nodes we're selecting.
1768 // This happens when we have something like:
1773 // Because we structurally match the load/store as a read/modify/write,
1774 // but the call is chained between them. We cannot fold in this case
1775 // because it would induce a cycle in the graph.
1776 if (!std::count(ChainedNodesInPattern.begin(),
1777 ChainedNodesInPattern.end(), User))
1778 return CR_InducesCycle;
1780 // Otherwise we found a node that is part of our pattern. For example in:
1784 // This would happen when we're scanning down from the load and see the
1785 // store as a user. Record that there is a use of ChainedNode that is
1786 // part of the pattern and keep scanning uses.
1787 Result = CR_LeadsToInteriorNode;
1788 InteriorChainedNodes.push_back(User);
1792 // If we found a TokenFactor, there are two cases to consider: first if the
1793 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1794 // uses of the TF are in our pattern) we just want to ignore it. Second,
1795 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1801 // | \ DAG's like cheese
1804 // [TokenFactor] [Op]
1811 // In this case, the TokenFactor becomes part of our match and we rewrite it
1812 // as a new TokenFactor.
1814 // To distinguish these two cases, do a recursive walk down the uses.
1815 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1817 // If the uses of the TokenFactor are just already-selected nodes, ignore
1818 // it, it is "below" our pattern.
1820 case CR_InducesCycle:
1821 // If the uses of the TokenFactor lead to nodes that are not part of our
1822 // pattern that are not selected, folding would turn this into a cycle,
1824 return CR_InducesCycle;
1825 case CR_LeadsToInteriorNode:
1826 break; // Otherwise, keep processing.
1829 // Okay, we know we're in the interesting interior case. The TokenFactor
1830 // is now going to be considered part of the pattern so that we rewrite its
1831 // uses (it may have uses that are not part of the pattern) with the
1832 // ultimate chain result of the generated code. We will also add its chain
1833 // inputs as inputs to the ultimate TokenFactor we create.
1834 Result = CR_LeadsToInteriorNode;
1835 ChainedNodesInPattern.push_back(User);
1836 InteriorChainedNodes.push_back(User);
1843 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1844 /// operation for when the pattern matched at least one node with a chains. The
1845 /// input vector contains a list of all of the chained nodes that we match. We
1846 /// must determine if this is a valid thing to cover (i.e. matching it won't
1847 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1848 /// be used as the input node chain for the generated nodes.
1850 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1851 SelectionDAG *CurDAG) {
1852 // Walk all of the chained nodes we've matched, recursively scanning down the
1853 // users of the chain result. This adds any TokenFactor nodes that are caught
1854 // in between chained nodes to the chained and interior nodes list.
1855 SmallVector<SDNode*, 3> InteriorChainedNodes;
1856 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1857 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1858 InteriorChainedNodes) == CR_InducesCycle)
1859 return SDValue(); // Would induce a cycle.
1862 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1863 // that we are interested in. Form our input TokenFactor node.
1864 SmallVector<SDValue, 3> InputChains;
1865 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1866 // Add the input chain of this node to the InputChains list (which will be
1867 // the operands of the generated TokenFactor) if it's not an interior node.
1868 SDNode *N = ChainNodesMatched[i];
1869 if (N->getOpcode() != ISD::TokenFactor) {
1870 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1873 // Otherwise, add the input chain.
1874 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1875 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1876 InputChains.push_back(InChain);
1880 // If we have a token factor, we want to add all inputs of the token factor
1881 // that are not part of the pattern we're matching.
1882 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1883 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1884 N->getOperand(op).getNode()))
1885 InputChains.push_back(N->getOperand(op));
1890 if (InputChains.size() == 1)
1891 return InputChains[0];
1892 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
1893 MVT::Other, &InputChains[0], InputChains.size());
1896 /// MorphNode - Handle morphing a node in place for the selector.
1897 SDNode *SelectionDAGISel::
1898 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1899 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1900 // It is possible we're using MorphNodeTo to replace a node with no
1901 // normal results with one that has a normal result (or we could be
1902 // adding a chain) and the input could have glue and chains as well.
1903 // In this case we need to shift the operands down.
1904 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1905 // than the old isel though.
1906 int OldGlueResultNo = -1, OldChainResultNo = -1;
1908 unsigned NTMNumResults = Node->getNumValues();
1909 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1910 OldGlueResultNo = NTMNumResults-1;
1911 if (NTMNumResults != 1 &&
1912 Node->getValueType(NTMNumResults-2) == MVT::Other)
1913 OldChainResultNo = NTMNumResults-2;
1914 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1915 OldChainResultNo = NTMNumResults-1;
1917 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1918 // that this deletes operands of the old node that become dead.
1919 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1921 // MorphNodeTo can operate in two ways: if an existing node with the
1922 // specified operands exists, it can just return it. Otherwise, it
1923 // updates the node in place to have the requested operands.
1925 // If we updated the node in place, reset the node ID. To the isel,
1926 // this should be just like a newly allocated machine node.
1930 unsigned ResNumResults = Res->getNumValues();
1931 // Move the glue if needed.
1932 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1933 (unsigned)OldGlueResultNo != ResNumResults-1)
1934 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1935 SDValue(Res, ResNumResults-1));
1937 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1940 // Move the chain reference if needed.
1941 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1942 (unsigned)OldChainResultNo != ResNumResults-1)
1943 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1944 SDValue(Res, ResNumResults-1));
1946 // Otherwise, no replacement happened because the node already exists. Replace
1947 // Uses of the old node with the new one.
1949 CurDAG->ReplaceAllUsesWith(Node, Res);
1954 /// CheckSame - Implements OP_CheckSame.
1955 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1956 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1958 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1959 // Accept if it is exactly the same as a previously recorded node.
1960 unsigned RecNo = MatcherTable[MatcherIndex++];
1961 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1962 return N == RecordedNodes[RecNo].first;
1965 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1966 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1967 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1968 const SelectionDAGISel &SDISel) {
1969 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1972 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1973 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1974 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1975 const SelectionDAGISel &SDISel, SDNode *N) {
1976 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1979 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1980 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1982 uint16_t Opc = MatcherTable[MatcherIndex++];
1983 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1984 return N->getOpcode() == Opc;
1987 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1988 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1989 SDValue N, const TargetLowering *TLI) {
1990 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1991 if (N.getValueType() == VT) return true;
1993 // Handle the case when VT is iPTR.
1994 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
1997 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1998 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1999 SDValue N, const TargetLowering *TLI,
2001 if (ChildNo >= N.getNumOperands())
2002 return false; // Match fails if out of range child #.
2003 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2006 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2007 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2009 return cast<CondCodeSDNode>(N)->get() ==
2010 (ISD::CondCode)MatcherTable[MatcherIndex++];
2013 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2014 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2015 SDValue N, const TargetLowering *TLI) {
2016 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2017 if (cast<VTSDNode>(N)->getVT() == VT)
2020 // Handle the case when VT is iPTR.
2021 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2024 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2025 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2027 int64_t Val = MatcherTable[MatcherIndex++];
2029 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2031 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2032 return C != 0 && C->getSExtValue() == Val;
2035 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2036 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2037 SDValue N, const SelectionDAGISel &SDISel) {
2038 int64_t Val = MatcherTable[MatcherIndex++];
2040 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2042 if (N->getOpcode() != ISD::AND) return false;
2044 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2045 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2048 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2049 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2050 SDValue N, const SelectionDAGISel &SDISel) {
2051 int64_t Val = MatcherTable[MatcherIndex++];
2053 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2055 if (N->getOpcode() != ISD::OR) return false;
2057 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2058 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2061 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2062 /// scope, evaluate the current node. If the current predicate is known to
2063 /// fail, set Result=true and return anything. If the current predicate is
2064 /// known to pass, set Result=false and return the MatcherIndex to continue
2065 /// with. If the current predicate is unknown, set Result=false and return the
2066 /// MatcherIndex to continue with.
2067 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2068 unsigned Index, SDValue N,
2070 const SelectionDAGISel &SDISel,
2071 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2072 switch (Table[Index++]) {
2075 return Index-1; // Could not evaluate this predicate.
2076 case SelectionDAGISel::OPC_CheckSame:
2077 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2079 case SelectionDAGISel::OPC_CheckPatternPredicate:
2080 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2082 case SelectionDAGISel::OPC_CheckPredicate:
2083 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2085 case SelectionDAGISel::OPC_CheckOpcode:
2086 Result = !::CheckOpcode(Table, Index, N.getNode());
2088 case SelectionDAGISel::OPC_CheckType:
2089 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2091 case SelectionDAGISel::OPC_CheckChild0Type:
2092 case SelectionDAGISel::OPC_CheckChild1Type:
2093 case SelectionDAGISel::OPC_CheckChild2Type:
2094 case SelectionDAGISel::OPC_CheckChild3Type:
2095 case SelectionDAGISel::OPC_CheckChild4Type:
2096 case SelectionDAGISel::OPC_CheckChild5Type:
2097 case SelectionDAGISel::OPC_CheckChild6Type:
2098 case SelectionDAGISel::OPC_CheckChild7Type:
2099 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2100 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2102 case SelectionDAGISel::OPC_CheckCondCode:
2103 Result = !::CheckCondCode(Table, Index, N);
2105 case SelectionDAGISel::OPC_CheckValueType:
2106 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2108 case SelectionDAGISel::OPC_CheckInteger:
2109 Result = !::CheckInteger(Table, Index, N);
2111 case SelectionDAGISel::OPC_CheckAndImm:
2112 Result = !::CheckAndImm(Table, Index, N, SDISel);
2114 case SelectionDAGISel::OPC_CheckOrImm:
2115 Result = !::CheckOrImm(Table, Index, N, SDISel);
2123 /// FailIndex - If this match fails, this is the index to continue with.
2126 /// NodeStack - The node stack when the scope was formed.
2127 SmallVector<SDValue, 4> NodeStack;
2129 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2130 unsigned NumRecordedNodes;
2132 /// NumMatchedMemRefs - The number of matched memref entries.
2133 unsigned NumMatchedMemRefs;
2135 /// InputChain/InputGlue - The current chain/glue
2136 SDValue InputChain, InputGlue;
2138 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2139 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2144 SDNode *SelectionDAGISel::
2145 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2146 unsigned TableSize) {
2147 // FIXME: Should these even be selected? Handle these cases in the caller?
2148 switch (NodeToMatch->getOpcode()) {
2151 case ISD::EntryToken: // These nodes remain the same.
2152 case ISD::BasicBlock:
2154 case ISD::RegisterMask:
2155 //case ISD::VALUETYPE:
2156 //case ISD::CONDCODE:
2157 case ISD::HANDLENODE:
2158 case ISD::MDNODE_SDNODE:
2159 case ISD::TargetConstant:
2160 case ISD::TargetConstantFP:
2161 case ISD::TargetConstantPool:
2162 case ISD::TargetFrameIndex:
2163 case ISD::TargetExternalSymbol:
2164 case ISD::TargetBlockAddress:
2165 case ISD::TargetJumpTable:
2166 case ISD::TargetGlobalTLSAddress:
2167 case ISD::TargetGlobalAddress:
2168 case ISD::TokenFactor:
2169 case ISD::CopyFromReg:
2170 case ISD::CopyToReg:
2172 case ISD::LIFETIME_START:
2173 case ISD::LIFETIME_END:
2174 NodeToMatch->setNodeId(-1); // Mark selected.
2176 case ISD::AssertSext:
2177 case ISD::AssertZext:
2178 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2179 NodeToMatch->getOperand(0));
2181 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2182 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2185 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2187 // Set up the node stack with NodeToMatch as the only node on the stack.
2188 SmallVector<SDValue, 8> NodeStack;
2189 SDValue N = SDValue(NodeToMatch, 0);
2190 NodeStack.push_back(N);
2192 // MatchScopes - Scopes used when matching, if a match failure happens, this
2193 // indicates where to continue checking.
2194 SmallVector<MatchScope, 8> MatchScopes;
2196 // RecordedNodes - This is the set of nodes that have been recorded by the
2197 // state machine. The second value is the parent of the node, or null if the
2198 // root is recorded.
2199 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2201 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2203 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2205 // These are the current input chain and glue for use when generating nodes.
2206 // Various Emit operations change these. For example, emitting a copytoreg
2207 // uses and updates these.
2208 SDValue InputChain, InputGlue;
2210 // ChainNodesMatched - If a pattern matches nodes that have input/output
2211 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2212 // which ones they are. The result is captured into this list so that we can
2213 // update the chain results when the pattern is complete.
2214 SmallVector<SDNode*, 3> ChainNodesMatched;
2215 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2217 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2218 NodeToMatch->dump(CurDAG);
2221 // Determine where to start the interpreter. Normally we start at opcode #0,
2222 // but if the state machine starts with an OPC_SwitchOpcode, then we
2223 // accelerate the first lookup (which is guaranteed to be hot) with the
2224 // OpcodeOffset table.
2225 unsigned MatcherIndex = 0;
2227 if (!OpcodeOffset.empty()) {
2228 // Already computed the OpcodeOffset table, just index into it.
2229 if (N.getOpcode() < OpcodeOffset.size())
2230 MatcherIndex = OpcodeOffset[N.getOpcode()];
2231 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2233 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2234 // Otherwise, the table isn't computed, but the state machine does start
2235 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2236 // is the first time we're selecting an instruction.
2239 // Get the size of this case.
2240 unsigned CaseSize = MatcherTable[Idx++];
2242 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2243 if (CaseSize == 0) break;
2245 // Get the opcode, add the index to the table.
2246 uint16_t Opc = MatcherTable[Idx++];
2247 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2248 if (Opc >= OpcodeOffset.size())
2249 OpcodeOffset.resize((Opc+1)*2);
2250 OpcodeOffset[Opc] = Idx;
2254 // Okay, do the lookup for the first opcode.
2255 if (N.getOpcode() < OpcodeOffset.size())
2256 MatcherIndex = OpcodeOffset[N.getOpcode()];
2260 assert(MatcherIndex < TableSize && "Invalid index");
2262 unsigned CurrentOpcodeIndex = MatcherIndex;
2264 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2267 // Okay, the semantics of this operation are that we should push a scope
2268 // then evaluate the first child. However, pushing a scope only to have
2269 // the first check fail (which then pops it) is inefficient. If we can
2270 // determine immediately that the first check (or first several) will
2271 // immediately fail, don't even bother pushing a scope for them.
2275 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2276 if (NumToSkip & 128)
2277 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2278 // Found the end of the scope with no match.
2279 if (NumToSkip == 0) {
2284 FailIndex = MatcherIndex+NumToSkip;
2286 unsigned MatcherIndexOfPredicate = MatcherIndex;
2287 (void)MatcherIndexOfPredicate; // silence warning.
2289 // If we can't evaluate this predicate without pushing a scope (e.g. if
2290 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2291 // push the scope and evaluate the full predicate chain.
2293 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2294 Result, *this, RecordedNodes);
2298 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2299 << "index " << MatcherIndexOfPredicate
2300 << ", continuing at " << FailIndex << "\n");
2301 ++NumDAGIselRetries;
2303 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2304 // move to the next case.
2305 MatcherIndex = FailIndex;
2308 // If the whole scope failed to match, bail.
2309 if (FailIndex == 0) break;
2311 // Push a MatchScope which indicates where to go if the first child fails
2313 MatchScope NewEntry;
2314 NewEntry.FailIndex = FailIndex;
2315 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2316 NewEntry.NumRecordedNodes = RecordedNodes.size();
2317 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2318 NewEntry.InputChain = InputChain;
2319 NewEntry.InputGlue = InputGlue;
2320 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2321 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2322 MatchScopes.push_back(NewEntry);
2325 case OPC_RecordNode: {
2326 // Remember this node, it may end up being an operand in the pattern.
2328 if (NodeStack.size() > 1)
2329 Parent = NodeStack[NodeStack.size()-2].getNode();
2330 RecordedNodes.push_back(std::make_pair(N, Parent));
2334 case OPC_RecordChild0: case OPC_RecordChild1:
2335 case OPC_RecordChild2: case OPC_RecordChild3:
2336 case OPC_RecordChild4: case OPC_RecordChild5:
2337 case OPC_RecordChild6: case OPC_RecordChild7: {
2338 unsigned ChildNo = Opcode-OPC_RecordChild0;
2339 if (ChildNo >= N.getNumOperands())
2340 break; // Match fails if out of range child #.
2342 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2346 case OPC_RecordMemRef:
2347 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2350 case OPC_CaptureGlueInput:
2351 // If the current node has an input glue, capture it in InputGlue.
2352 if (N->getNumOperands() != 0 &&
2353 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2354 InputGlue = N->getOperand(N->getNumOperands()-1);
2357 case OPC_MoveChild: {
2358 unsigned ChildNo = MatcherTable[MatcherIndex++];
2359 if (ChildNo >= N.getNumOperands())
2360 break; // Match fails if out of range child #.
2361 N = N.getOperand(ChildNo);
2362 NodeStack.push_back(N);
2366 case OPC_MoveParent:
2367 // Pop the current node off the NodeStack.
2368 NodeStack.pop_back();
2369 assert(!NodeStack.empty() && "Node stack imbalance!");
2370 N = NodeStack.back();
2374 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2376 case OPC_CheckPatternPredicate:
2377 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2379 case OPC_CheckPredicate:
2380 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2384 case OPC_CheckComplexPat: {
2385 unsigned CPNum = MatcherTable[MatcherIndex++];
2386 unsigned RecNo = MatcherTable[MatcherIndex++];
2387 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2388 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2389 RecordedNodes[RecNo].first, CPNum,
2394 case OPC_CheckOpcode:
2395 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2399 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2403 case OPC_SwitchOpcode: {
2404 unsigned CurNodeOpcode = N.getOpcode();
2405 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2408 // Get the size of this case.
2409 CaseSize = MatcherTable[MatcherIndex++];
2411 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2412 if (CaseSize == 0) break;
2414 uint16_t Opc = MatcherTable[MatcherIndex++];
2415 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2417 // If the opcode matches, then we will execute this case.
2418 if (CurNodeOpcode == Opc)
2421 // Otherwise, skip over this case.
2422 MatcherIndex += CaseSize;
2425 // If no cases matched, bail out.
2426 if (CaseSize == 0) break;
2428 // Otherwise, execute the case we found.
2429 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2430 << " to " << MatcherIndex << "\n");
2434 case OPC_SwitchType: {
2435 MVT CurNodeVT = N.getValueType().getSimpleVT();
2436 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2439 // Get the size of this case.
2440 CaseSize = MatcherTable[MatcherIndex++];
2442 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2443 if (CaseSize == 0) break;
2445 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2446 if (CaseVT == MVT::iPTR)
2447 CaseVT = getTargetLowering()->getPointerTy();
2449 // If the VT matches, then we will execute this case.
2450 if (CurNodeVT == CaseVT)
2453 // Otherwise, skip over this case.
2454 MatcherIndex += CaseSize;
2457 // If no cases matched, bail out.
2458 if (CaseSize == 0) break;
2460 // Otherwise, execute the case we found.
2461 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2462 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2465 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2466 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2467 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2468 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2469 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2470 Opcode-OPC_CheckChild0Type))
2473 case OPC_CheckCondCode:
2474 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2476 case OPC_CheckValueType:
2477 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2480 case OPC_CheckInteger:
2481 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2483 case OPC_CheckAndImm:
2484 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2486 case OPC_CheckOrImm:
2487 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2490 case OPC_CheckFoldableChainNode: {
2491 assert(NodeStack.size() != 1 && "No parent node");
2492 // Verify that all intermediate nodes between the root and this one have
2494 bool HasMultipleUses = false;
2495 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2496 if (!NodeStack[i].hasOneUse()) {
2497 HasMultipleUses = true;
2500 if (HasMultipleUses) break;
2502 // Check to see that the target thinks this is profitable to fold and that
2503 // we can fold it without inducing cycles in the graph.
2504 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2506 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2507 NodeToMatch, OptLevel,
2508 true/*We validate our own chains*/))
2513 case OPC_EmitInteger: {
2514 MVT::SimpleValueType VT =
2515 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2516 int64_t Val = MatcherTable[MatcherIndex++];
2518 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2519 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2520 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2523 case OPC_EmitRegister: {
2524 MVT::SimpleValueType VT =
2525 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2526 unsigned RegNo = MatcherTable[MatcherIndex++];
2527 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2528 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2531 case OPC_EmitRegister2: {
2532 // For targets w/ more than 256 register names, the register enum
2533 // values are stored in two bytes in the matcher table (just like
2535 MVT::SimpleValueType VT =
2536 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2537 unsigned RegNo = MatcherTable[MatcherIndex++];
2538 RegNo |= MatcherTable[MatcherIndex++] << 8;
2539 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2540 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2544 case OPC_EmitConvertToTarget: {
2545 // Convert from IMM/FPIMM to target version.
2546 unsigned RecNo = MatcherTable[MatcherIndex++];
2547 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2548 SDValue Imm = RecordedNodes[RecNo].first;
2550 if (Imm->getOpcode() == ISD::Constant) {
2551 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2552 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2553 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2554 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2555 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2558 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2562 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2563 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2564 // These are space-optimized forms of OPC_EmitMergeInputChains.
2565 assert(InputChain.getNode() == 0 &&
2566 "EmitMergeInputChains should be the first chain producing node");
2567 assert(ChainNodesMatched.empty() &&
2568 "Should only have one EmitMergeInputChains per match");
2570 // Read all of the chained nodes.
2571 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2572 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2573 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2575 // FIXME: What if other value results of the node have uses not matched
2577 if (ChainNodesMatched.back() != NodeToMatch &&
2578 !RecordedNodes[RecNo].first.hasOneUse()) {
2579 ChainNodesMatched.clear();
2583 // Merge the input chains if they are not intra-pattern references.
2584 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2586 if (InputChain.getNode() == 0)
2587 break; // Failed to merge.
2591 case OPC_EmitMergeInputChains: {
2592 assert(InputChain.getNode() == 0 &&
2593 "EmitMergeInputChains should be the first chain producing node");
2594 // This node gets a list of nodes we matched in the input that have
2595 // chains. We want to token factor all of the input chains to these nodes
2596 // together. However, if any of the input chains is actually one of the
2597 // nodes matched in this pattern, then we have an intra-match reference.
2598 // Ignore these because the newly token factored chain should not refer to
2600 unsigned NumChains = MatcherTable[MatcherIndex++];
2601 assert(NumChains != 0 && "Can't TF zero chains");
2603 assert(ChainNodesMatched.empty() &&
2604 "Should only have one EmitMergeInputChains per match");
2606 // Read all of the chained nodes.
2607 for (unsigned i = 0; i != NumChains; ++i) {
2608 unsigned RecNo = MatcherTable[MatcherIndex++];
2609 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2610 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2612 // FIXME: What if other value results of the node have uses not matched
2614 if (ChainNodesMatched.back() != NodeToMatch &&
2615 !RecordedNodes[RecNo].first.hasOneUse()) {
2616 ChainNodesMatched.clear();
2621 // If the inner loop broke out, the match fails.
2622 if (ChainNodesMatched.empty())
2625 // Merge the input chains if they are not intra-pattern references.
2626 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2628 if (InputChain.getNode() == 0)
2629 break; // Failed to merge.
2634 case OPC_EmitCopyToReg: {
2635 unsigned RecNo = MatcherTable[MatcherIndex++];
2636 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2637 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2639 if (InputChain.getNode() == 0)
2640 InputChain = CurDAG->getEntryNode();
2642 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2643 DestPhysReg, RecordedNodes[RecNo].first,
2646 InputGlue = InputChain.getValue(1);
2650 case OPC_EmitNodeXForm: {
2651 unsigned XFormNo = MatcherTable[MatcherIndex++];
2652 unsigned RecNo = MatcherTable[MatcherIndex++];
2653 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2654 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2655 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2660 case OPC_MorphNodeTo: {
2661 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2662 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2663 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2664 // Get the result VT list.
2665 unsigned NumVTs = MatcherTable[MatcherIndex++];
2666 SmallVector<EVT, 4> VTs;
2667 for (unsigned i = 0; i != NumVTs; ++i) {
2668 MVT::SimpleValueType VT =
2669 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2670 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2674 if (EmitNodeInfo & OPFL_Chain)
2675 VTs.push_back(MVT::Other);
2676 if (EmitNodeInfo & OPFL_GlueOutput)
2677 VTs.push_back(MVT::Glue);
2679 // This is hot code, so optimize the two most common cases of 1 and 2
2682 if (VTs.size() == 1)
2683 VTList = CurDAG->getVTList(VTs[0]);
2684 else if (VTs.size() == 2)
2685 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2687 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2689 // Get the operand list.
2690 unsigned NumOps = MatcherTable[MatcherIndex++];
2691 SmallVector<SDValue, 8> Ops;
2692 for (unsigned i = 0; i != NumOps; ++i) {
2693 unsigned RecNo = MatcherTable[MatcherIndex++];
2695 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2697 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2698 Ops.push_back(RecordedNodes[RecNo].first);
2701 // If there are variadic operands to add, handle them now.
2702 if (EmitNodeInfo & OPFL_VariadicInfo) {
2703 // Determine the start index to copy from.
2704 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2705 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2706 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2707 "Invalid variadic node");
2708 // Copy all of the variadic operands, not including a potential glue
2710 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2712 SDValue V = NodeToMatch->getOperand(i);
2713 if (V.getValueType() == MVT::Glue) break;
2718 // If this has chain/glue inputs, add them.
2719 if (EmitNodeInfo & OPFL_Chain)
2720 Ops.push_back(InputChain);
2721 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2722 Ops.push_back(InputGlue);
2726 if (Opcode != OPC_MorphNodeTo) {
2727 // If this is a normal EmitNode command, just create the new node and
2728 // add the results to the RecordedNodes list.
2729 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2732 // Add all the non-glue/non-chain results to the RecordedNodes list.
2733 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2734 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2735 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2739 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2740 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2743 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2744 // We will visit the equivalent node later.
2745 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2749 // If the node had chain/glue results, update our notion of the current
2751 if (EmitNodeInfo & OPFL_GlueOutput) {
2752 InputGlue = SDValue(Res, VTs.size()-1);
2753 if (EmitNodeInfo & OPFL_Chain)
2754 InputChain = SDValue(Res, VTs.size()-2);
2755 } else if (EmitNodeInfo & OPFL_Chain)
2756 InputChain = SDValue(Res, VTs.size()-1);
2758 // If the OPFL_MemRefs glue is set on this node, slap all of the
2759 // accumulated memrefs onto it.
2761 // FIXME: This is vastly incorrect for patterns with multiple outputs
2762 // instructions that access memory and for ComplexPatterns that match
2764 if (EmitNodeInfo & OPFL_MemRefs) {
2765 // Only attach load or store memory operands if the generated
2766 // instruction may load or store.
2767 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2768 bool mayLoad = MCID.mayLoad();
2769 bool mayStore = MCID.mayStore();
2771 unsigned NumMemRefs = 0;
2772 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2773 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2774 if ((*I)->isLoad()) {
2777 } else if ((*I)->isStore()) {
2785 MachineSDNode::mmo_iterator MemRefs =
2786 MF->allocateMemRefsArray(NumMemRefs);
2788 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2789 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2790 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2791 if ((*I)->isLoad()) {
2794 } else if ((*I)->isStore()) {
2802 cast<MachineSDNode>(Res)
2803 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2807 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2808 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
2810 // If this was a MorphNodeTo then we're completely done!
2811 if (Opcode == OPC_MorphNodeTo) {
2812 // Update chain and glue uses.
2813 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2814 InputGlue, GlueResultNodesMatched, true);
2821 case OPC_MarkGlueResults: {
2822 unsigned NumNodes = MatcherTable[MatcherIndex++];
2824 // Read and remember all the glue-result nodes.
2825 for (unsigned i = 0; i != NumNodes; ++i) {
2826 unsigned RecNo = MatcherTable[MatcherIndex++];
2828 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2830 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2831 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2836 case OPC_CompleteMatch: {
2837 // The match has been completed, and any new nodes (if any) have been
2838 // created. Patch up references to the matched dag to use the newly
2840 unsigned NumResults = MatcherTable[MatcherIndex++];
2842 for (unsigned i = 0; i != NumResults; ++i) {
2843 unsigned ResSlot = MatcherTable[MatcherIndex++];
2845 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2847 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2848 SDValue Res = RecordedNodes[ResSlot].first;
2850 assert(i < NodeToMatch->getNumValues() &&
2851 NodeToMatch->getValueType(i) != MVT::Other &&
2852 NodeToMatch->getValueType(i) != MVT::Glue &&
2853 "Invalid number of results to complete!");
2854 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2855 NodeToMatch->getValueType(i) == MVT::iPTR ||
2856 Res.getValueType() == MVT::iPTR ||
2857 NodeToMatch->getValueType(i).getSizeInBits() ==
2858 Res.getValueType().getSizeInBits()) &&
2859 "invalid replacement");
2860 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2863 // If the root node defines glue, add it to the glue nodes to update list.
2864 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2865 GlueResultNodesMatched.push_back(NodeToMatch);
2867 // Update chain and glue uses.
2868 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2869 InputGlue, GlueResultNodesMatched, false);
2871 assert(NodeToMatch->use_empty() &&
2872 "Didn't replace all uses of the node?");
2874 // FIXME: We just return here, which interacts correctly with SelectRoot
2875 // above. We should fix this to not return an SDNode* anymore.
2880 // If the code reached this point, then the match failed. See if there is
2881 // another child to try in the current 'Scope', otherwise pop it until we
2882 // find a case to check.
2883 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2884 ++NumDAGIselRetries;
2886 if (MatchScopes.empty()) {
2887 CannotYetSelect(NodeToMatch);
2891 // Restore the interpreter state back to the point where the scope was
2893 MatchScope &LastScope = MatchScopes.back();
2894 RecordedNodes.resize(LastScope.NumRecordedNodes);
2896 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2897 N = NodeStack.back();
2899 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2900 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2901 MatcherIndex = LastScope.FailIndex;
2903 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
2905 InputChain = LastScope.InputChain;
2906 InputGlue = LastScope.InputGlue;
2907 if (!LastScope.HasChainNodesMatched)
2908 ChainNodesMatched.clear();
2909 if (!LastScope.HasGlueResultNodesMatched)
2910 GlueResultNodesMatched.clear();
2912 // Check to see what the offset is at the new MatcherIndex. If it is zero
2913 // we have reached the end of this scope, otherwise we have another child
2914 // in the current scope to try.
2915 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2916 if (NumToSkip & 128)
2917 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2919 // If we have another child in this scope to match, update FailIndex and
2921 if (NumToSkip != 0) {
2922 LastScope.FailIndex = MatcherIndex+NumToSkip;
2926 // End of this scope, pop it and try the next child in the containing
2928 MatchScopes.pop_back();
2935 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2937 raw_string_ostream Msg(msg);
2938 Msg << "Cannot select: ";
2940 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2941 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2942 N->getOpcode() != ISD::INTRINSIC_VOID) {
2943 N->printrFull(Msg, CurDAG);
2944 Msg << "\nIn function: " << MF->getName();
2946 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2948 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2949 if (iid < Intrinsic::num_intrinsics)
2950 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2951 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2952 Msg << "target intrinsic %" << TII->getName(iid);
2954 Msg << "unknown intrinsic #" << iid;
2956 report_fatal_error(Msg.str());
2959 char SelectionDAGISel::ID = 0;