1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Constants.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/ParameterAttributes.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleDAG.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetData.h"
42 #include "llvm/Target/TargetFrameInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/Timer.h"
55 EnableValueProp("enable-value-prop", cl::Hidden);
57 EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
59 EnableFastISel("fast-isel", cl::Hidden,
60 cl::desc("Enable the experimental \"fast\" instruction selector"));
62 DisableFastISelAbort("fast-isel-no-abort", cl::Hidden,
63 cl::desc("Use the SelectionDAGISel when \"fast\" instruction "
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewISelDAGs("view-isel-dags", cl::Hidden,
83 cl::desc("Pop up a window to show isel dags as they are selected"));
85 ViewSchedDAGs("view-sched-dags", cl::Hidden,
86 cl::desc("Pop up a window to show sched dags as they are processed"));
88 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
89 cl::desc("Pop up a window to show SUnit dags after they are processed"));
91 static const bool ViewDAGCombine1 = false,
92 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
93 ViewDAGCombine2 = false,
94 ViewISelDAGs = false, ViewSchedDAGs = false,
95 ViewSUnitDAGs = false;
98 //===---------------------------------------------------------------------===//
100 /// RegisterScheduler class - Track the registration of instruction schedulers.
102 //===---------------------------------------------------------------------===//
103 MachinePassRegistry RegisterScheduler::Registry;
105 //===---------------------------------------------------------------------===//
107 /// ISHeuristic command line option for instruction schedulers.
109 //===---------------------------------------------------------------------===//
110 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
111 RegisterPassParser<RegisterScheduler> >
112 ISHeuristic("pre-RA-sched",
113 cl::init(&createDefaultScheduler),
114 cl::desc("Instruction schedulers available (before register"
117 static RegisterScheduler
118 defaultListDAGScheduler("default", " Best scheduler for the target",
119 createDefaultScheduler);
121 namespace { struct SDISelAsmOperandInfo; }
123 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
124 /// insertvalue or extractvalue indices that identify a member, return
125 /// the linearized index of the start of the member.
127 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
128 const unsigned *Indices,
129 const unsigned *IndicesEnd,
130 unsigned CurIndex = 0) {
131 // Base case: We're done.
132 if (Indices && Indices == IndicesEnd)
135 // Given a struct type, recursively traverse the elements.
136 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
137 for (StructType::element_iterator EB = STy->element_begin(),
139 EE = STy->element_end();
141 if (Indices && *Indices == unsigned(EI - EB))
142 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
143 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
146 // Given an array type, recursively traverse the elements.
147 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
148 const Type *EltTy = ATy->getElementType();
149 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
150 if (Indices && *Indices == i)
151 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
152 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
155 // We haven't found the type we're looking for, so keep searching.
159 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
160 /// MVTs that represent all the individual underlying
161 /// non-aggregate types that comprise it.
163 /// If Offsets is non-null, it points to a vector to be filled in
164 /// with the in-memory offsets of each of the individual values.
166 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
167 SmallVectorImpl<MVT> &ValueVTs,
168 SmallVectorImpl<uint64_t> *Offsets = 0,
169 uint64_t StartingOffset = 0) {
170 // Given a struct type, recursively traverse the elements.
171 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
172 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
173 for (StructType::element_iterator EB = STy->element_begin(),
175 EE = STy->element_end();
177 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
178 StartingOffset + SL->getElementOffset(EI - EB));
181 // Given an array type, recursively traverse the elements.
182 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
183 const Type *EltTy = ATy->getElementType();
184 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
185 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
186 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
187 StartingOffset + i * EltSize);
190 // Base case: we can get an MVT for this LLVM IR type.
191 ValueVTs.push_back(TLI.getValueType(Ty));
193 Offsets->push_back(StartingOffset);
197 /// RegsForValue - This struct represents the registers (physical or virtual)
198 /// that a particular set of values is assigned, and the type information about
199 /// the value. The most common situation is to represent one value at a time,
200 /// but struct or array values are handled element-wise as multiple values.
201 /// The splitting of aggregates is performed recursively, so that we never
202 /// have aggregate-typed registers. The values at this point do not necessarily
203 /// have legal types, so each value may require one or more registers of some
206 struct VISIBILITY_HIDDEN RegsForValue {
207 /// TLI - The TargetLowering object.
209 const TargetLowering *TLI;
211 /// ValueVTs - The value types of the values, which may not be legal, and
212 /// may need be promoted or synthesized from one or more registers.
214 SmallVector<MVT, 4> ValueVTs;
216 /// RegVTs - The value types of the registers. This is the same size as
217 /// ValueVTs and it records, for each value, what the type of the assigned
218 /// register or registers are. (Individual values are never synthesized
219 /// from more than one type of register.)
221 /// With virtual registers, the contents of RegVTs is redundant with TLI's
222 /// getRegisterType member function, however when with physical registers
223 /// it is necessary to have a separate record of the types.
225 SmallVector<MVT, 4> RegVTs;
227 /// Regs - This list holds the registers assigned to the values.
228 /// Each legal or promoted value requires one register, and each
229 /// expanded value requires multiple registers.
231 SmallVector<unsigned, 4> Regs;
233 RegsForValue() : TLI(0) {}
235 RegsForValue(const TargetLowering &tli,
236 const SmallVector<unsigned, 4> ®s,
237 MVT regvt, MVT valuevt)
238 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
239 RegsForValue(const TargetLowering &tli,
240 const SmallVector<unsigned, 4> ®s,
241 const SmallVector<MVT, 4> ®vts,
242 const SmallVector<MVT, 4> &valuevts)
243 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
244 RegsForValue(const TargetLowering &tli,
245 unsigned Reg, const Type *Ty) : TLI(&tli) {
246 ComputeValueVTs(tli, Ty, ValueVTs);
248 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
249 MVT ValueVT = ValueVTs[Value];
250 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
251 MVT RegisterVT = TLI->getRegisterType(ValueVT);
252 for (unsigned i = 0; i != NumRegs; ++i)
253 Regs.push_back(Reg + i);
254 RegVTs.push_back(RegisterVT);
259 /// append - Add the specified values to this one.
260 void append(const RegsForValue &RHS) {
262 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
263 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
264 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
268 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
269 /// this value and returns the result as a ValueVTs value. This uses
270 /// Chain/Flag as the input and updates them for the output Chain/Flag.
271 /// If the Flag pointer is NULL, no flag is used.
272 SDValue getCopyFromRegs(SelectionDAG &DAG,
273 SDValue &Chain, SDValue *Flag) const;
275 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
276 /// specified value into the registers specified by this object. This uses
277 /// Chain/Flag as the input and updates them for the output Chain/Flag.
278 /// If the Flag pointer is NULL, no flag is used.
279 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
280 SDValue &Chain, SDValue *Flag) const;
282 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
283 /// operand list. This adds the code marker and includes the number of
284 /// values added into it.
285 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
286 std::vector<SDValue> &Ops) const;
291 //===--------------------------------------------------------------------===//
292 /// createDefaultScheduler - This creates an instruction scheduler appropriate
294 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
296 MachineBasicBlock *BB,
298 TargetLowering &TLI = IS->getTargetLowering();
300 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
301 return createTDListDAGScheduler(IS, DAG, BB, Fast);
303 assert(TLI.getSchedulingPreference() ==
304 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
305 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
310 //===--------------------------------------------------------------------===//
311 /// FunctionLoweringInfo - This contains information that is global to a
312 /// function that is used when lowering a region of the function.
313 class FunctionLoweringInfo {
318 MachineRegisterInfo &RegInfo;
320 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
322 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
323 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
325 /// ValueMap - Since we emit code for the function a basic block at a time,
326 /// we must remember which virtual registers hold the values for
327 /// cross-basic-block values.
328 DenseMap<const Value*, unsigned> ValueMap;
330 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
331 /// the entry block. This allows the allocas to be efficiently referenced
332 /// anywhere in the function.
333 std::map<const AllocaInst*, int> StaticAllocaMap;
336 SmallSet<Instruction*, 8> CatchInfoLost;
337 SmallSet<Instruction*, 8> CatchInfoFound;
340 unsigned MakeReg(MVT VT) {
341 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
344 /// isExportedInst - Return true if the specified value is an instruction
345 /// exported from its block.
346 bool isExportedInst(const Value *V) {
347 return ValueMap.count(V);
350 unsigned CreateRegForValue(const Value *V);
352 unsigned InitializeRegForValue(const Value *V) {
353 unsigned &R = ValueMap[V];
354 assert(R == 0 && "Already initialized this value register!");
355 return R = CreateRegForValue(V);
359 unsigned NumSignBits;
360 APInt KnownOne, KnownZero;
361 LiveOutInfo() : NumSignBits(0) {}
364 /// LiveOutRegInfo - Information about live out vregs, indexed by their
365 /// register number offset by 'FirstVirtualRegister'.
366 std::vector<LiveOutInfo> LiveOutRegInfo;
370 /// isSelector - Return true if this instruction is a call to the
371 /// eh.selector intrinsic.
372 static bool isSelector(Instruction *I) {
373 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
374 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
375 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
379 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
380 /// PHI nodes or outside of the basic block that defines it, or used by a
381 /// switch or atomic instruction, which may expand to multiple basic blocks.
382 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
383 if (isa<PHINode>(I)) return true;
384 BasicBlock *BB = I->getParent();
385 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
386 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
387 // FIXME: Remove switchinst special case.
388 isa<SwitchInst>(*UI))
393 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
394 /// entry block, return true. This includes arguments used by switches, since
395 /// the switch may expand into multiple basic blocks.
396 static bool isOnlyUsedInEntryBlock(Argument *A) {
397 BasicBlock *Entry = A->getParent()->begin();
398 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
399 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
400 return false; // Use not in entry block.
404 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
405 Function &fn, MachineFunction &mf)
406 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
408 // Create a vreg for each argument register that is not dead and is used
409 // outside of the entry block for the function.
410 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
412 if (!isOnlyUsedInEntryBlock(AI))
413 InitializeRegForValue(AI);
415 // Initialize the mapping of values to registers. This is only set up for
416 // instruction values that are used outside of the block that defines
418 Function::iterator BB = Fn.begin(), EB = Fn.end();
419 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
420 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
421 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
422 const Type *Ty = AI->getAllocatedType();
423 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
425 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
428 TySize *= CUI->getZExtValue(); // Get total allocated size.
429 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
430 StaticAllocaMap[AI] =
431 MF.getFrameInfo()->CreateStackObject(TySize, Align);
434 for (; BB != EB; ++BB)
435 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
436 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
437 if (!isa<AllocaInst>(I) ||
438 !StaticAllocaMap.count(cast<AllocaInst>(I)))
439 InitializeRegForValue(I);
441 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
442 // also creates the initial PHI MachineInstrs, though none of the input
443 // operands are populated.
444 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
445 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
449 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
452 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
453 if (PN->use_empty()) continue;
455 unsigned PHIReg = ValueMap[PN];
456 assert(PHIReg && "PHI node does not have an assigned virtual register!");
458 SmallVector<MVT, 4> ValueVTs;
459 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
460 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
461 MVT VT = ValueVTs[vti];
462 unsigned NumRegisters = TLI.getNumRegisters(VT);
463 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
464 for (unsigned i = 0; i != NumRegisters; ++i)
465 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
466 PHIReg += NumRegisters;
472 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
473 /// the correctly promoted or expanded types. Assign these registers
474 /// consecutive vreg numbers and return the first assigned number.
476 /// In the case that the given value has struct or array type, this function
477 /// will assign registers for each member or element.
479 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
480 SmallVector<MVT, 4> ValueVTs;
481 ComputeValueVTs(TLI, V->getType(), ValueVTs);
483 unsigned FirstReg = 0;
484 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
485 MVT ValueVT = ValueVTs[Value];
486 MVT RegisterVT = TLI.getRegisterType(ValueVT);
488 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
489 for (unsigned i = 0; i != NumRegs; ++i) {
490 unsigned R = MakeReg(RegisterVT);
491 if (!FirstReg) FirstReg = R;
497 //===----------------------------------------------------------------------===//
498 /// SelectionDAGLowering - This is the common target-independent lowering
499 /// implementation that is parameterized by a TargetLowering object.
500 /// Also, targets can overload any lowering method.
503 class SelectionDAGLowering {
504 MachineBasicBlock *CurMBB;
506 DenseMap<const Value*, SDValue> NodeMap;
508 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
509 /// them up and then emit token factor nodes when possible. This allows us to
510 /// get simple disambiguation between loads without worrying about alias
512 SmallVector<SDValue, 8> PendingLoads;
514 /// PendingExports - CopyToReg nodes that copy values to virtual registers
515 /// for export to other blocks need to be emitted before any terminator
516 /// instruction, but they have no other ordering requirements. We bunch them
517 /// up and the emit a single tokenfactor for them just before terminator
519 std::vector<SDValue> PendingExports;
521 /// Case - A struct to record the Value for a switch case, and the
522 /// case's target basic block.
526 MachineBasicBlock* BB;
528 Case() : Low(0), High(0), BB(0) { }
529 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
530 Low(low), High(high), BB(bb) { }
531 uint64_t size() const {
532 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
533 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
534 return (rHigh - rLow + 1ULL);
540 MachineBasicBlock* BB;
543 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
544 Mask(mask), BB(bb), Bits(bits) { }
547 typedef std::vector<Case> CaseVector;
548 typedef std::vector<CaseBits> CaseBitsVector;
549 typedef CaseVector::iterator CaseItr;
550 typedef std::pair<CaseItr, CaseItr> CaseRange;
552 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
553 /// of conditional branches.
555 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
556 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
558 /// CaseBB - The MBB in which to emit the compare and branch
559 MachineBasicBlock *CaseBB;
560 /// LT, GE - If nonzero, we know the current case value must be less-than or
561 /// greater-than-or-equal-to these Constants.
564 /// Range - A pair of iterators representing the range of case values to be
565 /// processed at this point in the binary search tree.
569 typedef std::vector<CaseRec> CaseRecVector;
571 /// The comparison function for sorting the switch case values in the vector.
572 /// WARNING: Case ranges should be disjoint!
574 bool operator () (const Case& C1, const Case& C2) {
575 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
576 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
577 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
578 return CI1->getValue().slt(CI2->getValue());
583 bool operator () (const CaseBits& C1, const CaseBits& C2) {
584 return C1.Bits > C2.Bits;
588 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
591 // TLI - This is information that describes the available target features we
592 // need for lowering. This indicates when operations are unavailable,
593 // implemented with a libcall, etc.
596 const TargetData *TD;
599 /// SwitchCases - Vector of CaseBlock structures used to communicate
600 /// SwitchInst code generation information.
601 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
602 /// JTCases - Vector of JumpTable structures used to communicate
603 /// SwitchInst code generation information.
604 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
605 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
607 /// FuncInfo - Information about the function as a whole.
609 FunctionLoweringInfo &FuncInfo;
611 /// GFI - Garbage collection metadata for the function.
614 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
616 FunctionLoweringInfo &funcinfo,
618 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
619 FuncInfo(funcinfo), GFI(gfi) {
622 /// getRoot - Return the current virtual root of the Selection DAG,
623 /// flushing any PendingLoad items. This must be done before emitting
624 /// a store or any other node that may need to be ordered after any
625 /// prior load instructions.
628 if (PendingLoads.empty())
629 return DAG.getRoot();
631 if (PendingLoads.size() == 1) {
632 SDValue Root = PendingLoads[0];
634 PendingLoads.clear();
638 // Otherwise, we have to make a token factor node.
639 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
640 &PendingLoads[0], PendingLoads.size());
641 PendingLoads.clear();
646 /// getControlRoot - Similar to getRoot, but instead of flushing all the
647 /// PendingLoad items, flush all the PendingExports items. It is necessary
648 /// to do this before emitting a terminator instruction.
650 SDValue getControlRoot() {
651 SDValue Root = DAG.getRoot();
653 if (PendingExports.empty())
656 // Turn all of the CopyToReg chains into one factored node.
657 if (Root.getOpcode() != ISD::EntryToken) {
658 unsigned i = 0, e = PendingExports.size();
659 for (; i != e; ++i) {
660 assert(PendingExports[i].Val->getNumOperands() > 1);
661 if (PendingExports[i].Val->getOperand(0) == Root)
662 break; // Don't add the root if we already indirectly depend on it.
666 PendingExports.push_back(Root);
669 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
671 PendingExports.size());
672 PendingExports.clear();
677 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
679 void visit(Instruction &I) { visit(I.getOpcode(), I); }
681 void visit(unsigned Opcode, User &I) {
682 // Note: this doesn't use InstVisitor, because it has to work with
683 // ConstantExpr's in addition to instructions.
685 default: assert(0 && "Unknown instruction type encountered!");
687 // Build the switch statement using the Instruction.def file.
688 #define HANDLE_INST(NUM, OPCODE, CLASS) \
689 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
690 #include "llvm/Instruction.def"
694 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
696 SDValue getValue(const Value *V);
698 void setValue(const Value *V, SDValue NewN) {
699 SDValue &N = NodeMap[V];
700 assert(N.Val == 0 && "Already set a value for this node!");
704 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
705 std::set<unsigned> &OutputRegs,
706 std::set<unsigned> &InputRegs);
708 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
709 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
711 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
712 void ExportFromCurrentBlock(Value *V);
713 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
714 MachineBasicBlock *LandingPad = NULL);
716 // Terminator instructions.
717 void visitRet(ReturnInst &I);
718 void visitBr(BranchInst &I);
719 void visitSwitch(SwitchInst &I);
720 void visitUnreachable(UnreachableInst &I) { /* noop */ }
722 // Helpers for visitSwitch
723 bool handleSmallSwitchRange(CaseRec& CR,
724 CaseRecVector& WorkList,
726 MachineBasicBlock* Default);
727 bool handleJTSwitchCase(CaseRec& CR,
728 CaseRecVector& WorkList,
730 MachineBasicBlock* Default);
731 bool handleBTSplitSwitchCase(CaseRec& CR,
732 CaseRecVector& WorkList,
734 MachineBasicBlock* Default);
735 bool handleBitTestsSwitchCase(CaseRec& CR,
736 CaseRecVector& WorkList,
738 MachineBasicBlock* Default);
739 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
740 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
741 void visitBitTestCase(MachineBasicBlock* NextMBB,
743 SelectionDAGISel::BitTestCase &B);
744 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
745 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
746 SelectionDAGISel::JumpTableHeader &JTH);
748 // These all get lowered before this pass.
749 void visitInvoke(InvokeInst &I);
750 void visitUnwind(UnwindInst &I);
752 void visitBinary(User &I, unsigned OpCode);
753 void visitShift(User &I, unsigned Opcode);
754 void visitAdd(User &I) {
755 if (I.getType()->isFPOrFPVector())
756 visitBinary(I, ISD::FADD);
758 visitBinary(I, ISD::ADD);
760 void visitSub(User &I);
761 void visitMul(User &I) {
762 if (I.getType()->isFPOrFPVector())
763 visitBinary(I, ISD::FMUL);
765 visitBinary(I, ISD::MUL);
767 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
768 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
769 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
770 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
771 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
772 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
773 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
774 void visitOr (User &I) { visitBinary(I, ISD::OR); }
775 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
776 void visitShl (User &I) { visitShift(I, ISD::SHL); }
777 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
778 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
779 void visitICmp(User &I);
780 void visitFCmp(User &I);
781 void visitVICmp(User &I);
782 void visitVFCmp(User &I);
783 // Visit the conversion instructions
784 void visitTrunc(User &I);
785 void visitZExt(User &I);
786 void visitSExt(User &I);
787 void visitFPTrunc(User &I);
788 void visitFPExt(User &I);
789 void visitFPToUI(User &I);
790 void visitFPToSI(User &I);
791 void visitUIToFP(User &I);
792 void visitSIToFP(User &I);
793 void visitPtrToInt(User &I);
794 void visitIntToPtr(User &I);
795 void visitBitCast(User &I);
797 void visitExtractElement(User &I);
798 void visitInsertElement(User &I);
799 void visitShuffleVector(User &I);
801 void visitExtractValue(ExtractValueInst &I);
802 void visitInsertValue(InsertValueInst &I);
804 void visitGetElementPtr(User &I);
805 void visitSelect(User &I);
807 void visitMalloc(MallocInst &I);
808 void visitFree(FreeInst &I);
809 void visitAlloca(AllocaInst &I);
810 void visitLoad(LoadInst &I);
811 void visitStore(StoreInst &I);
812 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
813 void visitCall(CallInst &I);
814 void visitInlineAsm(CallSite CS);
815 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
816 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
818 void visitVAStart(CallInst &I);
819 void visitVAArg(VAArgInst &I);
820 void visitVAEnd(CallInst &I);
821 void visitVACopy(CallInst &I);
823 void visitUserOp1(Instruction &I) {
824 assert(0 && "UserOp1 should not exist at instruction selection time!");
827 void visitUserOp2(Instruction &I) {
828 assert(0 && "UserOp2 should not exist at instruction selection time!");
833 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
836 } // end namespace llvm
839 /// getCopyFromParts - Create a value that contains the specified legal parts
840 /// combined into the value they represent. If the parts combine to a type
841 /// larger then ValueVT then AssertOp can be used to specify whether the extra
842 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
843 /// (ISD::AssertSext).
844 static SDValue getCopyFromParts(SelectionDAG &DAG,
845 const SDValue *Parts,
849 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
850 assert(NumParts > 0 && "No parts to assemble!");
851 TargetLowering &TLI = DAG.getTargetLoweringInfo();
852 SDValue Val = Parts[0];
855 // Assemble the value from multiple parts.
856 if (!ValueVT.isVector()) {
857 unsigned PartBits = PartVT.getSizeInBits();
858 unsigned ValueBits = ValueVT.getSizeInBits();
860 // Assemble the power of 2 part.
861 unsigned RoundParts = NumParts & (NumParts - 1) ?
862 1 << Log2_32(NumParts) : NumParts;
863 unsigned RoundBits = PartBits * RoundParts;
864 MVT RoundVT = RoundBits == ValueBits ?
865 ValueVT : MVT::getIntegerVT(RoundBits);
868 if (RoundParts > 2) {
869 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
870 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
871 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
877 if (TLI.isBigEndian())
879 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
881 if (RoundParts < NumParts) {
882 // Assemble the trailing non-power-of-2 part.
883 unsigned OddParts = NumParts - RoundParts;
884 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
885 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
887 // Combine the round and odd parts.
889 if (TLI.isBigEndian())
891 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
892 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
893 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
894 DAG.getConstant(Lo.getValueType().getSizeInBits(),
895 TLI.getShiftAmountTy()));
896 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
897 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
900 // Handle a multi-element vector.
901 MVT IntermediateVT, RegisterVT;
902 unsigned NumIntermediates;
904 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
906 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
907 NumParts = NumRegs; // Silence a compiler warning.
908 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
909 assert(RegisterVT == Parts[0].getValueType() &&
910 "Part type doesn't match part!");
912 // Assemble the parts into intermediate operands.
913 SmallVector<SDValue, 8> Ops(NumIntermediates);
914 if (NumIntermediates == NumParts) {
915 // If the register was not expanded, truncate or copy the value,
917 for (unsigned i = 0; i != NumParts; ++i)
918 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
919 PartVT, IntermediateVT);
920 } else if (NumParts > 0) {
921 // If the intermediate type was expanded, build the intermediate operands
923 assert(NumParts % NumIntermediates == 0 &&
924 "Must expand into a divisible number of parts!");
925 unsigned Factor = NumParts / NumIntermediates;
926 for (unsigned i = 0; i != NumIntermediates; ++i)
927 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
928 PartVT, IntermediateVT);
931 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
933 Val = DAG.getNode(IntermediateVT.isVector() ?
934 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
935 ValueVT, &Ops[0], NumIntermediates);
939 // There is now one part, held in Val. Correct it to match ValueVT.
940 PartVT = Val.getValueType();
942 if (PartVT == ValueVT)
945 if (PartVT.isVector()) {
946 assert(ValueVT.isVector() && "Unknown vector conversion!");
947 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
950 if (ValueVT.isVector()) {
951 assert(ValueVT.getVectorElementType() == PartVT &&
952 ValueVT.getVectorNumElements() == 1 &&
953 "Only trivial scalar-to-vector conversions should get here!");
954 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
957 if (PartVT.isInteger() &&
958 ValueVT.isInteger()) {
959 if (ValueVT.bitsLT(PartVT)) {
960 // For a truncate, see if we have any information to
961 // indicate whether the truncated bits will always be
962 // zero or sign-extension.
963 if (AssertOp != ISD::DELETED_NODE)
964 Val = DAG.getNode(AssertOp, PartVT, Val,
965 DAG.getValueType(ValueVT));
966 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
968 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
972 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
973 if (ValueVT.bitsLT(Val.getValueType()))
974 // FP_ROUND's are always exact here.
975 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
976 DAG.getIntPtrConstant(1));
977 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
980 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
981 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
983 assert(0 && "Unknown mismatch!");
987 /// getCopyToParts - Create a series of nodes that contain the specified value
988 /// split into legal parts. If the parts contain more bits than Val, then, for
989 /// integers, ExtendKind can be used to specify how to generate the extra bits.
990 static void getCopyToParts(SelectionDAG &DAG,
995 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
996 TargetLowering &TLI = DAG.getTargetLoweringInfo();
997 MVT PtrVT = TLI.getPointerTy();
998 MVT ValueVT = Val.getValueType();
999 unsigned PartBits = PartVT.getSizeInBits();
1000 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
1005 if (!ValueVT.isVector()) {
1006 if (PartVT == ValueVT) {
1007 assert(NumParts == 1 && "No-op copy with multiple parts!");
1012 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
1013 // If the parts cover more bits than the value has, promote the value.
1014 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
1015 assert(NumParts == 1 && "Do not know what to promote to!");
1016 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
1017 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
1018 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1019 Val = DAG.getNode(ExtendKind, ValueVT, Val);
1021 assert(0 && "Unknown mismatch!");
1023 } else if (PartBits == ValueVT.getSizeInBits()) {
1024 // Different types of the same size.
1025 assert(NumParts == 1 && PartVT != ValueVT);
1026 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1027 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
1028 // If the parts cover less bits than value has, truncate the value.
1029 if (PartVT.isInteger() && ValueVT.isInteger()) {
1030 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1031 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1033 assert(0 && "Unknown mismatch!");
1037 // The value may have changed - recompute ValueVT.
1038 ValueVT = Val.getValueType();
1039 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1040 "Failed to tile the value with PartVT!");
1042 if (NumParts == 1) {
1043 assert(PartVT == ValueVT && "Type conversion failed!");
1048 // Expand the value into multiple parts.
1049 if (NumParts & (NumParts - 1)) {
1050 // The number of parts is not a power of 2. Split off and copy the tail.
1051 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1052 "Do not know what to expand to!");
1053 unsigned RoundParts = 1 << Log2_32(NumParts);
1054 unsigned RoundBits = RoundParts * PartBits;
1055 unsigned OddParts = NumParts - RoundParts;
1056 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1057 DAG.getConstant(RoundBits,
1058 TLI.getShiftAmountTy()));
1059 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1060 if (TLI.isBigEndian())
1061 // The odd parts were reversed by getCopyToParts - unreverse them.
1062 std::reverse(Parts + RoundParts, Parts + NumParts);
1063 NumParts = RoundParts;
1064 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1065 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1068 // The number of parts is a power of 2. Repeatedly bisect the value using
1070 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1071 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1073 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1074 for (unsigned i = 0; i < NumParts; i += StepSize) {
1075 unsigned ThisBits = StepSize * PartBits / 2;
1076 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1077 SDValue &Part0 = Parts[i];
1078 SDValue &Part1 = Parts[i+StepSize/2];
1080 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1081 DAG.getConstant(1, PtrVT));
1082 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1083 DAG.getConstant(0, PtrVT));
1085 if (ThisBits == PartBits && ThisVT != PartVT) {
1086 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1087 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1092 if (TLI.isBigEndian())
1093 std::reverse(Parts, Parts + NumParts);
1099 if (NumParts == 1) {
1100 if (PartVT != ValueVT) {
1101 if (PartVT.isVector()) {
1102 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1104 assert(ValueVT.getVectorElementType() == PartVT &&
1105 ValueVT.getVectorNumElements() == 1 &&
1106 "Only trivial vector-to-scalar conversions should get here!");
1107 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1108 DAG.getConstant(0, PtrVT));
1116 // Handle a multi-element vector.
1117 MVT IntermediateVT, RegisterVT;
1118 unsigned NumIntermediates;
1120 DAG.getTargetLoweringInfo()
1121 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1123 unsigned NumElements = ValueVT.getVectorNumElements();
1125 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1126 NumParts = NumRegs; // Silence a compiler warning.
1127 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1129 // Split the vector into intermediate operands.
1130 SmallVector<SDValue, 8> Ops(NumIntermediates);
1131 for (unsigned i = 0; i != NumIntermediates; ++i)
1132 if (IntermediateVT.isVector())
1133 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1134 IntermediateVT, Val,
1135 DAG.getConstant(i * (NumElements / NumIntermediates),
1138 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1139 IntermediateVT, Val,
1140 DAG.getConstant(i, PtrVT));
1142 // Split the intermediate operands into legal parts.
1143 if (NumParts == NumIntermediates) {
1144 // If the register was not expanded, promote or copy the value,
1146 for (unsigned i = 0; i != NumParts; ++i)
1147 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1148 } else if (NumParts > 0) {
1149 // If the intermediate type was expanded, split each the value into
1151 assert(NumParts % NumIntermediates == 0 &&
1152 "Must expand into a divisible number of parts!");
1153 unsigned Factor = NumParts / NumIntermediates;
1154 for (unsigned i = 0; i != NumIntermediates; ++i)
1155 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1160 SDValue SelectionDAGLowering::getValue(const Value *V) {
1161 SDValue &N = NodeMap[V];
1162 if (N.Val) return N;
1164 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1165 MVT VT = TLI.getValueType(V->getType(), true);
1167 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1168 return N = DAG.getConstant(CI->getValue(), VT);
1170 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1171 return N = DAG.getGlobalAddress(GV, VT);
1173 if (isa<ConstantPointerNull>(C))
1174 return N = DAG.getConstant(0, TLI.getPointerTy());
1176 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1177 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1179 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1180 !V->getType()->isAggregateType())
1181 return N = DAG.getNode(ISD::UNDEF, VT);
1183 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1184 visit(CE->getOpcode(), *CE);
1185 SDValue N1 = NodeMap[V];
1186 assert(N1.Val && "visit didn't populate the ValueMap!");
1190 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1191 SmallVector<SDValue, 4> Constants;
1192 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1194 SDNode *Val = getValue(*OI).Val;
1195 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1196 Constants.push_back(SDValue(Val, i));
1198 return DAG.getMergeValues(&Constants[0], Constants.size());
1201 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
1202 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1203 "Unknown struct or array constant!");
1205 SmallVector<MVT, 4> ValueVTs;
1206 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1207 unsigned NumElts = ValueVTs.size();
1209 return SDValue(); // empty struct
1210 SmallVector<SDValue, 4> Constants(NumElts);
1211 for (unsigned i = 0; i != NumElts; ++i) {
1212 MVT EltVT = ValueVTs[i];
1213 if (isa<UndefValue>(C))
1214 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1215 else if (EltVT.isFloatingPoint())
1216 Constants[i] = DAG.getConstantFP(0, EltVT);
1218 Constants[i] = DAG.getConstant(0, EltVT);
1220 return DAG.getMergeValues(&Constants[0], NumElts);
1223 const VectorType *VecTy = cast<VectorType>(V->getType());
1224 unsigned NumElements = VecTy->getNumElements();
1226 // Now that we know the number and type of the elements, get that number of
1227 // elements into the Ops array based on what kind of constant it is.
1228 SmallVector<SDValue, 16> Ops;
1229 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1230 for (unsigned i = 0; i != NumElements; ++i)
1231 Ops.push_back(getValue(CP->getOperand(i)));
1233 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1234 "Unknown vector constant!");
1235 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1238 if (isa<UndefValue>(C))
1239 Op = DAG.getNode(ISD::UNDEF, EltVT);
1240 else if (EltVT.isFloatingPoint())
1241 Op = DAG.getConstantFP(0, EltVT);
1243 Op = DAG.getConstant(0, EltVT);
1244 Ops.assign(NumElements, Op);
1247 // Create a BUILD_VECTOR node.
1248 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1251 // If this is a static alloca, generate it as the frameindex instead of
1253 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1254 std::map<const AllocaInst*, int>::iterator SI =
1255 FuncInfo.StaticAllocaMap.find(AI);
1256 if (SI != FuncInfo.StaticAllocaMap.end())
1257 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1260 unsigned InReg = FuncInfo.ValueMap[V];
1261 assert(InReg && "Value not in map!");
1263 RegsForValue RFV(TLI, InReg, V->getType());
1264 SDValue Chain = DAG.getEntryNode();
1265 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1269 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1270 if (I.getNumOperands() == 0) {
1271 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1275 SmallVector<SDValue, 8> NewValues;
1276 NewValues.push_back(getControlRoot());
1277 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1278 SDValue RetOp = getValue(I.getOperand(i));
1280 SmallVector<MVT, 4> ValueVTs;
1281 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1282 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1283 MVT VT = ValueVTs[j];
1285 // FIXME: C calling convention requires the return type to be promoted to
1286 // at least 32-bit. But this is not necessary for non-C calling conventions.
1287 if (VT.isInteger()) {
1288 MVT MinVT = TLI.getRegisterType(MVT::i32);
1289 if (VT.bitsLT(MinVT))
1293 unsigned NumParts = TLI.getNumRegisters(VT);
1294 MVT PartVT = TLI.getRegisterType(VT);
1295 SmallVector<SDValue, 4> Parts(NumParts);
1296 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1298 const Function *F = I.getParent()->getParent();
1299 if (F->paramHasAttr(0, ParamAttr::SExt))
1300 ExtendKind = ISD::SIGN_EXTEND;
1301 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1302 ExtendKind = ISD::ZERO_EXTEND;
1304 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
1305 &Parts[0], NumParts, PartVT, ExtendKind);
1307 for (unsigned i = 0; i < NumParts; ++i) {
1308 NewValues.push_back(Parts[i]);
1309 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1313 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1314 &NewValues[0], NewValues.size()));
1317 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1318 /// the current basic block, add it to ValueMap now so that we'll get a
1320 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1321 // No need to export constants.
1322 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1324 // Already exported?
1325 if (FuncInfo.isExportedInst(V)) return;
1327 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1328 CopyValueToVirtualRegister(V, Reg);
1331 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1332 const BasicBlock *FromBB) {
1333 // The operands of the setcc have to be in this block. We don't know
1334 // how to export them from some other block.
1335 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1336 // Can export from current BB.
1337 if (VI->getParent() == FromBB)
1340 // Is already exported, noop.
1341 return FuncInfo.isExportedInst(V);
1344 // If this is an argument, we can export it if the BB is the entry block or
1345 // if it is already exported.
1346 if (isa<Argument>(V)) {
1347 if (FromBB == &FromBB->getParent()->getEntryBlock())
1350 // Otherwise, can only export this if it is already exported.
1351 return FuncInfo.isExportedInst(V);
1354 // Otherwise, constants can always be exported.
1358 static bool InBlock(const Value *V, const BasicBlock *BB) {
1359 if (const Instruction *I = dyn_cast<Instruction>(V))
1360 return I->getParent() == BB;
1364 /// FindMergedConditions - If Cond is an expression like
1365 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1366 MachineBasicBlock *TBB,
1367 MachineBasicBlock *FBB,
1368 MachineBasicBlock *CurBB,
1370 // If this node is not part of the or/and tree, emit it as a branch.
1371 Instruction *BOp = dyn_cast<Instruction>(Cond);
1373 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1374 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1375 BOp->getParent() != CurBB->getBasicBlock() ||
1376 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1377 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1378 const BasicBlock *BB = CurBB->getBasicBlock();
1380 // If the leaf of the tree is a comparison, merge the condition into
1382 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1383 // The operands of the cmp have to be in this block. We don't know
1384 // how to export them from some other block. If this is the first block
1385 // of the sequence, no exporting is needed.
1387 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1388 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1389 BOp = cast<Instruction>(Cond);
1390 ISD::CondCode Condition;
1391 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1392 switch (IC->getPredicate()) {
1393 default: assert(0 && "Unknown icmp predicate opcode!");
1394 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1395 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1396 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1397 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1398 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1399 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1400 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1401 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1402 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1403 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1405 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1406 ISD::CondCode FPC, FOC;
1407 switch (FC->getPredicate()) {
1408 default: assert(0 && "Unknown fcmp predicate opcode!");
1409 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1410 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1411 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1412 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1413 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1414 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1415 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1416 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1417 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1418 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1419 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1420 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1421 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1422 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1423 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1424 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1426 if (FiniteOnlyFPMath())
1431 Condition = ISD::SETEQ; // silence warning.
1432 assert(0 && "Unknown compare instruction");
1435 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1436 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1437 SwitchCases.push_back(CB);
1441 // Create a CaseBlock record representing this branch.
1442 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1443 NULL, TBB, FBB, CurBB);
1444 SwitchCases.push_back(CB);
1449 // Create TmpBB after CurBB.
1450 MachineFunction::iterator BBI = CurBB;
1451 MachineFunction &MF = DAG.getMachineFunction();
1452 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1453 CurBB->getParent()->insert(++BBI, TmpBB);
1455 if (Opc == Instruction::Or) {
1456 // Codegen X | Y as:
1464 // Emit the LHS condition.
1465 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1467 // Emit the RHS condition into TmpBB.
1468 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1470 assert(Opc == Instruction::And && "Unknown merge op!");
1471 // Codegen X & Y as:
1478 // This requires creation of TmpBB after CurBB.
1480 // Emit the LHS condition.
1481 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1483 // Emit the RHS condition into TmpBB.
1484 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1488 /// If the set of cases should be emitted as a series of branches, return true.
1489 /// If we should emit this as a bunch of and/or'd together conditions, return
1492 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1493 if (Cases.size() != 2) return true;
1495 // If this is two comparisons of the same values or'd or and'd together, they
1496 // will get folded into a single comparison, so don't emit two blocks.
1497 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1498 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1499 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1500 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1507 void SelectionDAGLowering::visitBr(BranchInst &I) {
1508 // Update machine-CFG edges.
1509 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1511 // Figure out which block is immediately after the current one.
1512 MachineBasicBlock *NextBlock = 0;
1513 MachineFunction::iterator BBI = CurMBB;
1514 if (++BBI != CurMBB->getParent()->end())
1517 if (I.isUnconditional()) {
1518 // Update machine-CFG edges.
1519 CurMBB->addSuccessor(Succ0MBB);
1521 // If this is not a fall-through branch, emit the branch.
1522 if (Succ0MBB != NextBlock)
1523 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1524 DAG.getBasicBlock(Succ0MBB)));
1528 // If this condition is one of the special cases we handle, do special stuff
1530 Value *CondVal = I.getCondition();
1531 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1533 // If this is a series of conditions that are or'd or and'd together, emit
1534 // this as a sequence of branches instead of setcc's with and/or operations.
1535 // For example, instead of something like:
1548 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1549 if (BOp->hasOneUse() &&
1550 (BOp->getOpcode() == Instruction::And ||
1551 BOp->getOpcode() == Instruction::Or)) {
1552 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1553 // If the compares in later blocks need to use values not currently
1554 // exported from this block, export them now. This block should always
1555 // be the first entry.
1556 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1558 // Allow some cases to be rejected.
1559 if (ShouldEmitAsBranches(SwitchCases)) {
1560 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1561 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1562 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1565 // Emit the branch for this block.
1566 visitSwitchCase(SwitchCases[0]);
1567 SwitchCases.erase(SwitchCases.begin());
1571 // Okay, we decided not to do this, remove any inserted MBB's and clear
1573 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1574 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1576 SwitchCases.clear();
1580 // Create a CaseBlock record representing this branch.
1581 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1582 NULL, Succ0MBB, Succ1MBB, CurMBB);
1583 // Use visitSwitchCase to actually insert the fast branch sequence for this
1585 visitSwitchCase(CB);
1588 /// visitSwitchCase - Emits the necessary code to represent a single node in
1589 /// the binary search tree resulting from lowering a switch instruction.
1590 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1592 SDValue CondLHS = getValue(CB.CmpLHS);
1594 // Build the setcc now.
1595 if (CB.CmpMHS == NULL) {
1596 // Fold "(X == true)" to X and "(X == false)" to !X to
1597 // handle common cases produced by branch lowering.
1598 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1600 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1601 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1602 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1604 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1606 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1608 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1609 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1611 SDValue CmpOp = getValue(CB.CmpMHS);
1612 MVT VT = CmpOp.getValueType();
1614 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1615 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1617 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1618 Cond = DAG.getSetCC(MVT::i1, SUB,
1619 DAG.getConstant(High-Low, VT), ISD::SETULE);
1623 // Update successor info
1624 CurMBB->addSuccessor(CB.TrueBB);
1625 CurMBB->addSuccessor(CB.FalseBB);
1627 // Set NextBlock to be the MBB immediately after the current one, if any.
1628 // This is used to avoid emitting unnecessary branches to the next block.
1629 MachineBasicBlock *NextBlock = 0;
1630 MachineFunction::iterator BBI = CurMBB;
1631 if (++BBI != CurMBB->getParent()->end())
1634 // If the lhs block is the next block, invert the condition so that we can
1635 // fall through to the lhs instead of the rhs block.
1636 if (CB.TrueBB == NextBlock) {
1637 std::swap(CB.TrueBB, CB.FalseBB);
1638 SDValue True = DAG.getConstant(1, Cond.getValueType());
1639 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1641 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1642 DAG.getBasicBlock(CB.TrueBB));
1644 // If the branch was constant folded, fix up the CFG.
1645 if (BrCond.getOpcode() == ISD::BR) {
1646 CurMBB->removeSuccessor(CB.FalseBB);
1647 DAG.setRoot(BrCond);
1649 // Otherwise, go ahead and insert the false branch.
1650 if (BrCond == getControlRoot())
1651 CurMBB->removeSuccessor(CB.TrueBB);
1653 if (CB.FalseBB == NextBlock)
1654 DAG.setRoot(BrCond);
1656 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1657 DAG.getBasicBlock(CB.FalseBB)));
1661 /// visitJumpTable - Emit JumpTable node in the current MBB
1662 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1663 // Emit the code for the jump table
1664 assert(JT.Reg != -1U && "Should lower JT Header first!");
1665 MVT PTy = TLI.getPointerTy();
1666 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1667 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1668 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1673 /// visitJumpTableHeader - This function emits necessary code to produce index
1674 /// in the JumpTable from switch case.
1675 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1676 SelectionDAGISel::JumpTableHeader &JTH) {
1677 // Subtract the lowest switch case value from the value being switched on
1678 // and conditional branch to default mbb if the result is greater than the
1679 // difference between smallest and largest cases.
1680 SDValue SwitchOp = getValue(JTH.SValue);
1681 MVT VT = SwitchOp.getValueType();
1682 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1683 DAG.getConstant(JTH.First, VT));
1685 // The SDNode we just created, which holds the value being switched on
1686 // minus the the smallest case value, needs to be copied to a virtual
1687 // register so it can be used as an index into the jump table in a
1688 // subsequent basic block. This value may be smaller or larger than the
1689 // target's pointer type, and therefore require extension or truncating.
1690 if (VT.bitsGT(TLI.getPointerTy()))
1691 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1693 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1695 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1696 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1697 JT.Reg = JumpTableReg;
1699 // Emit the range check for the jump table, and branch to the default
1700 // block for the switch statement if the value being switched on exceeds
1701 // the largest case in the switch.
1702 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1703 DAG.getConstant(JTH.Last-JTH.First,VT),
1706 // Set NextBlock to be the MBB immediately after the current one, if any.
1707 // This is used to avoid emitting unnecessary branches to the next block.
1708 MachineBasicBlock *NextBlock = 0;
1709 MachineFunction::iterator BBI = CurMBB;
1710 if (++BBI != CurMBB->getParent()->end())
1713 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1714 DAG.getBasicBlock(JT.Default));
1716 if (JT.MBB == NextBlock)
1717 DAG.setRoot(BrCond);
1719 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1720 DAG.getBasicBlock(JT.MBB)));
1725 /// visitBitTestHeader - This function emits necessary code to produce value
1726 /// suitable for "bit tests"
1727 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1728 // Subtract the minimum value
1729 SDValue SwitchOp = getValue(B.SValue);
1730 MVT VT = SwitchOp.getValueType();
1731 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1732 DAG.getConstant(B.First, VT));
1735 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1736 DAG.getConstant(B.Range, VT),
1740 if (VT.bitsGT(TLI.getShiftAmountTy()))
1741 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1743 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1745 // Make desired shift
1746 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1747 DAG.getConstant(1, TLI.getPointerTy()),
1750 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1751 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1754 // Set NextBlock to be the MBB immediately after the current one, if any.
1755 // This is used to avoid emitting unnecessary branches to the next block.
1756 MachineBasicBlock *NextBlock = 0;
1757 MachineFunction::iterator BBI = CurMBB;
1758 if (++BBI != CurMBB->getParent()->end())
1761 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1763 CurMBB->addSuccessor(B.Default);
1764 CurMBB->addSuccessor(MBB);
1766 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1767 DAG.getBasicBlock(B.Default));
1769 if (MBB == NextBlock)
1770 DAG.setRoot(BrRange);
1772 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1773 DAG.getBasicBlock(MBB)));
1778 /// visitBitTestCase - this function produces one "bit test"
1779 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1781 SelectionDAGISel::BitTestCase &B) {
1782 // Emit bit tests and jumps
1783 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1784 TLI.getPointerTy());
1786 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1787 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1788 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1789 DAG.getConstant(0, TLI.getPointerTy()),
1792 CurMBB->addSuccessor(B.TargetBB);
1793 CurMBB->addSuccessor(NextMBB);
1795 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1796 AndCmp, DAG.getBasicBlock(B.TargetBB));
1798 // Set NextBlock to be the MBB immediately after the current one, if any.
1799 // This is used to avoid emitting unnecessary branches to the next block.
1800 MachineBasicBlock *NextBlock = 0;
1801 MachineFunction::iterator BBI = CurMBB;
1802 if (++BBI != CurMBB->getParent()->end())
1805 if (NextMBB == NextBlock)
1808 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1809 DAG.getBasicBlock(NextMBB)));
1814 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1815 // Retrieve successors.
1816 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1817 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1819 if (isa<InlineAsm>(I.getCalledValue()))
1822 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1824 // If the value of the invoke is used outside of its defining block, make it
1825 // available as a virtual register.
1826 if (!I.use_empty()) {
1827 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1828 if (VMI != FuncInfo.ValueMap.end())
1829 CopyValueToVirtualRegister(&I, VMI->second);
1832 // Update successor info
1833 CurMBB->addSuccessor(Return);
1834 CurMBB->addSuccessor(LandingPad);
1836 // Drop into normal successor.
1837 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1838 DAG.getBasicBlock(Return)));
1841 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1844 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1845 /// small case ranges).
1846 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1847 CaseRecVector& WorkList,
1849 MachineBasicBlock* Default) {
1850 Case& BackCase = *(CR.Range.second-1);
1852 // Size is the number of Cases represented by this range.
1853 unsigned Size = CR.Range.second - CR.Range.first;
1857 // Get the MachineFunction which holds the current MBB. This is used when
1858 // inserting any additional MBBs necessary to represent the switch.
1859 MachineFunction *CurMF = CurMBB->getParent();
1861 // Figure out which block is immediately after the current one.
1862 MachineBasicBlock *NextBlock = 0;
1863 MachineFunction::iterator BBI = CR.CaseBB;
1865 if (++BBI != CurMBB->getParent()->end())
1868 // TODO: If any two of the cases has the same destination, and if one value
1869 // is the same as the other, but has one bit unset that the other has set,
1870 // use bit manipulation to do two compares at once. For example:
1871 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1873 // Rearrange the case blocks so that the last one falls through if possible.
1874 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1875 // The last case block won't fall through into 'NextBlock' if we emit the
1876 // branches in this order. See if rearranging a case value would help.
1877 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1878 if (I->BB == NextBlock) {
1879 std::swap(*I, BackCase);
1885 // Create a CaseBlock record representing a conditional branch to
1886 // the Case's target mbb if the value being switched on SV is equal
1888 MachineBasicBlock *CurBlock = CR.CaseBB;
1889 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1890 MachineBasicBlock *FallThrough;
1892 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1893 CurMF->insert(BBI, FallThrough);
1895 // If the last case doesn't match, go to the default block.
1896 FallThrough = Default;
1899 Value *RHS, *LHS, *MHS;
1901 if (I->High == I->Low) {
1902 // This is just small small case range :) containing exactly 1 case
1904 LHS = SV; RHS = I->High; MHS = NULL;
1907 LHS = I->Low; MHS = SV; RHS = I->High;
1909 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1910 I->BB, FallThrough, CurBlock);
1912 // If emitting the first comparison, just call visitSwitchCase to emit the
1913 // code into the current block. Otherwise, push the CaseBlock onto the
1914 // vector to be later processed by SDISel, and insert the node's MBB
1915 // before the next MBB.
1916 if (CurBlock == CurMBB)
1917 visitSwitchCase(CB);
1919 SwitchCases.push_back(CB);
1921 CurBlock = FallThrough;
1927 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1928 return !DisableJumpTables &&
1929 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1930 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1933 /// handleJTSwitchCase - Emit jumptable for current switch case range
1934 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1935 CaseRecVector& WorkList,
1937 MachineBasicBlock* Default) {
1938 Case& FrontCase = *CR.Range.first;
1939 Case& BackCase = *(CR.Range.second-1);
1941 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1942 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1945 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1949 if (!areJTsAllowed(TLI) || TSize <= 3)
1952 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1956 DOUT << "Lowering jump table\n"
1957 << "First entry: " << First << ". Last entry: " << Last << "\n"
1958 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1960 // Get the MachineFunction which holds the current MBB. This is used when
1961 // inserting any additional MBBs necessary to represent the switch.
1962 MachineFunction *CurMF = CurMBB->getParent();
1964 // Figure out which block is immediately after the current one.
1965 MachineBasicBlock *NextBlock = 0;
1966 MachineFunction::iterator BBI = CR.CaseBB;
1968 if (++BBI != CurMBB->getParent()->end())
1971 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1973 // Create a new basic block to hold the code for loading the address
1974 // of the jump table, and jumping to it. Update successor information;
1975 // we will either branch to the default case for the switch, or the jump
1977 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1978 CurMF->insert(BBI, JumpTableBB);
1979 CR.CaseBB->addSuccessor(Default);
1980 CR.CaseBB->addSuccessor(JumpTableBB);
1982 // Build a vector of destination BBs, corresponding to each target
1983 // of the jump table. If the value of the jump table slot corresponds to
1984 // a case statement, push the case's BB onto the vector, otherwise, push
1986 std::vector<MachineBasicBlock*> DestBBs;
1987 int64_t TEI = First;
1988 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1989 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1990 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1992 if ((Low <= TEI) && (TEI <= High)) {
1993 DestBBs.push_back(I->BB);
1997 DestBBs.push_back(Default);
2001 // Update successor info. Add one edge to each unique successor.
2002 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2003 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2004 E = DestBBs.end(); I != E; ++I) {
2005 if (!SuccsHandled[(*I)->getNumber()]) {
2006 SuccsHandled[(*I)->getNumber()] = true;
2007 JumpTableBB->addSuccessor(*I);
2011 // Create a jump table index for this jump table, or return an existing
2013 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
2015 // Set the jump table information so that we can codegen it as a second
2016 // MachineBasicBlock
2017 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
2018 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
2019 (CR.CaseBB == CurMBB));
2020 if (CR.CaseBB == CurMBB)
2021 visitJumpTableHeader(JT, JTH);
2023 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2028 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2030 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2031 CaseRecVector& WorkList,
2033 MachineBasicBlock* Default) {
2034 // Get the MachineFunction which holds the current MBB. This is used when
2035 // inserting any additional MBBs necessary to represent the switch.
2036 MachineFunction *CurMF = CurMBB->getParent();
2038 // Figure out which block is immediately after the current one.
2039 MachineBasicBlock *NextBlock = 0;
2040 MachineFunction::iterator BBI = CR.CaseBB;
2042 if (++BBI != CurMBB->getParent()->end())
2045 Case& FrontCase = *CR.Range.first;
2046 Case& BackCase = *(CR.Range.second-1);
2047 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2049 // Size is the number of Cases represented by this range.
2050 unsigned Size = CR.Range.second - CR.Range.first;
2052 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2053 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2055 CaseItr Pivot = CR.Range.first + Size/2;
2057 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2058 // (heuristically) allow us to emit JumpTable's later.
2060 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2064 uint64_t LSize = FrontCase.size();
2065 uint64_t RSize = TSize-LSize;
2066 DOUT << "Selecting best pivot: \n"
2067 << "First: " << First << ", Last: " << Last <<"\n"
2068 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2069 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2071 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2072 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2073 assert((RBegin-LEnd>=1) && "Invalid case distance");
2074 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2075 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2076 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2077 // Should always split in some non-trivial place
2079 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2080 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2081 << "Metric: " << Metric << "\n";
2082 if (FMetric < Metric) {
2085 DOUT << "Current metric set to: " << FMetric << "\n";
2091 if (areJTsAllowed(TLI)) {
2092 // If our case is dense we *really* should handle it earlier!
2093 assert((FMetric > 0) && "Should handle dense range earlier!");
2095 Pivot = CR.Range.first + Size/2;
2098 CaseRange LHSR(CR.Range.first, Pivot);
2099 CaseRange RHSR(Pivot, CR.Range.second);
2100 Constant *C = Pivot->Low;
2101 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2103 // We know that we branch to the LHS if the Value being switched on is
2104 // less than the Pivot value, C. We use this to optimize our binary
2105 // tree a bit, by recognizing that if SV is greater than or equal to the
2106 // LHS's Case Value, and that Case Value is exactly one less than the
2107 // Pivot's Value, then we can branch directly to the LHS's Target,
2108 // rather than creating a leaf node for it.
2109 if ((LHSR.second - LHSR.first) == 1 &&
2110 LHSR.first->High == CR.GE &&
2111 cast<ConstantInt>(C)->getSExtValue() ==
2112 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2113 TrueBB = LHSR.first->BB;
2115 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2116 CurMF->insert(BBI, TrueBB);
2117 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2120 // Similar to the optimization above, if the Value being switched on is
2121 // known to be less than the Constant CR.LT, and the current Case Value
2122 // is CR.LT - 1, then we can branch directly to the target block for
2123 // the current Case Value, rather than emitting a RHS leaf node for it.
2124 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2125 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2126 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2127 FalseBB = RHSR.first->BB;
2129 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2130 CurMF->insert(BBI, FalseBB);
2131 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2134 // Create a CaseBlock record representing a conditional branch to
2135 // the LHS node if the value being switched on SV is less than C.
2136 // Otherwise, branch to LHS.
2137 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2138 TrueBB, FalseBB, CR.CaseBB);
2140 if (CR.CaseBB == CurMBB)
2141 visitSwitchCase(CB);
2143 SwitchCases.push_back(CB);
2148 /// handleBitTestsSwitchCase - if current case range has few destination and
2149 /// range span less, than machine word bitwidth, encode case range into series
2150 /// of masks and emit bit tests with these masks.
2151 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2152 CaseRecVector& WorkList,
2154 MachineBasicBlock* Default){
2155 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2157 Case& FrontCase = *CR.Range.first;
2158 Case& BackCase = *(CR.Range.second-1);
2160 // Get the MachineFunction which holds the current MBB. This is used when
2161 // inserting any additional MBBs necessary to represent the switch.
2162 MachineFunction *CurMF = CurMBB->getParent();
2164 unsigned numCmps = 0;
2165 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2167 // Single case counts one, case range - two.
2168 if (I->Low == I->High)
2174 // Count unique destinations
2175 SmallSet<MachineBasicBlock*, 4> Dests;
2176 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2177 Dests.insert(I->BB);
2178 if (Dests.size() > 3)
2179 // Don't bother the code below, if there are too much unique destinations
2182 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2183 << "Total number of comparisons: " << numCmps << "\n";
2185 // Compute span of values.
2186 Constant* minValue = FrontCase.Low;
2187 Constant* maxValue = BackCase.High;
2188 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2189 cast<ConstantInt>(minValue)->getSExtValue();
2190 DOUT << "Compare range: " << range << "\n"
2191 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2192 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2194 if (range>=IntPtrBits ||
2195 (!(Dests.size() == 1 && numCmps >= 3) &&
2196 !(Dests.size() == 2 && numCmps >= 5) &&
2197 !(Dests.size() >= 3 && numCmps >= 6)))
2200 DOUT << "Emitting bit tests\n";
2201 int64_t lowBound = 0;
2203 // Optimize the case where all the case values fit in a
2204 // word without having to subtract minValue. In this case,
2205 // we can optimize away the subtraction.
2206 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2207 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2208 range = cast<ConstantInt>(maxValue)->getSExtValue();
2210 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2213 CaseBitsVector CasesBits;
2214 unsigned i, count = 0;
2216 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2217 MachineBasicBlock* Dest = I->BB;
2218 for (i = 0; i < count; ++i)
2219 if (Dest == CasesBits[i].BB)
2223 assert((count < 3) && "Too much destinations to test!");
2224 CasesBits.push_back(CaseBits(0, Dest, 0));
2228 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2229 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2231 for (uint64_t j = lo; j <= hi; j++) {
2232 CasesBits[i].Mask |= 1ULL << j;
2233 CasesBits[i].Bits++;
2237 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2239 SelectionDAGISel::BitTestInfo BTC;
2241 // Figure out which block is immediately after the current one.
2242 MachineFunction::iterator BBI = CR.CaseBB;
2245 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2248 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2249 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2250 << ", BB: " << CasesBits[i].BB << "\n";
2252 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2253 CurMF->insert(BBI, CaseBB);
2254 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2259 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2260 -1U, (CR.CaseBB == CurMBB),
2261 CR.CaseBB, Default, BTC);
2263 if (CR.CaseBB == CurMBB)
2264 visitBitTestHeader(BTB);
2266 BitTestCases.push_back(BTB);
2272 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2273 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2274 const SwitchInst& SI) {
2275 unsigned numCmps = 0;
2277 // Start with "simple" cases
2278 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2279 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2280 Cases.push_back(Case(SI.getSuccessorValue(i),
2281 SI.getSuccessorValue(i),
2284 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2286 // Merge case into clusters
2287 if (Cases.size()>=2)
2288 // Must recompute end() each iteration because it may be
2289 // invalidated by erase if we hold on to it
2290 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2291 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2292 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2293 MachineBasicBlock* nextBB = J->BB;
2294 MachineBasicBlock* currentBB = I->BB;
2296 // If the two neighboring cases go to the same destination, merge them
2297 // into a single case.
2298 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2306 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2307 if (I->Low != I->High)
2308 // A range counts double, since it requires two compares.
2315 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2316 // Figure out which block is immediately after the current one.
2317 MachineBasicBlock *NextBlock = 0;
2318 MachineFunction::iterator BBI = CurMBB;
2320 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2322 // If there is only the default destination, branch to it if it is not the
2323 // next basic block. Otherwise, just fall through.
2324 if (SI.getNumOperands() == 2) {
2325 // Update machine-CFG edges.
2327 // If this is not a fall-through branch, emit the branch.
2328 CurMBB->addSuccessor(Default);
2329 if (Default != NextBlock)
2330 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2331 DAG.getBasicBlock(Default)));
2336 // If there are any non-default case statements, create a vector of Cases
2337 // representing each one, and sort the vector so that we can efficiently
2338 // create a binary search tree from them.
2340 unsigned numCmps = Clusterify(Cases, SI);
2341 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2342 << ". Total compares: " << numCmps << "\n";
2344 // Get the Value to be switched on and default basic blocks, which will be
2345 // inserted into CaseBlock records, representing basic blocks in the binary
2347 Value *SV = SI.getOperand(0);
2349 // Push the initial CaseRec onto the worklist
2350 CaseRecVector WorkList;
2351 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2353 while (!WorkList.empty()) {
2354 // Grab a record representing a case range to process off the worklist
2355 CaseRec CR = WorkList.back();
2356 WorkList.pop_back();
2358 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2361 // If the range has few cases (two or less) emit a series of specific
2363 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2366 // If the switch has more than 5 blocks, and at least 40% dense, and the
2367 // target supports indirect branches, then emit a jump table rather than
2368 // lowering the switch to a binary tree of conditional branches.
2369 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2372 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2373 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2374 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2379 void SelectionDAGLowering::visitSub(User &I) {
2380 // -0.0 - X --> fneg
2381 const Type *Ty = I.getType();
2382 if (isa<VectorType>(Ty)) {
2383 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2384 const VectorType *DestTy = cast<VectorType>(I.getType());
2385 const Type *ElTy = DestTy->getElementType();
2386 if (ElTy->isFloatingPoint()) {
2387 unsigned VL = DestTy->getNumElements();
2388 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2389 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2391 SDValue Op2 = getValue(I.getOperand(1));
2392 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2398 if (Ty->isFloatingPoint()) {
2399 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2400 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2401 SDValue Op2 = getValue(I.getOperand(1));
2402 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2407 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2410 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2411 SDValue Op1 = getValue(I.getOperand(0));
2412 SDValue Op2 = getValue(I.getOperand(1));
2414 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2417 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2418 SDValue Op1 = getValue(I.getOperand(0));
2419 SDValue Op2 = getValue(I.getOperand(1));
2420 if (!isa<VectorType>(I.getType())) {
2421 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2422 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2423 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2424 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2427 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2430 void SelectionDAGLowering::visitICmp(User &I) {
2431 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2432 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2433 predicate = IC->getPredicate();
2434 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2435 predicate = ICmpInst::Predicate(IC->getPredicate());
2436 SDValue Op1 = getValue(I.getOperand(0));
2437 SDValue Op2 = getValue(I.getOperand(1));
2438 ISD::CondCode Opcode;
2439 switch (predicate) {
2440 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2441 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2442 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2443 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2444 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2445 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2446 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2447 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2448 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2449 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2451 assert(!"Invalid ICmp predicate value");
2452 Opcode = ISD::SETEQ;
2455 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2458 void SelectionDAGLowering::visitFCmp(User &I) {
2459 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2460 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2461 predicate = FC->getPredicate();
2462 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2463 predicate = FCmpInst::Predicate(FC->getPredicate());
2464 SDValue Op1 = getValue(I.getOperand(0));
2465 SDValue Op2 = getValue(I.getOperand(1));
2466 ISD::CondCode Condition, FOC, FPC;
2467 switch (predicate) {
2468 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2469 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2470 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2471 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2472 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2473 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2474 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2475 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2476 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2477 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2478 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2479 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2480 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2481 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2482 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2483 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2485 assert(!"Invalid FCmp predicate value");
2486 FOC = FPC = ISD::SETFALSE;
2489 if (FiniteOnlyFPMath())
2493 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2496 void SelectionDAGLowering::visitVICmp(User &I) {
2497 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2498 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2499 predicate = IC->getPredicate();
2500 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2501 predicate = ICmpInst::Predicate(IC->getPredicate());
2502 SDValue Op1 = getValue(I.getOperand(0));
2503 SDValue Op2 = getValue(I.getOperand(1));
2504 ISD::CondCode Opcode;
2505 switch (predicate) {
2506 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2507 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2508 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2509 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2510 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2511 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2512 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2513 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2514 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2515 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2517 assert(!"Invalid ICmp predicate value");
2518 Opcode = ISD::SETEQ;
2521 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2524 void SelectionDAGLowering::visitVFCmp(User &I) {
2525 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2526 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2527 predicate = FC->getPredicate();
2528 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2529 predicate = FCmpInst::Predicate(FC->getPredicate());
2530 SDValue Op1 = getValue(I.getOperand(0));
2531 SDValue Op2 = getValue(I.getOperand(1));
2532 ISD::CondCode Condition, FOC, FPC;
2533 switch (predicate) {
2534 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2535 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2536 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2537 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2538 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2539 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2540 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2541 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2542 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2543 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2544 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2545 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2546 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2547 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2548 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2549 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2551 assert(!"Invalid VFCmp predicate value");
2552 FOC = FPC = ISD::SETFALSE;
2555 if (FiniteOnlyFPMath())
2560 MVT DestVT = TLI.getValueType(I.getType());
2562 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2565 void SelectionDAGLowering::visitSelect(User &I) {
2566 SDValue Cond = getValue(I.getOperand(0));
2567 SDValue TrueVal = getValue(I.getOperand(1));
2568 SDValue FalseVal = getValue(I.getOperand(2));
2569 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2570 TrueVal, FalseVal));
2574 void SelectionDAGLowering::visitTrunc(User &I) {
2575 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2576 SDValue N = getValue(I.getOperand(0));
2577 MVT DestVT = TLI.getValueType(I.getType());
2578 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2581 void SelectionDAGLowering::visitZExt(User &I) {
2582 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2583 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2584 SDValue N = getValue(I.getOperand(0));
2585 MVT DestVT = TLI.getValueType(I.getType());
2586 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2589 void SelectionDAGLowering::visitSExt(User &I) {
2590 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2591 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2592 SDValue N = getValue(I.getOperand(0));
2593 MVT DestVT = TLI.getValueType(I.getType());
2594 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2597 void SelectionDAGLowering::visitFPTrunc(User &I) {
2598 // FPTrunc is never a no-op cast, no need to check
2599 SDValue N = getValue(I.getOperand(0));
2600 MVT DestVT = TLI.getValueType(I.getType());
2601 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2604 void SelectionDAGLowering::visitFPExt(User &I){
2605 // FPTrunc is never a no-op cast, no need to check
2606 SDValue N = getValue(I.getOperand(0));
2607 MVT DestVT = TLI.getValueType(I.getType());
2608 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2611 void SelectionDAGLowering::visitFPToUI(User &I) {
2612 // FPToUI is never a no-op cast, no need to check
2613 SDValue N = getValue(I.getOperand(0));
2614 MVT DestVT = TLI.getValueType(I.getType());
2615 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2618 void SelectionDAGLowering::visitFPToSI(User &I) {
2619 // FPToSI is never a no-op cast, no need to check
2620 SDValue N = getValue(I.getOperand(0));
2621 MVT DestVT = TLI.getValueType(I.getType());
2622 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2625 void SelectionDAGLowering::visitUIToFP(User &I) {
2626 // UIToFP is never a no-op cast, no need to check
2627 SDValue N = getValue(I.getOperand(0));
2628 MVT DestVT = TLI.getValueType(I.getType());
2629 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2632 void SelectionDAGLowering::visitSIToFP(User &I){
2633 // UIToFP is never a no-op cast, no need to check
2634 SDValue N = getValue(I.getOperand(0));
2635 MVT DestVT = TLI.getValueType(I.getType());
2636 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2639 void SelectionDAGLowering::visitPtrToInt(User &I) {
2640 // What to do depends on the size of the integer and the size of the pointer.
2641 // We can either truncate, zero extend, or no-op, accordingly.
2642 SDValue N = getValue(I.getOperand(0));
2643 MVT SrcVT = N.getValueType();
2644 MVT DestVT = TLI.getValueType(I.getType());
2646 if (DestVT.bitsLT(SrcVT))
2647 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2649 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2650 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2651 setValue(&I, Result);
2654 void SelectionDAGLowering::visitIntToPtr(User &I) {
2655 // What to do depends on the size of the integer and the size of the pointer.
2656 // We can either truncate, zero extend, or no-op, accordingly.
2657 SDValue N = getValue(I.getOperand(0));
2658 MVT SrcVT = N.getValueType();
2659 MVT DestVT = TLI.getValueType(I.getType());
2660 if (DestVT.bitsLT(SrcVT))
2661 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2663 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2664 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2667 void SelectionDAGLowering::visitBitCast(User &I) {
2668 SDValue N = getValue(I.getOperand(0));
2669 MVT DestVT = TLI.getValueType(I.getType());
2671 // BitCast assures us that source and destination are the same size so this
2672 // is either a BIT_CONVERT or a no-op.
2673 if (DestVT != N.getValueType())
2674 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2676 setValue(&I, N); // noop cast.
2679 void SelectionDAGLowering::visitInsertElement(User &I) {
2680 SDValue InVec = getValue(I.getOperand(0));
2681 SDValue InVal = getValue(I.getOperand(1));
2682 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2683 getValue(I.getOperand(2)));
2685 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2686 TLI.getValueType(I.getType()),
2687 InVec, InVal, InIdx));
2690 void SelectionDAGLowering::visitExtractElement(User &I) {
2691 SDValue InVec = getValue(I.getOperand(0));
2692 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2693 getValue(I.getOperand(1)));
2694 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2695 TLI.getValueType(I.getType()), InVec, InIdx));
2698 void SelectionDAGLowering::visitShuffleVector(User &I) {
2699 SDValue V1 = getValue(I.getOperand(0));
2700 SDValue V2 = getValue(I.getOperand(1));
2701 SDValue Mask = getValue(I.getOperand(2));
2703 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2704 TLI.getValueType(I.getType()),
2708 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2709 const Value *Op0 = I.getOperand(0);
2710 const Value *Op1 = I.getOperand(1);
2711 const Type *AggTy = I.getType();
2712 const Type *ValTy = Op1->getType();
2713 bool IntoUndef = isa<UndefValue>(Op0);
2714 bool FromUndef = isa<UndefValue>(Op1);
2716 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2717 I.idx_begin(), I.idx_end());
2719 SmallVector<MVT, 4> AggValueVTs;
2720 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2721 SmallVector<MVT, 4> ValValueVTs;
2722 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2724 unsigned NumAggValues = AggValueVTs.size();
2725 unsigned NumValValues = ValValueVTs.size();
2726 SmallVector<SDValue, 4> Values(NumAggValues);
2728 SDValue Agg = getValue(Op0);
2729 SDValue Val = getValue(Op1);
2731 // Copy the beginning value(s) from the original aggregate.
2732 for (; i != LinearIndex; ++i)
2733 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2734 SDValue(Agg.Val, Agg.ResNo + i);
2735 // Copy values from the inserted value(s).
2736 for (; i != LinearIndex + NumValValues; ++i)
2737 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2738 SDValue(Val.Val, Val.ResNo + i - LinearIndex);
2739 // Copy remaining value(s) from the original aggregate.
2740 for (; i != NumAggValues; ++i)
2741 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2742 SDValue(Agg.Val, Agg.ResNo + i);
2744 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2745 &Values[0], NumAggValues));
2748 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2749 const Value *Op0 = I.getOperand(0);
2750 const Type *AggTy = Op0->getType();
2751 const Type *ValTy = I.getType();
2752 bool OutOfUndef = isa<UndefValue>(Op0);
2754 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2755 I.idx_begin(), I.idx_end());
2757 SmallVector<MVT, 4> ValValueVTs;
2758 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2760 unsigned NumValValues = ValValueVTs.size();
2761 SmallVector<SDValue, 4> Values(NumValValues);
2763 SDValue Agg = getValue(Op0);
2764 // Copy out the selected value(s).
2765 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2766 Values[i - LinearIndex] =
2767 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2768 SDValue(Agg.Val, Agg.ResNo + i);
2770 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2771 &Values[0], NumValValues));
2775 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2776 SDValue N = getValue(I.getOperand(0));
2777 const Type *Ty = I.getOperand(0)->getType();
2779 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2782 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2783 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2786 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2787 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2788 DAG.getIntPtrConstant(Offset));
2790 Ty = StTy->getElementType(Field);
2792 Ty = cast<SequentialType>(Ty)->getElementType();
2794 // If this is a constant subscript, handle it quickly.
2795 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2796 if (CI->getZExtValue() == 0) continue;
2798 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2799 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2800 DAG.getIntPtrConstant(Offs));
2804 // N = N + Idx * ElementSize;
2805 uint64_t ElementSize = TD->getABITypeSize(Ty);
2806 SDValue IdxN = getValue(Idx);
2808 // If the index is smaller or larger than intptr_t, truncate or extend
2810 if (IdxN.getValueType().bitsLT(N.getValueType()))
2811 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2812 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2813 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2815 // If this is a multiply by a power of two, turn it into a shl
2816 // immediately. This is a very common case.
2817 if (isPowerOf2_64(ElementSize)) {
2818 unsigned Amt = Log2_64(ElementSize);
2819 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2820 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2821 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2825 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2826 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2827 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2833 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2834 // If this is a fixed sized alloca in the entry block of the function,
2835 // allocate it statically on the stack.
2836 if (FuncInfo.StaticAllocaMap.count(&I))
2837 return; // getValue will auto-populate this.
2839 const Type *Ty = I.getAllocatedType();
2840 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2842 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2845 SDValue AllocSize = getValue(I.getArraySize());
2846 MVT IntPtr = TLI.getPointerTy();
2847 if (IntPtr.bitsLT(AllocSize.getValueType()))
2848 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2849 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2850 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2852 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2853 DAG.getIntPtrConstant(TySize));
2855 // Handle alignment. If the requested alignment is less than or equal to
2856 // the stack alignment, ignore it. If the size is greater than or equal to
2857 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2858 unsigned StackAlign =
2859 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2860 if (Align <= StackAlign)
2863 // Round the size of the allocation up to the stack alignment size
2864 // by add SA-1 to the size.
2865 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2866 DAG.getIntPtrConstant(StackAlign-1));
2867 // Mask out the low bits for alignment purposes.
2868 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2869 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2871 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2872 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2874 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2876 DAG.setRoot(DSA.getValue(1));
2878 // Inform the Frame Information that we have just allocated a variable-sized
2880 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2883 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2884 const Value *SV = I.getOperand(0);
2885 SDValue Ptr = getValue(SV);
2887 const Type *Ty = I.getType();
2888 bool isVolatile = I.isVolatile();
2889 unsigned Alignment = I.getAlignment();
2891 SmallVector<MVT, 4> ValueVTs;
2892 SmallVector<uint64_t, 4> Offsets;
2893 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2894 unsigned NumValues = ValueVTs.size();
2899 bool ConstantMemory = false;
2901 // Serialize volatile loads with other side effects.
2903 else if (AA.pointsToConstantMemory(SV)) {
2904 // Do not serialize (non-volatile) loads of constant memory with anything.
2905 Root = DAG.getEntryNode();
2906 ConstantMemory = true;
2908 // Do not serialize non-volatile loads against each other.
2909 Root = DAG.getRoot();
2912 SmallVector<SDValue, 4> Values(NumValues);
2913 SmallVector<SDValue, 4> Chains(NumValues);
2914 MVT PtrVT = Ptr.getValueType();
2915 for (unsigned i = 0; i != NumValues; ++i) {
2916 SDValue L = DAG.getLoad(ValueVTs[i], Root,
2917 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2918 DAG.getConstant(Offsets[i], PtrVT)),
2920 isVolatile, Alignment);
2922 Chains[i] = L.getValue(1);
2925 if (!ConstantMemory) {
2926 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2927 &Chains[0], NumValues);
2931 PendingLoads.push_back(Chain);
2934 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2935 &Values[0], NumValues));
2939 void SelectionDAGLowering::visitStore(StoreInst &I) {
2940 Value *SrcV = I.getOperand(0);
2941 Value *PtrV = I.getOperand(1);
2943 SmallVector<MVT, 4> ValueVTs;
2944 SmallVector<uint64_t, 4> Offsets;
2945 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2946 unsigned NumValues = ValueVTs.size();
2950 // Get the lowered operands. Note that we do this after
2951 // checking if NumResults is zero, because with zero results
2952 // the operands won't have values in the map.
2953 SDValue Src = getValue(SrcV);
2954 SDValue Ptr = getValue(PtrV);
2956 SDValue Root = getRoot();
2957 SmallVector<SDValue, 4> Chains(NumValues);
2958 MVT PtrVT = Ptr.getValueType();
2959 bool isVolatile = I.isVolatile();
2960 unsigned Alignment = I.getAlignment();
2961 for (unsigned i = 0; i != NumValues; ++i)
2962 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
2963 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2964 DAG.getConstant(Offsets[i], PtrVT)),
2966 isVolatile, Alignment);
2968 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2971 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2973 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2974 unsigned Intrinsic) {
2975 bool HasChain = !I.doesNotAccessMemory();
2976 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2978 // Build the operand list.
2979 SmallVector<SDValue, 8> Ops;
2980 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2982 // We don't need to serialize loads against other loads.
2983 Ops.push_back(DAG.getRoot());
2985 Ops.push_back(getRoot());
2989 // Add the intrinsic ID as an integer operand.
2990 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2992 // Add all operands of the call to the operand list.
2993 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2994 SDValue Op = getValue(I.getOperand(i));
2995 assert(TLI.isTypeLegal(Op.getValueType()) &&
2996 "Intrinsic uses a non-legal type?");
3000 std::vector<MVT> VTs;
3001 if (I.getType() != Type::VoidTy) {
3002 MVT VT = TLI.getValueType(I.getType());
3003 if (VT.isVector()) {
3004 const VectorType *DestTy = cast<VectorType>(I.getType());
3005 MVT EltVT = TLI.getValueType(DestTy->getElementType());
3007 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
3008 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
3011 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
3015 VTs.push_back(MVT::Other);
3017 const MVT *VTList = DAG.getNodeValueTypes(VTs);
3022 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
3023 &Ops[0], Ops.size());
3024 else if (I.getType() != Type::VoidTy)
3025 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
3026 &Ops[0], Ops.size());
3028 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
3029 &Ops[0], Ops.size());
3032 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
3034 PendingLoads.push_back(Chain);
3038 if (I.getType() != Type::VoidTy) {
3039 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3040 MVT VT = TLI.getValueType(PTy);
3041 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3043 setValue(&I, Result);
3047 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3048 static GlobalVariable *ExtractTypeInfo (Value *V) {
3049 V = V->stripPointerCasts();
3050 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3051 assert ((GV || isa<ConstantPointerNull>(V)) &&
3052 "TypeInfo must be a global variable or NULL");
3056 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3057 /// call, and add them to the specified machine basic block.
3058 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3059 MachineBasicBlock *MBB) {
3060 // Inform the MachineModuleInfo of the personality for this landing pad.
3061 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3062 assert(CE->getOpcode() == Instruction::BitCast &&
3063 isa<Function>(CE->getOperand(0)) &&
3064 "Personality should be a function");
3065 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3067 // Gather all the type infos for this landing pad and pass them along to
3068 // MachineModuleInfo.
3069 std::vector<GlobalVariable *> TyInfo;
3070 unsigned N = I.getNumOperands();
3072 for (unsigned i = N - 1; i > 2; --i) {
3073 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3074 unsigned FilterLength = CI->getZExtValue();
3075 unsigned FirstCatch = i + FilterLength + !FilterLength;
3076 assert (FirstCatch <= N && "Invalid filter length");
3078 if (FirstCatch < N) {
3079 TyInfo.reserve(N - FirstCatch);
3080 for (unsigned j = FirstCatch; j < N; ++j)
3081 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3082 MMI->addCatchTypeInfo(MBB, TyInfo);
3086 if (!FilterLength) {
3088 MMI->addCleanup(MBB);
3091 TyInfo.reserve(FilterLength - 1);
3092 for (unsigned j = i + 1; j < FirstCatch; ++j)
3093 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3094 MMI->addFilterTypeInfo(MBB, TyInfo);
3103 TyInfo.reserve(N - 3);
3104 for (unsigned j = 3; j < N; ++j)
3105 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3106 MMI->addCatchTypeInfo(MBB, TyInfo);
3111 /// Inlined utility function to implement binary input atomic intrinsics for
3112 // visitIntrinsicCall: I is a call instruction
3113 // Op is the associated NodeType for I
3115 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3116 SDValue Root = getRoot();
3117 SDValue L = DAG.getAtomic(Op, Root,
3118 getValue(I.getOperand(1)),
3119 getValue(I.getOperand(2)),
3122 DAG.setRoot(L.getValue(1));
3126 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3127 /// we want to emit this as a call to a named external function, return the name
3128 /// otherwise lower it and return null.
3130 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3131 switch (Intrinsic) {
3133 // By default, turn this into a target intrinsic node.
3134 visitTargetIntrinsic(I, Intrinsic);
3136 case Intrinsic::vastart: visitVAStart(I); return 0;
3137 case Intrinsic::vaend: visitVAEnd(I); return 0;
3138 case Intrinsic::vacopy: visitVACopy(I); return 0;
3139 case Intrinsic::returnaddress:
3140 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3141 getValue(I.getOperand(1))));
3143 case Intrinsic::frameaddress:
3144 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3145 getValue(I.getOperand(1))));
3147 case Intrinsic::setjmp:
3148 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3150 case Intrinsic::longjmp:
3151 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3153 case Intrinsic::memcpy_i32:
3154 case Intrinsic::memcpy_i64: {
3155 SDValue Op1 = getValue(I.getOperand(1));
3156 SDValue Op2 = getValue(I.getOperand(2));
3157 SDValue Op3 = getValue(I.getOperand(3));
3158 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3159 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3160 I.getOperand(1), 0, I.getOperand(2), 0));
3163 case Intrinsic::memset_i32:
3164 case Intrinsic::memset_i64: {
3165 SDValue Op1 = getValue(I.getOperand(1));
3166 SDValue Op2 = getValue(I.getOperand(2));
3167 SDValue Op3 = getValue(I.getOperand(3));
3168 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3169 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3170 I.getOperand(1), 0));
3173 case Intrinsic::memmove_i32:
3174 case Intrinsic::memmove_i64: {
3175 SDValue Op1 = getValue(I.getOperand(1));
3176 SDValue Op2 = getValue(I.getOperand(2));
3177 SDValue Op3 = getValue(I.getOperand(3));
3178 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3180 // If the source and destination are known to not be aliases, we can
3181 // lower memmove as memcpy.
3182 uint64_t Size = -1ULL;
3183 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3184 Size = C->getValue();
3185 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3186 AliasAnalysis::NoAlias) {
3187 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3188 I.getOperand(1), 0, I.getOperand(2), 0));
3192 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3193 I.getOperand(1), 0, I.getOperand(2), 0));
3196 case Intrinsic::dbg_stoppoint: {
3197 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3198 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3199 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3200 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3201 assert(DD && "Not a debug information descriptor");
3202 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3205 cast<CompileUnitDesc>(DD)));
3210 case Intrinsic::dbg_region_start: {
3211 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3212 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3213 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3214 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3215 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3220 case Intrinsic::dbg_region_end: {
3221 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3222 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3223 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3224 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3225 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3230 case Intrinsic::dbg_func_start: {
3231 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3233 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3234 Value *SP = FSI.getSubprogram();
3235 if (SP && MMI->Verify(SP)) {
3236 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3237 // what (most?) gdb expects.
3238 DebugInfoDesc *DD = MMI->getDescFor(SP);
3239 assert(DD && "Not a debug information descriptor");
3240 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3241 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3242 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3243 // Record the source line but does create a label. It will be emitted
3244 // at asm emission time.
3245 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3250 case Intrinsic::dbg_declare: {
3251 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3252 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3253 Value *Variable = DI.getVariable();
3254 if (MMI && Variable && MMI->Verify(Variable))
3255 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3256 getValue(DI.getAddress()), getValue(Variable)));
3260 case Intrinsic::eh_exception: {
3261 if (!CurMBB->isLandingPad()) {
3262 // FIXME: Mark exception register as live in. Hack for PR1508.
3263 unsigned Reg = TLI.getExceptionAddressRegister();
3264 if (Reg) CurMBB->addLiveIn(Reg);
3266 // Insert the EXCEPTIONADDR instruction.
3267 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3269 Ops[0] = DAG.getRoot();
3270 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3272 DAG.setRoot(Op.getValue(1));
3276 case Intrinsic::eh_selector_i32:
3277 case Intrinsic::eh_selector_i64: {
3278 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3279 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3280 MVT::i32 : MVT::i64);
3283 if (CurMBB->isLandingPad())
3284 addCatchInfo(I, MMI, CurMBB);
3287 FuncInfo.CatchInfoLost.insert(&I);
3289 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3290 unsigned Reg = TLI.getExceptionSelectorRegister();
3291 if (Reg) CurMBB->addLiveIn(Reg);
3294 // Insert the EHSELECTION instruction.
3295 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3297 Ops[0] = getValue(I.getOperand(1));
3299 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3301 DAG.setRoot(Op.getValue(1));
3303 setValue(&I, DAG.getConstant(0, VT));
3309 case Intrinsic::eh_typeid_for_i32:
3310 case Intrinsic::eh_typeid_for_i64: {
3311 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3312 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3313 MVT::i32 : MVT::i64);
3316 // Find the type id for the given typeinfo.
3317 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3319 unsigned TypeID = MMI->getTypeIDFor(GV);
3320 setValue(&I, DAG.getConstant(TypeID, VT));
3322 // Return something different to eh_selector.
3323 setValue(&I, DAG.getConstant(1, VT));
3329 case Intrinsic::eh_return: {
3330 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3333 MMI->setCallsEHReturn(true);
3334 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3337 getValue(I.getOperand(1)),
3338 getValue(I.getOperand(2))));
3340 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3346 case Intrinsic::eh_unwind_init: {
3347 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3348 MMI->setCallsUnwindInit(true);
3354 case Intrinsic::eh_dwarf_cfa: {
3355 MVT VT = getValue(I.getOperand(1)).getValueType();
3357 if (VT.bitsGT(TLI.getPointerTy()))
3358 CfaArg = DAG.getNode(ISD::TRUNCATE,
3359 TLI.getPointerTy(), getValue(I.getOperand(1)));
3361 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3362 TLI.getPointerTy(), getValue(I.getOperand(1)));
3364 SDValue Offset = DAG.getNode(ISD::ADD,
3366 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3367 TLI.getPointerTy()),
3369 setValue(&I, DAG.getNode(ISD::ADD,
3371 DAG.getNode(ISD::FRAMEADDR,
3374 TLI.getPointerTy())),
3379 case Intrinsic::sqrt:
3380 setValue(&I, DAG.getNode(ISD::FSQRT,
3381 getValue(I.getOperand(1)).getValueType(),
3382 getValue(I.getOperand(1))));
3384 case Intrinsic::powi:
3385 setValue(&I, DAG.getNode(ISD::FPOWI,
3386 getValue(I.getOperand(1)).getValueType(),
3387 getValue(I.getOperand(1)),
3388 getValue(I.getOperand(2))));
3390 case Intrinsic::sin:
3391 setValue(&I, DAG.getNode(ISD::FSIN,
3392 getValue(I.getOperand(1)).getValueType(),
3393 getValue(I.getOperand(1))));
3395 case Intrinsic::cos:
3396 setValue(&I, DAG.getNode(ISD::FCOS,
3397 getValue(I.getOperand(1)).getValueType(),
3398 getValue(I.getOperand(1))));
3400 case Intrinsic::pow:
3401 setValue(&I, DAG.getNode(ISD::FPOW,
3402 getValue(I.getOperand(1)).getValueType(),
3403 getValue(I.getOperand(1)),
3404 getValue(I.getOperand(2))));
3406 case Intrinsic::pcmarker: {
3407 SDValue Tmp = getValue(I.getOperand(1));
3408 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3411 case Intrinsic::readcyclecounter: {
3412 SDValue Op = getRoot();
3413 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3414 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3417 DAG.setRoot(Tmp.getValue(1));
3420 case Intrinsic::part_select: {
3421 // Currently not implemented: just abort
3422 assert(0 && "part_select intrinsic not implemented");
3425 case Intrinsic::part_set: {
3426 // Currently not implemented: just abort
3427 assert(0 && "part_set intrinsic not implemented");
3430 case Intrinsic::bswap:
3431 setValue(&I, DAG.getNode(ISD::BSWAP,
3432 getValue(I.getOperand(1)).getValueType(),
3433 getValue(I.getOperand(1))));
3435 case Intrinsic::cttz: {
3436 SDValue Arg = getValue(I.getOperand(1));
3437 MVT Ty = Arg.getValueType();
3438 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3439 setValue(&I, result);
3442 case Intrinsic::ctlz: {
3443 SDValue Arg = getValue(I.getOperand(1));
3444 MVT Ty = Arg.getValueType();
3445 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3446 setValue(&I, result);
3449 case Intrinsic::ctpop: {
3450 SDValue Arg = getValue(I.getOperand(1));
3451 MVT Ty = Arg.getValueType();
3452 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3453 setValue(&I, result);
3456 case Intrinsic::stacksave: {
3457 SDValue Op = getRoot();
3458 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
3459 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3461 DAG.setRoot(Tmp.getValue(1));
3464 case Intrinsic::stackrestore: {
3465 SDValue Tmp = getValue(I.getOperand(1));
3466 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3469 case Intrinsic::var_annotation:
3470 // Discard annotate attributes
3473 case Intrinsic::init_trampoline: {
3474 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3478 Ops[1] = getValue(I.getOperand(1));
3479 Ops[2] = getValue(I.getOperand(2));
3480 Ops[3] = getValue(I.getOperand(3));
3481 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3482 Ops[5] = DAG.getSrcValue(F);
3484 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
3485 DAG.getNodeValueTypes(TLI.getPointerTy(),
3490 DAG.setRoot(Tmp.getValue(1));
3494 case Intrinsic::gcroot:
3496 Value *Alloca = I.getOperand(1);
3497 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3499 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3500 GFI->addStackRoot(FI->getIndex(), TypeMap);
3504 case Intrinsic::gcread:
3505 case Intrinsic::gcwrite:
3506 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
3509 case Intrinsic::flt_rounds: {
3510 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3514 case Intrinsic::trap: {
3515 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3518 case Intrinsic::prefetch: {
3521 Ops[1] = getValue(I.getOperand(1));
3522 Ops[2] = getValue(I.getOperand(2));
3523 Ops[3] = getValue(I.getOperand(3));
3524 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3528 case Intrinsic::memory_barrier: {
3531 for (int x = 1; x < 6; ++x)
3532 Ops[x] = getValue(I.getOperand(x));
3534 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3537 case Intrinsic::atomic_cmp_swap: {
3538 SDValue Root = getRoot();
3539 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
3540 getValue(I.getOperand(1)),
3541 getValue(I.getOperand(2)),
3542 getValue(I.getOperand(3)),
3545 DAG.setRoot(L.getValue(1));
3548 case Intrinsic::atomic_load_add:
3549 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3550 case Intrinsic::atomic_load_sub:
3551 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
3552 case Intrinsic::atomic_load_and:
3553 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3554 case Intrinsic::atomic_load_or:
3555 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3556 case Intrinsic::atomic_load_xor:
3557 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3558 case Intrinsic::atomic_load_nand:
3559 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3560 case Intrinsic::atomic_load_min:
3561 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3562 case Intrinsic::atomic_load_max:
3563 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3564 case Intrinsic::atomic_load_umin:
3565 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3566 case Intrinsic::atomic_load_umax:
3567 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3568 case Intrinsic::atomic_swap:
3569 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3574 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
3576 MachineBasicBlock *LandingPad) {
3577 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3578 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3579 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3580 unsigned BeginLabel = 0, EndLabel = 0;
3582 TargetLowering::ArgListTy Args;
3583 TargetLowering::ArgListEntry Entry;
3584 Args.reserve(CS.arg_size());
3585 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3587 SDValue ArgNode = getValue(*i);
3588 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3590 unsigned attrInd = i - CS.arg_begin() + 1;
3591 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3592 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3593 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3594 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3595 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3596 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3597 Entry.Alignment = CS.getParamAlignment(attrInd);
3598 Args.push_back(Entry);
3601 if (LandingPad && MMI) {
3602 // Insert a label before the invoke call to mark the try range. This can be
3603 // used to detect deletion of the invoke via the MachineModuleInfo.
3604 BeginLabel = MMI->NextLabelID();
3605 // Both PendingLoads and PendingExports must be flushed here;
3606 // this call might not return.
3608 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
3611 std::pair<SDValue,SDValue> Result =
3612 TLI.LowerCallTo(getRoot(), CS.getType(),
3613 CS.paramHasAttr(0, ParamAttr::SExt),
3614 CS.paramHasAttr(0, ParamAttr::ZExt),
3615 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3617 if (CS.getType() != Type::VoidTy)
3618 setValue(CS.getInstruction(), Result.first);
3619 DAG.setRoot(Result.second);
3621 if (LandingPad && MMI) {
3622 // Insert a label at the end of the invoke call to mark the try range. This
3623 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3624 EndLabel = MMI->NextLabelID();
3625 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
3627 // Inform MachineModuleInfo of range.
3628 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3633 void SelectionDAGLowering::visitCall(CallInst &I) {
3634 const char *RenameFn = 0;
3635 if (Function *F = I.getCalledFunction()) {
3636 if (F->isDeclaration()) {
3637 if (unsigned IID = F->getIntrinsicID()) {
3638 RenameFn = visitIntrinsicCall(I, IID);
3644 // Check for well-known libc/libm calls. If the function is internal, it
3645 // can't be a library call.
3646 unsigned NameLen = F->getNameLen();
3647 if (!F->hasInternalLinkage() && NameLen) {
3648 const char *NameStr = F->getNameStart();
3649 if (NameStr[0] == 'c' &&
3650 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3651 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3652 if (I.getNumOperands() == 3 && // Basic sanity checks.
3653 I.getOperand(1)->getType()->isFloatingPoint() &&
3654 I.getType() == I.getOperand(1)->getType() &&
3655 I.getType() == I.getOperand(2)->getType()) {
3656 SDValue LHS = getValue(I.getOperand(1));
3657 SDValue RHS = getValue(I.getOperand(2));
3658 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3662 } else if (NameStr[0] == 'f' &&
3663 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3664 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3665 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3666 if (I.getNumOperands() == 2 && // Basic sanity checks.
3667 I.getOperand(1)->getType()->isFloatingPoint() &&
3668 I.getType() == I.getOperand(1)->getType()) {
3669 SDValue Tmp = getValue(I.getOperand(1));
3670 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3673 } else if (NameStr[0] == 's' &&
3674 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3675 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3676 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3677 if (I.getNumOperands() == 2 && // Basic sanity checks.
3678 I.getOperand(1)->getType()->isFloatingPoint() &&
3679 I.getType() == I.getOperand(1)->getType()) {
3680 SDValue Tmp = getValue(I.getOperand(1));
3681 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3684 } else if (NameStr[0] == 'c' &&
3685 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3686 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3687 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3688 if (I.getNumOperands() == 2 && // Basic sanity checks.
3689 I.getOperand(1)->getType()->isFloatingPoint() &&
3690 I.getType() == I.getOperand(1)->getType()) {
3691 SDValue Tmp = getValue(I.getOperand(1));
3692 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3697 } else if (isa<InlineAsm>(I.getOperand(0))) {
3704 Callee = getValue(I.getOperand(0));
3706 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3708 LowerCallTo(&I, Callee, I.isTailCall());
3712 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3713 /// this value and returns the result as a ValueVT value. This uses
3714 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3715 /// If the Flag pointer is NULL, no flag is used.
3716 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3718 SDValue *Flag) const {
3719 // Assemble the legal parts into the final values.
3720 SmallVector<SDValue, 4> Values(ValueVTs.size());
3721 SmallVector<SDValue, 8> Parts;
3722 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3723 // Copy the legal parts from the registers.
3724 MVT ValueVT = ValueVTs[Value];
3725 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3726 MVT RegisterVT = RegVTs[Value];
3728 Parts.resize(NumRegs);
3729 for (unsigned i = 0; i != NumRegs; ++i) {
3732 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3734 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3735 *Flag = P.getValue(2);
3737 Chain = P.getValue(1);
3739 // If the source register was virtual and if we know something about it,
3740 // add an assert node.
3741 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3742 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3743 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3744 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3745 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3746 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3748 unsigned RegSize = RegisterVT.getSizeInBits();
3749 unsigned NumSignBits = LOI.NumSignBits;
3750 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3752 // FIXME: We capture more information than the dag can represent. For
3753 // now, just use the tightest assertzext/assertsext possible.
3755 MVT FromVT(MVT::Other);
3756 if (NumSignBits == RegSize)
3757 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3758 else if (NumZeroBits >= RegSize-1)
3759 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3760 else if (NumSignBits > RegSize-8)
3761 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3762 else if (NumZeroBits >= RegSize-9)
3763 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3764 else if (NumSignBits > RegSize-16)
3765 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3766 else if (NumZeroBits >= RegSize-17)
3767 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3768 else if (NumSignBits > RegSize-32)
3769 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3770 else if (NumZeroBits >= RegSize-33)
3771 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3773 if (FromVT != MVT::Other) {
3774 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3775 RegisterVT, P, DAG.getValueType(FromVT));
3784 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3789 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3790 &Values[0], ValueVTs.size());
3793 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3794 /// specified value into the registers specified by this object. This uses
3795 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3796 /// If the Flag pointer is NULL, no flag is used.
3797 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
3798 SDValue &Chain, SDValue *Flag) const {
3799 // Get the list of the values's legal parts.
3800 unsigned NumRegs = Regs.size();
3801 SmallVector<SDValue, 8> Parts(NumRegs);
3802 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3803 MVT ValueVT = ValueVTs[Value];
3804 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3805 MVT RegisterVT = RegVTs[Value];
3807 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3808 &Parts[Part], NumParts, RegisterVT);
3812 // Copy the parts into the registers.
3813 SmallVector<SDValue, 8> Chains(NumRegs);
3814 for (unsigned i = 0; i != NumRegs; ++i) {
3817 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3819 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3820 *Flag = Part.getValue(1);
3822 Chains[i] = Part.getValue(0);
3825 if (NumRegs == 1 || Flag)
3826 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3827 // flagged to it. That is the CopyToReg nodes and the user are considered
3828 // a single scheduling unit. If we create a TokenFactor and return it as
3829 // chain, then the TokenFactor is both a predecessor (operand) of the
3830 // user as well as a successor (the TF operands are flagged to the user).
3831 // c1, f1 = CopyToReg
3832 // c2, f2 = CopyToReg
3833 // c3 = TokenFactor c1, c2
3836 Chain = Chains[NumRegs-1];
3838 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3841 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3842 /// operand list. This adds the code marker and includes the number of
3843 /// values added into it.
3844 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3845 std::vector<SDValue> &Ops) const {
3846 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3847 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3848 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3849 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3850 MVT RegisterVT = RegVTs[Value];
3851 for (unsigned i = 0; i != NumRegs; ++i)
3852 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3856 /// isAllocatableRegister - If the specified register is safe to allocate,
3857 /// i.e. it isn't a stack pointer or some other special register, return the
3858 /// register class for the register. Otherwise, return null.
3859 static const TargetRegisterClass *
3860 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3861 const TargetLowering &TLI,
3862 const TargetRegisterInfo *TRI) {
3863 MVT FoundVT = MVT::Other;
3864 const TargetRegisterClass *FoundRC = 0;
3865 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3866 E = TRI->regclass_end(); RCI != E; ++RCI) {
3867 MVT ThisVT = MVT::Other;
3869 const TargetRegisterClass *RC = *RCI;
3870 // If none of the the value types for this register class are valid, we
3871 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3872 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3874 if (TLI.isTypeLegal(*I)) {
3875 // If we have already found this register in a different register class,
3876 // choose the one with the largest VT specified. For example, on
3877 // PowerPC, we favor f64 register classes over f32.
3878 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3885 if (ThisVT == MVT::Other) continue;
3887 // NOTE: This isn't ideal. In particular, this might allocate the
3888 // frame pointer in functions that need it (due to them not being taken
3889 // out of allocation, because a variable sized allocation hasn't been seen
3890 // yet). This is a slight code pessimization, but should still work.
3891 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3892 E = RC->allocation_order_end(MF); I != E; ++I)
3894 // We found a matching register class. Keep looking at others in case
3895 // we find one with larger registers that this physreg is also in.
3906 /// AsmOperandInfo - This contains information for each constraint that we are
3908 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3909 /// CallOperand - If this is the result output operand or a clobber
3910 /// this is null, otherwise it is the incoming operand to the CallInst.
3911 /// This gets modified as the asm is processed.
3912 SDValue CallOperand;
3914 /// AssignedRegs - If this is a register or register class operand, this
3915 /// contains the set of register corresponding to the operand.
3916 RegsForValue AssignedRegs;
3918 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3919 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3922 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3923 /// busy in OutputRegs/InputRegs.
3924 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3925 std::set<unsigned> &OutputRegs,
3926 std::set<unsigned> &InputRegs,
3927 const TargetRegisterInfo &TRI) const {
3929 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3930 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3933 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3934 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3939 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3941 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3942 const TargetRegisterInfo &TRI) {
3943 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3945 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3946 for (; *Aliases; ++Aliases)
3947 Regs.insert(*Aliases);
3950 } // end anon namespace.
3953 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3954 /// specified operand. We prefer to assign virtual registers, to allow the
3955 /// register allocator handle the assignment process. However, if the asm uses
3956 /// features that we can't model on machineinstrs, we have SDISel do the
3957 /// allocation. This produces generally horrible, but correct, code.
3959 /// OpInfo describes the operand.
3960 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3961 /// or any explicitly clobbered registers.
3962 /// Input and OutputRegs are the set of already allocated physical registers.
3964 void SelectionDAGLowering::
3965 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3966 std::set<unsigned> &OutputRegs,
3967 std::set<unsigned> &InputRegs) {
3968 // Compute whether this value requires an input register, an output register,
3970 bool isOutReg = false;
3971 bool isInReg = false;
3972 switch (OpInfo.Type) {
3973 case InlineAsm::isOutput:
3976 // If this is an early-clobber output, or if there is an input
3977 // constraint that matches this, we need to reserve the input register
3978 // so no other inputs allocate to it.
3979 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3981 case InlineAsm::isInput:
3985 case InlineAsm::isClobber:
3992 MachineFunction &MF = DAG.getMachineFunction();
3993 SmallVector<unsigned, 4> Regs;
3995 // If this is a constraint for a single physreg, or a constraint for a
3996 // register class, find it.
3997 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3998 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3999 OpInfo.ConstraintVT);
4001 unsigned NumRegs = 1;
4002 if (OpInfo.ConstraintVT != MVT::Other)
4003 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4005 MVT ValueVT = OpInfo.ConstraintVT;
4008 // If this is a constraint for a specific physical register, like {r17},
4010 if (PhysReg.first) {
4011 if (OpInfo.ConstraintVT == MVT::Other)
4012 ValueVT = *PhysReg.second->vt_begin();
4014 // Get the actual register value type. This is important, because the user
4015 // may have asked for (e.g.) the AX register in i32 type. We need to
4016 // remember that AX is actually i16 to get the right extension.
4017 RegVT = *PhysReg.second->vt_begin();
4019 // This is a explicit reference to a physical register.
4020 Regs.push_back(PhysReg.first);
4022 // If this is an expanded reference, add the rest of the regs to Regs.
4024 TargetRegisterClass::iterator I = PhysReg.second->begin();
4025 for (; *I != PhysReg.first; ++I)
4026 assert(I != PhysReg.second->end() && "Didn't find reg!");
4028 // Already added the first reg.
4030 for (; NumRegs; --NumRegs, ++I) {
4031 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4035 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4036 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4037 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4041 // Otherwise, if this was a reference to an LLVM register class, create vregs
4042 // for this reference.
4043 std::vector<unsigned> RegClassRegs;
4044 const TargetRegisterClass *RC = PhysReg.second;
4046 // If this is an early clobber or tied register, our regalloc doesn't know
4047 // how to maintain the constraint. If it isn't, go ahead and create vreg
4048 // and let the regalloc do the right thing.
4049 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4050 // If there is some other early clobber and this is an input register,
4051 // then we are forced to pre-allocate the input reg so it doesn't
4052 // conflict with the earlyclobber.
4053 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4054 RegVT = *PhysReg.second->vt_begin();
4056 if (OpInfo.ConstraintVT == MVT::Other)
4059 // Create the appropriate number of virtual registers.
4060 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4061 for (; NumRegs; --NumRegs)
4062 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4064 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4068 // Otherwise, we can't allocate it. Let the code below figure out how to
4069 // maintain these constraints.
4070 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4073 // This is a reference to a register class that doesn't directly correspond
4074 // to an LLVM register class. Allocate NumRegs consecutive, available,
4075 // registers from the class.
4076 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4077 OpInfo.ConstraintVT);
4080 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4081 unsigned NumAllocated = 0;
4082 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4083 unsigned Reg = RegClassRegs[i];
4084 // See if this register is available.
4085 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4086 (isInReg && InputRegs.count(Reg))) { // Already used.
4087 // Make sure we find consecutive registers.
4092 // Check to see if this register is allocatable (i.e. don't give out the
4095 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4096 if (!RC) { // Couldn't allocate this register.
4097 // Reset NumAllocated to make sure we return consecutive registers.
4103 // Okay, this register is good, we can use it.
4106 // If we allocated enough consecutive registers, succeed.
4107 if (NumAllocated == NumRegs) {
4108 unsigned RegStart = (i-NumAllocated)+1;
4109 unsigned RegEnd = i+1;
4110 // Mark all of the allocated registers used.
4111 for (unsigned i = RegStart; i != RegEnd; ++i)
4112 Regs.push_back(RegClassRegs[i]);
4114 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4115 OpInfo.ConstraintVT);
4116 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4121 // Otherwise, we couldn't allocate enough registers for this.
4125 /// visitInlineAsm - Handle a call to an InlineAsm object.
4127 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4128 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4130 /// ConstraintOperands - Information about all of the constraints.
4131 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4133 SDValue Chain = getRoot();
4136 std::set<unsigned> OutputRegs, InputRegs;
4138 // Do a prepass over the constraints, canonicalizing them, and building up the
4139 // ConstraintOperands list.
4140 std::vector<InlineAsm::ConstraintInfo>
4141 ConstraintInfos = IA->ParseConstraints();
4143 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4144 // constraint. If so, we can't let the register allocator allocate any input
4145 // registers, because it will not know to avoid the earlyclobbered output reg.
4146 bool SawEarlyClobber = false;
4148 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4149 unsigned ResNo = 0; // ResNo - The result number of the next output.
4150 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4151 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4152 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4154 MVT OpVT = MVT::Other;
4156 // Compute the value type for each operand.
4157 switch (OpInfo.Type) {
4158 case InlineAsm::isOutput:
4159 // Indirect outputs just consume an argument.
4160 if (OpInfo.isIndirect) {
4161 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4164 // The return value of the call is this value. As such, there is no
4165 // corresponding argument.
4166 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4167 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4168 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4170 assert(ResNo == 0 && "Asm only has one result!");
4171 OpVT = TLI.getValueType(CS.getType());
4175 case InlineAsm::isInput:
4176 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4178 case InlineAsm::isClobber:
4183 // If this is an input or an indirect output, process the call argument.
4184 // BasicBlocks are labels, currently appearing only in asm's.
4185 if (OpInfo.CallOperandVal) {
4186 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4187 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4189 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4190 const Type *OpTy = OpInfo.CallOperandVal->getType();
4191 // If this is an indirect operand, the operand is a pointer to the
4193 if (OpInfo.isIndirect)
4194 OpTy = cast<PointerType>(OpTy)->getElementType();
4196 // If OpTy is not a single value, it may be a struct/union that we
4197 // can tile with integers.
4198 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4199 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4207 OpTy = IntegerType::get(BitSize);
4212 OpVT = TLI.getValueType(OpTy, true);
4216 OpInfo.ConstraintVT = OpVT;
4218 // Compute the constraint code and ConstraintType to use.
4219 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4221 // Keep track of whether we see an earlyclobber.
4222 SawEarlyClobber |= OpInfo.isEarlyClobber;
4224 // If we see a clobber of a register, it is an early clobber.
4225 if (!SawEarlyClobber &&
4226 OpInfo.Type == InlineAsm::isClobber &&
4227 OpInfo.ConstraintType == TargetLowering::C_Register) {
4228 // Note that we want to ignore things that we don't trick here, like
4229 // dirflag, fpsr, flags, etc.
4230 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4231 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4232 OpInfo.ConstraintVT);
4233 if (PhysReg.first || PhysReg.second) {
4234 // This is a register we know of.
4235 SawEarlyClobber = true;
4239 // If this is a memory input, and if the operand is not indirect, do what we
4240 // need to to provide an address for the memory input.
4241 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4242 !OpInfo.isIndirect) {
4243 assert(OpInfo.Type == InlineAsm::isInput &&
4244 "Can only indirectify direct input operands!");
4246 // Memory operands really want the address of the value. If we don't have
4247 // an indirect input, put it in the constpool if we can, otherwise spill
4248 // it to a stack slot.
4250 // If the operand is a float, integer, or vector constant, spill to a
4251 // constant pool entry to get its address.
4252 Value *OpVal = OpInfo.CallOperandVal;
4253 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4254 isa<ConstantVector>(OpVal)) {
4255 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4256 TLI.getPointerTy());
4258 // Otherwise, create a stack slot and emit a store to it before the
4260 const Type *Ty = OpVal->getType();
4261 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4262 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4263 MachineFunction &MF = DAG.getMachineFunction();
4264 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4265 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4266 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4267 OpInfo.CallOperand = StackSlot;
4270 // There is no longer a Value* corresponding to this operand.
4271 OpInfo.CallOperandVal = 0;
4272 // It is now an indirect operand.
4273 OpInfo.isIndirect = true;
4276 // If this constraint is for a specific register, allocate it before
4278 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4279 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4281 ConstraintInfos.clear();
4284 // Second pass - Loop over all of the operands, assigning virtual or physregs
4285 // to registerclass operands.
4286 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4287 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4289 // C_Register operands have already been allocated, Other/Memory don't need
4291 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4292 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4295 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4296 std::vector<SDValue> AsmNodeOperands;
4297 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
4298 AsmNodeOperands.push_back(
4299 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4302 // Loop over all of the inputs, copying the operand values into the
4303 // appropriate registers and processing the output regs.
4304 RegsForValue RetValRegs;
4306 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4307 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4309 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4310 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4312 switch (OpInfo.Type) {
4313 case InlineAsm::isOutput: {
4314 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4315 OpInfo.ConstraintType != TargetLowering::C_Register) {
4316 // Memory output, or 'other' output (e.g. 'X' constraint).
4317 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4319 // Add information to the INLINEASM node to know about this output.
4320 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4321 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4322 TLI.getPointerTy()));
4323 AsmNodeOperands.push_back(OpInfo.CallOperand);
4327 // Otherwise, this is a register or register class output.
4329 // Copy the output from the appropriate register. Find a register that
4331 if (OpInfo.AssignedRegs.Regs.empty()) {
4332 cerr << "Couldn't allocate output reg for constraint '"
4333 << OpInfo.ConstraintCode << "'!\n";
4337 // If this is an indirect operand, store through the pointer after the
4339 if (OpInfo.isIndirect) {
4340 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4341 OpInfo.CallOperandVal));
4343 // This is the result value of the call.
4344 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4345 // Concatenate this output onto the outputs list.
4346 RetValRegs.append(OpInfo.AssignedRegs);
4349 // Add information to the INLINEASM node to know that this register is
4351 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4355 case InlineAsm::isInput: {
4356 SDValue InOperandVal = OpInfo.CallOperand;
4358 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4359 // If this is required to match an output register we have already set,
4360 // just use its register.
4361 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4363 // Scan until we find the definition we already emitted of this operand.
4364 // When we find it, create a RegsForValue operand.
4365 unsigned CurOp = 2; // The first operand.
4366 for (; OperandNo; --OperandNo) {
4367 // Advance to the next operand.
4369 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4370 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4371 (NumOps & 7) == 4 /*MEM*/) &&
4372 "Skipped past definitions?");
4373 CurOp += (NumOps>>3)+1;
4377 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4378 if ((NumOps & 7) == 2 /*REGDEF*/) {
4379 // Add NumOps>>3 registers to MatchedRegs.
4380 RegsForValue MatchedRegs;
4381 MatchedRegs.TLI = &TLI;
4382 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4383 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4384 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4386 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4387 MatchedRegs.Regs.push_back(Reg);
4390 // Use the produced MatchedRegs object to
4391 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4392 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4395 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4396 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4397 // Add information to the INLINEASM node to know about this input.
4398 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4399 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4400 TLI.getPointerTy()));
4401 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4406 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4407 assert(!OpInfo.isIndirect &&
4408 "Don't know how to handle indirect other inputs yet!");
4410 std::vector<SDValue> Ops;
4411 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4414 cerr << "Invalid operand for inline asm constraint '"
4415 << OpInfo.ConstraintCode << "'!\n";
4419 // Add information to the INLINEASM node to know about this input.
4420 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4421 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4422 TLI.getPointerTy()));
4423 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4425 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4426 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4427 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4428 "Memory operands expect pointer values");
4430 // Add information to the INLINEASM node to know about this input.
4431 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4432 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4433 TLI.getPointerTy()));
4434 AsmNodeOperands.push_back(InOperandVal);
4438 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4439 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4440 "Unknown constraint type!");
4441 assert(!OpInfo.isIndirect &&
4442 "Don't know how to handle indirect register inputs yet!");
4444 // Copy the input into the appropriate registers.
4445 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4446 "Couldn't allocate input reg!");
4448 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4450 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4454 case InlineAsm::isClobber: {
4455 // Add the clobbered value to the operand list, so that the register
4456 // allocator is aware that the physreg got clobbered.
4457 if (!OpInfo.AssignedRegs.Regs.empty())
4458 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4465 // Finish up input operands.
4466 AsmNodeOperands[0] = Chain;
4467 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4469 Chain = DAG.getNode(ISD::INLINEASM,
4470 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4471 &AsmNodeOperands[0], AsmNodeOperands.size());
4472 Flag = Chain.getValue(1);
4474 // If this asm returns a register value, copy the result from that register
4475 // and set it as the value of the call.
4476 if (!RetValRegs.Regs.empty()) {
4477 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4479 // If any of the results of the inline asm is a vector, it may have the
4480 // wrong width/num elts. This can happen for register classes that can
4481 // contain multiple different value types. The preg or vreg allocated may
4482 // not have the same VT as was expected. Convert it to the right type with
4484 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4485 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4486 if (Val.Val->getValueType(i).isVector())
4487 Val = DAG.getNode(ISD::BIT_CONVERT,
4488 TLI.getValueType(ResSTy->getElementType(i)), Val);
4491 if (Val.getValueType().isVector())
4492 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4496 setValue(CS.getInstruction(), Val);
4499 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
4501 // Process indirect outputs, first output all of the flagged copies out of
4503 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4504 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4505 Value *Ptr = IndirectStoresToEmit[i].second;
4506 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4507 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4510 // Emit the non-flagged stores from the physregs.
4511 SmallVector<SDValue, 8> OutChains;
4512 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4513 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4514 getValue(StoresToEmit[i].second),
4515 StoresToEmit[i].second, 0));
4516 if (!OutChains.empty())
4517 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4518 &OutChains[0], OutChains.size());
4523 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4524 SDValue Src = getValue(I.getOperand(0));
4526 MVT IntPtr = TLI.getPointerTy();
4528 if (IntPtr.bitsLT(Src.getValueType()))
4529 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4530 else if (IntPtr.bitsGT(Src.getValueType()))
4531 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4533 // Scale the source by the type size.
4534 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4535 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4536 Src, DAG.getIntPtrConstant(ElementSize));
4538 TargetLowering::ArgListTy Args;
4539 TargetLowering::ArgListEntry Entry;
4541 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4542 Args.push_back(Entry);
4544 std::pair<SDValue,SDValue> Result =
4545 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4546 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4547 setValue(&I, Result.first); // Pointers always fit in registers
4548 DAG.setRoot(Result.second);
4551 void SelectionDAGLowering::visitFree(FreeInst &I) {
4552 TargetLowering::ArgListTy Args;
4553 TargetLowering::ArgListEntry Entry;
4554 Entry.Node = getValue(I.getOperand(0));
4555 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4556 Args.push_back(Entry);
4557 MVT IntPtr = TLI.getPointerTy();
4558 std::pair<SDValue,SDValue> Result =
4559 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4560 CallingConv::C, true,
4561 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4562 DAG.setRoot(Result.second);
4565 // EmitInstrWithCustomInserter - This method should be implemented by targets
4566 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4567 // instructions are special in various ways, which require special support to
4568 // insert. The specified MachineInstr is created but not inserted into any
4569 // basic blocks, and the scheduler passes ownership of it to this method.
4570 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4571 MachineBasicBlock *MBB) {
4572 cerr << "If a target marks an instruction with "
4573 << "'usesCustomDAGSchedInserter', it must implement "
4574 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4579 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4580 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4581 getValue(I.getOperand(1)),
4582 DAG.getSrcValue(I.getOperand(1))));
4585 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4586 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4587 getValue(I.getOperand(0)),
4588 DAG.getSrcValue(I.getOperand(0)));
4590 DAG.setRoot(V.getValue(1));
4593 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4594 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4595 getValue(I.getOperand(1)),
4596 DAG.getSrcValue(I.getOperand(1))));
4599 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4600 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4601 getValue(I.getOperand(1)),
4602 getValue(I.getOperand(2)),
4603 DAG.getSrcValue(I.getOperand(1)),
4604 DAG.getSrcValue(I.getOperand(2))));
4607 /// TargetLowering::LowerArguments - This is the default LowerArguments
4608 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4609 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4610 /// integrated into SDISel.
4611 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4612 SmallVectorImpl<SDValue> &ArgValues) {
4613 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4614 SmallVector<SDValue, 3+16> Ops;
4615 Ops.push_back(DAG.getRoot());
4616 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4617 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4619 // Add one result value for each formal argument.
4620 SmallVector<MVT, 16> RetVals;
4622 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4624 SmallVector<MVT, 4> ValueVTs;
4625 ComputeValueVTs(*this, I->getType(), ValueVTs);
4626 for (unsigned Value = 0, NumValues = ValueVTs.size();
4627 Value != NumValues; ++Value) {
4628 MVT VT = ValueVTs[Value];
4629 const Type *ArgTy = VT.getTypeForMVT();
4630 ISD::ArgFlagsTy Flags;
4631 unsigned OriginalAlignment =
4632 getTargetData()->getABITypeAlignment(ArgTy);
4634 if (F.paramHasAttr(j, ParamAttr::ZExt))
4636 if (F.paramHasAttr(j, ParamAttr::SExt))
4638 if (F.paramHasAttr(j, ParamAttr::InReg))
4640 if (F.paramHasAttr(j, ParamAttr::StructRet))
4642 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4644 const PointerType *Ty = cast<PointerType>(I->getType());
4645 const Type *ElementTy = Ty->getElementType();
4646 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4647 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4648 // For ByVal, alignment should be passed from FE. BE will guess if
4649 // this info is not there but there are cases it cannot get right.
4650 if (F.getParamAlignment(j))
4651 FrameAlign = F.getParamAlignment(j);
4652 Flags.setByValAlign(FrameAlign);
4653 Flags.setByValSize(FrameSize);
4655 if (F.paramHasAttr(j, ParamAttr::Nest))
4657 Flags.setOrigAlign(OriginalAlignment);
4659 MVT RegisterVT = getRegisterType(VT);
4660 unsigned NumRegs = getNumRegisters(VT);
4661 for (unsigned i = 0; i != NumRegs; ++i) {
4662 RetVals.push_back(RegisterVT);
4663 ISD::ArgFlagsTy MyFlags = Flags;
4664 if (NumRegs > 1 && i == 0)
4666 // if it isn't first piece, alignment must be 1
4668 MyFlags.setOrigAlign(1);
4669 Ops.push_back(DAG.getArgFlags(MyFlags));
4674 RetVals.push_back(MVT::Other);
4677 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4678 DAG.getVTList(&RetVals[0], RetVals.size()),
4679 &Ops[0], Ops.size()).Val;
4681 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4682 // allows exposing the loads that may be part of the argument access to the
4683 // first DAGCombiner pass.
4684 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
4686 // The number of results should match up, except that the lowered one may have
4687 // an extra flag result.
4688 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4689 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4690 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4691 && "Lowering produced unexpected number of results!");
4693 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
4694 if (Result != TmpRes.Val && Result->use_empty()) {
4695 HandleSDNode Dummy(DAG.getRoot());
4696 DAG.RemoveDeadNode(Result);
4699 Result = TmpRes.Val;
4701 unsigned NumArgRegs = Result->getNumValues() - 1;
4702 DAG.setRoot(SDValue(Result, NumArgRegs));
4704 // Set up the return result vector.
4707 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4709 SmallVector<MVT, 4> ValueVTs;
4710 ComputeValueVTs(*this, I->getType(), ValueVTs);
4711 for (unsigned Value = 0, NumValues = ValueVTs.size();
4712 Value != NumValues; ++Value) {
4713 MVT VT = ValueVTs[Value];
4714 MVT PartVT = getRegisterType(VT);
4716 unsigned NumParts = getNumRegisters(VT);
4717 SmallVector<SDValue, 4> Parts(NumParts);
4718 for (unsigned j = 0; j != NumParts; ++j)
4719 Parts[j] = SDValue(Result, i++);
4721 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4722 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4723 AssertOp = ISD::AssertSext;
4724 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4725 AssertOp = ISD::AssertZext;
4727 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4731 assert(i == NumArgRegs && "Argument register count mismatch!");
4735 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4736 /// implementation, which just inserts an ISD::CALL node, which is later custom
4737 /// lowered by the target to something concrete. FIXME: When all targets are
4738 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4739 std::pair<SDValue, SDValue>
4740 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
4741 bool RetSExt, bool RetZExt, bool isVarArg,
4742 unsigned CallingConv, bool isTailCall,
4744 ArgListTy &Args, SelectionDAG &DAG) {
4745 SmallVector<SDValue, 32> Ops;
4746 Ops.push_back(Chain); // Op#0 - Chain
4747 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4748 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4749 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4750 Ops.push_back(Callee);
4752 // Handle all of the outgoing arguments.
4753 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4754 SmallVector<MVT, 4> ValueVTs;
4755 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4756 for (unsigned Value = 0, NumValues = ValueVTs.size();
4757 Value != NumValues; ++Value) {
4758 MVT VT = ValueVTs[Value];
4759 const Type *ArgTy = VT.getTypeForMVT();
4760 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4761 ISD::ArgFlagsTy Flags;
4762 unsigned OriginalAlignment =
4763 getTargetData()->getABITypeAlignment(ArgTy);
4769 if (Args[i].isInReg)
4773 if (Args[i].isByVal) {
4775 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4776 const Type *ElementTy = Ty->getElementType();
4777 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4778 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4779 // For ByVal, alignment should come from FE. BE will guess if this
4780 // info is not there but there are cases it cannot get right.
4781 if (Args[i].Alignment)
4782 FrameAlign = Args[i].Alignment;
4783 Flags.setByValAlign(FrameAlign);
4784 Flags.setByValSize(FrameSize);
4788 Flags.setOrigAlign(OriginalAlignment);
4790 MVT PartVT = getRegisterType(VT);
4791 unsigned NumParts = getNumRegisters(VT);
4792 SmallVector<SDValue, 4> Parts(NumParts);
4793 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4796 ExtendKind = ISD::SIGN_EXTEND;
4797 else if (Args[i].isZExt)
4798 ExtendKind = ISD::ZERO_EXTEND;
4800 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4802 for (unsigned i = 0; i != NumParts; ++i) {
4803 // if it isn't first piece, alignment must be 1
4804 ISD::ArgFlagsTy MyFlags = Flags;
4805 if (NumParts > 1 && i == 0)
4808 MyFlags.setOrigAlign(1);
4810 Ops.push_back(Parts[i]);
4811 Ops.push_back(DAG.getArgFlags(MyFlags));
4816 // Figure out the result value types. We start by making a list of
4817 // the potentially illegal return value types.
4818 SmallVector<MVT, 4> LoweredRetTys;
4819 SmallVector<MVT, 4> RetTys;
4820 ComputeValueVTs(*this, RetTy, RetTys);
4822 // Then we translate that to a list of legal types.
4823 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4825 MVT RegisterVT = getRegisterType(VT);
4826 unsigned NumRegs = getNumRegisters(VT);
4827 for (unsigned i = 0; i != NumRegs; ++i)
4828 LoweredRetTys.push_back(RegisterVT);
4831 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4833 // Create the CALL node.
4834 SDValue Res = DAG.getNode(ISD::CALL,
4835 DAG.getVTList(&LoweredRetTys[0],
4836 LoweredRetTys.size()),
4837 &Ops[0], Ops.size());
4838 Chain = Res.getValue(LoweredRetTys.size() - 1);
4840 // Gather up the call result into a single value.
4841 if (RetTy != Type::VoidTy) {
4842 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4845 AssertOp = ISD::AssertSext;
4847 AssertOp = ISD::AssertZext;
4849 SmallVector<SDValue, 4> ReturnValues;
4851 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4853 MVT RegisterVT = getRegisterType(VT);
4854 unsigned NumRegs = getNumRegisters(VT);
4855 unsigned RegNoEnd = NumRegs + RegNo;
4856 SmallVector<SDValue, 4> Results;
4857 for (; RegNo != RegNoEnd; ++RegNo)
4858 Results.push_back(Res.getValue(RegNo));
4859 SDValue ReturnValue =
4860 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4862 ReturnValues.push_back(ReturnValue);
4864 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4865 &ReturnValues[0], ReturnValues.size());
4868 return std::make_pair(Res, Chain);
4871 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4872 assert(0 && "LowerOperation not implemented for this target!");
4878 //===----------------------------------------------------------------------===//
4879 // SelectionDAGISel code
4880 //===----------------------------------------------------------------------===//
4882 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4883 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4886 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4887 AU.addRequired<AliasAnalysis>();
4888 AU.addRequired<GCModuleInfo>();
4889 AU.setPreservesAll();
4892 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4893 // Get alias analysis for load/store combining.
4894 AA = &getAnalysis<AliasAnalysis>();
4896 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4897 if (MF.getFunction()->hasGC())
4898 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
4901 RegInfo = &MF.getRegInfo();
4902 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4904 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4906 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4907 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4908 // Mark landing pad.
4909 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4911 SelectAllBasicBlocks(Fn, MF, FuncInfo);
4913 // Add function live-ins to entry block live-in set.
4914 BasicBlock *EntryBB = &Fn.getEntryBlock();
4915 BB = FuncInfo.MBBMap[EntryBB];
4916 if (!RegInfo->livein_empty())
4917 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4918 E = RegInfo->livein_end(); I != E; ++I)
4919 BB->addLiveIn(I->first);
4922 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4923 "Not all catch info was assigned to a landing pad!");
4929 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4930 SDValue Op = getValue(V);
4931 assert((Op.getOpcode() != ISD::CopyFromReg ||
4932 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4933 "Copy from a reg to the same reg!");
4934 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4936 RegsForValue RFV(TLI, Reg, V->getType());
4937 SDValue Chain = DAG.getEntryNode();
4938 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4939 PendingExports.push_back(Chain);
4942 void SelectionDAGISel::
4943 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4944 // If this is the entry block, emit arguments.
4945 Function &F = *LLVMBB->getParent();
4946 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4947 SDValue OldRoot = SDL.DAG.getRoot();
4948 SmallVector<SDValue, 16> Args;
4949 TLI.LowerArguments(F, SDL.DAG, Args);
4952 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4954 SmallVector<MVT, 4> ValueVTs;
4955 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4956 unsigned NumValues = ValueVTs.size();
4957 if (!AI->use_empty()) {
4958 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
4959 // If this argument is live outside of the entry block, insert a copy from
4960 // whereever we got it to the vreg that other BB's will reference it as.
4961 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4962 if (VMI != FuncInfo.ValueMap.end()) {
4963 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4969 // Finally, if the target has anything special to do, allow it to do so.
4970 // FIXME: this should insert code into the DAG!
4971 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4974 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4975 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4976 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4977 if (isSelector(I)) {
4978 // Apply the catch info to DestBB.
4979 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4981 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4982 FLI.CatchInfoFound.insert(I);
4987 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4988 /// whether object offset >= 0.
4990 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
4991 if (!isa<FrameIndexSDNode>(Op)) return false;
4993 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4994 int FrameIdx = FrameIdxNode->getIndex();
4995 return MFI->isFixedObjectIndex(FrameIdx) &&
4996 MFI->getObjectOffset(FrameIdx) >= 0;
4999 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
5000 /// possibly be overwritten when lowering the outgoing arguments in a tail
5001 /// call. Currently the implementation of this call is very conservative and
5002 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
5003 /// virtual registers would be overwritten by direct lowering.
5004 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
5005 MachineFrameInfo * MFI) {
5006 RegisterSDNode * OpReg = NULL;
5007 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
5008 (Op.getOpcode()== ISD::CopyFromReg &&
5009 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
5010 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
5011 (Op.getOpcode() == ISD::LOAD &&
5012 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
5013 (Op.getOpcode() == ISD::MERGE_VALUES &&
5014 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
5015 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
5021 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
5022 /// DAG and fixes their tailcall attribute operand.
5023 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
5024 TargetLowering& TLI) {
5025 SDNode * Ret = NULL;
5026 SDValue Terminator = DAG.getRoot();
5029 if (Terminator.getOpcode() == ISD::RET) {
5030 Ret = Terminator.Val;
5033 // Fix tail call attribute of CALL nodes.
5034 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5035 BI = DAG.allnodes_end(); BI != BE; ) {
5037 if (BI->getOpcode() == ISD::CALL) {
5038 SDValue OpRet(Ret, 0);
5039 SDValue OpCall(BI, 0);
5040 bool isMarkedTailCall =
5041 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5042 // If CALL node has tail call attribute set to true and the call is not
5043 // eligible (no RET or the target rejects) the attribute is fixed to
5044 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5045 // must correctly identify tail call optimizable calls.
5046 if (!isMarkedTailCall) continue;
5048 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5049 // Not eligible. Mark CALL node as non tail call.
5050 SmallVector<SDValue, 32> Ops;
5052 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5053 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5057 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5059 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5061 // Look for tail call clobbered arguments. Emit a series of
5062 // copyto/copyfrom virtual register nodes to protect them.
5063 SmallVector<SDValue, 32> Ops;
5064 SDValue Chain = OpCall.getOperand(0), InFlag;
5066 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5067 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5069 if (idx > 4 && (idx % 2)) {
5070 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5071 getArgFlags().isByVal();
5072 MachineFunction &MF = DAG.getMachineFunction();
5073 MachineFrameInfo *MFI = MF.getFrameInfo();
5075 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5076 MVT VT = Arg.getValueType();
5077 unsigned VReg = MF.getRegInfo().
5078 createVirtualRegister(TLI.getRegClassFor(VT));
5079 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5080 InFlag = Chain.getValue(1);
5081 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5082 Chain = Arg.getValue(1);
5083 InFlag = Arg.getValue(2);
5088 // Link in chain of CopyTo/CopyFromReg.
5090 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5096 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5097 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5098 FunctionLoweringInfo &FuncInfo) {
5099 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GFI);
5100 BB = FuncInfo.MBBMap[LLVMBB];
5102 // Before doing SelectionDAG ISel, see if FastISel has been requested.
5103 // FastISel doesn't currently support entry blocks, because that
5104 // requires special handling for arguments. And it doesn't support EH
5105 // landing pads, which also require special handling.
5106 // For now, also exclude blocks with terminators that aren't
5107 // unconditional branches.
5108 BasicBlock::iterator Begin = LLVMBB->begin();
5109 if (EnableFastISel &&
5110 LLVMBB != &LLVMBB->getParent()->getEntryBlock() &&
5111 !BB->isLandingPad() &&
5112 isa<BranchInst>(LLVMBB->getTerminator()) &&
5113 cast<BranchInst>(LLVMBB->getTerminator())->isUnconditional()) {
5114 if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
5115 Begin = F->SelectInstructions(Begin, LLVMBB->end(),
5116 FuncInfo.ValueMap, BB);
5118 // Clean up the FastISel object. TODO: Reorganize what data is
5119 // stored in the FastISel class itself and what is merely passed
5120 // to the SelectInstructions method, and then move the creation
5121 // and deletion of the FastISel object up so that it is only
5122 // done once per MachineFunction.
5125 if (Begin == LLVMBB->end())
5126 // The "fast" selector selected the entire block, so we're done.
5129 if (!DisableFastISelAbort) {
5130 // The "fast" selector couldn't handle something and bailed.
5131 // For the purpose of debugging, just abort.
5135 assert(0 && "FastISel didn't select the entire block");
5141 // Lower any arguments needed in this block if this is the entry block.
5142 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5143 LowerArguments(LLVMBB, SDL);
5145 SDL.setCurrentBasicBlock(BB);
5147 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5149 if (MMI && BB->isLandingPad()) {
5150 // Add a label to mark the beginning of the landing pad. Deletion of the
5151 // landing pad can thus be detected via the MachineModuleInfo.
5152 unsigned LabelID = MMI->addLandingPad(BB);
5153 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
5155 // Mark exception register as live in.
5156 unsigned Reg = TLI.getExceptionAddressRegister();
5157 if (Reg) BB->addLiveIn(Reg);
5159 // Mark exception selector register as live in.
5160 Reg = TLI.getExceptionSelectorRegister();
5161 if (Reg) BB->addLiveIn(Reg);
5163 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5164 // function and list of typeids logically belong to the invoke (or, if you
5165 // like, the basic block containing the invoke), and need to be associated
5166 // with it in the dwarf exception handling tables. Currently however the
5167 // information is provided by an intrinsic (eh.selector) that can be moved
5168 // to unexpected places by the optimizers: if the unwind edge is critical,
5169 // then breaking it can result in the intrinsics being in the successor of
5170 // the landing pad, not the landing pad itself. This results in exceptions
5171 // not being caught because no typeids are associated with the invoke.
5172 // This may not be the only way things can go wrong, but it is the only way
5173 // we try to work around for the moment.
5174 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5176 if (Br && Br->isUnconditional()) { // Critical edge?
5177 BasicBlock::iterator I, E;
5178 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5183 // No catch info found - try to extract some from the successor.
5184 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5188 // Lower all of the non-terminator instructions.
5189 for (BasicBlock::iterator I = Begin, E = --LLVMBB->end();
5193 // Ensure that all instructions which are used outside of their defining
5194 // blocks are available as virtual registers. Invoke is handled elsewhere.
5195 for (BasicBlock::iterator I = Begin, E = LLVMBB->end(); I != E;++I)
5196 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5197 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5198 if (VMI != FuncInfo.ValueMap.end())
5199 SDL.CopyValueToVirtualRegister(I, VMI->second);
5202 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5203 // ensure constants are generated when needed. Remember the virtual registers
5204 // that need to be added to the Machine PHI nodes as input. We cannot just
5205 // directly add them, because expansion might result in multiple MBB's for one
5206 // BB. As such, the start of the BB might correspond to a different MBB than
5209 TerminatorInst *TI = LLVMBB->getTerminator();
5211 // Emit constants only once even if used by multiple PHI nodes.
5212 std::map<Constant*, unsigned> ConstantsOut;
5214 BitVector SuccsHandled;
5215 if (TI->getNumSuccessors())
5216 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5218 // Check successor nodes' PHI nodes that expect a constant to be available
5220 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5221 BasicBlock *SuccBB = TI->getSuccessor(succ);
5222 if (!isa<PHINode>(SuccBB->begin())) continue;
5223 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5225 // If this terminator has multiple identical successors (common for
5226 // switches), only handle each succ once.
5227 unsigned SuccMBBNo = SuccMBB->getNumber();
5228 if (SuccsHandled[SuccMBBNo]) continue;
5229 SuccsHandled[SuccMBBNo] = true;
5231 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5234 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5235 // nodes and Machine PHI nodes, but the incoming operands have not been
5237 for (BasicBlock::iterator I = SuccBB->begin();
5238 (PN = dyn_cast<PHINode>(I)); ++I) {
5239 // Ignore dead phi's.
5240 if (PN->use_empty()) continue;
5243 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5245 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5246 unsigned &RegOut = ConstantsOut[C];
5248 RegOut = FuncInfo.CreateRegForValue(C);
5249 SDL.CopyValueToVirtualRegister(C, RegOut);
5253 Reg = FuncInfo.ValueMap[PHIOp];
5255 assert(isa<AllocaInst>(PHIOp) &&
5256 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5257 "Didn't codegen value into a register!??");
5258 Reg = FuncInfo.CreateRegForValue(PHIOp);
5259 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5263 // Remember that this register needs to added to the machine PHI node as
5264 // the input for this MBB.
5265 SmallVector<MVT, 4> ValueVTs;
5266 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5267 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5268 MVT VT = ValueVTs[vti];
5269 unsigned NumRegisters = TLI.getNumRegisters(VT);
5270 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5271 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5272 Reg += NumRegisters;
5276 ConstantsOut.clear();
5278 // Lower the terminator after the copies are emitted.
5279 SDL.visit(*LLVMBB->getTerminator());
5281 // Copy over any CaseBlock records that may now exist due to SwitchInst
5282 // lowering, as well as any jump table information.
5283 SwitchCases.clear();
5284 SwitchCases = SDL.SwitchCases;
5286 JTCases = SDL.JTCases;
5287 BitTestCases.clear();
5288 BitTestCases = SDL.BitTestCases;
5290 // Make sure the root of the DAG is up-to-date.
5291 DAG.setRoot(SDL.getControlRoot());
5293 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5294 // with correct tailcall attribute so that the target can rely on the tailcall
5295 // attribute indicating whether the call is really eligible for tail call
5297 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5300 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5301 SmallPtrSet<SDNode*, 128> VisitedNodes;
5302 SmallVector<SDNode*, 128> Worklist;
5304 Worklist.push_back(DAG.getRoot().Val);
5310 while (!Worklist.empty()) {
5311 SDNode *N = Worklist.back();
5312 Worklist.pop_back();
5314 // If we've already seen this node, ignore it.
5315 if (!VisitedNodes.insert(N))
5318 // Otherwise, add all chain operands to the worklist.
5319 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5320 if (N->getOperand(i).getValueType() == MVT::Other)
5321 Worklist.push_back(N->getOperand(i).Val);
5323 // If this is a CopyToReg with a vreg dest, process it.
5324 if (N->getOpcode() != ISD::CopyToReg)
5327 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5328 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5331 // Ignore non-scalar or non-integer values.
5332 SDValue Src = N->getOperand(2);
5333 MVT SrcVT = Src.getValueType();
5334 if (!SrcVT.isInteger() || SrcVT.isVector())
5337 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5338 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5339 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5341 // Only install this information if it tells us something.
5342 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5343 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5344 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5345 if (DestReg >= FLI.LiveOutRegInfo.size())
5346 FLI.LiveOutRegInfo.resize(DestReg+1);
5347 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5348 LOI.NumSignBits = NumSignBits;
5349 LOI.KnownOne = NumSignBits;
5350 LOI.KnownZero = NumSignBits;
5355 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5356 std::string GroupName;
5357 if (TimePassesIsEnabled)
5358 GroupName = "Instruction Selection and Scheduling";
5359 std::string BlockName;
5360 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
5361 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
5362 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' +
5363 BB->getBasicBlock()->getName();
5365 DOUT << "Initial selection DAG:\n";
5368 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName);
5370 // Run the DAG combiner in pre-legalize mode.
5371 if (TimePassesIsEnabled) {
5372 NamedRegionTimer T("DAG Combining 1", GroupName);
5373 DAG.Combine(false, *AA, Fast);
5375 DAG.Combine(false, *AA, Fast);
5378 DOUT << "Optimized lowered selection DAG:\n";
5381 // Second step, hack on the DAG until it only uses operations and types that
5382 // the target supports.
5383 if (EnableLegalizeTypes) {// Enable this some day.
5384 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " +
5387 if (TimePassesIsEnabled) {
5388 NamedRegionTimer T("Type Legalization", GroupName);
5389 DAG.LegalizeTypes();
5391 DAG.LegalizeTypes();
5394 DOUT << "Type-legalized selection DAG:\n";
5397 // TODO: enable a dag combine pass here.
5400 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName);
5402 if (TimePassesIsEnabled) {
5403 NamedRegionTimer T("DAG Legalization", GroupName);
5409 DOUT << "Legalized selection DAG:\n";
5412 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName);
5414 // Run the DAG combiner in post-legalize mode.
5415 if (TimePassesIsEnabled) {
5416 NamedRegionTimer T("DAG Combining 2", GroupName);
5417 DAG.Combine(true, *AA, Fast);
5419 DAG.Combine(true, *AA, Fast);
5422 DOUT << "Optimized legalized selection DAG:\n";
5425 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
5427 if (!Fast && EnableValueProp)
5428 ComputeLiveOutVRegInfo(DAG);
5430 // Third, instruction select all of the operations to machine code, adding the
5431 // code to the MachineBasicBlock.
5432 if (TimePassesIsEnabled) {
5433 NamedRegionTimer T("Instruction Selection", GroupName);
5434 InstructionSelect(DAG);
5436 InstructionSelect(DAG);
5439 DOUT << "Selected selection DAG:\n";
5442 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName);
5444 // Schedule machine code.
5445 ScheduleDAG *Scheduler;
5446 if (TimePassesIsEnabled) {
5447 NamedRegionTimer T("Instruction Scheduling", GroupName);
5448 Scheduler = Schedule(DAG);
5450 Scheduler = Schedule(DAG);
5453 if (ViewSUnitDAGs) Scheduler->viewGraph();
5455 // Emit machine code to BB. This can change 'BB' to the last block being
5457 if (TimePassesIsEnabled) {
5458 NamedRegionTimer T("Instruction Creation", GroupName);
5459 BB = Scheduler->EmitSchedule();
5461 BB = Scheduler->EmitSchedule();
5464 // Free the scheduler state.
5465 if (TimePassesIsEnabled) {
5466 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
5472 // Perform target specific isel post processing.
5473 if (TimePassesIsEnabled) {
5474 NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
5475 InstructionSelectPostProcessing();
5477 InstructionSelectPostProcessing();
5480 DOUT << "Selected machine code:\n";
5484 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
5485 FunctionLoweringInfo &FuncInfo) {
5486 // Define NodeAllocator here so that memory allocation is reused for
5487 // each basic block.
5488 NodeAllocatorType NodeAllocator;
5490 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5491 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
5492 BasicBlock *LLVMBB = &*I;
5493 PHINodesToUpdate.clear();
5495 SelectBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
5496 FinishBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
5501 SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5502 FunctionLoweringInfo &FuncInfo,
5503 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5504 NodeAllocatorType &NodeAllocator) {
5505 SelectionDAG DAG(TLI, MF, FuncInfo,
5506 getAnalysisToUpdate<MachineModuleInfo>(),
5510 // First step, lower LLVM code to some DAG. This DAG may use operations and
5511 // types that are not supported by the target.
5512 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5514 // Second step, emit the lowered DAG as machine code.
5515 CodeGenAndEmitDAG(DAG);
5519 SelectionDAGISel::FinishBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5520 FunctionLoweringInfo &FuncInfo,
5521 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5522 NodeAllocatorType &NodeAllocator) {
5523 DOUT << "Total amount of phi nodes to update: "
5524 << PHINodesToUpdate.size() << "\n";
5525 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5526 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5527 << ", " << PHINodesToUpdate[i].second << ")\n";);
5529 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5530 // PHI nodes in successors.
5531 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5532 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5533 MachineInstr *PHI = PHINodesToUpdate[i].first;
5534 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5535 "This is not a machine PHI node that we are updating!");
5536 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5538 PHI->addOperand(MachineOperand::CreateMBB(BB));
5543 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5544 // Lower header first, if it wasn't already lowered
5545 if (!BitTestCases[i].Emitted) {
5546 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5547 getAnalysisToUpdate<MachineModuleInfo>(),
5550 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GFI);
5551 // Set the current basic block to the mbb we wish to insert the code into
5552 BB = BitTestCases[i].Parent;
5553 HSDL.setCurrentBasicBlock(BB);
5555 HSDL.visitBitTestHeader(BitTestCases[i]);
5556 HSDAG.setRoot(HSDL.getRoot());
5557 CodeGenAndEmitDAG(HSDAG);
5560 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5561 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5562 getAnalysisToUpdate<MachineModuleInfo>(),
5565 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GFI);
5566 // Set the current basic block to the mbb we wish to insert the code into
5567 BB = BitTestCases[i].Cases[j].ThisBB;
5568 BSDL.setCurrentBasicBlock(BB);
5571 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5572 BitTestCases[i].Reg,
5573 BitTestCases[i].Cases[j]);
5575 BSDL.visitBitTestCase(BitTestCases[i].Default,
5576 BitTestCases[i].Reg,
5577 BitTestCases[i].Cases[j]);
5580 BSDAG.setRoot(BSDL.getRoot());
5581 CodeGenAndEmitDAG(BSDAG);
5585 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5586 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5587 MachineBasicBlock *PHIBB = PHI->getParent();
5588 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5589 "This is not a machine PHI node that we are updating!");
5590 // This is "default" BB. We have two jumps to it. From "header" BB and
5591 // from last "case" BB.
5592 if (PHIBB == BitTestCases[i].Default) {
5593 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5595 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5596 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5598 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5601 // One of "cases" BB.
5602 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5603 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5604 if (cBB->succ_end() !=
5605 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5606 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5608 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5614 // If the JumpTable record is filled in, then we need to emit a jump table.
5615 // Updating the PHI nodes is tricky in this case, since we need to determine
5616 // whether the PHI is a successor of the range check MBB or the jump table MBB
5617 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5618 // Lower header first, if it wasn't already lowered
5619 if (!JTCases[i].first.Emitted) {
5620 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5621 getAnalysisToUpdate<MachineModuleInfo>(),
5624 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GFI);
5625 // Set the current basic block to the mbb we wish to insert the code into
5626 BB = JTCases[i].first.HeaderBB;
5627 HSDL.setCurrentBasicBlock(BB);
5629 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5630 HSDAG.setRoot(HSDL.getRoot());
5631 CodeGenAndEmitDAG(HSDAG);
5634 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5635 getAnalysisToUpdate<MachineModuleInfo>(),
5638 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GFI);
5639 // Set the current basic block to the mbb we wish to insert the code into
5640 BB = JTCases[i].second.MBB;
5641 JSDL.setCurrentBasicBlock(BB);
5643 JSDL.visitJumpTable(JTCases[i].second);
5644 JSDAG.setRoot(JSDL.getRoot());
5645 CodeGenAndEmitDAG(JSDAG);
5648 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5649 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5650 MachineBasicBlock *PHIBB = PHI->getParent();
5651 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5652 "This is not a machine PHI node that we are updating!");
5653 // "default" BB. We can go there only from header BB.
5654 if (PHIBB == JTCases[i].second.Default) {
5655 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5657 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5659 // JT BB. Just iterate over successors here
5660 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5661 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5663 PHI->addOperand(MachineOperand::CreateMBB(BB));
5668 // If the switch block involved a branch to one of the actual successors, we
5669 // need to update PHI nodes in that block.
5670 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5671 MachineInstr *PHI = PHINodesToUpdate[i].first;
5672 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5673 "This is not a machine PHI node that we are updating!");
5674 if (BB->isSuccessor(PHI->getParent())) {
5675 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5677 PHI->addOperand(MachineOperand::CreateMBB(BB));
5681 // If we generated any switch lowering information, build and codegen any
5682 // additional DAGs necessary.
5683 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5684 SelectionDAG SDAG(TLI, MF, FuncInfo,
5685 getAnalysisToUpdate<MachineModuleInfo>(),
5688 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GFI);
5690 // Set the current basic block to the mbb we wish to insert the code into
5691 BB = SwitchCases[i].ThisBB;
5692 SDL.setCurrentBasicBlock(BB);
5695 SDL.visitSwitchCase(SwitchCases[i]);
5696 SDAG.setRoot(SDL.getRoot());
5697 CodeGenAndEmitDAG(SDAG);
5699 // Handle any PHI nodes in successors of this chunk, as if we were coming
5700 // from the original BB before switch expansion. Note that PHI nodes can
5701 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5702 // handle them the right number of times.
5703 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5704 for (MachineBasicBlock::iterator Phi = BB->begin();
5705 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5706 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5707 for (unsigned pn = 0; ; ++pn) {
5708 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5709 if (PHINodesToUpdate[pn].first == Phi) {
5710 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5712 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5718 // Don't process RHS if same block as LHS.
5719 if (BB == SwitchCases[i].FalseBB)
5720 SwitchCases[i].FalseBB = 0;
5722 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5723 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5724 SwitchCases[i].FalseBB = 0;
5726 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5731 /// Schedule - Pick a safe ordering for instructions for each
5732 /// target node in the graph.
5734 ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
5735 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5739 RegisterScheduler::setDefault(Ctor);
5742 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, Fast);
5749 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5750 return new HazardRecognizer();
5753 //===----------------------------------------------------------------------===//
5754 // Helper functions used by the generated instruction selector.
5755 //===----------------------------------------------------------------------===//
5756 // Calls to these methods are generated by tblgen.
5758 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5759 /// the dag combiner simplified the 255, we still want to match. RHS is the
5760 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5761 /// specified in the .td file (e.g. 255).
5762 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
5763 int64_t DesiredMaskS) const {
5764 const APInt &ActualMask = RHS->getAPIntValue();
5765 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5767 // If the actual mask exactly matches, success!
5768 if (ActualMask == DesiredMask)
5771 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5772 if (ActualMask.intersects(~DesiredMask))
5775 // Otherwise, the DAG Combiner may have proven that the value coming in is
5776 // either already zero or is not demanded. Check for known zero input bits.
5777 APInt NeededMask = DesiredMask & ~ActualMask;
5778 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5781 // TODO: check to see if missing bits are just not demanded.
5783 // Otherwise, this pattern doesn't match.
5787 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5788 /// the dag combiner simplified the 255, we still want to match. RHS is the
5789 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5790 /// specified in the .td file (e.g. 255).
5791 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
5792 int64_t DesiredMaskS) const {
5793 const APInt &ActualMask = RHS->getAPIntValue();
5794 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5796 // If the actual mask exactly matches, success!
5797 if (ActualMask == DesiredMask)
5800 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5801 if (ActualMask.intersects(~DesiredMask))
5804 // Otherwise, the DAG Combiner may have proven that the value coming in is
5805 // either already zero or is not demanded. Check for known zero input bits.
5806 APInt NeededMask = DesiredMask & ~ActualMask;
5808 APInt KnownZero, KnownOne;
5809 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5811 // If all the missing bits in the or are already known to be set, match!
5812 if ((NeededMask & KnownOne) == NeededMask)
5815 // TODO: check to see if missing bits are just not demanded.
5817 // Otherwise, this pattern doesn't match.
5822 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5823 /// by tblgen. Others should not call it.
5824 void SelectionDAGISel::
5825 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) {
5826 std::vector<SDValue> InOps;
5827 std::swap(InOps, Ops);
5829 Ops.push_back(InOps[0]); // input chain.
5830 Ops.push_back(InOps[1]); // input asm string.
5832 unsigned i = 2, e = InOps.size();
5833 if (InOps[e-1].getValueType() == MVT::Flag)
5834 --e; // Don't process a flag operand if it is here.
5837 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5838 if ((Flags & 7) != 4 /*MEM*/) {
5839 // Just skip over this operand, copying the operands verbatim.
5840 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5841 i += (Flags >> 3) + 1;
5843 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5844 // Otherwise, this is a memory operand. Ask the target to select it.
5845 std::vector<SDValue> SelOps;
5846 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5847 cerr << "Could not match memory address. Inline asm failure!\n";
5851 // Add this to the output node.
5852 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5853 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5855 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5860 // Add the flag input back if present.
5861 if (e != InOps.size())
5862 Ops.push_back(InOps.back());
5865 char SelectionDAGISel::ID = 0;