1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the post legalize types"
84 " dag combine pass"));
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewDAGCombineLT = false,
99 ViewISelDAGs = false, ViewSchedDAGs = false,
100 ViewSUnitDAGs = false;
103 //===---------------------------------------------------------------------===//
105 /// RegisterScheduler class - Track the registration of instruction schedulers.
107 //===---------------------------------------------------------------------===//
108 MachinePassRegistry RegisterScheduler::Registry;
110 //===---------------------------------------------------------------------===//
112 /// ISHeuristic command line option for instruction schedulers.
114 //===---------------------------------------------------------------------===//
115 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
116 RegisterPassParser<RegisterScheduler> >
117 ISHeuristic("pre-RA-sched",
118 cl::init(&createDefaultScheduler),
119 cl::desc("Instruction schedulers available (before register"
122 static RegisterScheduler
123 defaultListDAGScheduler("default", "Best scheduler for the target",
124 createDefaultScheduler);
127 //===--------------------------------------------------------------------===//
128 /// createDefaultScheduler - This creates an instruction scheduler appropriate
130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
131 CodeGenOpt::Level OptLevel) {
132 const TargetLowering &TLI = IS->getTargetLowering();
134 if (OptLevel == CodeGenOpt::None)
135 return createFastDAGScheduler(IS, OptLevel);
136 if (TLI.getSchedulingPreference() == Sched::Latency)
137 return createTDListDAGScheduler(IS, OptLevel);
138 if (TLI.getSchedulingPreference() == Sched::RegPressure)
139 return createBURRListDAGScheduler(IS, OptLevel);
140 assert(TLI.getSchedulingPreference() == Sched::Hybrid &&
141 "Unknown sched type!");
142 return createHybridListDAGScheduler(IS, OptLevel);
146 // EmitInstrWithCustomInserter - This method should be implemented by targets
147 // that mark instructions with the 'usesCustomInserter' flag. These
148 // instructions are special in various ways, which require special support to
149 // insert. The specified MachineInstr is created but not inserted into any
150 // basic blocks, and this method is called to expand it into a sequence of
151 // instructions, potentially also creating new basic blocks and control flow.
152 // When new basic blocks are inserted and the edges from MBB to its successors
153 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
156 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
157 MachineBasicBlock *MBB) const {
159 dbgs() << "If a target marks an instruction with "
160 "'usesCustomInserter', it must implement "
161 "TargetLowering::EmitInstrWithCustomInserter!";
167 //===----------------------------------------------------------------------===//
168 // SelectionDAGISel code
169 //===----------------------------------------------------------------------===//
171 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
173 FuncInfo(new FunctionLoweringInfo(TLI)),
174 CurDAG(new SelectionDAG(tm)),
175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
181 SelectionDAGISel::~SelectionDAGISel() {
187 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
188 AU.addRequired<AliasAnalysis>();
189 AU.addPreserved<AliasAnalysis>();
190 AU.addRequired<GCModuleInfo>();
191 AU.addPreserved<GCModuleInfo>();
192 MachineFunctionPass::getAnalysisUsage(AU);
195 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
196 /// other function that gcc recognizes as "returning twice". This is used to
197 /// limit code-gen optimizations on the machine function.
199 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
200 static bool FunctionCallsSetJmp(const Function *F) {
201 const Module *M = F->getParent();
202 static const char *ReturnsTwiceFns[] = {
211 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
215 if (!Callee->use_empty())
216 for (Value::const_use_iterator
217 I = Callee->use_begin(), E = Callee->use_end();
219 if (const CallInst *CI = dyn_cast<CallInst>(I))
220 if (CI->getParent()->getParent() == F)
225 #undef NUM_RETURNS_TWICE_FNS
228 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
229 // Do some sanity-checking on the command-line options.
230 assert((!EnableFastISelVerbose || EnableFastISel) &&
231 "-fast-isel-verbose requires -fast-isel");
232 assert((!EnableFastISelAbort || EnableFastISel) &&
233 "-fast-isel-abort requires -fast-isel");
235 const Function &Fn = *mf.getFunction();
236 const TargetInstrInfo &TII = *TM.getInstrInfo();
237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
240 RegInfo = &MF->getRegInfo();
241 AA = &getAnalysis<AliasAnalysis>();
242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
247 FuncInfo->set(Fn, *MF);
250 SelectAllBasicBlocks(Fn);
252 // If the first basic block in the function has live ins that need to be
253 // copied into vregs, emit the copies into the top of the block before
254 // emitting the code for the block.
255 MachineBasicBlock *EntryMBB = MF->begin();
256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
258 DenseMap<unsigned, unsigned> LiveInMap;
259 if (!FuncInfo->ArgDbgValues.empty())
260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
261 E = RegInfo->livein_end(); LI != E; ++LI)
263 LiveInMap.insert(std::make_pair(LI->first, LI->second));
265 // Insert DBG_VALUE instructions for function arguments to the entry block.
266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
268 unsigned Reg = MI->getOperand(0).getReg();
269 if (TargetRegisterInfo::isPhysicalRegister(Reg))
270 EntryMBB->insert(EntryMBB->begin(), MI);
272 MachineInstr *Def = RegInfo->getVRegDef(Reg);
273 MachineBasicBlock::iterator InsertPos = Def;
274 // FIXME: VR def may not be in entry block.
275 Def->getParent()->insert(llvm::next(InsertPos), MI);
278 // If Reg is live-in then update debug info to track its copy in a vreg.
279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
280 if (LDI != LiveInMap.end()) {
281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
282 MachineBasicBlock::iterator InsertPos = Def;
283 const MDNode *Variable =
284 MI->getOperand(MI->getNumOperands()-1).getMetadata();
285 unsigned Offset = MI->getOperand(1).getImm();
286 // Def is never a terminator here, so it is ok to increment InsertPos.
287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
288 TII.get(TargetOpcode::DBG_VALUE))
289 .addReg(LDI->second, RegState::Debug)
290 .addImm(Offset).addMetadata(Variable);
294 // Determine if there are any calls in this machine function.
295 MachineFrameInfo *MFI = MF->getFrameInfo();
296 if (!MFI->hasCalls()) {
297 for (MachineFunction::const_iterator
298 I = MF->begin(), E = MF->end(); I != E; ++I) {
299 const MachineBasicBlock *MBB = I;
300 for (MachineBasicBlock::const_iterator
301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
304 // Operand 1 of an inline asm instruction indicates whether the asm
305 // needs stack or not.
306 if ((II->isInlineAsm() && II->getOperand(1).getImm()) ||
307 (TID.isCall() && !TID.isReturn())) {
308 MFI->setHasCalls(true);
316 // Determine if there is a call to setjmp in the machine function.
317 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
319 // Replace forward-declared registers with the registers containing
320 // the desired value.
321 MachineRegisterInfo &MRI = MF->getRegInfo();
322 for (DenseMap<unsigned, unsigned>::iterator
323 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
325 unsigned From = I->first;
326 unsigned To = I->second;
327 // If To is also scheduled to be replaced, find what its ultimate
330 DenseMap<unsigned, unsigned>::iterator J =
331 FuncInfo->RegFixups.find(To);
336 MRI.replaceRegWith(From, To);
339 // Release function-specific state. SDB and CurDAG are already cleared
347 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
348 BasicBlock::const_iterator End,
350 // Lower all of the non-terminator instructions. If a call is emitted
351 // as a tail call, cease emitting nodes for this block. Terminators
352 // are handled below.
353 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
356 // Make sure the root of the DAG is up-to-date.
357 CurDAG->setRoot(SDB->getControlRoot());
358 HadTailCall = SDB->HasTailCall;
361 // Final step, emit the lowered DAG as machine code.
366 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
367 /// nodes from the worklist.
368 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
369 SmallVector<SDNode*, 128> &Worklist;
370 SmallPtrSet<SDNode*, 128> &InWorklist;
372 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
373 SmallPtrSet<SDNode*, 128> &inwl)
374 : Worklist(wl), InWorklist(inwl) {}
376 void RemoveFromWorklist(SDNode *N) {
377 if (!InWorklist.erase(N)) return;
379 SmallVector<SDNode*, 128>::iterator I =
380 std::find(Worklist.begin(), Worklist.end(), N);
381 assert(I != Worklist.end() && "Not in worklist");
383 *I = Worklist.back();
387 virtual void NodeDeleted(SDNode *N, SDNode *E) {
388 RemoveFromWorklist(N);
391 virtual void NodeUpdated(SDNode *N) {
397 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
398 SmallPtrSet<SDNode*, 128> VisitedNodes;
399 SmallVector<SDNode*, 128> Worklist;
401 Worklist.push_back(CurDAG->getRoot().getNode());
408 SDNode *N = Worklist.pop_back_val();
410 // If we've already seen this node, ignore it.
411 if (!VisitedNodes.insert(N))
414 // Otherwise, add all chain operands to the worklist.
415 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
416 if (N->getOperand(i).getValueType() == MVT::Other)
417 Worklist.push_back(N->getOperand(i).getNode());
419 // If this is a CopyToReg with a vreg dest, process it.
420 if (N->getOpcode() != ISD::CopyToReg)
423 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
424 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
427 // Ignore non-scalar or non-integer values.
428 SDValue Src = N->getOperand(2);
429 EVT SrcVT = Src.getValueType();
430 if (!SrcVT.isInteger() || SrcVT.isVector())
433 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
434 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
435 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
437 // Only install this information if it tells us something.
438 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
439 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
440 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
441 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
442 FunctionLoweringInfo::LiveOutInfo &LOI =
443 FuncInfo->LiveOutRegInfo[DestReg];
444 LOI.NumSignBits = NumSignBits;
445 LOI.KnownOne = KnownOne;
446 LOI.KnownZero = KnownZero;
448 } while (!Worklist.empty());
451 void SelectionDAGISel::CodeGenAndEmitDAG() {
452 std::string GroupName;
453 if (TimePassesIsEnabled)
454 GroupName = "Instruction Selection and Scheduling";
455 std::string BlockName;
456 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
457 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
459 BlockName = MF->getFunction()->getNameStr() + ":" +
460 FuncInfo->MBB->getBasicBlock()->getNameStr();
462 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
464 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
466 // Run the DAG combiner in pre-legalize mode.
468 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
469 CurDAG->Combine(Unrestricted, *AA, OptLevel);
472 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
474 // Second step, hack on the DAG until it only uses operations and types that
475 // the target supports.
476 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
481 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
482 Changed = CurDAG->LegalizeTypes();
485 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
488 if (ViewDAGCombineLT)
489 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
491 // Run the DAG combiner in post-type-legalize mode.
493 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
494 TimePassesIsEnabled);
495 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
498 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
503 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
504 Changed = CurDAG->LegalizeVectors();
509 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
510 CurDAG->LegalizeTypes();
513 if (ViewDAGCombineLT)
514 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
516 // Run the DAG combiner in post-type-legalize mode.
518 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
519 TimePassesIsEnabled);
520 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
523 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
527 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
530 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
531 CurDAG->Legalize(OptLevel);
534 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
536 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
538 // Run the DAG combiner in post-legalize mode.
540 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
541 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
544 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
546 if (OptLevel != CodeGenOpt::None)
547 ComputeLiveOutVRegInfo();
549 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
551 // Third, instruction select all of the operations to machine code, adding the
552 // code to the MachineBasicBlock.
554 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
555 DoInstructionSelection();
558 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
560 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
562 // Schedule machine code.
563 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
565 NamedRegionTimer T("Instruction Scheduling", GroupName,
566 TimePassesIsEnabled);
567 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
570 if (ViewSUnitDAGs) Scheduler->viewGraph();
572 // Emit machine code to BB. This can change 'BB' to the last block being
575 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
577 FuncInfo->MBB = Scheduler->EmitSchedule();
578 FuncInfo->InsertPt = Scheduler->InsertPos;
581 // Free the scheduler state.
583 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
584 TimePassesIsEnabled);
588 // Free the SelectionDAG state, now that we're finished with it.
592 void SelectionDAGISel::DoInstructionSelection() {
593 DEBUG(errs() << "===== Instruction selection begins:\n");
597 // Select target instructions for the DAG.
599 // Number all nodes with a topological order and set DAGSize.
600 DAGSize = CurDAG->AssignTopologicalOrder();
602 // Create a dummy node (which is not added to allnodes), that adds
603 // a reference to the root node, preventing it from being deleted,
604 // and tracking any changes of the root.
605 HandleSDNode Dummy(CurDAG->getRoot());
606 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
609 // The AllNodes list is now topological-sorted. Visit the
610 // nodes by starting at the end of the list (the root of the
611 // graph) and preceding back toward the beginning (the entry
613 while (ISelPosition != CurDAG->allnodes_begin()) {
614 SDNode *Node = --ISelPosition;
615 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
616 // but there are currently some corner cases that it misses. Also, this
617 // makes it theoretically possible to disable the DAGCombiner.
618 if (Node->use_empty())
621 SDNode *ResNode = Select(Node);
623 // FIXME: This is pretty gross. 'Select' should be changed to not return
624 // anything at all and this code should be nuked with a tactical strike.
626 // If node should not be replaced, continue with the next one.
627 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
631 ReplaceUses(Node, ResNode);
633 // If after the replacement this node is not used any more,
634 // remove this dead node.
635 if (Node->use_empty()) { // Don't delete EntryToken, etc.
636 ISelUpdater ISU(ISelPosition);
637 CurDAG->RemoveDeadNode(Node, &ISU);
641 CurDAG->setRoot(Dummy.getValue());
644 DEBUG(errs() << "===== Instruction selection ends:\n");
646 PostprocessISelDAG();
649 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
650 /// do other setup for EH landing-pad blocks.
651 void SelectionDAGISel::PrepareEHLandingPad() {
652 // Add a label to mark the beginning of the landing pad. Deletion of the
653 // landing pad can thus be detected via the MachineModuleInfo.
654 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
656 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
657 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
660 // Mark exception register as live in.
661 unsigned Reg = TLI.getExceptionAddressRegister();
662 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
664 // Mark exception selector register as live in.
665 Reg = TLI.getExceptionSelectorRegister();
666 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
668 // FIXME: Hack around an exception handling flaw (PR1508): the personality
669 // function and list of typeids logically belong to the invoke (or, if you
670 // like, the basic block containing the invoke), and need to be associated
671 // with it in the dwarf exception handling tables. Currently however the
672 // information is provided by an intrinsic (eh.selector) that can be moved
673 // to unexpected places by the optimizers: if the unwind edge is critical,
674 // then breaking it can result in the intrinsics being in the successor of
675 // the landing pad, not the landing pad itself. This results
676 // in exceptions not being caught because no typeids are associated with
677 // the invoke. This may not be the only way things can go wrong, but it
678 // is the only way we try to work around for the moment.
679 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
680 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
682 if (Br && Br->isUnconditional()) { // Critical edge?
683 BasicBlock::const_iterator I, E;
684 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
685 if (isa<EHSelectorInst>(I))
689 // No catch info found - try to extract some from the successor.
690 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
694 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
695 // Initialize the Fast-ISel state, if needed.
696 FastISel *FastIS = 0;
698 FastIS = TLI.createFastISel(*FuncInfo);
700 // Iterate over all basic blocks in the function.
701 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
702 const BasicBlock *LLVMBB = &*I;
703 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
704 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
706 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
707 BasicBlock::const_iterator const End = LLVMBB->end();
708 BasicBlock::const_iterator BI = End;
710 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
712 // Setup an EH landing-pad block.
713 if (FuncInfo->MBB->isLandingPad())
714 PrepareEHLandingPad();
716 // Lower any arguments needed in this block if this is the entry block.
717 if (LLVMBB == &Fn.getEntryBlock())
718 LowerArguments(LLVMBB);
720 // Before doing SelectionDAG ISel, see if FastISel has been requested.
722 FastIS->startNewBlock();
724 // Emit code for any incoming arguments. This must happen before
725 // beginning FastISel on the entry block.
726 if (LLVMBB == &Fn.getEntryBlock()) {
727 CurDAG->setRoot(SDB->getControlRoot());
731 // If we inserted any instructions at the beginning, make a note of
732 // where they are, so we can be sure to emit subsequent instructions
734 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
735 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
737 FastIS->setLastLocalValue(0);
740 // Do FastISel on as many instructions as possible.
741 for (; BI != Begin; --BI) {
742 const Instruction *Inst = llvm::prior(BI);
744 // If we no longer require this instruction, skip it.
745 if (!Inst->mayWriteToMemory() &&
746 !isa<TerminatorInst>(Inst) &&
747 !isa<DbgInfoIntrinsic>(Inst) &&
748 !FuncInfo->isExportedInst(Inst))
751 // Bottom-up: reset the insert pos at the top, after any local-value
753 FastIS->recomputeInsertPt();
755 // Try to select the instruction with FastISel.
756 if (FastIS->SelectInstruction(Inst))
759 // Then handle certain instructions as single-LLVM-Instruction blocks.
760 if (isa<CallInst>(Inst)) {
761 ++NumFastIselFailures;
762 if (EnableFastISelVerbose || EnableFastISelAbort) {
763 dbgs() << "FastISel missed call: ";
767 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
768 unsigned &R = FuncInfo->ValueMap[Inst];
770 R = FuncInfo->CreateRegs(Inst->getType());
773 bool HadTailCall = false;
774 SelectBasicBlock(Inst, BI, HadTailCall);
776 // If the call was emitted as a tail call, we're done with the block.
785 // Otherwise, give up on FastISel for the rest of the block.
786 // For now, be a little lenient about non-branch terminators.
787 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
788 ++NumFastIselFailures;
789 if (EnableFastISelVerbose || EnableFastISelAbort) {
790 dbgs() << "FastISel miss: ";
793 if (EnableFastISelAbort)
794 // The "fast" selector couldn't handle something and bailed.
795 // For the purpose of debugging, just abort.
796 llvm_unreachable("FastISel didn't select the entire block");
801 FastIS->recomputeInsertPt();
804 // Run SelectionDAG instruction selection on the remainder of the block
805 // not handled by FastISel. If FastISel is not run, this is the entire
808 SelectBasicBlock(Begin, BI, HadTailCall);
811 FuncInfo->PHINodesToUpdate.clear();
818 SelectionDAGISel::FinishBasicBlock() {
820 DEBUG(dbgs() << "Total amount of phi nodes to update: "
821 << FuncInfo->PHINodesToUpdate.size() << "\n";
822 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
823 dbgs() << "Node " << i << " : ("
824 << FuncInfo->PHINodesToUpdate[i].first
825 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
827 // Next, now that we know what the last MBB the LLVM BB expanded is, update
828 // PHI nodes in successors.
829 if (SDB->SwitchCases.empty() &&
830 SDB->JTCases.empty() &&
831 SDB->BitTestCases.empty()) {
832 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
833 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
834 assert(PHI->isPHI() &&
835 "This is not a machine PHI node that we are updating!");
836 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
839 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
840 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
845 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
846 // Lower header first, if it wasn't already lowered
847 if (!SDB->BitTestCases[i].Emitted) {
848 // Set the current basic block to the mbb we wish to insert the code into
849 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
850 FuncInfo->InsertPt = FuncInfo->MBB->end();
852 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
853 CurDAG->setRoot(SDB->getRoot());
858 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
859 // Set the current basic block to the mbb we wish to insert the code into
860 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
861 FuncInfo->InsertPt = FuncInfo->MBB->end();
864 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
865 SDB->BitTestCases[i].Reg,
866 SDB->BitTestCases[i].Cases[j],
869 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
870 SDB->BitTestCases[i].Reg,
871 SDB->BitTestCases[i].Cases[j],
875 CurDAG->setRoot(SDB->getRoot());
881 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
883 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
884 MachineBasicBlock *PHIBB = PHI->getParent();
885 assert(PHI->isPHI() &&
886 "This is not a machine PHI node that we are updating!");
887 // This is "default" BB. We have two jumps to it. From "header" BB and
888 // from last "case" BB.
889 if (PHIBB == SDB->BitTestCases[i].Default) {
890 PHI->addOperand(MachineOperand::
891 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
893 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
894 PHI->addOperand(MachineOperand::
895 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
897 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
900 // One of "cases" BB.
901 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
903 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
904 if (cBB->isSuccessor(PHIBB)) {
905 PHI->addOperand(MachineOperand::
906 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
908 PHI->addOperand(MachineOperand::CreateMBB(cBB));
913 SDB->BitTestCases.clear();
915 // If the JumpTable record is filled in, then we need to emit a jump table.
916 // Updating the PHI nodes is tricky in this case, since we need to determine
917 // whether the PHI is a successor of the range check MBB or the jump table MBB
918 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
919 // Lower header first, if it wasn't already lowered
920 if (!SDB->JTCases[i].first.Emitted) {
921 // Set the current basic block to the mbb we wish to insert the code into
922 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
923 FuncInfo->InsertPt = FuncInfo->MBB->end();
925 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
927 CurDAG->setRoot(SDB->getRoot());
932 // Set the current basic block to the mbb we wish to insert the code into
933 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
934 FuncInfo->InsertPt = FuncInfo->MBB->end();
936 SDB->visitJumpTable(SDB->JTCases[i].second);
937 CurDAG->setRoot(SDB->getRoot());
942 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
944 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
945 MachineBasicBlock *PHIBB = PHI->getParent();
946 assert(PHI->isPHI() &&
947 "This is not a machine PHI node that we are updating!");
948 // "default" BB. We can go there only from header BB.
949 if (PHIBB == SDB->JTCases[i].second.Default) {
951 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
954 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
956 // JT BB. Just iterate over successors here
957 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
959 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
961 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
965 SDB->JTCases.clear();
967 // If the switch block involved a branch to one of the actual successors, we
968 // need to update PHI nodes in that block.
969 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
970 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
971 assert(PHI->isPHI() &&
972 "This is not a machine PHI node that we are updating!");
973 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
975 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
976 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
980 // If we generated any switch lowering information, build and codegen any
981 // additional DAGs necessary.
982 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
983 // Set the current basic block to the mbb we wish to insert the code into
984 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
985 FuncInfo->InsertPt = FuncInfo->MBB->end();
987 // Determine the unique successors.
988 SmallVector<MachineBasicBlock *, 2> Succs;
989 Succs.push_back(SDB->SwitchCases[i].TrueBB);
990 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
991 Succs.push_back(SDB->SwitchCases[i].FalseBB);
993 // Emit the code. Note that this could result in ThisBB being split, so
994 // we need to check for updates.
995 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
996 CurDAG->setRoot(SDB->getRoot());
999 ThisBB = FuncInfo->MBB;
1001 // Handle any PHI nodes in successors of this chunk, as if we were coming
1002 // from the original BB before switch expansion. Note that PHI nodes can
1003 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1004 // handle them the right number of times.
1005 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1006 FuncInfo->MBB = Succs[i];
1007 FuncInfo->InsertPt = FuncInfo->MBB->end();
1008 // FuncInfo->MBB may have been removed from the CFG if a branch was
1010 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1011 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1012 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1014 // This value for this PHI node is recorded in PHINodesToUpdate.
1015 for (unsigned pn = 0; ; ++pn) {
1016 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1017 "Didn't find PHI entry!");
1018 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1019 Phi->addOperand(MachineOperand::
1020 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1022 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1030 SDB->SwitchCases.clear();
1034 /// Create the scheduler. If a specific scheduler was specified
1035 /// via the SchedulerRegistry, use it, otherwise select the
1036 /// one preferred by the target.
1038 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1039 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1043 RegisterScheduler::setDefault(Ctor);
1046 return Ctor(this, OptLevel);
1049 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1050 return new ScheduleHazardRecognizer();
1053 //===----------------------------------------------------------------------===//
1054 // Helper functions used by the generated instruction selector.
1055 //===----------------------------------------------------------------------===//
1056 // Calls to these methods are generated by tblgen.
1058 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1059 /// the dag combiner simplified the 255, we still want to match. RHS is the
1060 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1061 /// specified in the .td file (e.g. 255).
1062 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1063 int64_t DesiredMaskS) const {
1064 const APInt &ActualMask = RHS->getAPIntValue();
1065 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1067 // If the actual mask exactly matches, success!
1068 if (ActualMask == DesiredMask)
1071 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1072 if (ActualMask.intersects(~DesiredMask))
1075 // Otherwise, the DAG Combiner may have proven that the value coming in is
1076 // either already zero or is not demanded. Check for known zero input bits.
1077 APInt NeededMask = DesiredMask & ~ActualMask;
1078 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1081 // TODO: check to see if missing bits are just not demanded.
1083 // Otherwise, this pattern doesn't match.
1087 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1088 /// the dag combiner simplified the 255, we still want to match. RHS is the
1089 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1090 /// specified in the .td file (e.g. 255).
1091 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1092 int64_t DesiredMaskS) const {
1093 const APInt &ActualMask = RHS->getAPIntValue();
1094 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1096 // If the actual mask exactly matches, success!
1097 if (ActualMask == DesiredMask)
1100 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1101 if (ActualMask.intersects(~DesiredMask))
1104 // Otherwise, the DAG Combiner may have proven that the value coming in is
1105 // either already zero or is not demanded. Check for known zero input bits.
1106 APInt NeededMask = DesiredMask & ~ActualMask;
1108 APInt KnownZero, KnownOne;
1109 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1111 // If all the missing bits in the or are already known to be set, match!
1112 if ((NeededMask & KnownOne) == NeededMask)
1115 // TODO: check to see if missing bits are just not demanded.
1117 // Otherwise, this pattern doesn't match.
1122 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1123 /// by tblgen. Others should not call it.
1124 void SelectionDAGISel::
1125 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1126 std::vector<SDValue> InOps;
1127 std::swap(InOps, Ops);
1129 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1130 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1131 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1132 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1134 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1135 if (InOps[e-1].getValueType() == MVT::Flag)
1136 --e; // Don't process a flag operand if it is here.
1139 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1140 if (!InlineAsm::isMemKind(Flags)) {
1141 // Just skip over this operand, copying the operands verbatim.
1142 Ops.insert(Ops.end(), InOps.begin()+i,
1143 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1144 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1146 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1147 "Memory operand with multiple values?");
1148 // Otherwise, this is a memory operand. Ask the target to select it.
1149 std::vector<SDValue> SelOps;
1150 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1151 report_fatal_error("Could not match memory address. Inline asm"
1154 // Add this to the output node.
1156 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1157 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1158 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1163 // Add the flag input back if present.
1164 if (e != InOps.size())
1165 Ops.push_back(InOps.back());
1168 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1171 static SDNode *findFlagUse(SDNode *N) {
1172 unsigned FlagResNo = N->getNumValues()-1;
1173 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1174 SDUse &Use = I.getUse();
1175 if (Use.getResNo() == FlagResNo)
1176 return Use.getUser();
1181 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1182 /// This function recursively traverses up the operand chain, ignoring
1184 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1185 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1186 bool IgnoreChains) {
1187 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1188 // greater than all of its (recursive) operands. If we scan to a point where
1189 // 'use' is smaller than the node we're scanning for, then we know we will
1192 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1193 // happen because we scan down to newly selected nodes in the case of flag
1195 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1198 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1199 // won't fail if we scan it again.
1200 if (!Visited.insert(Use))
1203 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1204 // Ignore chain uses, they are validated by HandleMergeInputChains.
1205 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1208 SDNode *N = Use->getOperand(i).getNode();
1210 if (Use == ImmedUse || Use == Root)
1211 continue; // We are not looking for immediate use.
1216 // Traverse up the operand chain.
1217 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1223 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1224 /// operand node N of U during instruction selection that starts at Root.
1225 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1226 SDNode *Root) const {
1227 if (OptLevel == CodeGenOpt::None) return false;
1228 return N.hasOneUse();
1231 /// IsLegalToFold - Returns true if the specific operand node N of
1232 /// U can be folded during instruction selection that starts at Root.
1233 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1234 CodeGenOpt::Level OptLevel,
1235 bool IgnoreChains) {
1236 if (OptLevel == CodeGenOpt::None) return false;
1238 // If Root use can somehow reach N through a path that that doesn't contain
1239 // U then folding N would create a cycle. e.g. In the following
1240 // diagram, Root can reach N through X. If N is folded into into Root, then
1241 // X is both a predecessor and a successor of U.
1252 // * indicates nodes to be folded together.
1254 // If Root produces a flag, then it gets (even more) interesting. Since it
1255 // will be "glued" together with its flag use in the scheduler, we need to
1256 // check if it might reach N.
1275 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1276 // (call it Fold), then X is a predecessor of FU and a successor of
1277 // Fold. But since Fold and FU are flagged together, this will create
1278 // a cycle in the scheduling graph.
1280 // If the node has flags, walk down the graph to the "lowest" node in the
1282 EVT VT = Root->getValueType(Root->getNumValues()-1);
1283 while (VT == MVT::Flag) {
1284 SDNode *FU = findFlagUse(Root);
1288 VT = Root->getValueType(Root->getNumValues()-1);
1290 // If our query node has a flag result with a use, we've walked up it. If
1291 // the user (which has already been selected) has a chain or indirectly uses
1292 // the chain, our WalkChainUsers predicate will not consider it. Because of
1293 // this, we cannot ignore chains in this predicate.
1294 IgnoreChains = false;
1298 SmallPtrSet<SDNode*, 16> Visited;
1299 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1302 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1303 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1304 SelectInlineAsmMemoryOperands(Ops);
1306 std::vector<EVT> VTs;
1307 VTs.push_back(MVT::Other);
1308 VTs.push_back(MVT::Flag);
1309 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1310 VTs, &Ops[0], Ops.size());
1312 return New.getNode();
1315 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1316 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1319 /// GetVBR - decode a vbr encoding whose top bit is set.
1320 ALWAYS_INLINE static uint64_t
1321 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1322 assert(Val >= 128 && "Not a VBR");
1323 Val &= 127; // Remove first vbr bit.
1328 NextBits = MatcherTable[Idx++];
1329 Val |= (NextBits&127) << Shift;
1331 } while (NextBits & 128);
1337 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1338 /// interior flag and chain results to use the new flag and chain results.
1339 void SelectionDAGISel::
1340 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1341 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1343 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1344 bool isMorphNodeTo) {
1345 SmallVector<SDNode*, 4> NowDeadNodes;
1347 ISelUpdater ISU(ISelPosition);
1349 // Now that all the normal results are replaced, we replace the chain and
1350 // flag results if present.
1351 if (!ChainNodesMatched.empty()) {
1352 assert(InputChain.getNode() != 0 &&
1353 "Matched input chains but didn't produce a chain");
1354 // Loop over all of the nodes we matched that produced a chain result.
1355 // Replace all the chain results with the final chain we ended up with.
1356 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1357 SDNode *ChainNode = ChainNodesMatched[i];
1359 // If this node was already deleted, don't look at it.
1360 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1363 // Don't replace the results of the root node if we're doing a
1365 if (ChainNode == NodeToMatch && isMorphNodeTo)
1368 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1369 if (ChainVal.getValueType() == MVT::Flag)
1370 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1371 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1372 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1374 // If the node became dead and we haven't already seen it, delete it.
1375 if (ChainNode->use_empty() &&
1376 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1377 NowDeadNodes.push_back(ChainNode);
1381 // If the result produces a flag, update any flag results in the matched
1382 // pattern with the flag result.
1383 if (InputFlag.getNode() != 0) {
1384 // Handle any interior nodes explicitly marked.
1385 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1386 SDNode *FRN = FlagResultNodesMatched[i];
1388 // If this node was already deleted, don't look at it.
1389 if (FRN->getOpcode() == ISD::DELETED_NODE)
1392 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1393 "Doesn't have a flag result");
1394 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1397 // If the node became dead and we haven't already seen it, delete it.
1398 if (FRN->use_empty() &&
1399 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1400 NowDeadNodes.push_back(FRN);
1404 if (!NowDeadNodes.empty())
1405 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1407 DEBUG(errs() << "ISEL: Match complete!\n");
1413 CR_LeadsToInteriorNode
1416 /// WalkChainUsers - Walk down the users of the specified chained node that is
1417 /// part of the pattern we're matching, looking at all of the users we find.
1418 /// This determines whether something is an interior node, whether we have a
1419 /// non-pattern node in between two pattern nodes (which prevent folding because
1420 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1421 /// between pattern nodes (in which case the TF becomes part of the pattern).
1423 /// The walk we do here is guaranteed to be small because we quickly get down to
1424 /// already selected nodes "below" us.
1426 WalkChainUsers(SDNode *ChainedNode,
1427 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1428 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1429 ChainResult Result = CR_Simple;
1431 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1432 E = ChainedNode->use_end(); UI != E; ++UI) {
1433 // Make sure the use is of the chain, not some other value we produce.
1434 if (UI.getUse().getValueType() != MVT::Other) continue;
1438 // If we see an already-selected machine node, then we've gone beyond the
1439 // pattern that we're selecting down into the already selected chunk of the
1441 if (User->isMachineOpcode() ||
1442 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1445 if (User->getOpcode() == ISD::CopyToReg ||
1446 User->getOpcode() == ISD::CopyFromReg ||
1447 User->getOpcode() == ISD::INLINEASM ||
1448 User->getOpcode() == ISD::EH_LABEL) {
1449 // If their node ID got reset to -1 then they've already been selected.
1450 // Treat them like a MachineOpcode.
1451 if (User->getNodeId() == -1)
1455 // If we have a TokenFactor, we handle it specially.
1456 if (User->getOpcode() != ISD::TokenFactor) {
1457 // If the node isn't a token factor and isn't part of our pattern, then it
1458 // must be a random chained node in between two nodes we're selecting.
1459 // This happens when we have something like:
1464 // Because we structurally match the load/store as a read/modify/write,
1465 // but the call is chained between them. We cannot fold in this case
1466 // because it would induce a cycle in the graph.
1467 if (!std::count(ChainedNodesInPattern.begin(),
1468 ChainedNodesInPattern.end(), User))
1469 return CR_InducesCycle;
1471 // Otherwise we found a node that is part of our pattern. For example in:
1475 // This would happen when we're scanning down from the load and see the
1476 // store as a user. Record that there is a use of ChainedNode that is
1477 // part of the pattern and keep scanning uses.
1478 Result = CR_LeadsToInteriorNode;
1479 InteriorChainedNodes.push_back(User);
1483 // If we found a TokenFactor, there are two cases to consider: first if the
1484 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1485 // uses of the TF are in our pattern) we just want to ignore it. Second,
1486 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1492 // | \ DAG's like cheese
1495 // [TokenFactor] [Op]
1502 // In this case, the TokenFactor becomes part of our match and we rewrite it
1503 // as a new TokenFactor.
1505 // To distinguish these two cases, do a recursive walk down the uses.
1506 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1508 // If the uses of the TokenFactor are just already-selected nodes, ignore
1509 // it, it is "below" our pattern.
1511 case CR_InducesCycle:
1512 // If the uses of the TokenFactor lead to nodes that are not part of our
1513 // pattern that are not selected, folding would turn this into a cycle,
1515 return CR_InducesCycle;
1516 case CR_LeadsToInteriorNode:
1517 break; // Otherwise, keep processing.
1520 // Okay, we know we're in the interesting interior case. The TokenFactor
1521 // is now going to be considered part of the pattern so that we rewrite its
1522 // uses (it may have uses that are not part of the pattern) with the
1523 // ultimate chain result of the generated code. We will also add its chain
1524 // inputs as inputs to the ultimate TokenFactor we create.
1525 Result = CR_LeadsToInteriorNode;
1526 ChainedNodesInPattern.push_back(User);
1527 InteriorChainedNodes.push_back(User);
1534 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1535 /// operation for when the pattern matched at least one node with a chains. The
1536 /// input vector contains a list of all of the chained nodes that we match. We
1537 /// must determine if this is a valid thing to cover (i.e. matching it won't
1538 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1539 /// be used as the input node chain for the generated nodes.
1541 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1542 SelectionDAG *CurDAG) {
1543 // Walk all of the chained nodes we've matched, recursively scanning down the
1544 // users of the chain result. This adds any TokenFactor nodes that are caught
1545 // in between chained nodes to the chained and interior nodes list.
1546 SmallVector<SDNode*, 3> InteriorChainedNodes;
1547 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1548 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1549 InteriorChainedNodes) == CR_InducesCycle)
1550 return SDValue(); // Would induce a cycle.
1553 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1554 // that we are interested in. Form our input TokenFactor node.
1555 SmallVector<SDValue, 3> InputChains;
1556 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1557 // Add the input chain of this node to the InputChains list (which will be
1558 // the operands of the generated TokenFactor) if it's not an interior node.
1559 SDNode *N = ChainNodesMatched[i];
1560 if (N->getOpcode() != ISD::TokenFactor) {
1561 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1564 // Otherwise, add the input chain.
1565 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1566 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1567 InputChains.push_back(InChain);
1571 // If we have a token factor, we want to add all inputs of the token factor
1572 // that are not part of the pattern we're matching.
1573 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1574 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1575 N->getOperand(op).getNode()))
1576 InputChains.push_back(N->getOperand(op));
1581 if (InputChains.size() == 1)
1582 return InputChains[0];
1583 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1584 MVT::Other, &InputChains[0], InputChains.size());
1587 /// MorphNode - Handle morphing a node in place for the selector.
1588 SDNode *SelectionDAGISel::
1589 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1590 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1591 // It is possible we're using MorphNodeTo to replace a node with no
1592 // normal results with one that has a normal result (or we could be
1593 // adding a chain) and the input could have flags and chains as well.
1594 // In this case we need to shift the operands down.
1595 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1596 // than the old isel though.
1597 int OldFlagResultNo = -1, OldChainResultNo = -1;
1599 unsigned NTMNumResults = Node->getNumValues();
1600 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1601 OldFlagResultNo = NTMNumResults-1;
1602 if (NTMNumResults != 1 &&
1603 Node->getValueType(NTMNumResults-2) == MVT::Other)
1604 OldChainResultNo = NTMNumResults-2;
1605 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1606 OldChainResultNo = NTMNumResults-1;
1608 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1609 // that this deletes operands of the old node that become dead.
1610 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1612 // MorphNodeTo can operate in two ways: if an existing node with the
1613 // specified operands exists, it can just return it. Otherwise, it
1614 // updates the node in place to have the requested operands.
1616 // If we updated the node in place, reset the node ID. To the isel,
1617 // this should be just like a newly allocated machine node.
1621 unsigned ResNumResults = Res->getNumValues();
1622 // Move the flag if needed.
1623 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1624 (unsigned)OldFlagResultNo != ResNumResults-1)
1625 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1626 SDValue(Res, ResNumResults-1));
1628 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1631 // Move the chain reference if needed.
1632 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1633 (unsigned)OldChainResultNo != ResNumResults-1)
1634 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1635 SDValue(Res, ResNumResults-1));
1637 // Otherwise, no replacement happened because the node already exists. Replace
1638 // Uses of the old node with the new one.
1640 CurDAG->ReplaceAllUsesWith(Node, Res);
1645 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1646 ALWAYS_INLINE static bool
1647 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1648 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1649 // Accept if it is exactly the same as a previously recorded node.
1650 unsigned RecNo = MatcherTable[MatcherIndex++];
1651 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1652 return N == RecordedNodes[RecNo];
1655 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1656 ALWAYS_INLINE static bool
1657 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1658 SelectionDAGISel &SDISel) {
1659 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1662 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1663 ALWAYS_INLINE static bool
1664 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1665 SelectionDAGISel &SDISel, SDNode *N) {
1666 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1669 ALWAYS_INLINE static bool
1670 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1672 uint16_t Opc = MatcherTable[MatcherIndex++];
1673 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1674 return N->getOpcode() == Opc;
1677 ALWAYS_INLINE static bool
1678 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1679 SDValue N, const TargetLowering &TLI) {
1680 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1681 if (N.getValueType() == VT) return true;
1683 // Handle the case when VT is iPTR.
1684 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1687 ALWAYS_INLINE static bool
1688 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1689 SDValue N, const TargetLowering &TLI,
1691 if (ChildNo >= N.getNumOperands())
1692 return false; // Match fails if out of range child #.
1693 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1697 ALWAYS_INLINE static bool
1698 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1700 return cast<CondCodeSDNode>(N)->get() ==
1701 (ISD::CondCode)MatcherTable[MatcherIndex++];
1704 ALWAYS_INLINE static bool
1705 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1706 SDValue N, const TargetLowering &TLI) {
1707 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1708 if (cast<VTSDNode>(N)->getVT() == VT)
1711 // Handle the case when VT is iPTR.
1712 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1715 ALWAYS_INLINE static bool
1716 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1718 int64_t Val = MatcherTable[MatcherIndex++];
1720 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1722 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1723 return C != 0 && C->getSExtValue() == Val;
1726 ALWAYS_INLINE static bool
1727 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1728 SDValue N, SelectionDAGISel &SDISel) {
1729 int64_t Val = MatcherTable[MatcherIndex++];
1731 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1733 if (N->getOpcode() != ISD::AND) return false;
1735 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1736 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1739 ALWAYS_INLINE static bool
1740 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1741 SDValue N, SelectionDAGISel &SDISel) {
1742 int64_t Val = MatcherTable[MatcherIndex++];
1744 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1746 if (N->getOpcode() != ISD::OR) return false;
1748 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1749 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1752 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1753 /// scope, evaluate the current node. If the current predicate is known to
1754 /// fail, set Result=true and return anything. If the current predicate is
1755 /// known to pass, set Result=false and return the MatcherIndex to continue
1756 /// with. If the current predicate is unknown, set Result=false and return the
1757 /// MatcherIndex to continue with.
1758 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1759 unsigned Index, SDValue N,
1760 bool &Result, SelectionDAGISel &SDISel,
1761 SmallVectorImpl<SDValue> &RecordedNodes){
1762 switch (Table[Index++]) {
1765 return Index-1; // Could not evaluate this predicate.
1766 case SelectionDAGISel::OPC_CheckSame:
1767 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1769 case SelectionDAGISel::OPC_CheckPatternPredicate:
1770 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1772 case SelectionDAGISel::OPC_CheckPredicate:
1773 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1775 case SelectionDAGISel::OPC_CheckOpcode:
1776 Result = !::CheckOpcode(Table, Index, N.getNode());
1778 case SelectionDAGISel::OPC_CheckType:
1779 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1781 case SelectionDAGISel::OPC_CheckChild0Type:
1782 case SelectionDAGISel::OPC_CheckChild1Type:
1783 case SelectionDAGISel::OPC_CheckChild2Type:
1784 case SelectionDAGISel::OPC_CheckChild3Type:
1785 case SelectionDAGISel::OPC_CheckChild4Type:
1786 case SelectionDAGISel::OPC_CheckChild5Type:
1787 case SelectionDAGISel::OPC_CheckChild6Type:
1788 case SelectionDAGISel::OPC_CheckChild7Type:
1789 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1790 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1792 case SelectionDAGISel::OPC_CheckCondCode:
1793 Result = !::CheckCondCode(Table, Index, N);
1795 case SelectionDAGISel::OPC_CheckValueType:
1796 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1798 case SelectionDAGISel::OPC_CheckInteger:
1799 Result = !::CheckInteger(Table, Index, N);
1801 case SelectionDAGISel::OPC_CheckAndImm:
1802 Result = !::CheckAndImm(Table, Index, N, SDISel);
1804 case SelectionDAGISel::OPC_CheckOrImm:
1805 Result = !::CheckOrImm(Table, Index, N, SDISel);
1813 /// FailIndex - If this match fails, this is the index to continue with.
1816 /// NodeStack - The node stack when the scope was formed.
1817 SmallVector<SDValue, 4> NodeStack;
1819 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1820 unsigned NumRecordedNodes;
1822 /// NumMatchedMemRefs - The number of matched memref entries.
1823 unsigned NumMatchedMemRefs;
1825 /// InputChain/InputFlag - The current chain/flag
1826 SDValue InputChain, InputFlag;
1828 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1829 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1834 SDNode *SelectionDAGISel::
1835 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1836 unsigned TableSize) {
1837 // FIXME: Should these even be selected? Handle these cases in the caller?
1838 switch (NodeToMatch->getOpcode()) {
1841 case ISD::EntryToken: // These nodes remain the same.
1842 case ISD::BasicBlock:
1844 //case ISD::VALUETYPE:
1845 //case ISD::CONDCODE:
1846 case ISD::HANDLENODE:
1847 case ISD::MDNODE_SDNODE:
1848 case ISD::TargetConstant:
1849 case ISD::TargetConstantFP:
1850 case ISD::TargetConstantPool:
1851 case ISD::TargetFrameIndex:
1852 case ISD::TargetExternalSymbol:
1853 case ISD::TargetBlockAddress:
1854 case ISD::TargetJumpTable:
1855 case ISD::TargetGlobalTLSAddress:
1856 case ISD::TargetGlobalAddress:
1857 case ISD::TokenFactor:
1858 case ISD::CopyFromReg:
1859 case ISD::CopyToReg:
1861 NodeToMatch->setNodeId(-1); // Mark selected.
1863 case ISD::AssertSext:
1864 case ISD::AssertZext:
1865 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1866 NodeToMatch->getOperand(0));
1868 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1869 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1872 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1874 // Set up the node stack with NodeToMatch as the only node on the stack.
1875 SmallVector<SDValue, 8> NodeStack;
1876 SDValue N = SDValue(NodeToMatch, 0);
1877 NodeStack.push_back(N);
1879 // MatchScopes - Scopes used when matching, if a match failure happens, this
1880 // indicates where to continue checking.
1881 SmallVector<MatchScope, 8> MatchScopes;
1883 // RecordedNodes - This is the set of nodes that have been recorded by the
1885 SmallVector<SDValue, 8> RecordedNodes;
1887 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1889 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1891 // These are the current input chain and flag for use when generating nodes.
1892 // Various Emit operations change these. For example, emitting a copytoreg
1893 // uses and updates these.
1894 SDValue InputChain, InputFlag;
1896 // ChainNodesMatched - If a pattern matches nodes that have input/output
1897 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1898 // which ones they are. The result is captured into this list so that we can
1899 // update the chain results when the pattern is complete.
1900 SmallVector<SDNode*, 3> ChainNodesMatched;
1901 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1903 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1904 NodeToMatch->dump(CurDAG);
1907 // Determine where to start the interpreter. Normally we start at opcode #0,
1908 // but if the state machine starts with an OPC_SwitchOpcode, then we
1909 // accelerate the first lookup (which is guaranteed to be hot) with the
1910 // OpcodeOffset table.
1911 unsigned MatcherIndex = 0;
1913 if (!OpcodeOffset.empty()) {
1914 // Already computed the OpcodeOffset table, just index into it.
1915 if (N.getOpcode() < OpcodeOffset.size())
1916 MatcherIndex = OpcodeOffset[N.getOpcode()];
1917 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1919 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1920 // Otherwise, the table isn't computed, but the state machine does start
1921 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1922 // is the first time we're selecting an instruction.
1925 // Get the size of this case.
1926 unsigned CaseSize = MatcherTable[Idx++];
1928 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1929 if (CaseSize == 0) break;
1931 // Get the opcode, add the index to the table.
1932 uint16_t Opc = MatcherTable[Idx++];
1933 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1934 if (Opc >= OpcodeOffset.size())
1935 OpcodeOffset.resize((Opc+1)*2);
1936 OpcodeOffset[Opc] = Idx;
1940 // Okay, do the lookup for the first opcode.
1941 if (N.getOpcode() < OpcodeOffset.size())
1942 MatcherIndex = OpcodeOffset[N.getOpcode()];
1946 assert(MatcherIndex < TableSize && "Invalid index");
1948 unsigned CurrentOpcodeIndex = MatcherIndex;
1950 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1953 // Okay, the semantics of this operation are that we should push a scope
1954 // then evaluate the first child. However, pushing a scope only to have
1955 // the first check fail (which then pops it) is inefficient. If we can
1956 // determine immediately that the first check (or first several) will
1957 // immediately fail, don't even bother pushing a scope for them.
1961 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1962 if (NumToSkip & 128)
1963 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1964 // Found the end of the scope with no match.
1965 if (NumToSkip == 0) {
1970 FailIndex = MatcherIndex+NumToSkip;
1972 unsigned MatcherIndexOfPredicate = MatcherIndex;
1973 (void)MatcherIndexOfPredicate; // silence warning.
1975 // If we can't evaluate this predicate without pushing a scope (e.g. if
1976 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1977 // push the scope and evaluate the full predicate chain.
1979 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1980 Result, *this, RecordedNodes);
1984 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
1985 << "index " << MatcherIndexOfPredicate
1986 << ", continuing at " << FailIndex << "\n");
1987 ++NumDAGIselRetries;
1989 // Otherwise, we know that this case of the Scope is guaranteed to fail,
1990 // move to the next case.
1991 MatcherIndex = FailIndex;
1994 // If the whole scope failed to match, bail.
1995 if (FailIndex == 0) break;
1997 // Push a MatchScope which indicates where to go if the first child fails
1999 MatchScope NewEntry;
2000 NewEntry.FailIndex = FailIndex;
2001 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2002 NewEntry.NumRecordedNodes = RecordedNodes.size();
2003 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2004 NewEntry.InputChain = InputChain;
2005 NewEntry.InputFlag = InputFlag;
2006 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2007 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2008 MatchScopes.push_back(NewEntry);
2011 case OPC_RecordNode:
2012 // Remember this node, it may end up being an operand in the pattern.
2013 RecordedNodes.push_back(N);
2016 case OPC_RecordChild0: case OPC_RecordChild1:
2017 case OPC_RecordChild2: case OPC_RecordChild3:
2018 case OPC_RecordChild4: case OPC_RecordChild5:
2019 case OPC_RecordChild6: case OPC_RecordChild7: {
2020 unsigned ChildNo = Opcode-OPC_RecordChild0;
2021 if (ChildNo >= N.getNumOperands())
2022 break; // Match fails if out of range child #.
2024 RecordedNodes.push_back(N->getOperand(ChildNo));
2027 case OPC_RecordMemRef:
2028 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2031 case OPC_CaptureFlagInput:
2032 // If the current node has an input flag, capture it in InputFlag.
2033 if (N->getNumOperands() != 0 &&
2034 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2035 InputFlag = N->getOperand(N->getNumOperands()-1);
2038 case OPC_MoveChild: {
2039 unsigned ChildNo = MatcherTable[MatcherIndex++];
2040 if (ChildNo >= N.getNumOperands())
2041 break; // Match fails if out of range child #.
2042 N = N.getOperand(ChildNo);
2043 NodeStack.push_back(N);
2047 case OPC_MoveParent:
2048 // Pop the current node off the NodeStack.
2049 NodeStack.pop_back();
2050 assert(!NodeStack.empty() && "Node stack imbalance!");
2051 N = NodeStack.back();
2055 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2057 case OPC_CheckPatternPredicate:
2058 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2060 case OPC_CheckPredicate:
2061 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2065 case OPC_CheckComplexPat: {
2066 unsigned CPNum = MatcherTable[MatcherIndex++];
2067 unsigned RecNo = MatcherTable[MatcherIndex++];
2068 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2069 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2074 case OPC_CheckOpcode:
2075 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2079 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2082 case OPC_SwitchOpcode: {
2083 unsigned CurNodeOpcode = N.getOpcode();
2084 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2087 // Get the size of this case.
2088 CaseSize = MatcherTable[MatcherIndex++];
2090 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2091 if (CaseSize == 0) break;
2093 uint16_t Opc = MatcherTable[MatcherIndex++];
2094 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2096 // If the opcode matches, then we will execute this case.
2097 if (CurNodeOpcode == Opc)
2100 // Otherwise, skip over this case.
2101 MatcherIndex += CaseSize;
2104 // If no cases matched, bail out.
2105 if (CaseSize == 0) break;
2107 // Otherwise, execute the case we found.
2108 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2109 << " to " << MatcherIndex << "\n");
2113 case OPC_SwitchType: {
2114 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2115 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2118 // Get the size of this case.
2119 CaseSize = MatcherTable[MatcherIndex++];
2121 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2122 if (CaseSize == 0) break;
2124 MVT::SimpleValueType CaseVT =
2125 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2126 if (CaseVT == MVT::iPTR)
2127 CaseVT = TLI.getPointerTy().SimpleTy;
2129 // If the VT matches, then we will execute this case.
2130 if (CurNodeVT == CaseVT)
2133 // Otherwise, skip over this case.
2134 MatcherIndex += CaseSize;
2137 // If no cases matched, bail out.
2138 if (CaseSize == 0) break;
2140 // Otherwise, execute the case we found.
2141 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2142 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2145 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2146 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2147 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2148 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2149 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2150 Opcode-OPC_CheckChild0Type))
2153 case OPC_CheckCondCode:
2154 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2156 case OPC_CheckValueType:
2157 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2159 case OPC_CheckInteger:
2160 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2162 case OPC_CheckAndImm:
2163 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2165 case OPC_CheckOrImm:
2166 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2169 case OPC_CheckFoldableChainNode: {
2170 assert(NodeStack.size() != 1 && "No parent node");
2171 // Verify that all intermediate nodes between the root and this one have
2173 bool HasMultipleUses = false;
2174 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2175 if (!NodeStack[i].hasOneUse()) {
2176 HasMultipleUses = true;
2179 if (HasMultipleUses) break;
2181 // Check to see that the target thinks this is profitable to fold and that
2182 // we can fold it without inducing cycles in the graph.
2183 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2185 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2186 NodeToMatch, OptLevel,
2187 true/*We validate our own chains*/))
2192 case OPC_EmitInteger: {
2193 MVT::SimpleValueType VT =
2194 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2195 int64_t Val = MatcherTable[MatcherIndex++];
2197 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2198 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2201 case OPC_EmitRegister: {
2202 MVT::SimpleValueType VT =
2203 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2204 unsigned RegNo = MatcherTable[MatcherIndex++];
2205 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2209 case OPC_EmitConvertToTarget: {
2210 // Convert from IMM/FPIMM to target version.
2211 unsigned RecNo = MatcherTable[MatcherIndex++];
2212 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2213 SDValue Imm = RecordedNodes[RecNo];
2215 if (Imm->getOpcode() == ISD::Constant) {
2216 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2217 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2218 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2219 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2220 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2223 RecordedNodes.push_back(Imm);
2227 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2228 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2229 // These are space-optimized forms of OPC_EmitMergeInputChains.
2230 assert(InputChain.getNode() == 0 &&
2231 "EmitMergeInputChains should be the first chain producing node");
2232 assert(ChainNodesMatched.empty() &&
2233 "Should only have one EmitMergeInputChains per match");
2235 // Read all of the chained nodes.
2236 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2237 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2238 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2240 // FIXME: What if other value results of the node have uses not matched
2242 if (ChainNodesMatched.back() != NodeToMatch &&
2243 !RecordedNodes[RecNo].hasOneUse()) {
2244 ChainNodesMatched.clear();
2248 // Merge the input chains if they are not intra-pattern references.
2249 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2251 if (InputChain.getNode() == 0)
2252 break; // Failed to merge.
2256 case OPC_EmitMergeInputChains: {
2257 assert(InputChain.getNode() == 0 &&
2258 "EmitMergeInputChains should be the first chain producing node");
2259 // This node gets a list of nodes we matched in the input that have
2260 // chains. We want to token factor all of the input chains to these nodes
2261 // together. However, if any of the input chains is actually one of the
2262 // nodes matched in this pattern, then we have an intra-match reference.
2263 // Ignore these because the newly token factored chain should not refer to
2265 unsigned NumChains = MatcherTable[MatcherIndex++];
2266 assert(NumChains != 0 && "Can't TF zero chains");
2268 assert(ChainNodesMatched.empty() &&
2269 "Should only have one EmitMergeInputChains per match");
2271 // Read all of the chained nodes.
2272 for (unsigned i = 0; i != NumChains; ++i) {
2273 unsigned RecNo = MatcherTable[MatcherIndex++];
2274 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2275 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2277 // FIXME: What if other value results of the node have uses not matched
2279 if (ChainNodesMatched.back() != NodeToMatch &&
2280 !RecordedNodes[RecNo].hasOneUse()) {
2281 ChainNodesMatched.clear();
2286 // If the inner loop broke out, the match fails.
2287 if (ChainNodesMatched.empty())
2290 // Merge the input chains if they are not intra-pattern references.
2291 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2293 if (InputChain.getNode() == 0)
2294 break; // Failed to merge.
2299 case OPC_EmitCopyToReg: {
2300 unsigned RecNo = MatcherTable[MatcherIndex++];
2301 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2302 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2304 if (InputChain.getNode() == 0)
2305 InputChain = CurDAG->getEntryNode();
2307 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2308 DestPhysReg, RecordedNodes[RecNo],
2311 InputFlag = InputChain.getValue(1);
2315 case OPC_EmitNodeXForm: {
2316 unsigned XFormNo = MatcherTable[MatcherIndex++];
2317 unsigned RecNo = MatcherTable[MatcherIndex++];
2318 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2319 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2324 case OPC_MorphNodeTo: {
2325 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2326 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2327 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2328 // Get the result VT list.
2329 unsigned NumVTs = MatcherTable[MatcherIndex++];
2330 SmallVector<EVT, 4> VTs;
2331 for (unsigned i = 0; i != NumVTs; ++i) {
2332 MVT::SimpleValueType VT =
2333 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2334 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2338 if (EmitNodeInfo & OPFL_Chain)
2339 VTs.push_back(MVT::Other);
2340 if (EmitNodeInfo & OPFL_FlagOutput)
2341 VTs.push_back(MVT::Flag);
2343 // This is hot code, so optimize the two most common cases of 1 and 2
2346 if (VTs.size() == 1)
2347 VTList = CurDAG->getVTList(VTs[0]);
2348 else if (VTs.size() == 2)
2349 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2351 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2353 // Get the operand list.
2354 unsigned NumOps = MatcherTable[MatcherIndex++];
2355 SmallVector<SDValue, 8> Ops;
2356 for (unsigned i = 0; i != NumOps; ++i) {
2357 unsigned RecNo = MatcherTable[MatcherIndex++];
2359 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2361 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2362 Ops.push_back(RecordedNodes[RecNo]);
2365 // If there are variadic operands to add, handle them now.
2366 if (EmitNodeInfo & OPFL_VariadicInfo) {
2367 // Determine the start index to copy from.
2368 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2369 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2370 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2371 "Invalid variadic node");
2372 // Copy all of the variadic operands, not including a potential flag
2374 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2376 SDValue V = NodeToMatch->getOperand(i);
2377 if (V.getValueType() == MVT::Flag) break;
2382 // If this has chain/flag inputs, add them.
2383 if (EmitNodeInfo & OPFL_Chain)
2384 Ops.push_back(InputChain);
2385 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2386 Ops.push_back(InputFlag);
2390 if (Opcode != OPC_MorphNodeTo) {
2391 // If this is a normal EmitNode command, just create the new node and
2392 // add the results to the RecordedNodes list.
2393 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2394 VTList, Ops.data(), Ops.size());
2396 // Add all the non-flag/non-chain results to the RecordedNodes list.
2397 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2398 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2399 RecordedNodes.push_back(SDValue(Res, i));
2403 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2407 // If the node had chain/flag results, update our notion of the current
2409 if (EmitNodeInfo & OPFL_FlagOutput) {
2410 InputFlag = SDValue(Res, VTs.size()-1);
2411 if (EmitNodeInfo & OPFL_Chain)
2412 InputChain = SDValue(Res, VTs.size()-2);
2413 } else if (EmitNodeInfo & OPFL_Chain)
2414 InputChain = SDValue(Res, VTs.size()-1);
2416 // If the OPFL_MemRefs flag is set on this node, slap all of the
2417 // accumulated memrefs onto it.
2419 // FIXME: This is vastly incorrect for patterns with multiple outputs
2420 // instructions that access memory and for ComplexPatterns that match
2422 if (EmitNodeInfo & OPFL_MemRefs) {
2423 MachineSDNode::mmo_iterator MemRefs =
2424 MF->allocateMemRefsArray(MatchedMemRefs.size());
2425 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2426 cast<MachineSDNode>(Res)
2427 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2431 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2432 << " node: "; Res->dump(CurDAG); errs() << "\n");
2434 // If this was a MorphNodeTo then we're completely done!
2435 if (Opcode == OPC_MorphNodeTo) {
2436 // Update chain and flag uses.
2437 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2438 InputFlag, FlagResultNodesMatched, true);
2445 case OPC_MarkFlagResults: {
2446 unsigned NumNodes = MatcherTable[MatcherIndex++];
2448 // Read and remember all the flag-result nodes.
2449 for (unsigned i = 0; i != NumNodes; ++i) {
2450 unsigned RecNo = MatcherTable[MatcherIndex++];
2452 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2454 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2455 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2460 case OPC_CompleteMatch: {
2461 // The match has been completed, and any new nodes (if any) have been
2462 // created. Patch up references to the matched dag to use the newly
2464 unsigned NumResults = MatcherTable[MatcherIndex++];
2466 for (unsigned i = 0; i != NumResults; ++i) {
2467 unsigned ResSlot = MatcherTable[MatcherIndex++];
2469 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2471 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2472 SDValue Res = RecordedNodes[ResSlot];
2474 assert(i < NodeToMatch->getNumValues() &&
2475 NodeToMatch->getValueType(i) != MVT::Other &&
2476 NodeToMatch->getValueType(i) != MVT::Flag &&
2477 "Invalid number of results to complete!");
2478 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2479 NodeToMatch->getValueType(i) == MVT::iPTR ||
2480 Res.getValueType() == MVT::iPTR ||
2481 NodeToMatch->getValueType(i).getSizeInBits() ==
2482 Res.getValueType().getSizeInBits()) &&
2483 "invalid replacement");
2484 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2487 // If the root node defines a flag, add it to the flag nodes to update
2489 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2490 FlagResultNodesMatched.push_back(NodeToMatch);
2492 // Update chain and flag uses.
2493 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2494 InputFlag, FlagResultNodesMatched, false);
2496 assert(NodeToMatch->use_empty() &&
2497 "Didn't replace all uses of the node?");
2499 // FIXME: We just return here, which interacts correctly with SelectRoot
2500 // above. We should fix this to not return an SDNode* anymore.
2505 // If the code reached this point, then the match failed. See if there is
2506 // another child to try in the current 'Scope', otherwise pop it until we
2507 // find a case to check.
2508 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2509 ++NumDAGIselRetries;
2511 if (MatchScopes.empty()) {
2512 CannotYetSelect(NodeToMatch);
2516 // Restore the interpreter state back to the point where the scope was
2518 MatchScope &LastScope = MatchScopes.back();
2519 RecordedNodes.resize(LastScope.NumRecordedNodes);
2521 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2522 N = NodeStack.back();
2524 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2525 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2526 MatcherIndex = LastScope.FailIndex;
2528 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2530 InputChain = LastScope.InputChain;
2531 InputFlag = LastScope.InputFlag;
2532 if (!LastScope.HasChainNodesMatched)
2533 ChainNodesMatched.clear();
2534 if (!LastScope.HasFlagResultNodesMatched)
2535 FlagResultNodesMatched.clear();
2537 // Check to see what the offset is at the new MatcherIndex. If it is zero
2538 // we have reached the end of this scope, otherwise we have another child
2539 // in the current scope to try.
2540 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2541 if (NumToSkip & 128)
2542 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2544 // If we have another child in this scope to match, update FailIndex and
2546 if (NumToSkip != 0) {
2547 LastScope.FailIndex = MatcherIndex+NumToSkip;
2551 // End of this scope, pop it and try the next child in the containing
2553 MatchScopes.pop_back();
2560 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2562 raw_string_ostream Msg(msg);
2563 Msg << "Cannot yet select: ";
2565 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2566 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2567 N->getOpcode() != ISD::INTRINSIC_VOID) {
2568 N->printrFull(Msg, CurDAG);
2570 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2572 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2573 if (iid < Intrinsic::num_intrinsics)
2574 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2575 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2576 Msg << "target intrinsic %" << TII->getName(iid);
2578 Msg << "unknown intrinsic #" << iid;
2580 report_fatal_error(Msg.str());
2583 char SelectionDAGISel::ID = 0;