1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register"
85 static RegisterScheduler
86 defaultListDAGScheduler("default", " Best scheduler for the target",
87 createDefaultScheduler);
90 namespace { struct SDISelAsmOperandInfo; }
93 /// RegsForValue - This struct represents the physical registers that a
94 /// particular value is assigned and the type information about the value.
95 /// This is needed because values can be promoted into larger registers and
96 /// expanded into multiple smaller registers than the value.
97 struct VISIBILITY_HIDDEN RegsForValue {
98 /// Regs - This list holds the register (for legal and promoted values)
99 /// or register set (for expanded values) that the value should be assigned
101 std::vector<unsigned> Regs;
103 /// RegVT - The value type of each register.
105 MVT::ValueType RegVT;
107 /// ValueVT - The value type of the LLVM value, which may be promoted from
108 /// RegVT or made from merging the two expanded parts.
109 MVT::ValueType ValueVT;
111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
114 : RegVT(regvt), ValueVT(valuevt) {
117 RegsForValue(const std::vector<unsigned> ®s,
118 MVT::ValueType regvt, MVT::ValueType valuevt)
119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
123 /// this value and returns the result as a ValueVT value. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
125 /// If the Flag pointer is NULL, no flag is used.
126 SDOperand getCopyFromRegs(SelectionDAG &DAG,
127 SDOperand &Chain, SDOperand *Flag) const;
129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
130 /// specified value into the registers specified by this object. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 /// If the Flag pointer is NULL, no flag is used.
133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
134 SDOperand &Chain, SDOperand *Flag) const;
136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
137 /// operand list. This adds the code marker and includes the number of
138 /// values added into it.
139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
140 std::vector<SDOperand> &Ops) const;
145 //===--------------------------------------------------------------------===//
146 /// createDefaultScheduler - This creates an instruction scheduler appropriate
148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
150 MachineBasicBlock *BB) {
151 TargetLowering &TLI = IS->getTargetLowering();
153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
154 return createTDListDAGScheduler(IS, DAG, BB);
156 assert(TLI.getSchedulingPreference() ==
157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
158 return createBURRListDAGScheduler(IS, DAG, BB);
163 //===--------------------------------------------------------------------===//
164 /// FunctionLoweringInfo - This contains information that is global to a
165 /// function that is used when lowering a region of the function.
166 class FunctionLoweringInfo {
171 MachineRegisterInfo &RegInfo;
173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
178 /// ValueMap - Since we emit code for the function a basic block at a time,
179 /// we must remember which virtual registers hold the values for
180 /// cross-basic-block values.
181 DenseMap<const Value*, unsigned> ValueMap;
183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
184 /// the entry block. This allows the allocas to be efficiently referenced
185 /// anywhere in the function.
186 std::map<const AllocaInst*, int> StaticAllocaMap;
189 SmallSet<Instruction*, 8> CatchInfoLost;
190 SmallSet<Instruction*, 8> CatchInfoFound;
193 unsigned MakeReg(MVT::ValueType VT) {
194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
197 /// isExportedInst - Return true if the specified value is an instruction
198 /// exported from its block.
199 bool isExportedInst(const Value *V) {
200 return ValueMap.count(V);
203 unsigned CreateRegForValue(const Value *V);
205 unsigned InitializeRegForValue(const Value *V) {
206 unsigned &R = ValueMap[V];
207 assert(R == 0 && "Already initialized this value register!");
208 return R = CreateRegForValue(V);
213 /// isSelector - Return true if this instruction is a call to the
214 /// eh.selector intrinsic.
215 static bool isSelector(Instruction *I) {
216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
218 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
222 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
223 /// PHI nodes or outside of the basic block that defines it, or used by a
224 /// switch or atomic instruction, which may expand to multiple basic blocks.
225 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
226 if (isa<PHINode>(I)) return true;
227 BasicBlock *BB = I->getParent();
228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
230 // FIXME: Remove switchinst special case.
231 isa<SwitchInst>(*UI))
236 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
237 /// entry block, return true. This includes arguments used by switches, since
238 /// the switch may expand into multiple basic blocks.
239 static bool isOnlyUsedInEntryBlock(Argument *A) {
240 BasicBlock *Entry = A->getParent()->begin();
241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
243 return false; // Use not in entry block.
247 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
248 Function &fn, MachineFunction &mf)
249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
251 // Create a vreg for each argument register that is not dead and is used
252 // outside of the entry block for the function.
253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
255 if (!isOnlyUsedInEntryBlock(AI))
256 InitializeRegForValue(AI);
258 // Initialize the mapping of values to registers. This is only set up for
259 // instruction values that are used outside of the block that defines
261 Function::iterator BB = Fn.begin(), EB = Fn.end();
262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
265 const Type *Ty = AI->getAllocatedType();
266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
271 TySize *= CUI->getZExtValue(); // Get total allocated size.
272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
273 StaticAllocaMap[AI] =
274 MF.getFrameInfo()->CreateStackObject(TySize, Align);
277 for (; BB != EB; ++BB)
278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
280 if (!isa<AllocaInst>(I) ||
281 !StaticAllocaMap.count(cast<AllocaInst>(I)))
282 InitializeRegForValue(I);
284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
285 // also creates the initial PHI MachineInstrs, though none of the input
286 // operands are populated.
287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
288 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
290 MF.getBasicBlockList().push_back(MBB);
292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
296 if (PN->use_empty()) continue;
298 MVT::ValueType VT = TLI.getValueType(PN->getType());
299 unsigned NumRegisters = TLI.getNumRegisters(VT);
300 unsigned PHIReg = ValueMap[PN];
301 assert(PHIReg && "PHI node does not have an assigned virtual register!");
302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
303 for (unsigned i = 0; i != NumRegisters; ++i)
304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
309 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
310 /// the correctly promoted or expanded types. Assign these registers
311 /// consecutive vreg numbers and return the first assigned number.
312 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
313 MVT::ValueType VT = TLI.getValueType(V->getType());
315 unsigned NumRegisters = TLI.getNumRegisters(VT);
316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
318 unsigned R = MakeReg(RegisterVT);
319 for (unsigned i = 1; i != NumRegisters; ++i)
325 //===----------------------------------------------------------------------===//
326 /// SelectionDAGLowering - This is the common target-independent lowering
327 /// implementation that is parameterized by a TargetLowering object.
328 /// Also, targets can overload any lowering method.
331 class SelectionDAGLowering {
332 MachineBasicBlock *CurMBB;
334 DenseMap<const Value*, SDOperand> NodeMap;
336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
337 /// them up and then emit token factor nodes when possible. This allows us to
338 /// get simple disambiguation between loads without worrying about alias
340 std::vector<SDOperand> PendingLoads;
342 /// PendingExports - CopyToReg nodes that copy values to virtual registers
343 /// for export to other blocks need to be emitted before any terminator
344 /// instruction, but they have no other ordering requirements. We bunch them
345 /// up and the emit a single tokenfactor for them just before terminator
347 std::vector<SDOperand> PendingExports;
349 /// Case - A struct to record the Value for a switch case, and the
350 /// case's target basic block.
354 MachineBasicBlock* BB;
356 Case() : Low(0), High(0), BB(0) { }
357 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
358 Low(low), High(high), BB(bb) { }
359 uint64_t size() const {
360 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
361 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
362 return (rHigh - rLow + 1ULL);
368 MachineBasicBlock* BB;
371 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
372 Mask(mask), BB(bb), Bits(bits) { }
375 typedef std::vector<Case> CaseVector;
376 typedef std::vector<CaseBits> CaseBitsVector;
377 typedef CaseVector::iterator CaseItr;
378 typedef std::pair<CaseItr, CaseItr> CaseRange;
380 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
381 /// of conditional branches.
383 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
384 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
386 /// CaseBB - The MBB in which to emit the compare and branch
387 MachineBasicBlock *CaseBB;
388 /// LT, GE - If nonzero, we know the current case value must be less-than or
389 /// greater-than-or-equal-to these Constants.
392 /// Range - A pair of iterators representing the range of case values to be
393 /// processed at this point in the binary search tree.
397 typedef std::vector<CaseRec> CaseRecVector;
399 /// The comparison function for sorting the switch case values in the vector.
400 /// WARNING: Case ranges should be disjoint!
402 bool operator () (const Case& C1, const Case& C2) {
403 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
404 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
405 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
406 return CI1->getValue().slt(CI2->getValue());
411 bool operator () (const CaseBits& C1, const CaseBits& C2) {
412 return C1.Bits > C2.Bits;
416 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
419 // TLI - This is information that describes the available target features we
420 // need for lowering. This indicates when operations are unavailable,
421 // implemented with a libcall, etc.
424 const TargetData *TD;
427 /// SwitchCases - Vector of CaseBlock structures used to communicate
428 /// SwitchInst code generation information.
429 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
430 /// JTCases - Vector of JumpTable structures used to communicate
431 /// SwitchInst code generation information.
432 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
433 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
435 /// FuncInfo - Information about the function as a whole.
437 FunctionLoweringInfo &FuncInfo;
439 /// GCI - Garbage collection metadata for the function.
440 CollectorMetadata *GCI;
442 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
444 FunctionLoweringInfo &funcinfo,
445 CollectorMetadata *gci)
446 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
447 FuncInfo(funcinfo), GCI(gci) {
450 /// getRoot - Return the current virtual root of the Selection DAG,
451 /// flushing any PendingLoad items. This must be done before emitting
452 /// a store or any other node that may need to be ordered after any
453 /// prior load instructions.
455 SDOperand getRoot() {
456 if (PendingLoads.empty())
457 return DAG.getRoot();
459 if (PendingLoads.size() == 1) {
460 SDOperand Root = PendingLoads[0];
462 PendingLoads.clear();
466 // Otherwise, we have to make a token factor node.
467 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
468 &PendingLoads[0], PendingLoads.size());
469 PendingLoads.clear();
474 /// getControlRoot - Similar to getRoot, but instead of flushing all the
475 /// PendingLoad items, flush all the PendingExports items. It is necessary
476 /// to do this before emitting a terminator instruction.
478 SDOperand getControlRoot() {
479 SDOperand Root = DAG.getRoot();
481 if (PendingExports.empty())
484 // Turn all of the CopyToReg chains into one factored node.
485 if (Root.getOpcode() != ISD::EntryToken) {
486 unsigned i = 0, e = PendingExports.size();
487 for (; i != e; ++i) {
488 assert(PendingExports[i].Val->getNumOperands() > 1);
489 if (PendingExports[i].Val->getOperand(0) == Root)
490 break; // Don't add the root if we already indirectly depend on it.
494 PendingExports.push_back(Root);
497 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
499 PendingExports.size());
500 PendingExports.clear();
505 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
507 void visit(Instruction &I) { visit(I.getOpcode(), I); }
509 void visit(unsigned Opcode, User &I) {
510 // Note: this doesn't use InstVisitor, because it has to work with
511 // ConstantExpr's in addition to instructions.
513 default: assert(0 && "Unknown instruction type encountered!");
515 // Build the switch statement using the Instruction.def file.
516 #define HANDLE_INST(NUM, OPCODE, CLASS) \
517 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
518 #include "llvm/Instruction.def"
522 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
524 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
525 const Value *SV, SDOperand Root,
526 bool isVolatile, unsigned Alignment);
528 SDOperand getValue(const Value *V);
530 void setValue(const Value *V, SDOperand NewN) {
531 SDOperand &N = NodeMap[V];
532 assert(N.Val == 0 && "Already set a value for this node!");
536 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
537 std::set<unsigned> &OutputRegs,
538 std::set<unsigned> &InputRegs);
540 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
541 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
543 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
544 void ExportFromCurrentBlock(Value *V);
545 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
546 MachineBasicBlock *LandingPad = NULL);
548 // Terminator instructions.
549 void visitRet(ReturnInst &I);
550 void visitBr(BranchInst &I);
551 void visitSwitch(SwitchInst &I);
552 void visitUnreachable(UnreachableInst &I) { /* noop */ }
554 // Helpers for visitSwitch
555 bool handleSmallSwitchRange(CaseRec& CR,
556 CaseRecVector& WorkList,
558 MachineBasicBlock* Default);
559 bool handleJTSwitchCase(CaseRec& CR,
560 CaseRecVector& WorkList,
562 MachineBasicBlock* Default);
563 bool handleBTSplitSwitchCase(CaseRec& CR,
564 CaseRecVector& WorkList,
566 MachineBasicBlock* Default);
567 bool handleBitTestsSwitchCase(CaseRec& CR,
568 CaseRecVector& WorkList,
570 MachineBasicBlock* Default);
571 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
572 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
573 void visitBitTestCase(MachineBasicBlock* NextMBB,
575 SelectionDAGISel::BitTestCase &B);
576 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
577 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
578 SelectionDAGISel::JumpTableHeader &JTH);
580 // These all get lowered before this pass.
581 void visitInvoke(InvokeInst &I);
582 void visitUnwind(UnwindInst &I);
584 void visitBinary(User &I, unsigned OpCode);
585 void visitShift(User &I, unsigned Opcode);
586 void visitAdd(User &I) {
587 if (I.getType()->isFPOrFPVector())
588 visitBinary(I, ISD::FADD);
590 visitBinary(I, ISD::ADD);
592 void visitSub(User &I);
593 void visitMul(User &I) {
594 if (I.getType()->isFPOrFPVector())
595 visitBinary(I, ISD::FMUL);
597 visitBinary(I, ISD::MUL);
599 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
600 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
601 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
602 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
603 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
604 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
605 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
606 void visitOr (User &I) { visitBinary(I, ISD::OR); }
607 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
608 void visitShl (User &I) { visitShift(I, ISD::SHL); }
609 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
610 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
611 void visitICmp(User &I);
612 void visitFCmp(User &I);
613 // Visit the conversion instructions
614 void visitTrunc(User &I);
615 void visitZExt(User &I);
616 void visitSExt(User &I);
617 void visitFPTrunc(User &I);
618 void visitFPExt(User &I);
619 void visitFPToUI(User &I);
620 void visitFPToSI(User &I);
621 void visitUIToFP(User &I);
622 void visitSIToFP(User &I);
623 void visitPtrToInt(User &I);
624 void visitIntToPtr(User &I);
625 void visitBitCast(User &I);
627 void visitExtractElement(User &I);
628 void visitInsertElement(User &I);
629 void visitShuffleVector(User &I);
631 void visitGetElementPtr(User &I);
632 void visitSelect(User &I);
634 void visitMalloc(MallocInst &I);
635 void visitFree(FreeInst &I);
636 void visitAlloca(AllocaInst &I);
637 void visitLoad(LoadInst &I);
638 void visitStore(StoreInst &I);
639 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
640 void visitCall(CallInst &I);
641 void visitInlineAsm(CallSite CS);
642 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
643 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
645 void visitVAStart(CallInst &I);
646 void visitVAArg(VAArgInst &I);
647 void visitVAEnd(CallInst &I);
648 void visitVACopy(CallInst &I);
650 void visitMemIntrinsic(CallInst &I, unsigned Op);
652 void visitGetResult(GetResultInst &I);
654 void visitUserOp1(Instruction &I) {
655 assert(0 && "UserOp1 should not exist at instruction selection time!");
658 void visitUserOp2(Instruction &I) {
659 assert(0 && "UserOp2 should not exist at instruction selection time!");
663 } // end namespace llvm
666 /// getCopyFromParts - Create a value that contains the specified legal parts
667 /// combined into the value they represent. If the parts combine to a type
668 /// larger then ValueVT then AssertOp can be used to specify whether the extra
669 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
670 /// (ISD::AssertSext).
671 static SDOperand getCopyFromParts(SelectionDAG &DAG,
672 const SDOperand *Parts,
674 MVT::ValueType PartVT,
675 MVT::ValueType ValueVT,
676 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
677 assert(NumParts > 0 && "No parts to assemble!");
678 TargetLowering &TLI = DAG.getTargetLoweringInfo();
679 SDOperand Val = Parts[0];
682 // Assemble the value from multiple parts.
683 if (!MVT::isVector(ValueVT)) {
684 unsigned PartBits = MVT::getSizeInBits(PartVT);
685 unsigned ValueBits = MVT::getSizeInBits(ValueVT);
687 // Assemble the power of 2 part.
688 unsigned RoundParts = NumParts & (NumParts - 1) ?
689 1 << Log2_32(NumParts) : NumParts;
690 unsigned RoundBits = PartBits * RoundParts;
691 MVT::ValueType RoundVT = RoundBits == ValueBits ?
692 ValueVT : MVT::getIntegerType(RoundBits);
695 if (RoundParts > 2) {
696 MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2);
697 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
698 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
704 if (TLI.isBigEndian())
706 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
708 if (RoundParts < NumParts) {
709 // Assemble the trailing non-power-of-2 part.
710 unsigned OddParts = NumParts - RoundParts;
711 MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits);
712 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
714 // Combine the round and odd parts.
716 if (TLI.isBigEndian())
718 MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits);
719 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
720 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
721 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
722 TLI.getShiftAmountTy()));
723 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
724 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
727 // Handle a multi-element vector.
728 MVT::ValueType IntermediateVT, RegisterVT;
729 unsigned NumIntermediates;
731 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
734 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
735 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
736 assert(RegisterVT == Parts[0].getValueType() &&
737 "Part type doesn't match part!");
739 // Assemble the parts into intermediate operands.
740 SmallVector<SDOperand, 8> Ops(NumIntermediates);
741 if (NumIntermediates == NumParts) {
742 // If the register was not expanded, truncate or copy the value,
744 for (unsigned i = 0; i != NumParts; ++i)
745 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
746 PartVT, IntermediateVT);
747 } else if (NumParts > 0) {
748 // If the intermediate type was expanded, build the intermediate operands
750 assert(NumParts % NumIntermediates == 0 &&
751 "Must expand into a divisible number of parts!");
752 unsigned Factor = NumParts / NumIntermediates;
753 for (unsigned i = 0; i != NumIntermediates; ++i)
754 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
755 PartVT, IntermediateVT);
758 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
760 Val = DAG.getNode(MVT::isVector(IntermediateVT) ?
761 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
762 ValueVT, &Ops[0], NumIntermediates);
766 // There is now one part, held in Val. Correct it to match ValueVT.
767 PartVT = Val.getValueType();
769 if (PartVT == ValueVT)
772 if (MVT::isVector(PartVT)) {
773 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
774 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
777 if (MVT::isVector(ValueVT)) {
778 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
779 MVT::getVectorNumElements(ValueVT) == 1 &&
780 "Only trivial scalar-to-vector conversions should get here!");
781 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
784 if (MVT::isInteger(PartVT) &&
785 MVT::isInteger(ValueVT)) {
786 if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) {
787 // For a truncate, see if we have any information to
788 // indicate whether the truncated bits will always be
789 // zero or sign-extension.
790 if (AssertOp != ISD::DELETED_NODE)
791 Val = DAG.getNode(AssertOp, PartVT, Val,
792 DAG.getValueType(ValueVT));
793 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
795 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
799 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
800 if (ValueVT < Val.getValueType())
801 // FP_ROUND's are always exact here.
802 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
803 DAG.getIntPtrConstant(1));
804 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
807 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
808 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
810 assert(0 && "Unknown mismatch!");
813 /// getCopyToParts - Create a series of nodes that contain the specified value
814 /// split into legal parts. If the parts contain more bits than Val, then, for
815 /// integers, ExtendKind can be used to specify how to generate the extra bits.
816 static void getCopyToParts(SelectionDAG &DAG,
820 MVT::ValueType PartVT,
821 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
822 TargetLowering &TLI = DAG.getTargetLoweringInfo();
823 MVT::ValueType PtrVT = TLI.getPointerTy();
824 MVT::ValueType ValueVT = Val.getValueType();
825 unsigned PartBits = MVT::getSizeInBits(PartVT);
826 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
831 if (!MVT::isVector(ValueVT)) {
832 if (PartVT == ValueVT) {
833 assert(NumParts == 1 && "No-op copy with multiple parts!");
838 if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) {
839 // If the parts cover more bits than the value has, promote the value.
840 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
841 assert(NumParts == 1 && "Do not know what to promote to!");
842 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
843 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
844 ValueVT = MVT::getIntegerType(NumParts * PartBits);
845 Val = DAG.getNode(ExtendKind, ValueVT, Val);
847 assert(0 && "Unknown mismatch!");
849 } else if (PartBits == MVT::getSizeInBits(ValueVT)) {
850 // Different types of the same size.
851 assert(NumParts == 1 && PartVT != ValueVT);
852 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
853 } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) {
854 // If the parts cover less bits than value has, truncate the value.
855 if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
856 ValueVT = MVT::getIntegerType(NumParts * PartBits);
857 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
859 assert(0 && "Unknown mismatch!");
863 // The value may have changed - recompute ValueVT.
864 ValueVT = Val.getValueType();
865 assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) &&
866 "Failed to tile the value with PartVT!");
869 assert(PartVT == ValueVT && "Type conversion failed!");
874 // Expand the value into multiple parts.
875 if (NumParts & (NumParts - 1)) {
876 // The number of parts is not a power of 2. Split off and copy the tail.
877 assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) &&
878 "Do not know what to expand to!");
879 unsigned RoundParts = 1 << Log2_32(NumParts);
880 unsigned RoundBits = RoundParts * PartBits;
881 unsigned OddParts = NumParts - RoundParts;
882 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
883 DAG.getConstant(RoundBits,
884 TLI.getShiftAmountTy()));
885 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
886 if (TLI.isBigEndian())
887 // The odd parts were reversed by getCopyToParts - unreverse them.
888 std::reverse(Parts + RoundParts, Parts + NumParts);
889 NumParts = RoundParts;
890 ValueVT = MVT::getIntegerType(NumParts * PartBits);
891 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
894 // The number of parts is a power of 2. Repeatedly bisect the value using
896 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
897 MVT::getIntegerType(MVT::getSizeInBits(ValueVT)),
899 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
900 for (unsigned i = 0; i < NumParts; i += StepSize) {
901 unsigned ThisBits = StepSize * PartBits / 2;
902 MVT::ValueType ThisVT = MVT::getIntegerType (ThisBits);
903 SDOperand &Part0 = Parts[i];
904 SDOperand &Part1 = Parts[i+StepSize/2];
906 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
907 DAG.getConstant(1, PtrVT));
908 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
909 DAG.getConstant(0, PtrVT));
911 if (ThisBits == PartBits && ThisVT != PartVT) {
912 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
913 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
918 if (TLI.isBigEndian())
919 std::reverse(Parts, Parts + NumParts);
926 if (PartVT != ValueVT) {
927 if (MVT::isVector(PartVT)) {
928 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
930 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
931 MVT::getVectorNumElements(ValueVT) == 1 &&
932 "Only trivial vector-to-scalar conversions should get here!");
933 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
934 DAG.getConstant(0, PtrVT));
942 // Handle a multi-element vector.
943 MVT::ValueType IntermediateVT, RegisterVT;
944 unsigned NumIntermediates;
946 DAG.getTargetLoweringInfo()
947 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
949 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
951 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
952 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
954 // Split the vector into intermediate operands.
955 SmallVector<SDOperand, 8> Ops(NumIntermediates);
956 for (unsigned i = 0; i != NumIntermediates; ++i)
957 if (MVT::isVector(IntermediateVT))
958 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
960 DAG.getConstant(i * (NumElements / NumIntermediates),
963 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
965 DAG.getConstant(i, PtrVT));
967 // Split the intermediate operands into legal parts.
968 if (NumParts == NumIntermediates) {
969 // If the register was not expanded, promote or copy the value,
971 for (unsigned i = 0; i != NumParts; ++i)
972 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
973 } else if (NumParts > 0) {
974 // If the intermediate type was expanded, split each the value into
976 assert(NumParts % NumIntermediates == 0 &&
977 "Must expand into a divisible number of parts!");
978 unsigned Factor = NumParts / NumIntermediates;
979 for (unsigned i = 0; i != NumIntermediates; ++i)
980 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
985 SDOperand SelectionDAGLowering::getValue(const Value *V) {
986 SDOperand &N = NodeMap[V];
989 const Type *VTy = V->getType();
990 MVT::ValueType VT = TLI.getValueType(VTy);
991 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
992 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
993 visit(CE->getOpcode(), *CE);
994 SDOperand N1 = NodeMap[V];
995 assert(N1.Val && "visit didn't populate the ValueMap!");
997 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
998 return N = DAG.getGlobalAddress(GV, VT);
999 } else if (isa<ConstantPointerNull>(C)) {
1000 return N = DAG.getConstant(0, TLI.getPointerTy());
1001 } else if (isa<UndefValue>(C)) {
1002 if (!isa<VectorType>(VTy))
1003 return N = DAG.getNode(ISD::UNDEF, VT);
1005 // Create a BUILD_VECTOR of undef nodes.
1006 const VectorType *PTy = cast<VectorType>(VTy);
1007 unsigned NumElements = PTy->getNumElements();
1008 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1010 SmallVector<SDOperand, 8> Ops;
1011 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
1013 // Create a VConstant node with generic Vector type.
1014 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
1015 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
1016 &Ops[0], Ops.size());
1017 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
1018 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1019 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
1020 unsigned NumElements = PTy->getNumElements();
1021 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1023 // Now that we know the number and type of the elements, push a
1024 // Constant or ConstantFP node onto the ops list for each element of
1025 // the vector constant.
1026 SmallVector<SDOperand, 8> Ops;
1027 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1028 for (unsigned i = 0; i != NumElements; ++i)
1029 Ops.push_back(getValue(CP->getOperand(i)));
1031 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1033 if (MVT::isFloatingPoint(PVT))
1034 Op = DAG.getConstantFP(0, PVT);
1036 Op = DAG.getConstant(0, PVT);
1037 Ops.assign(NumElements, Op);
1040 // Create a BUILD_VECTOR node.
1041 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
1042 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
1045 // Canonicalize all constant ints to be unsigned.
1046 return N = DAG.getConstant(cast<ConstantInt>(C)->getValue(),VT);
1050 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1051 std::map<const AllocaInst*, int>::iterator SI =
1052 FuncInfo.StaticAllocaMap.find(AI);
1053 if (SI != FuncInfo.StaticAllocaMap.end())
1054 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1057 unsigned InReg = FuncInfo.ValueMap[V];
1058 assert(InReg && "Value not in map!");
1060 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
1061 unsigned NumRegs = TLI.getNumRegisters(VT);
1063 std::vector<unsigned> Regs(NumRegs);
1064 for (unsigned i = 0; i != NumRegs; ++i)
1065 Regs[i] = InReg + i;
1067 RegsForValue RFV(Regs, RegisterVT, VT);
1068 SDOperand Chain = DAG.getEntryNode();
1070 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1074 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1075 if (I.getNumOperands() == 0) {
1076 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1079 SmallVector<SDOperand, 8> NewValues;
1080 NewValues.push_back(getControlRoot());
1081 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1082 SDOperand RetOp = getValue(I.getOperand(i));
1083 MVT::ValueType VT = RetOp.getValueType();
1085 // FIXME: C calling convention requires the return type to be promoted to
1086 // at least 32-bit. But this is not necessary for non-C calling conventions.
1087 if (MVT::isInteger(VT)) {
1088 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32);
1089 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT))
1093 unsigned NumParts = TLI.getNumRegisters(VT);
1094 MVT::ValueType PartVT = TLI.getRegisterType(VT);
1095 SmallVector<SDOperand, 4> Parts(NumParts);
1096 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1098 const Function *F = I.getParent()->getParent();
1099 if (F->paramHasAttr(0, ParamAttr::SExt))
1100 ExtendKind = ISD::SIGN_EXTEND;
1101 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1102 ExtendKind = ISD::ZERO_EXTEND;
1104 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
1106 for (unsigned i = 0; i < NumParts; ++i) {
1107 NewValues.push_back(Parts[i]);
1108 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1111 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1112 &NewValues[0], NewValues.size()));
1115 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1116 /// the current basic block, add it to ValueMap now so that we'll get a
1118 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1119 // No need to export constants.
1120 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1122 // Already exported?
1123 if (FuncInfo.isExportedInst(V)) return;
1125 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1126 CopyValueToVirtualRegister(V, Reg);
1129 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1130 const BasicBlock *FromBB) {
1131 // The operands of the setcc have to be in this block. We don't know
1132 // how to export them from some other block.
1133 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1134 // Can export from current BB.
1135 if (VI->getParent() == FromBB)
1138 // Is already exported, noop.
1139 return FuncInfo.isExportedInst(V);
1142 // If this is an argument, we can export it if the BB is the entry block or
1143 // if it is already exported.
1144 if (isa<Argument>(V)) {
1145 if (FromBB == &FromBB->getParent()->getEntryBlock())
1148 // Otherwise, can only export this if it is already exported.
1149 return FuncInfo.isExportedInst(V);
1152 // Otherwise, constants can always be exported.
1156 static bool InBlock(const Value *V, const BasicBlock *BB) {
1157 if (const Instruction *I = dyn_cast<Instruction>(V))
1158 return I->getParent() == BB;
1162 /// FindMergedConditions - If Cond is an expression like
1163 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1164 MachineBasicBlock *TBB,
1165 MachineBasicBlock *FBB,
1166 MachineBasicBlock *CurBB,
1168 // If this node is not part of the or/and tree, emit it as a branch.
1169 Instruction *BOp = dyn_cast<Instruction>(Cond);
1171 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1172 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1173 BOp->getParent() != CurBB->getBasicBlock() ||
1174 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1175 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1176 const BasicBlock *BB = CurBB->getBasicBlock();
1178 // If the leaf of the tree is a comparison, merge the condition into
1180 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1181 // The operands of the cmp have to be in this block. We don't know
1182 // how to export them from some other block. If this is the first block
1183 // of the sequence, no exporting is needed.
1185 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1186 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1187 BOp = cast<Instruction>(Cond);
1188 ISD::CondCode Condition;
1189 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1190 switch (IC->getPredicate()) {
1191 default: assert(0 && "Unknown icmp predicate opcode!");
1192 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1193 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1194 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1195 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1196 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1197 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1198 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1199 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1200 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1201 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1203 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1204 ISD::CondCode FPC, FOC;
1205 switch (FC->getPredicate()) {
1206 default: assert(0 && "Unknown fcmp predicate opcode!");
1207 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1208 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1209 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1210 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1211 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1212 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1213 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1214 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1215 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1216 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1217 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1218 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1219 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1220 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1221 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1222 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1224 if (FiniteOnlyFPMath())
1229 Condition = ISD::SETEQ; // silence warning.
1230 assert(0 && "Unknown compare instruction");
1233 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1234 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1235 SwitchCases.push_back(CB);
1239 // Create a CaseBlock record representing this branch.
1240 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1241 NULL, TBB, FBB, CurBB);
1242 SwitchCases.push_back(CB);
1247 // Create TmpBB after CurBB.
1248 MachineFunction::iterator BBI = CurBB;
1249 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1250 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1252 if (Opc == Instruction::Or) {
1253 // Codegen X | Y as:
1261 // Emit the LHS condition.
1262 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1264 // Emit the RHS condition into TmpBB.
1265 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1267 assert(Opc == Instruction::And && "Unknown merge op!");
1268 // Codegen X & Y as:
1275 // This requires creation of TmpBB after CurBB.
1277 // Emit the LHS condition.
1278 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1280 // Emit the RHS condition into TmpBB.
1281 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1285 /// If the set of cases should be emitted as a series of branches, return true.
1286 /// If we should emit this as a bunch of and/or'd together conditions, return
1289 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1290 if (Cases.size() != 2) return true;
1292 // If this is two comparisons of the same values or'd or and'd together, they
1293 // will get folded into a single comparison, so don't emit two blocks.
1294 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1295 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1296 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1297 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1304 void SelectionDAGLowering::visitBr(BranchInst &I) {
1305 // Update machine-CFG edges.
1306 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1308 // Figure out which block is immediately after the current one.
1309 MachineBasicBlock *NextBlock = 0;
1310 MachineFunction::iterator BBI = CurMBB;
1311 if (++BBI != CurMBB->getParent()->end())
1314 if (I.isUnconditional()) {
1315 // If this is not a fall-through branch, emit the branch.
1316 if (Succ0MBB != NextBlock)
1317 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1318 DAG.getBasicBlock(Succ0MBB)));
1320 // Update machine-CFG edges.
1321 CurMBB->addSuccessor(Succ0MBB);
1325 // If this condition is one of the special cases we handle, do special stuff
1327 Value *CondVal = I.getCondition();
1328 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1330 // If this is a series of conditions that are or'd or and'd together, emit
1331 // this as a sequence of branches instead of setcc's with and/or operations.
1332 // For example, instead of something like:
1345 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1346 if (BOp->hasOneUse() &&
1347 (BOp->getOpcode() == Instruction::And ||
1348 BOp->getOpcode() == Instruction::Or)) {
1349 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1350 // If the compares in later blocks need to use values not currently
1351 // exported from this block, export them now. This block should always
1352 // be the first entry.
1353 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1355 // Allow some cases to be rejected.
1356 if (ShouldEmitAsBranches(SwitchCases)) {
1357 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1358 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1359 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1362 // Emit the branch for this block.
1363 visitSwitchCase(SwitchCases[0]);
1364 SwitchCases.erase(SwitchCases.begin());
1368 // Okay, we decided not to do this, remove any inserted MBB's and clear
1370 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1371 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1373 SwitchCases.clear();
1377 // Create a CaseBlock record representing this branch.
1378 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1379 NULL, Succ0MBB, Succ1MBB, CurMBB);
1380 // Use visitSwitchCase to actually insert the fast branch sequence for this
1382 visitSwitchCase(CB);
1385 /// visitSwitchCase - Emits the necessary code to represent a single node in
1386 /// the binary search tree resulting from lowering a switch instruction.
1387 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1389 SDOperand CondLHS = getValue(CB.CmpLHS);
1391 // Build the setcc now.
1392 if (CB.CmpMHS == NULL) {
1393 // Fold "(X == true)" to X and "(X == false)" to !X to
1394 // handle common cases produced by branch lowering.
1395 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1397 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1398 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1399 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1401 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1403 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1405 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1406 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1408 SDOperand CmpOp = getValue(CB.CmpMHS);
1409 MVT::ValueType VT = CmpOp.getValueType();
1411 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1412 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1414 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1415 Cond = DAG.getSetCC(MVT::i1, SUB,
1416 DAG.getConstant(High-Low, VT), ISD::SETULE);
1421 // Set NextBlock to be the MBB immediately after the current one, if any.
1422 // This is used to avoid emitting unnecessary branches to the next block.
1423 MachineBasicBlock *NextBlock = 0;
1424 MachineFunction::iterator BBI = CurMBB;
1425 if (++BBI != CurMBB->getParent()->end())
1428 // If the lhs block is the next block, invert the condition so that we can
1429 // fall through to the lhs instead of the rhs block.
1430 if (CB.TrueBB == NextBlock) {
1431 std::swap(CB.TrueBB, CB.FalseBB);
1432 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1433 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1435 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1436 DAG.getBasicBlock(CB.TrueBB));
1437 if (CB.FalseBB == NextBlock)
1438 DAG.setRoot(BrCond);
1440 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1441 DAG.getBasicBlock(CB.FalseBB)));
1442 // Update successor info
1443 CurMBB->addSuccessor(CB.TrueBB);
1444 CurMBB->addSuccessor(CB.FalseBB);
1447 /// visitJumpTable - Emit JumpTable node in the current MBB
1448 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1449 // Emit the code for the jump table
1450 assert(JT.Reg != -1U && "Should lower JT Header first!");
1451 MVT::ValueType PTy = TLI.getPointerTy();
1452 SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1453 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1454 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1459 /// visitJumpTableHeader - This function emits necessary code to produce index
1460 /// in the JumpTable from switch case.
1461 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1462 SelectionDAGISel::JumpTableHeader &JTH) {
1463 // Subtract the lowest switch case value from the value being switched on
1464 // and conditional branch to default mbb if the result is greater than the
1465 // difference between smallest and largest cases.
1466 SDOperand SwitchOp = getValue(JTH.SValue);
1467 MVT::ValueType VT = SwitchOp.getValueType();
1468 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1469 DAG.getConstant(JTH.First, VT));
1471 // The SDNode we just created, which holds the value being switched on
1472 // minus the the smallest case value, needs to be copied to a virtual
1473 // register so it can be used as an index into the jump table in a
1474 // subsequent basic block. This value may be smaller or larger than the
1475 // target's pointer type, and therefore require extension or truncating.
1476 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1477 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1479 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1481 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1482 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1483 JT.Reg = JumpTableReg;
1485 // Emit the range check for the jump table, and branch to the default
1486 // block for the switch statement if the value being switched on exceeds
1487 // the largest case in the switch.
1488 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1489 DAG.getConstant(JTH.Last-JTH.First,VT),
1492 // Set NextBlock to be the MBB immediately after the current one, if any.
1493 // This is used to avoid emitting unnecessary branches to the next block.
1494 MachineBasicBlock *NextBlock = 0;
1495 MachineFunction::iterator BBI = CurMBB;
1496 if (++BBI != CurMBB->getParent()->end())
1499 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1500 DAG.getBasicBlock(JT.Default));
1502 if (JT.MBB == NextBlock)
1503 DAG.setRoot(BrCond);
1505 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1506 DAG.getBasicBlock(JT.MBB)));
1511 /// visitBitTestHeader - This function emits necessary code to produce value
1512 /// suitable for "bit tests"
1513 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1514 // Subtract the minimum value
1515 SDOperand SwitchOp = getValue(B.SValue);
1516 MVT::ValueType VT = SwitchOp.getValueType();
1517 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1518 DAG.getConstant(B.First, VT));
1521 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1522 DAG.getConstant(B.Range, VT),
1526 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1527 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1529 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1531 // Make desired shift
1532 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1533 DAG.getConstant(1, TLI.getPointerTy()),
1536 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1537 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1540 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1541 DAG.getBasicBlock(B.Default));
1543 // Set NextBlock to be the MBB immediately after the current one, if any.
1544 // This is used to avoid emitting unnecessary branches to the next block.
1545 MachineBasicBlock *NextBlock = 0;
1546 MachineFunction::iterator BBI = CurMBB;
1547 if (++BBI != CurMBB->getParent()->end())
1550 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1551 if (MBB == NextBlock)
1552 DAG.setRoot(BrRange);
1554 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1555 DAG.getBasicBlock(MBB)));
1557 CurMBB->addSuccessor(B.Default);
1558 CurMBB->addSuccessor(MBB);
1563 /// visitBitTestCase - this function produces one "bit test"
1564 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1566 SelectionDAGISel::BitTestCase &B) {
1567 // Emit bit tests and jumps
1568 SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, TLI.getPointerTy());
1570 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1572 DAG.getConstant(B.Mask,
1573 TLI.getPointerTy()));
1574 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1575 DAG.getConstant(0, TLI.getPointerTy()),
1577 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1578 AndCmp, DAG.getBasicBlock(B.TargetBB));
1580 // Set NextBlock to be the MBB immediately after the current one, if any.
1581 // This is used to avoid emitting unnecessary branches to the next block.
1582 MachineBasicBlock *NextBlock = 0;
1583 MachineFunction::iterator BBI = CurMBB;
1584 if (++BBI != CurMBB->getParent()->end())
1587 if (NextMBB == NextBlock)
1590 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1591 DAG.getBasicBlock(NextMBB)));
1593 CurMBB->addSuccessor(B.TargetBB);
1594 CurMBB->addSuccessor(NextMBB);
1599 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1600 // Retrieve successors.
1601 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1602 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1604 if (isa<InlineAsm>(I.getCalledValue()))
1607 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1609 // If the value of the invoke is used outside of its defining block, make it
1610 // available as a virtual register.
1611 if (!I.use_empty()) {
1612 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1613 if (VMI != FuncInfo.ValueMap.end())
1614 CopyValueToVirtualRegister(&I, VMI->second);
1617 // Drop into normal successor.
1618 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1619 DAG.getBasicBlock(Return)));
1621 // Update successor info
1622 CurMBB->addSuccessor(Return);
1623 CurMBB->addSuccessor(LandingPad);
1626 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1629 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1630 /// small case ranges).
1631 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1632 CaseRecVector& WorkList,
1634 MachineBasicBlock* Default) {
1635 Case& BackCase = *(CR.Range.second-1);
1637 // Size is the number of Cases represented by this range.
1638 unsigned Size = CR.Range.second - CR.Range.first;
1642 // Get the MachineFunction which holds the current MBB. This is used when
1643 // inserting any additional MBBs necessary to represent the switch.
1644 MachineFunction *CurMF = CurMBB->getParent();
1646 // Figure out which block is immediately after the current one.
1647 MachineBasicBlock *NextBlock = 0;
1648 MachineFunction::iterator BBI = CR.CaseBB;
1650 if (++BBI != CurMBB->getParent()->end())
1653 // TODO: If any two of the cases has the same destination, and if one value
1654 // is the same as the other, but has one bit unset that the other has set,
1655 // use bit manipulation to do two compares at once. For example:
1656 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1658 // Rearrange the case blocks so that the last one falls through if possible.
1659 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1660 // The last case block won't fall through into 'NextBlock' if we emit the
1661 // branches in this order. See if rearranging a case value would help.
1662 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1663 if (I->BB == NextBlock) {
1664 std::swap(*I, BackCase);
1670 // Create a CaseBlock record representing a conditional branch to
1671 // the Case's target mbb if the value being switched on SV is equal
1673 MachineBasicBlock *CurBlock = CR.CaseBB;
1674 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1675 MachineBasicBlock *FallThrough;
1677 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1678 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1680 // If the last case doesn't match, go to the default block.
1681 FallThrough = Default;
1684 Value *RHS, *LHS, *MHS;
1686 if (I->High == I->Low) {
1687 // This is just small small case range :) containing exactly 1 case
1689 LHS = SV; RHS = I->High; MHS = NULL;
1692 LHS = I->Low; MHS = SV; RHS = I->High;
1694 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1695 I->BB, FallThrough, CurBlock);
1697 // If emitting the first comparison, just call visitSwitchCase to emit the
1698 // code into the current block. Otherwise, push the CaseBlock onto the
1699 // vector to be later processed by SDISel, and insert the node's MBB
1700 // before the next MBB.
1701 if (CurBlock == CurMBB)
1702 visitSwitchCase(CB);
1704 SwitchCases.push_back(CB);
1706 CurBlock = FallThrough;
1712 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1713 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1714 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1717 /// handleJTSwitchCase - Emit jumptable for current switch case range
1718 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1719 CaseRecVector& WorkList,
1721 MachineBasicBlock* Default) {
1722 Case& FrontCase = *CR.Range.first;
1723 Case& BackCase = *(CR.Range.second-1);
1725 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1726 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1729 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1733 if (!areJTsAllowed(TLI) || TSize <= 3)
1736 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1740 DOUT << "Lowering jump table\n"
1741 << "First entry: " << First << ". Last entry: " << Last << "\n"
1742 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1744 // Get the MachineFunction which holds the current MBB. This is used when
1745 // inserting any additional MBBs necessary to represent the switch.
1746 MachineFunction *CurMF = CurMBB->getParent();
1748 // Figure out which block is immediately after the current one.
1749 MachineBasicBlock *NextBlock = 0;
1750 MachineFunction::iterator BBI = CR.CaseBB;
1752 if (++BBI != CurMBB->getParent()->end())
1755 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1757 // Create a new basic block to hold the code for loading the address
1758 // of the jump table, and jumping to it. Update successor information;
1759 // we will either branch to the default case for the switch, or the jump
1761 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1762 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1763 CR.CaseBB->addSuccessor(Default);
1764 CR.CaseBB->addSuccessor(JumpTableBB);
1766 // Build a vector of destination BBs, corresponding to each target
1767 // of the jump table. If the value of the jump table slot corresponds to
1768 // a case statement, push the case's BB onto the vector, otherwise, push
1770 std::vector<MachineBasicBlock*> DestBBs;
1771 int64_t TEI = First;
1772 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1773 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1774 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1776 if ((Low <= TEI) && (TEI <= High)) {
1777 DestBBs.push_back(I->BB);
1781 DestBBs.push_back(Default);
1785 // Update successor info. Add one edge to each unique successor.
1786 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1787 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1788 E = DestBBs.end(); I != E; ++I) {
1789 if (!SuccsHandled[(*I)->getNumber()]) {
1790 SuccsHandled[(*I)->getNumber()] = true;
1791 JumpTableBB->addSuccessor(*I);
1795 // Create a jump table index for this jump table, or return an existing
1797 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1799 // Set the jump table information so that we can codegen it as a second
1800 // MachineBasicBlock
1801 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1802 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1803 (CR.CaseBB == CurMBB));
1804 if (CR.CaseBB == CurMBB)
1805 visitJumpTableHeader(JT, JTH);
1807 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1812 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1814 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1815 CaseRecVector& WorkList,
1817 MachineBasicBlock* Default) {
1818 // Get the MachineFunction which holds the current MBB. This is used when
1819 // inserting any additional MBBs necessary to represent the switch.
1820 MachineFunction *CurMF = CurMBB->getParent();
1822 // Figure out which block is immediately after the current one.
1823 MachineBasicBlock *NextBlock = 0;
1824 MachineFunction::iterator BBI = CR.CaseBB;
1826 if (++BBI != CurMBB->getParent()->end())
1829 Case& FrontCase = *CR.Range.first;
1830 Case& BackCase = *(CR.Range.second-1);
1831 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1833 // Size is the number of Cases represented by this range.
1834 unsigned Size = CR.Range.second - CR.Range.first;
1836 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1837 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1839 CaseItr Pivot = CR.Range.first + Size/2;
1841 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1842 // (heuristically) allow us to emit JumpTable's later.
1844 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1848 uint64_t LSize = FrontCase.size();
1849 uint64_t RSize = TSize-LSize;
1850 DOUT << "Selecting best pivot: \n"
1851 << "First: " << First << ", Last: " << Last <<"\n"
1852 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1853 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1855 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1856 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1857 assert((RBegin-LEnd>=1) && "Invalid case distance");
1858 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1859 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1860 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1861 // Should always split in some non-trivial place
1863 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1864 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1865 << "Metric: " << Metric << "\n";
1866 if (FMetric < Metric) {
1869 DOUT << "Current metric set to: " << FMetric << "\n";
1875 if (areJTsAllowed(TLI)) {
1876 // If our case is dense we *really* should handle it earlier!
1877 assert((FMetric > 0) && "Should handle dense range earlier!");
1879 Pivot = CR.Range.first + Size/2;
1882 CaseRange LHSR(CR.Range.first, Pivot);
1883 CaseRange RHSR(Pivot, CR.Range.second);
1884 Constant *C = Pivot->Low;
1885 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1887 // We know that we branch to the LHS if the Value being switched on is
1888 // less than the Pivot value, C. We use this to optimize our binary
1889 // tree a bit, by recognizing that if SV is greater than or equal to the
1890 // LHS's Case Value, and that Case Value is exactly one less than the
1891 // Pivot's Value, then we can branch directly to the LHS's Target,
1892 // rather than creating a leaf node for it.
1893 if ((LHSR.second - LHSR.first) == 1 &&
1894 LHSR.first->High == CR.GE &&
1895 cast<ConstantInt>(C)->getSExtValue() ==
1896 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1897 TrueBB = LHSR.first->BB;
1899 TrueBB = new MachineBasicBlock(LLVMBB);
1900 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1901 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1904 // Similar to the optimization above, if the Value being switched on is
1905 // known to be less than the Constant CR.LT, and the current Case Value
1906 // is CR.LT - 1, then we can branch directly to the target block for
1907 // the current Case Value, rather than emitting a RHS leaf node for it.
1908 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1909 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1910 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1911 FalseBB = RHSR.first->BB;
1913 FalseBB = new MachineBasicBlock(LLVMBB);
1914 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1915 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1918 // Create a CaseBlock record representing a conditional branch to
1919 // the LHS node if the value being switched on SV is less than C.
1920 // Otherwise, branch to LHS.
1921 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1922 TrueBB, FalseBB, CR.CaseBB);
1924 if (CR.CaseBB == CurMBB)
1925 visitSwitchCase(CB);
1927 SwitchCases.push_back(CB);
1932 /// handleBitTestsSwitchCase - if current case range has few destination and
1933 /// range span less, than machine word bitwidth, encode case range into series
1934 /// of masks and emit bit tests with these masks.
1935 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1936 CaseRecVector& WorkList,
1938 MachineBasicBlock* Default){
1939 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1941 Case& FrontCase = *CR.Range.first;
1942 Case& BackCase = *(CR.Range.second-1);
1944 // Get the MachineFunction which holds the current MBB. This is used when
1945 // inserting any additional MBBs necessary to represent the switch.
1946 MachineFunction *CurMF = CurMBB->getParent();
1948 unsigned numCmps = 0;
1949 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1951 // Single case counts one, case range - two.
1952 if (I->Low == I->High)
1958 // Count unique destinations
1959 SmallSet<MachineBasicBlock*, 4> Dests;
1960 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1961 Dests.insert(I->BB);
1962 if (Dests.size() > 3)
1963 // Don't bother the code below, if there are too much unique destinations
1966 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1967 << "Total number of comparisons: " << numCmps << "\n";
1969 // Compute span of values.
1970 Constant* minValue = FrontCase.Low;
1971 Constant* maxValue = BackCase.High;
1972 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1973 cast<ConstantInt>(minValue)->getSExtValue();
1974 DOUT << "Compare range: " << range << "\n"
1975 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1976 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1978 if (range>=IntPtrBits ||
1979 (!(Dests.size() == 1 && numCmps >= 3) &&
1980 !(Dests.size() == 2 && numCmps >= 5) &&
1981 !(Dests.size() >= 3 && numCmps >= 6)))
1984 DOUT << "Emitting bit tests\n";
1985 int64_t lowBound = 0;
1987 // Optimize the case where all the case values fit in a
1988 // word without having to subtract minValue. In this case,
1989 // we can optimize away the subtraction.
1990 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1991 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1992 range = cast<ConstantInt>(maxValue)->getSExtValue();
1994 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1997 CaseBitsVector CasesBits;
1998 unsigned i, count = 0;
2000 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2001 MachineBasicBlock* Dest = I->BB;
2002 for (i = 0; i < count; ++i)
2003 if (Dest == CasesBits[i].BB)
2007 assert((count < 3) && "Too much destinations to test!");
2008 CasesBits.push_back(CaseBits(0, Dest, 0));
2012 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2013 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2015 for (uint64_t j = lo; j <= hi; j++) {
2016 CasesBits[i].Mask |= 1ULL << j;
2017 CasesBits[i].Bits++;
2021 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2023 SelectionDAGISel::BitTestInfo BTC;
2025 // Figure out which block is immediately after the current one.
2026 MachineFunction::iterator BBI = CR.CaseBB;
2029 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2032 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2033 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2034 << ", BB: " << CasesBits[i].BB << "\n";
2036 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
2037 CurMF->getBasicBlockList().insert(BBI, CaseBB);
2038 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2043 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2044 -1U, (CR.CaseBB == CurMBB),
2045 CR.CaseBB, Default, BTC);
2047 if (CR.CaseBB == CurMBB)
2048 visitBitTestHeader(BTB);
2050 BitTestCases.push_back(BTB);
2056 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2057 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2058 const SwitchInst& SI) {
2059 unsigned numCmps = 0;
2061 // Start with "simple" cases
2062 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2063 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2064 Cases.push_back(Case(SI.getSuccessorValue(i),
2065 SI.getSuccessorValue(i),
2068 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2070 // Merge case into clusters
2071 if (Cases.size()>=2)
2072 // Must recompute end() each iteration because it may be
2073 // invalidated by erase if we hold on to it
2074 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2075 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2076 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2077 MachineBasicBlock* nextBB = J->BB;
2078 MachineBasicBlock* currentBB = I->BB;
2080 // If the two neighboring cases go to the same destination, merge them
2081 // into a single case.
2082 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2090 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2091 if (I->Low != I->High)
2092 // A range counts double, since it requires two compares.
2099 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2100 // Figure out which block is immediately after the current one.
2101 MachineBasicBlock *NextBlock = 0;
2102 MachineFunction::iterator BBI = CurMBB;
2104 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2106 // If there is only the default destination, branch to it if it is not the
2107 // next basic block. Otherwise, just fall through.
2108 if (SI.getNumOperands() == 2) {
2109 // Update machine-CFG edges.
2111 // If this is not a fall-through branch, emit the branch.
2112 if (Default != NextBlock)
2113 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2114 DAG.getBasicBlock(Default)));
2116 CurMBB->addSuccessor(Default);
2120 // If there are any non-default case statements, create a vector of Cases
2121 // representing each one, and sort the vector so that we can efficiently
2122 // create a binary search tree from them.
2124 unsigned numCmps = Clusterify(Cases, SI);
2125 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2126 << ". Total compares: " << numCmps << "\n";
2128 // Get the Value to be switched on and default basic blocks, which will be
2129 // inserted into CaseBlock records, representing basic blocks in the binary
2131 Value *SV = SI.getOperand(0);
2133 // Push the initial CaseRec onto the worklist
2134 CaseRecVector WorkList;
2135 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2137 while (!WorkList.empty()) {
2138 // Grab a record representing a case range to process off the worklist
2139 CaseRec CR = WorkList.back();
2140 WorkList.pop_back();
2142 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2145 // If the range has few cases (two or less) emit a series of specific
2147 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2150 // If the switch has more than 5 blocks, and at least 40% dense, and the
2151 // target supports indirect branches, then emit a jump table rather than
2152 // lowering the switch to a binary tree of conditional branches.
2153 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2156 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2157 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2158 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2163 void SelectionDAGLowering::visitSub(User &I) {
2164 // -0.0 - X --> fneg
2165 const Type *Ty = I.getType();
2166 if (isa<VectorType>(Ty)) {
2167 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2168 const VectorType *DestTy = cast<VectorType>(I.getType());
2169 const Type *ElTy = DestTy->getElementType();
2170 if (ElTy->isFloatingPoint()) {
2171 unsigned VL = DestTy->getNumElements();
2172 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2173 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2175 SDOperand Op2 = getValue(I.getOperand(1));
2176 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2182 if (Ty->isFloatingPoint()) {
2183 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2184 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2185 SDOperand Op2 = getValue(I.getOperand(1));
2186 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2191 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2194 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2195 SDOperand Op1 = getValue(I.getOperand(0));
2196 SDOperand Op2 = getValue(I.getOperand(1));
2198 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2201 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2202 SDOperand Op1 = getValue(I.getOperand(0));
2203 SDOperand Op2 = getValue(I.getOperand(1));
2205 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2206 MVT::getSizeInBits(Op2.getValueType()))
2207 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2208 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2209 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2211 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2214 void SelectionDAGLowering::visitICmp(User &I) {
2215 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2216 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2217 predicate = IC->getPredicate();
2218 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2219 predicate = ICmpInst::Predicate(IC->getPredicate());
2220 SDOperand Op1 = getValue(I.getOperand(0));
2221 SDOperand Op2 = getValue(I.getOperand(1));
2222 ISD::CondCode Opcode;
2223 switch (predicate) {
2224 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2225 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2226 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2227 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2228 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2229 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2230 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2231 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2232 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2233 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2235 assert(!"Invalid ICmp predicate value");
2236 Opcode = ISD::SETEQ;
2239 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2242 void SelectionDAGLowering::visitFCmp(User &I) {
2243 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2244 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2245 predicate = FC->getPredicate();
2246 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2247 predicate = FCmpInst::Predicate(FC->getPredicate());
2248 SDOperand Op1 = getValue(I.getOperand(0));
2249 SDOperand Op2 = getValue(I.getOperand(1));
2250 ISD::CondCode Condition, FOC, FPC;
2251 switch (predicate) {
2252 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2253 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2254 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2255 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2256 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2257 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2258 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2259 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2260 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2261 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2262 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2263 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2264 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2265 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2266 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2267 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2269 assert(!"Invalid FCmp predicate value");
2270 FOC = FPC = ISD::SETFALSE;
2273 if (FiniteOnlyFPMath())
2277 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2280 void SelectionDAGLowering::visitSelect(User &I) {
2281 SDOperand Cond = getValue(I.getOperand(0));
2282 SDOperand TrueVal = getValue(I.getOperand(1));
2283 SDOperand FalseVal = getValue(I.getOperand(2));
2284 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2285 TrueVal, FalseVal));
2289 void SelectionDAGLowering::visitTrunc(User &I) {
2290 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2291 SDOperand N = getValue(I.getOperand(0));
2292 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2293 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2296 void SelectionDAGLowering::visitZExt(User &I) {
2297 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2298 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2299 SDOperand N = getValue(I.getOperand(0));
2300 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2301 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2304 void SelectionDAGLowering::visitSExt(User &I) {
2305 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2306 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2307 SDOperand N = getValue(I.getOperand(0));
2308 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2309 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2312 void SelectionDAGLowering::visitFPTrunc(User &I) {
2313 // FPTrunc is never a no-op cast, no need to check
2314 SDOperand N = getValue(I.getOperand(0));
2315 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2316 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2319 void SelectionDAGLowering::visitFPExt(User &I){
2320 // FPTrunc is never a no-op cast, no need to check
2321 SDOperand N = getValue(I.getOperand(0));
2322 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2323 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2326 void SelectionDAGLowering::visitFPToUI(User &I) {
2327 // FPToUI is never a no-op cast, no need to check
2328 SDOperand N = getValue(I.getOperand(0));
2329 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2330 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2333 void SelectionDAGLowering::visitFPToSI(User &I) {
2334 // FPToSI is never a no-op cast, no need to check
2335 SDOperand N = getValue(I.getOperand(0));
2336 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2337 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2340 void SelectionDAGLowering::visitUIToFP(User &I) {
2341 // UIToFP is never a no-op cast, no need to check
2342 SDOperand N = getValue(I.getOperand(0));
2343 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2344 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2347 void SelectionDAGLowering::visitSIToFP(User &I){
2348 // UIToFP is never a no-op cast, no need to check
2349 SDOperand N = getValue(I.getOperand(0));
2350 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2351 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2354 void SelectionDAGLowering::visitPtrToInt(User &I) {
2355 // What to do depends on the size of the integer and the size of the pointer.
2356 // We can either truncate, zero extend, or no-op, accordingly.
2357 SDOperand N = getValue(I.getOperand(0));
2358 MVT::ValueType SrcVT = N.getValueType();
2359 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2361 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2362 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2364 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2365 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2366 setValue(&I, Result);
2369 void SelectionDAGLowering::visitIntToPtr(User &I) {
2370 // What to do depends on the size of the integer and the size of the pointer.
2371 // We can either truncate, zero extend, or no-op, accordingly.
2372 SDOperand N = getValue(I.getOperand(0));
2373 MVT::ValueType SrcVT = N.getValueType();
2374 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2375 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2376 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2378 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2379 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2382 void SelectionDAGLowering::visitBitCast(User &I) {
2383 SDOperand N = getValue(I.getOperand(0));
2384 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2386 // BitCast assures us that source and destination are the same size so this
2387 // is either a BIT_CONVERT or a no-op.
2388 if (DestVT != N.getValueType())
2389 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2391 setValue(&I, N); // noop cast.
2394 void SelectionDAGLowering::visitInsertElement(User &I) {
2395 SDOperand InVec = getValue(I.getOperand(0));
2396 SDOperand InVal = getValue(I.getOperand(1));
2397 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2398 getValue(I.getOperand(2)));
2400 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2401 TLI.getValueType(I.getType()),
2402 InVec, InVal, InIdx));
2405 void SelectionDAGLowering::visitExtractElement(User &I) {
2406 SDOperand InVec = getValue(I.getOperand(0));
2407 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2408 getValue(I.getOperand(1)));
2409 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2410 TLI.getValueType(I.getType()), InVec, InIdx));
2413 void SelectionDAGLowering::visitShuffleVector(User &I) {
2414 SDOperand V1 = getValue(I.getOperand(0));
2415 SDOperand V2 = getValue(I.getOperand(1));
2416 SDOperand Mask = getValue(I.getOperand(2));
2418 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2419 TLI.getValueType(I.getType()),
2424 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2425 SDOperand N = getValue(I.getOperand(0));
2426 const Type *Ty = I.getOperand(0)->getType();
2428 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2431 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2432 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2435 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2436 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2437 DAG.getIntPtrConstant(Offset));
2439 Ty = StTy->getElementType(Field);
2441 Ty = cast<SequentialType>(Ty)->getElementType();
2443 // If this is a constant subscript, handle it quickly.
2444 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2445 if (CI->getZExtValue() == 0) continue;
2447 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2448 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2449 DAG.getIntPtrConstant(Offs));
2453 // N = N + Idx * ElementSize;
2454 uint64_t ElementSize = TD->getABITypeSize(Ty);
2455 SDOperand IdxN = getValue(Idx);
2457 // If the index is smaller or larger than intptr_t, truncate or extend
2459 if (IdxN.getValueType() < N.getValueType()) {
2460 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2461 } else if (IdxN.getValueType() > N.getValueType())
2462 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2464 // If this is a multiply by a power of two, turn it into a shl
2465 // immediately. This is a very common case.
2466 if (isPowerOf2_64(ElementSize)) {
2467 unsigned Amt = Log2_64(ElementSize);
2468 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2469 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2470 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2474 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2475 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2476 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2482 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2483 // If this is a fixed sized alloca in the entry block of the function,
2484 // allocate it statically on the stack.
2485 if (FuncInfo.StaticAllocaMap.count(&I))
2486 return; // getValue will auto-populate this.
2488 const Type *Ty = I.getAllocatedType();
2489 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2491 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2494 SDOperand AllocSize = getValue(I.getArraySize());
2495 MVT::ValueType IntPtr = TLI.getPointerTy();
2496 if (IntPtr < AllocSize.getValueType())
2497 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2498 else if (IntPtr > AllocSize.getValueType())
2499 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2501 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2502 DAG.getIntPtrConstant(TySize));
2504 // Handle alignment. If the requested alignment is less than or equal to
2505 // the stack alignment, ignore it. If the size is greater than or equal to
2506 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2507 unsigned StackAlign =
2508 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2509 if (Align <= StackAlign)
2512 // Round the size of the allocation up to the stack alignment size
2513 // by add SA-1 to the size.
2514 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2515 DAG.getIntPtrConstant(StackAlign-1));
2516 // Mask out the low bits for alignment purposes.
2517 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2518 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2520 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2521 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2523 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2525 DAG.setRoot(DSA.getValue(1));
2527 // Inform the Frame Information that we have just allocated a variable-sized
2529 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2532 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2533 SDOperand Ptr = getValue(I.getOperand(0));
2539 // Do not serialize non-volatile loads against each other.
2540 Root = DAG.getRoot();
2543 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2544 Root, I.isVolatile(), I.getAlignment()));
2547 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2548 const Value *SV, SDOperand Root,
2550 unsigned Alignment) {
2552 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2553 isVolatile, Alignment);
2556 DAG.setRoot(L.getValue(1));
2558 PendingLoads.push_back(L.getValue(1));
2564 void SelectionDAGLowering::visitStore(StoreInst &I) {
2565 Value *SrcV = I.getOperand(0);
2566 SDOperand Src = getValue(SrcV);
2567 SDOperand Ptr = getValue(I.getOperand(1));
2568 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2569 I.isVolatile(), I.getAlignment()));
2572 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2574 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2575 unsigned Intrinsic) {
2576 bool HasChain = !I.doesNotAccessMemory();
2577 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2579 // Build the operand list.
2580 SmallVector<SDOperand, 8> Ops;
2581 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2583 // We don't need to serialize loads against other loads.
2584 Ops.push_back(DAG.getRoot());
2586 Ops.push_back(getRoot());
2590 // Add the intrinsic ID as an integer operand.
2591 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2593 // Add all operands of the call to the operand list.
2594 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2595 SDOperand Op = getValue(I.getOperand(i));
2596 assert(TLI.isTypeLegal(Op.getValueType()) &&
2597 "Intrinsic uses a non-legal type?");
2601 std::vector<MVT::ValueType> VTs;
2602 if (I.getType() != Type::VoidTy) {
2603 MVT::ValueType VT = TLI.getValueType(I.getType());
2604 if (MVT::isVector(VT)) {
2605 const VectorType *DestTy = cast<VectorType>(I.getType());
2606 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2608 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2609 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2612 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2616 VTs.push_back(MVT::Other);
2618 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2623 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2624 &Ops[0], Ops.size());
2625 else if (I.getType() != Type::VoidTy)
2626 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2627 &Ops[0], Ops.size());
2629 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2630 &Ops[0], Ops.size());
2633 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2635 PendingLoads.push_back(Chain);
2639 if (I.getType() != Type::VoidTy) {
2640 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2641 MVT::ValueType VT = TLI.getValueType(PTy);
2642 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2644 setValue(&I, Result);
2648 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2649 static GlobalVariable *ExtractTypeInfo (Value *V) {
2650 V = IntrinsicInst::StripPointerCasts(V);
2651 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2652 assert ((GV || isa<ConstantPointerNull>(V)) &&
2653 "TypeInfo must be a global variable or NULL");
2657 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2658 /// call, and add them to the specified machine basic block.
2659 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2660 MachineBasicBlock *MBB) {
2661 // Inform the MachineModuleInfo of the personality for this landing pad.
2662 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2663 assert(CE->getOpcode() == Instruction::BitCast &&
2664 isa<Function>(CE->getOperand(0)) &&
2665 "Personality should be a function");
2666 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2668 // Gather all the type infos for this landing pad and pass them along to
2669 // MachineModuleInfo.
2670 std::vector<GlobalVariable *> TyInfo;
2671 unsigned N = I.getNumOperands();
2673 for (unsigned i = N - 1; i > 2; --i) {
2674 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2675 unsigned FilterLength = CI->getZExtValue();
2676 unsigned FirstCatch = i + FilterLength + !FilterLength;
2677 assert (FirstCatch <= N && "Invalid filter length");
2679 if (FirstCatch < N) {
2680 TyInfo.reserve(N - FirstCatch);
2681 for (unsigned j = FirstCatch; j < N; ++j)
2682 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2683 MMI->addCatchTypeInfo(MBB, TyInfo);
2687 if (!FilterLength) {
2689 MMI->addCleanup(MBB);
2692 TyInfo.reserve(FilterLength - 1);
2693 for (unsigned j = i + 1; j < FirstCatch; ++j)
2694 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2695 MMI->addFilterTypeInfo(MBB, TyInfo);
2704 TyInfo.reserve(N - 3);
2705 for (unsigned j = 3; j < N; ++j)
2706 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2707 MMI->addCatchTypeInfo(MBB, TyInfo);
2711 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2712 /// we want to emit this as a call to a named external function, return the name
2713 /// otherwise lower it and return null.
2715 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2716 switch (Intrinsic) {
2718 // By default, turn this into a target intrinsic node.
2719 visitTargetIntrinsic(I, Intrinsic);
2721 case Intrinsic::vastart: visitVAStart(I); return 0;
2722 case Intrinsic::vaend: visitVAEnd(I); return 0;
2723 case Intrinsic::vacopy: visitVACopy(I); return 0;
2724 case Intrinsic::returnaddress:
2725 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2726 getValue(I.getOperand(1))));
2728 case Intrinsic::frameaddress:
2729 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2730 getValue(I.getOperand(1))));
2732 case Intrinsic::setjmp:
2733 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2735 case Intrinsic::longjmp:
2736 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2738 case Intrinsic::memcpy_i32:
2739 case Intrinsic::memcpy_i64:
2740 visitMemIntrinsic(I, ISD::MEMCPY);
2742 case Intrinsic::memset_i32:
2743 case Intrinsic::memset_i64:
2744 visitMemIntrinsic(I, ISD::MEMSET);
2746 case Intrinsic::memmove_i32:
2747 case Intrinsic::memmove_i64:
2748 visitMemIntrinsic(I, ISD::MEMMOVE);
2751 case Intrinsic::dbg_stoppoint: {
2752 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2753 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2754 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2758 Ops[1] = getValue(SPI.getLineValue());
2759 Ops[2] = getValue(SPI.getColumnValue());
2761 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2762 assert(DD && "Not a debug information descriptor");
2763 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2765 Ops[3] = DAG.getString(CompileUnit->getFileName());
2766 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2768 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2773 case Intrinsic::dbg_region_start: {
2774 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2775 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2776 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2777 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2778 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2779 DAG.getConstant(LabelID, MVT::i32),
2780 DAG.getConstant(0, MVT::i32)));
2785 case Intrinsic::dbg_region_end: {
2786 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2787 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2788 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2789 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2790 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2791 DAG.getConstant(LabelID, MVT::i32),
2792 DAG.getConstant(0, MVT::i32)));
2797 case Intrinsic::dbg_func_start: {
2798 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2800 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2801 Value *SP = FSI.getSubprogram();
2802 if (SP && MMI->Verify(SP)) {
2803 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
2804 // what (most?) gdb expects.
2805 DebugInfoDesc *DD = MMI->getDescFor(SP);
2806 assert(DD && "Not a debug information descriptor");
2807 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
2808 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
2809 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
2810 CompileUnit->getFileName());
2811 // Record the source line but does create a label. It will be emitted
2812 // at asm emission time.
2813 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
2818 case Intrinsic::dbg_declare: {
2819 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2820 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2821 Value *Variable = DI.getVariable();
2822 if (MMI && Variable && MMI->Verify(Variable))
2823 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
2824 getValue(DI.getAddress()), getValue(Variable)));
2828 case Intrinsic::eh_exception: {
2829 if (ExceptionHandling) {
2830 if (!CurMBB->isLandingPad()) {
2831 // FIXME: Mark exception register as live in. Hack for PR1508.
2832 unsigned Reg = TLI.getExceptionAddressRegister();
2833 if (Reg) CurMBB->addLiveIn(Reg);
2835 // Insert the EXCEPTIONADDR instruction.
2836 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2838 Ops[0] = DAG.getRoot();
2839 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2841 DAG.setRoot(Op.getValue(1));
2843 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2848 case Intrinsic::eh_selector_i32:
2849 case Intrinsic::eh_selector_i64: {
2850 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2851 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2852 MVT::i32 : MVT::i64);
2854 if (ExceptionHandling && MMI) {
2855 if (CurMBB->isLandingPad())
2856 addCatchInfo(I, MMI, CurMBB);
2859 FuncInfo.CatchInfoLost.insert(&I);
2861 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2862 unsigned Reg = TLI.getExceptionSelectorRegister();
2863 if (Reg) CurMBB->addLiveIn(Reg);
2866 // Insert the EHSELECTION instruction.
2867 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2869 Ops[0] = getValue(I.getOperand(1));
2871 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2873 DAG.setRoot(Op.getValue(1));
2875 setValue(&I, DAG.getConstant(0, VT));
2881 case Intrinsic::eh_typeid_for_i32:
2882 case Intrinsic::eh_typeid_for_i64: {
2883 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2884 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2885 MVT::i32 : MVT::i64);
2888 // Find the type id for the given typeinfo.
2889 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2891 unsigned TypeID = MMI->getTypeIDFor(GV);
2892 setValue(&I, DAG.getConstant(TypeID, VT));
2894 // Return something different to eh_selector.
2895 setValue(&I, DAG.getConstant(1, VT));
2901 case Intrinsic::eh_return: {
2902 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2904 if (MMI && ExceptionHandling) {
2905 MMI->setCallsEHReturn(true);
2906 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2909 getValue(I.getOperand(1)),
2910 getValue(I.getOperand(2))));
2912 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2918 case Intrinsic::eh_unwind_init: {
2919 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2920 MMI->setCallsUnwindInit(true);
2926 case Intrinsic::eh_dwarf_cfa: {
2927 if (ExceptionHandling) {
2928 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2930 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2931 CfaArg = DAG.getNode(ISD::TRUNCATE,
2932 TLI.getPointerTy(), getValue(I.getOperand(1)));
2934 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2935 TLI.getPointerTy(), getValue(I.getOperand(1)));
2937 SDOperand Offset = DAG.getNode(ISD::ADD,
2939 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2940 TLI.getPointerTy()),
2942 setValue(&I, DAG.getNode(ISD::ADD,
2944 DAG.getNode(ISD::FRAMEADDR,
2947 TLI.getPointerTy())),
2950 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2956 case Intrinsic::sqrt:
2957 setValue(&I, DAG.getNode(ISD::FSQRT,
2958 getValue(I.getOperand(1)).getValueType(),
2959 getValue(I.getOperand(1))));
2961 case Intrinsic::powi:
2962 setValue(&I, DAG.getNode(ISD::FPOWI,
2963 getValue(I.getOperand(1)).getValueType(),
2964 getValue(I.getOperand(1)),
2965 getValue(I.getOperand(2))));
2967 case Intrinsic::sin:
2968 setValue(&I, DAG.getNode(ISD::FSIN,
2969 getValue(I.getOperand(1)).getValueType(),
2970 getValue(I.getOperand(1))));
2972 case Intrinsic::cos:
2973 setValue(&I, DAG.getNode(ISD::FCOS,
2974 getValue(I.getOperand(1)).getValueType(),
2975 getValue(I.getOperand(1))));
2977 case Intrinsic::pow:
2978 setValue(&I, DAG.getNode(ISD::FPOW,
2979 getValue(I.getOperand(1)).getValueType(),
2980 getValue(I.getOperand(1)),
2981 getValue(I.getOperand(2))));
2983 case Intrinsic::pcmarker: {
2984 SDOperand Tmp = getValue(I.getOperand(1));
2985 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2988 case Intrinsic::readcyclecounter: {
2989 SDOperand Op = getRoot();
2990 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2991 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2994 DAG.setRoot(Tmp.getValue(1));
2997 case Intrinsic::part_select: {
2998 // Currently not implemented: just abort
2999 assert(0 && "part_select intrinsic not implemented");
3002 case Intrinsic::part_set: {
3003 // Currently not implemented: just abort
3004 assert(0 && "part_set intrinsic not implemented");
3007 case Intrinsic::bswap:
3008 setValue(&I, DAG.getNode(ISD::BSWAP,
3009 getValue(I.getOperand(1)).getValueType(),
3010 getValue(I.getOperand(1))));
3012 case Intrinsic::cttz: {
3013 SDOperand Arg = getValue(I.getOperand(1));
3014 MVT::ValueType Ty = Arg.getValueType();
3015 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3016 setValue(&I, result);
3019 case Intrinsic::ctlz: {
3020 SDOperand Arg = getValue(I.getOperand(1));
3021 MVT::ValueType Ty = Arg.getValueType();
3022 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3023 setValue(&I, result);
3026 case Intrinsic::ctpop: {
3027 SDOperand Arg = getValue(I.getOperand(1));
3028 MVT::ValueType Ty = Arg.getValueType();
3029 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3030 setValue(&I, result);
3033 case Intrinsic::stacksave: {
3034 SDOperand Op = getRoot();
3035 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
3036 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3038 DAG.setRoot(Tmp.getValue(1));
3041 case Intrinsic::stackrestore: {
3042 SDOperand Tmp = getValue(I.getOperand(1));
3043 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3046 case Intrinsic::var_annotation:
3047 // Discard annotate attributes
3050 case Intrinsic::init_trampoline: {
3052 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
3056 Ops[1] = getValue(I.getOperand(1));
3057 Ops[2] = getValue(I.getOperand(2));
3058 Ops[3] = getValue(I.getOperand(3));
3059 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3060 Ops[5] = DAG.getSrcValue(F);
3062 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3063 DAG.getNodeValueTypes(TLI.getPointerTy(),
3068 DAG.setRoot(Tmp.getValue(1));
3072 case Intrinsic::gcroot:
3074 Value *Alloca = I.getOperand(1);
3075 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3077 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3078 GCI->addStackRoot(FI->getIndex(), TypeMap);
3082 case Intrinsic::gcread:
3083 case Intrinsic::gcwrite:
3084 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3087 case Intrinsic::flt_rounds: {
3088 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3092 case Intrinsic::trap: {
3093 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3096 case Intrinsic::prefetch: {
3099 Ops[1] = getValue(I.getOperand(1));
3100 Ops[2] = getValue(I.getOperand(2));
3101 Ops[3] = getValue(I.getOperand(3));
3102 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3106 case Intrinsic::memory_barrier: {
3109 for (int x = 1; x < 6; ++x)
3110 Ops[x] = getValue(I.getOperand(x));
3112 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3115 case Intrinsic::atomic_lcs: {
3116 SDOperand Root = getRoot();
3117 SDOperand O3 = getValue(I.getOperand(3));
3118 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root,
3119 getValue(I.getOperand(1)),
3120 getValue(I.getOperand(2)),
3121 O3, O3.getValueType());
3123 DAG.setRoot(L.getValue(1));
3126 case Intrinsic::atomic_las: {
3127 SDOperand Root = getRoot();
3128 SDOperand O2 = getValue(I.getOperand(2));
3129 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LAS, Root,
3130 getValue(I.getOperand(1)),
3131 O2, O2.getValueType());
3133 DAG.setRoot(L.getValue(1));
3136 case Intrinsic::atomic_swap: {
3137 SDOperand Root = getRoot();
3138 SDOperand O2 = getValue(I.getOperand(2));
3139 SDOperand L = DAG.getAtomic(ISD::ATOMIC_SWAP, Root,
3140 getValue(I.getOperand(1)),
3141 O2, O2.getValueType());
3143 DAG.setRoot(L.getValue(1));
3151 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3153 MachineBasicBlock *LandingPad) {
3154 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3155 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3156 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3157 unsigned BeginLabel = 0, EndLabel = 0;
3159 TargetLowering::ArgListTy Args;
3160 TargetLowering::ArgListEntry Entry;
3161 Args.reserve(CS.arg_size());
3162 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3164 SDOperand ArgNode = getValue(*i);
3165 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3167 unsigned attrInd = i - CS.arg_begin() + 1;
3168 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3169 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3170 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3171 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3172 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3173 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3174 Entry.Alignment = CS.getParamAlignment(attrInd);
3175 Args.push_back(Entry);
3178 if (LandingPad && ExceptionHandling && MMI) {
3179 // Insert a label before the invoke call to mark the try range. This can be
3180 // used to detect deletion of the invoke via the MachineModuleInfo.
3181 BeginLabel = MMI->NextLabelID();
3182 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3183 DAG.getConstant(BeginLabel, MVT::i32),
3184 DAG.getConstant(1, MVT::i32)));
3187 std::pair<SDOperand,SDOperand> Result =
3188 TLI.LowerCallTo(getRoot(), CS.getType(),
3189 CS.paramHasAttr(0, ParamAttr::SExt),
3190 CS.paramHasAttr(0, ParamAttr::ZExt),
3191 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3193 if (CS.getType() != Type::VoidTy)
3194 setValue(CS.getInstruction(), Result.first);
3195 DAG.setRoot(Result.second);
3197 if (LandingPad && ExceptionHandling && MMI) {
3198 // Insert a label at the end of the invoke call to mark the try range. This
3199 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3200 EndLabel = MMI->NextLabelID();
3201 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3202 DAG.getConstant(EndLabel, MVT::i32),
3203 DAG.getConstant(1, MVT::i32)));
3205 // Inform MachineModuleInfo of range.
3206 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3211 void SelectionDAGLowering::visitCall(CallInst &I) {
3212 const char *RenameFn = 0;
3213 if (Function *F = I.getCalledFunction()) {
3214 if (F->isDeclaration()) {
3215 if (unsigned IID = F->getIntrinsicID()) {
3216 RenameFn = visitIntrinsicCall(I, IID);
3222 // Check for well-known libc/libm calls. If the function is internal, it
3223 // can't be a library call.
3224 unsigned NameLen = F->getNameLen();
3225 if (!F->hasInternalLinkage() && NameLen) {
3226 const char *NameStr = F->getNameStart();
3227 if (NameStr[0] == 'c' &&
3228 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3229 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3230 if (I.getNumOperands() == 3 && // Basic sanity checks.
3231 I.getOperand(1)->getType()->isFloatingPoint() &&
3232 I.getType() == I.getOperand(1)->getType() &&
3233 I.getType() == I.getOperand(2)->getType()) {
3234 SDOperand LHS = getValue(I.getOperand(1));
3235 SDOperand RHS = getValue(I.getOperand(2));
3236 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3240 } else if (NameStr[0] == 'f' &&
3241 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3242 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3243 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3244 if (I.getNumOperands() == 2 && // Basic sanity checks.
3245 I.getOperand(1)->getType()->isFloatingPoint() &&
3246 I.getType() == I.getOperand(1)->getType()) {
3247 SDOperand Tmp = getValue(I.getOperand(1));
3248 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3251 } else if (NameStr[0] == 's' &&
3252 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3253 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3254 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3255 if (I.getNumOperands() == 2 && // Basic sanity checks.
3256 I.getOperand(1)->getType()->isFloatingPoint() &&
3257 I.getType() == I.getOperand(1)->getType()) {
3258 SDOperand Tmp = getValue(I.getOperand(1));
3259 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3262 } else if (NameStr[0] == 'c' &&
3263 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3264 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3265 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3266 if (I.getNumOperands() == 2 && // Basic sanity checks.
3267 I.getOperand(1)->getType()->isFloatingPoint() &&
3268 I.getType() == I.getOperand(1)->getType()) {
3269 SDOperand Tmp = getValue(I.getOperand(1));
3270 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3275 } else if (isa<InlineAsm>(I.getOperand(0))) {
3282 Callee = getValue(I.getOperand(0));
3284 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3286 LowerCallTo(&I, Callee, I.isTailCall());
3290 void SelectionDAGLowering::visitGetResult(GetResultInst &I) {
3291 SDOperand Call = getValue(I.getOperand(0));
3292 setValue(&I, SDOperand(Call.Val, I.getIndex()));
3296 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3297 /// this value and returns the result as a ValueVT value. This uses
3298 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3299 /// If the Flag pointer is NULL, no flag is used.
3300 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3301 SDOperand &Chain, SDOperand *Flag)const{
3302 // Copy the legal parts from the registers.
3303 unsigned NumParts = Regs.size();
3304 SmallVector<SDOperand, 8> Parts(NumParts);
3305 for (unsigned i = 0; i != NumParts; ++i) {
3306 SDOperand Part = Flag ?
3307 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3308 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3309 Chain = Part.getValue(1);
3311 *Flag = Part.getValue(2);
3315 // Assemble the legal parts into the final value.
3316 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3319 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3320 /// specified value into the registers specified by this object. This uses
3321 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3322 /// If the Flag pointer is NULL, no flag is used.
3323 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3324 SDOperand &Chain, SDOperand *Flag) const {
3325 // Get the list of the values's legal parts.
3326 unsigned NumParts = Regs.size();
3327 SmallVector<SDOperand, 8> Parts(NumParts);
3328 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3330 // Copy the parts into the registers.
3331 for (unsigned i = 0; i != NumParts; ++i) {
3332 SDOperand Part = Flag ?
3333 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3334 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3335 Chain = Part.getValue(0);
3337 *Flag = Part.getValue(1);
3341 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3342 /// operand list. This adds the code marker and includes the number of
3343 /// values added into it.
3344 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3345 std::vector<SDOperand> &Ops) const {
3346 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3347 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3348 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3349 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3352 /// isAllocatableRegister - If the specified register is safe to allocate,
3353 /// i.e. it isn't a stack pointer or some other special register, return the
3354 /// register class for the register. Otherwise, return null.
3355 static const TargetRegisterClass *
3356 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3357 const TargetLowering &TLI,
3358 const TargetRegisterInfo *TRI) {
3359 MVT::ValueType FoundVT = MVT::Other;
3360 const TargetRegisterClass *FoundRC = 0;
3361 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3362 E = TRI->regclass_end(); RCI != E; ++RCI) {
3363 MVT::ValueType ThisVT = MVT::Other;
3365 const TargetRegisterClass *RC = *RCI;
3366 // If none of the the value types for this register class are valid, we
3367 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3368 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3370 if (TLI.isTypeLegal(*I)) {
3371 // If we have already found this register in a different register class,
3372 // choose the one with the largest VT specified. For example, on
3373 // PowerPC, we favor f64 register classes over f32.
3374 if (FoundVT == MVT::Other ||
3375 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3382 if (ThisVT == MVT::Other) continue;
3384 // NOTE: This isn't ideal. In particular, this might allocate the
3385 // frame pointer in functions that need it (due to them not being taken
3386 // out of allocation, because a variable sized allocation hasn't been seen
3387 // yet). This is a slight code pessimization, but should still work.
3388 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3389 E = RC->allocation_order_end(MF); I != E; ++I)
3391 // We found a matching register class. Keep looking at others in case
3392 // we find one with larger registers that this physreg is also in.
3403 /// AsmOperandInfo - This contains information for each constraint that we are
3405 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3406 /// CallOperand - If this is the result output operand or a clobber
3407 /// this is null, otherwise it is the incoming operand to the CallInst.
3408 /// This gets modified as the asm is processed.
3409 SDOperand CallOperand;
3411 /// AssignedRegs - If this is a register or register class operand, this
3412 /// contains the set of register corresponding to the operand.
3413 RegsForValue AssignedRegs;
3415 SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3416 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3419 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3420 /// busy in OutputRegs/InputRegs.
3421 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3422 std::set<unsigned> &OutputRegs,
3423 std::set<unsigned> &InputRegs,
3424 const TargetRegisterInfo &TRI) const {
3426 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3427 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3430 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3431 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3436 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3438 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3439 const TargetRegisterInfo &TRI) {
3440 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3442 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3443 for (; *Aliases; ++Aliases)
3444 Regs.insert(*Aliases);
3447 } // end anon namespace.
3450 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3451 /// specified operand. We prefer to assign virtual registers, to allow the
3452 /// register allocator handle the assignment process. However, if the asm uses
3453 /// features that we can't model on machineinstrs, we have SDISel do the
3454 /// allocation. This produces generally horrible, but correct, code.
3456 /// OpInfo describes the operand.
3457 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3458 /// or any explicitly clobbered registers.
3459 /// Input and OutputRegs are the set of already allocated physical registers.
3461 void SelectionDAGLowering::
3462 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3463 std::set<unsigned> &OutputRegs,
3464 std::set<unsigned> &InputRegs) {
3465 // Compute whether this value requires an input register, an output register,
3467 bool isOutReg = false;
3468 bool isInReg = false;
3469 switch (OpInfo.Type) {
3470 case InlineAsm::isOutput:
3473 // If this is an early-clobber output, or if there is an input
3474 // constraint that matches this, we need to reserve the input register
3475 // so no other inputs allocate to it.
3476 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3478 case InlineAsm::isInput:
3482 case InlineAsm::isClobber:
3489 MachineFunction &MF = DAG.getMachineFunction();
3490 std::vector<unsigned> Regs;
3492 // If this is a constraint for a single physreg, or a constraint for a
3493 // register class, find it.
3494 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3495 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3496 OpInfo.ConstraintVT);
3498 unsigned NumRegs = 1;
3499 if (OpInfo.ConstraintVT != MVT::Other)
3500 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3501 MVT::ValueType RegVT;
3502 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3505 // If this is a constraint for a specific physical register, like {r17},
3507 if (PhysReg.first) {
3508 if (OpInfo.ConstraintVT == MVT::Other)
3509 ValueVT = *PhysReg.second->vt_begin();
3511 // Get the actual register value type. This is important, because the user
3512 // may have asked for (e.g.) the AX register in i32 type. We need to
3513 // remember that AX is actually i16 to get the right extension.
3514 RegVT = *PhysReg.second->vt_begin();
3516 // This is a explicit reference to a physical register.
3517 Regs.push_back(PhysReg.first);
3519 // If this is an expanded reference, add the rest of the regs to Regs.
3521 TargetRegisterClass::iterator I = PhysReg.second->begin();
3522 TargetRegisterClass::iterator E = PhysReg.second->end();
3523 for (; *I != PhysReg.first; ++I)
3524 assert(I != E && "Didn't find reg!");
3526 // Already added the first reg.
3528 for (; NumRegs; --NumRegs, ++I) {
3529 assert(I != E && "Ran out of registers to allocate!");
3533 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3534 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3535 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3539 // Otherwise, if this was a reference to an LLVM register class, create vregs
3540 // for this reference.
3541 std::vector<unsigned> RegClassRegs;
3542 const TargetRegisterClass *RC = PhysReg.second;
3544 // If this is an early clobber or tied register, our regalloc doesn't know
3545 // how to maintain the constraint. If it isn't, go ahead and create vreg
3546 // and let the regalloc do the right thing.
3547 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3548 // If there is some other early clobber and this is an input register,
3549 // then we are forced to pre-allocate the input reg so it doesn't
3550 // conflict with the earlyclobber.
3551 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3552 RegVT = *PhysReg.second->vt_begin();
3554 if (OpInfo.ConstraintVT == MVT::Other)
3557 // Create the appropriate number of virtual registers.
3558 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3559 for (; NumRegs; --NumRegs)
3560 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3562 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3566 // Otherwise, we can't allocate it. Let the code below figure out how to
3567 // maintain these constraints.
3568 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3571 // This is a reference to a register class that doesn't directly correspond
3572 // to an LLVM register class. Allocate NumRegs consecutive, available,
3573 // registers from the class.
3574 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3575 OpInfo.ConstraintVT);
3578 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3579 unsigned NumAllocated = 0;
3580 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3581 unsigned Reg = RegClassRegs[i];
3582 // See if this register is available.
3583 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3584 (isInReg && InputRegs.count(Reg))) { // Already used.
3585 // Make sure we find consecutive registers.
3590 // Check to see if this register is allocatable (i.e. don't give out the
3593 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
3594 if (!RC) { // Couldn't allocate this register.
3595 // Reset NumAllocated to make sure we return consecutive registers.
3601 // Okay, this register is good, we can use it.
3604 // If we allocated enough consecutive registers, succeed.
3605 if (NumAllocated == NumRegs) {
3606 unsigned RegStart = (i-NumAllocated)+1;
3607 unsigned RegEnd = i+1;
3608 // Mark all of the allocated registers used.
3609 for (unsigned i = RegStart; i != RegEnd; ++i)
3610 Regs.push_back(RegClassRegs[i]);
3612 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3613 OpInfo.ConstraintVT);
3614 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3619 // Otherwise, we couldn't allocate enough registers for this.
3624 /// visitInlineAsm - Handle a call to an InlineAsm object.
3626 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3627 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3629 /// ConstraintOperands - Information about all of the constraints.
3630 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
3632 SDOperand Chain = getRoot();
3635 std::set<unsigned> OutputRegs, InputRegs;
3637 // Do a prepass over the constraints, canonicalizing them, and building up the
3638 // ConstraintOperands list.
3639 std::vector<InlineAsm::ConstraintInfo>
3640 ConstraintInfos = IA->ParseConstraints();
3642 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3643 // constraint. If so, we can't let the register allocator allocate any input
3644 // registers, because it will not know to avoid the earlyclobbered output reg.
3645 bool SawEarlyClobber = false;
3647 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3648 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3649 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
3650 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
3652 MVT::ValueType OpVT = MVT::Other;
3654 // Compute the value type for each operand.
3655 switch (OpInfo.Type) {
3656 case InlineAsm::isOutput:
3657 if (!OpInfo.isIndirect) {
3658 // The return value of the call is this value. As such, there is no
3659 // corresponding argument.
3660 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3661 OpVT = TLI.getValueType(CS.getType());
3663 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3666 case InlineAsm::isInput:
3667 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3669 case InlineAsm::isClobber:
3674 // If this is an input or an indirect output, process the call argument.
3675 // BasicBlocks are labels, currently appearing only in asm's.
3676 if (OpInfo.CallOperandVal) {
3677 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3678 OpInfo.CallOperand =
3679 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(
3680 OpInfo.CallOperandVal)]);
3682 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3683 const Type *OpTy = OpInfo.CallOperandVal->getType();
3684 // If this is an indirect operand, the operand is a pointer to the
3686 if (OpInfo.isIndirect)
3687 OpTy = cast<PointerType>(OpTy)->getElementType();
3689 // If OpTy is not a first-class value, it may be a struct/union that we
3690 // can tile with integers.
3691 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3692 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3700 OpTy = IntegerType::get(BitSize);
3705 OpVT = TLI.getValueType(OpTy, true);
3709 OpInfo.ConstraintVT = OpVT;
3711 // Compute the constraint code and ConstraintType to use.
3712 OpInfo.ComputeConstraintToUse(TLI);
3714 // Keep track of whether we see an earlyclobber.
3715 SawEarlyClobber |= OpInfo.isEarlyClobber;
3717 // If we see a clobber of a register, it is an early clobber.
3718 if (!SawEarlyClobber &&
3719 OpInfo.Type == InlineAsm::isClobber &&
3720 OpInfo.ConstraintType == TargetLowering::C_Register) {
3721 // Note that we want to ignore things that we don't trick here, like
3722 // dirflag, fpsr, flags, etc.
3723 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3724 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3725 OpInfo.ConstraintVT);
3726 if (PhysReg.first || PhysReg.second) {
3727 // This is a register we know of.
3728 SawEarlyClobber = true;
3732 // If this is a memory input, and if the operand is not indirect, do what we
3733 // need to to provide an address for the memory input.
3734 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3735 !OpInfo.isIndirect) {
3736 assert(OpInfo.Type == InlineAsm::isInput &&
3737 "Can only indirectify direct input operands!");
3739 // Memory operands really want the address of the value. If we don't have
3740 // an indirect input, put it in the constpool if we can, otherwise spill
3741 // it to a stack slot.
3743 // If the operand is a float, integer, or vector constant, spill to a
3744 // constant pool entry to get its address.
3745 Value *OpVal = OpInfo.CallOperandVal;
3746 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3747 isa<ConstantVector>(OpVal)) {
3748 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3749 TLI.getPointerTy());
3751 // Otherwise, create a stack slot and emit a store to it before the
3753 const Type *Ty = OpVal->getType();
3754 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3755 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3756 MachineFunction &MF = DAG.getMachineFunction();
3757 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3758 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3759 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3760 OpInfo.CallOperand = StackSlot;
3763 // There is no longer a Value* corresponding to this operand.
3764 OpInfo.CallOperandVal = 0;
3765 // It is now an indirect operand.
3766 OpInfo.isIndirect = true;
3769 // If this constraint is for a specific register, allocate it before
3771 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3772 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3774 ConstraintInfos.clear();
3777 // Second pass - Loop over all of the operands, assigning virtual or physregs
3778 // to registerclass operands.
3779 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3780 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
3782 // C_Register operands have already been allocated, Other/Memory don't need
3784 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3785 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3788 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3789 std::vector<SDOperand> AsmNodeOperands;
3790 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3791 AsmNodeOperands.push_back(
3792 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3795 // Loop over all of the inputs, copying the operand values into the
3796 // appropriate registers and processing the output regs.
3797 RegsForValue RetValRegs;
3799 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3800 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3802 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3803 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
3805 switch (OpInfo.Type) {
3806 case InlineAsm::isOutput: {
3807 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3808 OpInfo.ConstraintType != TargetLowering::C_Register) {
3809 // Memory output, or 'other' output (e.g. 'X' constraint).
3810 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3812 // Add information to the INLINEASM node to know about this output.
3813 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3814 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3815 TLI.getPointerTy()));
3816 AsmNodeOperands.push_back(OpInfo.CallOperand);
3820 // Otherwise, this is a register or register class output.
3822 // Copy the output from the appropriate register. Find a register that
3824 if (OpInfo.AssignedRegs.Regs.empty()) {
3825 cerr << "Couldn't allocate output reg for contraint '"
3826 << OpInfo.ConstraintCode << "'!\n";
3830 if (!OpInfo.isIndirect) {
3831 // This is the result value of the call.
3832 assert(RetValRegs.Regs.empty() &&
3833 "Cannot have multiple output constraints yet!");
3834 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3835 RetValRegs = OpInfo.AssignedRegs;
3837 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3838 OpInfo.CallOperandVal));
3841 // Add information to the INLINEASM node to know that this register is
3843 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3847 case InlineAsm::isInput: {
3848 SDOperand InOperandVal = OpInfo.CallOperand;
3850 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3851 // If this is required to match an output register we have already set,
3852 // just use its register.
3853 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3855 // Scan until we find the definition we already emitted of this operand.
3856 // When we find it, create a RegsForValue operand.
3857 unsigned CurOp = 2; // The first operand.
3858 for (; OperandNo; --OperandNo) {
3859 // Advance to the next operand.
3861 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3862 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3863 (NumOps & 7) == 4 /*MEM*/) &&
3864 "Skipped past definitions?");
3865 CurOp += (NumOps>>3)+1;
3869 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3870 if ((NumOps & 7) == 2 /*REGDEF*/) {
3871 // Add NumOps>>3 registers to MatchedRegs.
3872 RegsForValue MatchedRegs;
3873 MatchedRegs.ValueVT = InOperandVal.getValueType();
3874 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3875 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3877 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3878 MatchedRegs.Regs.push_back(Reg);
3881 // Use the produced MatchedRegs object to
3882 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3883 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3886 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3887 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
3888 // Add information to the INLINEASM node to know about this input.
3889 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3890 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3891 TLI.getPointerTy()));
3892 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
3897 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3898 assert(!OpInfo.isIndirect &&
3899 "Don't know how to handle indirect other inputs yet!");
3901 std::vector<SDOperand> Ops;
3902 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3905 cerr << "Invalid operand for inline asm constraint '"
3906 << OpInfo.ConstraintCode << "'!\n";
3910 // Add information to the INLINEASM node to know about this input.
3911 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3912 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3913 TLI.getPointerTy()));
3914 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3916 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3917 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3918 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3919 "Memory operands expect pointer values");
3921 // Add information to the INLINEASM node to know about this input.
3922 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3923 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3924 TLI.getPointerTy()));
3925 AsmNodeOperands.push_back(InOperandVal);
3929 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3930 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3931 "Unknown constraint type!");
3932 assert(!OpInfo.isIndirect &&
3933 "Don't know how to handle indirect register inputs yet!");
3935 // Copy the input into the appropriate registers.
3936 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3937 "Couldn't allocate input reg!");
3939 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3941 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3945 case InlineAsm::isClobber: {
3946 // Add the clobbered value to the operand list, so that the register
3947 // allocator is aware that the physreg got clobbered.
3948 if (!OpInfo.AssignedRegs.Regs.empty())
3949 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3956 // Finish up input operands.
3957 AsmNodeOperands[0] = Chain;
3958 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3960 Chain = DAG.getNode(ISD::INLINEASM,
3961 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3962 &AsmNodeOperands[0], AsmNodeOperands.size());
3963 Flag = Chain.getValue(1);
3965 // If this asm returns a register value, copy the result from that register
3966 // and set it as the value of the call.
3967 if (!RetValRegs.Regs.empty()) {
3968 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3970 // If the result of the inline asm is a vector, it may have the wrong
3971 // width/num elts. Make sure to convert it to the right type with
3973 if (MVT::isVector(Val.getValueType())) {
3974 const VectorType *VTy = cast<VectorType>(CS.getType());
3975 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3977 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3980 setValue(CS.getInstruction(), Val);
3983 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3985 // Process indirect outputs, first output all of the flagged copies out of
3987 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3988 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3989 Value *Ptr = IndirectStoresToEmit[i].second;
3990 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3991 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3994 // Emit the non-flagged stores from the physregs.
3995 SmallVector<SDOperand, 8> OutChains;
3996 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3997 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3998 getValue(StoresToEmit[i].second),
3999 StoresToEmit[i].second, 0));
4000 if (!OutChains.empty())
4001 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4002 &OutChains[0], OutChains.size());
4007 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4008 SDOperand Src = getValue(I.getOperand(0));
4010 MVT::ValueType IntPtr = TLI.getPointerTy();
4012 if (IntPtr < Src.getValueType())
4013 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4014 else if (IntPtr > Src.getValueType())
4015 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4017 // Scale the source by the type size.
4018 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4019 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4020 Src, DAG.getIntPtrConstant(ElementSize));
4022 TargetLowering::ArgListTy Args;
4023 TargetLowering::ArgListEntry Entry;
4025 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4026 Args.push_back(Entry);
4028 std::pair<SDOperand,SDOperand> Result =
4029 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4030 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4031 setValue(&I, Result.first); // Pointers always fit in registers
4032 DAG.setRoot(Result.second);
4035 void SelectionDAGLowering::visitFree(FreeInst &I) {
4036 TargetLowering::ArgListTy Args;
4037 TargetLowering::ArgListEntry Entry;
4038 Entry.Node = getValue(I.getOperand(0));
4039 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4040 Args.push_back(Entry);
4041 MVT::ValueType IntPtr = TLI.getPointerTy();
4042 std::pair<SDOperand,SDOperand> Result =
4043 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4044 CallingConv::C, true,
4045 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4046 DAG.setRoot(Result.second);
4049 // EmitInstrWithCustomInserter - This method should be implemented by targets
4050 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4051 // instructions are special in various ways, which require special support to
4052 // insert. The specified MachineInstr is created but not inserted into any
4053 // basic blocks, and the scheduler passes ownership of it to this method.
4054 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4055 MachineBasicBlock *MBB) {
4056 cerr << "If a target marks an instruction with "
4057 << "'usesCustomDAGSchedInserter', it must implement "
4058 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4063 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4064 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4065 getValue(I.getOperand(1)),
4066 DAG.getSrcValue(I.getOperand(1))));
4069 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4070 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4071 getValue(I.getOperand(0)),
4072 DAG.getSrcValue(I.getOperand(0)));
4074 DAG.setRoot(V.getValue(1));
4077 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4078 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4079 getValue(I.getOperand(1)),
4080 DAG.getSrcValue(I.getOperand(1))));
4083 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4084 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4085 getValue(I.getOperand(1)),
4086 getValue(I.getOperand(2)),
4087 DAG.getSrcValue(I.getOperand(1)),
4088 DAG.getSrcValue(I.getOperand(2))));
4091 /// TargetLowering::LowerArguments - This is the default LowerArguments
4092 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4093 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4094 /// integrated into SDISel.
4095 std::vector<SDOperand>
4096 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
4097 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4098 std::vector<SDOperand> Ops;
4099 Ops.push_back(DAG.getRoot());
4100 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4101 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4103 // Add one result value for each formal argument.
4104 std::vector<MVT::ValueType> RetVals;
4106 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4108 MVT::ValueType VT = getValueType(I->getType());
4109 ISD::ArgFlagsTy Flags;
4110 unsigned OriginalAlignment =
4111 getTargetData()->getABITypeAlignment(I->getType());
4113 if (F.paramHasAttr(j, ParamAttr::ZExt))
4115 if (F.paramHasAttr(j, ParamAttr::SExt))
4117 if (F.paramHasAttr(j, ParamAttr::InReg))
4119 if (F.paramHasAttr(j, ParamAttr::StructRet))
4121 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4123 const PointerType *Ty = cast<PointerType>(I->getType());
4124 const Type *ElementTy = Ty->getElementType();
4125 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4126 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4127 // For ByVal, alignment should be passed from FE. BE will guess if
4128 // this info is not there but there are cases it cannot get right.
4129 if (F.getParamAlignment(j))
4130 FrameAlign = F.getParamAlignment(j);
4131 Flags.setByValAlign(FrameAlign);
4132 Flags.setByValSize(FrameSize);
4134 if (F.paramHasAttr(j, ParamAttr::Nest))
4136 Flags.setOrigAlign(OriginalAlignment);
4138 MVT::ValueType RegisterVT = getRegisterType(VT);
4139 unsigned NumRegs = getNumRegisters(VT);
4140 for (unsigned i = 0; i != NumRegs; ++i) {
4141 RetVals.push_back(RegisterVT);
4142 // if it isn't first piece, alignment must be 1
4144 Flags.setOrigAlign(1);
4145 Ops.push_back(DAG.getArgFlags(Flags));
4149 RetVals.push_back(MVT::Other);
4152 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4153 DAG.getVTList(&RetVals[0], RetVals.size()),
4154 &Ops[0], Ops.size()).Val;
4156 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4157 // allows exposing the loads that may be part of the argument access to the
4158 // first DAGCombiner pass.
4159 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4161 // The number of results should match up, except that the lowered one may have
4162 // an extra flag result.
4163 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4164 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4165 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4166 && "Lowering produced unexpected number of results!");
4167 Result = TmpRes.Val;
4169 unsigned NumArgRegs = Result->getNumValues() - 1;
4170 DAG.setRoot(SDOperand(Result, NumArgRegs));
4172 // Set up the return result vector.
4176 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4178 MVT::ValueType VT = getValueType(I->getType());
4179 MVT::ValueType PartVT = getRegisterType(VT);
4181 unsigned NumParts = getNumRegisters(VT);
4182 SmallVector<SDOperand, 4> Parts(NumParts);
4183 for (unsigned j = 0; j != NumParts; ++j)
4184 Parts[j] = SDOperand(Result, i++);
4186 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4187 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4188 AssertOp = ISD::AssertSext;
4189 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4190 AssertOp = ISD::AssertZext;
4192 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4195 assert(i == NumArgRegs && "Argument register count mismatch!");
4200 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4201 /// implementation, which just inserts an ISD::CALL node, which is later custom
4202 /// lowered by the target to something concrete. FIXME: When all targets are
4203 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4204 std::pair<SDOperand, SDOperand>
4205 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4206 bool RetSExt, bool RetZExt, bool isVarArg,
4207 unsigned CallingConv, bool isTailCall,
4209 ArgListTy &Args, SelectionDAG &DAG) {
4210 SmallVector<SDOperand, 32> Ops;
4211 Ops.push_back(Chain); // Op#0 - Chain
4212 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4213 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4214 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4215 Ops.push_back(Callee);
4217 // Handle all of the outgoing arguments.
4218 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4219 MVT::ValueType VT = getValueType(Args[i].Ty);
4220 SDOperand Op = Args[i].Node;
4221 ISD::ArgFlagsTy Flags;
4222 unsigned OriginalAlignment =
4223 getTargetData()->getABITypeAlignment(Args[i].Ty);
4229 if (Args[i].isInReg)
4233 if (Args[i].isByVal) {
4235 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4236 const Type *ElementTy = Ty->getElementType();
4237 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4238 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4239 // For ByVal, alignment should come from FE. BE will guess if this
4240 // info is not there but there are cases it cannot get right.
4241 if (Args[i].Alignment)
4242 FrameAlign = Args[i].Alignment;
4243 Flags.setByValAlign(FrameAlign);
4244 Flags.setByValSize(FrameSize);
4248 Flags.setOrigAlign(OriginalAlignment);
4250 MVT::ValueType PartVT = getRegisterType(VT);
4251 unsigned NumParts = getNumRegisters(VT);
4252 SmallVector<SDOperand, 4> Parts(NumParts);
4253 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4256 ExtendKind = ISD::SIGN_EXTEND;
4257 else if (Args[i].isZExt)
4258 ExtendKind = ISD::ZERO_EXTEND;
4260 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4262 for (unsigned i = 0; i != NumParts; ++i) {
4263 // if it isn't first piece, alignment must be 1
4264 ISD::ArgFlagsTy MyFlags = Flags;
4266 MyFlags.setOrigAlign(1);
4268 Ops.push_back(Parts[i]);
4269 Ops.push_back(DAG.getArgFlags(MyFlags));
4273 // Figure out the result value types. We start by making a list of
4274 // the high-level LLVM return types.
4275 SmallVector<const Type *, 4> LLVMRetTys;
4276 if (const StructType *ST = dyn_cast<StructType>(RetTy))
4277 // A struct return type in the LLVM IR means we have multiple return values.
4278 LLVMRetTys.insert(LLVMRetTys.end(), ST->element_begin(), ST->element_end());
4280 LLVMRetTys.push_back(RetTy);
4282 // Then we translate that to a list of lowered codegen result types.
4283 SmallVector<MVT::ValueType, 4> LoweredRetTys;
4284 SmallVector<MVT::ValueType, 4> RetTys;
4285 for (unsigned I = 0, E = LLVMRetTys.size(); I != E; ++I) {
4286 MVT::ValueType VT = getValueType(LLVMRetTys[I]);
4287 RetTys.push_back(VT);
4289 MVT::ValueType RegisterVT = getRegisterType(VT);
4290 unsigned NumRegs = getNumRegisters(VT);
4291 for (unsigned i = 0; i != NumRegs; ++i)
4292 LoweredRetTys.push_back(RegisterVT);
4295 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4297 // Create the CALL node.
4298 SDOperand Res = DAG.getNode(ISD::CALL,
4299 DAG.getVTList(&LoweredRetTys[0],
4300 LoweredRetTys.size()),
4301 &Ops[0], Ops.size());
4302 Chain = Res.getValue(LoweredRetTys.size() - 1);
4304 // Gather up the call result into a single value.
4305 if (RetTy != Type::VoidTy) {
4306 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4309 AssertOp = ISD::AssertSext;
4311 AssertOp = ISD::AssertZext;
4313 SmallVector<SDOperand, 4> ReturnValues;
4315 for (unsigned I = 0, E = LLVMRetTys.size(); I != E; ++I) {
4316 MVT::ValueType VT = getValueType(LLVMRetTys[I]);
4317 MVT::ValueType RegisterVT = getRegisterType(VT);
4318 unsigned NumRegs = getNumRegisters(VT);
4319 unsigned RegNoEnd = NumRegs + RegNo;
4320 SmallVector<SDOperand, 4> Results;
4321 for (; RegNo != RegNoEnd; ++RegNo)
4322 Results.push_back(Res.getValue(RegNo));
4323 SDOperand ReturnValue =
4324 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4326 ReturnValues.push_back(ReturnValue);
4328 Res = ReturnValues.size() == 1 ? ReturnValues.front() :
4329 DAG.getNode(ISD::MERGE_VALUES,
4330 DAG.getVTList(&RetTys[0], RetTys.size()),
4331 &ReturnValues[0], ReturnValues.size());
4334 return std::make_pair(Res, Chain);
4337 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4338 assert(0 && "LowerOperation not implemented for this target!");
4343 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4344 SelectionDAG &DAG) {
4345 assert(0 && "CustomPromoteOperation not implemented for this target!");
4350 /// getMemsetValue - Vectorized representation of the memset value
4352 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4353 SelectionDAG &DAG) {
4354 MVT::ValueType CurVT = VT;
4355 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4356 uint64_t Val = C->getValue() & 255;
4358 while (CurVT != MVT::i8) {
4359 Val = (Val << Shift) | Val;
4361 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4363 return DAG.getConstant(Val, VT);
4365 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4367 while (CurVT != MVT::i8) {
4369 DAG.getNode(ISD::OR, VT,
4370 DAG.getNode(ISD::SHL, VT, Value,
4371 DAG.getConstant(Shift, MVT::i8)), Value);
4373 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4380 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4381 /// used when a memcpy is turned into a memset when the source is a constant
4383 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4384 SelectionDAG &DAG, TargetLowering &TLI,
4385 std::string &Str, unsigned Offset) {
4387 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4388 if (TLI.isLittleEndian())
4389 Offset = Offset + MSB - 1;
4390 for (unsigned i = 0; i != MSB; ++i) {
4391 Val = (Val << 8) | (unsigned char)Str[Offset];
4392 Offset += TLI.isLittleEndian() ? -1 : 1;
4394 return DAG.getConstant(Val, VT);
4397 /// getMemBasePlusOffset - Returns base and offset node for the
4398 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4399 SelectionDAG &DAG, TargetLowering &TLI) {
4400 MVT::ValueType VT = Base.getValueType();
4401 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4404 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4405 /// to replace the memset / memcpy is below the threshold. It also returns the
4406 /// types of the sequence of memory ops to perform memset / memcpy.
4407 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4408 unsigned Limit, uint64_t Size,
4409 unsigned Align, TargetLowering &TLI) {
4412 if (TLI.allowsUnalignedMemoryAccesses()) {
4415 switch (Align & 7) {
4431 MVT::ValueType LVT = MVT::i64;
4432 while (!TLI.isTypeLegal(LVT))
4433 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4434 assert(MVT::isInteger(LVT));
4439 unsigned NumMemOps = 0;
4441 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4442 while (VTSize > Size) {
4443 VT = (MVT::ValueType)((unsigned)VT - 1);
4446 assert(MVT::isInteger(VT));
4448 if (++NumMemOps > Limit)
4450 MemOps.push_back(VT);
4457 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4458 SDOperand Op1 = getValue(I.getOperand(1));
4459 SDOperand Op2 = getValue(I.getOperand(2));
4460 SDOperand Op3 = getValue(I.getOperand(3));
4461 SDOperand Op4 = getValue(I.getOperand(4));
4462 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4463 if (Align == 0) Align = 1;
4465 // If the source and destination are known to not be aliases, we can
4466 // lower memmove as memcpy.
4467 if (Op == ISD::MEMMOVE) {
4468 uint64_t Size = -1ULL;
4469 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4470 Size = C->getValue();
4471 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4472 AliasAnalysis::NoAlias)
4476 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4477 std::vector<MVT::ValueType> MemOps;
4479 // Expand memset / memcpy to a series of load / store ops
4480 // if the size operand falls below a certain threshold.
4481 SmallVector<SDOperand, 8> OutChains;
4483 default: break; // Do nothing for now.
4485 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4486 Size->getValue(), Align, TLI)) {
4487 unsigned NumMemOps = MemOps.size();
4488 unsigned Offset = 0;
4489 for (unsigned i = 0; i < NumMemOps; i++) {
4490 MVT::ValueType VT = MemOps[i];
4491 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4492 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4493 SDOperand Store = DAG.getStore(getRoot(), Value,
4494 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4495 I.getOperand(1), Offset);
4496 OutChains.push_back(Store);
4503 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4504 Size->getValue(), Align, TLI)) {
4505 unsigned NumMemOps = MemOps.size();
4506 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4507 GlobalAddressSDNode *G = NULL;
4509 bool CopyFromStr = false;
4511 if (Op2.getOpcode() == ISD::GlobalAddress)
4512 G = cast<GlobalAddressSDNode>(Op2);
4513 else if (Op2.getOpcode() == ISD::ADD &&
4514 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4515 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4516 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4517 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4520 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4521 if (GV && GV->isConstant()) {
4522 Str = GV->getStringValue(false);
4530 for (unsigned i = 0; i < NumMemOps; i++) {
4531 MVT::ValueType VT = MemOps[i];
4532 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4533 SDOperand Value, Chain, Store;
4536 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4539 DAG.getStore(Chain, Value,
4540 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4541 I.getOperand(1), DstOff);
4543 Value = DAG.getLoad(VT, getRoot(),
4544 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4545 I.getOperand(2), SrcOff, false, Align);
4546 Chain = Value.getValue(1);
4548 DAG.getStore(Chain, Value,
4549 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4550 I.getOperand(1), DstOff, false, Align);
4552 OutChains.push_back(Store);
4561 if (!OutChains.empty()) {
4562 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4563 &OutChains[0], OutChains.size()));
4568 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4572 assert(0 && "Unknown Op");
4574 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4577 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4580 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4586 //===----------------------------------------------------------------------===//
4587 // SelectionDAGISel code
4588 //===----------------------------------------------------------------------===//
4590 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4591 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4594 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4595 AU.addRequired<AliasAnalysis>();
4596 AU.addRequired<CollectorModuleMetadata>();
4597 AU.setPreservesAll();
4602 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4603 // Get alias analysis for load/store combining.
4604 AA = &getAnalysis<AliasAnalysis>();
4606 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4607 if (MF.getFunction()->hasCollector())
4608 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4611 RegInfo = &MF.getRegInfo();
4612 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4614 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4616 if (ExceptionHandling)
4617 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4618 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4619 // Mark landing pad.
4620 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4622 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4623 SelectBasicBlock(I, MF, FuncInfo);
4625 // Add function live-ins to entry block live-in set.
4626 BasicBlock *EntryBB = &Fn.getEntryBlock();
4627 BB = FuncInfo.MBBMap[EntryBB];
4628 if (!RegInfo->livein_empty())
4629 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4630 E = RegInfo->livein_end(); I != E; ++I)
4631 BB->addLiveIn(I->first);
4634 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4635 "Not all catch info was assigned to a landing pad!");
4641 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4643 SDOperand Op = getValue(V);
4644 assert((Op.getOpcode() != ISD::CopyFromReg ||
4645 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4646 "Copy from a reg to the same reg!");
4647 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4649 MVT::ValueType SrcVT = Op.getValueType();
4650 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4651 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4652 SmallVector<SDOperand, 8> Regs(NumRegs);
4653 SmallVector<SDOperand, 8> Chains(NumRegs);
4655 // Copy the value by legal parts into sequential virtual registers.
4656 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4657 for (unsigned i = 0; i != NumRegs; ++i)
4658 Chains[i] = DAG.getCopyToReg(DAG.getEntryNode(), Reg + i, Regs[i]);
4659 SDOperand Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4660 PendingExports.push_back(Ch);
4663 void SelectionDAGISel::
4664 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4665 // If this is the entry block, emit arguments.
4666 Function &F = *LLVMBB->getParent();
4667 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4668 SDOperand OldRoot = SDL.DAG.getRoot();
4669 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4672 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4674 if (!AI->use_empty()) {
4675 SDL.setValue(AI, Args[a]);
4677 // If this argument is live outside of the entry block, insert a copy from
4678 // whereever we got it to the vreg that other BB's will reference it as.
4679 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4680 if (VMI != FuncInfo.ValueMap.end()) {
4681 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4685 // Finally, if the target has anything special to do, allow it to do so.
4686 // FIXME: this should insert code into the DAG!
4687 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4690 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4691 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4692 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4693 if (isSelector(I)) {
4694 // Apply the catch info to DestBB.
4695 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4697 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4698 FLI.CatchInfoFound.insert(I);
4703 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4704 /// DAG and fixes their tailcall attribute operand.
4705 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4706 TargetLowering& TLI) {
4707 SDNode * Ret = NULL;
4708 SDOperand Terminator = DAG.getRoot();
4711 if (Terminator.getOpcode() == ISD::RET) {
4712 Ret = Terminator.Val;
4715 // Fix tail call attribute of CALL nodes.
4716 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4717 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4718 if (BI->getOpcode() == ISD::CALL) {
4719 SDOperand OpRet(Ret, 0);
4720 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4721 bool isMarkedTailCall =
4722 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4723 // If CALL node has tail call attribute set to true and the call is not
4724 // eligible (no RET or the target rejects) the attribute is fixed to
4725 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4726 // must correctly identify tail call optimizable calls.
4727 if (isMarkedTailCall &&
4729 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4730 SmallVector<SDOperand, 32> Ops;
4732 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4733 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4737 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4739 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4745 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4746 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4747 FunctionLoweringInfo &FuncInfo) {
4748 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4750 // Lower any arguments needed in this block if this is the entry block.
4751 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4752 LowerArguments(LLVMBB, SDL);
4754 BB = FuncInfo.MBBMap[LLVMBB];
4755 SDL.setCurrentBasicBlock(BB);
4757 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4759 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4760 // Add a label to mark the beginning of the landing pad. Deletion of the
4761 // landing pad can thus be detected via the MachineModuleInfo.
4762 unsigned LabelID = MMI->addLandingPad(BB);
4763 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4764 DAG.getConstant(LabelID, MVT::i32),
4765 DAG.getConstant(1, MVT::i32)));
4767 // Mark exception register as live in.
4768 unsigned Reg = TLI.getExceptionAddressRegister();
4769 if (Reg) BB->addLiveIn(Reg);
4771 // Mark exception selector register as live in.
4772 Reg = TLI.getExceptionSelectorRegister();
4773 if (Reg) BB->addLiveIn(Reg);
4775 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4776 // function and list of typeids logically belong to the invoke (or, if you
4777 // like, the basic block containing the invoke), and need to be associated
4778 // with it in the dwarf exception handling tables. Currently however the
4779 // information is provided by an intrinsic (eh.selector) that can be moved
4780 // to unexpected places by the optimizers: if the unwind edge is critical,
4781 // then breaking it can result in the intrinsics being in the successor of
4782 // the landing pad, not the landing pad itself. This results in exceptions
4783 // not being caught because no typeids are associated with the invoke.
4784 // This may not be the only way things can go wrong, but it is the only way
4785 // we try to work around for the moment.
4786 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4788 if (Br && Br->isUnconditional()) { // Critical edge?
4789 BasicBlock::iterator I, E;
4790 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4795 // No catch info found - try to extract some from the successor.
4796 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4800 // Lower all of the non-terminator instructions.
4801 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4805 // Ensure that all instructions which are used outside of their defining
4806 // blocks are available as virtual registers. Invoke is handled elsewhere.
4807 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4808 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4809 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4810 if (VMI != FuncInfo.ValueMap.end())
4811 SDL.CopyValueToVirtualRegister(I, VMI->second);
4814 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4815 // ensure constants are generated when needed. Remember the virtual registers
4816 // that need to be added to the Machine PHI nodes as input. We cannot just
4817 // directly add them, because expansion might result in multiple MBB's for one
4818 // BB. As such, the start of the BB might correspond to a different MBB than
4821 TerminatorInst *TI = LLVMBB->getTerminator();
4823 // Emit constants only once even if used by multiple PHI nodes.
4824 std::map<Constant*, unsigned> ConstantsOut;
4826 // Vector bool would be better, but vector<bool> is really slow.
4827 std::vector<unsigned char> SuccsHandled;
4828 if (TI->getNumSuccessors())
4829 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4831 // Check successor nodes' PHI nodes that expect a constant to be available
4833 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4834 BasicBlock *SuccBB = TI->getSuccessor(succ);
4835 if (!isa<PHINode>(SuccBB->begin())) continue;
4836 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4838 // If this terminator has multiple identical successors (common for
4839 // switches), only handle each succ once.
4840 unsigned SuccMBBNo = SuccMBB->getNumber();
4841 if (SuccsHandled[SuccMBBNo]) continue;
4842 SuccsHandled[SuccMBBNo] = true;
4844 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4847 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4848 // nodes and Machine PHI nodes, but the incoming operands have not been
4850 for (BasicBlock::iterator I = SuccBB->begin();
4851 (PN = dyn_cast<PHINode>(I)); ++I) {
4852 // Ignore dead phi's.
4853 if (PN->use_empty()) continue;
4856 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4858 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4859 unsigned &RegOut = ConstantsOut[C];
4861 RegOut = FuncInfo.CreateRegForValue(C);
4862 SDL.CopyValueToVirtualRegister(C, RegOut);
4866 Reg = FuncInfo.ValueMap[PHIOp];
4868 assert(isa<AllocaInst>(PHIOp) &&
4869 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4870 "Didn't codegen value into a register!??");
4871 Reg = FuncInfo.CreateRegForValue(PHIOp);
4872 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
4876 // Remember that this register needs to added to the machine PHI node as
4877 // the input for this MBB.
4878 MVT::ValueType VT = TLI.getValueType(PN->getType());
4879 unsigned NumRegisters = TLI.getNumRegisters(VT);
4880 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4881 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4884 ConstantsOut.clear();
4886 // Lower the terminator after the copies are emitted.
4887 SDL.visit(*LLVMBB->getTerminator());
4889 // Copy over any CaseBlock records that may now exist due to SwitchInst
4890 // lowering, as well as any jump table information.
4891 SwitchCases.clear();
4892 SwitchCases = SDL.SwitchCases;
4894 JTCases = SDL.JTCases;
4895 BitTestCases.clear();
4896 BitTestCases = SDL.BitTestCases;
4898 // Make sure the root of the DAG is up-to-date.
4899 DAG.setRoot(SDL.getControlRoot());
4901 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4902 // with correct tailcall attribute so that the target can rely on the tailcall
4903 // attribute indicating whether the call is really eligible for tail call
4905 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4908 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4909 DOUT << "Lowered selection DAG:\n";
4912 // Run the DAG combiner in pre-legalize mode.
4913 DAG.Combine(false, *AA);
4915 DOUT << "Optimized lowered selection DAG:\n";
4918 // Second step, hack on the DAG until it only uses operations and types that
4919 // the target supports.
4920 #if 0 // Enable this some day.
4921 DAG.LegalizeTypes();
4922 // Someday even later, enable a dag combine pass here.
4926 DOUT << "Legalized selection DAG:\n";
4929 // Run the DAG combiner in post-legalize mode.
4930 DAG.Combine(true, *AA);
4932 DOUT << "Optimized legalized selection DAG:\n";
4935 if (ViewISelDAGs) DAG.viewGraph();
4937 // Third, instruction select all of the operations to machine code, adding the
4938 // code to the MachineBasicBlock.
4939 InstructionSelectBasicBlock(DAG);
4941 DOUT << "Selected machine code:\n";
4945 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4946 FunctionLoweringInfo &FuncInfo) {
4947 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4949 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4952 // First step, lower LLVM code to some DAG. This DAG may use operations and
4953 // types that are not supported by the target.
4954 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4956 // Second step, emit the lowered DAG as machine code.
4957 CodeGenAndEmitDAG(DAG);
4960 DOUT << "Total amount of phi nodes to update: "
4961 << PHINodesToUpdate.size() << "\n";
4962 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4963 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4964 << ", " << PHINodesToUpdate[i].second << ")\n";);
4966 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4967 // PHI nodes in successors.
4968 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4969 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4970 MachineInstr *PHI = PHINodesToUpdate[i].first;
4971 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4972 "This is not a machine PHI node that we are updating!");
4973 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4975 PHI->addOperand(MachineOperand::CreateMBB(BB));
4980 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4981 // Lower header first, if it wasn't already lowered
4982 if (!BitTestCases[i].Emitted) {
4983 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4985 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4986 // Set the current basic block to the mbb we wish to insert the code into
4987 BB = BitTestCases[i].Parent;
4988 HSDL.setCurrentBasicBlock(BB);
4990 HSDL.visitBitTestHeader(BitTestCases[i]);
4991 HSDAG.setRoot(HSDL.getRoot());
4992 CodeGenAndEmitDAG(HSDAG);
4995 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4996 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4998 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
4999 // Set the current basic block to the mbb we wish to insert the code into
5000 BB = BitTestCases[i].Cases[j].ThisBB;
5001 BSDL.setCurrentBasicBlock(BB);
5004 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5005 BitTestCases[i].Reg,
5006 BitTestCases[i].Cases[j]);
5008 BSDL.visitBitTestCase(BitTestCases[i].Default,
5009 BitTestCases[i].Reg,
5010 BitTestCases[i].Cases[j]);
5013 BSDAG.setRoot(BSDL.getRoot());
5014 CodeGenAndEmitDAG(BSDAG);
5018 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5019 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5020 MachineBasicBlock *PHIBB = PHI->getParent();
5021 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5022 "This is not a machine PHI node that we are updating!");
5023 // This is "default" BB. We have two jumps to it. From "header" BB and
5024 // from last "case" BB.
5025 if (PHIBB == BitTestCases[i].Default) {
5026 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5028 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5029 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5031 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5034 // One of "cases" BB.
5035 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5036 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5037 if (cBB->succ_end() !=
5038 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5039 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5041 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5047 // If the JumpTable record is filled in, then we need to emit a jump table.
5048 // Updating the PHI nodes is tricky in this case, since we need to determine
5049 // whether the PHI is a successor of the range check MBB or the jump table MBB
5050 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5051 // Lower header first, if it wasn't already lowered
5052 if (!JTCases[i].first.Emitted) {
5053 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5055 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5056 // Set the current basic block to the mbb we wish to insert the code into
5057 BB = JTCases[i].first.HeaderBB;
5058 HSDL.setCurrentBasicBlock(BB);
5060 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5061 HSDAG.setRoot(HSDL.getRoot());
5062 CodeGenAndEmitDAG(HSDAG);
5065 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5067 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5068 // Set the current basic block to the mbb we wish to insert the code into
5069 BB = JTCases[i].second.MBB;
5070 JSDL.setCurrentBasicBlock(BB);
5072 JSDL.visitJumpTable(JTCases[i].second);
5073 JSDAG.setRoot(JSDL.getRoot());
5074 CodeGenAndEmitDAG(JSDAG);
5077 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5078 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5079 MachineBasicBlock *PHIBB = PHI->getParent();
5080 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5081 "This is not a machine PHI node that we are updating!");
5082 // "default" BB. We can go there only from header BB.
5083 if (PHIBB == JTCases[i].second.Default) {
5084 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5086 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5088 // JT BB. Just iterate over successors here
5089 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5090 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5092 PHI->addOperand(MachineOperand::CreateMBB(BB));
5097 // If the switch block involved a branch to one of the actual successors, we
5098 // need to update PHI nodes in that block.
5099 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5100 MachineInstr *PHI = PHINodesToUpdate[i].first;
5101 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5102 "This is not a machine PHI node that we are updating!");
5103 if (BB->isSuccessor(PHI->getParent())) {
5104 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5106 PHI->addOperand(MachineOperand::CreateMBB(BB));
5110 // If we generated any switch lowering information, build and codegen any
5111 // additional DAGs necessary.
5112 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5113 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5115 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5117 // Set the current basic block to the mbb we wish to insert the code into
5118 BB = SwitchCases[i].ThisBB;
5119 SDL.setCurrentBasicBlock(BB);
5122 SDL.visitSwitchCase(SwitchCases[i]);
5123 SDAG.setRoot(SDL.getRoot());
5124 CodeGenAndEmitDAG(SDAG);
5126 // Handle any PHI nodes in successors of this chunk, as if we were coming
5127 // from the original BB before switch expansion. Note that PHI nodes can
5128 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5129 // handle them the right number of times.
5130 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5131 for (MachineBasicBlock::iterator Phi = BB->begin();
5132 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5133 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5134 for (unsigned pn = 0; ; ++pn) {
5135 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5136 if (PHINodesToUpdate[pn].first == Phi) {
5137 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5139 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5145 // Don't process RHS if same block as LHS.
5146 if (BB == SwitchCases[i].FalseBB)
5147 SwitchCases[i].FalseBB = 0;
5149 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5150 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5151 SwitchCases[i].FalseBB = 0;
5153 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5158 //===----------------------------------------------------------------------===//
5159 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5160 /// target node in the graph.
5161 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5162 if (ViewSchedDAGs) DAG.viewGraph();
5164 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5168 RegisterScheduler::setDefault(Ctor);
5171 ScheduleDAG *SL = Ctor(this, &DAG, BB);
5174 if (ViewSUnitDAGs) SL->viewGraph();
5180 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5181 return new HazardRecognizer();
5184 //===----------------------------------------------------------------------===//
5185 // Helper functions used by the generated instruction selector.
5186 //===----------------------------------------------------------------------===//
5187 // Calls to these methods are generated by tblgen.
5189 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5190 /// the dag combiner simplified the 255, we still want to match. RHS is the
5191 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5192 /// specified in the .td file (e.g. 255).
5193 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5194 int64_t DesiredMaskS) const {
5195 const APInt &ActualMask = RHS->getAPIntValue();
5196 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5198 // If the actual mask exactly matches, success!
5199 if (ActualMask == DesiredMask)
5202 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5203 if (ActualMask.intersects(~DesiredMask))
5206 // Otherwise, the DAG Combiner may have proven that the value coming in is
5207 // either already zero or is not demanded. Check for known zero input bits.
5208 APInt NeededMask = DesiredMask & ~ActualMask;
5209 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5212 // TODO: check to see if missing bits are just not demanded.
5214 // Otherwise, this pattern doesn't match.
5218 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5219 /// the dag combiner simplified the 255, we still want to match. RHS is the
5220 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5221 /// specified in the .td file (e.g. 255).
5222 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5223 int64_t DesiredMaskS) const {
5224 const APInt &ActualMask = RHS->getAPIntValue();
5225 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5227 // If the actual mask exactly matches, success!
5228 if (ActualMask == DesiredMask)
5231 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5232 if (ActualMask.intersects(~DesiredMask))
5235 // Otherwise, the DAG Combiner may have proven that the value coming in is
5236 // either already zero or is not demanded. Check for known zero input bits.
5237 APInt NeededMask = DesiredMask & ~ActualMask;
5239 APInt KnownZero, KnownOne;
5240 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5242 // If all the missing bits in the or are already known to be set, match!
5243 if ((NeededMask & KnownOne) == NeededMask)
5246 // TODO: check to see if missing bits are just not demanded.
5248 // Otherwise, this pattern doesn't match.
5253 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5254 /// by tblgen. Others should not call it.
5255 void SelectionDAGISel::
5256 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5257 std::vector<SDOperand> InOps;
5258 std::swap(InOps, Ops);
5260 Ops.push_back(InOps[0]); // input chain.
5261 Ops.push_back(InOps[1]); // input asm string.
5263 unsigned i = 2, e = InOps.size();
5264 if (InOps[e-1].getValueType() == MVT::Flag)
5265 --e; // Don't process a flag operand if it is here.
5268 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5269 if ((Flags & 7) != 4 /*MEM*/) {
5270 // Just skip over this operand, copying the operands verbatim.
5271 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5272 i += (Flags >> 3) + 1;
5274 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5275 // Otherwise, this is a memory operand. Ask the target to select it.
5276 std::vector<SDOperand> SelOps;
5277 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5278 cerr << "Could not match memory address. Inline asm failure!\n";
5282 // Add this to the output node.
5283 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5284 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5286 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5291 // Add the flag input back if present.
5292 if (e != InOps.size())
5293 Ops.push_back(InOps.back());
5296 char SelectionDAGISel::ID = 0;