1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/ADT/PostOrderIterator.h"
54 #include "llvm/ADT/Statistic.h"
58 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
59 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
60 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
61 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
62 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
65 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
66 cl::desc("Enable verbose messages in the \"fast\" "
67 "instruction selector"));
69 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
70 cl::desc("Enable abort calls when \"fast\" instruction fails"));
74 cl::desc("use Machine Branch Probability Info"),
75 cl::init(true), cl::Hidden);
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
114 //===---------------------------------------------------------------------===//
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
123 /// ISHeuristic command line option for instruction schedulers.
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createSourceListDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == Sched::RegPressure)
148 return createBURRListDAGScheduler(IS, OptLevel);
149 if (TLI.getSchedulingPreference() == Sched::Hybrid)
150 return createHybridListDAGScheduler(IS, OptLevel);
151 assert(TLI.getSchedulingPreference() == Sched::ILP &&
152 "Unknown sched type!");
153 return createILPListDAGScheduler(IS, OptLevel);
157 // EmitInstrWithCustomInserter - This method should be implemented by targets
158 // that mark instructions with the 'usesCustomInserter' flag. These
159 // instructions are special in various ways, which require special support to
160 // insert. The specified MachineInstr is created but not inserted into any
161 // basic blocks, and this method is called to expand it into a sequence of
162 // instructions, potentially also creating new basic blocks and control flow.
163 // When new basic blocks are inserted and the edges from MBB to its successors
164 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
167 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
168 MachineBasicBlock *MBB) const {
170 dbgs() << "If a target marks an instruction with "
171 "'usesCustomInserter', it must implement "
172 "TargetLowering::EmitInstrWithCustomInserter!";
178 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
179 SDNode *Node) const {
180 assert(!MI->getDesc().hasPostISelHook() &&
181 "If a target marks an instruction with 'hasPostISelHook', "
182 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
185 //===----------------------------------------------------------------------===//
186 // SelectionDAGISel code
187 //===----------------------------------------------------------------------===//
189 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
190 CodeGenOpt::Level OL) :
191 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
192 FuncInfo(new FunctionLoweringInfo(TLI)),
193 CurDAG(new SelectionDAG(tm)),
194 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
198 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
199 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
200 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
203 SelectionDAGISel::~SelectionDAGISel() {
209 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
210 AU.addRequired<AliasAnalysis>();
211 AU.addPreserved<AliasAnalysis>();
212 AU.addRequired<GCModuleInfo>();
213 AU.addPreserved<GCModuleInfo>();
214 if (UseMBPI && OptLevel != CodeGenOpt::None)
215 AU.addRequired<BranchProbabilityInfo>();
216 MachineFunctionPass::getAnalysisUsage(AU);
219 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
220 /// may trap on it. In this case we have to split the edge so that the path
221 /// through the predecessor block that doesn't go to the phi block doesn't
222 /// execute the possibly trapping instruction.
224 /// This is required for correctness, so it must be done at -O0.
226 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
227 // Loop for blocks with phi nodes.
228 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
229 PHINode *PN = dyn_cast<PHINode>(BB->begin());
230 if (PN == 0) continue;
233 // For each block with a PHI node, check to see if any of the input values
234 // are potentially trapping constant expressions. Constant expressions are
235 // the only potentially trapping value that can occur as the argument to a
237 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
238 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
239 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
240 if (CE == 0 || !CE->canTrap()) continue;
242 // The only case we have to worry about is when the edge is critical.
243 // Since this block has a PHI Node, we assume it has multiple input
244 // edges: check to see if the pred has multiple successors.
245 BasicBlock *Pred = PN->getIncomingBlock(i);
246 if (Pred->getTerminator()->getNumSuccessors() == 1)
249 // Okay, we have to split this edge.
250 SplitCriticalEdge(Pred->getTerminator(),
251 GetSuccessorNumber(Pred, BB), SDISel, true);
257 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
258 // Do some sanity-checking on the command-line options.
259 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
260 "-fast-isel-verbose requires -fast-isel");
261 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
262 "-fast-isel-abort requires -fast-isel");
264 const Function &Fn = *mf.getFunction();
265 const TargetInstrInfo &TII = *TM.getInstrInfo();
266 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
269 RegInfo = &MF->getRegInfo();
270 AA = &getAnalysis<AliasAnalysis>();
271 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
273 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
275 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
278 FuncInfo->set(Fn, *MF);
280 if (UseMBPI && OptLevel != CodeGenOpt::None)
281 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
287 SelectAllBasicBlocks(Fn);
289 // If the first basic block in the function has live ins that need to be
290 // copied into vregs, emit the copies into the top of the block before
291 // emitting the code for the block.
292 MachineBasicBlock *EntryMBB = MF->begin();
293 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
295 DenseMap<unsigned, unsigned> LiveInMap;
296 if (!FuncInfo->ArgDbgValues.empty())
297 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
298 E = RegInfo->livein_end(); LI != E; ++LI)
300 LiveInMap.insert(std::make_pair(LI->first, LI->second));
302 // Insert DBG_VALUE instructions for function arguments to the entry block.
303 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
304 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
305 unsigned Reg = MI->getOperand(0).getReg();
306 if (TargetRegisterInfo::isPhysicalRegister(Reg))
307 EntryMBB->insert(EntryMBB->begin(), MI);
309 MachineInstr *Def = RegInfo->getVRegDef(Reg);
310 MachineBasicBlock::iterator InsertPos = Def;
311 // FIXME: VR def may not be in entry block.
312 Def->getParent()->insert(llvm::next(InsertPos), MI);
315 // If Reg is live-in then update debug info to track its copy in a vreg.
316 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
317 if (LDI != LiveInMap.end()) {
318 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
319 MachineBasicBlock::iterator InsertPos = Def;
320 const MDNode *Variable =
321 MI->getOperand(MI->getNumOperands()-1).getMetadata();
322 unsigned Offset = MI->getOperand(1).getImm();
323 // Def is never a terminator here, so it is ok to increment InsertPos.
324 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
325 TII.get(TargetOpcode::DBG_VALUE))
326 .addReg(LDI->second, RegState::Debug)
327 .addImm(Offset).addMetadata(Variable);
329 // If this vreg is directly copied into an exported register then
330 // that COPY instructions also need DBG_VALUE, if it is the only
331 // user of LDI->second.
332 MachineInstr *CopyUseMI = NULL;
333 for (MachineRegisterInfo::use_iterator
334 UI = RegInfo->use_begin(LDI->second);
335 MachineInstr *UseMI = UI.skipInstruction();) {
336 if (UseMI->isDebugValue()) continue;
337 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
338 CopyUseMI = UseMI; continue;
340 // Otherwise this is another use or second copy use.
341 CopyUseMI = NULL; break;
344 MachineInstr *NewMI =
345 BuildMI(*MF, CopyUseMI->getDebugLoc(),
346 TII.get(TargetOpcode::DBG_VALUE))
347 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
348 .addImm(Offset).addMetadata(Variable);
349 EntryMBB->insertAfter(CopyUseMI, NewMI);
354 // Determine if there are any calls in this machine function.
355 MachineFrameInfo *MFI = MF->getFrameInfo();
356 if (!MFI->hasCalls()) {
357 for (MachineFunction::const_iterator
358 I = MF->begin(), E = MF->end(); I != E; ++I) {
359 const MachineBasicBlock *MBB = I;
360 for (MachineBasicBlock::const_iterator
361 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
362 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
364 if ((MCID.isCall() && !MCID.isReturn()) ||
365 II->isStackAligningInlineAsm()) {
366 MFI->setHasCalls(true);
374 // Determine if there is a call to setjmp in the machine function.
375 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice());
377 // Replace forward-declared registers with the registers containing
378 // the desired value.
379 MachineRegisterInfo &MRI = MF->getRegInfo();
380 for (DenseMap<unsigned, unsigned>::iterator
381 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
383 unsigned From = I->first;
384 unsigned To = I->second;
385 // If To is also scheduled to be replaced, find what its ultimate
388 DenseMap<unsigned, unsigned>::iterator J =
389 FuncInfo->RegFixups.find(To);
394 MRI.replaceRegWith(From, To);
397 // Release function-specific state. SDB and CurDAG are already cleared
404 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
405 BasicBlock::const_iterator End,
407 // Lower all of the non-terminator instructions. If a call is emitted
408 // as a tail call, cease emitting nodes for this block. Terminators
409 // are handled below.
410 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
413 // Make sure the root of the DAG is up-to-date.
414 CurDAG->setRoot(SDB->getControlRoot());
415 HadTailCall = SDB->HasTailCall;
418 // Final step, emit the lowered DAG as machine code.
422 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
423 SmallPtrSet<SDNode*, 128> VisitedNodes;
424 SmallVector<SDNode*, 128> Worklist;
426 Worklist.push_back(CurDAG->getRoot().getNode());
433 SDNode *N = Worklist.pop_back_val();
435 // If we've already seen this node, ignore it.
436 if (!VisitedNodes.insert(N))
439 // Otherwise, add all chain operands to the worklist.
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 if (N->getOperand(i).getValueType() == MVT::Other)
442 Worklist.push_back(N->getOperand(i).getNode());
444 // If this is a CopyToReg with a vreg dest, process it.
445 if (N->getOpcode() != ISD::CopyToReg)
448 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
449 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
452 // Ignore non-scalar or non-integer values.
453 SDValue Src = N->getOperand(2);
454 EVT SrcVT = Src.getValueType();
455 if (!SrcVT.isInteger() || SrcVT.isVector())
458 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
459 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
460 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
461 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
462 } while (!Worklist.empty());
465 void SelectionDAGISel::CodeGenAndEmitDAG() {
466 std::string GroupName;
467 if (TimePassesIsEnabled)
468 GroupName = "Instruction Selection and Scheduling";
469 std::string BlockName;
470 int BlockNumber = -1;
473 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
474 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
478 BlockNumber = FuncInfo->MBB->getNumber();
479 BlockName = MF->getFunction()->getName().str() + ":" +
480 FuncInfo->MBB->getBasicBlock()->getName().str();
482 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
483 << " '" << BlockName << "'\n"; CurDAG->dump());
485 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
487 // Run the DAG combiner in pre-legalize mode.
489 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
490 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
493 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
494 << " '" << BlockName << "'\n"; CurDAG->dump());
496 // Second step, hack on the DAG until it only uses operations and types that
497 // the target supports.
498 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
503 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
504 Changed = CurDAG->LegalizeTypes();
507 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
508 << " '" << BlockName << "'\n"; CurDAG->dump());
511 if (ViewDAGCombineLT)
512 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
514 // Run the DAG combiner in post-type-legalize mode.
516 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
517 TimePassesIsEnabled);
518 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
521 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
522 << " '" << BlockName << "'\n"; CurDAG->dump());
526 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
527 Changed = CurDAG->LegalizeVectors();
532 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
533 CurDAG->LegalizeTypes();
536 if (ViewDAGCombineLT)
537 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
539 // Run the DAG combiner in post-type-legalize mode.
541 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
542 TimePassesIsEnabled);
543 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
546 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
547 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
550 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
553 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
557 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
558 << " '" << BlockName << "'\n"; CurDAG->dump());
560 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
562 // Run the DAG combiner in post-legalize mode.
564 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
565 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
568 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
569 << " '" << BlockName << "'\n"; CurDAG->dump());
571 if (OptLevel != CodeGenOpt::None)
572 ComputeLiveOutVRegInfo();
574 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
576 // Third, instruction select all of the operations to machine code, adding the
577 // code to the MachineBasicBlock.
579 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
580 DoInstructionSelection();
583 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
584 << " '" << BlockName << "'\n"; CurDAG->dump());
586 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
588 // Schedule machine code.
589 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
591 NamedRegionTimer T("Instruction Scheduling", GroupName,
592 TimePassesIsEnabled);
593 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
596 if (ViewSUnitDAGs) Scheduler->viewGraph();
598 // Emit machine code to BB. This can change 'BB' to the last block being
600 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
602 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
604 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
605 FuncInfo->InsertPt = Scheduler->InsertPos;
608 // If the block was split, make sure we update any references that are used to
609 // update PHI nodes later on.
610 if (FirstMBB != LastMBB)
611 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
613 // Free the scheduler state.
615 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
616 TimePassesIsEnabled);
620 // Free the SelectionDAG state, now that we're finished with it.
624 void SelectionDAGISel::DoInstructionSelection() {
625 DEBUG(errs() << "===== Instruction selection begins: BB#"
626 << FuncInfo->MBB->getNumber()
627 << " '" << FuncInfo->MBB->getName() << "'\n");
631 // Select target instructions for the DAG.
633 // Number all nodes with a topological order and set DAGSize.
634 DAGSize = CurDAG->AssignTopologicalOrder();
636 // Create a dummy node (which is not added to allnodes), that adds
637 // a reference to the root node, preventing it from being deleted,
638 // and tracking any changes of the root.
639 HandleSDNode Dummy(CurDAG->getRoot());
640 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
643 // The AllNodes list is now topological-sorted. Visit the
644 // nodes by starting at the end of the list (the root of the
645 // graph) and preceding back toward the beginning (the entry
647 while (ISelPosition != CurDAG->allnodes_begin()) {
648 SDNode *Node = --ISelPosition;
649 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
650 // but there are currently some corner cases that it misses. Also, this
651 // makes it theoretically possible to disable the DAGCombiner.
652 if (Node->use_empty())
655 SDNode *ResNode = Select(Node);
657 // FIXME: This is pretty gross. 'Select' should be changed to not return
658 // anything at all and this code should be nuked with a tactical strike.
660 // If node should not be replaced, continue with the next one.
661 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
665 ReplaceUses(Node, ResNode);
667 // If after the replacement this node is not used any more,
668 // remove this dead node.
669 if (Node->use_empty()) { // Don't delete EntryToken, etc.
670 ISelUpdater ISU(ISelPosition);
671 CurDAG->RemoveDeadNode(Node, &ISU);
675 CurDAG->setRoot(Dummy.getValue());
678 DEBUG(errs() << "===== Instruction selection ends:\n");
680 PostprocessISelDAG();
683 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
684 /// do other setup for EH landing-pad blocks.
685 void SelectionDAGISel::PrepareEHLandingPad() {
686 MachineBasicBlock *MBB = FuncInfo->MBB;
688 // Add a label to mark the beginning of the landing pad. Deletion of the
689 // landing pad can thus be detected via the MachineModuleInfo.
690 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
692 // Assign the call site to the landing pad's begin label.
693 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
695 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
696 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
699 // Mark exception register as live in.
700 unsigned Reg = TLI.getExceptionAddressRegister();
701 if (Reg) MBB->addLiveIn(Reg);
703 // Mark exception selector register as live in.
704 Reg = TLI.getExceptionSelectorRegister();
705 if (Reg) MBB->addLiveIn(Reg);
707 // FIXME: Hack around an exception handling flaw (PR1508): the personality
708 // function and list of typeids logically belong to the invoke (or, if you
709 // like, the basic block containing the invoke), and need to be associated
710 // with it in the dwarf exception handling tables. Currently however the
711 // information is provided by an intrinsic (eh.selector) that can be moved
712 // to unexpected places by the optimizers: if the unwind edge is critical,
713 // then breaking it can result in the intrinsics being in the successor of
714 // the landing pad, not the landing pad itself. This results
715 // in exceptions not being caught because no typeids are associated with
716 // the invoke. This may not be the only way things can go wrong, but it
717 // is the only way we try to work around for the moment.
718 const BasicBlock *LLVMBB = MBB->getBasicBlock();
719 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
721 if (Br && Br->isUnconditional()) { // Critical edge?
722 BasicBlock::const_iterator I, E;
723 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
724 if (isa<EHSelectorInst>(I))
728 // No catch info found - try to extract some from the successor.
729 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
733 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
734 /// load into the specified FoldInst. Note that we could have a sequence where
735 /// multiple LLVM IR instructions are folded into the same machineinstr. For
736 /// example we could have:
737 /// A: x = load i32 *P
738 /// B: y = icmp A, 42
741 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
742 /// any other folded instructions) because it is between A and C.
744 /// If we succeed in folding the load into the operation, return true.
746 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
747 const Instruction *FoldInst,
749 // We know that the load has a single use, but don't know what it is. If it
750 // isn't one of the folded instructions, then we can't succeed here. Handle
751 // this by scanning the single-use users of the load until we get to FoldInst.
752 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
754 const Instruction *TheUser = LI->use_back();
755 while (TheUser != FoldInst && // Scan up until we find FoldInst.
756 // Stay in the right block.
757 TheUser->getParent() == FoldInst->getParent() &&
758 --MaxUsers) { // Don't scan too far.
759 // If there are multiple or no uses of this instruction, then bail out.
760 if (!TheUser->hasOneUse())
763 TheUser = TheUser->use_back();
766 // If we didn't find the fold instruction, then we failed to collapse the
768 if (TheUser != FoldInst)
771 // Don't try to fold volatile loads. Target has to deal with alignment
773 if (LI->isVolatile()) return false;
775 // Figure out which vreg this is going into. If there is no assigned vreg yet
776 // then there actually was no reference to it. Perhaps the load is referenced
777 // by a dead instruction.
778 unsigned LoadReg = FastIS->getRegForValue(LI);
782 // Check to see what the uses of this vreg are. If it has no uses, or more
783 // than one use (at the machine instr level) then we can't fold it.
784 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
785 if (RI == RegInfo->reg_end())
788 // See if there is exactly one use of the vreg. If there are multiple uses,
789 // then the instruction got lowered to multiple machine instructions or the
790 // use of the loaded value ended up being multiple operands of the result, in
791 // either case, we can't fold this.
792 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
793 if (PostRI != RegInfo->reg_end())
796 assert(RI.getOperand().isUse() &&
797 "The only use of the vreg must be a use, we haven't emitted the def!");
799 MachineInstr *User = &*RI;
801 // Set the insertion point properly. Folding the load can cause generation of
802 // other random instructions (like sign extends) for addressing modes, make
803 // sure they get inserted in a logical place before the new instruction.
804 FuncInfo->InsertPt = User;
805 FuncInfo->MBB = User->getParent();
807 // Ask the target to try folding the load.
808 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
811 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
812 /// side-effect free and is either dead or folded into a generated instruction.
813 /// Return false if it needs to be emitted.
814 static bool isFoldedOrDeadInstruction(const Instruction *I,
815 FunctionLoweringInfo *FuncInfo) {
816 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
817 !isa<TerminatorInst>(I) && // Terminators aren't folded.
818 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
819 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
820 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
823 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
824 // Initialize the Fast-ISel state, if needed.
825 FastISel *FastIS = 0;
826 if (TM.Options.EnableFastISel)
827 FastIS = TLI.createFastISel(*FuncInfo);
829 // Iterate over all basic blocks in the function.
830 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
831 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
832 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
833 const BasicBlock *LLVMBB = *I;
835 if (OptLevel != CodeGenOpt::None) {
836 bool AllPredsVisited = true;
837 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
839 if (!FuncInfo->VisitedBBs.count(*PI)) {
840 AllPredsVisited = false;
845 if (AllPredsVisited) {
846 for (BasicBlock::const_iterator I = LLVMBB->begin();
847 isa<PHINode>(I); ++I)
848 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
850 for (BasicBlock::const_iterator I = LLVMBB->begin();
851 isa<PHINode>(I); ++I)
852 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
855 FuncInfo->VisitedBBs.insert(LLVMBB);
858 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
859 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
861 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
862 BasicBlock::const_iterator const End = LLVMBB->end();
863 BasicBlock::const_iterator BI = End;
865 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
867 // Setup an EH landing-pad block.
868 if (FuncInfo->MBB->isLandingPad())
869 PrepareEHLandingPad();
871 // Lower any arguments needed in this block if this is the entry block.
872 if (LLVMBB == &Fn.getEntryBlock())
873 LowerArguments(LLVMBB);
875 // Before doing SelectionDAG ISel, see if FastISel has been requested.
877 FastIS->startNewBlock();
879 // Emit code for any incoming arguments. This must happen before
880 // beginning FastISel on the entry block.
881 if (LLVMBB == &Fn.getEntryBlock()) {
882 CurDAG->setRoot(SDB->getControlRoot());
886 // If we inserted any instructions at the beginning, make a note of
887 // where they are, so we can be sure to emit subsequent instructions
889 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
890 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
892 FastIS->setLastLocalValue(0);
895 unsigned NumFastIselRemaining = std::distance(Begin, End);
896 // Do FastISel on as many instructions as possible.
897 for (; BI != Begin; --BI) {
898 const Instruction *Inst = llvm::prior(BI);
900 // If we no longer require this instruction, skip it.
901 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
902 --NumFastIselRemaining;
906 // Bottom-up: reset the insert pos at the top, after any local-value
908 FastIS->recomputeInsertPt();
910 // Try to select the instruction with FastISel.
911 if (FastIS->SelectInstruction(Inst)) {
912 --NumFastIselRemaining;
913 ++NumFastIselSuccess;
914 // If fast isel succeeded, skip over all the folded instructions, and
915 // then see if there is a load right before the selected instructions.
916 // Try to fold the load if so.
917 const Instruction *BeforeInst = Inst;
918 while (BeforeInst != Begin) {
919 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
920 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
923 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
924 BeforeInst->hasOneUse() &&
925 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
926 // If we succeeded, don't re-select the load.
927 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
928 --NumFastIselRemaining;
929 ++NumFastIselSuccess;
934 // Then handle certain instructions as single-LLVM-Instruction blocks.
935 if (isa<CallInst>(Inst)) {
937 if (EnableFastISelVerbose || EnableFastISelAbort) {
938 dbgs() << "FastISel missed call: ";
942 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
943 unsigned &R = FuncInfo->ValueMap[Inst];
945 R = FuncInfo->CreateRegs(Inst->getType());
948 bool HadTailCall = false;
949 SelectBasicBlock(Inst, BI, HadTailCall);
951 // Recompute NumFastIselRemaining as Selection DAG instruction
952 // selection may have handled the call, input args, etc.
953 unsigned RemainingNow = std::distance(Begin, BI);
954 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
956 // If the call was emitted as a tail call, we're done with the block.
962 NumFastIselRemaining = RemainingNow;
966 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
967 // Don't abort, and use a different message for terminator misses.
968 NumFastIselFailures += NumFastIselRemaining;
969 if (EnableFastISelVerbose || EnableFastISelAbort) {
970 dbgs() << "FastISel missed terminator: ";
974 NumFastIselFailures += NumFastIselRemaining;
975 if (EnableFastISelVerbose || EnableFastISelAbort) {
976 dbgs() << "FastISel miss: ";
979 if (EnableFastISelAbort)
980 // The "fast" selector couldn't handle something and bailed.
981 // For the purpose of debugging, just abort.
982 llvm_unreachable("FastISel didn't select the entire block");
987 FastIS->recomputeInsertPt();
996 // Run SelectionDAG instruction selection on the remainder of the block
997 // not handled by FastISel. If FastISel is not run, this is the entire
1000 SelectBasicBlock(Begin, BI, HadTailCall);
1004 FuncInfo->PHINodesToUpdate.clear();
1008 SDB->clearDanglingDebugInfo();
1012 SelectionDAGISel::FinishBasicBlock() {
1014 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1015 << FuncInfo->PHINodesToUpdate.size() << "\n";
1016 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1017 dbgs() << "Node " << i << " : ("
1018 << FuncInfo->PHINodesToUpdate[i].first
1019 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1021 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1022 // PHI nodes in successors.
1023 if (SDB->SwitchCases.empty() &&
1024 SDB->JTCases.empty() &&
1025 SDB->BitTestCases.empty()) {
1026 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1027 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1028 assert(PHI->isPHI() &&
1029 "This is not a machine PHI node that we are updating!");
1030 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1033 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1034 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1039 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1040 // Lower header first, if it wasn't already lowered
1041 if (!SDB->BitTestCases[i].Emitted) {
1042 // Set the current basic block to the mbb we wish to insert the code into
1043 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1044 FuncInfo->InsertPt = FuncInfo->MBB->end();
1046 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1047 CurDAG->setRoot(SDB->getRoot());
1049 CodeGenAndEmitDAG();
1052 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1053 // Set the current basic block to the mbb we wish to insert the code into
1054 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1055 FuncInfo->InsertPt = FuncInfo->MBB->end();
1058 SDB->visitBitTestCase(SDB->BitTestCases[i],
1059 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1060 SDB->BitTestCases[i].Reg,
1061 SDB->BitTestCases[i].Cases[j],
1064 SDB->visitBitTestCase(SDB->BitTestCases[i],
1065 SDB->BitTestCases[i].Default,
1066 SDB->BitTestCases[i].Reg,
1067 SDB->BitTestCases[i].Cases[j],
1071 CurDAG->setRoot(SDB->getRoot());
1073 CodeGenAndEmitDAG();
1077 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1079 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1080 MachineBasicBlock *PHIBB = PHI->getParent();
1081 assert(PHI->isPHI() &&
1082 "This is not a machine PHI node that we are updating!");
1083 // This is "default" BB. We have two jumps to it. From "header" BB and
1084 // from last "case" BB.
1085 if (PHIBB == SDB->BitTestCases[i].Default) {
1086 PHI->addOperand(MachineOperand::
1087 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1089 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1090 PHI->addOperand(MachineOperand::
1091 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1093 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1096 // One of "cases" BB.
1097 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1099 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1100 if (cBB->isSuccessor(PHIBB)) {
1101 PHI->addOperand(MachineOperand::
1102 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1104 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1109 SDB->BitTestCases.clear();
1111 // If the JumpTable record is filled in, then we need to emit a jump table.
1112 // Updating the PHI nodes is tricky in this case, since we need to determine
1113 // whether the PHI is a successor of the range check MBB or the jump table MBB
1114 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1115 // Lower header first, if it wasn't already lowered
1116 if (!SDB->JTCases[i].first.Emitted) {
1117 // Set the current basic block to the mbb we wish to insert the code into
1118 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1119 FuncInfo->InsertPt = FuncInfo->MBB->end();
1121 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1123 CurDAG->setRoot(SDB->getRoot());
1125 CodeGenAndEmitDAG();
1128 // Set the current basic block to the mbb we wish to insert the code into
1129 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1130 FuncInfo->InsertPt = FuncInfo->MBB->end();
1132 SDB->visitJumpTable(SDB->JTCases[i].second);
1133 CurDAG->setRoot(SDB->getRoot());
1135 CodeGenAndEmitDAG();
1138 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1140 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1141 MachineBasicBlock *PHIBB = PHI->getParent();
1142 assert(PHI->isPHI() &&
1143 "This is not a machine PHI node that we are updating!");
1144 // "default" BB. We can go there only from header BB.
1145 if (PHIBB == SDB->JTCases[i].second.Default) {
1147 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1150 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1152 // JT BB. Just iterate over successors here
1153 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1155 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1157 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1161 SDB->JTCases.clear();
1163 // If the switch block involved a branch to one of the actual successors, we
1164 // need to update PHI nodes in that block.
1165 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1166 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1167 assert(PHI->isPHI() &&
1168 "This is not a machine PHI node that we are updating!");
1169 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1171 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1172 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1176 // If we generated any switch lowering information, build and codegen any
1177 // additional DAGs necessary.
1178 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1179 // Set the current basic block to the mbb we wish to insert the code into
1180 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1181 FuncInfo->InsertPt = FuncInfo->MBB->end();
1183 // Determine the unique successors.
1184 SmallVector<MachineBasicBlock *, 2> Succs;
1185 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1186 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1187 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1189 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1190 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1191 CurDAG->setRoot(SDB->getRoot());
1193 CodeGenAndEmitDAG();
1195 // Remember the last block, now that any splitting is done, for use in
1196 // populating PHI nodes in successors.
1197 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1199 // Handle any PHI nodes in successors of this chunk, as if we were coming
1200 // from the original BB before switch expansion. Note that PHI nodes can
1201 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1202 // handle them the right number of times.
1203 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1204 FuncInfo->MBB = Succs[i];
1205 FuncInfo->InsertPt = FuncInfo->MBB->end();
1206 // FuncInfo->MBB may have been removed from the CFG if a branch was
1208 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1209 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1210 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1212 // This value for this PHI node is recorded in PHINodesToUpdate.
1213 for (unsigned pn = 0; ; ++pn) {
1214 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1215 "Didn't find PHI entry!");
1216 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1217 Phi->addOperand(MachineOperand::
1218 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1220 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1228 SDB->SwitchCases.clear();
1232 /// Create the scheduler. If a specific scheduler was specified
1233 /// via the SchedulerRegistry, use it, otherwise select the
1234 /// one preferred by the target.
1236 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1237 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1241 RegisterScheduler::setDefault(Ctor);
1244 return Ctor(this, OptLevel);
1247 //===----------------------------------------------------------------------===//
1248 // Helper functions used by the generated instruction selector.
1249 //===----------------------------------------------------------------------===//
1250 // Calls to these methods are generated by tblgen.
1252 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1253 /// the dag combiner simplified the 255, we still want to match. RHS is the
1254 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1255 /// specified in the .td file (e.g. 255).
1256 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1257 int64_t DesiredMaskS) const {
1258 const APInt &ActualMask = RHS->getAPIntValue();
1259 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1261 // If the actual mask exactly matches, success!
1262 if (ActualMask == DesiredMask)
1265 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1266 if (ActualMask.intersects(~DesiredMask))
1269 // Otherwise, the DAG Combiner may have proven that the value coming in is
1270 // either already zero or is not demanded. Check for known zero input bits.
1271 APInt NeededMask = DesiredMask & ~ActualMask;
1272 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1275 // TODO: check to see if missing bits are just not demanded.
1277 // Otherwise, this pattern doesn't match.
1281 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1282 /// the dag combiner simplified the 255, we still want to match. RHS is the
1283 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1284 /// specified in the .td file (e.g. 255).
1285 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1286 int64_t DesiredMaskS) const {
1287 const APInt &ActualMask = RHS->getAPIntValue();
1288 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1290 // If the actual mask exactly matches, success!
1291 if (ActualMask == DesiredMask)
1294 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1295 if (ActualMask.intersects(~DesiredMask))
1298 // Otherwise, the DAG Combiner may have proven that the value coming in is
1299 // either already zero or is not demanded. Check for known zero input bits.
1300 APInt NeededMask = DesiredMask & ~ActualMask;
1302 APInt KnownZero, KnownOne;
1303 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1305 // If all the missing bits in the or are already known to be set, match!
1306 if ((NeededMask & KnownOne) == NeededMask)
1309 // TODO: check to see if missing bits are just not demanded.
1311 // Otherwise, this pattern doesn't match.
1316 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1317 /// by tblgen. Others should not call it.
1318 void SelectionDAGISel::
1319 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1320 std::vector<SDValue> InOps;
1321 std::swap(InOps, Ops);
1323 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1324 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1325 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1326 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1328 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1329 if (InOps[e-1].getValueType() == MVT::Glue)
1330 --e; // Don't process a glue operand if it is here.
1333 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1334 if (!InlineAsm::isMemKind(Flags)) {
1335 // Just skip over this operand, copying the operands verbatim.
1336 Ops.insert(Ops.end(), InOps.begin()+i,
1337 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1338 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1340 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1341 "Memory operand with multiple values?");
1342 // Otherwise, this is a memory operand. Ask the target to select it.
1343 std::vector<SDValue> SelOps;
1344 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1345 report_fatal_error("Could not match memory address. Inline asm"
1348 // Add this to the output node.
1350 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1351 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1352 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1357 // Add the glue input back if present.
1358 if (e != InOps.size())
1359 Ops.push_back(InOps.back());
1362 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1365 static SDNode *findGlueUse(SDNode *N) {
1366 unsigned FlagResNo = N->getNumValues()-1;
1367 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1368 SDUse &Use = I.getUse();
1369 if (Use.getResNo() == FlagResNo)
1370 return Use.getUser();
1375 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1376 /// This function recursively traverses up the operand chain, ignoring
1378 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1379 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1380 bool IgnoreChains) {
1381 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1382 // greater than all of its (recursive) operands. If we scan to a point where
1383 // 'use' is smaller than the node we're scanning for, then we know we will
1386 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1387 // happen because we scan down to newly selected nodes in the case of glue
1389 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1392 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1393 // won't fail if we scan it again.
1394 if (!Visited.insert(Use))
1397 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1398 // Ignore chain uses, they are validated by HandleMergeInputChains.
1399 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1402 SDNode *N = Use->getOperand(i).getNode();
1404 if (Use == ImmedUse || Use == Root)
1405 continue; // We are not looking for immediate use.
1410 // Traverse up the operand chain.
1411 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1417 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1418 /// operand node N of U during instruction selection that starts at Root.
1419 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1420 SDNode *Root) const {
1421 if (OptLevel == CodeGenOpt::None) return false;
1422 return N.hasOneUse();
1425 /// IsLegalToFold - Returns true if the specific operand node N of
1426 /// U can be folded during instruction selection that starts at Root.
1427 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1428 CodeGenOpt::Level OptLevel,
1429 bool IgnoreChains) {
1430 if (OptLevel == CodeGenOpt::None) return false;
1432 // If Root use can somehow reach N through a path that that doesn't contain
1433 // U then folding N would create a cycle. e.g. In the following
1434 // diagram, Root can reach N through X. If N is folded into into Root, then
1435 // X is both a predecessor and a successor of U.
1446 // * indicates nodes to be folded together.
1448 // If Root produces glue, then it gets (even more) interesting. Since it
1449 // will be "glued" together with its glue use in the scheduler, we need to
1450 // check if it might reach N.
1469 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1470 // (call it Fold), then X is a predecessor of GU and a successor of
1471 // Fold. But since Fold and GU are glued together, this will create
1472 // a cycle in the scheduling graph.
1474 // If the node has glue, walk down the graph to the "lowest" node in the
1476 EVT VT = Root->getValueType(Root->getNumValues()-1);
1477 while (VT == MVT::Glue) {
1478 SDNode *GU = findGlueUse(Root);
1482 VT = Root->getValueType(Root->getNumValues()-1);
1484 // If our query node has a glue result with a use, we've walked up it. If
1485 // the user (which has already been selected) has a chain or indirectly uses
1486 // the chain, our WalkChainUsers predicate will not consider it. Because of
1487 // this, we cannot ignore chains in this predicate.
1488 IgnoreChains = false;
1492 SmallPtrSet<SDNode*, 16> Visited;
1493 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1496 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1497 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1498 SelectInlineAsmMemoryOperands(Ops);
1500 std::vector<EVT> VTs;
1501 VTs.push_back(MVT::Other);
1502 VTs.push_back(MVT::Glue);
1503 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1504 VTs, &Ops[0], Ops.size());
1506 return New.getNode();
1509 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1510 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1513 /// GetVBR - decode a vbr encoding whose top bit is set.
1514 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1515 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1516 assert(Val >= 128 && "Not a VBR");
1517 Val &= 127; // Remove first vbr bit.
1522 NextBits = MatcherTable[Idx++];
1523 Val |= (NextBits&127) << Shift;
1525 } while (NextBits & 128);
1531 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1532 /// interior glue and chain results to use the new glue and chain results.
1533 void SelectionDAGISel::
1534 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1535 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1537 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1538 bool isMorphNodeTo) {
1539 SmallVector<SDNode*, 4> NowDeadNodes;
1541 ISelUpdater ISU(ISelPosition);
1543 // Now that all the normal results are replaced, we replace the chain and
1544 // glue results if present.
1545 if (!ChainNodesMatched.empty()) {
1546 assert(InputChain.getNode() != 0 &&
1547 "Matched input chains but didn't produce a chain");
1548 // Loop over all of the nodes we matched that produced a chain result.
1549 // Replace all the chain results with the final chain we ended up with.
1550 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1551 SDNode *ChainNode = ChainNodesMatched[i];
1553 // If this node was already deleted, don't look at it.
1554 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1557 // Don't replace the results of the root node if we're doing a
1559 if (ChainNode == NodeToMatch && isMorphNodeTo)
1562 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1563 if (ChainVal.getValueType() == MVT::Glue)
1564 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1565 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1566 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1568 // If the node became dead and we haven't already seen it, delete it.
1569 if (ChainNode->use_empty() &&
1570 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1571 NowDeadNodes.push_back(ChainNode);
1575 // If the result produces glue, update any glue results in the matched
1576 // pattern with the glue result.
1577 if (InputGlue.getNode() != 0) {
1578 // Handle any interior nodes explicitly marked.
1579 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1580 SDNode *FRN = GlueResultNodesMatched[i];
1582 // If this node was already deleted, don't look at it.
1583 if (FRN->getOpcode() == ISD::DELETED_NODE)
1586 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1587 "Doesn't have a glue result");
1588 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1591 // If the node became dead and we haven't already seen it, delete it.
1592 if (FRN->use_empty() &&
1593 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1594 NowDeadNodes.push_back(FRN);
1598 if (!NowDeadNodes.empty())
1599 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1601 DEBUG(errs() << "ISEL: Match complete!\n");
1607 CR_LeadsToInteriorNode
1610 /// WalkChainUsers - Walk down the users of the specified chained node that is
1611 /// part of the pattern we're matching, looking at all of the users we find.
1612 /// This determines whether something is an interior node, whether we have a
1613 /// non-pattern node in between two pattern nodes (which prevent folding because
1614 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1615 /// between pattern nodes (in which case the TF becomes part of the pattern).
1617 /// The walk we do here is guaranteed to be small because we quickly get down to
1618 /// already selected nodes "below" us.
1620 WalkChainUsers(SDNode *ChainedNode,
1621 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1622 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1623 ChainResult Result = CR_Simple;
1625 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1626 E = ChainedNode->use_end(); UI != E; ++UI) {
1627 // Make sure the use is of the chain, not some other value we produce.
1628 if (UI.getUse().getValueType() != MVT::Other) continue;
1632 // If we see an already-selected machine node, then we've gone beyond the
1633 // pattern that we're selecting down into the already selected chunk of the
1635 if (User->isMachineOpcode() ||
1636 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1639 if (User->getOpcode() == ISD::CopyToReg ||
1640 User->getOpcode() == ISD::CopyFromReg ||
1641 User->getOpcode() == ISD::INLINEASM ||
1642 User->getOpcode() == ISD::EH_LABEL) {
1643 // If their node ID got reset to -1 then they've already been selected.
1644 // Treat them like a MachineOpcode.
1645 if (User->getNodeId() == -1)
1649 // If we have a TokenFactor, we handle it specially.
1650 if (User->getOpcode() != ISD::TokenFactor) {
1651 // If the node isn't a token factor and isn't part of our pattern, then it
1652 // must be a random chained node in between two nodes we're selecting.
1653 // This happens when we have something like:
1658 // Because we structurally match the load/store as a read/modify/write,
1659 // but the call is chained between them. We cannot fold in this case
1660 // because it would induce a cycle in the graph.
1661 if (!std::count(ChainedNodesInPattern.begin(),
1662 ChainedNodesInPattern.end(), User))
1663 return CR_InducesCycle;
1665 // Otherwise we found a node that is part of our pattern. For example in:
1669 // This would happen when we're scanning down from the load and see the
1670 // store as a user. Record that there is a use of ChainedNode that is
1671 // part of the pattern and keep scanning uses.
1672 Result = CR_LeadsToInteriorNode;
1673 InteriorChainedNodes.push_back(User);
1677 // If we found a TokenFactor, there are two cases to consider: first if the
1678 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1679 // uses of the TF are in our pattern) we just want to ignore it. Second,
1680 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1686 // | \ DAG's like cheese
1689 // [TokenFactor] [Op]
1696 // In this case, the TokenFactor becomes part of our match and we rewrite it
1697 // as a new TokenFactor.
1699 // To distinguish these two cases, do a recursive walk down the uses.
1700 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1702 // If the uses of the TokenFactor are just already-selected nodes, ignore
1703 // it, it is "below" our pattern.
1705 case CR_InducesCycle:
1706 // If the uses of the TokenFactor lead to nodes that are not part of our
1707 // pattern that are not selected, folding would turn this into a cycle,
1709 return CR_InducesCycle;
1710 case CR_LeadsToInteriorNode:
1711 break; // Otherwise, keep processing.
1714 // Okay, we know we're in the interesting interior case. The TokenFactor
1715 // is now going to be considered part of the pattern so that we rewrite its
1716 // uses (it may have uses that are not part of the pattern) with the
1717 // ultimate chain result of the generated code. We will also add its chain
1718 // inputs as inputs to the ultimate TokenFactor we create.
1719 Result = CR_LeadsToInteriorNode;
1720 ChainedNodesInPattern.push_back(User);
1721 InteriorChainedNodes.push_back(User);
1728 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1729 /// operation for when the pattern matched at least one node with a chains. The
1730 /// input vector contains a list of all of the chained nodes that we match. We
1731 /// must determine if this is a valid thing to cover (i.e. matching it won't
1732 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1733 /// be used as the input node chain for the generated nodes.
1735 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1736 SelectionDAG *CurDAG) {
1737 // Walk all of the chained nodes we've matched, recursively scanning down the
1738 // users of the chain result. This adds any TokenFactor nodes that are caught
1739 // in between chained nodes to the chained and interior nodes list.
1740 SmallVector<SDNode*, 3> InteriorChainedNodes;
1741 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1742 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1743 InteriorChainedNodes) == CR_InducesCycle)
1744 return SDValue(); // Would induce a cycle.
1747 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1748 // that we are interested in. Form our input TokenFactor node.
1749 SmallVector<SDValue, 3> InputChains;
1750 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1751 // Add the input chain of this node to the InputChains list (which will be
1752 // the operands of the generated TokenFactor) if it's not an interior node.
1753 SDNode *N = ChainNodesMatched[i];
1754 if (N->getOpcode() != ISD::TokenFactor) {
1755 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1758 // Otherwise, add the input chain.
1759 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1760 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1761 InputChains.push_back(InChain);
1765 // If we have a token factor, we want to add all inputs of the token factor
1766 // that are not part of the pattern we're matching.
1767 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1768 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1769 N->getOperand(op).getNode()))
1770 InputChains.push_back(N->getOperand(op));
1775 if (InputChains.size() == 1)
1776 return InputChains[0];
1777 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1778 MVT::Other, &InputChains[0], InputChains.size());
1781 /// MorphNode - Handle morphing a node in place for the selector.
1782 SDNode *SelectionDAGISel::
1783 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1784 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1785 // It is possible we're using MorphNodeTo to replace a node with no
1786 // normal results with one that has a normal result (or we could be
1787 // adding a chain) and the input could have glue and chains as well.
1788 // In this case we need to shift the operands down.
1789 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1790 // than the old isel though.
1791 int OldGlueResultNo = -1, OldChainResultNo = -1;
1793 unsigned NTMNumResults = Node->getNumValues();
1794 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1795 OldGlueResultNo = NTMNumResults-1;
1796 if (NTMNumResults != 1 &&
1797 Node->getValueType(NTMNumResults-2) == MVT::Other)
1798 OldChainResultNo = NTMNumResults-2;
1799 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1800 OldChainResultNo = NTMNumResults-1;
1802 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1803 // that this deletes operands of the old node that become dead.
1804 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1806 // MorphNodeTo can operate in two ways: if an existing node with the
1807 // specified operands exists, it can just return it. Otherwise, it
1808 // updates the node in place to have the requested operands.
1810 // If we updated the node in place, reset the node ID. To the isel,
1811 // this should be just like a newly allocated machine node.
1815 unsigned ResNumResults = Res->getNumValues();
1816 // Move the glue if needed.
1817 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1818 (unsigned)OldGlueResultNo != ResNumResults-1)
1819 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1820 SDValue(Res, ResNumResults-1));
1822 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1825 // Move the chain reference if needed.
1826 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1827 (unsigned)OldChainResultNo != ResNumResults-1)
1828 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1829 SDValue(Res, ResNumResults-1));
1831 // Otherwise, no replacement happened because the node already exists. Replace
1832 // Uses of the old node with the new one.
1834 CurDAG->ReplaceAllUsesWith(Node, Res);
1839 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1840 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1841 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1843 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1844 // Accept if it is exactly the same as a previously recorded node.
1845 unsigned RecNo = MatcherTable[MatcherIndex++];
1846 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1847 return N == RecordedNodes[RecNo].first;
1850 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1851 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1852 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1853 SelectionDAGISel &SDISel) {
1854 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1857 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1858 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1859 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1860 SelectionDAGISel &SDISel, SDNode *N) {
1861 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1864 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1865 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1867 uint16_t Opc = MatcherTable[MatcherIndex++];
1868 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1869 return N->getOpcode() == Opc;
1872 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1873 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1874 SDValue N, const TargetLowering &TLI) {
1875 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1876 if (N.getValueType() == VT) return true;
1878 // Handle the case when VT is iPTR.
1879 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1882 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1883 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1884 SDValue N, const TargetLowering &TLI,
1886 if (ChildNo >= N.getNumOperands())
1887 return false; // Match fails if out of range child #.
1888 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1892 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1893 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1895 return cast<CondCodeSDNode>(N)->get() ==
1896 (ISD::CondCode)MatcherTable[MatcherIndex++];
1899 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1900 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1901 SDValue N, const TargetLowering &TLI) {
1902 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1903 if (cast<VTSDNode>(N)->getVT() == VT)
1906 // Handle the case when VT is iPTR.
1907 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1910 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1911 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1913 int64_t Val = MatcherTable[MatcherIndex++];
1915 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1918 return C != 0 && C->getSExtValue() == Val;
1921 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1922 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1923 SDValue N, SelectionDAGISel &SDISel) {
1924 int64_t Val = MatcherTable[MatcherIndex++];
1926 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1928 if (N->getOpcode() != ISD::AND) return false;
1930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1931 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1934 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1935 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1936 SDValue N, SelectionDAGISel &SDISel) {
1937 int64_t Val = MatcherTable[MatcherIndex++];
1939 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1941 if (N->getOpcode() != ISD::OR) return false;
1943 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1944 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1947 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1948 /// scope, evaluate the current node. If the current predicate is known to
1949 /// fail, set Result=true and return anything. If the current predicate is
1950 /// known to pass, set Result=false and return the MatcherIndex to continue
1951 /// with. If the current predicate is unknown, set Result=false and return the
1952 /// MatcherIndex to continue with.
1953 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1954 unsigned Index, SDValue N,
1955 bool &Result, SelectionDAGISel &SDISel,
1956 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1957 switch (Table[Index++]) {
1960 return Index-1; // Could not evaluate this predicate.
1961 case SelectionDAGISel::OPC_CheckSame:
1962 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1964 case SelectionDAGISel::OPC_CheckPatternPredicate:
1965 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1967 case SelectionDAGISel::OPC_CheckPredicate:
1968 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1970 case SelectionDAGISel::OPC_CheckOpcode:
1971 Result = !::CheckOpcode(Table, Index, N.getNode());
1973 case SelectionDAGISel::OPC_CheckType:
1974 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1976 case SelectionDAGISel::OPC_CheckChild0Type:
1977 case SelectionDAGISel::OPC_CheckChild1Type:
1978 case SelectionDAGISel::OPC_CheckChild2Type:
1979 case SelectionDAGISel::OPC_CheckChild3Type:
1980 case SelectionDAGISel::OPC_CheckChild4Type:
1981 case SelectionDAGISel::OPC_CheckChild5Type:
1982 case SelectionDAGISel::OPC_CheckChild6Type:
1983 case SelectionDAGISel::OPC_CheckChild7Type:
1984 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1985 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1987 case SelectionDAGISel::OPC_CheckCondCode:
1988 Result = !::CheckCondCode(Table, Index, N);
1990 case SelectionDAGISel::OPC_CheckValueType:
1991 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1993 case SelectionDAGISel::OPC_CheckInteger:
1994 Result = !::CheckInteger(Table, Index, N);
1996 case SelectionDAGISel::OPC_CheckAndImm:
1997 Result = !::CheckAndImm(Table, Index, N, SDISel);
1999 case SelectionDAGISel::OPC_CheckOrImm:
2000 Result = !::CheckOrImm(Table, Index, N, SDISel);
2008 /// FailIndex - If this match fails, this is the index to continue with.
2011 /// NodeStack - The node stack when the scope was formed.
2012 SmallVector<SDValue, 4> NodeStack;
2014 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2015 unsigned NumRecordedNodes;
2017 /// NumMatchedMemRefs - The number of matched memref entries.
2018 unsigned NumMatchedMemRefs;
2020 /// InputChain/InputGlue - The current chain/glue
2021 SDValue InputChain, InputGlue;
2023 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2024 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2029 SDNode *SelectionDAGISel::
2030 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2031 unsigned TableSize) {
2032 // FIXME: Should these even be selected? Handle these cases in the caller?
2033 switch (NodeToMatch->getOpcode()) {
2036 case ISD::EntryToken: // These nodes remain the same.
2037 case ISD::BasicBlock:
2039 //case ISD::VALUETYPE:
2040 //case ISD::CONDCODE:
2041 case ISD::HANDLENODE:
2042 case ISD::MDNODE_SDNODE:
2043 case ISD::TargetConstant:
2044 case ISD::TargetConstantFP:
2045 case ISD::TargetConstantPool:
2046 case ISD::TargetFrameIndex:
2047 case ISD::TargetExternalSymbol:
2048 case ISD::TargetBlockAddress:
2049 case ISD::TargetJumpTable:
2050 case ISD::TargetGlobalTLSAddress:
2051 case ISD::TargetGlobalAddress:
2052 case ISD::TokenFactor:
2053 case ISD::CopyFromReg:
2054 case ISD::CopyToReg:
2056 NodeToMatch->setNodeId(-1); // Mark selected.
2058 case ISD::AssertSext:
2059 case ISD::AssertZext:
2060 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2061 NodeToMatch->getOperand(0));
2063 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2064 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2067 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2069 // Set up the node stack with NodeToMatch as the only node on the stack.
2070 SmallVector<SDValue, 8> NodeStack;
2071 SDValue N = SDValue(NodeToMatch, 0);
2072 NodeStack.push_back(N);
2074 // MatchScopes - Scopes used when matching, if a match failure happens, this
2075 // indicates where to continue checking.
2076 SmallVector<MatchScope, 8> MatchScopes;
2078 // RecordedNodes - This is the set of nodes that have been recorded by the
2079 // state machine. The second value is the parent of the node, or null if the
2080 // root is recorded.
2081 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2083 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2085 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2087 // These are the current input chain and glue for use when generating nodes.
2088 // Various Emit operations change these. For example, emitting a copytoreg
2089 // uses and updates these.
2090 SDValue InputChain, InputGlue;
2092 // ChainNodesMatched - If a pattern matches nodes that have input/output
2093 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2094 // which ones they are. The result is captured into this list so that we can
2095 // update the chain results when the pattern is complete.
2096 SmallVector<SDNode*, 3> ChainNodesMatched;
2097 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2099 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2100 NodeToMatch->dump(CurDAG);
2103 // Determine where to start the interpreter. Normally we start at opcode #0,
2104 // but if the state machine starts with an OPC_SwitchOpcode, then we
2105 // accelerate the first lookup (which is guaranteed to be hot) with the
2106 // OpcodeOffset table.
2107 unsigned MatcherIndex = 0;
2109 if (!OpcodeOffset.empty()) {
2110 // Already computed the OpcodeOffset table, just index into it.
2111 if (N.getOpcode() < OpcodeOffset.size())
2112 MatcherIndex = OpcodeOffset[N.getOpcode()];
2113 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2115 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2116 // Otherwise, the table isn't computed, but the state machine does start
2117 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2118 // is the first time we're selecting an instruction.
2121 // Get the size of this case.
2122 unsigned CaseSize = MatcherTable[Idx++];
2124 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2125 if (CaseSize == 0) break;
2127 // Get the opcode, add the index to the table.
2128 uint16_t Opc = MatcherTable[Idx++];
2129 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2130 if (Opc >= OpcodeOffset.size())
2131 OpcodeOffset.resize((Opc+1)*2);
2132 OpcodeOffset[Opc] = Idx;
2136 // Okay, do the lookup for the first opcode.
2137 if (N.getOpcode() < OpcodeOffset.size())
2138 MatcherIndex = OpcodeOffset[N.getOpcode()];
2142 assert(MatcherIndex < TableSize && "Invalid index");
2144 unsigned CurrentOpcodeIndex = MatcherIndex;
2146 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2149 // Okay, the semantics of this operation are that we should push a scope
2150 // then evaluate the first child. However, pushing a scope only to have
2151 // the first check fail (which then pops it) is inefficient. If we can
2152 // determine immediately that the first check (or first several) will
2153 // immediately fail, don't even bother pushing a scope for them.
2157 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2158 if (NumToSkip & 128)
2159 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2160 // Found the end of the scope with no match.
2161 if (NumToSkip == 0) {
2166 FailIndex = MatcherIndex+NumToSkip;
2168 unsigned MatcherIndexOfPredicate = MatcherIndex;
2169 (void)MatcherIndexOfPredicate; // silence warning.
2171 // If we can't evaluate this predicate without pushing a scope (e.g. if
2172 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2173 // push the scope and evaluate the full predicate chain.
2175 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2176 Result, *this, RecordedNodes);
2180 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2181 << "index " << MatcherIndexOfPredicate
2182 << ", continuing at " << FailIndex << "\n");
2183 ++NumDAGIselRetries;
2185 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2186 // move to the next case.
2187 MatcherIndex = FailIndex;
2190 // If the whole scope failed to match, bail.
2191 if (FailIndex == 0) break;
2193 // Push a MatchScope which indicates where to go if the first child fails
2195 MatchScope NewEntry;
2196 NewEntry.FailIndex = FailIndex;
2197 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2198 NewEntry.NumRecordedNodes = RecordedNodes.size();
2199 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2200 NewEntry.InputChain = InputChain;
2201 NewEntry.InputGlue = InputGlue;
2202 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2203 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2204 MatchScopes.push_back(NewEntry);
2207 case OPC_RecordNode: {
2208 // Remember this node, it may end up being an operand in the pattern.
2210 if (NodeStack.size() > 1)
2211 Parent = NodeStack[NodeStack.size()-2].getNode();
2212 RecordedNodes.push_back(std::make_pair(N, Parent));
2216 case OPC_RecordChild0: case OPC_RecordChild1:
2217 case OPC_RecordChild2: case OPC_RecordChild3:
2218 case OPC_RecordChild4: case OPC_RecordChild5:
2219 case OPC_RecordChild6: case OPC_RecordChild7: {
2220 unsigned ChildNo = Opcode-OPC_RecordChild0;
2221 if (ChildNo >= N.getNumOperands())
2222 break; // Match fails if out of range child #.
2224 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2228 case OPC_RecordMemRef:
2229 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2232 case OPC_CaptureGlueInput:
2233 // If the current node has an input glue, capture it in InputGlue.
2234 if (N->getNumOperands() != 0 &&
2235 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2236 InputGlue = N->getOperand(N->getNumOperands()-1);
2239 case OPC_MoveChild: {
2240 unsigned ChildNo = MatcherTable[MatcherIndex++];
2241 if (ChildNo >= N.getNumOperands())
2242 break; // Match fails if out of range child #.
2243 N = N.getOperand(ChildNo);
2244 NodeStack.push_back(N);
2248 case OPC_MoveParent:
2249 // Pop the current node off the NodeStack.
2250 NodeStack.pop_back();
2251 assert(!NodeStack.empty() && "Node stack imbalance!");
2252 N = NodeStack.back();
2256 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2258 case OPC_CheckPatternPredicate:
2259 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2261 case OPC_CheckPredicate:
2262 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2266 case OPC_CheckComplexPat: {
2267 unsigned CPNum = MatcherTable[MatcherIndex++];
2268 unsigned RecNo = MatcherTable[MatcherIndex++];
2269 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2270 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2271 RecordedNodes[RecNo].first, CPNum,
2276 case OPC_CheckOpcode:
2277 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2281 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2284 case OPC_SwitchOpcode: {
2285 unsigned CurNodeOpcode = N.getOpcode();
2286 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2289 // Get the size of this case.
2290 CaseSize = MatcherTable[MatcherIndex++];
2292 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2293 if (CaseSize == 0) break;
2295 uint16_t Opc = MatcherTable[MatcherIndex++];
2296 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2298 // If the opcode matches, then we will execute this case.
2299 if (CurNodeOpcode == Opc)
2302 // Otherwise, skip over this case.
2303 MatcherIndex += CaseSize;
2306 // If no cases matched, bail out.
2307 if (CaseSize == 0) break;
2309 // Otherwise, execute the case we found.
2310 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2311 << " to " << MatcherIndex << "\n");
2315 case OPC_SwitchType: {
2316 MVT CurNodeVT = N.getValueType().getSimpleVT();
2317 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2320 // Get the size of this case.
2321 CaseSize = MatcherTable[MatcherIndex++];
2323 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2324 if (CaseSize == 0) break;
2326 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2327 if (CaseVT == MVT::iPTR)
2328 CaseVT = TLI.getPointerTy();
2330 // If the VT matches, then we will execute this case.
2331 if (CurNodeVT == CaseVT)
2334 // Otherwise, skip over this case.
2335 MatcherIndex += CaseSize;
2338 // If no cases matched, bail out.
2339 if (CaseSize == 0) break;
2341 // Otherwise, execute the case we found.
2342 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2343 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2346 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2347 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2348 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2349 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2350 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2351 Opcode-OPC_CheckChild0Type))
2354 case OPC_CheckCondCode:
2355 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2357 case OPC_CheckValueType:
2358 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2360 case OPC_CheckInteger:
2361 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2363 case OPC_CheckAndImm:
2364 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2366 case OPC_CheckOrImm:
2367 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2370 case OPC_CheckFoldableChainNode: {
2371 assert(NodeStack.size() != 1 && "No parent node");
2372 // Verify that all intermediate nodes between the root and this one have
2374 bool HasMultipleUses = false;
2375 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2376 if (!NodeStack[i].hasOneUse()) {
2377 HasMultipleUses = true;
2380 if (HasMultipleUses) break;
2382 // Check to see that the target thinks this is profitable to fold and that
2383 // we can fold it without inducing cycles in the graph.
2384 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2386 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2387 NodeToMatch, OptLevel,
2388 true/*We validate our own chains*/))
2393 case OPC_EmitInteger: {
2394 MVT::SimpleValueType VT =
2395 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2396 int64_t Val = MatcherTable[MatcherIndex++];
2398 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2399 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2400 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2403 case OPC_EmitRegister: {
2404 MVT::SimpleValueType VT =
2405 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2406 unsigned RegNo = MatcherTable[MatcherIndex++];
2407 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2408 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2411 case OPC_EmitRegister2: {
2412 // For targets w/ more than 256 register names, the register enum
2413 // values are stored in two bytes in the matcher table (just like
2415 MVT::SimpleValueType VT =
2416 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2417 unsigned RegNo = MatcherTable[MatcherIndex++];
2418 RegNo |= MatcherTable[MatcherIndex++] << 8;
2419 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2420 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2424 case OPC_EmitConvertToTarget: {
2425 // Convert from IMM/FPIMM to target version.
2426 unsigned RecNo = MatcherTable[MatcherIndex++];
2427 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2428 SDValue Imm = RecordedNodes[RecNo].first;
2430 if (Imm->getOpcode() == ISD::Constant) {
2431 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2432 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2433 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2434 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2435 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2438 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2442 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2443 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2444 // These are space-optimized forms of OPC_EmitMergeInputChains.
2445 assert(InputChain.getNode() == 0 &&
2446 "EmitMergeInputChains should be the first chain producing node");
2447 assert(ChainNodesMatched.empty() &&
2448 "Should only have one EmitMergeInputChains per match");
2450 // Read all of the chained nodes.
2451 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2452 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2453 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2455 // FIXME: What if other value results of the node have uses not matched
2457 if (ChainNodesMatched.back() != NodeToMatch &&
2458 !RecordedNodes[RecNo].first.hasOneUse()) {
2459 ChainNodesMatched.clear();
2463 // Merge the input chains if they are not intra-pattern references.
2464 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2466 if (InputChain.getNode() == 0)
2467 break; // Failed to merge.
2471 case OPC_EmitMergeInputChains: {
2472 assert(InputChain.getNode() == 0 &&
2473 "EmitMergeInputChains should be the first chain producing node");
2474 // This node gets a list of nodes we matched in the input that have
2475 // chains. We want to token factor all of the input chains to these nodes
2476 // together. However, if any of the input chains is actually one of the
2477 // nodes matched in this pattern, then we have an intra-match reference.
2478 // Ignore these because the newly token factored chain should not refer to
2480 unsigned NumChains = MatcherTable[MatcherIndex++];
2481 assert(NumChains != 0 && "Can't TF zero chains");
2483 assert(ChainNodesMatched.empty() &&
2484 "Should only have one EmitMergeInputChains per match");
2486 // Read all of the chained nodes.
2487 for (unsigned i = 0; i != NumChains; ++i) {
2488 unsigned RecNo = MatcherTable[MatcherIndex++];
2489 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2490 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2492 // FIXME: What if other value results of the node have uses not matched
2494 if (ChainNodesMatched.back() != NodeToMatch &&
2495 !RecordedNodes[RecNo].first.hasOneUse()) {
2496 ChainNodesMatched.clear();
2501 // If the inner loop broke out, the match fails.
2502 if (ChainNodesMatched.empty())
2505 // Merge the input chains if they are not intra-pattern references.
2506 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2508 if (InputChain.getNode() == 0)
2509 break; // Failed to merge.
2514 case OPC_EmitCopyToReg: {
2515 unsigned RecNo = MatcherTable[MatcherIndex++];
2516 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2517 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2519 if (InputChain.getNode() == 0)
2520 InputChain = CurDAG->getEntryNode();
2522 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2523 DestPhysReg, RecordedNodes[RecNo].first,
2526 InputGlue = InputChain.getValue(1);
2530 case OPC_EmitNodeXForm: {
2531 unsigned XFormNo = MatcherTable[MatcherIndex++];
2532 unsigned RecNo = MatcherTable[MatcherIndex++];
2533 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2534 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2535 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2540 case OPC_MorphNodeTo: {
2541 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2542 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2543 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2544 // Get the result VT list.
2545 unsigned NumVTs = MatcherTable[MatcherIndex++];
2546 SmallVector<EVT, 4> VTs;
2547 for (unsigned i = 0; i != NumVTs; ++i) {
2548 MVT::SimpleValueType VT =
2549 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2550 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2554 if (EmitNodeInfo & OPFL_Chain)
2555 VTs.push_back(MVT::Other);
2556 if (EmitNodeInfo & OPFL_GlueOutput)
2557 VTs.push_back(MVT::Glue);
2559 // This is hot code, so optimize the two most common cases of 1 and 2
2562 if (VTs.size() == 1)
2563 VTList = CurDAG->getVTList(VTs[0]);
2564 else if (VTs.size() == 2)
2565 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2567 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2569 // Get the operand list.
2570 unsigned NumOps = MatcherTable[MatcherIndex++];
2571 SmallVector<SDValue, 8> Ops;
2572 for (unsigned i = 0; i != NumOps; ++i) {
2573 unsigned RecNo = MatcherTable[MatcherIndex++];
2575 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2577 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2578 Ops.push_back(RecordedNodes[RecNo].first);
2581 // If there are variadic operands to add, handle them now.
2582 if (EmitNodeInfo & OPFL_VariadicInfo) {
2583 // Determine the start index to copy from.
2584 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2585 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2586 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2587 "Invalid variadic node");
2588 // Copy all of the variadic operands, not including a potential glue
2590 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2592 SDValue V = NodeToMatch->getOperand(i);
2593 if (V.getValueType() == MVT::Glue) break;
2598 // If this has chain/glue inputs, add them.
2599 if (EmitNodeInfo & OPFL_Chain)
2600 Ops.push_back(InputChain);
2601 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2602 Ops.push_back(InputGlue);
2606 if (Opcode != OPC_MorphNodeTo) {
2607 // If this is a normal EmitNode command, just create the new node and
2608 // add the results to the RecordedNodes list.
2609 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2610 VTList, Ops.data(), Ops.size());
2612 // Add all the non-glue/non-chain results to the RecordedNodes list.
2613 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2614 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2615 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2620 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2624 // If the node had chain/glue results, update our notion of the current
2626 if (EmitNodeInfo & OPFL_GlueOutput) {
2627 InputGlue = SDValue(Res, VTs.size()-1);
2628 if (EmitNodeInfo & OPFL_Chain)
2629 InputChain = SDValue(Res, VTs.size()-2);
2630 } else if (EmitNodeInfo & OPFL_Chain)
2631 InputChain = SDValue(Res, VTs.size()-1);
2633 // If the OPFL_MemRefs glue is set on this node, slap all of the
2634 // accumulated memrefs onto it.
2636 // FIXME: This is vastly incorrect for patterns with multiple outputs
2637 // instructions that access memory and for ComplexPatterns that match
2639 if (EmitNodeInfo & OPFL_MemRefs) {
2640 // Only attach load or store memory operands if the generated
2641 // instruction may load or store.
2642 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2643 bool mayLoad = MCID.mayLoad();
2644 bool mayStore = MCID.mayStore();
2646 unsigned NumMemRefs = 0;
2647 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2648 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2649 if ((*I)->isLoad()) {
2652 } else if ((*I)->isStore()) {
2660 MachineSDNode::mmo_iterator MemRefs =
2661 MF->allocateMemRefsArray(NumMemRefs);
2663 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2664 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2665 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2666 if ((*I)->isLoad()) {
2669 } else if ((*I)->isStore()) {
2677 cast<MachineSDNode>(Res)
2678 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2682 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2683 << " node: "; Res->dump(CurDAG); errs() << "\n");
2685 // If this was a MorphNodeTo then we're completely done!
2686 if (Opcode == OPC_MorphNodeTo) {
2687 // Update chain and glue uses.
2688 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2689 InputGlue, GlueResultNodesMatched, true);
2696 case OPC_MarkGlueResults: {
2697 unsigned NumNodes = MatcherTable[MatcherIndex++];
2699 // Read and remember all the glue-result nodes.
2700 for (unsigned i = 0; i != NumNodes; ++i) {
2701 unsigned RecNo = MatcherTable[MatcherIndex++];
2703 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2705 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2706 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2711 case OPC_CompleteMatch: {
2712 // The match has been completed, and any new nodes (if any) have been
2713 // created. Patch up references to the matched dag to use the newly
2715 unsigned NumResults = MatcherTable[MatcherIndex++];
2717 for (unsigned i = 0; i != NumResults; ++i) {
2718 unsigned ResSlot = MatcherTable[MatcherIndex++];
2720 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2722 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2723 SDValue Res = RecordedNodes[ResSlot].first;
2725 assert(i < NodeToMatch->getNumValues() &&
2726 NodeToMatch->getValueType(i) != MVT::Other &&
2727 NodeToMatch->getValueType(i) != MVT::Glue &&
2728 "Invalid number of results to complete!");
2729 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2730 NodeToMatch->getValueType(i) == MVT::iPTR ||
2731 Res.getValueType() == MVT::iPTR ||
2732 NodeToMatch->getValueType(i).getSizeInBits() ==
2733 Res.getValueType().getSizeInBits()) &&
2734 "invalid replacement");
2735 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2738 // If the root node defines glue, add it to the glue nodes to update list.
2739 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2740 GlueResultNodesMatched.push_back(NodeToMatch);
2742 // Update chain and glue uses.
2743 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2744 InputGlue, GlueResultNodesMatched, false);
2746 assert(NodeToMatch->use_empty() &&
2747 "Didn't replace all uses of the node?");
2749 // FIXME: We just return here, which interacts correctly with SelectRoot
2750 // above. We should fix this to not return an SDNode* anymore.
2755 // If the code reached this point, then the match failed. See if there is
2756 // another child to try in the current 'Scope', otherwise pop it until we
2757 // find a case to check.
2758 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2759 ++NumDAGIselRetries;
2761 if (MatchScopes.empty()) {
2762 CannotYetSelect(NodeToMatch);
2766 // Restore the interpreter state back to the point where the scope was
2768 MatchScope &LastScope = MatchScopes.back();
2769 RecordedNodes.resize(LastScope.NumRecordedNodes);
2771 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2772 N = NodeStack.back();
2774 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2775 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2776 MatcherIndex = LastScope.FailIndex;
2778 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2780 InputChain = LastScope.InputChain;
2781 InputGlue = LastScope.InputGlue;
2782 if (!LastScope.HasChainNodesMatched)
2783 ChainNodesMatched.clear();
2784 if (!LastScope.HasGlueResultNodesMatched)
2785 GlueResultNodesMatched.clear();
2787 // Check to see what the offset is at the new MatcherIndex. If it is zero
2788 // we have reached the end of this scope, otherwise we have another child
2789 // in the current scope to try.
2790 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2791 if (NumToSkip & 128)
2792 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2794 // If we have another child in this scope to match, update FailIndex and
2796 if (NumToSkip != 0) {
2797 LastScope.FailIndex = MatcherIndex+NumToSkip;
2801 // End of this scope, pop it and try the next child in the containing
2803 MatchScopes.pop_back();
2810 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2812 raw_string_ostream Msg(msg);
2813 Msg << "Cannot select: ";
2815 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2816 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2817 N->getOpcode() != ISD::INTRINSIC_VOID) {
2818 N->printrFull(Msg, CurDAG);
2820 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2822 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2823 if (iid < Intrinsic::num_intrinsics)
2824 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2825 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2826 Msg << "target intrinsic %" << TII->getName(iid);
2828 Msg << "unknown intrinsic #" << iid;
2830 report_fatal_error(Msg.str());
2833 char SelectionDAGISel::ID = 0;