1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
57 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
58 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 STATISTIC(NumBBWithOutOfOrderLineInfo,
60 "Number of blocks with out of order line number info");
61 STATISTIC(NumMBBWithOutOfOrderLineInfo,
62 "Number of machine blocks with out of order line number info");
65 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
66 cl::desc("Enable verbose messages in the \"fast\" "
67 "instruction selector"));
69 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
70 cl::desc("Enable abort calls when \"fast\" instruction fails"));
74 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
75 cl::desc("Pop up a window to show dags before the first "
78 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before legalize types"));
81 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
82 cl::desc("Pop up a window to show dags before legalize"));
84 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
85 cl::desc("Pop up a window to show dags before the second "
88 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
89 cl::desc("Pop up a window to show dags before the post legalize types"
90 " dag combine pass"));
92 ViewISelDAGs("view-isel-dags", cl::Hidden,
93 cl::desc("Pop up a window to show isel dags as they are selected"));
95 ViewSchedDAGs("view-sched-dags", cl::Hidden,
96 cl::desc("Pop up a window to show sched dags as they are processed"));
98 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
99 cl::desc("Pop up a window to show SUnit dags after they are processed"));
101 static const bool ViewDAGCombine1 = false,
102 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
103 ViewDAGCombine2 = false,
104 ViewDAGCombineLT = false,
105 ViewISelDAGs = false, ViewSchedDAGs = false,
106 ViewSUnitDAGs = false;
109 //===---------------------------------------------------------------------===//
111 /// RegisterScheduler class - Track the registration of instruction schedulers.
113 //===---------------------------------------------------------------------===//
114 MachinePassRegistry RegisterScheduler::Registry;
116 //===---------------------------------------------------------------------===//
118 /// ISHeuristic command line option for instruction schedulers.
120 //===---------------------------------------------------------------------===//
121 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
122 RegisterPassParser<RegisterScheduler> >
123 ISHeuristic("pre-RA-sched",
124 cl::init(&createDefaultScheduler),
125 cl::desc("Instruction schedulers available (before register"
128 static RegisterScheduler
129 defaultListDAGScheduler("default", "Best scheduler for the target",
130 createDefaultScheduler);
133 //===--------------------------------------------------------------------===//
134 /// createDefaultScheduler - This creates an instruction scheduler appropriate
136 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
137 CodeGenOpt::Level OptLevel) {
138 const TargetLowering &TLI = IS->getTargetLowering();
140 if (OptLevel == CodeGenOpt::None)
141 return createSourceListDAGScheduler(IS, OptLevel);
142 if (TLI.getSchedulingPreference() == Sched::Latency)
143 return createTDListDAGScheduler(IS, OptLevel);
144 if (TLI.getSchedulingPreference() == Sched::RegPressure)
145 return createBURRListDAGScheduler(IS, OptLevel);
146 if (TLI.getSchedulingPreference() == Sched::Hybrid)
147 return createHybridListDAGScheduler(IS, OptLevel);
148 assert(TLI.getSchedulingPreference() == Sched::ILP &&
149 "Unknown sched type!");
150 return createILPListDAGScheduler(IS, OptLevel);
154 // EmitInstrWithCustomInserter - This method should be implemented by targets
155 // that mark instructions with the 'usesCustomInserter' flag. These
156 // instructions are special in various ways, which require special support to
157 // insert. The specified MachineInstr is created but not inserted into any
158 // basic blocks, and this method is called to expand it into a sequence of
159 // instructions, potentially also creating new basic blocks and control flow.
160 // When new basic blocks are inserted and the edges from MBB to its successors
161 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
164 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
165 MachineBasicBlock *MBB) const {
167 dbgs() << "If a target marks an instruction with "
168 "'usesCustomInserter', it must implement "
169 "TargetLowering::EmitInstrWithCustomInserter!";
175 //===----------------------------------------------------------------------===//
176 // SelectionDAGISel code
177 //===----------------------------------------------------------------------===//
179 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
180 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
181 FuncInfo(new FunctionLoweringInfo(TLI)),
182 CurDAG(new SelectionDAG(tm)),
183 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
187 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
188 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
191 SelectionDAGISel::~SelectionDAGISel() {
197 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
198 AU.addRequired<AliasAnalysis>();
199 AU.addPreserved<AliasAnalysis>();
200 AU.addRequired<GCModuleInfo>();
201 AU.addPreserved<GCModuleInfo>();
202 MachineFunctionPass::getAnalysisUsage(AU);
205 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
206 /// other function that gcc recognizes as "returning twice". This is used to
207 /// limit code-gen optimizations on the machine function.
209 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
210 static bool FunctionCallsSetJmp(const Function *F) {
211 const Module *M = F->getParent();
212 static const char *ReturnsTwiceFns[] = {
221 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
223 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
224 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
225 if (!Callee->use_empty())
226 for (Value::const_use_iterator
227 I = Callee->use_begin(), E = Callee->use_end();
229 if (const CallInst *CI = dyn_cast<CallInst>(*I))
230 if (CI->getParent()->getParent() == F)
235 #undef NUM_RETURNS_TWICE_FNS
238 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
239 // Do some sanity-checking on the command-line options.
240 assert((!EnableFastISelVerbose || EnableFastISel) &&
241 "-fast-isel-verbose requires -fast-isel");
242 assert((!EnableFastISelAbort || EnableFastISel) &&
243 "-fast-isel-abort requires -fast-isel");
245 const Function &Fn = *mf.getFunction();
246 const TargetInstrInfo &TII = *TM.getInstrInfo();
247 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
250 RegInfo = &MF->getRegInfo();
251 AA = &getAnalysis<AliasAnalysis>();
252 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
254 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
257 FuncInfo->set(Fn, *MF);
260 SelectAllBasicBlocks(Fn);
262 // If the first basic block in the function has live ins that need to be
263 // copied into vregs, emit the copies into the top of the block before
264 // emitting the code for the block.
265 MachineBasicBlock *EntryMBB = MF->begin();
266 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
268 DenseMap<unsigned, unsigned> LiveInMap;
269 if (!FuncInfo->ArgDbgValues.empty())
270 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
271 E = RegInfo->livein_end(); LI != E; ++LI)
273 LiveInMap.insert(std::make_pair(LI->first, LI->second));
275 // Insert DBG_VALUE instructions for function arguments to the entry block.
276 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
277 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
278 unsigned Reg = MI->getOperand(0).getReg();
279 if (TargetRegisterInfo::isPhysicalRegister(Reg))
280 EntryMBB->insert(EntryMBB->begin(), MI);
282 MachineInstr *Def = RegInfo->getVRegDef(Reg);
283 MachineBasicBlock::iterator InsertPos = Def;
284 // FIXME: VR def may not be in entry block.
285 Def->getParent()->insert(llvm::next(InsertPos), MI);
288 // If Reg is live-in then update debug info to track its copy in a vreg.
289 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
290 if (LDI != LiveInMap.end()) {
291 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
292 MachineBasicBlock::iterator InsertPos = Def;
293 const MDNode *Variable =
294 MI->getOperand(MI->getNumOperands()-1).getMetadata();
295 unsigned Offset = MI->getOperand(1).getImm();
296 // Def is never a terminator here, so it is ok to increment InsertPos.
297 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
298 TII.get(TargetOpcode::DBG_VALUE))
299 .addReg(LDI->second, RegState::Debug)
300 .addImm(Offset).addMetadata(Variable);
302 // If this vreg is directly copied into an exported register then
303 // that COPY instructions also need DBG_VALUE, if it is the only
304 // user of LDI->second.
305 MachineInstr *CopyUseMI = NULL;
306 for (MachineRegisterInfo::use_iterator
307 UI = RegInfo->use_begin(LDI->second);
308 MachineInstr *UseMI = UI.skipInstruction();) {
309 if (UseMI->isDebugValue()) continue;
310 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
311 CopyUseMI = UseMI; continue;
313 // Otherwise this is another use or second copy use.
314 CopyUseMI = NULL; break;
317 MachineInstr *NewMI =
318 BuildMI(*MF, CopyUseMI->getDebugLoc(),
319 TII.get(TargetOpcode::DBG_VALUE))
320 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
321 .addImm(Offset).addMetadata(Variable);
322 EntryMBB->insertAfter(CopyUseMI, NewMI);
327 // Determine if there are any calls in this machine function.
328 MachineFrameInfo *MFI = MF->getFrameInfo();
329 if (!MFI->hasCalls()) {
330 for (MachineFunction::const_iterator
331 I = MF->begin(), E = MF->end(); I != E; ++I) {
332 const MachineBasicBlock *MBB = I;
333 for (MachineBasicBlock::const_iterator
334 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
335 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
337 // Operand 1 of an inline asm instruction indicates whether the asm
338 // needs stack or not.
339 if ((II->isInlineAsm() && II->getOperand(1).getImm()) ||
340 (TID.isCall() && !TID.isReturn())) {
341 MFI->setHasCalls(true);
349 // Determine if there is a call to setjmp in the machine function.
350 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
352 // Replace forward-declared registers with the registers containing
353 // the desired value.
354 MachineRegisterInfo &MRI = MF->getRegInfo();
355 for (DenseMap<unsigned, unsigned>::iterator
356 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
358 unsigned From = I->first;
359 unsigned To = I->second;
360 // If To is also scheduled to be replaced, find what its ultimate
363 DenseMap<unsigned, unsigned>::iterator J =
364 FuncInfo->RegFixups.find(To);
369 MRI.replaceRegWith(From, To);
372 // Release function-specific state. SDB and CurDAG are already cleared
380 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
381 BasicBlock::const_iterator End,
383 // Lower all of the non-terminator instructions. If a call is emitted
384 // as a tail call, cease emitting nodes for this block. Terminators
385 // are handled below.
386 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
389 // Make sure the root of the DAG is up-to-date.
390 CurDAG->setRoot(SDB->getControlRoot());
391 HadTailCall = SDB->HasTailCall;
394 // Final step, emit the lowered DAG as machine code.
399 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
400 SmallPtrSet<SDNode*, 128> VisitedNodes;
401 SmallVector<SDNode*, 128> Worklist;
403 Worklist.push_back(CurDAG->getRoot().getNode());
410 SDNode *N = Worklist.pop_back_val();
412 // If we've already seen this node, ignore it.
413 if (!VisitedNodes.insert(N))
416 // Otherwise, add all chain operands to the worklist.
417 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
418 if (N->getOperand(i).getValueType() == MVT::Other)
419 Worklist.push_back(N->getOperand(i).getNode());
421 // If this is a CopyToReg with a vreg dest, process it.
422 if (N->getOpcode() != ISD::CopyToReg)
425 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
426 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
429 // Ignore non-scalar or non-integer values.
430 SDValue Src = N->getOperand(2);
431 EVT SrcVT = Src.getValueType();
432 if (!SrcVT.isInteger() || SrcVT.isVector())
435 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
436 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
437 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
439 // Only install this information if it tells us something.
440 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
441 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
442 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
443 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
444 FunctionLoweringInfo::LiveOutInfo &LOI =
445 FuncInfo->LiveOutRegInfo[DestReg];
446 LOI.NumSignBits = NumSignBits;
447 LOI.KnownOne = KnownOne;
448 LOI.KnownZero = KnownZero;
450 } while (!Worklist.empty());
453 void SelectionDAGISel::CodeGenAndEmitDAG() {
454 std::string GroupName;
455 if (TimePassesIsEnabled)
456 GroupName = "Instruction Selection and Scheduling";
457 std::string BlockName;
458 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
459 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
461 BlockName = MF->getFunction()->getNameStr() + ":" +
462 FuncInfo->MBB->getBasicBlock()->getNameStr();
464 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
466 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
468 // Run the DAG combiner in pre-legalize mode.
470 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
471 CurDAG->Combine(Unrestricted, *AA, OptLevel);
474 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
476 // Second step, hack on the DAG until it only uses operations and types that
477 // the target supports.
478 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
483 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
484 Changed = CurDAG->LegalizeTypes();
487 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
490 if (ViewDAGCombineLT)
491 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
493 // Run the DAG combiner in post-type-legalize mode.
495 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
496 TimePassesIsEnabled);
497 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
500 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
505 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
506 Changed = CurDAG->LegalizeVectors();
511 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
512 CurDAG->LegalizeTypes();
515 if (ViewDAGCombineLT)
516 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
518 // Run the DAG combiner in post-type-legalize mode.
520 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
521 TimePassesIsEnabled);
522 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
525 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
529 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
532 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
533 CurDAG->Legalize(OptLevel);
536 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
538 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
540 // Run the DAG combiner in post-legalize mode.
542 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
543 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
546 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
548 if (OptLevel != CodeGenOpt::None)
549 ComputeLiveOutVRegInfo();
551 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
553 // Third, instruction select all of the operations to machine code, adding the
554 // code to the MachineBasicBlock.
556 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
557 DoInstructionSelection();
560 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
562 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
564 // Schedule machine code.
565 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
567 NamedRegionTimer T("Instruction Scheduling", GroupName,
568 TimePassesIsEnabled);
569 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
572 if (ViewSUnitDAGs) Scheduler->viewGraph();
574 // Emit machine code to BB. This can change 'BB' to the last block being
576 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
578 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
580 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
581 FuncInfo->InsertPt = Scheduler->InsertPos;
584 // If the block was split, make sure we update any references that are used to
585 // update PHI nodes later on.
586 if (FirstMBB != LastMBB)
587 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
589 // Free the scheduler state.
591 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
592 TimePassesIsEnabled);
596 // Free the SelectionDAG state, now that we're finished with it.
600 void SelectionDAGISel::DoInstructionSelection() {
601 DEBUG(errs() << "===== Instruction selection begins:\n");
605 // Select target instructions for the DAG.
607 // Number all nodes with a topological order and set DAGSize.
608 DAGSize = CurDAG->AssignTopologicalOrder();
610 // Create a dummy node (which is not added to allnodes), that adds
611 // a reference to the root node, preventing it from being deleted,
612 // and tracking any changes of the root.
613 HandleSDNode Dummy(CurDAG->getRoot());
614 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
617 // The AllNodes list is now topological-sorted. Visit the
618 // nodes by starting at the end of the list (the root of the
619 // graph) and preceding back toward the beginning (the entry
621 while (ISelPosition != CurDAG->allnodes_begin()) {
622 SDNode *Node = --ISelPosition;
623 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
624 // but there are currently some corner cases that it misses. Also, this
625 // makes it theoretically possible to disable the DAGCombiner.
626 if (Node->use_empty())
629 SDNode *ResNode = Select(Node);
631 // FIXME: This is pretty gross. 'Select' should be changed to not return
632 // anything at all and this code should be nuked with a tactical strike.
634 // If node should not be replaced, continue with the next one.
635 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
639 ReplaceUses(Node, ResNode);
641 // If after the replacement this node is not used any more,
642 // remove this dead node.
643 if (Node->use_empty()) { // Don't delete EntryToken, etc.
644 ISelUpdater ISU(ISelPosition);
645 CurDAG->RemoveDeadNode(Node, &ISU);
649 CurDAG->setRoot(Dummy.getValue());
652 DEBUG(errs() << "===== Instruction selection ends:\n");
654 PostprocessISelDAG();
657 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
658 /// do other setup for EH landing-pad blocks.
659 void SelectionDAGISel::PrepareEHLandingPad() {
660 // Add a label to mark the beginning of the landing pad. Deletion of the
661 // landing pad can thus be detected via the MachineModuleInfo.
662 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
664 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
665 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
668 // Mark exception register as live in.
669 unsigned Reg = TLI.getExceptionAddressRegister();
670 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
672 // Mark exception selector register as live in.
673 Reg = TLI.getExceptionSelectorRegister();
674 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
676 // FIXME: Hack around an exception handling flaw (PR1508): the personality
677 // function and list of typeids logically belong to the invoke (or, if you
678 // like, the basic block containing the invoke), and need to be associated
679 // with it in the dwarf exception handling tables. Currently however the
680 // information is provided by an intrinsic (eh.selector) that can be moved
681 // to unexpected places by the optimizers: if the unwind edge is critical,
682 // then breaking it can result in the intrinsics being in the successor of
683 // the landing pad, not the landing pad itself. This results
684 // in exceptions not being caught because no typeids are associated with
685 // the invoke. This may not be the only way things can go wrong, but it
686 // is the only way we try to work around for the moment.
687 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
688 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
690 if (Br && Br->isUnconditional()) { // Critical edge?
691 BasicBlock::const_iterator I, E;
692 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
693 if (isa<EHSelectorInst>(I))
697 // No catch info found - try to extract some from the successor.
698 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
705 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
707 // Don't try to fold volatile loads. Target has to deal with alignment
709 if (LI->isVolatile()) return false;
711 // Figure out which vreg this is going into.
712 unsigned LoadReg = FastIS->getRegForValue(LI);
713 assert(LoadReg && "Load isn't already assigned a vreg? ");
715 // Check to see what the uses of this vreg are. If it has no uses, or more
716 // than one use (at the machine instr level) then we can't fold it.
717 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
718 if (RI == RegInfo->reg_end())
721 // See if there is exactly one use of the vreg. If there are multiple uses,
722 // then the instruction got lowered to multiple machine instructions or the
723 // use of the loaded value ended up being multiple operands of the result, in
724 // either case, we can't fold this.
725 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
726 if (PostRI != RegInfo->reg_end())
729 assert(RI.getOperand().isUse() &&
730 "The only use of the vreg must be a use, we haven't emitted the def!");
732 // Ask the target to try folding the load.
733 return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI);
737 /// CheckLineNumbers - Check if basic block instructions follow source order
739 static void CheckLineNumbers(const BasicBlock *BB) {
742 for (BasicBlock::const_iterator BI = BB->begin(),
743 BE = BB->end(); BI != BE; ++BI) {
744 const DebugLoc DL = BI->getDebugLoc();
745 if (DL.isUnknown()) continue;
746 unsigned L = DL.getLine();
747 unsigned C = DL.getCol();
748 if (L < Line || (L == Line && C < Col)) {
749 ++NumBBWithOutOfOrderLineInfo;
757 /// CheckLineNumbers - Check if machine basic block instructions follow source
759 static void CheckLineNumbers(const MachineBasicBlock *MBB) {
762 for (MachineBasicBlock::const_iterator MBI = MBB->begin(),
763 MBE = MBB->end(); MBI != MBE; ++MBI) {
764 const DebugLoc DL = MBI->getDebugLoc();
765 if (DL.isUnknown()) continue;
766 unsigned L = DL.getLine();
767 unsigned C = DL.getCol();
768 if (L < Line || (L == Line && C < Col)) {
769 ++NumMBBWithOutOfOrderLineInfo;
778 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
779 // Initialize the Fast-ISel state, if needed.
780 FastISel *FastIS = 0;
782 FastIS = TLI.createFastISel(*FuncInfo);
784 // Iterate over all basic blocks in the function.
785 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
786 bool BBSelectedUsingDAG = false;
787 const BasicBlock *LLVMBB = &*I;
789 CheckLineNumbers(LLVMBB);
791 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
792 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
794 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
795 BasicBlock::const_iterator const End = LLVMBB->end();
796 BasicBlock::const_iterator BI = End;
798 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
800 // Setup an EH landing-pad block.
801 if (FuncInfo->MBB->isLandingPad())
802 PrepareEHLandingPad();
804 // Lower any arguments needed in this block if this is the entry block.
805 if (LLVMBB == &Fn.getEntryBlock())
806 LowerArguments(LLVMBB);
808 // Before doing SelectionDAG ISel, see if FastISel has been requested.
810 FastIS->startNewBlock();
812 // Emit code for any incoming arguments. This must happen before
813 // beginning FastISel on the entry block.
814 if (LLVMBB == &Fn.getEntryBlock()) {
815 CurDAG->setRoot(SDB->getControlRoot());
819 // If we inserted any instructions at the beginning, make a note of
820 // where they are, so we can be sure to emit subsequent instructions
822 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
823 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
825 FastIS->setLastLocalValue(0);
828 // Do FastISel on as many instructions as possible.
829 for (; BI != Begin; --BI) {
830 const Instruction *Inst = llvm::prior(BI);
832 // If we no longer require this instruction, skip it.
833 if (!Inst->mayWriteToMemory() &&
834 !isa<TerminatorInst>(Inst) &&
835 !isa<DbgInfoIntrinsic>(Inst) &&
836 !FuncInfo->isExportedInst(Inst))
839 // Bottom-up: reset the insert pos at the top, after any local-value
841 FastIS->recomputeInsertPt();
843 // Try to select the instruction with FastISel.
844 if (FastIS->SelectInstruction(Inst)) {
845 // If fast isel succeeded, check to see if there is a single-use
846 // non-volatile load right before the selected instruction, and see if
847 // the load is used by the instruction. If so, try to fold it.
848 const Instruction *BeforeInst = 0;
850 BeforeInst = llvm::prior(llvm::prior(BI));
851 if (BeforeInst && isa<LoadInst>(BeforeInst) &&
852 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst &&
853 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS)) {
854 // If we succeeded, don't re-select the load.
860 // Then handle certain instructions as single-LLVM-Instruction blocks.
861 if (isa<CallInst>(Inst)) {
862 ++NumFastIselFailures;
863 if (EnableFastISelVerbose || EnableFastISelAbort) {
864 dbgs() << "FastISel missed call: ";
868 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
869 unsigned &R = FuncInfo->ValueMap[Inst];
871 R = FuncInfo->CreateRegs(Inst->getType());
874 bool HadTailCall = false;
875 BBSelectedUsingDAG |= SelectBasicBlock(Inst, BI, HadTailCall);
877 // If the call was emitted as a tail call, we're done with the block.
886 // Otherwise, give up on FastISel for the rest of the block.
887 // For now, be a little lenient about non-branch terminators.
888 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
889 ++NumFastIselFailures;
890 if (EnableFastISelVerbose || EnableFastISelAbort) {
891 dbgs() << "FastISel miss: ";
894 if (EnableFastISelAbort)
895 // The "fast" selector couldn't handle something and bailed.
896 // For the purpose of debugging, just abort.
897 llvm_unreachable("FastISel didn't select the entire block");
902 FastIS->recomputeInsertPt();
905 // Run SelectionDAG instruction selection on the remainder of the block
906 // not handled by FastISel. If FastISel is not run, this is the entire
909 BBSelectedUsingDAG |= SelectBasicBlock(Begin, BI, HadTailCall);
912 FuncInfo->PHINodesToUpdate.clear();
913 if (BBSelectedUsingDAG)
921 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end();
923 CheckLineNumbers(MBI);
928 SelectionDAGISel::FinishBasicBlock() {
930 DEBUG(dbgs() << "Total amount of phi nodes to update: "
931 << FuncInfo->PHINodesToUpdate.size() << "\n";
932 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
933 dbgs() << "Node " << i << " : ("
934 << FuncInfo->PHINodesToUpdate[i].first
935 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
937 // Next, now that we know what the last MBB the LLVM BB expanded is, update
938 // PHI nodes in successors.
939 if (SDB->SwitchCases.empty() &&
940 SDB->JTCases.empty() &&
941 SDB->BitTestCases.empty()) {
942 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
943 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
944 assert(PHI->isPHI() &&
945 "This is not a machine PHI node that we are updating!");
946 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
949 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
950 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
955 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
956 // Lower header first, if it wasn't already lowered
957 if (!SDB->BitTestCases[i].Emitted) {
958 // Set the current basic block to the mbb we wish to insert the code into
959 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
960 FuncInfo->InsertPt = FuncInfo->MBB->end();
962 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
963 CurDAG->setRoot(SDB->getRoot());
968 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
969 // Set the current basic block to the mbb we wish to insert the code into
970 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
971 FuncInfo->InsertPt = FuncInfo->MBB->end();
974 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
975 SDB->BitTestCases[i].Reg,
976 SDB->BitTestCases[i].Cases[j],
979 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
980 SDB->BitTestCases[i].Reg,
981 SDB->BitTestCases[i].Cases[j],
985 CurDAG->setRoot(SDB->getRoot());
991 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
993 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
994 MachineBasicBlock *PHIBB = PHI->getParent();
995 assert(PHI->isPHI() &&
996 "This is not a machine PHI node that we are updating!");
997 // This is "default" BB. We have two jumps to it. From "header" BB and
998 // from last "case" BB.
999 if (PHIBB == SDB->BitTestCases[i].Default) {
1000 PHI->addOperand(MachineOperand::
1001 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1003 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1004 PHI->addOperand(MachineOperand::
1005 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1007 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1010 // One of "cases" BB.
1011 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1013 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1014 if (cBB->isSuccessor(PHIBB)) {
1015 PHI->addOperand(MachineOperand::
1016 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1018 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1023 SDB->BitTestCases.clear();
1025 // If the JumpTable record is filled in, then we need to emit a jump table.
1026 // Updating the PHI nodes is tricky in this case, since we need to determine
1027 // whether the PHI is a successor of the range check MBB or the jump table MBB
1028 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1029 // Lower header first, if it wasn't already lowered
1030 if (!SDB->JTCases[i].first.Emitted) {
1031 // Set the current basic block to the mbb we wish to insert the code into
1032 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1033 FuncInfo->InsertPt = FuncInfo->MBB->end();
1035 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1037 CurDAG->setRoot(SDB->getRoot());
1039 CodeGenAndEmitDAG();
1042 // Set the current basic block to the mbb we wish to insert the code into
1043 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1044 FuncInfo->InsertPt = FuncInfo->MBB->end();
1046 SDB->visitJumpTable(SDB->JTCases[i].second);
1047 CurDAG->setRoot(SDB->getRoot());
1049 CodeGenAndEmitDAG();
1052 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1054 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1055 MachineBasicBlock *PHIBB = PHI->getParent();
1056 assert(PHI->isPHI() &&
1057 "This is not a machine PHI node that we are updating!");
1058 // "default" BB. We can go there only from header BB.
1059 if (PHIBB == SDB->JTCases[i].second.Default) {
1061 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1064 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1066 // JT BB. Just iterate over successors here
1067 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1069 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1071 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1075 SDB->JTCases.clear();
1077 // If the switch block involved a branch to one of the actual successors, we
1078 // need to update PHI nodes in that block.
1079 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1080 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1081 assert(PHI->isPHI() &&
1082 "This is not a machine PHI node that we are updating!");
1083 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1085 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1086 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1090 // If we generated any switch lowering information, build and codegen any
1091 // additional DAGs necessary.
1092 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1093 // Set the current basic block to the mbb we wish to insert the code into
1094 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1095 FuncInfo->InsertPt = FuncInfo->MBB->end();
1097 // Determine the unique successors.
1098 SmallVector<MachineBasicBlock *, 2> Succs;
1099 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1100 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1101 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1103 // Emit the code. Note that this could result in ThisBB being split, so
1104 // we need to check for updates.
1105 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1106 CurDAG->setRoot(SDB->getRoot());
1108 CodeGenAndEmitDAG();
1109 ThisBB = FuncInfo->MBB;
1111 // Handle any PHI nodes in successors of this chunk, as if we were coming
1112 // from the original BB before switch expansion. Note that PHI nodes can
1113 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1114 // handle them the right number of times.
1115 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1116 FuncInfo->MBB = Succs[i];
1117 FuncInfo->InsertPt = FuncInfo->MBB->end();
1118 // FuncInfo->MBB may have been removed from the CFG if a branch was
1120 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1121 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1122 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1124 // This value for this PHI node is recorded in PHINodesToUpdate.
1125 for (unsigned pn = 0; ; ++pn) {
1126 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1127 "Didn't find PHI entry!");
1128 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1129 Phi->addOperand(MachineOperand::
1130 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1132 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1140 SDB->SwitchCases.clear();
1144 /// Create the scheduler. If a specific scheduler was specified
1145 /// via the SchedulerRegistry, use it, otherwise select the
1146 /// one preferred by the target.
1148 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1149 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1153 RegisterScheduler::setDefault(Ctor);
1156 return Ctor(this, OptLevel);
1159 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1160 return new ScheduleHazardRecognizer();
1163 //===----------------------------------------------------------------------===//
1164 // Helper functions used by the generated instruction selector.
1165 //===----------------------------------------------------------------------===//
1166 // Calls to these methods are generated by tblgen.
1168 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1169 /// the dag combiner simplified the 255, we still want to match. RHS is the
1170 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1171 /// specified in the .td file (e.g. 255).
1172 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1173 int64_t DesiredMaskS) const {
1174 const APInt &ActualMask = RHS->getAPIntValue();
1175 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1177 // If the actual mask exactly matches, success!
1178 if (ActualMask == DesiredMask)
1181 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1182 if (ActualMask.intersects(~DesiredMask))
1185 // Otherwise, the DAG Combiner may have proven that the value coming in is
1186 // either already zero or is not demanded. Check for known zero input bits.
1187 APInt NeededMask = DesiredMask & ~ActualMask;
1188 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1191 // TODO: check to see if missing bits are just not demanded.
1193 // Otherwise, this pattern doesn't match.
1197 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1198 /// the dag combiner simplified the 255, we still want to match. RHS is the
1199 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1200 /// specified in the .td file (e.g. 255).
1201 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1202 int64_t DesiredMaskS) const {
1203 const APInt &ActualMask = RHS->getAPIntValue();
1204 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1206 // If the actual mask exactly matches, success!
1207 if (ActualMask == DesiredMask)
1210 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1211 if (ActualMask.intersects(~DesiredMask))
1214 // Otherwise, the DAG Combiner may have proven that the value coming in is
1215 // either already zero or is not demanded. Check for known zero input bits.
1216 APInt NeededMask = DesiredMask & ~ActualMask;
1218 APInt KnownZero, KnownOne;
1219 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1221 // If all the missing bits in the or are already known to be set, match!
1222 if ((NeededMask & KnownOne) == NeededMask)
1225 // TODO: check to see if missing bits are just not demanded.
1227 // Otherwise, this pattern doesn't match.
1232 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1233 /// by tblgen. Others should not call it.
1234 void SelectionDAGISel::
1235 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1236 std::vector<SDValue> InOps;
1237 std::swap(InOps, Ops);
1239 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1240 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1241 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1242 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1244 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1245 if (InOps[e-1].getValueType() == MVT::Flag)
1246 --e; // Don't process a flag operand if it is here.
1249 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1250 if (!InlineAsm::isMemKind(Flags)) {
1251 // Just skip over this operand, copying the operands verbatim.
1252 Ops.insert(Ops.end(), InOps.begin()+i,
1253 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1254 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1256 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1257 "Memory operand with multiple values?");
1258 // Otherwise, this is a memory operand. Ask the target to select it.
1259 std::vector<SDValue> SelOps;
1260 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1261 report_fatal_error("Could not match memory address. Inline asm"
1264 // Add this to the output node.
1266 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1267 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1268 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1273 // Add the flag input back if present.
1274 if (e != InOps.size())
1275 Ops.push_back(InOps.back());
1278 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1281 static SDNode *findFlagUse(SDNode *N) {
1282 unsigned FlagResNo = N->getNumValues()-1;
1283 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1284 SDUse &Use = I.getUse();
1285 if (Use.getResNo() == FlagResNo)
1286 return Use.getUser();
1291 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1292 /// This function recursively traverses up the operand chain, ignoring
1294 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1295 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1296 bool IgnoreChains) {
1297 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1298 // greater than all of its (recursive) operands. If we scan to a point where
1299 // 'use' is smaller than the node we're scanning for, then we know we will
1302 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1303 // happen because we scan down to newly selected nodes in the case of flag
1305 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1308 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1309 // won't fail if we scan it again.
1310 if (!Visited.insert(Use))
1313 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1314 // Ignore chain uses, they are validated by HandleMergeInputChains.
1315 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1318 SDNode *N = Use->getOperand(i).getNode();
1320 if (Use == ImmedUse || Use == Root)
1321 continue; // We are not looking for immediate use.
1326 // Traverse up the operand chain.
1327 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1333 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1334 /// operand node N of U during instruction selection that starts at Root.
1335 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1336 SDNode *Root) const {
1337 if (OptLevel == CodeGenOpt::None) return false;
1338 return N.hasOneUse();
1341 /// IsLegalToFold - Returns true if the specific operand node N of
1342 /// U can be folded during instruction selection that starts at Root.
1343 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1344 CodeGenOpt::Level OptLevel,
1345 bool IgnoreChains) {
1346 if (OptLevel == CodeGenOpt::None) return false;
1348 // If Root use can somehow reach N through a path that that doesn't contain
1349 // U then folding N would create a cycle. e.g. In the following
1350 // diagram, Root can reach N through X. If N is folded into into Root, then
1351 // X is both a predecessor and a successor of U.
1362 // * indicates nodes to be folded together.
1364 // If Root produces a flag, then it gets (even more) interesting. Since it
1365 // will be "glued" together with its flag use in the scheduler, we need to
1366 // check if it might reach N.
1385 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1386 // (call it Fold), then X is a predecessor of FU and a successor of
1387 // Fold. But since Fold and FU are flagged together, this will create
1388 // a cycle in the scheduling graph.
1390 // If the node has flags, walk down the graph to the "lowest" node in the
1392 EVT VT = Root->getValueType(Root->getNumValues()-1);
1393 while (VT == MVT::Flag) {
1394 SDNode *FU = findFlagUse(Root);
1398 VT = Root->getValueType(Root->getNumValues()-1);
1400 // If our query node has a flag result with a use, we've walked up it. If
1401 // the user (which has already been selected) has a chain or indirectly uses
1402 // the chain, our WalkChainUsers predicate will not consider it. Because of
1403 // this, we cannot ignore chains in this predicate.
1404 IgnoreChains = false;
1408 SmallPtrSet<SDNode*, 16> Visited;
1409 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1412 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1413 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1414 SelectInlineAsmMemoryOperands(Ops);
1416 std::vector<EVT> VTs;
1417 VTs.push_back(MVT::Other);
1418 VTs.push_back(MVT::Flag);
1419 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1420 VTs, &Ops[0], Ops.size());
1422 return New.getNode();
1425 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1426 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1429 /// GetVBR - decode a vbr encoding whose top bit is set.
1430 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1431 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1432 assert(Val >= 128 && "Not a VBR");
1433 Val &= 127; // Remove first vbr bit.
1438 NextBits = MatcherTable[Idx++];
1439 Val |= (NextBits&127) << Shift;
1441 } while (NextBits & 128);
1447 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1448 /// interior flag and chain results to use the new flag and chain results.
1449 void SelectionDAGISel::
1450 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1451 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1453 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1454 bool isMorphNodeTo) {
1455 SmallVector<SDNode*, 4> NowDeadNodes;
1457 ISelUpdater ISU(ISelPosition);
1459 // Now that all the normal results are replaced, we replace the chain and
1460 // flag results if present.
1461 if (!ChainNodesMatched.empty()) {
1462 assert(InputChain.getNode() != 0 &&
1463 "Matched input chains but didn't produce a chain");
1464 // Loop over all of the nodes we matched that produced a chain result.
1465 // Replace all the chain results with the final chain we ended up with.
1466 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1467 SDNode *ChainNode = ChainNodesMatched[i];
1469 // If this node was already deleted, don't look at it.
1470 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1473 // Don't replace the results of the root node if we're doing a
1475 if (ChainNode == NodeToMatch && isMorphNodeTo)
1478 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1479 if (ChainVal.getValueType() == MVT::Flag)
1480 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1481 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1482 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1484 // If the node became dead and we haven't already seen it, delete it.
1485 if (ChainNode->use_empty() &&
1486 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1487 NowDeadNodes.push_back(ChainNode);
1491 // If the result produces a flag, update any flag results in the matched
1492 // pattern with the flag result.
1493 if (InputFlag.getNode() != 0) {
1494 // Handle any interior nodes explicitly marked.
1495 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1496 SDNode *FRN = FlagResultNodesMatched[i];
1498 // If this node was already deleted, don't look at it.
1499 if (FRN->getOpcode() == ISD::DELETED_NODE)
1502 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1503 "Doesn't have a flag result");
1504 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1507 // If the node became dead and we haven't already seen it, delete it.
1508 if (FRN->use_empty() &&
1509 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1510 NowDeadNodes.push_back(FRN);
1514 if (!NowDeadNodes.empty())
1515 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1517 DEBUG(errs() << "ISEL: Match complete!\n");
1523 CR_LeadsToInteriorNode
1526 /// WalkChainUsers - Walk down the users of the specified chained node that is
1527 /// part of the pattern we're matching, looking at all of the users we find.
1528 /// This determines whether something is an interior node, whether we have a
1529 /// non-pattern node in between two pattern nodes (which prevent folding because
1530 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1531 /// between pattern nodes (in which case the TF becomes part of the pattern).
1533 /// The walk we do here is guaranteed to be small because we quickly get down to
1534 /// already selected nodes "below" us.
1536 WalkChainUsers(SDNode *ChainedNode,
1537 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1538 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1539 ChainResult Result = CR_Simple;
1541 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1542 E = ChainedNode->use_end(); UI != E; ++UI) {
1543 // Make sure the use is of the chain, not some other value we produce.
1544 if (UI.getUse().getValueType() != MVT::Other) continue;
1548 // If we see an already-selected machine node, then we've gone beyond the
1549 // pattern that we're selecting down into the already selected chunk of the
1551 if (User->isMachineOpcode() ||
1552 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1555 if (User->getOpcode() == ISD::CopyToReg ||
1556 User->getOpcode() == ISD::CopyFromReg ||
1557 User->getOpcode() == ISD::INLINEASM ||
1558 User->getOpcode() == ISD::EH_LABEL) {
1559 // If their node ID got reset to -1 then they've already been selected.
1560 // Treat them like a MachineOpcode.
1561 if (User->getNodeId() == -1)
1565 // If we have a TokenFactor, we handle it specially.
1566 if (User->getOpcode() != ISD::TokenFactor) {
1567 // If the node isn't a token factor and isn't part of our pattern, then it
1568 // must be a random chained node in between two nodes we're selecting.
1569 // This happens when we have something like:
1574 // Because we structurally match the load/store as a read/modify/write,
1575 // but the call is chained between them. We cannot fold in this case
1576 // because it would induce a cycle in the graph.
1577 if (!std::count(ChainedNodesInPattern.begin(),
1578 ChainedNodesInPattern.end(), User))
1579 return CR_InducesCycle;
1581 // Otherwise we found a node that is part of our pattern. For example in:
1585 // This would happen when we're scanning down from the load and see the
1586 // store as a user. Record that there is a use of ChainedNode that is
1587 // part of the pattern and keep scanning uses.
1588 Result = CR_LeadsToInteriorNode;
1589 InteriorChainedNodes.push_back(User);
1593 // If we found a TokenFactor, there are two cases to consider: first if the
1594 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1595 // uses of the TF are in our pattern) we just want to ignore it. Second,
1596 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1602 // | \ DAG's like cheese
1605 // [TokenFactor] [Op]
1612 // In this case, the TokenFactor becomes part of our match and we rewrite it
1613 // as a new TokenFactor.
1615 // To distinguish these two cases, do a recursive walk down the uses.
1616 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1618 // If the uses of the TokenFactor are just already-selected nodes, ignore
1619 // it, it is "below" our pattern.
1621 case CR_InducesCycle:
1622 // If the uses of the TokenFactor lead to nodes that are not part of our
1623 // pattern that are not selected, folding would turn this into a cycle,
1625 return CR_InducesCycle;
1626 case CR_LeadsToInteriorNode:
1627 break; // Otherwise, keep processing.
1630 // Okay, we know we're in the interesting interior case. The TokenFactor
1631 // is now going to be considered part of the pattern so that we rewrite its
1632 // uses (it may have uses that are not part of the pattern) with the
1633 // ultimate chain result of the generated code. We will also add its chain
1634 // inputs as inputs to the ultimate TokenFactor we create.
1635 Result = CR_LeadsToInteriorNode;
1636 ChainedNodesInPattern.push_back(User);
1637 InteriorChainedNodes.push_back(User);
1644 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1645 /// operation for when the pattern matched at least one node with a chains. The
1646 /// input vector contains a list of all of the chained nodes that we match. We
1647 /// must determine if this is a valid thing to cover (i.e. matching it won't
1648 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1649 /// be used as the input node chain for the generated nodes.
1651 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1652 SelectionDAG *CurDAG) {
1653 // Walk all of the chained nodes we've matched, recursively scanning down the
1654 // users of the chain result. This adds any TokenFactor nodes that are caught
1655 // in between chained nodes to the chained and interior nodes list.
1656 SmallVector<SDNode*, 3> InteriorChainedNodes;
1657 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1658 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1659 InteriorChainedNodes) == CR_InducesCycle)
1660 return SDValue(); // Would induce a cycle.
1663 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1664 // that we are interested in. Form our input TokenFactor node.
1665 SmallVector<SDValue, 3> InputChains;
1666 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1667 // Add the input chain of this node to the InputChains list (which will be
1668 // the operands of the generated TokenFactor) if it's not an interior node.
1669 SDNode *N = ChainNodesMatched[i];
1670 if (N->getOpcode() != ISD::TokenFactor) {
1671 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1674 // Otherwise, add the input chain.
1675 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1676 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1677 InputChains.push_back(InChain);
1681 // If we have a token factor, we want to add all inputs of the token factor
1682 // that are not part of the pattern we're matching.
1683 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1684 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1685 N->getOperand(op).getNode()))
1686 InputChains.push_back(N->getOperand(op));
1691 if (InputChains.size() == 1)
1692 return InputChains[0];
1693 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1694 MVT::Other, &InputChains[0], InputChains.size());
1697 /// MorphNode - Handle morphing a node in place for the selector.
1698 SDNode *SelectionDAGISel::
1699 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1700 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1701 // It is possible we're using MorphNodeTo to replace a node with no
1702 // normal results with one that has a normal result (or we could be
1703 // adding a chain) and the input could have flags and chains as well.
1704 // In this case we need to shift the operands down.
1705 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1706 // than the old isel though.
1707 int OldFlagResultNo = -1, OldChainResultNo = -1;
1709 unsigned NTMNumResults = Node->getNumValues();
1710 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1711 OldFlagResultNo = NTMNumResults-1;
1712 if (NTMNumResults != 1 &&
1713 Node->getValueType(NTMNumResults-2) == MVT::Other)
1714 OldChainResultNo = NTMNumResults-2;
1715 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1716 OldChainResultNo = NTMNumResults-1;
1718 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1719 // that this deletes operands of the old node that become dead.
1720 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1722 // MorphNodeTo can operate in two ways: if an existing node with the
1723 // specified operands exists, it can just return it. Otherwise, it
1724 // updates the node in place to have the requested operands.
1726 // If we updated the node in place, reset the node ID. To the isel,
1727 // this should be just like a newly allocated machine node.
1731 unsigned ResNumResults = Res->getNumValues();
1732 // Move the flag if needed.
1733 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1734 (unsigned)OldFlagResultNo != ResNumResults-1)
1735 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1736 SDValue(Res, ResNumResults-1));
1738 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1741 // Move the chain reference if needed.
1742 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1743 (unsigned)OldChainResultNo != ResNumResults-1)
1744 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1745 SDValue(Res, ResNumResults-1));
1747 // Otherwise, no replacement happened because the node already exists. Replace
1748 // Uses of the old node with the new one.
1750 CurDAG->ReplaceAllUsesWith(Node, Res);
1755 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1756 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1757 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1759 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1760 // Accept if it is exactly the same as a previously recorded node.
1761 unsigned RecNo = MatcherTable[MatcherIndex++];
1762 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1763 return N == RecordedNodes[RecNo].first;
1766 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1767 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1768 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1769 SelectionDAGISel &SDISel) {
1770 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1773 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1774 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1775 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1776 SelectionDAGISel &SDISel, SDNode *N) {
1777 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1780 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1781 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1783 uint16_t Opc = MatcherTable[MatcherIndex++];
1784 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1785 return N->getOpcode() == Opc;
1788 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1789 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1790 SDValue N, const TargetLowering &TLI) {
1791 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1792 if (N.getValueType() == VT) return true;
1794 // Handle the case when VT is iPTR.
1795 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1798 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1799 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1800 SDValue N, const TargetLowering &TLI,
1802 if (ChildNo >= N.getNumOperands())
1803 return false; // Match fails if out of range child #.
1804 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1808 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1809 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1811 return cast<CondCodeSDNode>(N)->get() ==
1812 (ISD::CondCode)MatcherTable[MatcherIndex++];
1815 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1816 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1817 SDValue N, const TargetLowering &TLI) {
1818 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1819 if (cast<VTSDNode>(N)->getVT() == VT)
1822 // Handle the case when VT is iPTR.
1823 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1826 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1827 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1829 int64_t Val = MatcherTable[MatcherIndex++];
1831 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1833 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1834 return C != 0 && C->getSExtValue() == Val;
1837 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1838 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1839 SDValue N, SelectionDAGISel &SDISel) {
1840 int64_t Val = MatcherTable[MatcherIndex++];
1842 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1844 if (N->getOpcode() != ISD::AND) return false;
1846 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1847 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1850 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1851 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1852 SDValue N, SelectionDAGISel &SDISel) {
1853 int64_t Val = MatcherTable[MatcherIndex++];
1855 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1857 if (N->getOpcode() != ISD::OR) return false;
1859 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1860 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1863 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1864 /// scope, evaluate the current node. If the current predicate is known to
1865 /// fail, set Result=true and return anything. If the current predicate is
1866 /// known to pass, set Result=false and return the MatcherIndex to continue
1867 /// with. If the current predicate is unknown, set Result=false and return the
1868 /// MatcherIndex to continue with.
1869 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1870 unsigned Index, SDValue N,
1871 bool &Result, SelectionDAGISel &SDISel,
1872 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1873 switch (Table[Index++]) {
1876 return Index-1; // Could not evaluate this predicate.
1877 case SelectionDAGISel::OPC_CheckSame:
1878 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1880 case SelectionDAGISel::OPC_CheckPatternPredicate:
1881 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1883 case SelectionDAGISel::OPC_CheckPredicate:
1884 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1886 case SelectionDAGISel::OPC_CheckOpcode:
1887 Result = !::CheckOpcode(Table, Index, N.getNode());
1889 case SelectionDAGISel::OPC_CheckType:
1890 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1892 case SelectionDAGISel::OPC_CheckChild0Type:
1893 case SelectionDAGISel::OPC_CheckChild1Type:
1894 case SelectionDAGISel::OPC_CheckChild2Type:
1895 case SelectionDAGISel::OPC_CheckChild3Type:
1896 case SelectionDAGISel::OPC_CheckChild4Type:
1897 case SelectionDAGISel::OPC_CheckChild5Type:
1898 case SelectionDAGISel::OPC_CheckChild6Type:
1899 case SelectionDAGISel::OPC_CheckChild7Type:
1900 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1901 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1903 case SelectionDAGISel::OPC_CheckCondCode:
1904 Result = !::CheckCondCode(Table, Index, N);
1906 case SelectionDAGISel::OPC_CheckValueType:
1907 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1909 case SelectionDAGISel::OPC_CheckInteger:
1910 Result = !::CheckInteger(Table, Index, N);
1912 case SelectionDAGISel::OPC_CheckAndImm:
1913 Result = !::CheckAndImm(Table, Index, N, SDISel);
1915 case SelectionDAGISel::OPC_CheckOrImm:
1916 Result = !::CheckOrImm(Table, Index, N, SDISel);
1924 /// FailIndex - If this match fails, this is the index to continue with.
1927 /// NodeStack - The node stack when the scope was formed.
1928 SmallVector<SDValue, 4> NodeStack;
1930 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1931 unsigned NumRecordedNodes;
1933 /// NumMatchedMemRefs - The number of matched memref entries.
1934 unsigned NumMatchedMemRefs;
1936 /// InputChain/InputFlag - The current chain/flag
1937 SDValue InputChain, InputFlag;
1939 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1940 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1945 SDNode *SelectionDAGISel::
1946 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1947 unsigned TableSize) {
1948 // FIXME: Should these even be selected? Handle these cases in the caller?
1949 switch (NodeToMatch->getOpcode()) {
1952 case ISD::EntryToken: // These nodes remain the same.
1953 case ISD::BasicBlock:
1955 //case ISD::VALUETYPE:
1956 //case ISD::CONDCODE:
1957 case ISD::HANDLENODE:
1958 case ISD::MDNODE_SDNODE:
1959 case ISD::TargetConstant:
1960 case ISD::TargetConstantFP:
1961 case ISD::TargetConstantPool:
1962 case ISD::TargetFrameIndex:
1963 case ISD::TargetExternalSymbol:
1964 case ISD::TargetBlockAddress:
1965 case ISD::TargetJumpTable:
1966 case ISD::TargetGlobalTLSAddress:
1967 case ISD::TargetGlobalAddress:
1968 case ISD::TokenFactor:
1969 case ISD::CopyFromReg:
1970 case ISD::CopyToReg:
1972 NodeToMatch->setNodeId(-1); // Mark selected.
1974 case ISD::AssertSext:
1975 case ISD::AssertZext:
1976 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1977 NodeToMatch->getOperand(0));
1979 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1980 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1983 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1985 // Set up the node stack with NodeToMatch as the only node on the stack.
1986 SmallVector<SDValue, 8> NodeStack;
1987 SDValue N = SDValue(NodeToMatch, 0);
1988 NodeStack.push_back(N);
1990 // MatchScopes - Scopes used when matching, if a match failure happens, this
1991 // indicates where to continue checking.
1992 SmallVector<MatchScope, 8> MatchScopes;
1994 // RecordedNodes - This is the set of nodes that have been recorded by the
1995 // state machine. The second value is the parent of the node, or null if the
1996 // root is recorded.
1997 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
1999 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2001 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2003 // These are the current input chain and flag for use when generating nodes.
2004 // Various Emit operations change these. For example, emitting a copytoreg
2005 // uses and updates these.
2006 SDValue InputChain, InputFlag;
2008 // ChainNodesMatched - If a pattern matches nodes that have input/output
2009 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2010 // which ones they are. The result is captured into this list so that we can
2011 // update the chain results when the pattern is complete.
2012 SmallVector<SDNode*, 3> ChainNodesMatched;
2013 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2015 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2016 NodeToMatch->dump(CurDAG);
2019 // Determine where to start the interpreter. Normally we start at opcode #0,
2020 // but if the state machine starts with an OPC_SwitchOpcode, then we
2021 // accelerate the first lookup (which is guaranteed to be hot) with the
2022 // OpcodeOffset table.
2023 unsigned MatcherIndex = 0;
2025 if (!OpcodeOffset.empty()) {
2026 // Already computed the OpcodeOffset table, just index into it.
2027 if (N.getOpcode() < OpcodeOffset.size())
2028 MatcherIndex = OpcodeOffset[N.getOpcode()];
2029 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2031 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2032 // Otherwise, the table isn't computed, but the state machine does start
2033 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2034 // is the first time we're selecting an instruction.
2037 // Get the size of this case.
2038 unsigned CaseSize = MatcherTable[Idx++];
2040 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2041 if (CaseSize == 0) break;
2043 // Get the opcode, add the index to the table.
2044 uint16_t Opc = MatcherTable[Idx++];
2045 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2046 if (Opc >= OpcodeOffset.size())
2047 OpcodeOffset.resize((Opc+1)*2);
2048 OpcodeOffset[Opc] = Idx;
2052 // Okay, do the lookup for the first opcode.
2053 if (N.getOpcode() < OpcodeOffset.size())
2054 MatcherIndex = OpcodeOffset[N.getOpcode()];
2058 assert(MatcherIndex < TableSize && "Invalid index");
2060 unsigned CurrentOpcodeIndex = MatcherIndex;
2062 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2065 // Okay, the semantics of this operation are that we should push a scope
2066 // then evaluate the first child. However, pushing a scope only to have
2067 // the first check fail (which then pops it) is inefficient. If we can
2068 // determine immediately that the first check (or first several) will
2069 // immediately fail, don't even bother pushing a scope for them.
2073 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2074 if (NumToSkip & 128)
2075 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2076 // Found the end of the scope with no match.
2077 if (NumToSkip == 0) {
2082 FailIndex = MatcherIndex+NumToSkip;
2084 unsigned MatcherIndexOfPredicate = MatcherIndex;
2085 (void)MatcherIndexOfPredicate; // silence warning.
2087 // If we can't evaluate this predicate without pushing a scope (e.g. if
2088 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2089 // push the scope and evaluate the full predicate chain.
2091 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2092 Result, *this, RecordedNodes);
2096 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2097 << "index " << MatcherIndexOfPredicate
2098 << ", continuing at " << FailIndex << "\n");
2099 ++NumDAGIselRetries;
2101 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2102 // move to the next case.
2103 MatcherIndex = FailIndex;
2106 // If the whole scope failed to match, bail.
2107 if (FailIndex == 0) break;
2109 // Push a MatchScope which indicates where to go if the first child fails
2111 MatchScope NewEntry;
2112 NewEntry.FailIndex = FailIndex;
2113 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2114 NewEntry.NumRecordedNodes = RecordedNodes.size();
2115 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2116 NewEntry.InputChain = InputChain;
2117 NewEntry.InputFlag = InputFlag;
2118 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2119 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2120 MatchScopes.push_back(NewEntry);
2123 case OPC_RecordNode: {
2124 // Remember this node, it may end up being an operand in the pattern.
2126 if (NodeStack.size() > 1)
2127 Parent = NodeStack[NodeStack.size()-2].getNode();
2128 RecordedNodes.push_back(std::make_pair(N, Parent));
2132 case OPC_RecordChild0: case OPC_RecordChild1:
2133 case OPC_RecordChild2: case OPC_RecordChild3:
2134 case OPC_RecordChild4: case OPC_RecordChild5:
2135 case OPC_RecordChild6: case OPC_RecordChild7: {
2136 unsigned ChildNo = Opcode-OPC_RecordChild0;
2137 if (ChildNo >= N.getNumOperands())
2138 break; // Match fails if out of range child #.
2140 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2144 case OPC_RecordMemRef:
2145 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2148 case OPC_CaptureFlagInput:
2149 // If the current node has an input flag, capture it in InputFlag.
2150 if (N->getNumOperands() != 0 &&
2151 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2152 InputFlag = N->getOperand(N->getNumOperands()-1);
2155 case OPC_MoveChild: {
2156 unsigned ChildNo = MatcherTable[MatcherIndex++];
2157 if (ChildNo >= N.getNumOperands())
2158 break; // Match fails if out of range child #.
2159 N = N.getOperand(ChildNo);
2160 NodeStack.push_back(N);
2164 case OPC_MoveParent:
2165 // Pop the current node off the NodeStack.
2166 NodeStack.pop_back();
2167 assert(!NodeStack.empty() && "Node stack imbalance!");
2168 N = NodeStack.back();
2172 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2174 case OPC_CheckPatternPredicate:
2175 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2177 case OPC_CheckPredicate:
2178 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2182 case OPC_CheckComplexPat: {
2183 unsigned CPNum = MatcherTable[MatcherIndex++];
2184 unsigned RecNo = MatcherTable[MatcherIndex++];
2185 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2186 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2187 RecordedNodes[RecNo].first, CPNum,
2192 case OPC_CheckOpcode:
2193 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2197 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2200 case OPC_SwitchOpcode: {
2201 unsigned CurNodeOpcode = N.getOpcode();
2202 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2205 // Get the size of this case.
2206 CaseSize = MatcherTable[MatcherIndex++];
2208 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2209 if (CaseSize == 0) break;
2211 uint16_t Opc = MatcherTable[MatcherIndex++];
2212 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2214 // If the opcode matches, then we will execute this case.
2215 if (CurNodeOpcode == Opc)
2218 // Otherwise, skip over this case.
2219 MatcherIndex += CaseSize;
2222 // If no cases matched, bail out.
2223 if (CaseSize == 0) break;
2225 // Otherwise, execute the case we found.
2226 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2227 << " to " << MatcherIndex << "\n");
2231 case OPC_SwitchType: {
2232 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2233 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2236 // Get the size of this case.
2237 CaseSize = MatcherTable[MatcherIndex++];
2239 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2240 if (CaseSize == 0) break;
2242 MVT::SimpleValueType CaseVT =
2243 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2244 if (CaseVT == MVT::iPTR)
2245 CaseVT = TLI.getPointerTy().SimpleTy;
2247 // If the VT matches, then we will execute this case.
2248 if (CurNodeVT == CaseVT)
2251 // Otherwise, skip over this case.
2252 MatcherIndex += CaseSize;
2255 // If no cases matched, bail out.
2256 if (CaseSize == 0) break;
2258 // Otherwise, execute the case we found.
2259 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2260 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2263 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2264 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2265 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2266 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2267 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2268 Opcode-OPC_CheckChild0Type))
2271 case OPC_CheckCondCode:
2272 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2274 case OPC_CheckValueType:
2275 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2277 case OPC_CheckInteger:
2278 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2280 case OPC_CheckAndImm:
2281 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2283 case OPC_CheckOrImm:
2284 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2287 case OPC_CheckFoldableChainNode: {
2288 assert(NodeStack.size() != 1 && "No parent node");
2289 // Verify that all intermediate nodes between the root and this one have
2291 bool HasMultipleUses = false;
2292 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2293 if (!NodeStack[i].hasOneUse()) {
2294 HasMultipleUses = true;
2297 if (HasMultipleUses) break;
2299 // Check to see that the target thinks this is profitable to fold and that
2300 // we can fold it without inducing cycles in the graph.
2301 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2303 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2304 NodeToMatch, OptLevel,
2305 true/*We validate our own chains*/))
2310 case OPC_EmitInteger: {
2311 MVT::SimpleValueType VT =
2312 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2313 int64_t Val = MatcherTable[MatcherIndex++];
2315 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2316 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2317 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2320 case OPC_EmitRegister: {
2321 MVT::SimpleValueType VT =
2322 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2323 unsigned RegNo = MatcherTable[MatcherIndex++];
2324 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2325 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2329 case OPC_EmitConvertToTarget: {
2330 // Convert from IMM/FPIMM to target version.
2331 unsigned RecNo = MatcherTable[MatcherIndex++];
2332 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2333 SDValue Imm = RecordedNodes[RecNo].first;
2335 if (Imm->getOpcode() == ISD::Constant) {
2336 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2337 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2338 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2339 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2340 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2343 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2347 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2348 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2349 // These are space-optimized forms of OPC_EmitMergeInputChains.
2350 assert(InputChain.getNode() == 0 &&
2351 "EmitMergeInputChains should be the first chain producing node");
2352 assert(ChainNodesMatched.empty() &&
2353 "Should only have one EmitMergeInputChains per match");
2355 // Read all of the chained nodes.
2356 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2357 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2358 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2360 // FIXME: What if other value results of the node have uses not matched
2362 if (ChainNodesMatched.back() != NodeToMatch &&
2363 !RecordedNodes[RecNo].first.hasOneUse()) {
2364 ChainNodesMatched.clear();
2368 // Merge the input chains if they are not intra-pattern references.
2369 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2371 if (InputChain.getNode() == 0)
2372 break; // Failed to merge.
2376 case OPC_EmitMergeInputChains: {
2377 assert(InputChain.getNode() == 0 &&
2378 "EmitMergeInputChains should be the first chain producing node");
2379 // This node gets a list of nodes we matched in the input that have
2380 // chains. We want to token factor all of the input chains to these nodes
2381 // together. However, if any of the input chains is actually one of the
2382 // nodes matched in this pattern, then we have an intra-match reference.
2383 // Ignore these because the newly token factored chain should not refer to
2385 unsigned NumChains = MatcherTable[MatcherIndex++];
2386 assert(NumChains != 0 && "Can't TF zero chains");
2388 assert(ChainNodesMatched.empty() &&
2389 "Should only have one EmitMergeInputChains per match");
2391 // Read all of the chained nodes.
2392 for (unsigned i = 0; i != NumChains; ++i) {
2393 unsigned RecNo = MatcherTable[MatcherIndex++];
2394 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2395 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2397 // FIXME: What if other value results of the node have uses not matched
2399 if (ChainNodesMatched.back() != NodeToMatch &&
2400 !RecordedNodes[RecNo].first.hasOneUse()) {
2401 ChainNodesMatched.clear();
2406 // If the inner loop broke out, the match fails.
2407 if (ChainNodesMatched.empty())
2410 // Merge the input chains if they are not intra-pattern references.
2411 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2413 if (InputChain.getNode() == 0)
2414 break; // Failed to merge.
2419 case OPC_EmitCopyToReg: {
2420 unsigned RecNo = MatcherTable[MatcherIndex++];
2421 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2422 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2424 if (InputChain.getNode() == 0)
2425 InputChain = CurDAG->getEntryNode();
2427 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2428 DestPhysReg, RecordedNodes[RecNo].first,
2431 InputFlag = InputChain.getValue(1);
2435 case OPC_EmitNodeXForm: {
2436 unsigned XFormNo = MatcherTable[MatcherIndex++];
2437 unsigned RecNo = MatcherTable[MatcherIndex++];
2438 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2439 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2440 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2445 case OPC_MorphNodeTo: {
2446 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2447 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2448 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2449 // Get the result VT list.
2450 unsigned NumVTs = MatcherTable[MatcherIndex++];
2451 SmallVector<EVT, 4> VTs;
2452 for (unsigned i = 0; i != NumVTs; ++i) {
2453 MVT::SimpleValueType VT =
2454 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2455 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2459 if (EmitNodeInfo & OPFL_Chain)
2460 VTs.push_back(MVT::Other);
2461 if (EmitNodeInfo & OPFL_FlagOutput)
2462 VTs.push_back(MVT::Flag);
2464 // This is hot code, so optimize the two most common cases of 1 and 2
2467 if (VTs.size() == 1)
2468 VTList = CurDAG->getVTList(VTs[0]);
2469 else if (VTs.size() == 2)
2470 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2472 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2474 // Get the operand list.
2475 unsigned NumOps = MatcherTable[MatcherIndex++];
2476 SmallVector<SDValue, 8> Ops;
2477 for (unsigned i = 0; i != NumOps; ++i) {
2478 unsigned RecNo = MatcherTable[MatcherIndex++];
2480 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2482 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2483 Ops.push_back(RecordedNodes[RecNo].first);
2486 // If there are variadic operands to add, handle them now.
2487 if (EmitNodeInfo & OPFL_VariadicInfo) {
2488 // Determine the start index to copy from.
2489 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2490 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2491 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2492 "Invalid variadic node");
2493 // Copy all of the variadic operands, not including a potential flag
2495 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2497 SDValue V = NodeToMatch->getOperand(i);
2498 if (V.getValueType() == MVT::Flag) break;
2503 // If this has chain/flag inputs, add them.
2504 if (EmitNodeInfo & OPFL_Chain)
2505 Ops.push_back(InputChain);
2506 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2507 Ops.push_back(InputFlag);
2511 if (Opcode != OPC_MorphNodeTo) {
2512 // If this is a normal EmitNode command, just create the new node and
2513 // add the results to the RecordedNodes list.
2514 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2515 VTList, Ops.data(), Ops.size());
2517 // Add all the non-flag/non-chain results to the RecordedNodes list.
2518 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2519 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2520 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2525 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2529 // If the node had chain/flag results, update our notion of the current
2531 if (EmitNodeInfo & OPFL_FlagOutput) {
2532 InputFlag = SDValue(Res, VTs.size()-1);
2533 if (EmitNodeInfo & OPFL_Chain)
2534 InputChain = SDValue(Res, VTs.size()-2);
2535 } else if (EmitNodeInfo & OPFL_Chain)
2536 InputChain = SDValue(Res, VTs.size()-1);
2538 // If the OPFL_MemRefs flag is set on this node, slap all of the
2539 // accumulated memrefs onto it.
2541 // FIXME: This is vastly incorrect for patterns with multiple outputs
2542 // instructions that access memory and for ComplexPatterns that match
2544 if (EmitNodeInfo & OPFL_MemRefs) {
2545 MachineSDNode::mmo_iterator MemRefs =
2546 MF->allocateMemRefsArray(MatchedMemRefs.size());
2547 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2548 cast<MachineSDNode>(Res)
2549 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2553 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2554 << " node: "; Res->dump(CurDAG); errs() << "\n");
2556 // If this was a MorphNodeTo then we're completely done!
2557 if (Opcode == OPC_MorphNodeTo) {
2558 // Update chain and flag uses.
2559 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2560 InputFlag, FlagResultNodesMatched, true);
2567 case OPC_MarkFlagResults: {
2568 unsigned NumNodes = MatcherTable[MatcherIndex++];
2570 // Read and remember all the flag-result nodes.
2571 for (unsigned i = 0; i != NumNodes; ++i) {
2572 unsigned RecNo = MatcherTable[MatcherIndex++];
2574 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2576 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2577 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2582 case OPC_CompleteMatch: {
2583 // The match has been completed, and any new nodes (if any) have been
2584 // created. Patch up references to the matched dag to use the newly
2586 unsigned NumResults = MatcherTable[MatcherIndex++];
2588 for (unsigned i = 0; i != NumResults; ++i) {
2589 unsigned ResSlot = MatcherTable[MatcherIndex++];
2591 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2593 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2594 SDValue Res = RecordedNodes[ResSlot].first;
2596 assert(i < NodeToMatch->getNumValues() &&
2597 NodeToMatch->getValueType(i) != MVT::Other &&
2598 NodeToMatch->getValueType(i) != MVT::Flag &&
2599 "Invalid number of results to complete!");
2600 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2601 NodeToMatch->getValueType(i) == MVT::iPTR ||
2602 Res.getValueType() == MVT::iPTR ||
2603 NodeToMatch->getValueType(i).getSizeInBits() ==
2604 Res.getValueType().getSizeInBits()) &&
2605 "invalid replacement");
2606 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2609 // If the root node defines a flag, add it to the flag nodes to update
2611 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2612 FlagResultNodesMatched.push_back(NodeToMatch);
2614 // Update chain and flag uses.
2615 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2616 InputFlag, FlagResultNodesMatched, false);
2618 assert(NodeToMatch->use_empty() &&
2619 "Didn't replace all uses of the node?");
2621 // FIXME: We just return here, which interacts correctly with SelectRoot
2622 // above. We should fix this to not return an SDNode* anymore.
2627 // If the code reached this point, then the match failed. See if there is
2628 // another child to try in the current 'Scope', otherwise pop it until we
2629 // find a case to check.
2630 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2631 ++NumDAGIselRetries;
2633 if (MatchScopes.empty()) {
2634 CannotYetSelect(NodeToMatch);
2638 // Restore the interpreter state back to the point where the scope was
2640 MatchScope &LastScope = MatchScopes.back();
2641 RecordedNodes.resize(LastScope.NumRecordedNodes);
2643 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2644 N = NodeStack.back();
2646 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2647 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2648 MatcherIndex = LastScope.FailIndex;
2650 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2652 InputChain = LastScope.InputChain;
2653 InputFlag = LastScope.InputFlag;
2654 if (!LastScope.HasChainNodesMatched)
2655 ChainNodesMatched.clear();
2656 if (!LastScope.HasFlagResultNodesMatched)
2657 FlagResultNodesMatched.clear();
2659 // Check to see what the offset is at the new MatcherIndex. If it is zero
2660 // we have reached the end of this scope, otherwise we have another child
2661 // in the current scope to try.
2662 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2663 if (NumToSkip & 128)
2664 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2666 // If we have another child in this scope to match, update FailIndex and
2668 if (NumToSkip != 0) {
2669 LastScope.FailIndex = MatcherIndex+NumToSkip;
2673 // End of this scope, pop it and try the next child in the containing
2675 MatchScopes.pop_back();
2682 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2684 raw_string_ostream Msg(msg);
2685 Msg << "Cannot yet select: ";
2687 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2688 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2689 N->getOpcode() != ISD::INTRINSIC_VOID) {
2690 N->printrFull(Msg, CurDAG);
2692 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2694 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2695 if (iid < Intrinsic::num_intrinsics)
2696 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2697 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2698 Msg << "target intrinsic %" << TII->getName(iid);
2700 Msg << "unknown intrinsic #" << iid;
2702 report_fatal_error(Msg.str());
2705 char SelectionDAGISel::ID = 0;