1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/ADT/Statistic.h"
56 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
57 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
58 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
59 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
62 STATISTIC(NumBBWithOutOfOrderLineInfo,
63 "Number of blocks with out of order line number info");
64 STATISTIC(NumMBBWithOutOfOrderLineInfo,
65 "Number of machine blocks with out of order line number info");
69 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
70 cl::desc("Enable verbose messages in the \"fast\" "
71 "instruction selector"));
73 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
74 cl::desc("Enable abort calls when \"fast\" instruction fails"));
78 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the first "
82 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before legalize types"));
85 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
86 cl::desc("Pop up a window to show dags before legalize"));
88 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
89 cl::desc("Pop up a window to show dags before the second "
92 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
93 cl::desc("Pop up a window to show dags before the post legalize types"
94 " dag combine pass"));
96 ViewISelDAGs("view-isel-dags", cl::Hidden,
97 cl::desc("Pop up a window to show isel dags as they are selected"));
99 ViewSchedDAGs("view-sched-dags", cl::Hidden,
100 cl::desc("Pop up a window to show sched dags as they are processed"));
102 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
103 cl::desc("Pop up a window to show SUnit dags after they are processed"));
105 static const bool ViewDAGCombine1 = false,
106 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
107 ViewDAGCombine2 = false,
108 ViewDAGCombineLT = false,
109 ViewISelDAGs = false, ViewSchedDAGs = false,
110 ViewSUnitDAGs = false;
113 //===---------------------------------------------------------------------===//
115 /// RegisterScheduler class - Track the registration of instruction schedulers.
117 //===---------------------------------------------------------------------===//
118 MachinePassRegistry RegisterScheduler::Registry;
120 //===---------------------------------------------------------------------===//
122 /// ISHeuristic command line option for instruction schedulers.
124 //===---------------------------------------------------------------------===//
125 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
126 RegisterPassParser<RegisterScheduler> >
127 ISHeuristic("pre-RA-sched",
128 cl::init(&createDefaultScheduler),
129 cl::desc("Instruction schedulers available (before register"
132 static RegisterScheduler
133 defaultListDAGScheduler("default", "Best scheduler for the target",
134 createDefaultScheduler);
137 //===--------------------------------------------------------------------===//
138 /// createDefaultScheduler - This creates an instruction scheduler appropriate
140 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
141 CodeGenOpt::Level OptLevel) {
142 const TargetLowering &TLI = IS->getTargetLowering();
144 if (OptLevel == CodeGenOpt::None)
145 return createSourceListDAGScheduler(IS, OptLevel);
146 if (TLI.getSchedulingPreference() == Sched::Latency)
147 return createTDListDAGScheduler(IS, OptLevel);
148 if (TLI.getSchedulingPreference() == Sched::RegPressure)
149 return createBURRListDAGScheduler(IS, OptLevel);
150 if (TLI.getSchedulingPreference() == Sched::Hybrid)
151 return createHybridListDAGScheduler(IS, OptLevel);
152 assert(TLI.getSchedulingPreference() == Sched::ILP &&
153 "Unknown sched type!");
154 return createILPListDAGScheduler(IS, OptLevel);
158 // EmitInstrWithCustomInserter - This method should be implemented by targets
159 // that mark instructions with the 'usesCustomInserter' flag. These
160 // instructions are special in various ways, which require special support to
161 // insert. The specified MachineInstr is created but not inserted into any
162 // basic blocks, and this method is called to expand it into a sequence of
163 // instructions, potentially also creating new basic blocks and control flow.
164 // When new basic blocks are inserted and the edges from MBB to its successors
165 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
168 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
169 MachineBasicBlock *MBB) const {
171 dbgs() << "If a target marks an instruction with "
172 "'usesCustomInserter', it must implement "
173 "TargetLowering::EmitInstrWithCustomInserter!";
179 //===----------------------------------------------------------------------===//
180 // SelectionDAGISel code
181 //===----------------------------------------------------------------------===//
183 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
184 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
185 FuncInfo(new FunctionLoweringInfo(TLI)),
186 CurDAG(new SelectionDAG(tm)),
187 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
191 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
192 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
195 SelectionDAGISel::~SelectionDAGISel() {
201 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
202 AU.addRequired<AliasAnalysis>();
203 AU.addPreserved<AliasAnalysis>();
204 AU.addRequired<GCModuleInfo>();
205 AU.addPreserved<GCModuleInfo>();
206 MachineFunctionPass::getAnalysisUsage(AU);
209 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
210 /// other function that gcc recognizes as "returning twice". This is used to
211 /// limit code-gen optimizations on the machine function.
213 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
214 static bool FunctionCallsSetJmp(const Function *F) {
215 const Module *M = F->getParent();
216 static const char *ReturnsTwiceFns[] = {
226 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
228 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
229 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
230 if (!Callee->use_empty())
231 for (Value::const_use_iterator
232 I = Callee->use_begin(), E = Callee->use_end();
234 if (const CallInst *CI = dyn_cast<CallInst>(*I))
235 if (CI->getParent()->getParent() == F)
240 #undef NUM_RETURNS_TWICE_FNS
243 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
244 /// may trap on it. In this case we have to split the edge so that the path
245 /// through the predecessor block that doesn't go to the phi block doesn't
246 /// execute the possibly trapping instruction.
248 /// This is required for correctness, so it must be done at -O0.
250 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
251 // Loop for blocks with phi nodes.
252 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
253 PHINode *PN = dyn_cast<PHINode>(BB->begin());
254 if (PN == 0) continue;
257 // For each block with a PHI node, check to see if any of the input values
258 // are potentially trapping constant expressions. Constant expressions are
259 // the only potentially trapping value that can occur as the argument to a
261 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
262 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
263 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
264 if (CE == 0 || !CE->canTrap()) continue;
266 // The only case we have to worry about is when the edge is critical.
267 // Since this block has a PHI Node, we assume it has multiple input
268 // edges: check to see if the pred has multiple successors.
269 BasicBlock *Pred = PN->getIncomingBlock(i);
270 if (Pred->getTerminator()->getNumSuccessors() == 1)
273 // Okay, we have to split this edge.
274 SplitCriticalEdge(Pred->getTerminator(),
275 GetSuccessorNumber(Pred, BB), SDISel, true);
281 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
282 // Do some sanity-checking on the command-line options.
283 assert((!EnableFastISelVerbose || EnableFastISel) &&
284 "-fast-isel-verbose requires -fast-isel");
285 assert((!EnableFastISelAbort || EnableFastISel) &&
286 "-fast-isel-abort requires -fast-isel");
288 const Function &Fn = *mf.getFunction();
289 const TargetInstrInfo &TII = *TM.getInstrInfo();
290 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
293 RegInfo = &MF->getRegInfo();
294 AA = &getAnalysis<AliasAnalysis>();
295 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
297 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
299 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
302 FuncInfo->set(Fn, *MF);
305 SelectAllBasicBlocks(Fn);
307 // If the first basic block in the function has live ins that need to be
308 // copied into vregs, emit the copies into the top of the block before
309 // emitting the code for the block.
310 MachineBasicBlock *EntryMBB = MF->begin();
311 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
313 DenseMap<unsigned, unsigned> LiveInMap;
314 if (!FuncInfo->ArgDbgValues.empty())
315 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
316 E = RegInfo->livein_end(); LI != E; ++LI)
318 LiveInMap.insert(std::make_pair(LI->first, LI->second));
320 // Insert DBG_VALUE instructions for function arguments to the entry block.
321 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
322 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
323 unsigned Reg = MI->getOperand(0).getReg();
324 if (TargetRegisterInfo::isPhysicalRegister(Reg))
325 EntryMBB->insert(EntryMBB->begin(), MI);
327 MachineInstr *Def = RegInfo->getVRegDef(Reg);
328 MachineBasicBlock::iterator InsertPos = Def;
329 // FIXME: VR def may not be in entry block.
330 Def->getParent()->insert(llvm::next(InsertPos), MI);
333 // If Reg is live-in then update debug info to track its copy in a vreg.
334 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
335 if (LDI != LiveInMap.end()) {
336 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
337 MachineBasicBlock::iterator InsertPos = Def;
338 const MDNode *Variable =
339 MI->getOperand(MI->getNumOperands()-1).getMetadata();
340 unsigned Offset = MI->getOperand(1).getImm();
341 // Def is never a terminator here, so it is ok to increment InsertPos.
342 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
343 TII.get(TargetOpcode::DBG_VALUE))
344 .addReg(LDI->second, RegState::Debug)
345 .addImm(Offset).addMetadata(Variable);
347 // If this vreg is directly copied into an exported register then
348 // that COPY instructions also need DBG_VALUE, if it is the only
349 // user of LDI->second.
350 MachineInstr *CopyUseMI = NULL;
351 for (MachineRegisterInfo::use_iterator
352 UI = RegInfo->use_begin(LDI->second);
353 MachineInstr *UseMI = UI.skipInstruction();) {
354 if (UseMI->isDebugValue()) continue;
355 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
356 CopyUseMI = UseMI; continue;
358 // Otherwise this is another use or second copy use.
359 CopyUseMI = NULL; break;
362 MachineInstr *NewMI =
363 BuildMI(*MF, CopyUseMI->getDebugLoc(),
364 TII.get(TargetOpcode::DBG_VALUE))
365 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
366 .addImm(Offset).addMetadata(Variable);
367 EntryMBB->insertAfter(CopyUseMI, NewMI);
372 // Determine if there are any calls in this machine function.
373 MachineFrameInfo *MFI = MF->getFrameInfo();
374 if (!MFI->hasCalls()) {
375 for (MachineFunction::const_iterator
376 I = MF->begin(), E = MF->end(); I != E; ++I) {
377 const MachineBasicBlock *MBB = I;
378 for (MachineBasicBlock::const_iterator
379 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
380 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
382 // Operand 1 of an inline asm instruction indicates whether the asm
383 // needs stack or not.
384 if ((II->isInlineAsm() && II->getOperand(1).getImm()) ||
385 (TID.isCall() && !TID.isReturn())) {
386 MFI->setHasCalls(true);
394 // Determine if there is a call to setjmp in the machine function.
395 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
397 // Replace forward-declared registers with the registers containing
398 // the desired value.
399 MachineRegisterInfo &MRI = MF->getRegInfo();
400 for (DenseMap<unsigned, unsigned>::iterator
401 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
403 unsigned From = I->first;
404 unsigned To = I->second;
405 // If To is also scheduled to be replaced, find what its ultimate
408 DenseMap<unsigned, unsigned>::iterator J =
409 FuncInfo->RegFixups.find(To);
414 MRI.replaceRegWith(From, To);
417 // Release function-specific state. SDB and CurDAG are already cleared
425 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
426 BasicBlock::const_iterator End,
428 // Lower all of the non-terminator instructions. If a call is emitted
429 // as a tail call, cease emitting nodes for this block. Terminators
430 // are handled below.
431 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
434 // Make sure the root of the DAG is up-to-date.
435 CurDAG->setRoot(SDB->getControlRoot());
436 HadTailCall = SDB->HasTailCall;
439 // Final step, emit the lowered DAG as machine code.
444 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
445 SmallPtrSet<SDNode*, 128> VisitedNodes;
446 SmallVector<SDNode*, 128> Worklist;
448 Worklist.push_back(CurDAG->getRoot().getNode());
455 SDNode *N = Worklist.pop_back_val();
457 // If we've already seen this node, ignore it.
458 if (!VisitedNodes.insert(N))
461 // Otherwise, add all chain operands to the worklist.
462 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
463 if (N->getOperand(i).getValueType() == MVT::Other)
464 Worklist.push_back(N->getOperand(i).getNode());
466 // If this is a CopyToReg with a vreg dest, process it.
467 if (N->getOpcode() != ISD::CopyToReg)
470 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
471 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
474 // Ignore non-scalar or non-integer values.
475 SDValue Src = N->getOperand(2);
476 EVT SrcVT = Src.getValueType();
477 if (!SrcVT.isInteger() || SrcVT.isVector())
480 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
481 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
482 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
484 // Only install this information if it tells us something.
485 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
486 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
487 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
488 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
489 FunctionLoweringInfo::LiveOutInfo &LOI =
490 FuncInfo->LiveOutRegInfo[DestReg];
491 LOI.NumSignBits = NumSignBits;
492 LOI.KnownOne = KnownOne;
493 LOI.KnownZero = KnownZero;
495 } while (!Worklist.empty());
498 void SelectionDAGISel::CodeGenAndEmitDAG() {
499 std::string GroupName;
500 if (TimePassesIsEnabled)
501 GroupName = "Instruction Selection and Scheduling";
502 std::string BlockName;
503 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
504 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
506 BlockName = MF->getFunction()->getNameStr() + ":" +
507 FuncInfo->MBB->getBasicBlock()->getNameStr();
509 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
511 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
513 // Run the DAG combiner in pre-legalize mode.
515 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
516 CurDAG->Combine(Unrestricted, *AA, OptLevel);
519 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
521 // Second step, hack on the DAG until it only uses operations and types that
522 // the target supports.
523 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
528 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
529 Changed = CurDAG->LegalizeTypes();
532 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
535 if (ViewDAGCombineLT)
536 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
538 // Run the DAG combiner in post-type-legalize mode.
540 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
541 TimePassesIsEnabled);
542 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
545 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
550 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
551 Changed = CurDAG->LegalizeVectors();
556 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
557 CurDAG->LegalizeTypes();
560 if (ViewDAGCombineLT)
561 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
563 // Run the DAG combiner in post-type-legalize mode.
565 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
566 TimePassesIsEnabled);
567 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
570 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
574 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
577 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
578 CurDAG->Legalize(OptLevel);
581 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
583 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
585 // Run the DAG combiner in post-legalize mode.
587 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
588 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
591 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
593 if (OptLevel != CodeGenOpt::None)
594 ComputeLiveOutVRegInfo();
596 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
598 // Third, instruction select all of the operations to machine code, adding the
599 // code to the MachineBasicBlock.
601 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
602 DoInstructionSelection();
605 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
607 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
609 // Schedule machine code.
610 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
612 NamedRegionTimer T("Instruction Scheduling", GroupName,
613 TimePassesIsEnabled);
614 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
617 if (ViewSUnitDAGs) Scheduler->viewGraph();
619 // Emit machine code to BB. This can change 'BB' to the last block being
621 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
623 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
625 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
626 FuncInfo->InsertPt = Scheduler->InsertPos;
629 // If the block was split, make sure we update any references that are used to
630 // update PHI nodes later on.
631 if (FirstMBB != LastMBB)
632 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
634 // Free the scheduler state.
636 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
637 TimePassesIsEnabled);
641 // Free the SelectionDAG state, now that we're finished with it.
645 void SelectionDAGISel::DoInstructionSelection() {
646 DEBUG(errs() << "===== Instruction selection begins:\n");
650 // Select target instructions for the DAG.
652 // Number all nodes with a topological order and set DAGSize.
653 DAGSize = CurDAG->AssignTopologicalOrder();
655 // Create a dummy node (which is not added to allnodes), that adds
656 // a reference to the root node, preventing it from being deleted,
657 // and tracking any changes of the root.
658 HandleSDNode Dummy(CurDAG->getRoot());
659 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
662 // The AllNodes list is now topological-sorted. Visit the
663 // nodes by starting at the end of the list (the root of the
664 // graph) and preceding back toward the beginning (the entry
666 while (ISelPosition != CurDAG->allnodes_begin()) {
667 SDNode *Node = --ISelPosition;
668 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
669 // but there are currently some corner cases that it misses. Also, this
670 // makes it theoretically possible to disable the DAGCombiner.
671 if (Node->use_empty())
674 SDNode *ResNode = Select(Node);
676 // FIXME: This is pretty gross. 'Select' should be changed to not return
677 // anything at all and this code should be nuked with a tactical strike.
679 // If node should not be replaced, continue with the next one.
680 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
684 ReplaceUses(Node, ResNode);
686 // If after the replacement this node is not used any more,
687 // remove this dead node.
688 if (Node->use_empty()) { // Don't delete EntryToken, etc.
689 ISelUpdater ISU(ISelPosition);
690 CurDAG->RemoveDeadNode(Node, &ISU);
694 CurDAG->setRoot(Dummy.getValue());
697 DEBUG(errs() << "===== Instruction selection ends:\n");
699 PostprocessISelDAG();
702 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
703 /// do other setup for EH landing-pad blocks.
704 void SelectionDAGISel::PrepareEHLandingPad() {
705 // Add a label to mark the beginning of the landing pad. Deletion of the
706 // landing pad can thus be detected via the MachineModuleInfo.
707 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
709 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
710 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
713 // Mark exception register as live in.
714 unsigned Reg = TLI.getExceptionAddressRegister();
715 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
717 // Mark exception selector register as live in.
718 Reg = TLI.getExceptionSelectorRegister();
719 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
721 // FIXME: Hack around an exception handling flaw (PR1508): the personality
722 // function and list of typeids logically belong to the invoke (or, if you
723 // like, the basic block containing the invoke), and need to be associated
724 // with it in the dwarf exception handling tables. Currently however the
725 // information is provided by an intrinsic (eh.selector) that can be moved
726 // to unexpected places by the optimizers: if the unwind edge is critical,
727 // then breaking it can result in the intrinsics being in the successor of
728 // the landing pad, not the landing pad itself. This results
729 // in exceptions not being caught because no typeids are associated with
730 // the invoke. This may not be the only way things can go wrong, but it
731 // is the only way we try to work around for the moment.
732 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
733 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
735 if (Br && Br->isUnconditional()) { // Critical edge?
736 BasicBlock::const_iterator I, E;
737 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
738 if (isa<EHSelectorInst>(I))
742 // No catch info found - try to extract some from the successor.
743 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
750 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
752 // Don't try to fold volatile loads. Target has to deal with alignment
754 if (LI->isVolatile()) return false;
756 // Figure out which vreg this is going into.
757 unsigned LoadReg = FastIS->getRegForValue(LI);
758 assert(LoadReg && "Load isn't already assigned a vreg? ");
760 // Check to see what the uses of this vreg are. If it has no uses, or more
761 // than one use (at the machine instr level) then we can't fold it.
762 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
763 if (RI == RegInfo->reg_end())
766 // See if there is exactly one use of the vreg. If there are multiple uses,
767 // then the instruction got lowered to multiple machine instructions or the
768 // use of the loaded value ended up being multiple operands of the result, in
769 // either case, we can't fold this.
770 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
771 if (PostRI != RegInfo->reg_end())
774 assert(RI.getOperand().isUse() &&
775 "The only use of the vreg must be a use, we haven't emitted the def!");
777 // Ask the target to try folding the load.
778 return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI);
782 /// CheckLineNumbers - Check if basic block instructions follow source order
784 static void CheckLineNumbers(const BasicBlock *BB) {
787 for (BasicBlock::const_iterator BI = BB->begin(),
788 BE = BB->end(); BI != BE; ++BI) {
789 const DebugLoc DL = BI->getDebugLoc();
790 if (DL.isUnknown()) continue;
791 unsigned L = DL.getLine();
792 unsigned C = DL.getCol();
793 if (L < Line || (L == Line && C < Col)) {
794 ++NumBBWithOutOfOrderLineInfo;
802 /// CheckLineNumbers - Check if machine basic block instructions follow source
804 static void CheckLineNumbers(const MachineBasicBlock *MBB) {
807 for (MachineBasicBlock::const_iterator MBI = MBB->begin(),
808 MBE = MBB->end(); MBI != MBE; ++MBI) {
809 const DebugLoc DL = MBI->getDebugLoc();
810 if (DL.isUnknown()) continue;
811 unsigned L = DL.getLine();
812 unsigned C = DL.getCol();
813 if (L < Line || (L == Line && C < Col)) {
814 ++NumMBBWithOutOfOrderLineInfo;
823 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
824 // Initialize the Fast-ISel state, if needed.
825 FastISel *FastIS = 0;
827 FastIS = TLI.createFastISel(*FuncInfo);
829 // Iterate over all basic blocks in the function.
830 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
831 const BasicBlock *LLVMBB = &*I;
833 CheckLineNumbers(LLVMBB);
835 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
836 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
838 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
839 BasicBlock::const_iterator const End = LLVMBB->end();
840 BasicBlock::const_iterator BI = End;
842 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
844 // Setup an EH landing-pad block.
845 if (FuncInfo->MBB->isLandingPad())
846 PrepareEHLandingPad();
848 // Lower any arguments needed in this block if this is the entry block.
849 if (LLVMBB == &Fn.getEntryBlock())
850 LowerArguments(LLVMBB);
852 // Before doing SelectionDAG ISel, see if FastISel has been requested.
854 FastIS->startNewBlock();
856 // Emit code for any incoming arguments. This must happen before
857 // beginning FastISel on the entry block.
858 if (LLVMBB == &Fn.getEntryBlock()) {
859 CurDAG->setRoot(SDB->getControlRoot());
863 // If we inserted any instructions at the beginning, make a note of
864 // where they are, so we can be sure to emit subsequent instructions
866 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
867 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
869 FastIS->setLastLocalValue(0);
872 // Do FastISel on as many instructions as possible.
873 for (; BI != Begin; --BI) {
874 const Instruction *Inst = llvm::prior(BI);
876 // If we no longer require this instruction, skip it.
877 if (!Inst->mayWriteToMemory() &&
878 !isa<TerminatorInst>(Inst) &&
879 !isa<DbgInfoIntrinsic>(Inst) &&
880 !FuncInfo->isExportedInst(Inst))
883 // Bottom-up: reset the insert pos at the top, after any local-value
885 FastIS->recomputeInsertPt();
887 // Try to select the instruction with FastISel.
888 if (FastIS->SelectInstruction(Inst)) {
889 // If fast isel succeeded, check to see if there is a single-use
890 // non-volatile load right before the selected instruction, and see if
891 // the load is used by the instruction. If so, try to fold it.
892 const Instruction *BeforeInst = 0;
894 BeforeInst = llvm::prior(llvm::prior(BI));
895 if (BeforeInst && isa<LoadInst>(BeforeInst) &&
896 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst &&
897 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS)) {
898 // If we succeeded, don't re-select the load.
904 // Then handle certain instructions as single-LLVM-Instruction blocks.
905 if (isa<CallInst>(Inst)) {
906 ++NumFastIselFailures;
907 if (EnableFastISelVerbose || EnableFastISelAbort) {
908 dbgs() << "FastISel missed call: ";
912 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
913 unsigned &R = FuncInfo->ValueMap[Inst];
915 R = FuncInfo->CreateRegs(Inst->getType());
918 bool HadTailCall = false;
919 SelectBasicBlock(Inst, BI, HadTailCall);
921 // If the call was emitted as a tail call, we're done with the block.
930 // Otherwise, give up on FastISel for the rest of the block.
931 // For now, be a little lenient about non-branch terminators.
932 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
933 ++NumFastIselFailures;
934 if (EnableFastISelVerbose || EnableFastISelAbort) {
935 dbgs() << "FastISel miss: ";
938 if (EnableFastISelAbort)
939 // The "fast" selector couldn't handle something and bailed.
940 // For the purpose of debugging, just abort.
941 llvm_unreachable("FastISel didn't select the entire block");
946 FastIS->recomputeInsertPt();
954 // Run SelectionDAG instruction selection on the remainder of the block
955 // not handled by FastISel. If FastISel is not run, this is the entire
958 SelectBasicBlock(Begin, BI, HadTailCall);
961 FuncInfo->PHINodesToUpdate.clear();
966 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end();
968 CheckLineNumbers(MBI);
973 SelectionDAGISel::FinishBasicBlock() {
975 DEBUG(dbgs() << "Total amount of phi nodes to update: "
976 << FuncInfo->PHINodesToUpdate.size() << "\n";
977 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
978 dbgs() << "Node " << i << " : ("
979 << FuncInfo->PHINodesToUpdate[i].first
980 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
982 // Next, now that we know what the last MBB the LLVM BB expanded is, update
983 // PHI nodes in successors.
984 if (SDB->SwitchCases.empty() &&
985 SDB->JTCases.empty() &&
986 SDB->BitTestCases.empty()) {
987 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
988 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
989 assert(PHI->isPHI() &&
990 "This is not a machine PHI node that we are updating!");
991 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
994 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
995 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1000 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1001 // Lower header first, if it wasn't already lowered
1002 if (!SDB->BitTestCases[i].Emitted) {
1003 // Set the current basic block to the mbb we wish to insert the code into
1004 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1005 FuncInfo->InsertPt = FuncInfo->MBB->end();
1007 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1008 CurDAG->setRoot(SDB->getRoot());
1010 CodeGenAndEmitDAG();
1013 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1014 // Set the current basic block to the mbb we wish to insert the code into
1015 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1016 FuncInfo->InsertPt = FuncInfo->MBB->end();
1019 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1020 SDB->BitTestCases[i].Reg,
1021 SDB->BitTestCases[i].Cases[j],
1024 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1025 SDB->BitTestCases[i].Reg,
1026 SDB->BitTestCases[i].Cases[j],
1030 CurDAG->setRoot(SDB->getRoot());
1032 CodeGenAndEmitDAG();
1036 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1038 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1039 MachineBasicBlock *PHIBB = PHI->getParent();
1040 assert(PHI->isPHI() &&
1041 "This is not a machine PHI node that we are updating!");
1042 // This is "default" BB. We have two jumps to it. From "header" BB and
1043 // from last "case" BB.
1044 if (PHIBB == SDB->BitTestCases[i].Default) {
1045 PHI->addOperand(MachineOperand::
1046 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1048 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1049 PHI->addOperand(MachineOperand::
1050 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1052 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1055 // One of "cases" BB.
1056 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1058 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1059 if (cBB->isSuccessor(PHIBB)) {
1060 PHI->addOperand(MachineOperand::
1061 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1063 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1068 SDB->BitTestCases.clear();
1070 // If the JumpTable record is filled in, then we need to emit a jump table.
1071 // Updating the PHI nodes is tricky in this case, since we need to determine
1072 // whether the PHI is a successor of the range check MBB or the jump table MBB
1073 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1074 // Lower header first, if it wasn't already lowered
1075 if (!SDB->JTCases[i].first.Emitted) {
1076 // Set the current basic block to the mbb we wish to insert the code into
1077 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1078 FuncInfo->InsertPt = FuncInfo->MBB->end();
1080 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1082 CurDAG->setRoot(SDB->getRoot());
1084 CodeGenAndEmitDAG();
1087 // Set the current basic block to the mbb we wish to insert the code into
1088 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1089 FuncInfo->InsertPt = FuncInfo->MBB->end();
1091 SDB->visitJumpTable(SDB->JTCases[i].second);
1092 CurDAG->setRoot(SDB->getRoot());
1094 CodeGenAndEmitDAG();
1097 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1099 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1100 MachineBasicBlock *PHIBB = PHI->getParent();
1101 assert(PHI->isPHI() &&
1102 "This is not a machine PHI node that we are updating!");
1103 // "default" BB. We can go there only from header BB.
1104 if (PHIBB == SDB->JTCases[i].second.Default) {
1106 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1109 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1111 // JT BB. Just iterate over successors here
1112 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1114 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1116 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1120 SDB->JTCases.clear();
1122 // If the switch block involved a branch to one of the actual successors, we
1123 // need to update PHI nodes in that block.
1124 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1125 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1126 assert(PHI->isPHI() &&
1127 "This is not a machine PHI node that we are updating!");
1128 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1130 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1131 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1135 // If we generated any switch lowering information, build and codegen any
1136 // additional DAGs necessary.
1137 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1138 // Set the current basic block to the mbb we wish to insert the code into
1139 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1140 FuncInfo->InsertPt = FuncInfo->MBB->end();
1142 // Determine the unique successors.
1143 SmallVector<MachineBasicBlock *, 2> Succs;
1144 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1145 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1146 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1148 // Emit the code. Note that this could result in ThisBB being split, so
1149 // we need to check for updates.
1150 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1151 CurDAG->setRoot(SDB->getRoot());
1153 CodeGenAndEmitDAG();
1154 ThisBB = FuncInfo->MBB;
1156 // Handle any PHI nodes in successors of this chunk, as if we were coming
1157 // from the original BB before switch expansion. Note that PHI nodes can
1158 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1159 // handle them the right number of times.
1160 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1161 FuncInfo->MBB = Succs[i];
1162 FuncInfo->InsertPt = FuncInfo->MBB->end();
1163 // FuncInfo->MBB may have been removed from the CFG if a branch was
1165 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1166 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1167 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1169 // This value for this PHI node is recorded in PHINodesToUpdate.
1170 for (unsigned pn = 0; ; ++pn) {
1171 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1172 "Didn't find PHI entry!");
1173 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1174 Phi->addOperand(MachineOperand::
1175 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1177 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1185 SDB->SwitchCases.clear();
1189 /// Create the scheduler. If a specific scheduler was specified
1190 /// via the SchedulerRegistry, use it, otherwise select the
1191 /// one preferred by the target.
1193 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1194 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1198 RegisterScheduler::setDefault(Ctor);
1201 return Ctor(this, OptLevel);
1204 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1205 return new ScheduleHazardRecognizer();
1208 //===----------------------------------------------------------------------===//
1209 // Helper functions used by the generated instruction selector.
1210 //===----------------------------------------------------------------------===//
1211 // Calls to these methods are generated by tblgen.
1213 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1214 /// the dag combiner simplified the 255, we still want to match. RHS is the
1215 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1216 /// specified in the .td file (e.g. 255).
1217 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1218 int64_t DesiredMaskS) const {
1219 const APInt &ActualMask = RHS->getAPIntValue();
1220 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1222 // If the actual mask exactly matches, success!
1223 if (ActualMask == DesiredMask)
1226 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1227 if (ActualMask.intersects(~DesiredMask))
1230 // Otherwise, the DAG Combiner may have proven that the value coming in is
1231 // either already zero or is not demanded. Check for known zero input bits.
1232 APInt NeededMask = DesiredMask & ~ActualMask;
1233 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1236 // TODO: check to see if missing bits are just not demanded.
1238 // Otherwise, this pattern doesn't match.
1242 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1243 /// the dag combiner simplified the 255, we still want to match. RHS is the
1244 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1245 /// specified in the .td file (e.g. 255).
1246 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1247 int64_t DesiredMaskS) const {
1248 const APInt &ActualMask = RHS->getAPIntValue();
1249 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1251 // If the actual mask exactly matches, success!
1252 if (ActualMask == DesiredMask)
1255 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1256 if (ActualMask.intersects(~DesiredMask))
1259 // Otherwise, the DAG Combiner may have proven that the value coming in is
1260 // either already zero or is not demanded. Check for known zero input bits.
1261 APInt NeededMask = DesiredMask & ~ActualMask;
1263 APInt KnownZero, KnownOne;
1264 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1266 // If all the missing bits in the or are already known to be set, match!
1267 if ((NeededMask & KnownOne) == NeededMask)
1270 // TODO: check to see if missing bits are just not demanded.
1272 // Otherwise, this pattern doesn't match.
1277 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1278 /// by tblgen. Others should not call it.
1279 void SelectionDAGISel::
1280 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1281 std::vector<SDValue> InOps;
1282 std::swap(InOps, Ops);
1284 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1285 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1286 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1287 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1289 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1290 if (InOps[e-1].getValueType() == MVT::Flag)
1291 --e; // Don't process a flag operand if it is here.
1294 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1295 if (!InlineAsm::isMemKind(Flags)) {
1296 // Just skip over this operand, copying the operands verbatim.
1297 Ops.insert(Ops.end(), InOps.begin()+i,
1298 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1299 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1301 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1302 "Memory operand with multiple values?");
1303 // Otherwise, this is a memory operand. Ask the target to select it.
1304 std::vector<SDValue> SelOps;
1305 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1306 report_fatal_error("Could not match memory address. Inline asm"
1309 // Add this to the output node.
1311 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1312 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1313 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1318 // Add the flag input back if present.
1319 if (e != InOps.size())
1320 Ops.push_back(InOps.back());
1323 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1326 static SDNode *findFlagUse(SDNode *N) {
1327 unsigned FlagResNo = N->getNumValues()-1;
1328 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1329 SDUse &Use = I.getUse();
1330 if (Use.getResNo() == FlagResNo)
1331 return Use.getUser();
1336 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1337 /// This function recursively traverses up the operand chain, ignoring
1339 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1340 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1341 bool IgnoreChains) {
1342 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1343 // greater than all of its (recursive) operands. If we scan to a point where
1344 // 'use' is smaller than the node we're scanning for, then we know we will
1347 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1348 // happen because we scan down to newly selected nodes in the case of flag
1350 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1353 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1354 // won't fail if we scan it again.
1355 if (!Visited.insert(Use))
1358 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1359 // Ignore chain uses, they are validated by HandleMergeInputChains.
1360 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1363 SDNode *N = Use->getOperand(i).getNode();
1365 if (Use == ImmedUse || Use == Root)
1366 continue; // We are not looking for immediate use.
1371 // Traverse up the operand chain.
1372 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1378 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1379 /// operand node N of U during instruction selection that starts at Root.
1380 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1381 SDNode *Root) const {
1382 if (OptLevel == CodeGenOpt::None) return false;
1383 return N.hasOneUse();
1386 /// IsLegalToFold - Returns true if the specific operand node N of
1387 /// U can be folded during instruction selection that starts at Root.
1388 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1389 CodeGenOpt::Level OptLevel,
1390 bool IgnoreChains) {
1391 if (OptLevel == CodeGenOpt::None) return false;
1393 // If Root use can somehow reach N through a path that that doesn't contain
1394 // U then folding N would create a cycle. e.g. In the following
1395 // diagram, Root can reach N through X. If N is folded into into Root, then
1396 // X is both a predecessor and a successor of U.
1407 // * indicates nodes to be folded together.
1409 // If Root produces a flag, then it gets (even more) interesting. Since it
1410 // will be "glued" together with its flag use in the scheduler, we need to
1411 // check if it might reach N.
1430 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1431 // (call it Fold), then X is a predecessor of FU and a successor of
1432 // Fold. But since Fold and FU are flagged together, this will create
1433 // a cycle in the scheduling graph.
1435 // If the node has flags, walk down the graph to the "lowest" node in the
1437 EVT VT = Root->getValueType(Root->getNumValues()-1);
1438 while (VT == MVT::Flag) {
1439 SDNode *FU = findFlagUse(Root);
1443 VT = Root->getValueType(Root->getNumValues()-1);
1445 // If our query node has a flag result with a use, we've walked up it. If
1446 // the user (which has already been selected) has a chain or indirectly uses
1447 // the chain, our WalkChainUsers predicate will not consider it. Because of
1448 // this, we cannot ignore chains in this predicate.
1449 IgnoreChains = false;
1453 SmallPtrSet<SDNode*, 16> Visited;
1454 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1457 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1458 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1459 SelectInlineAsmMemoryOperands(Ops);
1461 std::vector<EVT> VTs;
1462 VTs.push_back(MVT::Other);
1463 VTs.push_back(MVT::Flag);
1464 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1465 VTs, &Ops[0], Ops.size());
1467 return New.getNode();
1470 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1471 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1474 /// GetVBR - decode a vbr encoding whose top bit is set.
1475 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1476 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1477 assert(Val >= 128 && "Not a VBR");
1478 Val &= 127; // Remove first vbr bit.
1483 NextBits = MatcherTable[Idx++];
1484 Val |= (NextBits&127) << Shift;
1486 } while (NextBits & 128);
1492 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1493 /// interior flag and chain results to use the new flag and chain results.
1494 void SelectionDAGISel::
1495 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1496 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1498 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1499 bool isMorphNodeTo) {
1500 SmallVector<SDNode*, 4> NowDeadNodes;
1502 ISelUpdater ISU(ISelPosition);
1504 // Now that all the normal results are replaced, we replace the chain and
1505 // flag results if present.
1506 if (!ChainNodesMatched.empty()) {
1507 assert(InputChain.getNode() != 0 &&
1508 "Matched input chains but didn't produce a chain");
1509 // Loop over all of the nodes we matched that produced a chain result.
1510 // Replace all the chain results with the final chain we ended up with.
1511 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1512 SDNode *ChainNode = ChainNodesMatched[i];
1514 // If this node was already deleted, don't look at it.
1515 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1518 // Don't replace the results of the root node if we're doing a
1520 if (ChainNode == NodeToMatch && isMorphNodeTo)
1523 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1524 if (ChainVal.getValueType() == MVT::Flag)
1525 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1526 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1527 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1529 // If the node became dead and we haven't already seen it, delete it.
1530 if (ChainNode->use_empty() &&
1531 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1532 NowDeadNodes.push_back(ChainNode);
1536 // If the result produces a flag, update any flag results in the matched
1537 // pattern with the flag result.
1538 if (InputFlag.getNode() != 0) {
1539 // Handle any interior nodes explicitly marked.
1540 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1541 SDNode *FRN = FlagResultNodesMatched[i];
1543 // If this node was already deleted, don't look at it.
1544 if (FRN->getOpcode() == ISD::DELETED_NODE)
1547 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1548 "Doesn't have a flag result");
1549 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1552 // If the node became dead and we haven't already seen it, delete it.
1553 if (FRN->use_empty() &&
1554 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1555 NowDeadNodes.push_back(FRN);
1559 if (!NowDeadNodes.empty())
1560 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1562 DEBUG(errs() << "ISEL: Match complete!\n");
1568 CR_LeadsToInteriorNode
1571 /// WalkChainUsers - Walk down the users of the specified chained node that is
1572 /// part of the pattern we're matching, looking at all of the users we find.
1573 /// This determines whether something is an interior node, whether we have a
1574 /// non-pattern node in between two pattern nodes (which prevent folding because
1575 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1576 /// between pattern nodes (in which case the TF becomes part of the pattern).
1578 /// The walk we do here is guaranteed to be small because we quickly get down to
1579 /// already selected nodes "below" us.
1581 WalkChainUsers(SDNode *ChainedNode,
1582 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1583 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1584 ChainResult Result = CR_Simple;
1586 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1587 E = ChainedNode->use_end(); UI != E; ++UI) {
1588 // Make sure the use is of the chain, not some other value we produce.
1589 if (UI.getUse().getValueType() != MVT::Other) continue;
1593 // If we see an already-selected machine node, then we've gone beyond the
1594 // pattern that we're selecting down into the already selected chunk of the
1596 if (User->isMachineOpcode() ||
1597 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1600 if (User->getOpcode() == ISD::CopyToReg ||
1601 User->getOpcode() == ISD::CopyFromReg ||
1602 User->getOpcode() == ISD::INLINEASM ||
1603 User->getOpcode() == ISD::EH_LABEL) {
1604 // If their node ID got reset to -1 then they've already been selected.
1605 // Treat them like a MachineOpcode.
1606 if (User->getNodeId() == -1)
1610 // If we have a TokenFactor, we handle it specially.
1611 if (User->getOpcode() != ISD::TokenFactor) {
1612 // If the node isn't a token factor and isn't part of our pattern, then it
1613 // must be a random chained node in between two nodes we're selecting.
1614 // This happens when we have something like:
1619 // Because we structurally match the load/store as a read/modify/write,
1620 // but the call is chained between them. We cannot fold in this case
1621 // because it would induce a cycle in the graph.
1622 if (!std::count(ChainedNodesInPattern.begin(),
1623 ChainedNodesInPattern.end(), User))
1624 return CR_InducesCycle;
1626 // Otherwise we found a node that is part of our pattern. For example in:
1630 // This would happen when we're scanning down from the load and see the
1631 // store as a user. Record that there is a use of ChainedNode that is
1632 // part of the pattern and keep scanning uses.
1633 Result = CR_LeadsToInteriorNode;
1634 InteriorChainedNodes.push_back(User);
1638 // If we found a TokenFactor, there are two cases to consider: first if the
1639 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1640 // uses of the TF are in our pattern) we just want to ignore it. Second,
1641 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1647 // | \ DAG's like cheese
1650 // [TokenFactor] [Op]
1657 // In this case, the TokenFactor becomes part of our match and we rewrite it
1658 // as a new TokenFactor.
1660 // To distinguish these two cases, do a recursive walk down the uses.
1661 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1663 // If the uses of the TokenFactor are just already-selected nodes, ignore
1664 // it, it is "below" our pattern.
1666 case CR_InducesCycle:
1667 // If the uses of the TokenFactor lead to nodes that are not part of our
1668 // pattern that are not selected, folding would turn this into a cycle,
1670 return CR_InducesCycle;
1671 case CR_LeadsToInteriorNode:
1672 break; // Otherwise, keep processing.
1675 // Okay, we know we're in the interesting interior case. The TokenFactor
1676 // is now going to be considered part of the pattern so that we rewrite its
1677 // uses (it may have uses that are not part of the pattern) with the
1678 // ultimate chain result of the generated code. We will also add its chain
1679 // inputs as inputs to the ultimate TokenFactor we create.
1680 Result = CR_LeadsToInteriorNode;
1681 ChainedNodesInPattern.push_back(User);
1682 InteriorChainedNodes.push_back(User);
1689 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1690 /// operation for when the pattern matched at least one node with a chains. The
1691 /// input vector contains a list of all of the chained nodes that we match. We
1692 /// must determine if this is a valid thing to cover (i.e. matching it won't
1693 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1694 /// be used as the input node chain for the generated nodes.
1696 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1697 SelectionDAG *CurDAG) {
1698 // Walk all of the chained nodes we've matched, recursively scanning down the
1699 // users of the chain result. This adds any TokenFactor nodes that are caught
1700 // in between chained nodes to the chained and interior nodes list.
1701 SmallVector<SDNode*, 3> InteriorChainedNodes;
1702 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1703 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1704 InteriorChainedNodes) == CR_InducesCycle)
1705 return SDValue(); // Would induce a cycle.
1708 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1709 // that we are interested in. Form our input TokenFactor node.
1710 SmallVector<SDValue, 3> InputChains;
1711 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1712 // Add the input chain of this node to the InputChains list (which will be
1713 // the operands of the generated TokenFactor) if it's not an interior node.
1714 SDNode *N = ChainNodesMatched[i];
1715 if (N->getOpcode() != ISD::TokenFactor) {
1716 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1719 // Otherwise, add the input chain.
1720 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1721 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1722 InputChains.push_back(InChain);
1726 // If we have a token factor, we want to add all inputs of the token factor
1727 // that are not part of the pattern we're matching.
1728 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1729 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1730 N->getOperand(op).getNode()))
1731 InputChains.push_back(N->getOperand(op));
1736 if (InputChains.size() == 1)
1737 return InputChains[0];
1738 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1739 MVT::Other, &InputChains[0], InputChains.size());
1742 /// MorphNode - Handle morphing a node in place for the selector.
1743 SDNode *SelectionDAGISel::
1744 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1745 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1746 // It is possible we're using MorphNodeTo to replace a node with no
1747 // normal results with one that has a normal result (or we could be
1748 // adding a chain) and the input could have flags and chains as well.
1749 // In this case we need to shift the operands down.
1750 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1751 // than the old isel though.
1752 int OldFlagResultNo = -1, OldChainResultNo = -1;
1754 unsigned NTMNumResults = Node->getNumValues();
1755 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1756 OldFlagResultNo = NTMNumResults-1;
1757 if (NTMNumResults != 1 &&
1758 Node->getValueType(NTMNumResults-2) == MVT::Other)
1759 OldChainResultNo = NTMNumResults-2;
1760 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1761 OldChainResultNo = NTMNumResults-1;
1763 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1764 // that this deletes operands of the old node that become dead.
1765 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1767 // MorphNodeTo can operate in two ways: if an existing node with the
1768 // specified operands exists, it can just return it. Otherwise, it
1769 // updates the node in place to have the requested operands.
1771 // If we updated the node in place, reset the node ID. To the isel,
1772 // this should be just like a newly allocated machine node.
1776 unsigned ResNumResults = Res->getNumValues();
1777 // Move the flag if needed.
1778 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1779 (unsigned)OldFlagResultNo != ResNumResults-1)
1780 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1781 SDValue(Res, ResNumResults-1));
1783 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1786 // Move the chain reference if needed.
1787 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1788 (unsigned)OldChainResultNo != ResNumResults-1)
1789 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1790 SDValue(Res, ResNumResults-1));
1792 // Otherwise, no replacement happened because the node already exists. Replace
1793 // Uses of the old node with the new one.
1795 CurDAG->ReplaceAllUsesWith(Node, Res);
1800 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1801 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1802 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1804 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1805 // Accept if it is exactly the same as a previously recorded node.
1806 unsigned RecNo = MatcherTable[MatcherIndex++];
1807 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1808 return N == RecordedNodes[RecNo].first;
1811 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1812 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1813 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1814 SelectionDAGISel &SDISel) {
1815 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1818 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1819 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1820 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1821 SelectionDAGISel &SDISel, SDNode *N) {
1822 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1825 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1826 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1828 uint16_t Opc = MatcherTable[MatcherIndex++];
1829 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1830 return N->getOpcode() == Opc;
1833 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1834 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1835 SDValue N, const TargetLowering &TLI) {
1836 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1837 if (N.getValueType() == VT) return true;
1839 // Handle the case when VT is iPTR.
1840 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1843 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1844 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1845 SDValue N, const TargetLowering &TLI,
1847 if (ChildNo >= N.getNumOperands())
1848 return false; // Match fails if out of range child #.
1849 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1853 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1854 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1856 return cast<CondCodeSDNode>(N)->get() ==
1857 (ISD::CondCode)MatcherTable[MatcherIndex++];
1860 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1861 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1862 SDValue N, const TargetLowering &TLI) {
1863 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1864 if (cast<VTSDNode>(N)->getVT() == VT)
1867 // Handle the case when VT is iPTR.
1868 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1871 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1872 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1874 int64_t Val = MatcherTable[MatcherIndex++];
1876 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1878 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1879 return C != 0 && C->getSExtValue() == Val;
1882 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1883 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1884 SDValue N, SelectionDAGISel &SDISel) {
1885 int64_t Val = MatcherTable[MatcherIndex++];
1887 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1889 if (N->getOpcode() != ISD::AND) return false;
1891 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1892 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1895 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1896 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1897 SDValue N, SelectionDAGISel &SDISel) {
1898 int64_t Val = MatcherTable[MatcherIndex++];
1900 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1902 if (N->getOpcode() != ISD::OR) return false;
1904 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1905 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1908 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1909 /// scope, evaluate the current node. If the current predicate is known to
1910 /// fail, set Result=true and return anything. If the current predicate is
1911 /// known to pass, set Result=false and return the MatcherIndex to continue
1912 /// with. If the current predicate is unknown, set Result=false and return the
1913 /// MatcherIndex to continue with.
1914 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1915 unsigned Index, SDValue N,
1916 bool &Result, SelectionDAGISel &SDISel,
1917 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1918 switch (Table[Index++]) {
1921 return Index-1; // Could not evaluate this predicate.
1922 case SelectionDAGISel::OPC_CheckSame:
1923 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1925 case SelectionDAGISel::OPC_CheckPatternPredicate:
1926 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1928 case SelectionDAGISel::OPC_CheckPredicate:
1929 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1931 case SelectionDAGISel::OPC_CheckOpcode:
1932 Result = !::CheckOpcode(Table, Index, N.getNode());
1934 case SelectionDAGISel::OPC_CheckType:
1935 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1937 case SelectionDAGISel::OPC_CheckChild0Type:
1938 case SelectionDAGISel::OPC_CheckChild1Type:
1939 case SelectionDAGISel::OPC_CheckChild2Type:
1940 case SelectionDAGISel::OPC_CheckChild3Type:
1941 case SelectionDAGISel::OPC_CheckChild4Type:
1942 case SelectionDAGISel::OPC_CheckChild5Type:
1943 case SelectionDAGISel::OPC_CheckChild6Type:
1944 case SelectionDAGISel::OPC_CheckChild7Type:
1945 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1946 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1948 case SelectionDAGISel::OPC_CheckCondCode:
1949 Result = !::CheckCondCode(Table, Index, N);
1951 case SelectionDAGISel::OPC_CheckValueType:
1952 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1954 case SelectionDAGISel::OPC_CheckInteger:
1955 Result = !::CheckInteger(Table, Index, N);
1957 case SelectionDAGISel::OPC_CheckAndImm:
1958 Result = !::CheckAndImm(Table, Index, N, SDISel);
1960 case SelectionDAGISel::OPC_CheckOrImm:
1961 Result = !::CheckOrImm(Table, Index, N, SDISel);
1969 /// FailIndex - If this match fails, this is the index to continue with.
1972 /// NodeStack - The node stack when the scope was formed.
1973 SmallVector<SDValue, 4> NodeStack;
1975 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1976 unsigned NumRecordedNodes;
1978 /// NumMatchedMemRefs - The number of matched memref entries.
1979 unsigned NumMatchedMemRefs;
1981 /// InputChain/InputFlag - The current chain/flag
1982 SDValue InputChain, InputFlag;
1984 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1985 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1990 SDNode *SelectionDAGISel::
1991 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1992 unsigned TableSize) {
1993 // FIXME: Should these even be selected? Handle these cases in the caller?
1994 switch (NodeToMatch->getOpcode()) {
1997 case ISD::EntryToken: // These nodes remain the same.
1998 case ISD::BasicBlock:
2000 //case ISD::VALUETYPE:
2001 //case ISD::CONDCODE:
2002 case ISD::HANDLENODE:
2003 case ISD::MDNODE_SDNODE:
2004 case ISD::TargetConstant:
2005 case ISD::TargetConstantFP:
2006 case ISD::TargetConstantPool:
2007 case ISD::TargetFrameIndex:
2008 case ISD::TargetExternalSymbol:
2009 case ISD::TargetBlockAddress:
2010 case ISD::TargetJumpTable:
2011 case ISD::TargetGlobalTLSAddress:
2012 case ISD::TargetGlobalAddress:
2013 case ISD::TokenFactor:
2014 case ISD::CopyFromReg:
2015 case ISD::CopyToReg:
2017 NodeToMatch->setNodeId(-1); // Mark selected.
2019 case ISD::AssertSext:
2020 case ISD::AssertZext:
2021 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2022 NodeToMatch->getOperand(0));
2024 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2025 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2028 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2030 // Set up the node stack with NodeToMatch as the only node on the stack.
2031 SmallVector<SDValue, 8> NodeStack;
2032 SDValue N = SDValue(NodeToMatch, 0);
2033 NodeStack.push_back(N);
2035 // MatchScopes - Scopes used when matching, if a match failure happens, this
2036 // indicates where to continue checking.
2037 SmallVector<MatchScope, 8> MatchScopes;
2039 // RecordedNodes - This is the set of nodes that have been recorded by the
2040 // state machine. The second value is the parent of the node, or null if the
2041 // root is recorded.
2042 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2044 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2046 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2048 // These are the current input chain and flag for use when generating nodes.
2049 // Various Emit operations change these. For example, emitting a copytoreg
2050 // uses and updates these.
2051 SDValue InputChain, InputFlag;
2053 // ChainNodesMatched - If a pattern matches nodes that have input/output
2054 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2055 // which ones they are. The result is captured into this list so that we can
2056 // update the chain results when the pattern is complete.
2057 SmallVector<SDNode*, 3> ChainNodesMatched;
2058 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2060 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2061 NodeToMatch->dump(CurDAG);
2064 // Determine where to start the interpreter. Normally we start at opcode #0,
2065 // but if the state machine starts with an OPC_SwitchOpcode, then we
2066 // accelerate the first lookup (which is guaranteed to be hot) with the
2067 // OpcodeOffset table.
2068 unsigned MatcherIndex = 0;
2070 if (!OpcodeOffset.empty()) {
2071 // Already computed the OpcodeOffset table, just index into it.
2072 if (N.getOpcode() < OpcodeOffset.size())
2073 MatcherIndex = OpcodeOffset[N.getOpcode()];
2074 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2076 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2077 // Otherwise, the table isn't computed, but the state machine does start
2078 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2079 // is the first time we're selecting an instruction.
2082 // Get the size of this case.
2083 unsigned CaseSize = MatcherTable[Idx++];
2085 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2086 if (CaseSize == 0) break;
2088 // Get the opcode, add the index to the table.
2089 uint16_t Opc = MatcherTable[Idx++];
2090 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2091 if (Opc >= OpcodeOffset.size())
2092 OpcodeOffset.resize((Opc+1)*2);
2093 OpcodeOffset[Opc] = Idx;
2097 // Okay, do the lookup for the first opcode.
2098 if (N.getOpcode() < OpcodeOffset.size())
2099 MatcherIndex = OpcodeOffset[N.getOpcode()];
2103 assert(MatcherIndex < TableSize && "Invalid index");
2105 unsigned CurrentOpcodeIndex = MatcherIndex;
2107 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2110 // Okay, the semantics of this operation are that we should push a scope
2111 // then evaluate the first child. However, pushing a scope only to have
2112 // the first check fail (which then pops it) is inefficient. If we can
2113 // determine immediately that the first check (or first several) will
2114 // immediately fail, don't even bother pushing a scope for them.
2118 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2119 if (NumToSkip & 128)
2120 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2121 // Found the end of the scope with no match.
2122 if (NumToSkip == 0) {
2127 FailIndex = MatcherIndex+NumToSkip;
2129 unsigned MatcherIndexOfPredicate = MatcherIndex;
2130 (void)MatcherIndexOfPredicate; // silence warning.
2132 // If we can't evaluate this predicate without pushing a scope (e.g. if
2133 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2134 // push the scope and evaluate the full predicate chain.
2136 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2137 Result, *this, RecordedNodes);
2141 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2142 << "index " << MatcherIndexOfPredicate
2143 << ", continuing at " << FailIndex << "\n");
2144 ++NumDAGIselRetries;
2146 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2147 // move to the next case.
2148 MatcherIndex = FailIndex;
2151 // If the whole scope failed to match, bail.
2152 if (FailIndex == 0) break;
2154 // Push a MatchScope which indicates where to go if the first child fails
2156 MatchScope NewEntry;
2157 NewEntry.FailIndex = FailIndex;
2158 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2159 NewEntry.NumRecordedNodes = RecordedNodes.size();
2160 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2161 NewEntry.InputChain = InputChain;
2162 NewEntry.InputFlag = InputFlag;
2163 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2164 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2165 MatchScopes.push_back(NewEntry);
2168 case OPC_RecordNode: {
2169 // Remember this node, it may end up being an operand in the pattern.
2171 if (NodeStack.size() > 1)
2172 Parent = NodeStack[NodeStack.size()-2].getNode();
2173 RecordedNodes.push_back(std::make_pair(N, Parent));
2177 case OPC_RecordChild0: case OPC_RecordChild1:
2178 case OPC_RecordChild2: case OPC_RecordChild3:
2179 case OPC_RecordChild4: case OPC_RecordChild5:
2180 case OPC_RecordChild6: case OPC_RecordChild7: {
2181 unsigned ChildNo = Opcode-OPC_RecordChild0;
2182 if (ChildNo >= N.getNumOperands())
2183 break; // Match fails if out of range child #.
2185 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2189 case OPC_RecordMemRef:
2190 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2193 case OPC_CaptureFlagInput:
2194 // If the current node has an input flag, capture it in InputFlag.
2195 if (N->getNumOperands() != 0 &&
2196 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2197 InputFlag = N->getOperand(N->getNumOperands()-1);
2200 case OPC_MoveChild: {
2201 unsigned ChildNo = MatcherTable[MatcherIndex++];
2202 if (ChildNo >= N.getNumOperands())
2203 break; // Match fails if out of range child #.
2204 N = N.getOperand(ChildNo);
2205 NodeStack.push_back(N);
2209 case OPC_MoveParent:
2210 // Pop the current node off the NodeStack.
2211 NodeStack.pop_back();
2212 assert(!NodeStack.empty() && "Node stack imbalance!");
2213 N = NodeStack.back();
2217 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2219 case OPC_CheckPatternPredicate:
2220 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2222 case OPC_CheckPredicate:
2223 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2227 case OPC_CheckComplexPat: {
2228 unsigned CPNum = MatcherTable[MatcherIndex++];
2229 unsigned RecNo = MatcherTable[MatcherIndex++];
2230 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2231 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2232 RecordedNodes[RecNo].first, CPNum,
2237 case OPC_CheckOpcode:
2238 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2242 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2245 case OPC_SwitchOpcode: {
2246 unsigned CurNodeOpcode = N.getOpcode();
2247 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2250 // Get the size of this case.
2251 CaseSize = MatcherTable[MatcherIndex++];
2253 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2254 if (CaseSize == 0) break;
2256 uint16_t Opc = MatcherTable[MatcherIndex++];
2257 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2259 // If the opcode matches, then we will execute this case.
2260 if (CurNodeOpcode == Opc)
2263 // Otherwise, skip over this case.
2264 MatcherIndex += CaseSize;
2267 // If no cases matched, bail out.
2268 if (CaseSize == 0) break;
2270 // Otherwise, execute the case we found.
2271 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2272 << " to " << MatcherIndex << "\n");
2276 case OPC_SwitchType: {
2277 MVT CurNodeVT = N.getValueType().getSimpleVT();
2278 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2281 // Get the size of this case.
2282 CaseSize = MatcherTable[MatcherIndex++];
2284 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2285 if (CaseSize == 0) break;
2287 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2288 if (CaseVT == MVT::iPTR)
2289 CaseVT = TLI.getPointerTy();
2291 // If the VT matches, then we will execute this case.
2292 if (CurNodeVT == CaseVT)
2295 // Otherwise, skip over this case.
2296 MatcherIndex += CaseSize;
2299 // If no cases matched, bail out.
2300 if (CaseSize == 0) break;
2302 // Otherwise, execute the case we found.
2303 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2304 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2307 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2308 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2309 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2310 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2311 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2312 Opcode-OPC_CheckChild0Type))
2315 case OPC_CheckCondCode:
2316 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2318 case OPC_CheckValueType:
2319 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2321 case OPC_CheckInteger:
2322 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2324 case OPC_CheckAndImm:
2325 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2327 case OPC_CheckOrImm:
2328 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2331 case OPC_CheckFoldableChainNode: {
2332 assert(NodeStack.size() != 1 && "No parent node");
2333 // Verify that all intermediate nodes between the root and this one have
2335 bool HasMultipleUses = false;
2336 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2337 if (!NodeStack[i].hasOneUse()) {
2338 HasMultipleUses = true;
2341 if (HasMultipleUses) break;
2343 // Check to see that the target thinks this is profitable to fold and that
2344 // we can fold it without inducing cycles in the graph.
2345 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2347 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2348 NodeToMatch, OptLevel,
2349 true/*We validate our own chains*/))
2354 case OPC_EmitInteger: {
2355 MVT::SimpleValueType VT =
2356 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2357 int64_t Val = MatcherTable[MatcherIndex++];
2359 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2360 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2361 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2364 case OPC_EmitRegister: {
2365 MVT::SimpleValueType VT =
2366 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2367 unsigned RegNo = MatcherTable[MatcherIndex++];
2368 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2369 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2373 case OPC_EmitConvertToTarget: {
2374 // Convert from IMM/FPIMM to target version.
2375 unsigned RecNo = MatcherTable[MatcherIndex++];
2376 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2377 SDValue Imm = RecordedNodes[RecNo].first;
2379 if (Imm->getOpcode() == ISD::Constant) {
2380 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2381 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2382 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2383 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2384 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2387 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2391 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2392 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2393 // These are space-optimized forms of OPC_EmitMergeInputChains.
2394 assert(InputChain.getNode() == 0 &&
2395 "EmitMergeInputChains should be the first chain producing node");
2396 assert(ChainNodesMatched.empty() &&
2397 "Should only have one EmitMergeInputChains per match");
2399 // Read all of the chained nodes.
2400 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2401 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2402 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2404 // FIXME: What if other value results of the node have uses not matched
2406 if (ChainNodesMatched.back() != NodeToMatch &&
2407 !RecordedNodes[RecNo].first.hasOneUse()) {
2408 ChainNodesMatched.clear();
2412 // Merge the input chains if they are not intra-pattern references.
2413 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2415 if (InputChain.getNode() == 0)
2416 break; // Failed to merge.
2420 case OPC_EmitMergeInputChains: {
2421 assert(InputChain.getNode() == 0 &&
2422 "EmitMergeInputChains should be the first chain producing node");
2423 // This node gets a list of nodes we matched in the input that have
2424 // chains. We want to token factor all of the input chains to these nodes
2425 // together. However, if any of the input chains is actually one of the
2426 // nodes matched in this pattern, then we have an intra-match reference.
2427 // Ignore these because the newly token factored chain should not refer to
2429 unsigned NumChains = MatcherTable[MatcherIndex++];
2430 assert(NumChains != 0 && "Can't TF zero chains");
2432 assert(ChainNodesMatched.empty() &&
2433 "Should only have one EmitMergeInputChains per match");
2435 // Read all of the chained nodes.
2436 for (unsigned i = 0; i != NumChains; ++i) {
2437 unsigned RecNo = MatcherTable[MatcherIndex++];
2438 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2439 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2441 // FIXME: What if other value results of the node have uses not matched
2443 if (ChainNodesMatched.back() != NodeToMatch &&
2444 !RecordedNodes[RecNo].first.hasOneUse()) {
2445 ChainNodesMatched.clear();
2450 // If the inner loop broke out, the match fails.
2451 if (ChainNodesMatched.empty())
2454 // Merge the input chains if they are not intra-pattern references.
2455 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2457 if (InputChain.getNode() == 0)
2458 break; // Failed to merge.
2463 case OPC_EmitCopyToReg: {
2464 unsigned RecNo = MatcherTable[MatcherIndex++];
2465 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2466 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2468 if (InputChain.getNode() == 0)
2469 InputChain = CurDAG->getEntryNode();
2471 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2472 DestPhysReg, RecordedNodes[RecNo].first,
2475 InputFlag = InputChain.getValue(1);
2479 case OPC_EmitNodeXForm: {
2480 unsigned XFormNo = MatcherTable[MatcherIndex++];
2481 unsigned RecNo = MatcherTable[MatcherIndex++];
2482 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2483 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2484 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2489 case OPC_MorphNodeTo: {
2490 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2491 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2492 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2493 // Get the result VT list.
2494 unsigned NumVTs = MatcherTable[MatcherIndex++];
2495 SmallVector<EVT, 4> VTs;
2496 for (unsigned i = 0; i != NumVTs; ++i) {
2497 MVT::SimpleValueType VT =
2498 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2499 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2503 if (EmitNodeInfo & OPFL_Chain)
2504 VTs.push_back(MVT::Other);
2505 if (EmitNodeInfo & OPFL_FlagOutput)
2506 VTs.push_back(MVT::Flag);
2508 // This is hot code, so optimize the two most common cases of 1 and 2
2511 if (VTs.size() == 1)
2512 VTList = CurDAG->getVTList(VTs[0]);
2513 else if (VTs.size() == 2)
2514 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2516 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2518 // Get the operand list.
2519 unsigned NumOps = MatcherTable[MatcherIndex++];
2520 SmallVector<SDValue, 8> Ops;
2521 for (unsigned i = 0; i != NumOps; ++i) {
2522 unsigned RecNo = MatcherTable[MatcherIndex++];
2524 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2526 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2527 Ops.push_back(RecordedNodes[RecNo].first);
2530 // If there are variadic operands to add, handle them now.
2531 if (EmitNodeInfo & OPFL_VariadicInfo) {
2532 // Determine the start index to copy from.
2533 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2534 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2535 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2536 "Invalid variadic node");
2537 // Copy all of the variadic operands, not including a potential flag
2539 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2541 SDValue V = NodeToMatch->getOperand(i);
2542 if (V.getValueType() == MVT::Flag) break;
2547 // If this has chain/flag inputs, add them.
2548 if (EmitNodeInfo & OPFL_Chain)
2549 Ops.push_back(InputChain);
2550 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2551 Ops.push_back(InputFlag);
2555 if (Opcode != OPC_MorphNodeTo) {
2556 // If this is a normal EmitNode command, just create the new node and
2557 // add the results to the RecordedNodes list.
2558 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2559 VTList, Ops.data(), Ops.size());
2561 // Add all the non-flag/non-chain results to the RecordedNodes list.
2562 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2563 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2564 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2569 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2573 // If the node had chain/flag results, update our notion of the current
2575 if (EmitNodeInfo & OPFL_FlagOutput) {
2576 InputFlag = SDValue(Res, VTs.size()-1);
2577 if (EmitNodeInfo & OPFL_Chain)
2578 InputChain = SDValue(Res, VTs.size()-2);
2579 } else if (EmitNodeInfo & OPFL_Chain)
2580 InputChain = SDValue(Res, VTs.size()-1);
2582 // If the OPFL_MemRefs flag is set on this node, slap all of the
2583 // accumulated memrefs onto it.
2585 // FIXME: This is vastly incorrect for patterns with multiple outputs
2586 // instructions that access memory and for ComplexPatterns that match
2588 if (EmitNodeInfo & OPFL_MemRefs) {
2589 MachineSDNode::mmo_iterator MemRefs =
2590 MF->allocateMemRefsArray(MatchedMemRefs.size());
2591 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2592 cast<MachineSDNode>(Res)
2593 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2597 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2598 << " node: "; Res->dump(CurDAG); errs() << "\n");
2600 // If this was a MorphNodeTo then we're completely done!
2601 if (Opcode == OPC_MorphNodeTo) {
2602 // Update chain and flag uses.
2603 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2604 InputFlag, FlagResultNodesMatched, true);
2611 case OPC_MarkFlagResults: {
2612 unsigned NumNodes = MatcherTable[MatcherIndex++];
2614 // Read and remember all the flag-result nodes.
2615 for (unsigned i = 0; i != NumNodes; ++i) {
2616 unsigned RecNo = MatcherTable[MatcherIndex++];
2618 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2620 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2621 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2626 case OPC_CompleteMatch: {
2627 // The match has been completed, and any new nodes (if any) have been
2628 // created. Patch up references to the matched dag to use the newly
2630 unsigned NumResults = MatcherTable[MatcherIndex++];
2632 for (unsigned i = 0; i != NumResults; ++i) {
2633 unsigned ResSlot = MatcherTable[MatcherIndex++];
2635 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2637 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2638 SDValue Res = RecordedNodes[ResSlot].first;
2640 assert(i < NodeToMatch->getNumValues() &&
2641 NodeToMatch->getValueType(i) != MVT::Other &&
2642 NodeToMatch->getValueType(i) != MVT::Flag &&
2643 "Invalid number of results to complete!");
2644 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2645 NodeToMatch->getValueType(i) == MVT::iPTR ||
2646 Res.getValueType() == MVT::iPTR ||
2647 NodeToMatch->getValueType(i).getSizeInBits() ==
2648 Res.getValueType().getSizeInBits()) &&
2649 "invalid replacement");
2650 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2653 // If the root node defines a flag, add it to the flag nodes to update
2655 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2656 FlagResultNodesMatched.push_back(NodeToMatch);
2658 // Update chain and flag uses.
2659 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2660 InputFlag, FlagResultNodesMatched, false);
2662 assert(NodeToMatch->use_empty() &&
2663 "Didn't replace all uses of the node?");
2665 // FIXME: We just return here, which interacts correctly with SelectRoot
2666 // above. We should fix this to not return an SDNode* anymore.
2671 // If the code reached this point, then the match failed. See if there is
2672 // another child to try in the current 'Scope', otherwise pop it until we
2673 // find a case to check.
2674 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2675 ++NumDAGIselRetries;
2677 if (MatchScopes.empty()) {
2678 CannotYetSelect(NodeToMatch);
2682 // Restore the interpreter state back to the point where the scope was
2684 MatchScope &LastScope = MatchScopes.back();
2685 RecordedNodes.resize(LastScope.NumRecordedNodes);
2687 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2688 N = NodeStack.back();
2690 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2691 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2692 MatcherIndex = LastScope.FailIndex;
2694 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2696 InputChain = LastScope.InputChain;
2697 InputFlag = LastScope.InputFlag;
2698 if (!LastScope.HasChainNodesMatched)
2699 ChainNodesMatched.clear();
2700 if (!LastScope.HasFlagResultNodesMatched)
2701 FlagResultNodesMatched.clear();
2703 // Check to see what the offset is at the new MatcherIndex. If it is zero
2704 // we have reached the end of this scope, otherwise we have another child
2705 // in the current scope to try.
2706 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2707 if (NumToSkip & 128)
2708 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2710 // If we have another child in this scope to match, update FailIndex and
2712 if (NumToSkip != 0) {
2713 LastScope.FailIndex = MatcherIndex+NumToSkip;
2717 // End of this scope, pop it and try the next child in the containing
2719 MatchScopes.pop_back();
2726 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2728 raw_string_ostream Msg(msg);
2729 Msg << "Cannot yet select: ";
2731 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2732 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2733 N->getOpcode() != ISD::INTRINSIC_VOID) {
2734 N->printrFull(Msg, CurDAG);
2736 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2738 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2739 if (iid < Intrinsic::num_intrinsics)
2740 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2741 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2742 Msg << "target intrinsic %" << TII->getName(iid);
2744 Msg << "unknown intrinsic #" << iid;
2746 report_fatal_error(Msg.str());
2749 char SelectionDAGISel::ID = 0;