1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SSARegMap.h"
37 #include "llvm/Target/MRegisterInfo.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetFrameInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
52 ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
55 ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
59 cl::desc("Pop up a window to show SUnit dags after they are processed"));
61 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
64 //===---------------------------------------------------------------------===//
66 /// RegisterScheduler class - Track the registration of instruction schedulers.
68 //===---------------------------------------------------------------------===//
69 MachinePassRegistry RegisterScheduler::Registry;
71 //===---------------------------------------------------------------------===//
73 /// ISHeuristic command line option for instruction schedulers.
75 //===---------------------------------------------------------------------===//
77 cl::opt<RegisterScheduler::FunctionPassCtor, false,
78 RegisterPassParser<RegisterScheduler> >
79 ISHeuristic("pre-RA-sched",
80 cl::init(&createDefaultScheduler),
81 cl::desc("Instruction schedulers available (before register allocation):"));
83 static RegisterScheduler
84 defaultListDAGScheduler("default", " Best scheduler for the target",
85 createDefaultScheduler);
88 namespace { struct AsmOperandInfo; }
91 /// RegsForValue - This struct represents the physical registers that a
92 /// particular value is assigned and the type information about the value.
93 /// This is needed because values can be promoted into larger registers and
94 /// expanded into multiple smaller registers than the value.
95 struct VISIBILITY_HIDDEN RegsForValue {
96 /// Regs - This list holds the register (for legal and promoted values)
97 /// or register set (for expanded values) that the value should be assigned
99 std::vector<unsigned> Regs;
101 /// RegVT - The value type of each register.
103 MVT::ValueType RegVT;
105 /// ValueVT - The value type of the LLVM value, which may be promoted from
106 /// RegVT or made from merging the two expanded parts.
107 MVT::ValueType ValueVT;
109 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
111 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
112 : RegVT(regvt), ValueVT(valuevt) {
115 RegsForValue(const std::vector<unsigned> ®s,
116 MVT::ValueType regvt, MVT::ValueType valuevt)
117 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
120 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
121 /// this value and returns the result as a ValueVT value. This uses
122 /// Chain/Flag as the input and updates them for the output Chain/Flag.
123 /// If the Flag pointer is NULL, no flag is used.
124 SDOperand getCopyFromRegs(SelectionDAG &DAG,
125 SDOperand &Chain, SDOperand *Flag) const;
127 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
128 /// specified value into the registers specified by this object. This uses
129 /// Chain/Flag as the input and updates them for the output Chain/Flag.
130 /// If the Flag pointer is NULL, no flag is used.
131 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
132 SDOperand &Chain, SDOperand *Flag) const;
134 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
135 /// operand list. This adds the code marker and includes the number of
136 /// values added into it.
137 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
138 std::vector<SDOperand> &Ops) const;
143 //===--------------------------------------------------------------------===//
144 /// createDefaultScheduler - This creates an instruction scheduler appropriate
146 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
148 MachineBasicBlock *BB) {
149 TargetLowering &TLI = IS->getTargetLowering();
151 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
152 return createTDListDAGScheduler(IS, DAG, BB);
154 assert(TLI.getSchedulingPreference() ==
155 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
156 return createBURRListDAGScheduler(IS, DAG, BB);
161 //===--------------------------------------------------------------------===//
162 /// FunctionLoweringInfo - This contains information that is global to a
163 /// function that is used when lowering a region of the function.
164 class FunctionLoweringInfo {
171 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
173 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
174 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
176 /// ValueMap - Since we emit code for the function a basic block at a time,
177 /// we must remember which virtual registers hold the values for
178 /// cross-basic-block values.
179 DenseMap<const Value*, unsigned> ValueMap;
181 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
182 /// the entry block. This allows the allocas to be efficiently referenced
183 /// anywhere in the function.
184 std::map<const AllocaInst*, int> StaticAllocaMap;
187 SmallSet<Instruction*, 8> CatchInfoLost;
188 SmallSet<Instruction*, 8> CatchInfoFound;
191 unsigned MakeReg(MVT::ValueType VT) {
192 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
195 /// isExportedInst - Return true if the specified value is an instruction
196 /// exported from its block.
197 bool isExportedInst(const Value *V) {
198 return ValueMap.count(V);
201 unsigned CreateRegForValue(const Value *V);
203 unsigned InitializeRegForValue(const Value *V) {
204 unsigned &R = ValueMap[V];
205 assert(R == 0 && "Already initialized this value register!");
206 return R = CreateRegForValue(V);
211 /// isSelector - Return true if this instruction is a call to the
212 /// eh.selector intrinsic.
213 static bool isSelector(Instruction *I) {
214 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
215 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
216 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
220 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
221 /// PHI nodes or outside of the basic block that defines it, or used by a
222 /// switch instruction, which may expand to multiple basic blocks.
223 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
224 if (isa<PHINode>(I)) return true;
225 BasicBlock *BB = I->getParent();
226 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
227 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
228 // FIXME: Remove switchinst special case.
229 isa<SwitchInst>(*UI))
234 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
235 /// entry block, return true. This includes arguments used by switches, since
236 /// the switch may expand into multiple basic blocks.
237 static bool isOnlyUsedInEntryBlock(Argument *A) {
238 BasicBlock *Entry = A->getParent()->begin();
239 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
240 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
241 return false; // Use not in entry block.
245 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
246 Function &fn, MachineFunction &mf)
247 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
249 // Create a vreg for each argument register that is not dead and is used
250 // outside of the entry block for the function.
251 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
253 if (!isOnlyUsedInEntryBlock(AI))
254 InitializeRegForValue(AI);
256 // Initialize the mapping of values to registers. This is only set up for
257 // instruction values that are used outside of the block that defines
259 Function::iterator BB = Fn.begin(), EB = Fn.end();
260 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
261 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
262 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
263 const Type *Ty = AI->getAllocatedType();
264 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
266 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
269 TySize *= CUI->getZExtValue(); // Get total allocated size.
270 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
271 StaticAllocaMap[AI] =
272 MF.getFrameInfo()->CreateStackObject(TySize, Align);
275 for (; BB != EB; ++BB)
276 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
277 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
278 if (!isa<AllocaInst>(I) ||
279 !StaticAllocaMap.count(cast<AllocaInst>(I)))
280 InitializeRegForValue(I);
282 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
283 // also creates the initial PHI MachineInstrs, though none of the input
284 // operands are populated.
285 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
286 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
288 MF.getBasicBlockList().push_back(MBB);
290 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
293 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
294 if (PN->use_empty()) continue;
296 MVT::ValueType VT = TLI.getValueType(PN->getType());
297 unsigned NumRegisters = TLI.getNumRegisters(VT);
298 unsigned PHIReg = ValueMap[PN];
299 assert(PHIReg && "PHI node does not have an assigned virtual register!");
300 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
301 for (unsigned i = 0; i != NumRegisters; ++i)
302 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
307 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
308 /// the correctly promoted or expanded types. Assign these registers
309 /// consecutive vreg numbers and return the first assigned number.
310 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
311 MVT::ValueType VT = TLI.getValueType(V->getType());
313 unsigned NumRegisters = TLI.getNumRegisters(VT);
314 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
316 unsigned R = MakeReg(RegisterVT);
317 for (unsigned i = 1; i != NumRegisters; ++i)
323 //===----------------------------------------------------------------------===//
324 /// SelectionDAGLowering - This is the common target-independent lowering
325 /// implementation that is parameterized by a TargetLowering object.
326 /// Also, targets can overload any lowering method.
329 class SelectionDAGLowering {
330 MachineBasicBlock *CurMBB;
332 DenseMap<const Value*, SDOperand> NodeMap;
334 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
335 /// them up and then emit token factor nodes when possible. This allows us to
336 /// get simple disambiguation between loads without worrying about alias
338 std::vector<SDOperand> PendingLoads;
340 /// Case - A struct to record the Value for a switch case, and the
341 /// case's target basic block.
345 MachineBasicBlock* BB;
347 Case() : Low(0), High(0), BB(0) { }
348 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
349 Low(low), High(high), BB(bb) { }
350 uint64_t size() const {
351 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
352 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
353 return (rHigh - rLow + 1ULL);
359 MachineBasicBlock* BB;
362 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
363 Mask(mask), BB(bb), Bits(bits) { }
366 typedef std::vector<Case> CaseVector;
367 typedef std::vector<CaseBits> CaseBitsVector;
368 typedef CaseVector::iterator CaseItr;
369 typedef std::pair<CaseItr, CaseItr> CaseRange;
371 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
372 /// of conditional branches.
374 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
375 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
377 /// CaseBB - The MBB in which to emit the compare and branch
378 MachineBasicBlock *CaseBB;
379 /// LT, GE - If nonzero, we know the current case value must be less-than or
380 /// greater-than-or-equal-to these Constants.
383 /// Range - A pair of iterators representing the range of case values to be
384 /// processed at this point in the binary search tree.
388 typedef std::vector<CaseRec> CaseRecVector;
390 /// The comparison function for sorting the switch case values in the vector.
391 /// WARNING: Case ranges should be disjoint!
393 bool operator () (const Case& C1, const Case& C2) {
394 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
395 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
396 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
397 return CI1->getValue().slt(CI2->getValue());
402 bool operator () (const CaseBits& C1, const CaseBits& C2) {
403 return C1.Bits > C2.Bits;
407 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
410 // TLI - This is information that describes the available target features we
411 // need for lowering. This indicates when operations are unavailable,
412 // implemented with a libcall, etc.
415 const TargetData *TD;
418 /// SwitchCases - Vector of CaseBlock structures used to communicate
419 /// SwitchInst code generation information.
420 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
421 /// JTCases - Vector of JumpTable structures used to communicate
422 /// SwitchInst code generation information.
423 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
424 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
426 /// FuncInfo - Information about the function as a whole.
428 FunctionLoweringInfo &FuncInfo;
430 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
432 FunctionLoweringInfo &funcinfo)
433 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
437 /// getRoot - Return the current virtual root of the Selection DAG.
439 SDOperand getRoot() {
440 if (PendingLoads.empty())
441 return DAG.getRoot();
443 if (PendingLoads.size() == 1) {
444 SDOperand Root = PendingLoads[0];
446 PendingLoads.clear();
450 // Otherwise, we have to make a token factor node.
451 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
452 &PendingLoads[0], PendingLoads.size());
453 PendingLoads.clear();
458 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
460 void visit(Instruction &I) { visit(I.getOpcode(), I); }
462 void visit(unsigned Opcode, User &I) {
463 // Note: this doesn't use InstVisitor, because it has to work with
464 // ConstantExpr's in addition to instructions.
466 default: assert(0 && "Unknown instruction type encountered!");
468 // Build the switch statement using the Instruction.def file.
469 #define HANDLE_INST(NUM, OPCODE, CLASS) \
470 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
471 #include "llvm/Instruction.def"
475 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
477 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
478 const Value *SV, SDOperand Root,
479 bool isVolatile, unsigned Alignment);
481 SDOperand getIntPtrConstant(uint64_t Val) {
482 return DAG.getConstant(Val, TLI.getPointerTy());
485 SDOperand getValue(const Value *V);
487 void setValue(const Value *V, SDOperand NewN) {
488 SDOperand &N = NodeMap[V];
489 assert(N.Val == 0 && "Already set a value for this node!");
493 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
494 std::set<unsigned> &OutputRegs,
495 std::set<unsigned> &InputRegs);
497 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
498 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
500 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
501 void ExportFromCurrentBlock(Value *V);
502 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
503 MachineBasicBlock *LandingPad = NULL);
505 // Terminator instructions.
506 void visitRet(ReturnInst &I);
507 void visitBr(BranchInst &I);
508 void visitSwitch(SwitchInst &I);
509 void visitUnreachable(UnreachableInst &I) { /* noop */ }
511 // Helpers for visitSwitch
512 bool handleSmallSwitchRange(CaseRec& CR,
513 CaseRecVector& WorkList,
515 MachineBasicBlock* Default);
516 bool handleJTSwitchCase(CaseRec& CR,
517 CaseRecVector& WorkList,
519 MachineBasicBlock* Default);
520 bool handleBTSplitSwitchCase(CaseRec& CR,
521 CaseRecVector& WorkList,
523 MachineBasicBlock* Default);
524 bool handleBitTestsSwitchCase(CaseRec& CR,
525 CaseRecVector& WorkList,
527 MachineBasicBlock* Default);
528 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
529 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
530 void visitBitTestCase(MachineBasicBlock* NextMBB,
532 SelectionDAGISel::BitTestCase &B);
533 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
534 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
535 SelectionDAGISel::JumpTableHeader &JTH);
537 // These all get lowered before this pass.
538 void visitInvoke(InvokeInst &I);
539 void visitUnwind(UnwindInst &I);
541 void visitBinary(User &I, unsigned OpCode);
542 void visitShift(User &I, unsigned Opcode);
543 void visitAdd(User &I) {
544 if (I.getType()->isFPOrFPVector())
545 visitBinary(I, ISD::FADD);
547 visitBinary(I, ISD::ADD);
549 void visitSub(User &I);
550 void visitMul(User &I) {
551 if (I.getType()->isFPOrFPVector())
552 visitBinary(I, ISD::FMUL);
554 visitBinary(I, ISD::MUL);
556 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
557 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
558 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
559 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
560 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
561 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
562 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
563 void visitOr (User &I) { visitBinary(I, ISD::OR); }
564 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
565 void visitShl (User &I) { visitShift(I, ISD::SHL); }
566 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
567 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
568 void visitICmp(User &I);
569 void visitFCmp(User &I);
570 // Visit the conversion instructions
571 void visitTrunc(User &I);
572 void visitZExt(User &I);
573 void visitSExt(User &I);
574 void visitFPTrunc(User &I);
575 void visitFPExt(User &I);
576 void visitFPToUI(User &I);
577 void visitFPToSI(User &I);
578 void visitUIToFP(User &I);
579 void visitSIToFP(User &I);
580 void visitPtrToInt(User &I);
581 void visitIntToPtr(User &I);
582 void visitBitCast(User &I);
584 void visitExtractElement(User &I);
585 void visitInsertElement(User &I);
586 void visitShuffleVector(User &I);
588 void visitGetElementPtr(User &I);
589 void visitSelect(User &I);
591 void visitMalloc(MallocInst &I);
592 void visitFree(FreeInst &I);
593 void visitAlloca(AllocaInst &I);
594 void visitLoad(LoadInst &I);
595 void visitStore(StoreInst &I);
596 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
597 void visitCall(CallInst &I);
598 void visitInlineAsm(CallSite CS);
599 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
600 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
602 void visitVAStart(CallInst &I);
603 void visitVAArg(VAArgInst &I);
604 void visitVAEnd(CallInst &I);
605 void visitVACopy(CallInst &I);
607 void visitMemIntrinsic(CallInst &I, unsigned Op);
609 void visitUserOp1(Instruction &I) {
610 assert(0 && "UserOp1 should not exist at instruction selection time!");
613 void visitUserOp2(Instruction &I) {
614 assert(0 && "UserOp2 should not exist at instruction selection time!");
618 } // end namespace llvm
621 /// getCopyFromParts - Create a value that contains the
622 /// specified legal parts combined into the value they represent.
623 static SDOperand getCopyFromParts(SelectionDAG &DAG,
624 const SDOperand *Parts,
626 MVT::ValueType PartVT,
627 MVT::ValueType ValueVT,
628 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
629 if (!MVT::isVector(ValueVT) || NumParts == 1) {
630 SDOperand Val = Parts[0];
632 // If the value was expanded, copy from the top part.
634 assert(NumParts == 2 &&
635 "Cannot expand to more than 2 elts yet!");
636 SDOperand Hi = Parts[1];
637 if (!DAG.getTargetLoweringInfo().isLittleEndian())
639 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
642 // Otherwise, if the value was promoted or extended, truncate it to the
644 if (PartVT == ValueVT)
647 if (MVT::isVector(PartVT)) {
648 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
649 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
652 if (MVT::isVector(ValueVT)) {
653 assert(NumParts == 1 &&
654 MVT::getVectorElementType(ValueVT) == PartVT &&
655 MVT::getVectorNumElements(ValueVT) == 1 &&
656 "Only trivial scalar-to-vector conversions should get here!");
657 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
660 if (MVT::isInteger(PartVT) &&
661 MVT::isInteger(ValueVT)) {
662 if (ValueVT < PartVT) {
663 // For a truncate, see if we have any information to
664 // indicate whether the truncated bits will always be
665 // zero or sign-extension.
666 if (AssertOp != ISD::DELETED_NODE)
667 Val = DAG.getNode(AssertOp, PartVT, Val,
668 DAG.getValueType(ValueVT));
669 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
671 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
675 if (MVT::isFloatingPoint(PartVT) &&
676 MVT::isFloatingPoint(ValueVT))
677 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
679 if (MVT::getSizeInBits(PartVT) ==
680 MVT::getSizeInBits(ValueVT))
681 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
683 assert(0 && "Unknown mismatch!");
686 // Handle a multi-element vector.
687 MVT::ValueType IntermediateVT, RegisterVT;
688 unsigned NumIntermediates;
690 DAG.getTargetLoweringInfo()
691 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
694 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
695 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
696 assert(RegisterVT == Parts[0].getValueType() &&
697 "Part type doesn't match part!");
699 // Assemble the parts into intermediate operands.
700 SmallVector<SDOperand, 8> Ops(NumIntermediates);
701 if (NumIntermediates == NumParts) {
702 // If the register was not expanded, truncate or copy the value,
704 for (unsigned i = 0; i != NumParts; ++i)
705 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
706 PartVT, IntermediateVT);
707 } else if (NumParts > 0) {
708 // If the intermediate type was expanded, build the intermediate operands
710 assert(NumParts % NumIntermediates == 0 &&
711 "Must expand into a divisible number of parts!");
712 unsigned Factor = NumParts / NumIntermediates;
713 for (unsigned i = 0; i != NumIntermediates; ++i)
714 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
715 PartVT, IntermediateVT);
718 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
720 return DAG.getNode(MVT::isVector(IntermediateVT) ?
721 ISD::CONCAT_VECTORS :
723 ValueVT, &Ops[0], NumIntermediates);
726 /// getCopyToParts - Create a series of nodes that contain the
727 /// specified value split into legal parts.
728 static void getCopyToParts(SelectionDAG &DAG,
732 MVT::ValueType PartVT) {
733 TargetLowering &TLI = DAG.getTargetLoweringInfo();
734 MVT::ValueType PtrVT = TLI.getPointerTy();
735 MVT::ValueType ValueVT = Val.getValueType();
737 if (!MVT::isVector(ValueVT) || NumParts == 1) {
738 // If the value was expanded, copy from the parts.
740 for (unsigned i = 0; i != NumParts; ++i)
741 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
742 DAG.getConstant(i, PtrVT));
743 if (!DAG.getTargetLoweringInfo().isLittleEndian())
744 std::reverse(Parts, Parts + NumParts);
748 // If there is a single part and the types differ, this must be
750 if (PartVT != ValueVT) {
751 if (MVT::isVector(PartVT)) {
752 assert(MVT::isVector(ValueVT) &&
753 "Not a vector-vector cast?");
754 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
755 } else if (MVT::isVector(ValueVT)) {
756 assert(NumParts == 1 &&
757 MVT::getVectorElementType(ValueVT) == PartVT &&
758 MVT::getVectorNumElements(ValueVT) == 1 &&
759 "Only trivial vector-to-scalar conversions should get here!");
760 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
761 DAG.getConstant(0, PtrVT));
762 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
763 if (PartVT < ValueVT)
764 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
766 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
767 } else if (MVT::isFloatingPoint(PartVT) &&
768 MVT::isFloatingPoint(ValueVT)) {
769 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
770 } else if (MVT::getSizeInBits(PartVT) ==
771 MVT::getSizeInBits(ValueVT)) {
772 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
774 assert(0 && "Unknown mismatch!");
781 // Handle a multi-element vector.
782 MVT::ValueType IntermediateVT, RegisterVT;
783 unsigned NumIntermediates;
785 DAG.getTargetLoweringInfo()
786 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
788 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
790 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
791 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
793 // Split the vector into intermediate operands.
794 SmallVector<SDOperand, 8> Ops(NumIntermediates);
795 for (unsigned i = 0; i != NumIntermediates; ++i)
796 if (MVT::isVector(IntermediateVT))
797 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
799 DAG.getConstant(i * (NumElements / NumIntermediates),
802 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
804 DAG.getConstant(i, PtrVT));
806 // Split the intermediate operands into legal parts.
807 if (NumParts == NumIntermediates) {
808 // If the register was not expanded, promote or copy the value,
810 for (unsigned i = 0; i != NumParts; ++i)
811 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
812 } else if (NumParts > 0) {
813 // If the intermediate type was expanded, split each the value into
815 assert(NumParts % NumIntermediates == 0 &&
816 "Must expand into a divisible number of parts!");
817 unsigned Factor = NumParts / NumIntermediates;
818 for (unsigned i = 0; i != NumIntermediates; ++i)
819 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
824 SDOperand SelectionDAGLowering::getValue(const Value *V) {
825 SDOperand &N = NodeMap[V];
828 const Type *VTy = V->getType();
829 MVT::ValueType VT = TLI.getValueType(VTy);
830 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
831 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
832 visit(CE->getOpcode(), *CE);
833 SDOperand N1 = NodeMap[V];
834 assert(N1.Val && "visit didn't populate the ValueMap!");
836 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
837 return N = DAG.getGlobalAddress(GV, VT);
838 } else if (isa<ConstantPointerNull>(C)) {
839 return N = DAG.getConstant(0, TLI.getPointerTy());
840 } else if (isa<UndefValue>(C)) {
841 if (!isa<VectorType>(VTy))
842 return N = DAG.getNode(ISD::UNDEF, VT);
844 // Create a BUILD_VECTOR of undef nodes.
845 const VectorType *PTy = cast<VectorType>(VTy);
846 unsigned NumElements = PTy->getNumElements();
847 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
849 SmallVector<SDOperand, 8> Ops;
850 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
852 // Create a VConstant node with generic Vector type.
853 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
854 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
855 &Ops[0], Ops.size());
856 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
857 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
858 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
859 unsigned NumElements = PTy->getNumElements();
860 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
862 // Now that we know the number and type of the elements, push a
863 // Constant or ConstantFP node onto the ops list for each element of
864 // the vector constant.
865 SmallVector<SDOperand, 8> Ops;
866 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
867 for (unsigned i = 0; i != NumElements; ++i)
868 Ops.push_back(getValue(CP->getOperand(i)));
870 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
872 if (MVT::isFloatingPoint(PVT))
873 Op = DAG.getConstantFP(0, PVT);
875 Op = DAG.getConstant(0, PVT);
876 Ops.assign(NumElements, Op);
879 // Create a BUILD_VECTOR node.
880 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
881 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
884 // Canonicalize all constant ints to be unsigned.
885 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
889 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
890 std::map<const AllocaInst*, int>::iterator SI =
891 FuncInfo.StaticAllocaMap.find(AI);
892 if (SI != FuncInfo.StaticAllocaMap.end())
893 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
896 unsigned InReg = FuncInfo.ValueMap[V];
897 assert(InReg && "Value not in map!");
899 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
900 unsigned NumRegs = TLI.getNumRegisters(VT);
902 std::vector<unsigned> Regs(NumRegs);
903 for (unsigned i = 0; i != NumRegs; ++i)
906 RegsForValue RFV(Regs, RegisterVT, VT);
907 SDOperand Chain = DAG.getEntryNode();
909 return RFV.getCopyFromRegs(DAG, Chain, NULL);
913 void SelectionDAGLowering::visitRet(ReturnInst &I) {
914 if (I.getNumOperands() == 0) {
915 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
918 SmallVector<SDOperand, 8> NewValues;
919 NewValues.push_back(getRoot());
920 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
921 SDOperand RetOp = getValue(I.getOperand(i));
923 // If this is an integer return value, we need to promote it ourselves to
924 // the full width of a register, since getCopyToParts and Legalize will use
925 // ANY_EXTEND rather than sign/zero.
926 // FIXME: C calling convention requires the return type to be promoted to
927 // at least 32-bit. But this is not necessary for non-C calling conventions.
928 if (MVT::isInteger(RetOp.getValueType()) &&
929 RetOp.getValueType() < MVT::i64) {
930 MVT::ValueType TmpVT;
931 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
932 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
935 const Function *F = I.getParent()->getParent();
936 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
937 if (F->paramHasAttr(0, ParamAttr::SExt))
938 ExtendKind = ISD::SIGN_EXTEND;
939 if (F->paramHasAttr(0, ParamAttr::ZExt))
940 ExtendKind = ISD::ZERO_EXTEND;
941 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
942 NewValues.push_back(RetOp);
943 NewValues.push_back(DAG.getConstant(false, MVT::i32));
945 MVT::ValueType VT = RetOp.getValueType();
946 unsigned NumParts = TLI.getNumRegisters(VT);
947 MVT::ValueType PartVT = TLI.getRegisterType(VT);
948 SmallVector<SDOperand, 4> Parts(NumParts);
949 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
950 for (unsigned i = 0; i < NumParts; ++i) {
951 NewValues.push_back(Parts[i]);
952 NewValues.push_back(DAG.getConstant(false, MVT::i32));
956 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
957 &NewValues[0], NewValues.size()));
960 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
961 /// the current basic block, add it to ValueMap now so that we'll get a
963 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
964 // No need to export constants.
965 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
968 if (FuncInfo.isExportedInst(V)) return;
970 unsigned Reg = FuncInfo.InitializeRegForValue(V);
971 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
974 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
975 const BasicBlock *FromBB) {
976 // The operands of the setcc have to be in this block. We don't know
977 // how to export them from some other block.
978 if (Instruction *VI = dyn_cast<Instruction>(V)) {
979 // Can export from current BB.
980 if (VI->getParent() == FromBB)
983 // Is already exported, noop.
984 return FuncInfo.isExportedInst(V);
987 // If this is an argument, we can export it if the BB is the entry block or
988 // if it is already exported.
989 if (isa<Argument>(V)) {
990 if (FromBB == &FromBB->getParent()->getEntryBlock())
993 // Otherwise, can only export this if it is already exported.
994 return FuncInfo.isExportedInst(V);
997 // Otherwise, constants can always be exported.
1001 static bool InBlock(const Value *V, const BasicBlock *BB) {
1002 if (const Instruction *I = dyn_cast<Instruction>(V))
1003 return I->getParent() == BB;
1007 /// FindMergedConditions - If Cond is an expression like
1008 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1009 MachineBasicBlock *TBB,
1010 MachineBasicBlock *FBB,
1011 MachineBasicBlock *CurBB,
1013 // If this node is not part of the or/and tree, emit it as a branch.
1014 Instruction *BOp = dyn_cast<Instruction>(Cond);
1016 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1017 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1018 BOp->getParent() != CurBB->getBasicBlock() ||
1019 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1020 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1021 const BasicBlock *BB = CurBB->getBasicBlock();
1023 // If the leaf of the tree is a comparison, merge the condition into
1025 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1026 // The operands of the cmp have to be in this block. We don't know
1027 // how to export them from some other block. If this is the first block
1028 // of the sequence, no exporting is needed.
1030 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1031 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1032 BOp = cast<Instruction>(Cond);
1033 ISD::CondCode Condition;
1034 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1035 switch (IC->getPredicate()) {
1036 default: assert(0 && "Unknown icmp predicate opcode!");
1037 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1038 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1039 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1040 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1041 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1042 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1043 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1044 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1045 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1046 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1048 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1049 ISD::CondCode FPC, FOC;
1050 switch (FC->getPredicate()) {
1051 default: assert(0 && "Unknown fcmp predicate opcode!");
1052 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1053 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1054 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1055 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1056 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1057 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1058 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1059 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1060 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1061 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1062 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1063 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1064 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1065 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1066 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1067 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1069 if (FiniteOnlyFPMath())
1074 Condition = ISD::SETEQ; // silence warning.
1075 assert(0 && "Unknown compare instruction");
1078 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1079 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1080 SwitchCases.push_back(CB);
1084 // Create a CaseBlock record representing this branch.
1085 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1086 NULL, TBB, FBB, CurBB);
1087 SwitchCases.push_back(CB);
1092 // Create TmpBB after CurBB.
1093 MachineFunction::iterator BBI = CurBB;
1094 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1095 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1097 if (Opc == Instruction::Or) {
1098 // Codegen X | Y as:
1106 // Emit the LHS condition.
1107 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1109 // Emit the RHS condition into TmpBB.
1110 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1112 assert(Opc == Instruction::And && "Unknown merge op!");
1113 // Codegen X & Y as:
1120 // This requires creation of TmpBB after CurBB.
1122 // Emit the LHS condition.
1123 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1125 // Emit the RHS condition into TmpBB.
1126 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1130 /// If the set of cases should be emitted as a series of branches, return true.
1131 /// If we should emit this as a bunch of and/or'd together conditions, return
1134 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1135 if (Cases.size() != 2) return true;
1137 // If this is two comparisons of the same values or'd or and'd together, they
1138 // will get folded into a single comparison, so don't emit two blocks.
1139 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1140 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1141 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1142 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1149 void SelectionDAGLowering::visitBr(BranchInst &I) {
1150 // Update machine-CFG edges.
1151 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1153 // Figure out which block is immediately after the current one.
1154 MachineBasicBlock *NextBlock = 0;
1155 MachineFunction::iterator BBI = CurMBB;
1156 if (++BBI != CurMBB->getParent()->end())
1159 if (I.isUnconditional()) {
1160 // If this is not a fall-through branch, emit the branch.
1161 if (Succ0MBB != NextBlock)
1162 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1163 DAG.getBasicBlock(Succ0MBB)));
1165 // Update machine-CFG edges.
1166 CurMBB->addSuccessor(Succ0MBB);
1170 // If this condition is one of the special cases we handle, do special stuff
1172 Value *CondVal = I.getCondition();
1173 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1175 // If this is a series of conditions that are or'd or and'd together, emit
1176 // this as a sequence of branches instead of setcc's with and/or operations.
1177 // For example, instead of something like:
1190 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1191 if (BOp->hasOneUse() &&
1192 (BOp->getOpcode() == Instruction::And ||
1193 BOp->getOpcode() == Instruction::Or)) {
1194 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1195 // If the compares in later blocks need to use values not currently
1196 // exported from this block, export them now. This block should always
1197 // be the first entry.
1198 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1200 // Allow some cases to be rejected.
1201 if (ShouldEmitAsBranches(SwitchCases)) {
1202 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1203 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1204 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1207 // Emit the branch for this block.
1208 visitSwitchCase(SwitchCases[0]);
1209 SwitchCases.erase(SwitchCases.begin());
1213 // Okay, we decided not to do this, remove any inserted MBB's and clear
1215 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1216 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1218 SwitchCases.clear();
1222 // Create a CaseBlock record representing this branch.
1223 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1224 NULL, Succ0MBB, Succ1MBB, CurMBB);
1225 // Use visitSwitchCase to actually insert the fast branch sequence for this
1227 visitSwitchCase(CB);
1230 /// visitSwitchCase - Emits the necessary code to represent a single node in
1231 /// the binary search tree resulting from lowering a switch instruction.
1232 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1234 SDOperand CondLHS = getValue(CB.CmpLHS);
1236 // Build the setcc now.
1237 if (CB.CmpMHS == NULL) {
1238 // Fold "(X == true)" to X and "(X == false)" to !X to
1239 // handle common cases produced by branch lowering.
1240 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1242 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1243 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1244 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1246 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1248 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1250 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1251 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1253 SDOperand CmpOp = getValue(CB.CmpMHS);
1254 MVT::ValueType VT = CmpOp.getValueType();
1256 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1257 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1259 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1260 Cond = DAG.getSetCC(MVT::i1, SUB,
1261 DAG.getConstant(High-Low, VT), ISD::SETULE);
1266 // Set NextBlock to be the MBB immediately after the current one, if any.
1267 // This is used to avoid emitting unnecessary branches to the next block.
1268 MachineBasicBlock *NextBlock = 0;
1269 MachineFunction::iterator BBI = CurMBB;
1270 if (++BBI != CurMBB->getParent()->end())
1273 // If the lhs block is the next block, invert the condition so that we can
1274 // fall through to the lhs instead of the rhs block.
1275 if (CB.TrueBB == NextBlock) {
1276 std::swap(CB.TrueBB, CB.FalseBB);
1277 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1278 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1280 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1281 DAG.getBasicBlock(CB.TrueBB));
1282 if (CB.FalseBB == NextBlock)
1283 DAG.setRoot(BrCond);
1285 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1286 DAG.getBasicBlock(CB.FalseBB)));
1287 // Update successor info
1288 CurMBB->addSuccessor(CB.TrueBB);
1289 CurMBB->addSuccessor(CB.FalseBB);
1292 /// visitJumpTable - Emit JumpTable node in the current MBB
1293 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1294 // Emit the code for the jump table
1295 assert(JT.Reg != -1U && "Should lower JT Header first!");
1296 MVT::ValueType PTy = TLI.getPointerTy();
1297 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1298 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1299 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1304 /// visitJumpTableHeader - This function emits necessary code to produce index
1305 /// in the JumpTable from switch case.
1306 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1307 SelectionDAGISel::JumpTableHeader &JTH) {
1308 // Subtract the lowest switch case value from the value being switched on
1309 // and conditional branch to default mbb if the result is greater than the
1310 // difference between smallest and largest cases.
1311 SDOperand SwitchOp = getValue(JTH.SValue);
1312 MVT::ValueType VT = SwitchOp.getValueType();
1313 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1314 DAG.getConstant(JTH.First, VT));
1316 // The SDNode we just created, which holds the value being switched on
1317 // minus the the smallest case value, needs to be copied to a virtual
1318 // register so it can be used as an index into the jump table in a
1319 // subsequent basic block. This value may be smaller or larger than the
1320 // target's pointer type, and therefore require extension or truncating.
1321 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1322 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1324 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1326 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1327 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1328 JT.Reg = JumpTableReg;
1330 // Emit the range check for the jump table, and branch to the default
1331 // block for the switch statement if the value being switched on exceeds
1332 // the largest case in the switch.
1333 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1334 DAG.getConstant(JTH.Last-JTH.First,VT),
1337 // Set NextBlock to be the MBB immediately after the current one, if any.
1338 // This is used to avoid emitting unnecessary branches to the next block.
1339 MachineBasicBlock *NextBlock = 0;
1340 MachineFunction::iterator BBI = CurMBB;
1341 if (++BBI != CurMBB->getParent()->end())
1344 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1345 DAG.getBasicBlock(JT.Default));
1347 if (JT.MBB == NextBlock)
1348 DAG.setRoot(BrCond);
1350 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1351 DAG.getBasicBlock(JT.MBB)));
1356 /// visitBitTestHeader - This function emits necessary code to produce value
1357 /// suitable for "bit tests"
1358 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1359 // Subtract the minimum value
1360 SDOperand SwitchOp = getValue(B.SValue);
1361 MVT::ValueType VT = SwitchOp.getValueType();
1362 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1363 DAG.getConstant(B.First, VT));
1366 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1367 DAG.getConstant(B.Range, VT),
1371 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1372 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1374 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1376 // Make desired shift
1377 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1378 DAG.getConstant(1, TLI.getPointerTy()),
1381 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1382 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1385 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1386 DAG.getBasicBlock(B.Default));
1388 // Set NextBlock to be the MBB immediately after the current one, if any.
1389 // This is used to avoid emitting unnecessary branches to the next block.
1390 MachineBasicBlock *NextBlock = 0;
1391 MachineFunction::iterator BBI = CurMBB;
1392 if (++BBI != CurMBB->getParent()->end())
1395 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1396 if (MBB == NextBlock)
1397 DAG.setRoot(BrRange);
1399 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1400 DAG.getBasicBlock(MBB)));
1402 CurMBB->addSuccessor(B.Default);
1403 CurMBB->addSuccessor(MBB);
1408 /// visitBitTestCase - this function produces one "bit test"
1409 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1411 SelectionDAGISel::BitTestCase &B) {
1412 // Emit bit tests and jumps
1413 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1415 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1417 DAG.getConstant(B.Mask,
1418 TLI.getPointerTy()));
1419 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1420 DAG.getConstant(0, TLI.getPointerTy()),
1422 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1423 AndCmp, DAG.getBasicBlock(B.TargetBB));
1425 // Set NextBlock to be the MBB immediately after the current one, if any.
1426 // This is used to avoid emitting unnecessary branches to the next block.
1427 MachineBasicBlock *NextBlock = 0;
1428 MachineFunction::iterator BBI = CurMBB;
1429 if (++BBI != CurMBB->getParent()->end())
1432 if (NextMBB == NextBlock)
1435 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1436 DAG.getBasicBlock(NextMBB)));
1438 CurMBB->addSuccessor(B.TargetBB);
1439 CurMBB->addSuccessor(NextMBB);
1444 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1445 // Retrieve successors.
1446 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1447 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1449 if (isa<InlineAsm>(I.getCalledValue()))
1452 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1454 // If the value of the invoke is used outside of its defining block, make it
1455 // available as a virtual register.
1456 if (!I.use_empty()) {
1457 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1458 if (VMI != FuncInfo.ValueMap.end())
1459 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1462 // Drop into normal successor.
1463 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1464 DAG.getBasicBlock(Return)));
1466 // Update successor info
1467 CurMBB->addSuccessor(Return);
1468 CurMBB->addSuccessor(LandingPad);
1471 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1474 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1475 /// small case ranges).
1476 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1477 CaseRecVector& WorkList,
1479 MachineBasicBlock* Default) {
1480 Case& BackCase = *(CR.Range.second-1);
1482 // Size is the number of Cases represented by this range.
1483 unsigned Size = CR.Range.second - CR.Range.first;
1487 // Get the MachineFunction which holds the current MBB. This is used when
1488 // inserting any additional MBBs necessary to represent the switch.
1489 MachineFunction *CurMF = CurMBB->getParent();
1491 // Figure out which block is immediately after the current one.
1492 MachineBasicBlock *NextBlock = 0;
1493 MachineFunction::iterator BBI = CR.CaseBB;
1495 if (++BBI != CurMBB->getParent()->end())
1498 // TODO: If any two of the cases has the same destination, and if one value
1499 // is the same as the other, but has one bit unset that the other has set,
1500 // use bit manipulation to do two compares at once. For example:
1501 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1503 // Rearrange the case blocks so that the last one falls through if possible.
1504 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1505 // The last case block won't fall through into 'NextBlock' if we emit the
1506 // branches in this order. See if rearranging a case value would help.
1507 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1508 if (I->BB == NextBlock) {
1509 std::swap(*I, BackCase);
1515 // Create a CaseBlock record representing a conditional branch to
1516 // the Case's target mbb if the value being switched on SV is equal
1518 MachineBasicBlock *CurBlock = CR.CaseBB;
1519 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1520 MachineBasicBlock *FallThrough;
1522 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1523 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1525 // If the last case doesn't match, go to the default block.
1526 FallThrough = Default;
1529 Value *RHS, *LHS, *MHS;
1531 if (I->High == I->Low) {
1532 // This is just small small case range :) containing exactly 1 case
1534 LHS = SV; RHS = I->High; MHS = NULL;
1537 LHS = I->Low; MHS = SV; RHS = I->High;
1539 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1540 I->BB, FallThrough, CurBlock);
1542 // If emitting the first comparison, just call visitSwitchCase to emit the
1543 // code into the current block. Otherwise, push the CaseBlock onto the
1544 // vector to be later processed by SDISel, and insert the node's MBB
1545 // before the next MBB.
1546 if (CurBlock == CurMBB)
1547 visitSwitchCase(CB);
1549 SwitchCases.push_back(CB);
1551 CurBlock = FallThrough;
1557 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1558 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1559 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1562 /// handleJTSwitchCase - Emit jumptable for current switch case range
1563 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1564 CaseRecVector& WorkList,
1566 MachineBasicBlock* Default) {
1567 Case& FrontCase = *CR.Range.first;
1568 Case& BackCase = *(CR.Range.second-1);
1570 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1571 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1574 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1578 if (!areJTsAllowed(TLI) || TSize <= 3)
1581 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1585 DOUT << "Lowering jump table\n"
1586 << "First entry: " << First << ". Last entry: " << Last << "\n"
1587 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1589 // Get the MachineFunction which holds the current MBB. This is used when
1590 // inserting any additional MBBs necessary to represent the switch.
1591 MachineFunction *CurMF = CurMBB->getParent();
1593 // Figure out which block is immediately after the current one.
1594 MachineBasicBlock *NextBlock = 0;
1595 MachineFunction::iterator BBI = CR.CaseBB;
1597 if (++BBI != CurMBB->getParent()->end())
1600 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1602 // Create a new basic block to hold the code for loading the address
1603 // of the jump table, and jumping to it. Update successor information;
1604 // we will either branch to the default case for the switch, or the jump
1606 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1607 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1608 CR.CaseBB->addSuccessor(Default);
1609 CR.CaseBB->addSuccessor(JumpTableBB);
1611 // Build a vector of destination BBs, corresponding to each target
1612 // of the jump table. If the value of the jump table slot corresponds to
1613 // a case statement, push the case's BB onto the vector, otherwise, push
1615 std::vector<MachineBasicBlock*> DestBBs;
1616 int64_t TEI = First;
1617 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1618 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1619 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1621 if ((Low <= TEI) && (TEI <= High)) {
1622 DestBBs.push_back(I->BB);
1626 DestBBs.push_back(Default);
1630 // Update successor info. Add one edge to each unique successor.
1631 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1632 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1633 E = DestBBs.end(); I != E; ++I) {
1634 if (!SuccsHandled[(*I)->getNumber()]) {
1635 SuccsHandled[(*I)->getNumber()] = true;
1636 JumpTableBB->addSuccessor(*I);
1640 // Create a jump table index for this jump table, or return an existing
1642 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1644 // Set the jump table information so that we can codegen it as a second
1645 // MachineBasicBlock
1646 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1647 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1648 (CR.CaseBB == CurMBB));
1649 if (CR.CaseBB == CurMBB)
1650 visitJumpTableHeader(JT, JTH);
1652 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1657 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1659 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1660 CaseRecVector& WorkList,
1662 MachineBasicBlock* Default) {
1663 // Get the MachineFunction which holds the current MBB. This is used when
1664 // inserting any additional MBBs necessary to represent the switch.
1665 MachineFunction *CurMF = CurMBB->getParent();
1667 // Figure out which block is immediately after the current one.
1668 MachineBasicBlock *NextBlock = 0;
1669 MachineFunction::iterator BBI = CR.CaseBB;
1671 if (++BBI != CurMBB->getParent()->end())
1674 Case& FrontCase = *CR.Range.first;
1675 Case& BackCase = *(CR.Range.second-1);
1676 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1678 // Size is the number of Cases represented by this range.
1679 unsigned Size = CR.Range.second - CR.Range.first;
1681 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1682 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1684 CaseItr Pivot = CR.Range.first + Size/2;
1686 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1687 // (heuristically) allow us to emit JumpTable's later.
1689 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1693 uint64_t LSize = FrontCase.size();
1694 uint64_t RSize = TSize-LSize;
1695 DOUT << "Selecting best pivot: \n"
1696 << "First: " << First << ", Last: " << Last <<"\n"
1697 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1698 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1700 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1701 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1702 assert((RBegin-LEnd>=1) && "Invalid case distance");
1703 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1704 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1705 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1706 // Should always split in some non-trivial place
1708 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1709 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1710 << "Metric: " << Metric << "\n";
1711 if (FMetric < Metric) {
1714 DOUT << "Current metric set to: " << FMetric << "\n";
1720 if (areJTsAllowed(TLI)) {
1721 // If our case is dense we *really* should handle it earlier!
1722 assert((FMetric > 0) && "Should handle dense range earlier!");
1724 Pivot = CR.Range.first + Size/2;
1727 CaseRange LHSR(CR.Range.first, Pivot);
1728 CaseRange RHSR(Pivot, CR.Range.second);
1729 Constant *C = Pivot->Low;
1730 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1732 // We know that we branch to the LHS if the Value being switched on is
1733 // less than the Pivot value, C. We use this to optimize our binary
1734 // tree a bit, by recognizing that if SV is greater than or equal to the
1735 // LHS's Case Value, and that Case Value is exactly one less than the
1736 // Pivot's Value, then we can branch directly to the LHS's Target,
1737 // rather than creating a leaf node for it.
1738 if ((LHSR.second - LHSR.first) == 1 &&
1739 LHSR.first->High == CR.GE &&
1740 cast<ConstantInt>(C)->getSExtValue() ==
1741 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1742 TrueBB = LHSR.first->BB;
1744 TrueBB = new MachineBasicBlock(LLVMBB);
1745 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1746 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1749 // Similar to the optimization above, if the Value being switched on is
1750 // known to be less than the Constant CR.LT, and the current Case Value
1751 // is CR.LT - 1, then we can branch directly to the target block for
1752 // the current Case Value, rather than emitting a RHS leaf node for it.
1753 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1754 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1755 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1756 FalseBB = RHSR.first->BB;
1758 FalseBB = new MachineBasicBlock(LLVMBB);
1759 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1760 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1763 // Create a CaseBlock record representing a conditional branch to
1764 // the LHS node if the value being switched on SV is less than C.
1765 // Otherwise, branch to LHS.
1766 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1767 TrueBB, FalseBB, CR.CaseBB);
1769 if (CR.CaseBB == CurMBB)
1770 visitSwitchCase(CB);
1772 SwitchCases.push_back(CB);
1777 /// handleBitTestsSwitchCase - if current case range has few destination and
1778 /// range span less, than machine word bitwidth, encode case range into series
1779 /// of masks and emit bit tests with these masks.
1780 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1781 CaseRecVector& WorkList,
1783 MachineBasicBlock* Default){
1784 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1786 Case& FrontCase = *CR.Range.first;
1787 Case& BackCase = *(CR.Range.second-1);
1789 // Get the MachineFunction which holds the current MBB. This is used when
1790 // inserting any additional MBBs necessary to represent the switch.
1791 MachineFunction *CurMF = CurMBB->getParent();
1793 unsigned numCmps = 0;
1794 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1796 // Single case counts one, case range - two.
1797 if (I->Low == I->High)
1803 // Count unique destinations
1804 SmallSet<MachineBasicBlock*, 4> Dests;
1805 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1806 Dests.insert(I->BB);
1807 if (Dests.size() > 3)
1808 // Don't bother the code below, if there are too much unique destinations
1811 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1812 << "Total number of comparisons: " << numCmps << "\n";
1814 // Compute span of values.
1815 Constant* minValue = FrontCase.Low;
1816 Constant* maxValue = BackCase.High;
1817 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1818 cast<ConstantInt>(minValue)->getSExtValue();
1819 DOUT << "Compare range: " << range << "\n"
1820 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1821 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1823 if (range>=IntPtrBits ||
1824 (!(Dests.size() == 1 && numCmps >= 3) &&
1825 !(Dests.size() == 2 && numCmps >= 5) &&
1826 !(Dests.size() >= 3 && numCmps >= 6)))
1829 DOUT << "Emitting bit tests\n";
1830 int64_t lowBound = 0;
1832 // Optimize the case where all the case values fit in a
1833 // word without having to subtract minValue. In this case,
1834 // we can optimize away the subtraction.
1835 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1836 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1837 range = cast<ConstantInt>(maxValue)->getSExtValue();
1839 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1842 CaseBitsVector CasesBits;
1843 unsigned i, count = 0;
1845 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1846 MachineBasicBlock* Dest = I->BB;
1847 for (i = 0; i < count; ++i)
1848 if (Dest == CasesBits[i].BB)
1852 assert((count < 3) && "Too much destinations to test!");
1853 CasesBits.push_back(CaseBits(0, Dest, 0));
1857 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1858 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1860 for (uint64_t j = lo; j <= hi; j++) {
1861 CasesBits[i].Mask |= 1ULL << j;
1862 CasesBits[i].Bits++;
1866 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1868 SelectionDAGISel::BitTestInfo BTC;
1870 // Figure out which block is immediately after the current one.
1871 MachineFunction::iterator BBI = CR.CaseBB;
1874 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1877 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1878 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1879 << ", BB: " << CasesBits[i].BB << "\n";
1881 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1882 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1883 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1888 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1889 -1U, (CR.CaseBB == CurMBB),
1890 CR.CaseBB, Default, BTC);
1892 if (CR.CaseBB == CurMBB)
1893 visitBitTestHeader(BTB);
1895 BitTestCases.push_back(BTB);
1901 // Clusterify - Transform simple list of Cases into list of CaseRange's
1902 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1903 const SwitchInst& SI) {
1904 unsigned numCmps = 0;
1906 // Start with "simple" cases
1907 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1908 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1909 Cases.push_back(Case(SI.getSuccessorValue(i),
1910 SI.getSuccessorValue(i),
1913 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1915 // Merge case into clusters
1916 if (Cases.size()>=2)
1917 // Must recompute end() each iteration because it may be
1918 // invalidated by erase if we hold on to it
1919 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1920 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1921 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1922 MachineBasicBlock* nextBB = J->BB;
1923 MachineBasicBlock* currentBB = I->BB;
1925 // If the two neighboring cases go to the same destination, merge them
1926 // into a single case.
1927 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1935 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1936 if (I->Low != I->High)
1937 // A range counts double, since it requires two compares.
1944 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1945 // Figure out which block is immediately after the current one.
1946 MachineBasicBlock *NextBlock = 0;
1947 MachineFunction::iterator BBI = CurMBB;
1949 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1951 // If there is only the default destination, branch to it if it is not the
1952 // next basic block. Otherwise, just fall through.
1953 if (SI.getNumOperands() == 2) {
1954 // Update machine-CFG edges.
1956 // If this is not a fall-through branch, emit the branch.
1957 if (Default != NextBlock)
1958 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1959 DAG.getBasicBlock(Default)));
1961 CurMBB->addSuccessor(Default);
1965 // If there are any non-default case statements, create a vector of Cases
1966 // representing each one, and sort the vector so that we can efficiently
1967 // create a binary search tree from them.
1969 unsigned numCmps = Clusterify(Cases, SI);
1970 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1971 << ". Total compares: " << numCmps << "\n";
1973 // Get the Value to be switched on and default basic blocks, which will be
1974 // inserted into CaseBlock records, representing basic blocks in the binary
1976 Value *SV = SI.getOperand(0);
1978 // Push the initial CaseRec onto the worklist
1979 CaseRecVector WorkList;
1980 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1982 while (!WorkList.empty()) {
1983 // Grab a record representing a case range to process off the worklist
1984 CaseRec CR = WorkList.back();
1985 WorkList.pop_back();
1987 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1990 // If the range has few cases (two or less) emit a series of specific
1992 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1995 // If the switch has more than 5 blocks, and at least 40% dense, and the
1996 // target supports indirect branches, then emit a jump table rather than
1997 // lowering the switch to a binary tree of conditional branches.
1998 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2001 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2002 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2003 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2008 void SelectionDAGLowering::visitSub(User &I) {
2009 // -0.0 - X --> fneg
2010 const Type *Ty = I.getType();
2011 if (isa<VectorType>(Ty)) {
2012 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2013 const VectorType *DestTy = cast<VectorType>(I.getType());
2014 const Type *ElTy = DestTy->getElementType();
2015 if (ElTy->isFloatingPoint()) {
2016 unsigned VL = DestTy->getNumElements();
2017 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2018 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2020 SDOperand Op2 = getValue(I.getOperand(1));
2021 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2027 if (Ty->isFloatingPoint()) {
2028 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2029 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2030 SDOperand Op2 = getValue(I.getOperand(1));
2031 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2036 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2039 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2040 SDOperand Op1 = getValue(I.getOperand(0));
2041 SDOperand Op2 = getValue(I.getOperand(1));
2043 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2046 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2047 SDOperand Op1 = getValue(I.getOperand(0));
2048 SDOperand Op2 = getValue(I.getOperand(1));
2050 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2051 MVT::getSizeInBits(Op2.getValueType()))
2052 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2053 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2054 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2056 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2059 void SelectionDAGLowering::visitICmp(User &I) {
2060 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2061 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2062 predicate = IC->getPredicate();
2063 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2064 predicate = ICmpInst::Predicate(IC->getPredicate());
2065 SDOperand Op1 = getValue(I.getOperand(0));
2066 SDOperand Op2 = getValue(I.getOperand(1));
2067 ISD::CondCode Opcode;
2068 switch (predicate) {
2069 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2070 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2071 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2072 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2073 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2074 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2075 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2076 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2077 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2078 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2080 assert(!"Invalid ICmp predicate value");
2081 Opcode = ISD::SETEQ;
2084 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2087 void SelectionDAGLowering::visitFCmp(User &I) {
2088 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2089 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2090 predicate = FC->getPredicate();
2091 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2092 predicate = FCmpInst::Predicate(FC->getPredicate());
2093 SDOperand Op1 = getValue(I.getOperand(0));
2094 SDOperand Op2 = getValue(I.getOperand(1));
2095 ISD::CondCode Condition, FOC, FPC;
2096 switch (predicate) {
2097 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2098 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2099 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2100 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2101 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2102 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2103 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2104 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2105 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2106 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2107 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2108 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2109 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2110 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2111 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2112 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2114 assert(!"Invalid FCmp predicate value");
2115 FOC = FPC = ISD::SETFALSE;
2118 if (FiniteOnlyFPMath())
2122 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2125 void SelectionDAGLowering::visitSelect(User &I) {
2126 SDOperand Cond = getValue(I.getOperand(0));
2127 SDOperand TrueVal = getValue(I.getOperand(1));
2128 SDOperand FalseVal = getValue(I.getOperand(2));
2129 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2130 TrueVal, FalseVal));
2134 void SelectionDAGLowering::visitTrunc(User &I) {
2135 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2136 SDOperand N = getValue(I.getOperand(0));
2137 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2138 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2141 void SelectionDAGLowering::visitZExt(User &I) {
2142 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2143 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2144 SDOperand N = getValue(I.getOperand(0));
2145 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2146 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2149 void SelectionDAGLowering::visitSExt(User &I) {
2150 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2151 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2152 SDOperand N = getValue(I.getOperand(0));
2153 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2154 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2157 void SelectionDAGLowering::visitFPTrunc(User &I) {
2158 // FPTrunc is never a no-op cast, no need to check
2159 SDOperand N = getValue(I.getOperand(0));
2160 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2161 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
2164 void SelectionDAGLowering::visitFPExt(User &I){
2165 // FPTrunc is never a no-op cast, no need to check
2166 SDOperand N = getValue(I.getOperand(0));
2167 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2168 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2171 void SelectionDAGLowering::visitFPToUI(User &I) {
2172 // FPToUI is never a no-op cast, no need to check
2173 SDOperand N = getValue(I.getOperand(0));
2174 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2175 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2178 void SelectionDAGLowering::visitFPToSI(User &I) {
2179 // FPToSI is never a no-op cast, no need to check
2180 SDOperand N = getValue(I.getOperand(0));
2181 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2182 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2185 void SelectionDAGLowering::visitUIToFP(User &I) {
2186 // UIToFP is never a no-op cast, no need to check
2187 SDOperand N = getValue(I.getOperand(0));
2188 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2189 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2192 void SelectionDAGLowering::visitSIToFP(User &I){
2193 // UIToFP is never a no-op cast, no need to check
2194 SDOperand N = getValue(I.getOperand(0));
2195 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2196 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2199 void SelectionDAGLowering::visitPtrToInt(User &I) {
2200 // What to do depends on the size of the integer and the size of the pointer.
2201 // We can either truncate, zero extend, or no-op, accordingly.
2202 SDOperand N = getValue(I.getOperand(0));
2203 MVT::ValueType SrcVT = N.getValueType();
2204 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2206 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2207 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2209 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2210 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2211 setValue(&I, Result);
2214 void SelectionDAGLowering::visitIntToPtr(User &I) {
2215 // What to do depends on the size of the integer and the size of the pointer.
2216 // We can either truncate, zero extend, or no-op, accordingly.
2217 SDOperand N = getValue(I.getOperand(0));
2218 MVT::ValueType SrcVT = N.getValueType();
2219 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2220 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2221 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2223 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2224 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2227 void SelectionDAGLowering::visitBitCast(User &I) {
2228 SDOperand N = getValue(I.getOperand(0));
2229 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2231 // BitCast assures us that source and destination are the same size so this
2232 // is either a BIT_CONVERT or a no-op.
2233 if (DestVT != N.getValueType())
2234 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2236 setValue(&I, N); // noop cast.
2239 void SelectionDAGLowering::visitInsertElement(User &I) {
2240 SDOperand InVec = getValue(I.getOperand(0));
2241 SDOperand InVal = getValue(I.getOperand(1));
2242 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2243 getValue(I.getOperand(2)));
2245 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2246 TLI.getValueType(I.getType()),
2247 InVec, InVal, InIdx));
2250 void SelectionDAGLowering::visitExtractElement(User &I) {
2251 SDOperand InVec = getValue(I.getOperand(0));
2252 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2253 getValue(I.getOperand(1)));
2254 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2255 TLI.getValueType(I.getType()), InVec, InIdx));
2258 void SelectionDAGLowering::visitShuffleVector(User &I) {
2259 SDOperand V1 = getValue(I.getOperand(0));
2260 SDOperand V2 = getValue(I.getOperand(1));
2261 SDOperand Mask = getValue(I.getOperand(2));
2263 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2264 TLI.getValueType(I.getType()),
2269 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2270 SDOperand N = getValue(I.getOperand(0));
2271 const Type *Ty = I.getOperand(0)->getType();
2273 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2276 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2277 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2280 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2281 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2282 getIntPtrConstant(Offset));
2284 Ty = StTy->getElementType(Field);
2286 Ty = cast<SequentialType>(Ty)->getElementType();
2288 // If this is a constant subscript, handle it quickly.
2289 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2290 if (CI->getZExtValue() == 0) continue;
2292 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2293 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
2297 // N = N + Idx * ElementSize;
2298 uint64_t ElementSize = TD->getABITypeSize(Ty);
2299 SDOperand IdxN = getValue(Idx);
2301 // If the index is smaller or larger than intptr_t, truncate or extend
2303 if (IdxN.getValueType() < N.getValueType()) {
2304 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2305 } else if (IdxN.getValueType() > N.getValueType())
2306 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2308 // If this is a multiply by a power of two, turn it into a shl
2309 // immediately. This is a very common case.
2310 if (isPowerOf2_64(ElementSize)) {
2311 unsigned Amt = Log2_64(ElementSize);
2312 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2313 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2314 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2318 SDOperand Scale = getIntPtrConstant(ElementSize);
2319 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2320 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2326 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2327 // If this is a fixed sized alloca in the entry block of the function,
2328 // allocate it statically on the stack.
2329 if (FuncInfo.StaticAllocaMap.count(&I))
2330 return; // getValue will auto-populate this.
2332 const Type *Ty = I.getAllocatedType();
2333 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2335 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2338 SDOperand AllocSize = getValue(I.getArraySize());
2339 MVT::ValueType IntPtr = TLI.getPointerTy();
2340 if (IntPtr < AllocSize.getValueType())
2341 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2342 else if (IntPtr > AllocSize.getValueType())
2343 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2345 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2346 getIntPtrConstant(TySize));
2348 // Handle alignment. If the requested alignment is less than or equal to
2349 // the stack alignment, ignore it. If the size is greater than or equal to
2350 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2351 unsigned StackAlign =
2352 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2353 if (Align <= StackAlign)
2356 // Round the size of the allocation up to the stack alignment size
2357 // by add SA-1 to the size.
2358 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2359 getIntPtrConstant(StackAlign-1));
2360 // Mask out the low bits for alignment purposes.
2361 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2362 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2364 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
2365 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2367 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2369 DAG.setRoot(DSA.getValue(1));
2371 // Inform the Frame Information that we have just allocated a variable-sized
2373 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2376 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2377 SDOperand Ptr = getValue(I.getOperand(0));
2383 // Do not serialize non-volatile loads against each other.
2384 Root = DAG.getRoot();
2387 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2388 Root, I.isVolatile(), I.getAlignment()));
2391 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2392 const Value *SV, SDOperand Root,
2394 unsigned Alignment) {
2396 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2397 isVolatile, Alignment);
2400 DAG.setRoot(L.getValue(1));
2402 PendingLoads.push_back(L.getValue(1));
2408 void SelectionDAGLowering::visitStore(StoreInst &I) {
2409 Value *SrcV = I.getOperand(0);
2410 SDOperand Src = getValue(SrcV);
2411 SDOperand Ptr = getValue(I.getOperand(1));
2412 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2413 I.isVolatile(), I.getAlignment()));
2416 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2418 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2419 unsigned Intrinsic) {
2420 bool HasChain = !I.doesNotAccessMemory();
2421 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2423 // Build the operand list.
2424 SmallVector<SDOperand, 8> Ops;
2425 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2427 // We don't need to serialize loads against other loads.
2428 Ops.push_back(DAG.getRoot());
2430 Ops.push_back(getRoot());
2434 // Add the intrinsic ID as an integer operand.
2435 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2437 // Add all operands of the call to the operand list.
2438 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2439 SDOperand Op = getValue(I.getOperand(i));
2440 assert(TLI.isTypeLegal(Op.getValueType()) &&
2441 "Intrinsic uses a non-legal type?");
2445 std::vector<MVT::ValueType> VTs;
2446 if (I.getType() != Type::VoidTy) {
2447 MVT::ValueType VT = TLI.getValueType(I.getType());
2448 if (MVT::isVector(VT)) {
2449 const VectorType *DestTy = cast<VectorType>(I.getType());
2450 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2452 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2453 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2456 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2460 VTs.push_back(MVT::Other);
2462 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2467 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2468 &Ops[0], Ops.size());
2469 else if (I.getType() != Type::VoidTy)
2470 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2471 &Ops[0], Ops.size());
2473 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2474 &Ops[0], Ops.size());
2477 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2479 PendingLoads.push_back(Chain);
2483 if (I.getType() != Type::VoidTy) {
2484 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2485 MVT::ValueType VT = TLI.getValueType(PTy);
2486 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2488 setValue(&I, Result);
2492 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2493 static GlobalVariable *ExtractTypeInfo (Value *V) {
2494 V = IntrinsicInst::StripPointerCasts(V);
2495 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2496 assert (GV || isa<ConstantPointerNull>(V) &&
2497 "TypeInfo must be a global variable or NULL");
2501 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2502 /// call, and add them to the specified machine basic block.
2503 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2504 MachineBasicBlock *MBB) {
2505 // Inform the MachineModuleInfo of the personality for this landing pad.
2506 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2507 assert(CE->getOpcode() == Instruction::BitCast &&
2508 isa<Function>(CE->getOperand(0)) &&
2509 "Personality should be a function");
2510 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2512 // Gather all the type infos for this landing pad and pass them along to
2513 // MachineModuleInfo.
2514 std::vector<GlobalVariable *> TyInfo;
2515 unsigned N = I.getNumOperands();
2517 for (unsigned i = N - 1; i > 2; --i) {
2518 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2519 unsigned FilterLength = CI->getZExtValue();
2520 unsigned FirstCatch = i + FilterLength + !FilterLength;
2521 assert (FirstCatch <= N && "Invalid filter length");
2523 if (FirstCatch < N) {
2524 TyInfo.reserve(N - FirstCatch);
2525 for (unsigned j = FirstCatch; j < N; ++j)
2526 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2527 MMI->addCatchTypeInfo(MBB, TyInfo);
2531 if (!FilterLength) {
2533 MMI->addCleanup(MBB);
2536 TyInfo.reserve(FilterLength - 1);
2537 for (unsigned j = i + 1; j < FirstCatch; ++j)
2538 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2539 MMI->addFilterTypeInfo(MBB, TyInfo);
2548 TyInfo.reserve(N - 3);
2549 for (unsigned j = 3; j < N; ++j)
2550 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2551 MMI->addCatchTypeInfo(MBB, TyInfo);
2555 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2556 /// we want to emit this as a call to a named external function, return the name
2557 /// otherwise lower it and return null.
2559 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2560 switch (Intrinsic) {
2562 // By default, turn this into a target intrinsic node.
2563 visitTargetIntrinsic(I, Intrinsic);
2565 case Intrinsic::vastart: visitVAStart(I); return 0;
2566 case Intrinsic::vaend: visitVAEnd(I); return 0;
2567 case Intrinsic::vacopy: visitVACopy(I); return 0;
2568 case Intrinsic::returnaddress:
2569 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2570 getValue(I.getOperand(1))));
2572 case Intrinsic::frameaddress:
2573 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2574 getValue(I.getOperand(1))));
2576 case Intrinsic::setjmp:
2577 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2579 case Intrinsic::longjmp:
2580 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2582 case Intrinsic::memcpy_i32:
2583 case Intrinsic::memcpy_i64:
2584 visitMemIntrinsic(I, ISD::MEMCPY);
2586 case Intrinsic::memset_i32:
2587 case Intrinsic::memset_i64:
2588 visitMemIntrinsic(I, ISD::MEMSET);
2590 case Intrinsic::memmove_i32:
2591 case Intrinsic::memmove_i64:
2592 visitMemIntrinsic(I, ISD::MEMMOVE);
2595 case Intrinsic::dbg_stoppoint: {
2596 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2597 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2598 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2602 Ops[1] = getValue(SPI.getLineValue());
2603 Ops[2] = getValue(SPI.getColumnValue());
2605 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2606 assert(DD && "Not a debug information descriptor");
2607 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2609 Ops[3] = DAG.getString(CompileUnit->getFileName());
2610 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2612 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2617 case Intrinsic::dbg_region_start: {
2618 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2619 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2620 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2621 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2622 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2623 DAG.getConstant(LabelID, MVT::i32)));
2628 case Intrinsic::dbg_region_end: {
2629 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2630 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2631 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2632 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2633 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2634 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2639 case Intrinsic::dbg_func_start: {
2640 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2641 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2642 if (MMI && FSI.getSubprogram() &&
2643 MMI->Verify(FSI.getSubprogram())) {
2644 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
2645 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2646 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2651 case Intrinsic::dbg_declare: {
2652 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2653 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2654 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
2655 SDOperand AddressOp = getValue(DI.getAddress());
2656 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2657 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
2663 case Intrinsic::eh_exception: {
2664 if (ExceptionHandling) {
2665 if (!CurMBB->isLandingPad()) {
2666 // FIXME: Mark exception register as live in. Hack for PR1508.
2667 unsigned Reg = TLI.getExceptionAddressRegister();
2668 if (Reg) CurMBB->addLiveIn(Reg);
2670 // Insert the EXCEPTIONADDR instruction.
2671 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2673 Ops[0] = DAG.getRoot();
2674 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2676 DAG.setRoot(Op.getValue(1));
2678 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2683 case Intrinsic::eh_selector_i32:
2684 case Intrinsic::eh_selector_i64: {
2685 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2686 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2687 MVT::i32 : MVT::i64);
2689 if (ExceptionHandling && MMI) {
2690 if (CurMBB->isLandingPad())
2691 addCatchInfo(I, MMI, CurMBB);
2694 FuncInfo.CatchInfoLost.insert(&I);
2696 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2697 unsigned Reg = TLI.getExceptionSelectorRegister();
2698 if (Reg) CurMBB->addLiveIn(Reg);
2701 // Insert the EHSELECTION instruction.
2702 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2704 Ops[0] = getValue(I.getOperand(1));
2706 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2708 DAG.setRoot(Op.getValue(1));
2710 setValue(&I, DAG.getConstant(0, VT));
2716 case Intrinsic::eh_typeid_for_i32:
2717 case Intrinsic::eh_typeid_for_i64: {
2718 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2719 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2720 MVT::i32 : MVT::i64);
2723 // Find the type id for the given typeinfo.
2724 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2726 unsigned TypeID = MMI->getTypeIDFor(GV);
2727 setValue(&I, DAG.getConstant(TypeID, VT));
2729 // Return something different to eh_selector.
2730 setValue(&I, DAG.getConstant(1, VT));
2736 case Intrinsic::eh_return: {
2737 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2739 if (MMI && ExceptionHandling) {
2740 MMI->setCallsEHReturn(true);
2741 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2744 getValue(I.getOperand(1)),
2745 getValue(I.getOperand(2))));
2747 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2753 case Intrinsic::eh_unwind_init: {
2754 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2755 MMI->setCallsUnwindInit(true);
2761 case Intrinsic::eh_dwarf_cfa: {
2762 if (ExceptionHandling) {
2763 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2765 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2766 CfaArg = DAG.getNode(ISD::TRUNCATE,
2767 TLI.getPointerTy(), getValue(I.getOperand(1)));
2769 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2770 TLI.getPointerTy(), getValue(I.getOperand(1)));
2772 SDOperand Offset = DAG.getNode(ISD::ADD,
2774 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2775 TLI.getPointerTy()),
2777 setValue(&I, DAG.getNode(ISD::ADD,
2779 DAG.getNode(ISD::FRAMEADDR,
2782 TLI.getPointerTy())),
2785 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2791 case Intrinsic::sqrt:
2792 setValue(&I, DAG.getNode(ISD::FSQRT,
2793 getValue(I.getOperand(1)).getValueType(),
2794 getValue(I.getOperand(1))));
2796 case Intrinsic::powi:
2797 setValue(&I, DAG.getNode(ISD::FPOWI,
2798 getValue(I.getOperand(1)).getValueType(),
2799 getValue(I.getOperand(1)),
2800 getValue(I.getOperand(2))));
2802 case Intrinsic::sin:
2803 setValue(&I, DAG.getNode(ISD::FSIN,
2804 getValue(I.getOperand(1)).getValueType(),
2805 getValue(I.getOperand(1))));
2807 case Intrinsic::cos:
2808 setValue(&I, DAG.getNode(ISD::FCOS,
2809 getValue(I.getOperand(1)).getValueType(),
2810 getValue(I.getOperand(1))));
2812 case Intrinsic::pow:
2813 setValue(&I, DAG.getNode(ISD::FPOW,
2814 getValue(I.getOperand(1)).getValueType(),
2815 getValue(I.getOperand(1)),
2816 getValue(I.getOperand(2))));
2818 case Intrinsic::pcmarker: {
2819 SDOperand Tmp = getValue(I.getOperand(1));
2820 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2823 case Intrinsic::readcyclecounter: {
2824 SDOperand Op = getRoot();
2825 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2826 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2829 DAG.setRoot(Tmp.getValue(1));
2832 case Intrinsic::part_select: {
2833 // Currently not implemented: just abort
2834 assert(0 && "part_select intrinsic not implemented");
2837 case Intrinsic::part_set: {
2838 // Currently not implemented: just abort
2839 assert(0 && "part_set intrinsic not implemented");
2842 case Intrinsic::bswap:
2843 setValue(&I, DAG.getNode(ISD::BSWAP,
2844 getValue(I.getOperand(1)).getValueType(),
2845 getValue(I.getOperand(1))));
2847 case Intrinsic::cttz: {
2848 SDOperand Arg = getValue(I.getOperand(1));
2849 MVT::ValueType Ty = Arg.getValueType();
2850 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2851 setValue(&I, result);
2854 case Intrinsic::ctlz: {
2855 SDOperand Arg = getValue(I.getOperand(1));
2856 MVT::ValueType Ty = Arg.getValueType();
2857 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2858 setValue(&I, result);
2861 case Intrinsic::ctpop: {
2862 SDOperand Arg = getValue(I.getOperand(1));
2863 MVT::ValueType Ty = Arg.getValueType();
2864 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2865 setValue(&I, result);
2868 case Intrinsic::stacksave: {
2869 SDOperand Op = getRoot();
2870 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2871 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2873 DAG.setRoot(Tmp.getValue(1));
2876 case Intrinsic::stackrestore: {
2877 SDOperand Tmp = getValue(I.getOperand(1));
2878 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2881 case Intrinsic::prefetch:
2882 // FIXME: Currently discarding prefetches.
2885 case Intrinsic::var_annotation:
2886 // Discard annotate attributes
2889 case Intrinsic::init_trampoline: {
2891 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
2895 Ops[1] = getValue(I.getOperand(1));
2896 Ops[2] = getValue(I.getOperand(2));
2897 Ops[3] = getValue(I.getOperand(3));
2898 Ops[4] = DAG.getSrcValue(I.getOperand(1));
2899 Ops[5] = DAG.getSrcValue(F);
2901 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
2902 DAG.getNodeValueTypes(TLI.getPointerTy(),
2907 DAG.setRoot(Tmp.getValue(1));
2910 case Intrinsic::flt_rounds: {
2911 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32));
2918 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
2920 MachineBasicBlock *LandingPad) {
2921 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2922 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2923 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2924 unsigned BeginLabel = 0, EndLabel = 0;
2926 TargetLowering::ArgListTy Args;
2927 TargetLowering::ArgListEntry Entry;
2928 Args.reserve(CS.arg_size());
2929 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2931 SDOperand ArgNode = getValue(*i);
2932 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
2934 unsigned attrInd = i - CS.arg_begin() + 1;
2935 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
2936 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
2937 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
2938 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
2939 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
2940 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
2941 Args.push_back(Entry);
2944 bool MarkTryRange = LandingPad ||
2945 // C++ requires special handling of 'nounwind' calls.
2946 (CS.doesNotThrow());
2948 if (MarkTryRange && ExceptionHandling && MMI) {
2949 // Insert a label before the invoke call to mark the try range. This can be
2950 // used to detect deletion of the invoke via the MachineModuleInfo.
2951 BeginLabel = MMI->NextLabelID();
2952 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2953 DAG.getConstant(BeginLabel, MVT::i32)));
2956 std::pair<SDOperand,SDOperand> Result =
2957 TLI.LowerCallTo(getRoot(), CS.getType(),
2958 CS.paramHasAttr(0, ParamAttr::SExt),
2959 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
2961 if (CS.getType() != Type::VoidTy)
2962 setValue(CS.getInstruction(), Result.first);
2963 DAG.setRoot(Result.second);
2965 if (MarkTryRange && ExceptionHandling && MMI) {
2966 // Insert a label at the end of the invoke call to mark the try range. This
2967 // can be used to detect deletion of the invoke via the MachineModuleInfo.
2968 EndLabel = MMI->NextLabelID();
2969 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2970 DAG.getConstant(EndLabel, MVT::i32)));
2972 // Inform MachineModuleInfo of range.
2973 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
2978 void SelectionDAGLowering::visitCall(CallInst &I) {
2979 const char *RenameFn = 0;
2980 if (Function *F = I.getCalledFunction()) {
2981 if (F->isDeclaration()) {
2982 if (unsigned IID = F->getIntrinsicID()) {
2983 RenameFn = visitIntrinsicCall(I, IID);
2989 // Check for well-known libc/libm calls. If the function is internal, it
2990 // can't be a library call.
2991 unsigned NameLen = F->getNameLen();
2992 if (!F->hasInternalLinkage() && NameLen) {
2993 const char *NameStr = F->getNameStart();
2994 if (NameStr[0] == 'c' &&
2995 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
2996 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
2997 if (I.getNumOperands() == 3 && // Basic sanity checks.
2998 I.getOperand(1)->getType()->isFloatingPoint() &&
2999 I.getType() == I.getOperand(1)->getType() &&
3000 I.getType() == I.getOperand(2)->getType()) {
3001 SDOperand LHS = getValue(I.getOperand(1));
3002 SDOperand RHS = getValue(I.getOperand(2));
3003 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3007 } else if (NameStr[0] == 'f' &&
3008 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3009 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3010 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3011 if (I.getNumOperands() == 2 && // Basic sanity checks.
3012 I.getOperand(1)->getType()->isFloatingPoint() &&
3013 I.getType() == I.getOperand(1)->getType()) {
3014 SDOperand Tmp = getValue(I.getOperand(1));
3015 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3018 } else if (NameStr[0] == 's' &&
3019 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3020 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3021 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3022 if (I.getNumOperands() == 2 && // Basic sanity checks.
3023 I.getOperand(1)->getType()->isFloatingPoint() &&
3024 I.getType() == I.getOperand(1)->getType()) {
3025 SDOperand Tmp = getValue(I.getOperand(1));
3026 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3029 } else if (NameStr[0] == 'c' &&
3030 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3031 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3032 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3033 if (I.getNumOperands() == 2 && // Basic sanity checks.
3034 I.getOperand(1)->getType()->isFloatingPoint() &&
3035 I.getType() == I.getOperand(1)->getType()) {
3036 SDOperand Tmp = getValue(I.getOperand(1));
3037 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3042 } else if (isa<InlineAsm>(I.getOperand(0))) {
3049 Callee = getValue(I.getOperand(0));
3051 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3053 LowerCallTo(&I, Callee, I.isTailCall());
3057 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3058 /// this value and returns the result as a ValueVT value. This uses
3059 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3060 /// If the Flag pointer is NULL, no flag is used.
3061 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3062 SDOperand &Chain, SDOperand *Flag)const{
3063 // Copy the legal parts from the registers.
3064 unsigned NumParts = Regs.size();
3065 SmallVector<SDOperand, 8> Parts(NumParts);
3066 for (unsigned i = 0; i != NumParts; ++i) {
3067 SDOperand Part = Flag ?
3068 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3069 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3070 Chain = Part.getValue(1);
3072 *Flag = Part.getValue(2);
3076 // Assemble the legal parts into the final value.
3077 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3080 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3081 /// specified value into the registers specified by this object. This uses
3082 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3083 /// If the Flag pointer is NULL, no flag is used.
3084 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3085 SDOperand &Chain, SDOperand *Flag) const {
3086 // Get the list of the values's legal parts.
3087 unsigned NumParts = Regs.size();
3088 SmallVector<SDOperand, 8> Parts(NumParts);
3089 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3091 // Copy the parts into the registers.
3092 for (unsigned i = 0; i != NumParts; ++i) {
3093 SDOperand Part = Flag ?
3094 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3095 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3096 Chain = Part.getValue(0);
3098 *Flag = Part.getValue(1);
3102 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3103 /// operand list. This adds the code marker and includes the number of
3104 /// values added into it.
3105 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3106 std::vector<SDOperand> &Ops) const {
3107 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3108 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3109 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3110 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3113 /// isAllocatableRegister - If the specified register is safe to allocate,
3114 /// i.e. it isn't a stack pointer or some other special register, return the
3115 /// register class for the register. Otherwise, return null.
3116 static const TargetRegisterClass *
3117 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3118 const TargetLowering &TLI, const MRegisterInfo *MRI) {
3119 MVT::ValueType FoundVT = MVT::Other;
3120 const TargetRegisterClass *FoundRC = 0;
3121 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
3122 E = MRI->regclass_end(); RCI != E; ++RCI) {
3123 MVT::ValueType ThisVT = MVT::Other;
3125 const TargetRegisterClass *RC = *RCI;
3126 // If none of the the value types for this register class are valid, we
3127 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3128 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3130 if (TLI.isTypeLegal(*I)) {
3131 // If we have already found this register in a different register class,
3132 // choose the one with the largest VT specified. For example, on
3133 // PowerPC, we favor f64 register classes over f32.
3134 if (FoundVT == MVT::Other ||
3135 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3142 if (ThisVT == MVT::Other) continue;
3144 // NOTE: This isn't ideal. In particular, this might allocate the
3145 // frame pointer in functions that need it (due to them not being taken
3146 // out of allocation, because a variable sized allocation hasn't been seen
3147 // yet). This is a slight code pessimization, but should still work.
3148 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3149 E = RC->allocation_order_end(MF); I != E; ++I)
3151 // We found a matching register class. Keep looking at others in case
3152 // we find one with larger registers that this physreg is also in.
3163 /// AsmOperandInfo - This contains information for each constraint that we are
3165 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3166 /// ConstraintCode - This contains the actual string for the code, like "m".
3167 std::string ConstraintCode;
3169 /// ConstraintType - Information about the constraint code, e.g. Register,
3170 /// RegisterClass, Memory, Other, Unknown.
3171 TargetLowering::ConstraintType ConstraintType;
3173 /// CallOperand/CallOperandval - If this is the result output operand or a
3174 /// clobber, this is null, otherwise it is the incoming operand to the
3175 /// CallInst. This gets modified as the asm is processed.
3176 SDOperand CallOperand;
3177 Value *CallOperandVal;
3179 /// ConstraintVT - The ValueType for the operand value.
3180 MVT::ValueType ConstraintVT;
3182 /// AssignedRegs - If this is a register or register class operand, this
3183 /// contains the set of register corresponding to the operand.
3184 RegsForValue AssignedRegs;
3186 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3187 : InlineAsm::ConstraintInfo(info),
3188 ConstraintType(TargetLowering::C_Unknown),
3189 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3192 void ComputeConstraintToUse(const TargetLowering &TLI);
3194 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3195 /// busy in OutputRegs/InputRegs.
3196 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3197 std::set<unsigned> &OutputRegs,
3198 std::set<unsigned> &InputRegs) const {
3200 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3202 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3205 } // end anon namespace.
3207 /// getConstraintGenerality - Return an integer indicating how general CT is.
3208 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3210 default: assert(0 && "Unknown constraint type!");
3211 case TargetLowering::C_Other:
3212 case TargetLowering::C_Unknown:
3214 case TargetLowering::C_Register:
3216 case TargetLowering::C_RegisterClass:
3218 case TargetLowering::C_Memory:
3223 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3224 assert(!Codes.empty() && "Must have at least one constraint");
3226 std::string *Current = &Codes[0];
3227 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3228 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3229 ConstraintCode = *Current;
3230 ConstraintType = CurType;
3234 unsigned CurGenerality = getConstraintGenerality(CurType);
3236 // If we have multiple constraints, try to pick the most general one ahead
3237 // of time. This isn't a wonderful solution, but handles common cases.
3238 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3239 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3240 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3241 if (ThisGenerality > CurGenerality) {
3242 // This constraint letter is more general than the previous one,
3245 Current = &Codes[j];
3246 CurGenerality = ThisGenerality;
3250 ConstraintCode = *Current;
3251 ConstraintType = CurType;
3255 void SelectionDAGLowering::
3256 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3257 std::set<unsigned> &OutputRegs,
3258 std::set<unsigned> &InputRegs) {
3259 // Compute whether this value requires an input register, an output register,
3261 bool isOutReg = false;
3262 bool isInReg = false;
3263 switch (OpInfo.Type) {
3264 case InlineAsm::isOutput:
3267 // If this is an early-clobber output, or if there is an input
3268 // constraint that matches this, we need to reserve the input register
3269 // so no other inputs allocate to it.
3270 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3272 case InlineAsm::isInput:
3276 case InlineAsm::isClobber:
3283 MachineFunction &MF = DAG.getMachineFunction();
3284 std::vector<unsigned> Regs;
3286 // If this is a constraint for a single physreg, or a constraint for a
3287 // register class, find it.
3288 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3289 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3290 OpInfo.ConstraintVT);
3292 unsigned NumRegs = 1;
3293 if (OpInfo.ConstraintVT != MVT::Other)
3294 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3295 MVT::ValueType RegVT;
3296 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3299 // If this is a constraint for a specific physical register, like {r17},
3301 if (PhysReg.first) {
3302 if (OpInfo.ConstraintVT == MVT::Other)
3303 ValueVT = *PhysReg.second->vt_begin();
3305 // Get the actual register value type. This is important, because the user
3306 // may have asked for (e.g.) the AX register in i32 type. We need to
3307 // remember that AX is actually i16 to get the right extension.
3308 RegVT = *PhysReg.second->vt_begin();
3310 // This is a explicit reference to a physical register.
3311 Regs.push_back(PhysReg.first);
3313 // If this is an expanded reference, add the rest of the regs to Regs.
3315 TargetRegisterClass::iterator I = PhysReg.second->begin();
3316 TargetRegisterClass::iterator E = PhysReg.second->end();
3317 for (; *I != PhysReg.first; ++I)
3318 assert(I != E && "Didn't find reg!");
3320 // Already added the first reg.
3322 for (; NumRegs; --NumRegs, ++I) {
3323 assert(I != E && "Ran out of registers to allocate!");
3327 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3328 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3332 // Otherwise, if this was a reference to an LLVM register class, create vregs
3333 // for this reference.
3334 std::vector<unsigned> RegClassRegs;
3335 const TargetRegisterClass *RC = PhysReg.second;
3337 // If this is an early clobber or tied register, our regalloc doesn't know
3338 // how to maintain the constraint. If it isn't, go ahead and create vreg
3339 // and let the regalloc do the right thing.
3340 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3341 // If there is some other early clobber and this is an input register,
3342 // then we are forced to pre-allocate the input reg so it doesn't
3343 // conflict with the earlyclobber.
3344 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3345 RegVT = *PhysReg.second->vt_begin();
3347 if (OpInfo.ConstraintVT == MVT::Other)
3350 // Create the appropriate number of virtual registers.
3351 SSARegMap *RegMap = MF.getSSARegMap();
3352 for (; NumRegs; --NumRegs)
3353 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
3355 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3356 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3360 // Otherwise, we can't allocate it. Let the code below figure out how to
3361 // maintain these constraints.
3362 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3365 // This is a reference to a register class that doesn't directly correspond
3366 // to an LLVM register class. Allocate NumRegs consecutive, available,
3367 // registers from the class.
3368 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3369 OpInfo.ConstraintVT);
3372 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3373 unsigned NumAllocated = 0;
3374 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3375 unsigned Reg = RegClassRegs[i];
3376 // See if this register is available.
3377 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3378 (isInReg && InputRegs.count(Reg))) { // Already used.
3379 // Make sure we find consecutive registers.
3384 // Check to see if this register is allocatable (i.e. don't give out the
3387 RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3388 if (!RC) { // Couldn't allocate this register.
3389 // Reset NumAllocated to make sure we return consecutive registers.
3395 // Okay, this register is good, we can use it.
3398 // If we allocated enough consecutive registers, succeed.
3399 if (NumAllocated == NumRegs) {
3400 unsigned RegStart = (i-NumAllocated)+1;
3401 unsigned RegEnd = i+1;
3402 // Mark all of the allocated registers used.
3403 for (unsigned i = RegStart; i != RegEnd; ++i)
3404 Regs.push_back(RegClassRegs[i]);
3406 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3407 OpInfo.ConstraintVT);
3408 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3413 // Otherwise, we couldn't allocate enough registers for this.
3418 /// visitInlineAsm - Handle a call to an InlineAsm object.
3420 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3421 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3423 /// ConstraintOperands - Information about all of the constraints.
3424 std::vector<AsmOperandInfo> ConstraintOperands;
3426 SDOperand Chain = getRoot();
3429 std::set<unsigned> OutputRegs, InputRegs;
3431 // Do a prepass over the constraints, canonicalizing them, and building up the
3432 // ConstraintOperands list.
3433 std::vector<InlineAsm::ConstraintInfo>
3434 ConstraintInfos = IA->ParseConstraints();
3436 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3437 // constraint. If so, we can't let the register allocator allocate any input
3438 // registers, because it will not know to avoid the earlyclobbered output reg.
3439 bool SawEarlyClobber = false;
3441 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3442 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3443 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3444 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3446 MVT::ValueType OpVT = MVT::Other;
3448 // Compute the value type for each operand.
3449 switch (OpInfo.Type) {
3450 case InlineAsm::isOutput:
3451 if (!OpInfo.isIndirect) {
3452 // The return value of the call is this value. As such, there is no
3453 // corresponding argument.
3454 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3455 OpVT = TLI.getValueType(CS.getType());
3457 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3460 case InlineAsm::isInput:
3461 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3463 case InlineAsm::isClobber:
3468 // If this is an input or an indirect output, process the call argument.
3469 // BasicBlocks are labels, currently appearing only in asm's.
3470 if (OpInfo.CallOperandVal) {
3471 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3472 OpInfo.CallOperand =
3473 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(OpInfo.CallOperandVal)]);
3475 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3476 const Type *OpTy = OpInfo.CallOperandVal->getType();
3477 // If this is an indirect operand, the operand is a pointer to the
3479 if (OpInfo.isIndirect)
3480 OpTy = cast<PointerType>(OpTy)->getElementType();
3482 // If OpTy is not a first-class value, it may be a struct/union that we
3483 // can tile with integers.
3484 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3485 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3493 OpTy = IntegerType::get(BitSize);
3498 OpVT = TLI.getValueType(OpTy, true);
3502 OpInfo.ConstraintVT = OpVT;
3504 // Compute the constraint code and ConstraintType to use.
3505 OpInfo.ComputeConstraintToUse(TLI);
3507 // Keep track of whether we see an earlyclobber.
3508 SawEarlyClobber |= OpInfo.isEarlyClobber;
3510 // If this is a memory input, and if the operand is not indirect, do what we
3511 // need to to provide an address for the memory input.
3512 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3513 !OpInfo.isIndirect) {
3514 assert(OpInfo.Type == InlineAsm::isInput &&
3515 "Can only indirectify direct input operands!");
3517 // Memory operands really want the address of the value. If we don't have
3518 // an indirect input, put it in the constpool if we can, otherwise spill
3519 // it to a stack slot.
3521 // If the operand is a float, integer, or vector constant, spill to a
3522 // constant pool entry to get its address.
3523 Value *OpVal = OpInfo.CallOperandVal;
3524 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3525 isa<ConstantVector>(OpVal)) {
3526 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3527 TLI.getPointerTy());
3529 // Otherwise, create a stack slot and emit a store to it before the
3531 const Type *Ty = OpVal->getType();
3532 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3533 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3534 MachineFunction &MF = DAG.getMachineFunction();
3535 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3536 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3537 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3538 OpInfo.CallOperand = StackSlot;
3541 // There is no longer a Value* corresponding to this operand.
3542 OpInfo.CallOperandVal = 0;
3543 // It is now an indirect operand.
3544 OpInfo.isIndirect = true;
3547 // If this constraint is for a specific register, allocate it before
3549 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3550 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3552 ConstraintInfos.clear();
3555 // Second pass - Loop over all of the operands, assigning virtual or physregs
3556 // to registerclass operands.
3557 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3558 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3560 // C_Register operands have already been allocated, Other/Memory don't need
3562 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3563 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3566 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3567 std::vector<SDOperand> AsmNodeOperands;
3568 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3569 AsmNodeOperands.push_back(
3570 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3573 // Loop over all of the inputs, copying the operand values into the
3574 // appropriate registers and processing the output regs.
3575 RegsForValue RetValRegs;
3577 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3578 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3580 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3581 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3583 switch (OpInfo.Type) {
3584 case InlineAsm::isOutput: {
3585 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3586 OpInfo.ConstraintType != TargetLowering::C_Register) {
3587 // Memory output, or 'other' output (e.g. 'X' constraint).
3588 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3590 // Add information to the INLINEASM node to know about this output.
3591 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3592 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3593 TLI.getPointerTy()));
3594 AsmNodeOperands.push_back(OpInfo.CallOperand);
3598 // Otherwise, this is a register or register class output.
3600 // Copy the output from the appropriate register. Find a register that
3602 if (OpInfo.AssignedRegs.Regs.empty()) {
3603 cerr << "Couldn't allocate output reg for contraint '"
3604 << OpInfo.ConstraintCode << "'!\n";
3608 if (!OpInfo.isIndirect) {
3609 // This is the result value of the call.
3610 assert(RetValRegs.Regs.empty() &&
3611 "Cannot have multiple output constraints yet!");
3612 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3613 RetValRegs = OpInfo.AssignedRegs;
3615 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3616 OpInfo.CallOperandVal));
3619 // Add information to the INLINEASM node to know that this register is
3621 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3625 case InlineAsm::isInput: {
3626 SDOperand InOperandVal = OpInfo.CallOperand;
3628 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3629 // If this is required to match an output register we have already set,
3630 // just use its register.
3631 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3633 // Scan until we find the definition we already emitted of this operand.
3634 // When we find it, create a RegsForValue operand.
3635 unsigned CurOp = 2; // The first operand.
3636 for (; OperandNo; --OperandNo) {
3637 // Advance to the next operand.
3639 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3640 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3641 (NumOps & 7) == 4 /*MEM*/) &&
3642 "Skipped past definitions?");
3643 CurOp += (NumOps>>3)+1;
3647 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3648 if ((NumOps & 7) == 2 /*REGDEF*/) {
3649 // Add NumOps>>3 registers to MatchedRegs.
3650 RegsForValue MatchedRegs;
3651 MatchedRegs.ValueVT = InOperandVal.getValueType();
3652 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3653 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3655 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3656 MatchedRegs.Regs.push_back(Reg);
3659 // Use the produced MatchedRegs object to
3660 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3661 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3664 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3665 assert(0 && "matching constraints for memory operands unimp");
3669 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3670 assert(!OpInfo.isIndirect &&
3671 "Don't know how to handle indirect other inputs yet!");
3673 std::vector<SDOperand> Ops;
3674 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3677 cerr << "Invalid operand for inline asm constraint '"
3678 << OpInfo.ConstraintCode << "'!\n";
3682 // Add information to the INLINEASM node to know about this input.
3683 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3684 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3685 TLI.getPointerTy()));
3686 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3688 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3689 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3690 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3691 "Memory operands expect pointer values");
3693 // Add information to the INLINEASM node to know about this input.
3694 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3695 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3696 TLI.getPointerTy()));
3697 AsmNodeOperands.push_back(InOperandVal);
3701 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3702 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3703 "Unknown constraint type!");
3704 assert(!OpInfo.isIndirect &&
3705 "Don't know how to handle indirect register inputs yet!");
3707 // Copy the input into the appropriate registers.
3708 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3709 "Couldn't allocate input reg!");
3711 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3713 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3717 case InlineAsm::isClobber: {
3718 // Add the clobbered value to the operand list, so that the register
3719 // allocator is aware that the physreg got clobbered.
3720 if (!OpInfo.AssignedRegs.Regs.empty())
3721 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3728 // Finish up input operands.
3729 AsmNodeOperands[0] = Chain;
3730 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3732 Chain = DAG.getNode(ISD::INLINEASM,
3733 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3734 &AsmNodeOperands[0], AsmNodeOperands.size());
3735 Flag = Chain.getValue(1);
3737 // If this asm returns a register value, copy the result from that register
3738 // and set it as the value of the call.
3739 if (!RetValRegs.Regs.empty()) {
3740 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3742 // If the result of the inline asm is a vector, it may have the wrong
3743 // width/num elts. Make sure to convert it to the right type with
3745 if (MVT::isVector(Val.getValueType())) {
3746 const VectorType *VTy = cast<VectorType>(CS.getType());
3747 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3749 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3752 setValue(CS.getInstruction(), Val);
3755 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3757 // Process indirect outputs, first output all of the flagged copies out of
3759 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3760 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3761 Value *Ptr = IndirectStoresToEmit[i].second;
3762 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3763 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3766 // Emit the non-flagged stores from the physregs.
3767 SmallVector<SDOperand, 8> OutChains;
3768 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3769 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3770 getValue(StoresToEmit[i].second),
3771 StoresToEmit[i].second, 0));
3772 if (!OutChains.empty())
3773 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3774 &OutChains[0], OutChains.size());
3779 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3780 SDOperand Src = getValue(I.getOperand(0));
3782 MVT::ValueType IntPtr = TLI.getPointerTy();
3784 if (IntPtr < Src.getValueType())
3785 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3786 else if (IntPtr > Src.getValueType())
3787 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3789 // Scale the source by the type size.
3790 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
3791 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3792 Src, getIntPtrConstant(ElementSize));
3794 TargetLowering::ArgListTy Args;
3795 TargetLowering::ArgListEntry Entry;
3797 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3798 Args.push_back(Entry);
3800 std::pair<SDOperand,SDOperand> Result =
3801 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
3802 DAG.getExternalSymbol("malloc", IntPtr),
3804 setValue(&I, Result.first); // Pointers always fit in registers
3805 DAG.setRoot(Result.second);
3808 void SelectionDAGLowering::visitFree(FreeInst &I) {
3809 TargetLowering::ArgListTy Args;
3810 TargetLowering::ArgListEntry Entry;
3811 Entry.Node = getValue(I.getOperand(0));
3812 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3813 Args.push_back(Entry);
3814 MVT::ValueType IntPtr = TLI.getPointerTy();
3815 std::pair<SDOperand,SDOperand> Result =
3816 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
3817 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3818 DAG.setRoot(Result.second);
3821 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
3822 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3823 // instructions are special in various ways, which require special support to
3824 // insert. The specified MachineInstr is created but not inserted into any
3825 // basic blocks, and the scheduler passes ownership of it to this method.
3826 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
3827 MachineBasicBlock *MBB) {
3828 cerr << "If a target marks an instruction with "
3829 << "'usesCustomDAGSchedInserter', it must implement "
3830 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
3835 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3836 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3837 getValue(I.getOperand(1)),
3838 DAG.getSrcValue(I.getOperand(1))));
3841 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3842 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3843 getValue(I.getOperand(0)),
3844 DAG.getSrcValue(I.getOperand(0)));
3846 DAG.setRoot(V.getValue(1));
3849 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3850 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3851 getValue(I.getOperand(1)),
3852 DAG.getSrcValue(I.getOperand(1))));
3855 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3856 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3857 getValue(I.getOperand(1)),
3858 getValue(I.getOperand(2)),
3859 DAG.getSrcValue(I.getOperand(1)),
3860 DAG.getSrcValue(I.getOperand(2))));
3863 /// TargetLowering::LowerArguments - This is the default LowerArguments
3864 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3865 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3866 /// integrated into SDISel.
3867 std::vector<SDOperand>
3868 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3869 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3870 std::vector<SDOperand> Ops;
3871 Ops.push_back(DAG.getRoot());
3872 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3873 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3875 // Add one result value for each formal argument.
3876 std::vector<MVT::ValueType> RetVals;
3878 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3880 MVT::ValueType VT = getValueType(I->getType());
3881 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3882 unsigned OriginalAlignment =
3883 getTargetData()->getABITypeAlignment(I->getType());
3885 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3886 // that is zero extended!
3887 if (F.paramHasAttr(j, ParamAttr::ZExt))
3888 Flags &= ~(ISD::ParamFlags::SExt);
3889 if (F.paramHasAttr(j, ParamAttr::SExt))
3890 Flags |= ISD::ParamFlags::SExt;
3891 if (F.paramHasAttr(j, ParamAttr::InReg))
3892 Flags |= ISD::ParamFlags::InReg;
3893 if (F.paramHasAttr(j, ParamAttr::StructRet))
3894 Flags |= ISD::ParamFlags::StructReturn;
3895 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
3896 Flags |= ISD::ParamFlags::ByVal;
3897 const PointerType *Ty = cast<PointerType>(I->getType());
3898 const StructType *STy = cast<StructType>(Ty->getElementType());
3899 unsigned StructAlign =
3900 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy));
3901 unsigned StructSize = getTargetData()->getABITypeSize(STy);
3902 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
3903 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs);
3905 if (F.paramHasAttr(j, ParamAttr::Nest))
3906 Flags |= ISD::ParamFlags::Nest;
3907 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
3909 switch (getTypeAction(VT)) {
3910 default: assert(0 && "Unknown type action!");
3912 RetVals.push_back(VT);
3913 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3916 RetVals.push_back(getTypeToTransformTo(VT));
3917 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3920 // If this is an illegal type, it needs to be broken up to fit into
3922 MVT::ValueType RegisterVT = getRegisterType(VT);
3923 unsigned NumRegs = getNumRegisters(VT);
3924 for (unsigned i = 0; i != NumRegs; ++i) {
3925 RetVals.push_back(RegisterVT);
3926 // if it isn't first piece, alignment must be 1
3928 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3929 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3930 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3937 RetVals.push_back(MVT::Other);
3940 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3941 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3942 &Ops[0], Ops.size()).Val;
3943 unsigned NumArgRegs = Result->getNumValues() - 1;
3944 DAG.setRoot(SDOperand(Result, NumArgRegs));
3946 // Set up the return result vector.
3950 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3952 MVT::ValueType VT = getValueType(I->getType());
3954 switch (getTypeAction(VT)) {
3955 default: assert(0 && "Unknown type action!");
3957 Ops.push_back(SDOperand(Result, i++));
3960 SDOperand Op(Result, i++);
3961 if (MVT::isInteger(VT)) {
3962 if (F.paramHasAttr(Idx, ParamAttr::SExt))
3963 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
3964 DAG.getValueType(VT));
3965 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
3966 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
3967 DAG.getValueType(VT));
3968 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
3970 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3971 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
3977 MVT::ValueType PartVT = getRegisterType(VT);
3978 unsigned NumParts = getNumRegisters(VT);
3979 SmallVector<SDOperand, 4> Parts(NumParts);
3980 for (unsigned j = 0; j != NumParts; ++j)
3981 Parts[j] = SDOperand(Result, i++);
3982 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
3987 assert(i == NumArgRegs && "Argument register count mismatch!");
3992 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
3993 /// implementation, which just inserts an ISD::CALL node, which is later custom
3994 /// lowered by the target to something concrete. FIXME: When all targets are
3995 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
3996 std::pair<SDOperand, SDOperand>
3997 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
3998 bool RetTyIsSigned, bool isVarArg,
3999 unsigned CallingConv, bool isTailCall,
4001 ArgListTy &Args, SelectionDAG &DAG) {
4002 SmallVector<SDOperand, 32> Ops;
4003 Ops.push_back(Chain); // Op#0 - Chain
4004 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4005 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4006 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4007 Ops.push_back(Callee);
4009 // Handle all of the outgoing arguments.
4010 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4011 MVT::ValueType VT = getValueType(Args[i].Ty);
4012 SDOperand Op = Args[i].Node;
4013 unsigned Flags = ISD::ParamFlags::NoFlagSet;
4014 unsigned OriginalAlignment =
4015 getTargetData()->getABITypeAlignment(Args[i].Ty);
4018 Flags |= ISD::ParamFlags::SExt;
4020 Flags |= ISD::ParamFlags::ZExt;
4021 if (Args[i].isInReg)
4022 Flags |= ISD::ParamFlags::InReg;
4024 Flags |= ISD::ParamFlags::StructReturn;
4025 if (Args[i].isByVal) {
4026 Flags |= ISD::ParamFlags::ByVal;
4027 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4028 const StructType *STy = cast<StructType>(Ty->getElementType());
4029 unsigned StructAlign =
4030 Log2_32(getTargetData()->getCallFrameTypeAlignment(STy));
4031 unsigned StructSize = getTargetData()->getABITypeSize(STy);
4032 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
4033 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs);
4036 Flags |= ISD::ParamFlags::Nest;
4037 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
4039 switch (getTypeAction(VT)) {
4040 default: assert(0 && "Unknown type action!");
4043 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4046 if (MVT::isInteger(VT)) {
4049 ExtOp = ISD::SIGN_EXTEND;
4050 else if (Args[i].isZExt)
4051 ExtOp = ISD::ZERO_EXTEND;
4053 ExtOp = ISD::ANY_EXTEND;
4054 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
4056 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
4057 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
4060 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4063 MVT::ValueType PartVT = getRegisterType(VT);
4064 unsigned NumParts = getNumRegisters(VT);
4065 SmallVector<SDOperand, 4> Parts(NumParts);
4066 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
4067 for (unsigned i = 0; i != NumParts; ++i) {
4068 // if it isn't first piece, alignment must be 1
4069 unsigned MyFlags = Flags;
4071 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4072 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4074 Ops.push_back(Parts[i]);
4075 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
4082 // Figure out the result value types.
4083 MVT::ValueType VT = getValueType(RetTy);
4084 MVT::ValueType RegisterVT = getRegisterType(VT);
4085 unsigned NumRegs = getNumRegisters(VT);
4086 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4087 for (unsigned i = 0; i != NumRegs; ++i)
4088 RetTys[i] = RegisterVT;
4090 RetTys.push_back(MVT::Other); // Always has a chain.
4092 // Create the CALL node.
4093 SDOperand Res = DAG.getNode(ISD::CALL,
4094 DAG.getVTList(&RetTys[0], NumRegs + 1),
4095 &Ops[0], Ops.size());
4096 Chain = Res.getValue(NumRegs);
4098 // Gather up the call result into a single value.
4099 if (RetTy != Type::VoidTy) {
4100 ISD::NodeType AssertOp = ISD::AssertSext;
4102 AssertOp = ISD::AssertZext;
4103 SmallVector<SDOperand, 4> Results(NumRegs);
4104 for (unsigned i = 0; i != NumRegs; ++i)
4105 Results[i] = Res.getValue(i);
4106 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
4109 return std::make_pair(Res, Chain);
4112 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4113 assert(0 && "LowerOperation not implemented for this target!");
4118 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4119 SelectionDAG &DAG) {
4120 assert(0 && "CustomPromoteOperation not implemented for this target!");
4125 /// getMemsetValue - Vectorized representation of the memset value
4127 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4128 SelectionDAG &DAG) {
4129 MVT::ValueType CurVT = VT;
4130 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4131 uint64_t Val = C->getValue() & 255;
4133 while (CurVT != MVT::i8) {
4134 Val = (Val << Shift) | Val;
4136 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4138 return DAG.getConstant(Val, VT);
4140 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4142 while (CurVT != MVT::i8) {
4144 DAG.getNode(ISD::OR, VT,
4145 DAG.getNode(ISD::SHL, VT, Value,
4146 DAG.getConstant(Shift, MVT::i8)), Value);
4148 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4155 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4156 /// used when a memcpy is turned into a memset when the source is a constant
4158 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4159 SelectionDAG &DAG, TargetLowering &TLI,
4160 std::string &Str, unsigned Offset) {
4162 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4163 if (TLI.isLittleEndian())
4164 Offset = Offset + MSB - 1;
4165 for (unsigned i = 0; i != MSB; ++i) {
4166 Val = (Val << 8) | (unsigned char)Str[Offset];
4167 Offset += TLI.isLittleEndian() ? -1 : 1;
4169 return DAG.getConstant(Val, VT);
4172 /// getMemBasePlusOffset - Returns base and offset node for the
4173 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4174 SelectionDAG &DAG, TargetLowering &TLI) {
4175 MVT::ValueType VT = Base.getValueType();
4176 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4179 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4180 /// to replace the memset / memcpy is below the threshold. It also returns the
4181 /// types of the sequence of memory ops to perform memset / memcpy.
4182 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4183 unsigned Limit, uint64_t Size,
4184 unsigned Align, TargetLowering &TLI) {
4187 if (TLI.allowsUnalignedMemoryAccesses()) {
4190 switch (Align & 7) {
4206 MVT::ValueType LVT = MVT::i64;
4207 while (!TLI.isTypeLegal(LVT))
4208 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4209 assert(MVT::isInteger(LVT));
4214 unsigned NumMemOps = 0;
4216 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4217 while (VTSize > Size) {
4218 VT = (MVT::ValueType)((unsigned)VT - 1);
4221 assert(MVT::isInteger(VT));
4223 if (++NumMemOps > Limit)
4225 MemOps.push_back(VT);
4232 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4233 SDOperand Op1 = getValue(I.getOperand(1));
4234 SDOperand Op2 = getValue(I.getOperand(2));
4235 SDOperand Op3 = getValue(I.getOperand(3));
4236 SDOperand Op4 = getValue(I.getOperand(4));
4237 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4238 if (Align == 0) Align = 1;
4240 // If the source and destination are known to not be aliases, we can
4241 // lower memmove as memcpy.
4242 if (Op == ISD::MEMMOVE) {
4243 uint64_t Size = -1ULL;
4244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4245 Size = C->getValue();
4246 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4247 AliasAnalysis::NoAlias)
4251 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4252 std::vector<MVT::ValueType> MemOps;
4254 // Expand memset / memcpy to a series of load / store ops
4255 // if the size operand falls below a certain threshold.
4256 SmallVector<SDOperand, 8> OutChains;
4258 default: break; // Do nothing for now.
4260 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4261 Size->getValue(), Align, TLI)) {
4262 unsigned NumMemOps = MemOps.size();
4263 unsigned Offset = 0;
4264 for (unsigned i = 0; i < NumMemOps; i++) {
4265 MVT::ValueType VT = MemOps[i];
4266 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4267 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4268 SDOperand Store = DAG.getStore(getRoot(), Value,
4269 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4270 I.getOperand(1), Offset);
4271 OutChains.push_back(Store);
4278 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4279 Size->getValue(), Align, TLI)) {
4280 unsigned NumMemOps = MemOps.size();
4281 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4282 GlobalAddressSDNode *G = NULL;
4284 bool CopyFromStr = false;
4286 if (Op2.getOpcode() == ISD::GlobalAddress)
4287 G = cast<GlobalAddressSDNode>(Op2);
4288 else if (Op2.getOpcode() == ISD::ADD &&
4289 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4290 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4291 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4292 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4295 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4296 if (GV && GV->isConstant()) {
4297 Str = GV->getStringValue(false);
4305 for (unsigned i = 0; i < NumMemOps; i++) {
4306 MVT::ValueType VT = MemOps[i];
4307 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4308 SDOperand Value, Chain, Store;
4311 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4314 DAG.getStore(Chain, Value,
4315 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4316 I.getOperand(1), DstOff);
4318 Value = DAG.getLoad(VT, getRoot(),
4319 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4320 I.getOperand(2), SrcOff, false, Align);
4321 Chain = Value.getValue(1);
4323 DAG.getStore(Chain, Value,
4324 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4325 I.getOperand(1), DstOff, false, Align);
4327 OutChains.push_back(Store);
4336 if (!OutChains.empty()) {
4337 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4338 &OutChains[0], OutChains.size()));
4343 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4347 assert(0 && "Unknown Op");
4349 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4352 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4355 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4361 //===----------------------------------------------------------------------===//
4362 // SelectionDAGISel code
4363 //===----------------------------------------------------------------------===//
4365 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4366 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
4369 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4370 AU.addRequired<AliasAnalysis>();
4371 AU.setPreservesAll();
4376 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4377 // Get alias analysis for load/store combining.
4378 AA = &getAnalysis<AliasAnalysis>();
4380 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4381 RegMap = MF.getSSARegMap();
4382 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4384 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4386 if (ExceptionHandling)
4387 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4388 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4389 // Mark landing pad.
4390 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4392 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4393 SelectBasicBlock(I, MF, FuncInfo);
4395 // Add function live-ins to entry block live-in set.
4396 BasicBlock *EntryBB = &Fn.getEntryBlock();
4397 BB = FuncInfo.MBBMap[EntryBB];
4398 if (!MF.livein_empty())
4399 for (MachineFunction::livein_iterator I = MF.livein_begin(),
4400 E = MF.livein_end(); I != E; ++I)
4401 BB->addLiveIn(I->first);
4404 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4405 "Not all catch info was assigned to a landing pad!");
4411 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4413 SDOperand Op = getValue(V);
4414 assert((Op.getOpcode() != ISD::CopyFromReg ||
4415 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4416 "Copy from a reg to the same reg!");
4418 MVT::ValueType SrcVT = Op.getValueType();
4419 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4420 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4421 SmallVector<SDOperand, 8> Regs(NumRegs);
4422 SmallVector<SDOperand, 8> Chains(NumRegs);
4424 // Copy the value by legal parts into sequential virtual registers.
4425 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4426 for (unsigned i = 0; i != NumRegs; ++i)
4427 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4428 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4431 void SelectionDAGISel::
4432 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4433 std::vector<SDOperand> &UnorderedChains) {
4434 // If this is the entry block, emit arguments.
4435 Function &F = *LLVMBB->getParent();
4436 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4437 SDOperand OldRoot = SDL.DAG.getRoot();
4438 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4441 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4443 if (!AI->use_empty()) {
4444 SDL.setValue(AI, Args[a]);
4446 // If this argument is live outside of the entry block, insert a copy from
4447 // whereever we got it to the vreg that other BB's will reference it as.
4448 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4449 if (VMI != FuncInfo.ValueMap.end()) {
4450 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4451 UnorderedChains.push_back(Copy);
4455 // Finally, if the target has anything special to do, allow it to do so.
4456 // FIXME: this should insert code into the DAG!
4457 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4460 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4461 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4462 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4463 if (isSelector(I)) {
4464 // Apply the catch info to DestBB.
4465 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4467 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4468 FLI.CatchInfoFound.insert(I);
4473 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4474 /// DAG and fixes their tailcall attribute operand.
4475 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4476 TargetLowering& TLI) {
4477 SDNode * Ret = NULL;
4478 SDOperand Terminator = DAG.getRoot();
4481 if (Terminator.getOpcode() == ISD::RET) {
4482 Ret = Terminator.Val;
4485 // Fix tail call attribute of CALL nodes.
4486 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4487 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4488 if (BI->getOpcode() == ISD::CALL) {
4489 SDOperand OpRet(Ret, 0);
4490 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4491 bool isMarkedTailCall =
4492 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4493 // If CALL node has tail call attribute set to true and the call is not
4494 // eligible (no RET or the target rejects) the attribute is fixed to
4495 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4496 // must correctly identify tail call optimizable calls.
4497 if (isMarkedTailCall &&
4499 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4500 SmallVector<SDOperand, 32> Ops;
4502 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4503 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4507 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4509 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4515 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4516 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4517 FunctionLoweringInfo &FuncInfo) {
4518 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo);
4520 std::vector<SDOperand> UnorderedChains;
4522 // Lower any arguments needed in this block if this is the entry block.
4523 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4524 LowerArguments(LLVMBB, SDL, UnorderedChains);
4526 BB = FuncInfo.MBBMap[LLVMBB];
4527 SDL.setCurrentBasicBlock(BB);
4529 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4531 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4532 // Add a label to mark the beginning of the landing pad. Deletion of the
4533 // landing pad can thus be detected via the MachineModuleInfo.
4534 unsigned LabelID = MMI->addLandingPad(BB);
4535 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4536 DAG.getConstant(LabelID, MVT::i32)));
4538 // Mark exception register as live in.
4539 unsigned Reg = TLI.getExceptionAddressRegister();
4540 if (Reg) BB->addLiveIn(Reg);
4542 // Mark exception selector register as live in.
4543 Reg = TLI.getExceptionSelectorRegister();
4544 if (Reg) BB->addLiveIn(Reg);
4546 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4547 // function and list of typeids logically belong to the invoke (or, if you
4548 // like, the basic block containing the invoke), and need to be associated
4549 // with it in the dwarf exception handling tables. Currently however the
4550 // information is provided by an intrinsic (eh.selector) that can be moved
4551 // to unexpected places by the optimizers: if the unwind edge is critical,
4552 // then breaking it can result in the intrinsics being in the successor of
4553 // the landing pad, not the landing pad itself. This results in exceptions
4554 // not being caught because no typeids are associated with the invoke.
4555 // This may not be the only way things can go wrong, but it is the only way
4556 // we try to work around for the moment.
4557 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4559 if (Br && Br->isUnconditional()) { // Critical edge?
4560 BasicBlock::iterator I, E;
4561 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4566 // No catch info found - try to extract some from the successor.
4567 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4571 // Lower all of the non-terminator instructions.
4572 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4576 // Ensure that all instructions which are used outside of their defining
4577 // blocks are available as virtual registers. Invoke is handled elsewhere.
4578 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4579 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4580 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4581 if (VMI != FuncInfo.ValueMap.end())
4582 UnorderedChains.push_back(
4583 SDL.CopyValueToVirtualRegister(I, VMI->second));
4586 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4587 // ensure constants are generated when needed. Remember the virtual registers
4588 // that need to be added to the Machine PHI nodes as input. We cannot just
4589 // directly add them, because expansion might result in multiple MBB's for one
4590 // BB. As such, the start of the BB might correspond to a different MBB than
4593 TerminatorInst *TI = LLVMBB->getTerminator();
4595 // Emit constants only once even if used by multiple PHI nodes.
4596 std::map<Constant*, unsigned> ConstantsOut;
4598 // Vector bool would be better, but vector<bool> is really slow.
4599 std::vector<unsigned char> SuccsHandled;
4600 if (TI->getNumSuccessors())
4601 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4603 // Check successor nodes' PHI nodes that expect a constant to be available
4605 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4606 BasicBlock *SuccBB = TI->getSuccessor(succ);
4607 if (!isa<PHINode>(SuccBB->begin())) continue;
4608 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4610 // If this terminator has multiple identical successors (common for
4611 // switches), only handle each succ once.
4612 unsigned SuccMBBNo = SuccMBB->getNumber();
4613 if (SuccsHandled[SuccMBBNo]) continue;
4614 SuccsHandled[SuccMBBNo] = true;
4616 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4619 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4620 // nodes and Machine PHI nodes, but the incoming operands have not been
4622 for (BasicBlock::iterator I = SuccBB->begin();
4623 (PN = dyn_cast<PHINode>(I)); ++I) {
4624 // Ignore dead phi's.
4625 if (PN->use_empty()) continue;
4628 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4630 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4631 unsigned &RegOut = ConstantsOut[C];
4633 RegOut = FuncInfo.CreateRegForValue(C);
4634 UnorderedChains.push_back(
4635 SDL.CopyValueToVirtualRegister(C, RegOut));
4639 Reg = FuncInfo.ValueMap[PHIOp];
4641 assert(isa<AllocaInst>(PHIOp) &&
4642 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4643 "Didn't codegen value into a register!??");
4644 Reg = FuncInfo.CreateRegForValue(PHIOp);
4645 UnorderedChains.push_back(
4646 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4650 // Remember that this register needs to added to the machine PHI node as
4651 // the input for this MBB.
4652 MVT::ValueType VT = TLI.getValueType(PN->getType());
4653 unsigned NumRegisters = TLI.getNumRegisters(VT);
4654 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4655 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4658 ConstantsOut.clear();
4660 // Turn all of the unordered chains into one factored node.
4661 if (!UnorderedChains.empty()) {
4662 SDOperand Root = SDL.getRoot();
4663 if (Root.getOpcode() != ISD::EntryToken) {
4664 unsigned i = 0, e = UnorderedChains.size();
4665 for (; i != e; ++i) {
4666 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4667 if (UnorderedChains[i].Val->getOperand(0) == Root)
4668 break; // Don't add the root if we already indirectly depend on it.
4672 UnorderedChains.push_back(Root);
4674 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4675 &UnorderedChains[0], UnorderedChains.size()));
4678 // Lower the terminator after the copies are emitted.
4679 SDL.visit(*LLVMBB->getTerminator());
4681 // Copy over any CaseBlock records that may now exist due to SwitchInst
4682 // lowering, as well as any jump table information.
4683 SwitchCases.clear();
4684 SwitchCases = SDL.SwitchCases;
4686 JTCases = SDL.JTCases;
4687 BitTestCases.clear();
4688 BitTestCases = SDL.BitTestCases;
4690 // Make sure the root of the DAG is up-to-date.
4691 DAG.setRoot(SDL.getRoot());
4693 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4694 // with correct tailcall attribute so that the target can rely on the tailcall
4695 // attribute indicating whether the call is really eligible for tail call
4697 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4700 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4701 DOUT << "Lowered selection DAG:\n";
4704 // Run the DAG combiner in pre-legalize mode.
4705 DAG.Combine(false, *AA);
4707 DOUT << "Optimized lowered selection DAG:\n";
4710 // Second step, hack on the DAG until it only uses operations and types that
4711 // the target supports.
4712 #if 0 // Enable this some day.
4713 DAG.LegalizeTypes();
4714 // Someday even later, enable a dag combine pass here.
4718 DOUT << "Legalized selection DAG:\n";
4721 // Run the DAG combiner in post-legalize mode.
4722 DAG.Combine(true, *AA);
4724 DOUT << "Optimized legalized selection DAG:\n";
4727 if (ViewISelDAGs) DAG.viewGraph();
4729 // Third, instruction select all of the operations to machine code, adding the
4730 // code to the MachineBasicBlock.
4731 InstructionSelectBasicBlock(DAG);
4733 DOUT << "Selected machine code:\n";
4737 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4738 FunctionLoweringInfo &FuncInfo) {
4739 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4741 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4744 // First step, lower LLVM code to some DAG. This DAG may use operations and
4745 // types that are not supported by the target.
4746 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4748 // Second step, emit the lowered DAG as machine code.
4749 CodeGenAndEmitDAG(DAG);
4752 DOUT << "Total amount of phi nodes to update: "
4753 << PHINodesToUpdate.size() << "\n";
4754 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4755 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4756 << ", " << PHINodesToUpdate[i].second << ")\n";);
4758 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4759 // PHI nodes in successors.
4760 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4761 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4762 MachineInstr *PHI = PHINodesToUpdate[i].first;
4763 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4764 "This is not a machine PHI node that we are updating!");
4765 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4767 PHI->addOperand(MachineOperand::CreateMBB(BB));
4772 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4773 // Lower header first, if it wasn't already lowered
4774 if (!BitTestCases[i].Emitted) {
4775 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4777 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo);
4778 // Set the current basic block to the mbb we wish to insert the code into
4779 BB = BitTestCases[i].Parent;
4780 HSDL.setCurrentBasicBlock(BB);
4782 HSDL.visitBitTestHeader(BitTestCases[i]);
4783 HSDAG.setRoot(HSDL.getRoot());
4784 CodeGenAndEmitDAG(HSDAG);
4787 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4788 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4790 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo);
4791 // Set the current basic block to the mbb we wish to insert the code into
4792 BB = BitTestCases[i].Cases[j].ThisBB;
4793 BSDL.setCurrentBasicBlock(BB);
4796 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4797 BitTestCases[i].Reg,
4798 BitTestCases[i].Cases[j]);
4800 BSDL.visitBitTestCase(BitTestCases[i].Default,
4801 BitTestCases[i].Reg,
4802 BitTestCases[i].Cases[j]);
4805 BSDAG.setRoot(BSDL.getRoot());
4806 CodeGenAndEmitDAG(BSDAG);
4810 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4811 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4812 MachineBasicBlock *PHIBB = PHI->getParent();
4813 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4814 "This is not a machine PHI node that we are updating!");
4815 // This is "default" BB. We have two jumps to it. From "header" BB and
4816 // from last "case" BB.
4817 if (PHIBB == BitTestCases[i].Default) {
4818 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4820 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
4821 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4823 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
4826 // One of "cases" BB.
4827 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4828 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4829 if (cBB->succ_end() !=
4830 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4831 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4833 PHI->addOperand(MachineOperand::CreateMBB(cBB));
4839 // If the JumpTable record is filled in, then we need to emit a jump table.
4840 // Updating the PHI nodes is tricky in this case, since we need to determine
4841 // whether the PHI is a successor of the range check MBB or the jump table MBB
4842 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4843 // Lower header first, if it wasn't already lowered
4844 if (!JTCases[i].first.Emitted) {
4845 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4847 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo);
4848 // Set the current basic block to the mbb we wish to insert the code into
4849 BB = JTCases[i].first.HeaderBB;
4850 HSDL.setCurrentBasicBlock(BB);
4852 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4853 HSDAG.setRoot(HSDL.getRoot());
4854 CodeGenAndEmitDAG(HSDAG);
4857 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4859 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo);
4860 // Set the current basic block to the mbb we wish to insert the code into
4861 BB = JTCases[i].second.MBB;
4862 JSDL.setCurrentBasicBlock(BB);
4864 JSDL.visitJumpTable(JTCases[i].second);
4865 JSDAG.setRoot(JSDL.getRoot());
4866 CodeGenAndEmitDAG(JSDAG);
4869 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4870 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4871 MachineBasicBlock *PHIBB = PHI->getParent();
4872 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4873 "This is not a machine PHI node that we are updating!");
4874 // "default" BB. We can go there only from header BB.
4875 if (PHIBB == JTCases[i].second.Default) {
4876 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4878 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
4880 // JT BB. Just iterate over successors here
4881 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4882 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4884 PHI->addOperand(MachineOperand::CreateMBB(BB));
4889 // If the switch block involved a branch to one of the actual successors, we
4890 // need to update PHI nodes in that block.
4891 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4892 MachineInstr *PHI = PHINodesToUpdate[i].first;
4893 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4894 "This is not a machine PHI node that we are updating!");
4895 if (BB->isSuccessor(PHI->getParent())) {
4896 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4898 PHI->addOperand(MachineOperand::CreateMBB(BB));
4902 // If we generated any switch lowering information, build and codegen any
4903 // additional DAGs necessary.
4904 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4905 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4907 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo);
4909 // Set the current basic block to the mbb we wish to insert the code into
4910 BB = SwitchCases[i].ThisBB;
4911 SDL.setCurrentBasicBlock(BB);
4914 SDL.visitSwitchCase(SwitchCases[i]);
4915 SDAG.setRoot(SDL.getRoot());
4916 CodeGenAndEmitDAG(SDAG);
4918 // Handle any PHI nodes in successors of this chunk, as if we were coming
4919 // from the original BB before switch expansion. Note that PHI nodes can
4920 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4921 // handle them the right number of times.
4922 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4923 for (MachineBasicBlock::iterator Phi = BB->begin();
4924 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4925 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4926 for (unsigned pn = 0; ; ++pn) {
4927 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4928 if (PHINodesToUpdate[pn].first == Phi) {
4929 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
4931 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
4937 // Don't process RHS if same block as LHS.
4938 if (BB == SwitchCases[i].FalseBB)
4939 SwitchCases[i].FalseBB = 0;
4941 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4942 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4943 SwitchCases[i].FalseBB = 0;
4945 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4950 //===----------------------------------------------------------------------===//
4951 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4952 /// target node in the graph.
4953 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4954 if (ViewSchedDAGs) DAG.viewGraph();
4956 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4960 RegisterScheduler::setDefault(Ctor);
4963 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4966 if (ViewSUnitDAGs) SL->viewGraph();
4972 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4973 return new HazardRecognizer();
4976 //===----------------------------------------------------------------------===//
4977 // Helper functions used by the generated instruction selector.
4978 //===----------------------------------------------------------------------===//
4979 // Calls to these methods are generated by tblgen.
4981 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4982 /// the dag combiner simplified the 255, we still want to match. RHS is the
4983 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4984 /// specified in the .td file (e.g. 255).
4985 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4986 int64_t DesiredMaskS) const {
4987 uint64_t ActualMask = RHS->getValue();
4988 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4990 // If the actual mask exactly matches, success!
4991 if (ActualMask == DesiredMask)
4994 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4995 if (ActualMask & ~DesiredMask)
4998 // Otherwise, the DAG Combiner may have proven that the value coming in is
4999 // either already zero or is not demanded. Check for known zero input bits.
5000 uint64_t NeededMask = DesiredMask & ~ActualMask;
5001 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5004 // TODO: check to see if missing bits are just not demanded.
5006 // Otherwise, this pattern doesn't match.
5010 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5011 /// the dag combiner simplified the 255, we still want to match. RHS is the
5012 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5013 /// specified in the .td file (e.g. 255).
5014 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5015 int64_t DesiredMaskS) const {
5016 uint64_t ActualMask = RHS->getValue();
5017 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5019 // If the actual mask exactly matches, success!
5020 if (ActualMask == DesiredMask)
5023 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5024 if (ActualMask & ~DesiredMask)
5027 // Otherwise, the DAG Combiner may have proven that the value coming in is
5028 // either already zero or is not demanded. Check for known zero input bits.
5029 uint64_t NeededMask = DesiredMask & ~ActualMask;
5031 uint64_t KnownZero, KnownOne;
5032 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5034 // If all the missing bits in the or are already known to be set, match!
5035 if ((NeededMask & KnownOne) == NeededMask)
5038 // TODO: check to see if missing bits are just not demanded.
5040 // Otherwise, this pattern doesn't match.
5045 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5046 /// by tblgen. Others should not call it.
5047 void SelectionDAGISel::
5048 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5049 std::vector<SDOperand> InOps;
5050 std::swap(InOps, Ops);
5052 Ops.push_back(InOps[0]); // input chain.
5053 Ops.push_back(InOps[1]); // input asm string.
5055 unsigned i = 2, e = InOps.size();
5056 if (InOps[e-1].getValueType() == MVT::Flag)
5057 --e; // Don't process a flag operand if it is here.
5060 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5061 if ((Flags & 7) != 4 /*MEM*/) {
5062 // Just skip over this operand, copying the operands verbatim.
5063 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5064 i += (Flags >> 3) + 1;
5066 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5067 // Otherwise, this is a memory operand. Ask the target to select it.
5068 std::vector<SDOperand> SelOps;
5069 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5070 cerr << "Could not match memory address. Inline asm failure!\n";
5074 // Add this to the output node.
5075 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5076 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5078 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5083 // Add the flag input back if present.
5084 if (e != InOps.size())
5085 Ops.push_back(InOps.back());
5088 char SelectionDAGISel::ID = 0;