1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "SelectionDAGBuild.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleDAGSDNodes.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetData.h"
42 #include "llvm/Target/TargetFrameInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/Timer.h"
55 EnableValueProp("enable-value-prop", cl::Hidden);
57 DisableLegalizeTypes("disable-legalize-types", cl::Hidden);
60 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
61 cl::desc("Enable verbose messages in the \"fast\" "
62 "instruction selector"));
64 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
65 cl::desc("Enable abort calls when \"fast\" instruction fails"));
67 static const bool EnableFastISelVerbose = false,
68 EnableFastISelAbort = false;
71 SchedLiveInCopies("schedule-livein-copies",
72 cl::desc("Schedule copies of livein registers"),
77 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
78 cl::desc("Pop up a window to show dags before the first "
81 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
82 cl::desc("Pop up a window to show dags before legalize types"));
84 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
85 cl::desc("Pop up a window to show dags before legalize"));
87 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
88 cl::desc("Pop up a window to show dags before the second "
91 ViewISelDAGs("view-isel-dags", cl::Hidden,
92 cl::desc("Pop up a window to show isel dags as they are selected"));
94 ViewSchedDAGs("view-sched-dags", cl::Hidden,
95 cl::desc("Pop up a window to show sched dags as they are processed"));
97 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
98 cl::desc("Pop up a window to show SUnit dags after they are processed"));
100 static const bool ViewDAGCombine1 = false,
101 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
102 ViewDAGCombine2 = false,
103 ViewISelDAGs = false, ViewSchedDAGs = false,
104 ViewSUnitDAGs = false;
107 //===---------------------------------------------------------------------===//
109 /// RegisterScheduler class - Track the registration of instruction schedulers.
111 //===---------------------------------------------------------------------===//
112 MachinePassRegistry RegisterScheduler::Registry;
114 //===---------------------------------------------------------------------===//
116 /// ISHeuristic command line option for instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
120 RegisterPassParser<RegisterScheduler> >
121 ISHeuristic("pre-RA-sched",
122 cl::init(&createDefaultScheduler),
123 cl::desc("Instruction schedulers available (before register"
126 static RegisterScheduler
127 defaultListDAGScheduler("default", "Best scheduler for the target",
128 createDefaultScheduler);
131 //===--------------------------------------------------------------------===//
132 /// createDefaultScheduler - This creates an instruction scheduler appropriate
134 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
136 const TargetMachine *TM,
137 MachineBasicBlock *BB,
139 TargetLowering &TLI = IS->getTargetLowering();
142 return createFastDAGScheduler(IS, DAG, TM, BB, Fast);
143 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
144 return createTDListDAGScheduler(IS, DAG, TM, BB, Fast);
145 assert(TLI.getSchedulingPreference() ==
146 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
147 return createBURRListDAGScheduler(IS, DAG, TM, BB, Fast);
151 // EmitInstrWithCustomInserter - This method should be implemented by targets
152 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
153 // instructions are special in various ways, which require special support to
154 // insert. The specified MachineInstr is created but not inserted into any
155 // basic blocks, and the scheduler passes ownership of it to this method.
156 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
157 MachineBasicBlock *MBB) {
158 cerr << "If a target marks an instruction with "
159 << "'usesCustomDAGSchedInserter', it must implement "
160 << "TargetLowering::EmitInstrWithCustomInserter!\n";
165 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
166 /// physical register has only a single copy use, then coalesced the copy
168 static void EmitLiveInCopy(MachineBasicBlock *MBB,
169 MachineBasicBlock::iterator &InsertPos,
170 unsigned VirtReg, unsigned PhysReg,
171 const TargetRegisterClass *RC,
172 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
173 const MachineRegisterInfo &MRI,
174 const TargetRegisterInfo &TRI,
175 const TargetInstrInfo &TII) {
176 unsigned NumUses = 0;
177 MachineInstr *UseMI = NULL;
178 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
179 UE = MRI.use_end(); UI != UE; ++UI) {
185 // If the number of uses is not one, or the use is not a move instruction,
186 // don't coalesce. Also, only coalesce away a virtual register to virtual
188 bool Coalesced = false;
189 unsigned SrcReg, DstReg;
191 TII.isMoveInstr(*UseMI, SrcReg, DstReg) &&
192 TargetRegisterInfo::isVirtualRegister(DstReg)) {
197 // Now find an ideal location to insert the copy.
198 MachineBasicBlock::iterator Pos = InsertPos;
199 while (Pos != MBB->begin()) {
200 MachineInstr *PrevMI = prior(Pos);
201 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
202 // copyRegToReg might emit multiple instructions to do a copy.
203 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
204 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
205 // This is what the BB looks like right now:
210 // We want to insert "r1025 = mov r1". Inserting this copy below the
211 // move to r1024 makes it impossible for that move to be coalesced.
218 break; // Woot! Found a good location.
222 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
223 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
225 if (&*InsertPos == UseMI) ++InsertPos;
230 /// EmitLiveInCopies - If this is the first basic block in the function,
231 /// and if it has live ins that need to be copied into vregs, emit the
232 /// copies into the block.
233 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
234 const MachineRegisterInfo &MRI,
235 const TargetRegisterInfo &TRI,
236 const TargetInstrInfo &TII) {
237 if (SchedLiveInCopies) {
238 // Emit the copies at a heuristically-determined location in the block.
239 DenseMap<MachineInstr*, unsigned> CopyRegMap;
240 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
241 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
242 E = MRI.livein_end(); LI != E; ++LI)
244 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
245 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
246 RC, CopyRegMap, MRI, TRI, TII);
249 // Emit the copies into the top of the block.
250 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
251 E = MRI.livein_end(); LI != E; ++LI)
253 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
254 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
255 LI->second, LI->first, RC, RC);
260 //===----------------------------------------------------------------------===//
261 // SelectionDAGISel code
262 //===----------------------------------------------------------------------===//
264 SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) :
265 FunctionPass(&ID), TLI(tli),
266 FuncInfo(new FunctionLoweringInfo(TLI)),
267 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
268 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
274 SelectionDAGISel::~SelectionDAGISel() {
280 unsigned SelectionDAGISel::MakeReg(MVT VT) {
281 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
284 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
285 AU.addRequired<AliasAnalysis>();
286 AU.addRequired<GCModuleInfo>();
287 AU.setPreservesAll();
290 bool SelectionDAGISel::runOnFunction(Function &Fn) {
291 // Do some sanity-checking on the command-line options.
292 assert((!EnableFastISelVerbose || EnableFastISel) &&
293 "-fast-isel-verbose requires -fast-isel");
294 assert((!EnableFastISelAbort || EnableFastISel) &&
295 "-fast-isel-abort requires -fast-isel");
297 // Get alias analysis for load/store combining.
298 AA = &getAnalysis<AliasAnalysis>();
300 TargetMachine &TM = TLI.getTargetMachine();
301 MachineFunction &MF = MachineFunction::construct(&Fn, TM);
302 const MachineRegisterInfo &MRI = MF.getRegInfo();
303 const TargetInstrInfo &TII = *TM.getInstrInfo();
304 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
306 if (MF.getFunction()->hasGC())
307 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
310 RegInfo = &MF.getRegInfo();
311 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
313 FuncInfo->set(Fn, MF, EnableFastISel);
314 MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>();
315 CurDAG->init(MF, MMI);
318 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
319 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
321 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
323 SelectAllBasicBlocks(Fn, MF, MMI, TII);
325 // If the first basic block in the function has live ins that need to be
326 // copied into vregs, emit the copies into the top of the block before
327 // emitting the code for the block.
328 EmitLiveInCopies(MF.begin(), MRI, TRI, TII);
330 // Add function live-ins to entry block live-in set.
331 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
332 E = RegInfo->livein_end(); I != E; ++I)
333 MF.begin()->addLiveIn(I->first);
336 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
337 "Not all catch info was assigned to a landing pad!");
345 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
346 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
347 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
348 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) {
349 // Apply the catch info to DestBB.
350 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]);
352 if (!FLI.MBBMap[SrcBB]->isLandingPad())
353 FLI.CatchInfoFound.insert(EHSel);
358 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
359 /// whether object offset >= 0.
361 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
362 if (!isa<FrameIndexSDNode>(Op)) return false;
364 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
365 int FrameIdx = FrameIdxNode->getIndex();
366 return MFI->isFixedObjectIndex(FrameIdx) &&
367 MFI->getObjectOffset(FrameIdx) >= 0;
370 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
371 /// possibly be overwritten when lowering the outgoing arguments in a tail
372 /// call. Currently the implementation of this call is very conservative and
373 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
374 /// virtual registers would be overwritten by direct lowering.
375 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
376 MachineFrameInfo * MFI) {
377 RegisterSDNode * OpReg = NULL;
378 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
379 (Op.getOpcode()== ISD::CopyFromReg &&
380 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
381 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
382 (Op.getOpcode() == ISD::LOAD &&
383 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
384 (Op.getOpcode() == ISD::MERGE_VALUES &&
385 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
386 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
392 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
393 /// DAG and fixes their tailcall attribute operand.
394 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
395 TargetLowering& TLI) {
397 SDValue Terminator = DAG.getRoot();
400 if (Terminator.getOpcode() == ISD::RET) {
401 Ret = Terminator.getNode();
404 // Fix tail call attribute of CALL nodes.
405 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
406 BI = DAG.allnodes_end(); BI != BE; ) {
408 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) {
409 SDValue OpRet(Ret, 0);
410 SDValue OpCall(BI, 0);
411 bool isMarkedTailCall = TheCall->isTailCall();
412 // If CALL node has tail call attribute set to true and the call is not
413 // eligible (no RET or the target rejects) the attribute is fixed to
414 // false. The TargetLowering::IsEligibleForTailCallOptimization function
415 // must correctly identify tail call optimizable calls.
416 if (!isMarkedTailCall) continue;
418 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) {
419 // Not eligible. Mark CALL node as non tail call. Note that we
420 // can modify the call node in place since calls are not CSE'd.
421 TheCall->setNotTailCall();
423 // Look for tail call clobbered arguments. Emit a series of
424 // copyto/copyfrom virtual register nodes to protect them.
425 SmallVector<SDValue, 32> Ops;
426 SDValue Chain = TheCall->getChain(), InFlag;
427 Ops.push_back(Chain);
428 Ops.push_back(TheCall->getCallee());
429 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
430 SDValue Arg = TheCall->getArg(i);
431 bool isByVal = TheCall->getArgFlags(i).isByVal();
432 MachineFunction &MF = DAG.getMachineFunction();
433 MachineFrameInfo *MFI = MF.getFrameInfo();
435 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
436 MVT VT = Arg.getValueType();
437 unsigned VReg = MF.getRegInfo().
438 createVirtualRegister(TLI.getRegClassFor(VT));
439 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
440 InFlag = Chain.getValue(1);
441 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
442 Chain = Arg.getValue(1);
443 InFlag = Arg.getValue(2);
446 Ops.push_back(TheCall->getArgFlagsVal(i));
448 // Link in chain of CopyTo/CopyFromReg.
450 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
456 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
457 BasicBlock::iterator Begin,
458 BasicBlock::iterator End) {
459 SDL->setCurrentBasicBlock(BB);
461 // Lower all of the non-terminator instructions.
462 for (BasicBlock::iterator I = Begin; I != End; ++I)
463 if (!isa<TerminatorInst>(I))
466 // Ensure that all instructions which are used outside of their defining
467 // blocks are available as virtual registers. Invoke is handled elsewhere.
468 for (BasicBlock::iterator I = Begin; I != End; ++I)
469 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
470 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I);
471 if (VMI != FuncInfo->ValueMap.end())
472 SDL->CopyValueToVirtualRegister(I, VMI->second);
475 // Handle PHI nodes in successor blocks.
476 if (End == LLVMBB->end()) {
477 HandlePHINodesInSuccessorBlocks(LLVMBB);
479 // Lower the terminator after the copies are emitted.
480 SDL->visit(*LLVMBB->getTerminator());
483 // Make sure the root of the DAG is up-to-date.
484 CurDAG->setRoot(SDL->getControlRoot());
486 // Check whether calls in this block are real tail calls. Fix up CALL nodes
487 // with correct tailcall attribute so that the target can rely on the tailcall
488 // attribute indicating whether the call is really eligible for tail call
490 if (PerformTailCallOpt)
491 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
493 // Final step, emit the lowered DAG as machine code.
498 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
499 SmallPtrSet<SDNode*, 128> VisitedNodes;
500 SmallVector<SDNode*, 128> Worklist;
502 Worklist.push_back(CurDAG->getRoot().getNode());
508 while (!Worklist.empty()) {
509 SDNode *N = Worklist.back();
512 // If we've already seen this node, ignore it.
513 if (!VisitedNodes.insert(N))
516 // Otherwise, add all chain operands to the worklist.
517 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
518 if (N->getOperand(i).getValueType() == MVT::Other)
519 Worklist.push_back(N->getOperand(i).getNode());
521 // If this is a CopyToReg with a vreg dest, process it.
522 if (N->getOpcode() != ISD::CopyToReg)
525 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
526 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
529 // Ignore non-scalar or non-integer values.
530 SDValue Src = N->getOperand(2);
531 MVT SrcVT = Src.getValueType();
532 if (!SrcVT.isInteger() || SrcVT.isVector())
535 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
536 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
537 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
539 // Only install this information if it tells us something.
540 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
541 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
542 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
543 if (DestReg >= FLI.LiveOutRegInfo.size())
544 FLI.LiveOutRegInfo.resize(DestReg+1);
545 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
546 LOI.NumSignBits = NumSignBits;
547 LOI.KnownOne = NumSignBits;
548 LOI.KnownZero = NumSignBits;
553 void SelectionDAGISel::CodeGenAndEmitDAG() {
554 std::string GroupName;
555 if (TimePassesIsEnabled)
556 GroupName = "Instruction Selection and Scheduling";
557 std::string BlockName;
558 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
559 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
560 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' +
561 BB->getBasicBlock()->getName();
563 DOUT << "Initial selection DAG:\n";
564 DEBUG(CurDAG->dump());
566 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
568 // Run the DAG combiner in pre-legalize mode.
569 if (TimePassesIsEnabled) {
570 NamedRegionTimer T("DAG Combining 1", GroupName);
571 CurDAG->Combine(false, *AA, Fast);
573 CurDAG->Combine(false, *AA, Fast);
576 DOUT << "Optimized lowered selection DAG:\n";
577 DEBUG(CurDAG->dump());
579 // Second step, hack on the DAG until it only uses operations and types that
580 // the target supports.
581 if (!DisableLegalizeTypes) {
582 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
585 if (TimePassesIsEnabled) {
586 NamedRegionTimer T("Type Legalization", GroupName);
587 CurDAG->LegalizeTypes();
589 CurDAG->LegalizeTypes();
592 DOUT << "Type-legalized selection DAG:\n";
593 DEBUG(CurDAG->dump());
595 // TODO: enable a dag combine pass here.
598 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
600 if (TimePassesIsEnabled) {
601 NamedRegionTimer T("DAG Legalization", GroupName);
607 DOUT << "Legalized selection DAG:\n";
608 DEBUG(CurDAG->dump());
610 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
612 // Run the DAG combiner in post-legalize mode.
613 if (TimePassesIsEnabled) {
614 NamedRegionTimer T("DAG Combining 2", GroupName);
615 CurDAG->Combine(true, *AA, Fast);
617 CurDAG->Combine(true, *AA, Fast);
620 DOUT << "Optimized legalized selection DAG:\n";
621 DEBUG(CurDAG->dump());
623 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
625 if (!Fast && EnableValueProp)
626 ComputeLiveOutVRegInfo();
628 // Third, instruction select all of the operations to machine code, adding the
629 // code to the MachineBasicBlock.
630 if (TimePassesIsEnabled) {
631 NamedRegionTimer T("Instruction Selection", GroupName);
637 DOUT << "Selected selection DAG:\n";
638 DEBUG(CurDAG->dump());
640 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
642 // Schedule machine code.
643 ScheduleDAG *Scheduler;
644 if (TimePassesIsEnabled) {
645 NamedRegionTimer T("Instruction Scheduling", GroupName);
646 Scheduler = Schedule();
648 Scheduler = Schedule();
651 if (ViewSUnitDAGs) Scheduler->viewGraph();
653 // Emit machine code to BB. This can change 'BB' to the last block being
655 if (TimePassesIsEnabled) {
656 NamedRegionTimer T("Instruction Creation", GroupName);
657 BB = Scheduler->EmitSchedule();
659 BB = Scheduler->EmitSchedule();
662 // Free the scheduler state.
663 if (TimePassesIsEnabled) {
664 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
670 DOUT << "Selected machine code:\n";
674 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
675 MachineModuleInfo *MMI,
676 const TargetInstrInfo &TII) {
677 // Initialize the Fast-ISel state, if needed.
678 FastISel *FastIS = 0;
680 FastIS = TLI.createFastISel(*FuncInfo->MF, MMI,
683 FuncInfo->StaticAllocaMap
685 , FuncInfo->CatchInfoLost
689 // Iterate over all basic blocks in the function.
690 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
691 BasicBlock *LLVMBB = &*I;
692 BB = FuncInfo->MBBMap[LLVMBB];
694 BasicBlock::iterator const Begin = LLVMBB->begin();
695 BasicBlock::iterator const End = LLVMBB->end();
696 BasicBlock::iterator BI = Begin;
698 // Lower any arguments needed in this block if this is the entry block.
699 bool SuppressFastISel = false;
700 if (LLVMBB == &Fn.getEntryBlock()) {
701 LowerArguments(LLVMBB);
703 // If any of the arguments has the byval attribute, forgo
704 // fast-isel in the entry block.
707 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
709 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
710 if (EnableFastISelVerbose || EnableFastISelAbort)
711 cerr << "FastISel skips entry block due to byval argument\n";
712 SuppressFastISel = true;
718 if (MMI && BB->isLandingPad()) {
719 // Add a label to mark the beginning of the landing pad. Deletion of the
720 // landing pad can thus be detected via the MachineModuleInfo.
721 unsigned LabelID = MMI->addLandingPad(BB);
723 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL);
724 BuildMI(BB, II).addImm(LabelID);
726 // Mark exception register as live in.
727 unsigned Reg = TLI.getExceptionAddressRegister();
728 if (Reg) BB->addLiveIn(Reg);
730 // Mark exception selector register as live in.
731 Reg = TLI.getExceptionSelectorRegister();
732 if (Reg) BB->addLiveIn(Reg);
734 // FIXME: Hack around an exception handling flaw (PR1508): the personality
735 // function and list of typeids logically belong to the invoke (or, if you
736 // like, the basic block containing the invoke), and need to be associated
737 // with it in the dwarf exception handling tables. Currently however the
738 // information is provided by an intrinsic (eh.selector) that can be moved
739 // to unexpected places by the optimizers: if the unwind edge is critical,
740 // then breaking it can result in the intrinsics being in the successor of
741 // the landing pad, not the landing pad itself. This results in exceptions
742 // not being caught because no typeids are associated with the invoke.
743 // This may not be the only way things can go wrong, but it is the only way
744 // we try to work around for the moment.
745 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
747 if (Br && Br->isUnconditional()) { // Critical edge?
748 BasicBlock::iterator I, E;
749 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
750 if (isa<EHSelectorInst>(I))
754 // No catch info found - try to extract some from the successor.
755 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
759 // Before doing SelectionDAG ISel, see if FastISel has been requested.
760 if (FastIS && !SuppressFastISel) {
761 // Emit code for any incoming arguments. This must happen before
762 // beginning FastISel on the entry block.
763 if (LLVMBB == &Fn.getEntryBlock()) {
764 CurDAG->setRoot(SDL->getControlRoot());
768 FastIS->startNewBlock(BB);
769 // Do FastISel on as many instructions as possible.
770 for (; BI != End; ++BI) {
771 // Just before the terminator instruction, insert instructions to
772 // feed PHI nodes in successor blocks.
773 if (isa<TerminatorInst>(BI))
774 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
775 if (EnableFastISelVerbose || EnableFastISelAbort) {
776 cerr << "FastISel miss: ";
779 if (EnableFastISelAbort)
780 assert(0 && "FastISel didn't handle a PHI in a successor");
784 // First try normal tablegen-generated "fast" selection.
785 if (FastIS->SelectInstruction(BI))
788 // Next, try calling the target to attempt to handle the instruction.
789 if (FastIS->TargetSelectInstruction(BI))
792 // Then handle certain instructions as single-LLVM-Instruction blocks.
793 if (isa<CallInst>(BI)) {
794 if (EnableFastISelVerbose || EnableFastISelAbort) {
795 cerr << "FastISel missed call: ";
799 if (BI->getType() != Type::VoidTy) {
800 unsigned &R = FuncInfo->ValueMap[BI];
802 R = FuncInfo->CreateRegForValue(BI);
805 SelectBasicBlock(LLVMBB, BI, next(BI));
806 // If the instruction was codegen'd with multiple blocks,
807 // inform the FastISel object where to resume inserting.
808 FastIS->setCurrentBlock(BB);
812 // Otherwise, give up on FastISel for the rest of the block.
813 // For now, be a little lenient about non-branch terminators.
814 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
815 if (EnableFastISelVerbose || EnableFastISelAbort) {
816 cerr << "FastISel miss: ";
819 if (EnableFastISelAbort)
820 // The "fast" selector couldn't handle something and bailed.
821 // For the purpose of debugging, just abort.
822 assert(0 && "FastISel didn't select the entire block");
828 // Run SelectionDAG instruction selection on the remainder of the block
829 // not handled by FastISel. If FastISel is not run, this is the entire
832 SelectBasicBlock(LLVMBB, BI, End);
841 SelectionDAGISel::FinishBasicBlock() {
843 DOUT << "Target-post-processed machine code:\n";
846 DOUT << "Total amount of phi nodes to update: "
847 << SDL->PHINodesToUpdate.size() << "\n";
848 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
849 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first
850 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";);
852 // Next, now that we know what the last MBB the LLVM BB expanded is, update
853 // PHI nodes in successors.
854 if (SDL->SwitchCases.empty() &&
855 SDL->JTCases.empty() &&
856 SDL->BitTestCases.empty()) {
857 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
858 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
859 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
860 "This is not a machine PHI node that we are updating!");
861 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
863 PHI->addOperand(MachineOperand::CreateMBB(BB));
865 SDL->PHINodesToUpdate.clear();
869 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
870 // Lower header first, if it wasn't already lowered
871 if (!SDL->BitTestCases[i].Emitted) {
872 // Set the current basic block to the mbb we wish to insert the code into
873 BB = SDL->BitTestCases[i].Parent;
874 SDL->setCurrentBasicBlock(BB);
876 SDL->visitBitTestHeader(SDL->BitTestCases[i]);
877 CurDAG->setRoot(SDL->getRoot());
882 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
883 // Set the current basic block to the mbb we wish to insert the code into
884 BB = SDL->BitTestCases[i].Cases[j].ThisBB;
885 SDL->setCurrentBasicBlock(BB);
888 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
889 SDL->BitTestCases[i].Reg,
890 SDL->BitTestCases[i].Cases[j]);
892 SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
893 SDL->BitTestCases[i].Reg,
894 SDL->BitTestCases[i].Cases[j]);
897 CurDAG->setRoot(SDL->getRoot());
903 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
904 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
905 MachineBasicBlock *PHIBB = PHI->getParent();
906 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
907 "This is not a machine PHI node that we are updating!");
908 // This is "default" BB. We have two jumps to it. From "header" BB and
909 // from last "case" BB.
910 if (PHIBB == SDL->BitTestCases[i].Default) {
911 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
913 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
914 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
916 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
919 // One of "cases" BB.
920 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
922 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
923 if (cBB->succ_end() !=
924 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
925 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
927 PHI->addOperand(MachineOperand::CreateMBB(cBB));
932 SDL->BitTestCases.clear();
934 // If the JumpTable record is filled in, then we need to emit a jump table.
935 // Updating the PHI nodes is tricky in this case, since we need to determine
936 // whether the PHI is a successor of the range check MBB or the jump table MBB
937 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
938 // Lower header first, if it wasn't already lowered
939 if (!SDL->JTCases[i].first.Emitted) {
940 // Set the current basic block to the mbb we wish to insert the code into
941 BB = SDL->JTCases[i].first.HeaderBB;
942 SDL->setCurrentBasicBlock(BB);
944 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
945 CurDAG->setRoot(SDL->getRoot());
950 // Set the current basic block to the mbb we wish to insert the code into
951 BB = SDL->JTCases[i].second.MBB;
952 SDL->setCurrentBasicBlock(BB);
954 SDL->visitJumpTable(SDL->JTCases[i].second);
955 CurDAG->setRoot(SDL->getRoot());
960 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
961 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
962 MachineBasicBlock *PHIBB = PHI->getParent();
963 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
964 "This is not a machine PHI node that we are updating!");
965 // "default" BB. We can go there only from header BB.
966 if (PHIBB == SDL->JTCases[i].second.Default) {
967 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
969 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
971 // JT BB. Just iterate over successors here
972 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
973 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
975 PHI->addOperand(MachineOperand::CreateMBB(BB));
979 SDL->JTCases.clear();
981 // If the switch block involved a branch to one of the actual successors, we
982 // need to update PHI nodes in that block.
983 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
984 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
985 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
986 "This is not a machine PHI node that we are updating!");
987 if (BB->isSuccessor(PHI->getParent())) {
988 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
990 PHI->addOperand(MachineOperand::CreateMBB(BB));
994 // If we generated any switch lowering information, build and codegen any
995 // additional DAGs necessary.
996 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
997 // Set the current basic block to the mbb we wish to insert the code into
998 BB = SDL->SwitchCases[i].ThisBB;
999 SDL->setCurrentBasicBlock(BB);
1002 SDL->visitSwitchCase(SDL->SwitchCases[i]);
1003 CurDAG->setRoot(SDL->getRoot());
1004 CodeGenAndEmitDAG();
1007 // Handle any PHI nodes in successors of this chunk, as if we were coming
1008 // from the original BB before switch expansion. Note that PHI nodes can
1009 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1010 // handle them the right number of times.
1011 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1012 for (MachineBasicBlock::iterator Phi = BB->begin();
1013 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
1014 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
1015 for (unsigned pn = 0; ; ++pn) {
1016 assert(pn != SDL->PHINodesToUpdate.size() &&
1017 "Didn't find PHI entry!");
1018 if (SDL->PHINodesToUpdate[pn].first == Phi) {
1019 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
1021 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
1027 // Don't process RHS if same block as LHS.
1028 if (BB == SDL->SwitchCases[i].FalseBB)
1029 SDL->SwitchCases[i].FalseBB = 0;
1031 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1032 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
1033 SDL->SwitchCases[i].FalseBB = 0;
1035 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
1037 SDL->SwitchCases.clear();
1039 SDL->PHINodesToUpdate.clear();
1043 /// Schedule - Pick a safe ordering for instructions for each
1044 /// target node in the graph.
1046 ScheduleDAG *SelectionDAGISel::Schedule() {
1047 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1051 RegisterScheduler::setDefault(Ctor);
1054 TargetMachine &TM = getTargetLowering().getTargetMachine();
1055 ScheduleDAG *Scheduler = Ctor(this, CurDAG, &TM, BB, Fast);
1062 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1063 return new HazardRecognizer();
1066 //===----------------------------------------------------------------------===//
1067 // Helper functions used by the generated instruction selector.
1068 //===----------------------------------------------------------------------===//
1069 // Calls to these methods are generated by tblgen.
1071 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1072 /// the dag combiner simplified the 255, we still want to match. RHS is the
1073 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1074 /// specified in the .td file (e.g. 255).
1075 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1076 int64_t DesiredMaskS) const {
1077 const APInt &ActualMask = RHS->getAPIntValue();
1078 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1080 // If the actual mask exactly matches, success!
1081 if (ActualMask == DesiredMask)
1084 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1085 if (ActualMask.intersects(~DesiredMask))
1088 // Otherwise, the DAG Combiner may have proven that the value coming in is
1089 // either already zero or is not demanded. Check for known zero input bits.
1090 APInt NeededMask = DesiredMask & ~ActualMask;
1091 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1094 // TODO: check to see if missing bits are just not demanded.
1096 // Otherwise, this pattern doesn't match.
1100 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1101 /// the dag combiner simplified the 255, we still want to match. RHS is the
1102 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1103 /// specified in the .td file (e.g. 255).
1104 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1105 int64_t DesiredMaskS) const {
1106 const APInt &ActualMask = RHS->getAPIntValue();
1107 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1109 // If the actual mask exactly matches, success!
1110 if (ActualMask == DesiredMask)
1113 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1114 if (ActualMask.intersects(~DesiredMask))
1117 // Otherwise, the DAG Combiner may have proven that the value coming in is
1118 // either already zero or is not demanded. Check for known zero input bits.
1119 APInt NeededMask = DesiredMask & ~ActualMask;
1121 APInt KnownZero, KnownOne;
1122 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1124 // If all the missing bits in the or are already known to be set, match!
1125 if ((NeededMask & KnownOne) == NeededMask)
1128 // TODO: check to see if missing bits are just not demanded.
1130 // Otherwise, this pattern doesn't match.
1135 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1136 /// by tblgen. Others should not call it.
1137 void SelectionDAGISel::
1138 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1139 std::vector<SDValue> InOps;
1140 std::swap(InOps, Ops);
1142 Ops.push_back(InOps[0]); // input chain.
1143 Ops.push_back(InOps[1]); // input asm string.
1145 unsigned i = 2, e = InOps.size();
1146 if (InOps[e-1].getValueType() == MVT::Flag)
1147 --e; // Don't process a flag operand if it is here.
1150 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1151 if ((Flags & 7) != 4 /*MEM*/) {
1152 // Just skip over this operand, copying the operands verbatim.
1153 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
1154 i += (Flags >> 3) + 1;
1156 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
1157 // Otherwise, this is a memory operand. Ask the target to select it.
1158 std::vector<SDValue> SelOps;
1159 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1160 cerr << "Could not match memory address. Inline asm failure!\n";
1164 // Add this to the output node.
1165 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
1166 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1168 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1173 // Add the flag input back if present.
1174 if (e != InOps.size())
1175 Ops.push_back(InOps.back());
1178 char SelectionDAGISel::ID = 0;