1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register"
85 static RegisterScheduler
86 defaultListDAGScheduler("default", " Best scheduler for the target",
87 createDefaultScheduler);
90 namespace { struct AsmOperandInfo; }
93 /// RegsForValue - This struct represents the physical registers that a
94 /// particular value is assigned and the type information about the value.
95 /// This is needed because values can be promoted into larger registers and
96 /// expanded into multiple smaller registers than the value.
97 struct VISIBILITY_HIDDEN RegsForValue {
98 /// Regs - This list holds the register (for legal and promoted values)
99 /// or register set (for expanded values) that the value should be assigned
101 std::vector<unsigned> Regs;
103 /// RegVT - The value type of each register.
105 MVT::ValueType RegVT;
107 /// ValueVT - The value type of the LLVM value, which may be promoted from
108 /// RegVT or made from merging the two expanded parts.
109 MVT::ValueType ValueVT;
111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
114 : RegVT(regvt), ValueVT(valuevt) {
117 RegsForValue(const std::vector<unsigned> ®s,
118 MVT::ValueType regvt, MVT::ValueType valuevt)
119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
123 /// this value and returns the result as a ValueVT value. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
125 /// If the Flag pointer is NULL, no flag is used.
126 SDOperand getCopyFromRegs(SelectionDAG &DAG,
127 SDOperand &Chain, SDOperand *Flag) const;
129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
130 /// specified value into the registers specified by this object. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 /// If the Flag pointer is NULL, no flag is used.
133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
134 SDOperand &Chain, SDOperand *Flag) const;
136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
137 /// operand list. This adds the code marker and includes the number of
138 /// values added into it.
139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
140 std::vector<SDOperand> &Ops) const;
145 //===--------------------------------------------------------------------===//
146 /// createDefaultScheduler - This creates an instruction scheduler appropriate
148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
150 MachineBasicBlock *BB) {
151 TargetLowering &TLI = IS->getTargetLowering();
153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
154 return createTDListDAGScheduler(IS, DAG, BB);
156 assert(TLI.getSchedulingPreference() ==
157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
158 return createBURRListDAGScheduler(IS, DAG, BB);
163 //===--------------------------------------------------------------------===//
164 /// FunctionLoweringInfo - This contains information that is global to a
165 /// function that is used when lowering a region of the function.
166 class FunctionLoweringInfo {
171 MachineRegisterInfo &RegInfo;
173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
178 /// ValueMap - Since we emit code for the function a basic block at a time,
179 /// we must remember which virtual registers hold the values for
180 /// cross-basic-block values.
181 DenseMap<const Value*, unsigned> ValueMap;
183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
184 /// the entry block. This allows the allocas to be efficiently referenced
185 /// anywhere in the function.
186 std::map<const AllocaInst*, int> StaticAllocaMap;
189 SmallSet<Instruction*, 8> CatchInfoLost;
190 SmallSet<Instruction*, 8> CatchInfoFound;
193 unsigned MakeReg(MVT::ValueType VT) {
194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
197 /// isExportedInst - Return true if the specified value is an instruction
198 /// exported from its block.
199 bool isExportedInst(const Value *V) {
200 return ValueMap.count(V);
203 unsigned CreateRegForValue(const Value *V);
205 unsigned InitializeRegForValue(const Value *V) {
206 unsigned &R = ValueMap[V];
207 assert(R == 0 && "Already initialized this value register!");
208 return R = CreateRegForValue(V);
213 /// isSelector - Return true if this instruction is a call to the
214 /// eh.selector intrinsic.
215 static bool isSelector(Instruction *I) {
216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
218 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
222 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
223 /// PHI nodes or outside of the basic block that defines it, or used by a
224 /// switch instruction, which may expand to multiple basic blocks.
225 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
226 if (isa<PHINode>(I)) return true;
227 BasicBlock *BB = I->getParent();
228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
230 // FIXME: Remove switchinst special case.
231 isa<SwitchInst>(*UI))
236 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
237 /// entry block, return true. This includes arguments used by switches, since
238 /// the switch may expand into multiple basic blocks.
239 static bool isOnlyUsedInEntryBlock(Argument *A) {
240 BasicBlock *Entry = A->getParent()->begin();
241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
243 return false; // Use not in entry block.
247 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
248 Function &fn, MachineFunction &mf)
249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
251 // Create a vreg for each argument register that is not dead and is used
252 // outside of the entry block for the function.
253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
255 if (!isOnlyUsedInEntryBlock(AI))
256 InitializeRegForValue(AI);
258 // Initialize the mapping of values to registers. This is only set up for
259 // instruction values that are used outside of the block that defines
261 Function::iterator BB = Fn.begin(), EB = Fn.end();
262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
265 const Type *Ty = AI->getAllocatedType();
266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
271 TySize *= CUI->getZExtValue(); // Get total allocated size.
272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
273 StaticAllocaMap[AI] =
274 MF.getFrameInfo()->CreateStackObject(TySize, Align);
277 for (; BB != EB; ++BB)
278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
280 if (!isa<AllocaInst>(I) ||
281 !StaticAllocaMap.count(cast<AllocaInst>(I)))
282 InitializeRegForValue(I);
284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
285 // also creates the initial PHI MachineInstrs, though none of the input
286 // operands are populated.
287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
288 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
290 MF.getBasicBlockList().push_back(MBB);
292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
296 if (PN->use_empty()) continue;
298 MVT::ValueType VT = TLI.getValueType(PN->getType());
299 unsigned NumRegisters = TLI.getNumRegisters(VT);
300 unsigned PHIReg = ValueMap[PN];
301 assert(PHIReg && "PHI node does not have an assigned virtual register!");
302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
303 for (unsigned i = 0; i != NumRegisters; ++i)
304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
309 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
310 /// the correctly promoted or expanded types. Assign these registers
311 /// consecutive vreg numbers and return the first assigned number.
312 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
313 MVT::ValueType VT = TLI.getValueType(V->getType());
315 unsigned NumRegisters = TLI.getNumRegisters(VT);
316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
318 unsigned R = MakeReg(RegisterVT);
319 for (unsigned i = 1; i != NumRegisters; ++i)
325 //===----------------------------------------------------------------------===//
326 /// SelectionDAGLowering - This is the common target-independent lowering
327 /// implementation that is parameterized by a TargetLowering object.
328 /// Also, targets can overload any lowering method.
331 class SelectionDAGLowering {
332 MachineBasicBlock *CurMBB;
334 DenseMap<const Value*, SDOperand> NodeMap;
336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
337 /// them up and then emit token factor nodes when possible. This allows us to
338 /// get simple disambiguation between loads without worrying about alias
340 std::vector<SDOperand> PendingLoads;
342 /// Case - A struct to record the Value for a switch case, and the
343 /// case's target basic block.
347 MachineBasicBlock* BB;
349 Case() : Low(0), High(0), BB(0) { }
350 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
351 Low(low), High(high), BB(bb) { }
352 uint64_t size() const {
353 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
354 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
355 return (rHigh - rLow + 1ULL);
361 MachineBasicBlock* BB;
364 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
365 Mask(mask), BB(bb), Bits(bits) { }
368 typedef std::vector<Case> CaseVector;
369 typedef std::vector<CaseBits> CaseBitsVector;
370 typedef CaseVector::iterator CaseItr;
371 typedef std::pair<CaseItr, CaseItr> CaseRange;
373 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
374 /// of conditional branches.
376 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
377 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
379 /// CaseBB - The MBB in which to emit the compare and branch
380 MachineBasicBlock *CaseBB;
381 /// LT, GE - If nonzero, we know the current case value must be less-than or
382 /// greater-than-or-equal-to these Constants.
385 /// Range - A pair of iterators representing the range of case values to be
386 /// processed at this point in the binary search tree.
390 typedef std::vector<CaseRec> CaseRecVector;
392 /// The comparison function for sorting the switch case values in the vector.
393 /// WARNING: Case ranges should be disjoint!
395 bool operator () (const Case& C1, const Case& C2) {
396 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
397 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
398 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
399 return CI1->getValue().slt(CI2->getValue());
404 bool operator () (const CaseBits& C1, const CaseBits& C2) {
405 return C1.Bits > C2.Bits;
409 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
412 // TLI - This is information that describes the available target features we
413 // need for lowering. This indicates when operations are unavailable,
414 // implemented with a libcall, etc.
417 const TargetData *TD;
420 /// SwitchCases - Vector of CaseBlock structures used to communicate
421 /// SwitchInst code generation information.
422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
423 /// JTCases - Vector of JumpTable structures used to communicate
424 /// SwitchInst code generation information.
425 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
426 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
428 /// FuncInfo - Information about the function as a whole.
430 FunctionLoweringInfo &FuncInfo;
432 /// GCI - Garbage collection metadata for the function.
433 CollectorMetadata *GCI;
435 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
437 FunctionLoweringInfo &funcinfo,
438 CollectorMetadata *gci)
439 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
440 FuncInfo(funcinfo), GCI(gci) {
443 /// getRoot - Return the current virtual root of the Selection DAG.
445 SDOperand getRoot() {
446 if (PendingLoads.empty())
447 return DAG.getRoot();
449 if (PendingLoads.size() == 1) {
450 SDOperand Root = PendingLoads[0];
452 PendingLoads.clear();
456 // Otherwise, we have to make a token factor node.
457 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
458 &PendingLoads[0], PendingLoads.size());
459 PendingLoads.clear();
464 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
466 void visit(Instruction &I) { visit(I.getOpcode(), I); }
468 void visit(unsigned Opcode, User &I) {
469 // Note: this doesn't use InstVisitor, because it has to work with
470 // ConstantExpr's in addition to instructions.
472 default: assert(0 && "Unknown instruction type encountered!");
474 // Build the switch statement using the Instruction.def file.
475 #define HANDLE_INST(NUM, OPCODE, CLASS) \
476 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
477 #include "llvm/Instruction.def"
481 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
483 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
484 const Value *SV, SDOperand Root,
485 bool isVolatile, unsigned Alignment);
487 SDOperand getValue(const Value *V);
489 void setValue(const Value *V, SDOperand NewN) {
490 SDOperand &N = NodeMap[V];
491 assert(N.Val == 0 && "Already set a value for this node!");
495 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
496 std::set<unsigned> &OutputRegs,
497 std::set<unsigned> &InputRegs);
499 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
500 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
502 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
503 void ExportFromCurrentBlock(Value *V);
504 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
505 MachineBasicBlock *LandingPad = NULL);
507 // Terminator instructions.
508 void visitRet(ReturnInst &I);
509 void visitBr(BranchInst &I);
510 void visitSwitch(SwitchInst &I);
511 void visitUnreachable(UnreachableInst &I) { /* noop */ }
513 // Helpers for visitSwitch
514 bool handleSmallSwitchRange(CaseRec& CR,
515 CaseRecVector& WorkList,
517 MachineBasicBlock* Default);
518 bool handleJTSwitchCase(CaseRec& CR,
519 CaseRecVector& WorkList,
521 MachineBasicBlock* Default);
522 bool handleBTSplitSwitchCase(CaseRec& CR,
523 CaseRecVector& WorkList,
525 MachineBasicBlock* Default);
526 bool handleBitTestsSwitchCase(CaseRec& CR,
527 CaseRecVector& WorkList,
529 MachineBasicBlock* Default);
530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
532 void visitBitTestCase(MachineBasicBlock* NextMBB,
534 SelectionDAGISel::BitTestCase &B);
535 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
537 SelectionDAGISel::JumpTableHeader &JTH);
539 // These all get lowered before this pass.
540 void visitInvoke(InvokeInst &I);
541 void visitUnwind(UnwindInst &I);
543 void visitBinary(User &I, unsigned OpCode);
544 void visitShift(User &I, unsigned Opcode);
545 void visitAdd(User &I) {
546 if (I.getType()->isFPOrFPVector())
547 visitBinary(I, ISD::FADD);
549 visitBinary(I, ISD::ADD);
551 void visitSub(User &I);
552 void visitMul(User &I) {
553 if (I.getType()->isFPOrFPVector())
554 visitBinary(I, ISD::FMUL);
556 visitBinary(I, ISD::MUL);
558 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
564 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
565 void visitOr (User &I) { visitBinary(I, ISD::OR); }
566 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
567 void visitShl (User &I) { visitShift(I, ISD::SHL); }
568 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
569 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
570 void visitICmp(User &I);
571 void visitFCmp(User &I);
572 // Visit the conversion instructions
573 void visitTrunc(User &I);
574 void visitZExt(User &I);
575 void visitSExt(User &I);
576 void visitFPTrunc(User &I);
577 void visitFPExt(User &I);
578 void visitFPToUI(User &I);
579 void visitFPToSI(User &I);
580 void visitUIToFP(User &I);
581 void visitSIToFP(User &I);
582 void visitPtrToInt(User &I);
583 void visitIntToPtr(User &I);
584 void visitBitCast(User &I);
586 void visitExtractElement(User &I);
587 void visitInsertElement(User &I);
588 void visitShuffleVector(User &I);
590 void visitGetElementPtr(User &I);
591 void visitSelect(User &I);
593 void visitMalloc(MallocInst &I);
594 void visitFree(FreeInst &I);
595 void visitAlloca(AllocaInst &I);
596 void visitLoad(LoadInst &I);
597 void visitStore(StoreInst &I);
598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
599 void visitCall(CallInst &I);
600 void visitInlineAsm(CallSite CS);
601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
604 void visitVAStart(CallInst &I);
605 void visitVAArg(VAArgInst &I);
606 void visitVAEnd(CallInst &I);
607 void visitVACopy(CallInst &I);
609 void visitMemIntrinsic(CallInst &I, unsigned Op);
611 void visitUserOp1(Instruction &I) {
612 assert(0 && "UserOp1 should not exist at instruction selection time!");
615 void visitUserOp2(Instruction &I) {
616 assert(0 && "UserOp2 should not exist at instruction selection time!");
620 } // end namespace llvm
623 /// getCopyFromParts - Create a value that contains the specified legal parts
624 /// combined into the value they represent. If the parts combine to a type
625 /// larger then ValueVT then AssertOp can be used to specify whether the extra
626 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
627 /// (ISD::AssertSext). Likewise TruncExact is used for floating point types to
628 /// indicate that the extra bits can be discarded without losing precision.
629 static SDOperand getCopyFromParts(SelectionDAG &DAG,
630 const SDOperand *Parts,
632 MVT::ValueType PartVT,
633 MVT::ValueType ValueVT,
634 ISD::NodeType AssertOp = ISD::DELETED_NODE,
635 bool TruncExact = false) {
636 if (!MVT::isVector(ValueVT) || NumParts == 1) {
637 SDOperand Val = Parts[0];
639 // If the value was expanded, copy from the top part.
641 assert(NumParts == 2 &&
642 "Cannot expand to more than 2 elts yet!");
643 SDOperand Hi = Parts[1];
644 if (!DAG.getTargetLoweringInfo().isLittleEndian())
646 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
649 // Otherwise, if the value was promoted or extended, truncate it to the
651 if (PartVT == ValueVT)
654 if (MVT::isVector(PartVT)) {
655 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
656 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
659 if (MVT::isVector(ValueVT)) {
660 assert(NumParts == 1 &&
661 MVT::getVectorElementType(ValueVT) == PartVT &&
662 MVT::getVectorNumElements(ValueVT) == 1 &&
663 "Only trivial scalar-to-vector conversions should get here!");
664 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
667 if (MVT::isInteger(PartVT) &&
668 MVT::isInteger(ValueVT)) {
669 if (ValueVT < PartVT) {
670 // For a truncate, see if we have any information to
671 // indicate whether the truncated bits will always be
672 // zero or sign-extension.
673 if (AssertOp != ISD::DELETED_NODE)
674 Val = DAG.getNode(AssertOp, PartVT, Val,
675 DAG.getValueType(ValueVT));
676 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
678 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
682 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
683 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
684 DAG.getIntPtrConstant(TruncExact));
686 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
687 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
689 assert(0 && "Unknown mismatch!");
692 // Handle a multi-element vector.
693 MVT::ValueType IntermediateVT, RegisterVT;
694 unsigned NumIntermediates;
696 DAG.getTargetLoweringInfo()
697 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
700 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
701 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
702 assert(RegisterVT == Parts[0].getValueType() &&
703 "Part type doesn't match part!");
705 // Assemble the parts into intermediate operands.
706 SmallVector<SDOperand, 8> Ops(NumIntermediates);
707 if (NumIntermediates == NumParts) {
708 // If the register was not expanded, truncate or copy the value,
710 for (unsigned i = 0; i != NumParts; ++i)
711 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
712 PartVT, IntermediateVT);
713 } else if (NumParts > 0) {
714 // If the intermediate type was expanded, build the intermediate operands
716 assert(NumParts % NumIntermediates == 0 &&
717 "Must expand into a divisible number of parts!");
718 unsigned Factor = NumParts / NumIntermediates;
719 for (unsigned i = 0; i != NumIntermediates; ++i)
720 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
721 PartVT, IntermediateVT);
724 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
726 return DAG.getNode(MVT::isVector(IntermediateVT) ?
727 ISD::CONCAT_VECTORS :
729 ValueVT, &Ops[0], NumIntermediates);
732 /// getCopyToParts - Create a series of nodes that contain the specified value
733 /// split into legal parts. If the parts contain more bits than Val, then, for
734 /// integers, ExtendKind can be used to specify how to generate the extra bits.
735 static void getCopyToParts(SelectionDAG &DAG,
739 MVT::ValueType PartVT,
740 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
741 TargetLowering &TLI = DAG.getTargetLoweringInfo();
742 MVT::ValueType PtrVT = TLI.getPointerTy();
743 MVT::ValueType ValueVT = Val.getValueType();
745 if (!MVT::isVector(ValueVT) || NumParts == 1) {
746 // If the value was expanded, copy from the parts.
748 for (unsigned i = 0; i != NumParts; ++i)
749 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
750 DAG.getConstant(i, PtrVT));
751 if (!DAG.getTargetLoweringInfo().isLittleEndian())
752 std::reverse(Parts, Parts + NumParts);
756 // If there is a single part and the types differ, this must be
758 if (PartVT != ValueVT) {
759 if (MVT::isVector(PartVT)) {
760 assert(MVT::isVector(ValueVT) &&
761 "Not a vector-vector cast?");
762 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
763 } else if (MVT::isVector(ValueVT)) {
764 assert(NumParts == 1 &&
765 MVT::getVectorElementType(ValueVT) == PartVT &&
766 MVT::getVectorNumElements(ValueVT) == 1 &&
767 "Only trivial vector-to-scalar conversions should get here!");
768 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
769 DAG.getConstant(0, PtrVT));
770 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
771 if (PartVT < ValueVT)
772 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
774 Val = DAG.getNode(ExtendKind, PartVT, Val);
775 } else if (MVT::isFloatingPoint(PartVT) &&
776 MVT::isFloatingPoint(ValueVT)) {
777 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
778 } else if (MVT::getSizeInBits(PartVT) ==
779 MVT::getSizeInBits(ValueVT)) {
780 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
782 assert(0 && "Unknown mismatch!");
789 // Handle a multi-element vector.
790 MVT::ValueType IntermediateVT, RegisterVT;
791 unsigned NumIntermediates;
793 DAG.getTargetLoweringInfo()
794 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
796 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
798 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
799 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
801 // Split the vector into intermediate operands.
802 SmallVector<SDOperand, 8> Ops(NumIntermediates);
803 for (unsigned i = 0; i != NumIntermediates; ++i)
804 if (MVT::isVector(IntermediateVT))
805 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
807 DAG.getConstant(i * (NumElements / NumIntermediates),
810 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
812 DAG.getConstant(i, PtrVT));
814 // Split the intermediate operands into legal parts.
815 if (NumParts == NumIntermediates) {
816 // If the register was not expanded, promote or copy the value,
818 for (unsigned i = 0; i != NumParts; ++i)
819 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
820 } else if (NumParts > 0) {
821 // If the intermediate type was expanded, split each the value into
823 assert(NumParts % NumIntermediates == 0 &&
824 "Must expand into a divisible number of parts!");
825 unsigned Factor = NumParts / NumIntermediates;
826 for (unsigned i = 0; i != NumIntermediates; ++i)
827 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
832 SDOperand SelectionDAGLowering::getValue(const Value *V) {
833 SDOperand &N = NodeMap[V];
836 const Type *VTy = V->getType();
837 MVT::ValueType VT = TLI.getValueType(VTy);
838 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
839 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
840 visit(CE->getOpcode(), *CE);
841 SDOperand N1 = NodeMap[V];
842 assert(N1.Val && "visit didn't populate the ValueMap!");
844 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
845 return N = DAG.getGlobalAddress(GV, VT);
846 } else if (isa<ConstantPointerNull>(C)) {
847 return N = DAG.getConstant(0, TLI.getPointerTy());
848 } else if (isa<UndefValue>(C)) {
849 if (!isa<VectorType>(VTy))
850 return N = DAG.getNode(ISD::UNDEF, VT);
852 // Create a BUILD_VECTOR of undef nodes.
853 const VectorType *PTy = cast<VectorType>(VTy);
854 unsigned NumElements = PTy->getNumElements();
855 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
857 SmallVector<SDOperand, 8> Ops;
858 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
860 // Create a VConstant node with generic Vector type.
861 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
862 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
863 &Ops[0], Ops.size());
864 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
865 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
866 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
867 unsigned NumElements = PTy->getNumElements();
868 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
870 // Now that we know the number and type of the elements, push a
871 // Constant or ConstantFP node onto the ops list for each element of
872 // the vector constant.
873 SmallVector<SDOperand, 8> Ops;
874 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
875 for (unsigned i = 0; i != NumElements; ++i)
876 Ops.push_back(getValue(CP->getOperand(i)));
878 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
880 if (MVT::isFloatingPoint(PVT))
881 Op = DAG.getConstantFP(0, PVT);
883 Op = DAG.getConstant(0, PVT);
884 Ops.assign(NumElements, Op);
887 // Create a BUILD_VECTOR node.
888 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
889 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
892 // Canonicalize all constant ints to be unsigned.
893 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
897 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
898 std::map<const AllocaInst*, int>::iterator SI =
899 FuncInfo.StaticAllocaMap.find(AI);
900 if (SI != FuncInfo.StaticAllocaMap.end())
901 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
904 unsigned InReg = FuncInfo.ValueMap[V];
905 assert(InReg && "Value not in map!");
907 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
908 unsigned NumRegs = TLI.getNumRegisters(VT);
910 std::vector<unsigned> Regs(NumRegs);
911 for (unsigned i = 0; i != NumRegs; ++i)
914 RegsForValue RFV(Regs, RegisterVT, VT);
915 SDOperand Chain = DAG.getEntryNode();
917 return RFV.getCopyFromRegs(DAG, Chain, NULL);
921 void SelectionDAGLowering::visitRet(ReturnInst &I) {
922 if (I.getNumOperands() == 0) {
923 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
926 SmallVector<SDOperand, 8> NewValues;
927 NewValues.push_back(getRoot());
928 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
929 SDOperand RetOp = getValue(I.getOperand(i));
930 MVT::ValueType VT = RetOp.getValueType();
932 // FIXME: C calling convention requires the return type to be promoted to
933 // at least 32-bit. But this is not necessary for non-C calling conventions.
934 if (MVT::isInteger(VT)) {
935 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32);
936 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT))
940 unsigned NumParts = TLI.getNumRegisters(VT);
941 MVT::ValueType PartVT = TLI.getRegisterType(VT);
942 SmallVector<SDOperand, 4> Parts(NumParts);
943 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
945 const Function *F = I.getParent()->getParent();
946 if (F->paramHasAttr(0, ParamAttr::SExt))
947 ExtendKind = ISD::SIGN_EXTEND;
948 else if (F->paramHasAttr(0, ParamAttr::ZExt))
949 ExtendKind = ISD::ZERO_EXTEND;
951 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
953 for (unsigned i = 0; i < NumParts; ++i) {
954 NewValues.push_back(Parts[i]);
955 NewValues.push_back(DAG.getConstant(false, MVT::i32));
958 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
959 &NewValues[0], NewValues.size()));
962 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
963 /// the current basic block, add it to ValueMap now so that we'll get a
965 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
966 // No need to export constants.
967 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
970 if (FuncInfo.isExportedInst(V)) return;
972 unsigned Reg = FuncInfo.InitializeRegForValue(V);
973 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
976 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
977 const BasicBlock *FromBB) {
978 // The operands of the setcc have to be in this block. We don't know
979 // how to export them from some other block.
980 if (Instruction *VI = dyn_cast<Instruction>(V)) {
981 // Can export from current BB.
982 if (VI->getParent() == FromBB)
985 // Is already exported, noop.
986 return FuncInfo.isExportedInst(V);
989 // If this is an argument, we can export it if the BB is the entry block or
990 // if it is already exported.
991 if (isa<Argument>(V)) {
992 if (FromBB == &FromBB->getParent()->getEntryBlock())
995 // Otherwise, can only export this if it is already exported.
996 return FuncInfo.isExportedInst(V);
999 // Otherwise, constants can always be exported.
1003 static bool InBlock(const Value *V, const BasicBlock *BB) {
1004 if (const Instruction *I = dyn_cast<Instruction>(V))
1005 return I->getParent() == BB;
1009 /// FindMergedConditions - If Cond is an expression like
1010 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1011 MachineBasicBlock *TBB,
1012 MachineBasicBlock *FBB,
1013 MachineBasicBlock *CurBB,
1015 // If this node is not part of the or/and tree, emit it as a branch.
1016 Instruction *BOp = dyn_cast<Instruction>(Cond);
1018 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1019 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1020 BOp->getParent() != CurBB->getBasicBlock() ||
1021 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1022 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1023 const BasicBlock *BB = CurBB->getBasicBlock();
1025 // If the leaf of the tree is a comparison, merge the condition into
1027 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1028 // The operands of the cmp have to be in this block. We don't know
1029 // how to export them from some other block. If this is the first block
1030 // of the sequence, no exporting is needed.
1032 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1033 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1034 BOp = cast<Instruction>(Cond);
1035 ISD::CondCode Condition;
1036 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1037 switch (IC->getPredicate()) {
1038 default: assert(0 && "Unknown icmp predicate opcode!");
1039 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1040 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1041 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1042 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1043 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1044 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1045 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1046 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1047 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1048 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1050 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1051 ISD::CondCode FPC, FOC;
1052 switch (FC->getPredicate()) {
1053 default: assert(0 && "Unknown fcmp predicate opcode!");
1054 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1055 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1056 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1057 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1058 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1059 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1060 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1061 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1062 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1063 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1064 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1065 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1066 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1067 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1068 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1069 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1071 if (FiniteOnlyFPMath())
1076 Condition = ISD::SETEQ; // silence warning.
1077 assert(0 && "Unknown compare instruction");
1080 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1081 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1082 SwitchCases.push_back(CB);
1086 // Create a CaseBlock record representing this branch.
1087 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1088 NULL, TBB, FBB, CurBB);
1089 SwitchCases.push_back(CB);
1094 // Create TmpBB after CurBB.
1095 MachineFunction::iterator BBI = CurBB;
1096 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1097 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1099 if (Opc == Instruction::Or) {
1100 // Codegen X | Y as:
1108 // Emit the LHS condition.
1109 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1111 // Emit the RHS condition into TmpBB.
1112 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1114 assert(Opc == Instruction::And && "Unknown merge op!");
1115 // Codegen X & Y as:
1122 // This requires creation of TmpBB after CurBB.
1124 // Emit the LHS condition.
1125 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1127 // Emit the RHS condition into TmpBB.
1128 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1132 /// If the set of cases should be emitted as a series of branches, return true.
1133 /// If we should emit this as a bunch of and/or'd together conditions, return
1136 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1137 if (Cases.size() != 2) return true;
1139 // If this is two comparisons of the same values or'd or and'd together, they
1140 // will get folded into a single comparison, so don't emit two blocks.
1141 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1142 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1143 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1144 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1151 void SelectionDAGLowering::visitBr(BranchInst &I) {
1152 // Update machine-CFG edges.
1153 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1155 // Figure out which block is immediately after the current one.
1156 MachineBasicBlock *NextBlock = 0;
1157 MachineFunction::iterator BBI = CurMBB;
1158 if (++BBI != CurMBB->getParent()->end())
1161 if (I.isUnconditional()) {
1162 // If this is not a fall-through branch, emit the branch.
1163 if (Succ0MBB != NextBlock)
1164 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1165 DAG.getBasicBlock(Succ0MBB)));
1167 // Update machine-CFG edges.
1168 CurMBB->addSuccessor(Succ0MBB);
1172 // If this condition is one of the special cases we handle, do special stuff
1174 Value *CondVal = I.getCondition();
1175 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1177 // If this is a series of conditions that are or'd or and'd together, emit
1178 // this as a sequence of branches instead of setcc's with and/or operations.
1179 // For example, instead of something like:
1192 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1193 if (BOp->hasOneUse() &&
1194 (BOp->getOpcode() == Instruction::And ||
1195 BOp->getOpcode() == Instruction::Or)) {
1196 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1197 // If the compares in later blocks need to use values not currently
1198 // exported from this block, export them now. This block should always
1199 // be the first entry.
1200 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1202 // Allow some cases to be rejected.
1203 if (ShouldEmitAsBranches(SwitchCases)) {
1204 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1205 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1206 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1209 // Emit the branch for this block.
1210 visitSwitchCase(SwitchCases[0]);
1211 SwitchCases.erase(SwitchCases.begin());
1215 // Okay, we decided not to do this, remove any inserted MBB's and clear
1217 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1218 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1220 SwitchCases.clear();
1224 // Create a CaseBlock record representing this branch.
1225 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1226 NULL, Succ0MBB, Succ1MBB, CurMBB);
1227 // Use visitSwitchCase to actually insert the fast branch sequence for this
1229 visitSwitchCase(CB);
1232 /// visitSwitchCase - Emits the necessary code to represent a single node in
1233 /// the binary search tree resulting from lowering a switch instruction.
1234 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1236 SDOperand CondLHS = getValue(CB.CmpLHS);
1238 // Build the setcc now.
1239 if (CB.CmpMHS == NULL) {
1240 // Fold "(X == true)" to X and "(X == false)" to !X to
1241 // handle common cases produced by branch lowering.
1242 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1244 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1245 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1246 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1248 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1250 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1252 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1253 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1255 SDOperand CmpOp = getValue(CB.CmpMHS);
1256 MVT::ValueType VT = CmpOp.getValueType();
1258 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1259 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1261 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1262 Cond = DAG.getSetCC(MVT::i1, SUB,
1263 DAG.getConstant(High-Low, VT), ISD::SETULE);
1268 // Set NextBlock to be the MBB immediately after the current one, if any.
1269 // This is used to avoid emitting unnecessary branches to the next block.
1270 MachineBasicBlock *NextBlock = 0;
1271 MachineFunction::iterator BBI = CurMBB;
1272 if (++BBI != CurMBB->getParent()->end())
1275 // If the lhs block is the next block, invert the condition so that we can
1276 // fall through to the lhs instead of the rhs block.
1277 if (CB.TrueBB == NextBlock) {
1278 std::swap(CB.TrueBB, CB.FalseBB);
1279 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1280 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1282 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1283 DAG.getBasicBlock(CB.TrueBB));
1284 if (CB.FalseBB == NextBlock)
1285 DAG.setRoot(BrCond);
1287 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1288 DAG.getBasicBlock(CB.FalseBB)));
1289 // Update successor info
1290 CurMBB->addSuccessor(CB.TrueBB);
1291 CurMBB->addSuccessor(CB.FalseBB);
1294 /// visitJumpTable - Emit JumpTable node in the current MBB
1295 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1296 // Emit the code for the jump table
1297 assert(JT.Reg != -1U && "Should lower JT Header first!");
1298 MVT::ValueType PTy = TLI.getPointerTy();
1299 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1300 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1301 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1306 /// visitJumpTableHeader - This function emits necessary code to produce index
1307 /// in the JumpTable from switch case.
1308 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1309 SelectionDAGISel::JumpTableHeader &JTH) {
1310 // Subtract the lowest switch case value from the value being switched on
1311 // and conditional branch to default mbb if the result is greater than the
1312 // difference between smallest and largest cases.
1313 SDOperand SwitchOp = getValue(JTH.SValue);
1314 MVT::ValueType VT = SwitchOp.getValueType();
1315 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1316 DAG.getConstant(JTH.First, VT));
1318 // The SDNode we just created, which holds the value being switched on
1319 // minus the the smallest case value, needs to be copied to a virtual
1320 // register so it can be used as an index into the jump table in a
1321 // subsequent basic block. This value may be smaller or larger than the
1322 // target's pointer type, and therefore require extension or truncating.
1323 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1324 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1326 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1328 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1329 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1330 JT.Reg = JumpTableReg;
1332 // Emit the range check for the jump table, and branch to the default
1333 // block for the switch statement if the value being switched on exceeds
1334 // the largest case in the switch.
1335 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1336 DAG.getConstant(JTH.Last-JTH.First,VT),
1339 // Set NextBlock to be the MBB immediately after the current one, if any.
1340 // This is used to avoid emitting unnecessary branches to the next block.
1341 MachineBasicBlock *NextBlock = 0;
1342 MachineFunction::iterator BBI = CurMBB;
1343 if (++BBI != CurMBB->getParent()->end())
1346 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1347 DAG.getBasicBlock(JT.Default));
1349 if (JT.MBB == NextBlock)
1350 DAG.setRoot(BrCond);
1352 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1353 DAG.getBasicBlock(JT.MBB)));
1358 /// visitBitTestHeader - This function emits necessary code to produce value
1359 /// suitable for "bit tests"
1360 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1361 // Subtract the minimum value
1362 SDOperand SwitchOp = getValue(B.SValue);
1363 MVT::ValueType VT = SwitchOp.getValueType();
1364 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1365 DAG.getConstant(B.First, VT));
1368 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1369 DAG.getConstant(B.Range, VT),
1373 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1374 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1376 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1378 // Make desired shift
1379 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1380 DAG.getConstant(1, TLI.getPointerTy()),
1383 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1384 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1387 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1388 DAG.getBasicBlock(B.Default));
1390 // Set NextBlock to be the MBB immediately after the current one, if any.
1391 // This is used to avoid emitting unnecessary branches to the next block.
1392 MachineBasicBlock *NextBlock = 0;
1393 MachineFunction::iterator BBI = CurMBB;
1394 if (++BBI != CurMBB->getParent()->end())
1397 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1398 if (MBB == NextBlock)
1399 DAG.setRoot(BrRange);
1401 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1402 DAG.getBasicBlock(MBB)));
1404 CurMBB->addSuccessor(B.Default);
1405 CurMBB->addSuccessor(MBB);
1410 /// visitBitTestCase - this function produces one "bit test"
1411 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1413 SelectionDAGISel::BitTestCase &B) {
1414 // Emit bit tests and jumps
1415 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1417 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1419 DAG.getConstant(B.Mask,
1420 TLI.getPointerTy()));
1421 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1422 DAG.getConstant(0, TLI.getPointerTy()),
1424 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1425 AndCmp, DAG.getBasicBlock(B.TargetBB));
1427 // Set NextBlock to be the MBB immediately after the current one, if any.
1428 // This is used to avoid emitting unnecessary branches to the next block.
1429 MachineBasicBlock *NextBlock = 0;
1430 MachineFunction::iterator BBI = CurMBB;
1431 if (++BBI != CurMBB->getParent()->end())
1434 if (NextMBB == NextBlock)
1437 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1438 DAG.getBasicBlock(NextMBB)));
1440 CurMBB->addSuccessor(B.TargetBB);
1441 CurMBB->addSuccessor(NextMBB);
1446 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1447 // Retrieve successors.
1448 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1449 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1451 if (isa<InlineAsm>(I.getCalledValue()))
1454 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1456 // If the value of the invoke is used outside of its defining block, make it
1457 // available as a virtual register.
1458 if (!I.use_empty()) {
1459 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1460 if (VMI != FuncInfo.ValueMap.end())
1461 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1464 // Drop into normal successor.
1465 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1466 DAG.getBasicBlock(Return)));
1468 // Update successor info
1469 CurMBB->addSuccessor(Return);
1470 CurMBB->addSuccessor(LandingPad);
1473 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1476 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1477 /// small case ranges).
1478 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1479 CaseRecVector& WorkList,
1481 MachineBasicBlock* Default) {
1482 Case& BackCase = *(CR.Range.second-1);
1484 // Size is the number of Cases represented by this range.
1485 unsigned Size = CR.Range.second - CR.Range.first;
1489 // Get the MachineFunction which holds the current MBB. This is used when
1490 // inserting any additional MBBs necessary to represent the switch.
1491 MachineFunction *CurMF = CurMBB->getParent();
1493 // Figure out which block is immediately after the current one.
1494 MachineBasicBlock *NextBlock = 0;
1495 MachineFunction::iterator BBI = CR.CaseBB;
1497 if (++BBI != CurMBB->getParent()->end())
1500 // TODO: If any two of the cases has the same destination, and if one value
1501 // is the same as the other, but has one bit unset that the other has set,
1502 // use bit manipulation to do two compares at once. For example:
1503 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1505 // Rearrange the case blocks so that the last one falls through if possible.
1506 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1507 // The last case block won't fall through into 'NextBlock' if we emit the
1508 // branches in this order. See if rearranging a case value would help.
1509 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1510 if (I->BB == NextBlock) {
1511 std::swap(*I, BackCase);
1517 // Create a CaseBlock record representing a conditional branch to
1518 // the Case's target mbb if the value being switched on SV is equal
1520 MachineBasicBlock *CurBlock = CR.CaseBB;
1521 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1522 MachineBasicBlock *FallThrough;
1524 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1525 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1527 // If the last case doesn't match, go to the default block.
1528 FallThrough = Default;
1531 Value *RHS, *LHS, *MHS;
1533 if (I->High == I->Low) {
1534 // This is just small small case range :) containing exactly 1 case
1536 LHS = SV; RHS = I->High; MHS = NULL;
1539 LHS = I->Low; MHS = SV; RHS = I->High;
1541 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1542 I->BB, FallThrough, CurBlock);
1544 // If emitting the first comparison, just call visitSwitchCase to emit the
1545 // code into the current block. Otherwise, push the CaseBlock onto the
1546 // vector to be later processed by SDISel, and insert the node's MBB
1547 // before the next MBB.
1548 if (CurBlock == CurMBB)
1549 visitSwitchCase(CB);
1551 SwitchCases.push_back(CB);
1553 CurBlock = FallThrough;
1559 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1560 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1561 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1564 /// handleJTSwitchCase - Emit jumptable for current switch case range
1565 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1566 CaseRecVector& WorkList,
1568 MachineBasicBlock* Default) {
1569 Case& FrontCase = *CR.Range.first;
1570 Case& BackCase = *(CR.Range.second-1);
1572 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1573 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1576 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1580 if (!areJTsAllowed(TLI) || TSize <= 3)
1583 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1587 DOUT << "Lowering jump table\n"
1588 << "First entry: " << First << ". Last entry: " << Last << "\n"
1589 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1591 // Get the MachineFunction which holds the current MBB. This is used when
1592 // inserting any additional MBBs necessary to represent the switch.
1593 MachineFunction *CurMF = CurMBB->getParent();
1595 // Figure out which block is immediately after the current one.
1596 MachineBasicBlock *NextBlock = 0;
1597 MachineFunction::iterator BBI = CR.CaseBB;
1599 if (++BBI != CurMBB->getParent()->end())
1602 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1604 // Create a new basic block to hold the code for loading the address
1605 // of the jump table, and jumping to it. Update successor information;
1606 // we will either branch to the default case for the switch, or the jump
1608 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1609 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1610 CR.CaseBB->addSuccessor(Default);
1611 CR.CaseBB->addSuccessor(JumpTableBB);
1613 // Build a vector of destination BBs, corresponding to each target
1614 // of the jump table. If the value of the jump table slot corresponds to
1615 // a case statement, push the case's BB onto the vector, otherwise, push
1617 std::vector<MachineBasicBlock*> DestBBs;
1618 int64_t TEI = First;
1619 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1620 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1621 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1623 if ((Low <= TEI) && (TEI <= High)) {
1624 DestBBs.push_back(I->BB);
1628 DestBBs.push_back(Default);
1632 // Update successor info. Add one edge to each unique successor.
1633 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1634 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1635 E = DestBBs.end(); I != E; ++I) {
1636 if (!SuccsHandled[(*I)->getNumber()]) {
1637 SuccsHandled[(*I)->getNumber()] = true;
1638 JumpTableBB->addSuccessor(*I);
1642 // Create a jump table index for this jump table, or return an existing
1644 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1646 // Set the jump table information so that we can codegen it as a second
1647 // MachineBasicBlock
1648 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1649 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1650 (CR.CaseBB == CurMBB));
1651 if (CR.CaseBB == CurMBB)
1652 visitJumpTableHeader(JT, JTH);
1654 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1659 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1661 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1662 CaseRecVector& WorkList,
1664 MachineBasicBlock* Default) {
1665 // Get the MachineFunction which holds the current MBB. This is used when
1666 // inserting any additional MBBs necessary to represent the switch.
1667 MachineFunction *CurMF = CurMBB->getParent();
1669 // Figure out which block is immediately after the current one.
1670 MachineBasicBlock *NextBlock = 0;
1671 MachineFunction::iterator BBI = CR.CaseBB;
1673 if (++BBI != CurMBB->getParent()->end())
1676 Case& FrontCase = *CR.Range.first;
1677 Case& BackCase = *(CR.Range.second-1);
1678 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1680 // Size is the number of Cases represented by this range.
1681 unsigned Size = CR.Range.second - CR.Range.first;
1683 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1684 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1686 CaseItr Pivot = CR.Range.first + Size/2;
1688 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1689 // (heuristically) allow us to emit JumpTable's later.
1691 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1695 uint64_t LSize = FrontCase.size();
1696 uint64_t RSize = TSize-LSize;
1697 DOUT << "Selecting best pivot: \n"
1698 << "First: " << First << ", Last: " << Last <<"\n"
1699 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1700 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1702 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1703 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1704 assert((RBegin-LEnd>=1) && "Invalid case distance");
1705 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1706 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1707 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1708 // Should always split in some non-trivial place
1710 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1711 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1712 << "Metric: " << Metric << "\n";
1713 if (FMetric < Metric) {
1716 DOUT << "Current metric set to: " << FMetric << "\n";
1722 if (areJTsAllowed(TLI)) {
1723 // If our case is dense we *really* should handle it earlier!
1724 assert((FMetric > 0) && "Should handle dense range earlier!");
1726 Pivot = CR.Range.first + Size/2;
1729 CaseRange LHSR(CR.Range.first, Pivot);
1730 CaseRange RHSR(Pivot, CR.Range.second);
1731 Constant *C = Pivot->Low;
1732 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1734 // We know that we branch to the LHS if the Value being switched on is
1735 // less than the Pivot value, C. We use this to optimize our binary
1736 // tree a bit, by recognizing that if SV is greater than or equal to the
1737 // LHS's Case Value, and that Case Value is exactly one less than the
1738 // Pivot's Value, then we can branch directly to the LHS's Target,
1739 // rather than creating a leaf node for it.
1740 if ((LHSR.second - LHSR.first) == 1 &&
1741 LHSR.first->High == CR.GE &&
1742 cast<ConstantInt>(C)->getSExtValue() ==
1743 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1744 TrueBB = LHSR.first->BB;
1746 TrueBB = new MachineBasicBlock(LLVMBB);
1747 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1748 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1751 // Similar to the optimization above, if the Value being switched on is
1752 // known to be less than the Constant CR.LT, and the current Case Value
1753 // is CR.LT - 1, then we can branch directly to the target block for
1754 // the current Case Value, rather than emitting a RHS leaf node for it.
1755 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1756 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1757 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1758 FalseBB = RHSR.first->BB;
1760 FalseBB = new MachineBasicBlock(LLVMBB);
1761 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1762 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1765 // Create a CaseBlock record representing a conditional branch to
1766 // the LHS node if the value being switched on SV is less than C.
1767 // Otherwise, branch to LHS.
1768 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1769 TrueBB, FalseBB, CR.CaseBB);
1771 if (CR.CaseBB == CurMBB)
1772 visitSwitchCase(CB);
1774 SwitchCases.push_back(CB);
1779 /// handleBitTestsSwitchCase - if current case range has few destination and
1780 /// range span less, than machine word bitwidth, encode case range into series
1781 /// of masks and emit bit tests with these masks.
1782 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1783 CaseRecVector& WorkList,
1785 MachineBasicBlock* Default){
1786 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1788 Case& FrontCase = *CR.Range.first;
1789 Case& BackCase = *(CR.Range.second-1);
1791 // Get the MachineFunction which holds the current MBB. This is used when
1792 // inserting any additional MBBs necessary to represent the switch.
1793 MachineFunction *CurMF = CurMBB->getParent();
1795 unsigned numCmps = 0;
1796 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1798 // Single case counts one, case range - two.
1799 if (I->Low == I->High)
1805 // Count unique destinations
1806 SmallSet<MachineBasicBlock*, 4> Dests;
1807 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1808 Dests.insert(I->BB);
1809 if (Dests.size() > 3)
1810 // Don't bother the code below, if there are too much unique destinations
1813 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1814 << "Total number of comparisons: " << numCmps << "\n";
1816 // Compute span of values.
1817 Constant* minValue = FrontCase.Low;
1818 Constant* maxValue = BackCase.High;
1819 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1820 cast<ConstantInt>(minValue)->getSExtValue();
1821 DOUT << "Compare range: " << range << "\n"
1822 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1823 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1825 if (range>=IntPtrBits ||
1826 (!(Dests.size() == 1 && numCmps >= 3) &&
1827 !(Dests.size() == 2 && numCmps >= 5) &&
1828 !(Dests.size() >= 3 && numCmps >= 6)))
1831 DOUT << "Emitting bit tests\n";
1832 int64_t lowBound = 0;
1834 // Optimize the case where all the case values fit in a
1835 // word without having to subtract minValue. In this case,
1836 // we can optimize away the subtraction.
1837 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1838 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1839 range = cast<ConstantInt>(maxValue)->getSExtValue();
1841 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1844 CaseBitsVector CasesBits;
1845 unsigned i, count = 0;
1847 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1848 MachineBasicBlock* Dest = I->BB;
1849 for (i = 0; i < count; ++i)
1850 if (Dest == CasesBits[i].BB)
1854 assert((count < 3) && "Too much destinations to test!");
1855 CasesBits.push_back(CaseBits(0, Dest, 0));
1859 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1860 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1862 for (uint64_t j = lo; j <= hi; j++) {
1863 CasesBits[i].Mask |= 1ULL << j;
1864 CasesBits[i].Bits++;
1868 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1870 SelectionDAGISel::BitTestInfo BTC;
1872 // Figure out which block is immediately after the current one.
1873 MachineFunction::iterator BBI = CR.CaseBB;
1876 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1879 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1880 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1881 << ", BB: " << CasesBits[i].BB << "\n";
1883 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1884 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1885 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1890 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1891 -1U, (CR.CaseBB == CurMBB),
1892 CR.CaseBB, Default, BTC);
1894 if (CR.CaseBB == CurMBB)
1895 visitBitTestHeader(BTB);
1897 BitTestCases.push_back(BTB);
1903 // Clusterify - Transform simple list of Cases into list of CaseRange's
1904 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1905 const SwitchInst& SI) {
1906 unsigned numCmps = 0;
1908 // Start with "simple" cases
1909 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1910 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1911 Cases.push_back(Case(SI.getSuccessorValue(i),
1912 SI.getSuccessorValue(i),
1915 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1917 // Merge case into clusters
1918 if (Cases.size()>=2)
1919 // Must recompute end() each iteration because it may be
1920 // invalidated by erase if we hold on to it
1921 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1922 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1923 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1924 MachineBasicBlock* nextBB = J->BB;
1925 MachineBasicBlock* currentBB = I->BB;
1927 // If the two neighboring cases go to the same destination, merge them
1928 // into a single case.
1929 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1937 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1938 if (I->Low != I->High)
1939 // A range counts double, since it requires two compares.
1946 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1947 // Figure out which block is immediately after the current one.
1948 MachineBasicBlock *NextBlock = 0;
1949 MachineFunction::iterator BBI = CurMBB;
1951 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1953 // If there is only the default destination, branch to it if it is not the
1954 // next basic block. Otherwise, just fall through.
1955 if (SI.getNumOperands() == 2) {
1956 // Update machine-CFG edges.
1958 // If this is not a fall-through branch, emit the branch.
1959 if (Default != NextBlock)
1960 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1961 DAG.getBasicBlock(Default)));
1963 CurMBB->addSuccessor(Default);
1967 // If there are any non-default case statements, create a vector of Cases
1968 // representing each one, and sort the vector so that we can efficiently
1969 // create a binary search tree from them.
1971 unsigned numCmps = Clusterify(Cases, SI);
1972 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1973 << ". Total compares: " << numCmps << "\n";
1975 // Get the Value to be switched on and default basic blocks, which will be
1976 // inserted into CaseBlock records, representing basic blocks in the binary
1978 Value *SV = SI.getOperand(0);
1980 // Push the initial CaseRec onto the worklist
1981 CaseRecVector WorkList;
1982 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1984 while (!WorkList.empty()) {
1985 // Grab a record representing a case range to process off the worklist
1986 CaseRec CR = WorkList.back();
1987 WorkList.pop_back();
1989 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1992 // If the range has few cases (two or less) emit a series of specific
1994 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1997 // If the switch has more than 5 blocks, and at least 40% dense, and the
1998 // target supports indirect branches, then emit a jump table rather than
1999 // lowering the switch to a binary tree of conditional branches.
2000 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2003 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2004 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2005 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2010 void SelectionDAGLowering::visitSub(User &I) {
2011 // -0.0 - X --> fneg
2012 const Type *Ty = I.getType();
2013 if (isa<VectorType>(Ty)) {
2014 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2015 const VectorType *DestTy = cast<VectorType>(I.getType());
2016 const Type *ElTy = DestTy->getElementType();
2017 if (ElTy->isFloatingPoint()) {
2018 unsigned VL = DestTy->getNumElements();
2019 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2020 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2022 SDOperand Op2 = getValue(I.getOperand(1));
2023 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2029 if (Ty->isFloatingPoint()) {
2030 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2031 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2032 SDOperand Op2 = getValue(I.getOperand(1));
2033 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2038 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2041 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2042 SDOperand Op1 = getValue(I.getOperand(0));
2043 SDOperand Op2 = getValue(I.getOperand(1));
2045 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2048 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2049 SDOperand Op1 = getValue(I.getOperand(0));
2050 SDOperand Op2 = getValue(I.getOperand(1));
2052 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2053 MVT::getSizeInBits(Op2.getValueType()))
2054 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2055 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2056 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2058 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2061 void SelectionDAGLowering::visitICmp(User &I) {
2062 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2063 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2064 predicate = IC->getPredicate();
2065 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2066 predicate = ICmpInst::Predicate(IC->getPredicate());
2067 SDOperand Op1 = getValue(I.getOperand(0));
2068 SDOperand Op2 = getValue(I.getOperand(1));
2069 ISD::CondCode Opcode;
2070 switch (predicate) {
2071 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2072 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2073 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2074 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2075 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2076 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2077 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2078 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2079 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2080 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2082 assert(!"Invalid ICmp predicate value");
2083 Opcode = ISD::SETEQ;
2086 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2089 void SelectionDAGLowering::visitFCmp(User &I) {
2090 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2091 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2092 predicate = FC->getPredicate();
2093 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2094 predicate = FCmpInst::Predicate(FC->getPredicate());
2095 SDOperand Op1 = getValue(I.getOperand(0));
2096 SDOperand Op2 = getValue(I.getOperand(1));
2097 ISD::CondCode Condition, FOC, FPC;
2098 switch (predicate) {
2099 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2100 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2101 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2102 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2103 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2104 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2105 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2106 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2107 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2108 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2109 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2110 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2111 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2112 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2113 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2114 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2116 assert(!"Invalid FCmp predicate value");
2117 FOC = FPC = ISD::SETFALSE;
2120 if (FiniteOnlyFPMath())
2124 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2127 void SelectionDAGLowering::visitSelect(User &I) {
2128 SDOperand Cond = getValue(I.getOperand(0));
2129 SDOperand TrueVal = getValue(I.getOperand(1));
2130 SDOperand FalseVal = getValue(I.getOperand(2));
2131 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2132 TrueVal, FalseVal));
2136 void SelectionDAGLowering::visitTrunc(User &I) {
2137 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2138 SDOperand N = getValue(I.getOperand(0));
2139 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2140 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2143 void SelectionDAGLowering::visitZExt(User &I) {
2144 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2145 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2146 SDOperand N = getValue(I.getOperand(0));
2147 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2148 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2151 void SelectionDAGLowering::visitSExt(User &I) {
2152 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2153 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2154 SDOperand N = getValue(I.getOperand(0));
2155 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2156 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2159 void SelectionDAGLowering::visitFPTrunc(User &I) {
2160 // FPTrunc is never a no-op cast, no need to check
2161 SDOperand N = getValue(I.getOperand(0));
2162 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2163 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2166 void SelectionDAGLowering::visitFPExt(User &I){
2167 // FPTrunc is never a no-op cast, no need to check
2168 SDOperand N = getValue(I.getOperand(0));
2169 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2170 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2173 void SelectionDAGLowering::visitFPToUI(User &I) {
2174 // FPToUI is never a no-op cast, no need to check
2175 SDOperand N = getValue(I.getOperand(0));
2176 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2177 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2180 void SelectionDAGLowering::visitFPToSI(User &I) {
2181 // FPToSI is never a no-op cast, no need to check
2182 SDOperand N = getValue(I.getOperand(0));
2183 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2184 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2187 void SelectionDAGLowering::visitUIToFP(User &I) {
2188 // UIToFP is never a no-op cast, no need to check
2189 SDOperand N = getValue(I.getOperand(0));
2190 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2191 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2194 void SelectionDAGLowering::visitSIToFP(User &I){
2195 // UIToFP is never a no-op cast, no need to check
2196 SDOperand N = getValue(I.getOperand(0));
2197 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2198 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2201 void SelectionDAGLowering::visitPtrToInt(User &I) {
2202 // What to do depends on the size of the integer and the size of the pointer.
2203 // We can either truncate, zero extend, or no-op, accordingly.
2204 SDOperand N = getValue(I.getOperand(0));
2205 MVT::ValueType SrcVT = N.getValueType();
2206 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2208 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2209 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2211 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2212 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2213 setValue(&I, Result);
2216 void SelectionDAGLowering::visitIntToPtr(User &I) {
2217 // What to do depends on the size of the integer and the size of the pointer.
2218 // We can either truncate, zero extend, or no-op, accordingly.
2219 SDOperand N = getValue(I.getOperand(0));
2220 MVT::ValueType SrcVT = N.getValueType();
2221 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2222 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2223 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2225 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2226 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2229 void SelectionDAGLowering::visitBitCast(User &I) {
2230 SDOperand N = getValue(I.getOperand(0));
2231 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2233 // BitCast assures us that source and destination are the same size so this
2234 // is either a BIT_CONVERT or a no-op.
2235 if (DestVT != N.getValueType())
2236 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2238 setValue(&I, N); // noop cast.
2241 void SelectionDAGLowering::visitInsertElement(User &I) {
2242 SDOperand InVec = getValue(I.getOperand(0));
2243 SDOperand InVal = getValue(I.getOperand(1));
2244 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2245 getValue(I.getOperand(2)));
2247 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2248 TLI.getValueType(I.getType()),
2249 InVec, InVal, InIdx));
2252 void SelectionDAGLowering::visitExtractElement(User &I) {
2253 SDOperand InVec = getValue(I.getOperand(0));
2254 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2255 getValue(I.getOperand(1)));
2256 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2257 TLI.getValueType(I.getType()), InVec, InIdx));
2260 void SelectionDAGLowering::visitShuffleVector(User &I) {
2261 SDOperand V1 = getValue(I.getOperand(0));
2262 SDOperand V2 = getValue(I.getOperand(1));
2263 SDOperand Mask = getValue(I.getOperand(2));
2265 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2266 TLI.getValueType(I.getType()),
2271 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2272 SDOperand N = getValue(I.getOperand(0));
2273 const Type *Ty = I.getOperand(0)->getType();
2275 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2278 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2279 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2282 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2283 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2284 DAG.getIntPtrConstant(Offset));
2286 Ty = StTy->getElementType(Field);
2288 Ty = cast<SequentialType>(Ty)->getElementType();
2290 // If this is a constant subscript, handle it quickly.
2291 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2292 if (CI->getZExtValue() == 0) continue;
2294 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2295 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2296 DAG.getIntPtrConstant(Offs));
2300 // N = N + Idx * ElementSize;
2301 uint64_t ElementSize = TD->getABITypeSize(Ty);
2302 SDOperand IdxN = getValue(Idx);
2304 // If the index is smaller or larger than intptr_t, truncate or extend
2306 if (IdxN.getValueType() < N.getValueType()) {
2307 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2308 } else if (IdxN.getValueType() > N.getValueType())
2309 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2311 // If this is a multiply by a power of two, turn it into a shl
2312 // immediately. This is a very common case.
2313 if (isPowerOf2_64(ElementSize)) {
2314 unsigned Amt = Log2_64(ElementSize);
2315 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2316 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2317 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2321 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2322 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2323 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2329 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2330 // If this is a fixed sized alloca in the entry block of the function,
2331 // allocate it statically on the stack.
2332 if (FuncInfo.StaticAllocaMap.count(&I))
2333 return; // getValue will auto-populate this.
2335 const Type *Ty = I.getAllocatedType();
2336 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2338 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2341 SDOperand AllocSize = getValue(I.getArraySize());
2342 MVT::ValueType IntPtr = TLI.getPointerTy();
2343 if (IntPtr < AllocSize.getValueType())
2344 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2345 else if (IntPtr > AllocSize.getValueType())
2346 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2348 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2349 DAG.getIntPtrConstant(TySize));
2351 // Handle alignment. If the requested alignment is less than or equal to
2352 // the stack alignment, ignore it. If the size is greater than or equal to
2353 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2354 unsigned StackAlign =
2355 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2356 if (Align <= StackAlign)
2359 // Round the size of the allocation up to the stack alignment size
2360 // by add SA-1 to the size.
2361 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2362 DAG.getIntPtrConstant(StackAlign-1));
2363 // Mask out the low bits for alignment purposes.
2364 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2365 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2367 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2368 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2370 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2372 DAG.setRoot(DSA.getValue(1));
2374 // Inform the Frame Information that we have just allocated a variable-sized
2376 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2379 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2380 SDOperand Ptr = getValue(I.getOperand(0));
2386 // Do not serialize non-volatile loads against each other.
2387 Root = DAG.getRoot();
2390 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2391 Root, I.isVolatile(), I.getAlignment()));
2394 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2395 const Value *SV, SDOperand Root,
2397 unsigned Alignment) {
2399 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2400 isVolatile, Alignment);
2403 DAG.setRoot(L.getValue(1));
2405 PendingLoads.push_back(L.getValue(1));
2411 void SelectionDAGLowering::visitStore(StoreInst &I) {
2412 Value *SrcV = I.getOperand(0);
2413 SDOperand Src = getValue(SrcV);
2414 SDOperand Ptr = getValue(I.getOperand(1));
2415 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2416 I.isVolatile(), I.getAlignment()));
2419 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2421 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2422 unsigned Intrinsic) {
2423 bool HasChain = !I.doesNotAccessMemory();
2424 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2426 // Build the operand list.
2427 SmallVector<SDOperand, 8> Ops;
2428 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2430 // We don't need to serialize loads against other loads.
2431 Ops.push_back(DAG.getRoot());
2433 Ops.push_back(getRoot());
2437 // Add the intrinsic ID as an integer operand.
2438 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2440 // Add all operands of the call to the operand list.
2441 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2442 SDOperand Op = getValue(I.getOperand(i));
2443 assert(TLI.isTypeLegal(Op.getValueType()) &&
2444 "Intrinsic uses a non-legal type?");
2448 std::vector<MVT::ValueType> VTs;
2449 if (I.getType() != Type::VoidTy) {
2450 MVT::ValueType VT = TLI.getValueType(I.getType());
2451 if (MVT::isVector(VT)) {
2452 const VectorType *DestTy = cast<VectorType>(I.getType());
2453 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2455 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2456 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2459 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2463 VTs.push_back(MVT::Other);
2465 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2470 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2471 &Ops[0], Ops.size());
2472 else if (I.getType() != Type::VoidTy)
2473 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2474 &Ops[0], Ops.size());
2476 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2477 &Ops[0], Ops.size());
2480 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2482 PendingLoads.push_back(Chain);
2486 if (I.getType() != Type::VoidTy) {
2487 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2488 MVT::ValueType VT = TLI.getValueType(PTy);
2489 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2491 setValue(&I, Result);
2495 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2496 static GlobalVariable *ExtractTypeInfo (Value *V) {
2497 V = IntrinsicInst::StripPointerCasts(V);
2498 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2499 assert (GV || isa<ConstantPointerNull>(V) &&
2500 "TypeInfo must be a global variable or NULL");
2504 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2505 /// call, and add them to the specified machine basic block.
2506 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2507 MachineBasicBlock *MBB) {
2508 // Inform the MachineModuleInfo of the personality for this landing pad.
2509 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2510 assert(CE->getOpcode() == Instruction::BitCast &&
2511 isa<Function>(CE->getOperand(0)) &&
2512 "Personality should be a function");
2513 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2515 // Gather all the type infos for this landing pad and pass them along to
2516 // MachineModuleInfo.
2517 std::vector<GlobalVariable *> TyInfo;
2518 unsigned N = I.getNumOperands();
2520 for (unsigned i = N - 1; i > 2; --i) {
2521 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2522 unsigned FilterLength = CI->getZExtValue();
2523 unsigned FirstCatch = i + FilterLength + !FilterLength;
2524 assert (FirstCatch <= N && "Invalid filter length");
2526 if (FirstCatch < N) {
2527 TyInfo.reserve(N - FirstCatch);
2528 for (unsigned j = FirstCatch; j < N; ++j)
2529 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2530 MMI->addCatchTypeInfo(MBB, TyInfo);
2534 if (!FilterLength) {
2536 MMI->addCleanup(MBB);
2539 TyInfo.reserve(FilterLength - 1);
2540 for (unsigned j = i + 1; j < FirstCatch; ++j)
2541 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2542 MMI->addFilterTypeInfo(MBB, TyInfo);
2551 TyInfo.reserve(N - 3);
2552 for (unsigned j = 3; j < N; ++j)
2553 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2554 MMI->addCatchTypeInfo(MBB, TyInfo);
2558 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2559 /// we want to emit this as a call to a named external function, return the name
2560 /// otherwise lower it and return null.
2562 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2563 switch (Intrinsic) {
2565 // By default, turn this into a target intrinsic node.
2566 visitTargetIntrinsic(I, Intrinsic);
2568 case Intrinsic::vastart: visitVAStart(I); return 0;
2569 case Intrinsic::vaend: visitVAEnd(I); return 0;
2570 case Intrinsic::vacopy: visitVACopy(I); return 0;
2571 case Intrinsic::returnaddress:
2572 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2573 getValue(I.getOperand(1))));
2575 case Intrinsic::frameaddress:
2576 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2577 getValue(I.getOperand(1))));
2579 case Intrinsic::setjmp:
2580 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2582 case Intrinsic::longjmp:
2583 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2585 case Intrinsic::memcpy_i32:
2586 case Intrinsic::memcpy_i64:
2587 visitMemIntrinsic(I, ISD::MEMCPY);
2589 case Intrinsic::memset_i32:
2590 case Intrinsic::memset_i64:
2591 visitMemIntrinsic(I, ISD::MEMSET);
2593 case Intrinsic::memmove_i32:
2594 case Intrinsic::memmove_i64:
2595 visitMemIntrinsic(I, ISD::MEMMOVE);
2598 case Intrinsic::dbg_stoppoint: {
2599 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2600 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2601 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2605 Ops[1] = getValue(SPI.getLineValue());
2606 Ops[2] = getValue(SPI.getColumnValue());
2608 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2609 assert(DD && "Not a debug information descriptor");
2610 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2612 Ops[3] = DAG.getString(CompileUnit->getFileName());
2613 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2615 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2620 case Intrinsic::dbg_region_start: {
2621 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2622 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2623 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2624 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2625 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2626 DAG.getConstant(LabelID, MVT::i32),
2627 DAG.getConstant(0, MVT::i32)));
2632 case Intrinsic::dbg_region_end: {
2633 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2634 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2635 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2636 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2637 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2638 DAG.getConstant(LabelID, MVT::i32),
2639 DAG.getConstant(0, MVT::i32)));
2644 case Intrinsic::dbg_func_start: {
2645 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2647 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2648 Value *SP = FSI.getSubprogram();
2649 if (SP && MMI->Verify(SP)) {
2650 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
2651 // what (most?) gdb expects.
2652 DebugInfoDesc *DD = MMI->getDescFor(SP);
2653 assert(DD && "Not a debug information descriptor");
2654 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
2655 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
2656 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
2657 CompileUnit->getFileName());
2658 // Record the source line but does create a label. It will be emitted
2659 // at asm emission time.
2660 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
2665 case Intrinsic::dbg_declare: {
2666 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2667 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2668 Value *Variable = DI.getVariable();
2669 if (MMI && Variable && MMI->Verify(Variable))
2670 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
2671 getValue(DI.getAddress()), getValue(Variable)));
2675 case Intrinsic::eh_exception: {
2676 if (ExceptionHandling) {
2677 if (!CurMBB->isLandingPad()) {
2678 // FIXME: Mark exception register as live in. Hack for PR1508.
2679 unsigned Reg = TLI.getExceptionAddressRegister();
2680 if (Reg) CurMBB->addLiveIn(Reg);
2682 // Insert the EXCEPTIONADDR instruction.
2683 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2685 Ops[0] = DAG.getRoot();
2686 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2688 DAG.setRoot(Op.getValue(1));
2690 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2695 case Intrinsic::eh_selector_i32:
2696 case Intrinsic::eh_selector_i64: {
2697 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2698 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2699 MVT::i32 : MVT::i64);
2701 if (ExceptionHandling && MMI) {
2702 if (CurMBB->isLandingPad())
2703 addCatchInfo(I, MMI, CurMBB);
2706 FuncInfo.CatchInfoLost.insert(&I);
2708 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2709 unsigned Reg = TLI.getExceptionSelectorRegister();
2710 if (Reg) CurMBB->addLiveIn(Reg);
2713 // Insert the EHSELECTION instruction.
2714 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2716 Ops[0] = getValue(I.getOperand(1));
2718 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2720 DAG.setRoot(Op.getValue(1));
2722 setValue(&I, DAG.getConstant(0, VT));
2728 case Intrinsic::eh_typeid_for_i32:
2729 case Intrinsic::eh_typeid_for_i64: {
2730 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2731 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2732 MVT::i32 : MVT::i64);
2735 // Find the type id for the given typeinfo.
2736 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2738 unsigned TypeID = MMI->getTypeIDFor(GV);
2739 setValue(&I, DAG.getConstant(TypeID, VT));
2741 // Return something different to eh_selector.
2742 setValue(&I, DAG.getConstant(1, VT));
2748 case Intrinsic::eh_return: {
2749 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2751 if (MMI && ExceptionHandling) {
2752 MMI->setCallsEHReturn(true);
2753 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2756 getValue(I.getOperand(1)),
2757 getValue(I.getOperand(2))));
2759 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2765 case Intrinsic::eh_unwind_init: {
2766 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2767 MMI->setCallsUnwindInit(true);
2773 case Intrinsic::eh_dwarf_cfa: {
2774 if (ExceptionHandling) {
2775 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2777 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2778 CfaArg = DAG.getNode(ISD::TRUNCATE,
2779 TLI.getPointerTy(), getValue(I.getOperand(1)));
2781 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2782 TLI.getPointerTy(), getValue(I.getOperand(1)));
2784 SDOperand Offset = DAG.getNode(ISD::ADD,
2786 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2787 TLI.getPointerTy()),
2789 setValue(&I, DAG.getNode(ISD::ADD,
2791 DAG.getNode(ISD::FRAMEADDR,
2794 TLI.getPointerTy())),
2797 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2803 case Intrinsic::sqrt:
2804 setValue(&I, DAG.getNode(ISD::FSQRT,
2805 getValue(I.getOperand(1)).getValueType(),
2806 getValue(I.getOperand(1))));
2808 case Intrinsic::powi:
2809 setValue(&I, DAG.getNode(ISD::FPOWI,
2810 getValue(I.getOperand(1)).getValueType(),
2811 getValue(I.getOperand(1)),
2812 getValue(I.getOperand(2))));
2814 case Intrinsic::sin:
2815 setValue(&I, DAG.getNode(ISD::FSIN,
2816 getValue(I.getOperand(1)).getValueType(),
2817 getValue(I.getOperand(1))));
2819 case Intrinsic::cos:
2820 setValue(&I, DAG.getNode(ISD::FCOS,
2821 getValue(I.getOperand(1)).getValueType(),
2822 getValue(I.getOperand(1))));
2824 case Intrinsic::pow:
2825 setValue(&I, DAG.getNode(ISD::FPOW,
2826 getValue(I.getOperand(1)).getValueType(),
2827 getValue(I.getOperand(1)),
2828 getValue(I.getOperand(2))));
2830 case Intrinsic::pcmarker: {
2831 SDOperand Tmp = getValue(I.getOperand(1));
2832 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2835 case Intrinsic::readcyclecounter: {
2836 SDOperand Op = getRoot();
2837 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2838 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2841 DAG.setRoot(Tmp.getValue(1));
2844 case Intrinsic::part_select: {
2845 // Currently not implemented: just abort
2846 assert(0 && "part_select intrinsic not implemented");
2849 case Intrinsic::part_set: {
2850 // Currently not implemented: just abort
2851 assert(0 && "part_set intrinsic not implemented");
2854 case Intrinsic::bswap:
2855 setValue(&I, DAG.getNode(ISD::BSWAP,
2856 getValue(I.getOperand(1)).getValueType(),
2857 getValue(I.getOperand(1))));
2859 case Intrinsic::cttz: {
2860 SDOperand Arg = getValue(I.getOperand(1));
2861 MVT::ValueType Ty = Arg.getValueType();
2862 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2863 setValue(&I, result);
2866 case Intrinsic::ctlz: {
2867 SDOperand Arg = getValue(I.getOperand(1));
2868 MVT::ValueType Ty = Arg.getValueType();
2869 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2870 setValue(&I, result);
2873 case Intrinsic::ctpop: {
2874 SDOperand Arg = getValue(I.getOperand(1));
2875 MVT::ValueType Ty = Arg.getValueType();
2876 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2877 setValue(&I, result);
2880 case Intrinsic::stacksave: {
2881 SDOperand Op = getRoot();
2882 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2883 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2885 DAG.setRoot(Tmp.getValue(1));
2888 case Intrinsic::stackrestore: {
2889 SDOperand Tmp = getValue(I.getOperand(1));
2890 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2893 case Intrinsic::prefetch:
2894 // FIXME: Currently discarding prefetches.
2897 case Intrinsic::var_annotation:
2898 // Discard annotate attributes
2901 case Intrinsic::init_trampoline: {
2903 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
2907 Ops[1] = getValue(I.getOperand(1));
2908 Ops[2] = getValue(I.getOperand(2));
2909 Ops[3] = getValue(I.getOperand(3));
2910 Ops[4] = DAG.getSrcValue(I.getOperand(1));
2911 Ops[5] = DAG.getSrcValue(F);
2913 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
2914 DAG.getNodeValueTypes(TLI.getPointerTy(),
2919 DAG.setRoot(Tmp.getValue(1));
2923 case Intrinsic::gcroot:
2925 Value *Alloca = I.getOperand(1);
2926 Constant *TypeMap = cast<Constant>(I.getOperand(2));
2928 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
2929 GCI->addStackRoot(FI->getIndex(), TypeMap);
2933 case Intrinsic::gcread:
2934 case Intrinsic::gcwrite:
2935 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
2938 case Intrinsic::flt_rounds: {
2939 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
2943 case Intrinsic::trap: {
2944 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
2951 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
2953 MachineBasicBlock *LandingPad) {
2954 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2955 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2956 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2957 unsigned BeginLabel = 0, EndLabel = 0;
2959 TargetLowering::ArgListTy Args;
2960 TargetLowering::ArgListEntry Entry;
2961 Args.reserve(CS.arg_size());
2962 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2964 SDOperand ArgNode = getValue(*i);
2965 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
2967 unsigned attrInd = i - CS.arg_begin() + 1;
2968 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
2969 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
2970 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
2971 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
2972 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
2973 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
2974 Args.push_back(Entry);
2977 bool MarkTryRange = LandingPad ||
2978 // C++ requires special handling of 'nounwind' calls.
2979 (CS.doesNotThrow());
2981 if (MarkTryRange && ExceptionHandling && MMI) {
2982 // Insert a label before the invoke call to mark the try range. This can be
2983 // used to detect deletion of the invoke via the MachineModuleInfo.
2984 BeginLabel = MMI->NextLabelID();
2985 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2986 DAG.getConstant(BeginLabel, MVT::i32),
2987 DAG.getConstant(1, MVT::i32)));
2990 std::pair<SDOperand,SDOperand> Result =
2991 TLI.LowerCallTo(getRoot(), CS.getType(),
2992 CS.paramHasAttr(0, ParamAttr::SExt),
2993 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
2995 if (CS.getType() != Type::VoidTy)
2996 setValue(CS.getInstruction(), Result.first);
2997 DAG.setRoot(Result.second);
2999 if (MarkTryRange && ExceptionHandling && MMI) {
3000 // Insert a label at the end of the invoke call to mark the try range. This
3001 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3002 EndLabel = MMI->NextLabelID();
3003 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3004 DAG.getConstant(EndLabel, MVT::i32),
3005 DAG.getConstant(1, MVT::i32)));
3007 // Inform MachineModuleInfo of range.
3008 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3013 void SelectionDAGLowering::visitCall(CallInst &I) {
3014 const char *RenameFn = 0;
3015 if (Function *F = I.getCalledFunction()) {
3016 if (F->isDeclaration()) {
3017 if (unsigned IID = F->getIntrinsicID()) {
3018 RenameFn = visitIntrinsicCall(I, IID);
3024 // Check for well-known libc/libm calls. If the function is internal, it
3025 // can't be a library call.
3026 unsigned NameLen = F->getNameLen();
3027 if (!F->hasInternalLinkage() && NameLen) {
3028 const char *NameStr = F->getNameStart();
3029 if (NameStr[0] == 'c' &&
3030 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3031 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3032 if (I.getNumOperands() == 3 && // Basic sanity checks.
3033 I.getOperand(1)->getType()->isFloatingPoint() &&
3034 I.getType() == I.getOperand(1)->getType() &&
3035 I.getType() == I.getOperand(2)->getType()) {
3036 SDOperand LHS = getValue(I.getOperand(1));
3037 SDOperand RHS = getValue(I.getOperand(2));
3038 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3042 } else if (NameStr[0] == 'f' &&
3043 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3044 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3045 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3046 if (I.getNumOperands() == 2 && // Basic sanity checks.
3047 I.getOperand(1)->getType()->isFloatingPoint() &&
3048 I.getType() == I.getOperand(1)->getType()) {
3049 SDOperand Tmp = getValue(I.getOperand(1));
3050 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3053 } else if (NameStr[0] == 's' &&
3054 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3055 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3056 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3057 if (I.getNumOperands() == 2 && // Basic sanity checks.
3058 I.getOperand(1)->getType()->isFloatingPoint() &&
3059 I.getType() == I.getOperand(1)->getType()) {
3060 SDOperand Tmp = getValue(I.getOperand(1));
3061 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3064 } else if (NameStr[0] == 'c' &&
3065 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3066 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3067 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3068 if (I.getNumOperands() == 2 && // Basic sanity checks.
3069 I.getOperand(1)->getType()->isFloatingPoint() &&
3070 I.getType() == I.getOperand(1)->getType()) {
3071 SDOperand Tmp = getValue(I.getOperand(1));
3072 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3077 } else if (isa<InlineAsm>(I.getOperand(0))) {
3084 Callee = getValue(I.getOperand(0));
3086 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3088 LowerCallTo(&I, Callee, I.isTailCall());
3092 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3093 /// this value and returns the result as a ValueVT value. This uses
3094 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3095 /// If the Flag pointer is NULL, no flag is used.
3096 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3097 SDOperand &Chain, SDOperand *Flag)const{
3098 // Copy the legal parts from the registers.
3099 unsigned NumParts = Regs.size();
3100 SmallVector<SDOperand, 8> Parts(NumParts);
3101 for (unsigned i = 0; i != NumParts; ++i) {
3102 SDOperand Part = Flag ?
3103 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3104 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3105 Chain = Part.getValue(1);
3107 *Flag = Part.getValue(2);
3111 // Assemble the legal parts into the final value.
3112 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3115 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3116 /// specified value into the registers specified by this object. This uses
3117 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3118 /// If the Flag pointer is NULL, no flag is used.
3119 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3120 SDOperand &Chain, SDOperand *Flag) const {
3121 // Get the list of the values's legal parts.
3122 unsigned NumParts = Regs.size();
3123 SmallVector<SDOperand, 8> Parts(NumParts);
3124 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3126 // Copy the parts into the registers.
3127 for (unsigned i = 0; i != NumParts; ++i) {
3128 SDOperand Part = Flag ?
3129 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3130 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3131 Chain = Part.getValue(0);
3133 *Flag = Part.getValue(1);
3137 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3138 /// operand list. This adds the code marker and includes the number of
3139 /// values added into it.
3140 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3141 std::vector<SDOperand> &Ops) const {
3142 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3143 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3144 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3145 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3148 /// isAllocatableRegister - If the specified register is safe to allocate,
3149 /// i.e. it isn't a stack pointer or some other special register, return the
3150 /// register class for the register. Otherwise, return null.
3151 static const TargetRegisterClass *
3152 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3153 const TargetLowering &TLI,
3154 const TargetRegisterInfo *TRI) {
3155 MVT::ValueType FoundVT = MVT::Other;
3156 const TargetRegisterClass *FoundRC = 0;
3157 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3158 E = TRI->regclass_end(); RCI != E; ++RCI) {
3159 MVT::ValueType ThisVT = MVT::Other;
3161 const TargetRegisterClass *RC = *RCI;
3162 // If none of the the value types for this register class are valid, we
3163 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3164 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3166 if (TLI.isTypeLegal(*I)) {
3167 // If we have already found this register in a different register class,
3168 // choose the one with the largest VT specified. For example, on
3169 // PowerPC, we favor f64 register classes over f32.
3170 if (FoundVT == MVT::Other ||
3171 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3178 if (ThisVT == MVT::Other) continue;
3180 // NOTE: This isn't ideal. In particular, this might allocate the
3181 // frame pointer in functions that need it (due to them not being taken
3182 // out of allocation, because a variable sized allocation hasn't been seen
3183 // yet). This is a slight code pessimization, but should still work.
3184 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3185 E = RC->allocation_order_end(MF); I != E; ++I)
3187 // We found a matching register class. Keep looking at others in case
3188 // we find one with larger registers that this physreg is also in.
3199 /// AsmOperandInfo - This contains information for each constraint that we are
3201 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3202 /// ConstraintCode - This contains the actual string for the code, like "m".
3203 std::string ConstraintCode;
3205 /// ConstraintType - Information about the constraint code, e.g. Register,
3206 /// RegisterClass, Memory, Other, Unknown.
3207 TargetLowering::ConstraintType ConstraintType;
3209 /// CallOperand/CallOperandval - If this is the result output operand or a
3210 /// clobber, this is null, otherwise it is the incoming operand to the
3211 /// CallInst. This gets modified as the asm is processed.
3212 SDOperand CallOperand;
3213 Value *CallOperandVal;
3215 /// ConstraintVT - The ValueType for the operand value.
3216 MVT::ValueType ConstraintVT;
3218 /// AssignedRegs - If this is a register or register class operand, this
3219 /// contains the set of register corresponding to the operand.
3220 RegsForValue AssignedRegs;
3222 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3223 : InlineAsm::ConstraintInfo(info),
3224 ConstraintType(TargetLowering::C_Unknown),
3225 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3228 void ComputeConstraintToUse(const TargetLowering &TLI);
3230 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3231 /// busy in OutputRegs/InputRegs.
3232 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3233 std::set<unsigned> &OutputRegs,
3234 std::set<unsigned> &InputRegs) const {
3236 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3238 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3241 } // end anon namespace.
3243 /// getConstraintGenerality - Return an integer indicating how general CT is.
3244 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3246 default: assert(0 && "Unknown constraint type!");
3247 case TargetLowering::C_Other:
3248 case TargetLowering::C_Unknown:
3250 case TargetLowering::C_Register:
3252 case TargetLowering::C_RegisterClass:
3254 case TargetLowering::C_Memory:
3259 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3260 assert(!Codes.empty() && "Must have at least one constraint");
3262 std::string *Current = &Codes[0];
3263 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3264 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3265 ConstraintCode = *Current;
3266 ConstraintType = CurType;
3268 unsigned CurGenerality = getConstraintGenerality(CurType);
3270 // If we have multiple constraints, try to pick the most general one ahead
3271 // of time. This isn't a wonderful solution, but handles common cases.
3272 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3273 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3274 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3275 if (ThisGenerality > CurGenerality) {
3276 // This constraint letter is more general than the previous one,
3279 Current = &Codes[j];
3280 CurGenerality = ThisGenerality;
3284 ConstraintCode = *Current;
3285 ConstraintType = CurType;
3288 if (ConstraintCode == "X") {
3289 if (isa<BasicBlock>(CallOperandVal) || isa<ConstantInt>(CallOperandVal))
3291 // This matches anything. Labels and constants we handle elsewhere
3292 // ('X' is the only thing that matches labels). Otherwise, try to
3293 // resolve it to something we know about by looking at the actual
3296 TLI.lowerXConstraint(ConstraintVT, s);
3299 ConstraintType = TLI.getConstraintType(ConstraintCode);
3305 void SelectionDAGLowering::
3306 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3307 std::set<unsigned> &OutputRegs,
3308 std::set<unsigned> &InputRegs) {
3309 // Compute whether this value requires an input register, an output register,
3311 bool isOutReg = false;
3312 bool isInReg = false;
3313 switch (OpInfo.Type) {
3314 case InlineAsm::isOutput:
3317 // If this is an early-clobber output, or if there is an input
3318 // constraint that matches this, we need to reserve the input register
3319 // so no other inputs allocate to it.
3320 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3322 case InlineAsm::isInput:
3326 case InlineAsm::isClobber:
3333 MachineFunction &MF = DAG.getMachineFunction();
3334 std::vector<unsigned> Regs;
3336 // If this is a constraint for a single physreg, or a constraint for a
3337 // register class, find it.
3338 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3339 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3340 OpInfo.ConstraintVT);
3342 unsigned NumRegs = 1;
3343 if (OpInfo.ConstraintVT != MVT::Other)
3344 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3345 MVT::ValueType RegVT;
3346 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3349 // If this is a constraint for a specific physical register, like {r17},
3351 if (PhysReg.first) {
3352 if (OpInfo.ConstraintVT == MVT::Other)
3353 ValueVT = *PhysReg.second->vt_begin();
3355 // Get the actual register value type. This is important, because the user
3356 // may have asked for (e.g.) the AX register in i32 type. We need to
3357 // remember that AX is actually i16 to get the right extension.
3358 RegVT = *PhysReg.second->vt_begin();
3360 // This is a explicit reference to a physical register.
3361 Regs.push_back(PhysReg.first);
3363 // If this is an expanded reference, add the rest of the regs to Regs.
3365 TargetRegisterClass::iterator I = PhysReg.second->begin();
3366 TargetRegisterClass::iterator E = PhysReg.second->end();
3367 for (; *I != PhysReg.first; ++I)
3368 assert(I != E && "Didn't find reg!");
3370 // Already added the first reg.
3372 for (; NumRegs; --NumRegs, ++I) {
3373 assert(I != E && "Ran out of registers to allocate!");
3377 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3378 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3382 // Otherwise, if this was a reference to an LLVM register class, create vregs
3383 // for this reference.
3384 std::vector<unsigned> RegClassRegs;
3385 const TargetRegisterClass *RC = PhysReg.second;
3387 // If this is an early clobber or tied register, our regalloc doesn't know
3388 // how to maintain the constraint. If it isn't, go ahead and create vreg
3389 // and let the regalloc do the right thing.
3390 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3391 // If there is some other early clobber and this is an input register,
3392 // then we are forced to pre-allocate the input reg so it doesn't
3393 // conflict with the earlyclobber.
3394 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3395 RegVT = *PhysReg.second->vt_begin();
3397 if (OpInfo.ConstraintVT == MVT::Other)
3400 // Create the appropriate number of virtual registers.
3401 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3402 for (; NumRegs; --NumRegs)
3403 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3405 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3406 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3410 // Otherwise, we can't allocate it. Let the code below figure out how to
3411 // maintain these constraints.
3412 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3415 // This is a reference to a register class that doesn't directly correspond
3416 // to an LLVM register class. Allocate NumRegs consecutive, available,
3417 // registers from the class.
3418 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3419 OpInfo.ConstraintVT);
3422 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3423 unsigned NumAllocated = 0;
3424 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3425 unsigned Reg = RegClassRegs[i];
3426 // See if this register is available.
3427 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3428 (isInReg && InputRegs.count(Reg))) { // Already used.
3429 // Make sure we find consecutive registers.
3434 // Check to see if this register is allocatable (i.e. don't give out the
3437 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
3438 if (!RC) { // Couldn't allocate this register.
3439 // Reset NumAllocated to make sure we return consecutive registers.
3445 // Okay, this register is good, we can use it.
3448 // If we allocated enough consecutive registers, succeed.
3449 if (NumAllocated == NumRegs) {
3450 unsigned RegStart = (i-NumAllocated)+1;
3451 unsigned RegEnd = i+1;
3452 // Mark all of the allocated registers used.
3453 for (unsigned i = RegStart; i != RegEnd; ++i)
3454 Regs.push_back(RegClassRegs[i]);
3456 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3457 OpInfo.ConstraintVT);
3458 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3463 // Otherwise, we couldn't allocate enough registers for this.
3468 /// visitInlineAsm - Handle a call to an InlineAsm object.
3470 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3471 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3473 /// ConstraintOperands - Information about all of the constraints.
3474 std::vector<AsmOperandInfo> ConstraintOperands;
3476 SDOperand Chain = getRoot();
3479 std::set<unsigned> OutputRegs, InputRegs;
3481 // Do a prepass over the constraints, canonicalizing them, and building up the
3482 // ConstraintOperands list.
3483 std::vector<InlineAsm::ConstraintInfo>
3484 ConstraintInfos = IA->ParseConstraints();
3486 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3487 // constraint. If so, we can't let the register allocator allocate any input
3488 // registers, because it will not know to avoid the earlyclobbered output reg.
3489 bool SawEarlyClobber = false;
3491 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3492 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3493 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3494 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3496 MVT::ValueType OpVT = MVT::Other;
3498 // Compute the value type for each operand.
3499 switch (OpInfo.Type) {
3500 case InlineAsm::isOutput:
3501 if (!OpInfo.isIndirect) {
3502 // The return value of the call is this value. As such, there is no
3503 // corresponding argument.
3504 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3505 OpVT = TLI.getValueType(CS.getType());
3507 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3510 case InlineAsm::isInput:
3511 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3513 case InlineAsm::isClobber:
3518 // If this is an input or an indirect output, process the call argument.
3519 // BasicBlocks are labels, currently appearing only in asm's.
3520 if (OpInfo.CallOperandVal) {
3521 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3522 OpInfo.CallOperand =
3523 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(
3524 OpInfo.CallOperandVal)]);
3526 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3527 const Type *OpTy = OpInfo.CallOperandVal->getType();
3528 // If this is an indirect operand, the operand is a pointer to the
3530 if (OpInfo.isIndirect)
3531 OpTy = cast<PointerType>(OpTy)->getElementType();
3533 // If OpTy is not a first-class value, it may be a struct/union that we
3534 // can tile with integers.
3535 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3536 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3544 OpTy = IntegerType::get(BitSize);
3549 OpVT = TLI.getValueType(OpTy, true);
3553 OpInfo.ConstraintVT = OpVT;
3555 // Compute the constraint code and ConstraintType to use.
3556 OpInfo.ComputeConstraintToUse(TLI);
3558 // Keep track of whether we see an earlyclobber.
3559 SawEarlyClobber |= OpInfo.isEarlyClobber;
3561 // If this is a memory input, and if the operand is not indirect, do what we
3562 // need to to provide an address for the memory input.
3563 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3564 !OpInfo.isIndirect) {
3565 assert(OpInfo.Type == InlineAsm::isInput &&
3566 "Can only indirectify direct input operands!");
3568 // Memory operands really want the address of the value. If we don't have
3569 // an indirect input, put it in the constpool if we can, otherwise spill
3570 // it to a stack slot.
3572 // If the operand is a float, integer, or vector constant, spill to a
3573 // constant pool entry to get its address.
3574 Value *OpVal = OpInfo.CallOperandVal;
3575 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3576 isa<ConstantVector>(OpVal)) {
3577 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3578 TLI.getPointerTy());
3580 // Otherwise, create a stack slot and emit a store to it before the
3582 const Type *Ty = OpVal->getType();
3583 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3584 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3585 MachineFunction &MF = DAG.getMachineFunction();
3586 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3587 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3588 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3589 OpInfo.CallOperand = StackSlot;
3592 // There is no longer a Value* corresponding to this operand.
3593 OpInfo.CallOperandVal = 0;
3594 // It is now an indirect operand.
3595 OpInfo.isIndirect = true;
3598 // If this constraint is for a specific register, allocate it before
3600 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3601 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3603 ConstraintInfos.clear();
3606 // Second pass - Loop over all of the operands, assigning virtual or physregs
3607 // to registerclass operands.
3608 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3609 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3611 // C_Register operands have already been allocated, Other/Memory don't need
3613 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3614 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3617 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3618 std::vector<SDOperand> AsmNodeOperands;
3619 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3620 AsmNodeOperands.push_back(
3621 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3624 // Loop over all of the inputs, copying the operand values into the
3625 // appropriate registers and processing the output regs.
3626 RegsForValue RetValRegs;
3628 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3629 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3631 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3632 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3634 switch (OpInfo.Type) {
3635 case InlineAsm::isOutput: {
3636 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3637 OpInfo.ConstraintType != TargetLowering::C_Register) {
3638 // Memory output, or 'other' output (e.g. 'X' constraint).
3639 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3641 // Add information to the INLINEASM node to know about this output.
3642 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3643 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3644 TLI.getPointerTy()));
3645 AsmNodeOperands.push_back(OpInfo.CallOperand);
3649 // Otherwise, this is a register or register class output.
3651 // Copy the output from the appropriate register. Find a register that
3653 if (OpInfo.AssignedRegs.Regs.empty()) {
3654 cerr << "Couldn't allocate output reg for contraint '"
3655 << OpInfo.ConstraintCode << "'!\n";
3659 if (!OpInfo.isIndirect) {
3660 // This is the result value of the call.
3661 assert(RetValRegs.Regs.empty() &&
3662 "Cannot have multiple output constraints yet!");
3663 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3664 RetValRegs = OpInfo.AssignedRegs;
3666 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3667 OpInfo.CallOperandVal));
3670 // Add information to the INLINEASM node to know that this register is
3672 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3676 case InlineAsm::isInput: {
3677 SDOperand InOperandVal = OpInfo.CallOperand;
3679 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3680 // If this is required to match an output register we have already set,
3681 // just use its register.
3682 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3684 // Scan until we find the definition we already emitted of this operand.
3685 // When we find it, create a RegsForValue operand.
3686 unsigned CurOp = 2; // The first operand.
3687 for (; OperandNo; --OperandNo) {
3688 // Advance to the next operand.
3690 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3691 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3692 (NumOps & 7) == 4 /*MEM*/) &&
3693 "Skipped past definitions?");
3694 CurOp += (NumOps>>3)+1;
3698 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3699 if ((NumOps & 7) == 2 /*REGDEF*/) {
3700 // Add NumOps>>3 registers to MatchedRegs.
3701 RegsForValue MatchedRegs;
3702 MatchedRegs.ValueVT = InOperandVal.getValueType();
3703 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3704 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3706 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3707 MatchedRegs.Regs.push_back(Reg);
3710 // Use the produced MatchedRegs object to
3711 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3712 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3715 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3716 assert(0 && "matching constraints for memory operands unimp");
3720 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3721 assert(!OpInfo.isIndirect &&
3722 "Don't know how to handle indirect other inputs yet!");
3724 std::vector<SDOperand> Ops;
3725 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3728 cerr << "Invalid operand for inline asm constraint '"
3729 << OpInfo.ConstraintCode << "'!\n";
3733 // Add information to the INLINEASM node to know about this input.
3734 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3735 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3736 TLI.getPointerTy()));
3737 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3739 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3740 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3741 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3742 "Memory operands expect pointer values");
3744 // Add information to the INLINEASM node to know about this input.
3745 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3746 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3747 TLI.getPointerTy()));
3748 AsmNodeOperands.push_back(InOperandVal);
3752 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3753 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3754 "Unknown constraint type!");
3755 assert(!OpInfo.isIndirect &&
3756 "Don't know how to handle indirect register inputs yet!");
3758 // Copy the input into the appropriate registers.
3759 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3760 "Couldn't allocate input reg!");
3762 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3764 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3768 case InlineAsm::isClobber: {
3769 // Add the clobbered value to the operand list, so that the register
3770 // allocator is aware that the physreg got clobbered.
3771 if (!OpInfo.AssignedRegs.Regs.empty())
3772 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3779 // Finish up input operands.
3780 AsmNodeOperands[0] = Chain;
3781 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3783 Chain = DAG.getNode(ISD::INLINEASM,
3784 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3785 &AsmNodeOperands[0], AsmNodeOperands.size());
3786 Flag = Chain.getValue(1);
3788 // If this asm returns a register value, copy the result from that register
3789 // and set it as the value of the call.
3790 if (!RetValRegs.Regs.empty()) {
3791 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3793 // If the result of the inline asm is a vector, it may have the wrong
3794 // width/num elts. Make sure to convert it to the right type with
3796 if (MVT::isVector(Val.getValueType())) {
3797 const VectorType *VTy = cast<VectorType>(CS.getType());
3798 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3800 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3803 setValue(CS.getInstruction(), Val);
3806 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3808 // Process indirect outputs, first output all of the flagged copies out of
3810 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3811 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3812 Value *Ptr = IndirectStoresToEmit[i].second;
3813 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3814 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3817 // Emit the non-flagged stores from the physregs.
3818 SmallVector<SDOperand, 8> OutChains;
3819 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3820 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3821 getValue(StoresToEmit[i].second),
3822 StoresToEmit[i].second, 0));
3823 if (!OutChains.empty())
3824 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3825 &OutChains[0], OutChains.size());
3830 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3831 SDOperand Src = getValue(I.getOperand(0));
3833 MVT::ValueType IntPtr = TLI.getPointerTy();
3835 if (IntPtr < Src.getValueType())
3836 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3837 else if (IntPtr > Src.getValueType())
3838 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3840 // Scale the source by the type size.
3841 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
3842 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3843 Src, DAG.getIntPtrConstant(ElementSize));
3845 TargetLowering::ArgListTy Args;
3846 TargetLowering::ArgListEntry Entry;
3848 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3849 Args.push_back(Entry);
3851 std::pair<SDOperand,SDOperand> Result =
3852 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
3853 DAG.getExternalSymbol("malloc", IntPtr),
3855 setValue(&I, Result.first); // Pointers always fit in registers
3856 DAG.setRoot(Result.second);
3859 void SelectionDAGLowering::visitFree(FreeInst &I) {
3860 TargetLowering::ArgListTy Args;
3861 TargetLowering::ArgListEntry Entry;
3862 Entry.Node = getValue(I.getOperand(0));
3863 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3864 Args.push_back(Entry);
3865 MVT::ValueType IntPtr = TLI.getPointerTy();
3866 std::pair<SDOperand,SDOperand> Result =
3867 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
3868 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3869 DAG.setRoot(Result.second);
3872 // EmitInstrWithCustomInserter - This method should be implemented by targets
3873 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3874 // instructions are special in various ways, which require special support to
3875 // insert. The specified MachineInstr is created but not inserted into any
3876 // basic blocks, and the scheduler passes ownership of it to this method.
3877 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3878 MachineBasicBlock *MBB) {
3879 cerr << "If a target marks an instruction with "
3880 << "'usesCustomDAGSchedInserter', it must implement "
3881 << "TargetLowering::EmitInstrWithCustomInserter!\n";
3886 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3887 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3888 getValue(I.getOperand(1)),
3889 DAG.getSrcValue(I.getOperand(1))));
3892 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3893 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3894 getValue(I.getOperand(0)),
3895 DAG.getSrcValue(I.getOperand(0)));
3897 DAG.setRoot(V.getValue(1));
3900 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3901 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3902 getValue(I.getOperand(1)),
3903 DAG.getSrcValue(I.getOperand(1))));
3906 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3907 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3908 getValue(I.getOperand(1)),
3909 getValue(I.getOperand(2)),
3910 DAG.getSrcValue(I.getOperand(1)),
3911 DAG.getSrcValue(I.getOperand(2))));
3914 /// TargetLowering::LowerArguments - This is the default LowerArguments
3915 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3916 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3917 /// integrated into SDISel.
3918 std::vector<SDOperand>
3919 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3920 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3921 std::vector<SDOperand> Ops;
3922 Ops.push_back(DAG.getRoot());
3923 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3924 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3926 // Add one result value for each formal argument.
3927 std::vector<MVT::ValueType> RetVals;
3929 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3931 MVT::ValueType VT = getValueType(I->getType());
3932 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3933 unsigned OriginalAlignment =
3934 getTargetData()->getABITypeAlignment(I->getType());
3936 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3937 // that is zero extended!
3938 if (F.paramHasAttr(j, ParamAttr::ZExt))
3939 Flags &= ~(ISD::ParamFlags::SExt);
3940 if (F.paramHasAttr(j, ParamAttr::SExt))
3941 Flags |= ISD::ParamFlags::SExt;
3942 if (F.paramHasAttr(j, ParamAttr::InReg))
3943 Flags |= ISD::ParamFlags::InReg;
3944 if (F.paramHasAttr(j, ParamAttr::StructRet))
3945 Flags |= ISD::ParamFlags::StructReturn;
3946 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
3947 Flags |= ISD::ParamFlags::ByVal;
3948 const PointerType *Ty = cast<PointerType>(I->getType());
3949 const Type *ElementTy = Ty->getElementType();
3950 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
3951 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
3952 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
3953 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
3955 if (F.paramHasAttr(j, ParamAttr::Nest))
3956 Flags |= ISD::ParamFlags::Nest;
3957 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
3959 MVT::ValueType RegisterVT = getRegisterType(VT);
3960 unsigned NumRegs = getNumRegisters(VT);
3961 for (unsigned i = 0; i != NumRegs; ++i) {
3962 RetVals.push_back(RegisterVT);
3963 // if it isn't first piece, alignment must be 1
3965 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3966 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3967 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3971 RetVals.push_back(MVT::Other);
3974 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3975 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3976 &Ops[0], Ops.size()).Val;
3977 unsigned NumArgRegs = Result->getNumValues() - 1;
3978 DAG.setRoot(SDOperand(Result, NumArgRegs));
3980 // Set up the return result vector.
3984 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3986 MVT::ValueType VT = getValueType(I->getType());
3987 MVT::ValueType PartVT = getRegisterType(VT);
3989 unsigned NumParts = getNumRegisters(VT);
3990 SmallVector<SDOperand, 4> Parts(NumParts);
3991 for (unsigned j = 0; j != NumParts; ++j)
3992 Parts[j] = SDOperand(Result, i++);
3994 ISD::NodeType AssertOp = ISD::DELETED_NODE;
3995 if (F.paramHasAttr(Idx, ParamAttr::SExt))
3996 AssertOp = ISD::AssertSext;
3997 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
3998 AssertOp = ISD::AssertZext;
4000 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4003 assert(i == NumArgRegs && "Argument register count mismatch!");
4008 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4009 /// implementation, which just inserts an ISD::CALL node, which is later custom
4010 /// lowered by the target to something concrete. FIXME: When all targets are
4011 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4012 std::pair<SDOperand, SDOperand>
4013 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4014 bool RetTyIsSigned, bool isVarArg,
4015 unsigned CallingConv, bool isTailCall,
4017 ArgListTy &Args, SelectionDAG &DAG) {
4018 SmallVector<SDOperand, 32> Ops;
4019 Ops.push_back(Chain); // Op#0 - Chain
4020 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4021 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4022 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4023 Ops.push_back(Callee);
4025 // Handle all of the outgoing arguments.
4026 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4027 MVT::ValueType VT = getValueType(Args[i].Ty);
4028 SDOperand Op = Args[i].Node;
4029 unsigned Flags = ISD::ParamFlags::NoFlagSet;
4030 unsigned OriginalAlignment =
4031 getTargetData()->getABITypeAlignment(Args[i].Ty);
4034 Flags |= ISD::ParamFlags::SExt;
4036 Flags |= ISD::ParamFlags::ZExt;
4037 if (Args[i].isInReg)
4038 Flags |= ISD::ParamFlags::InReg;
4040 Flags |= ISD::ParamFlags::StructReturn;
4041 if (Args[i].isByVal) {
4042 Flags |= ISD::ParamFlags::ByVal;
4043 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4044 const Type *ElementTy = Ty->getElementType();
4045 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
4046 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4047 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
4048 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
4051 Flags |= ISD::ParamFlags::Nest;
4052 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
4054 MVT::ValueType PartVT = getRegisterType(VT);
4055 unsigned NumParts = getNumRegisters(VT);
4056 SmallVector<SDOperand, 4> Parts(NumParts);
4057 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4060 ExtendKind = ISD::SIGN_EXTEND;
4061 else if (Args[i].isZExt)
4062 ExtendKind = ISD::ZERO_EXTEND;
4064 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4066 for (unsigned i = 0; i != NumParts; ++i) {
4067 // if it isn't first piece, alignment must be 1
4068 unsigned MyFlags = Flags;
4070 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4071 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4073 Ops.push_back(Parts[i]);
4074 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
4078 // Figure out the result value types.
4079 MVT::ValueType VT = getValueType(RetTy);
4080 MVT::ValueType RegisterVT = getRegisterType(VT);
4081 unsigned NumRegs = getNumRegisters(VT);
4082 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4083 for (unsigned i = 0; i != NumRegs; ++i)
4084 RetTys[i] = RegisterVT;
4086 RetTys.push_back(MVT::Other); // Always has a chain.
4088 // Create the CALL node.
4089 SDOperand Res = DAG.getNode(ISD::CALL,
4090 DAG.getVTList(&RetTys[0], NumRegs + 1),
4091 &Ops[0], Ops.size());
4092 Chain = Res.getValue(NumRegs);
4094 // Gather up the call result into a single value.
4095 if (RetTy != Type::VoidTy) {
4096 ISD::NodeType AssertOp = ISD::AssertSext;
4098 AssertOp = ISD::AssertZext;
4099 SmallVector<SDOperand, 4> Results(NumRegs);
4100 for (unsigned i = 0; i != NumRegs; ++i)
4101 Results[i] = Res.getValue(i);
4102 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
4105 return std::make_pair(Res, Chain);
4108 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4109 assert(0 && "LowerOperation not implemented for this target!");
4114 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4115 SelectionDAG &DAG) {
4116 assert(0 && "CustomPromoteOperation not implemented for this target!");
4121 /// getMemsetValue - Vectorized representation of the memset value
4123 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4124 SelectionDAG &DAG) {
4125 MVT::ValueType CurVT = VT;
4126 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4127 uint64_t Val = C->getValue() & 255;
4129 while (CurVT != MVT::i8) {
4130 Val = (Val << Shift) | Val;
4132 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4134 return DAG.getConstant(Val, VT);
4136 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4138 while (CurVT != MVT::i8) {
4140 DAG.getNode(ISD::OR, VT,
4141 DAG.getNode(ISD::SHL, VT, Value,
4142 DAG.getConstant(Shift, MVT::i8)), Value);
4144 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4151 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4152 /// used when a memcpy is turned into a memset when the source is a constant
4154 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4155 SelectionDAG &DAG, TargetLowering &TLI,
4156 std::string &Str, unsigned Offset) {
4158 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4159 if (TLI.isLittleEndian())
4160 Offset = Offset + MSB - 1;
4161 for (unsigned i = 0; i != MSB; ++i) {
4162 Val = (Val << 8) | (unsigned char)Str[Offset];
4163 Offset += TLI.isLittleEndian() ? -1 : 1;
4165 return DAG.getConstant(Val, VT);
4168 /// getMemBasePlusOffset - Returns base and offset node for the
4169 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4170 SelectionDAG &DAG, TargetLowering &TLI) {
4171 MVT::ValueType VT = Base.getValueType();
4172 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4175 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4176 /// to replace the memset / memcpy is below the threshold. It also returns the
4177 /// types of the sequence of memory ops to perform memset / memcpy.
4178 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4179 unsigned Limit, uint64_t Size,
4180 unsigned Align, TargetLowering &TLI) {
4183 if (TLI.allowsUnalignedMemoryAccesses()) {
4186 switch (Align & 7) {
4202 MVT::ValueType LVT = MVT::i64;
4203 while (!TLI.isTypeLegal(LVT))
4204 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4205 assert(MVT::isInteger(LVT));
4210 unsigned NumMemOps = 0;
4212 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4213 while (VTSize > Size) {
4214 VT = (MVT::ValueType)((unsigned)VT - 1);
4217 assert(MVT::isInteger(VT));
4219 if (++NumMemOps > Limit)
4221 MemOps.push_back(VT);
4228 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4229 SDOperand Op1 = getValue(I.getOperand(1));
4230 SDOperand Op2 = getValue(I.getOperand(2));
4231 SDOperand Op3 = getValue(I.getOperand(3));
4232 SDOperand Op4 = getValue(I.getOperand(4));
4233 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4234 if (Align == 0) Align = 1;
4236 // If the source and destination are known to not be aliases, we can
4237 // lower memmove as memcpy.
4238 if (Op == ISD::MEMMOVE) {
4239 uint64_t Size = -1ULL;
4240 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4241 Size = C->getValue();
4242 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4243 AliasAnalysis::NoAlias)
4247 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4248 std::vector<MVT::ValueType> MemOps;
4250 // Expand memset / memcpy to a series of load / store ops
4251 // if the size operand falls below a certain threshold.
4252 SmallVector<SDOperand, 8> OutChains;
4254 default: break; // Do nothing for now.
4256 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4257 Size->getValue(), Align, TLI)) {
4258 unsigned NumMemOps = MemOps.size();
4259 unsigned Offset = 0;
4260 for (unsigned i = 0; i < NumMemOps; i++) {
4261 MVT::ValueType VT = MemOps[i];
4262 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4263 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4264 SDOperand Store = DAG.getStore(getRoot(), Value,
4265 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4266 I.getOperand(1), Offset);
4267 OutChains.push_back(Store);
4274 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4275 Size->getValue(), Align, TLI)) {
4276 unsigned NumMemOps = MemOps.size();
4277 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4278 GlobalAddressSDNode *G = NULL;
4280 bool CopyFromStr = false;
4282 if (Op2.getOpcode() == ISD::GlobalAddress)
4283 G = cast<GlobalAddressSDNode>(Op2);
4284 else if (Op2.getOpcode() == ISD::ADD &&
4285 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4286 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4287 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4288 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4291 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4292 if (GV && GV->isConstant()) {
4293 Str = GV->getStringValue(false);
4301 for (unsigned i = 0; i < NumMemOps; i++) {
4302 MVT::ValueType VT = MemOps[i];
4303 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4304 SDOperand Value, Chain, Store;
4307 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4310 DAG.getStore(Chain, Value,
4311 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4312 I.getOperand(1), DstOff);
4314 Value = DAG.getLoad(VT, getRoot(),
4315 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4316 I.getOperand(2), SrcOff, false, Align);
4317 Chain = Value.getValue(1);
4319 DAG.getStore(Chain, Value,
4320 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4321 I.getOperand(1), DstOff, false, Align);
4323 OutChains.push_back(Store);
4332 if (!OutChains.empty()) {
4333 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4334 &OutChains[0], OutChains.size()));
4339 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4343 assert(0 && "Unknown Op");
4345 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4348 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4351 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4357 //===----------------------------------------------------------------------===//
4358 // SelectionDAGISel code
4359 //===----------------------------------------------------------------------===//
4361 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4362 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4365 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4366 AU.addRequired<AliasAnalysis>();
4367 AU.addRequired<CollectorModuleMetadata>();
4368 AU.setPreservesAll();
4373 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4374 // Get alias analysis for load/store combining.
4375 AA = &getAnalysis<AliasAnalysis>();
4377 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4378 if (MF.getFunction()->hasCollector())
4379 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4382 RegInfo = &MF.getRegInfo();
4383 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4385 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4387 if (ExceptionHandling)
4388 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4389 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4390 // Mark landing pad.
4391 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4393 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4394 SelectBasicBlock(I, MF, FuncInfo);
4396 // Add function live-ins to entry block live-in set.
4397 BasicBlock *EntryBB = &Fn.getEntryBlock();
4398 BB = FuncInfo.MBBMap[EntryBB];
4399 if (!RegInfo->livein_empty())
4400 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4401 E = RegInfo->livein_end(); I != E; ++I)
4402 BB->addLiveIn(I->first);
4405 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4406 "Not all catch info was assigned to a landing pad!");
4412 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4414 SDOperand Op = getValue(V);
4415 assert((Op.getOpcode() != ISD::CopyFromReg ||
4416 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4417 "Copy from a reg to the same reg!");
4419 MVT::ValueType SrcVT = Op.getValueType();
4420 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4421 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4422 SmallVector<SDOperand, 8> Regs(NumRegs);
4423 SmallVector<SDOperand, 8> Chains(NumRegs);
4425 // Copy the value by legal parts into sequential virtual registers.
4426 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4427 for (unsigned i = 0; i != NumRegs; ++i)
4428 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4429 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4432 void SelectionDAGISel::
4433 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4434 std::vector<SDOperand> &UnorderedChains) {
4435 // If this is the entry block, emit arguments.
4436 Function &F = *LLVMBB->getParent();
4437 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4438 SDOperand OldRoot = SDL.DAG.getRoot();
4439 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4442 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4444 if (!AI->use_empty()) {
4445 SDL.setValue(AI, Args[a]);
4447 // If this argument is live outside of the entry block, insert a copy from
4448 // whereever we got it to the vreg that other BB's will reference it as.
4449 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4450 if (VMI != FuncInfo.ValueMap.end()) {
4451 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4452 UnorderedChains.push_back(Copy);
4456 // Finally, if the target has anything special to do, allow it to do so.
4457 // FIXME: this should insert code into the DAG!
4458 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4461 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4462 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4463 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4464 if (isSelector(I)) {
4465 // Apply the catch info to DestBB.
4466 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4468 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4469 FLI.CatchInfoFound.insert(I);
4474 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4475 /// DAG and fixes their tailcall attribute operand.
4476 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4477 TargetLowering& TLI) {
4478 SDNode * Ret = NULL;
4479 SDOperand Terminator = DAG.getRoot();
4482 if (Terminator.getOpcode() == ISD::RET) {
4483 Ret = Terminator.Val;
4486 // Fix tail call attribute of CALL nodes.
4487 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4488 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4489 if (BI->getOpcode() == ISD::CALL) {
4490 SDOperand OpRet(Ret, 0);
4491 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4492 bool isMarkedTailCall =
4493 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4494 // If CALL node has tail call attribute set to true and the call is not
4495 // eligible (no RET or the target rejects) the attribute is fixed to
4496 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4497 // must correctly identify tail call optimizable calls.
4498 if (isMarkedTailCall &&
4500 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4501 SmallVector<SDOperand, 32> Ops;
4503 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4504 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4508 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4510 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4516 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4517 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4518 FunctionLoweringInfo &FuncInfo) {
4519 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4521 std::vector<SDOperand> UnorderedChains;
4523 // Lower any arguments needed in this block if this is the entry block.
4524 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4525 LowerArguments(LLVMBB, SDL, UnorderedChains);
4527 BB = FuncInfo.MBBMap[LLVMBB];
4528 SDL.setCurrentBasicBlock(BB);
4530 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4532 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4533 // Add a label to mark the beginning of the landing pad. Deletion of the
4534 // landing pad can thus be detected via the MachineModuleInfo.
4535 unsigned LabelID = MMI->addLandingPad(BB);
4536 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4537 DAG.getConstant(LabelID, MVT::i32),
4538 DAG.getConstant(1, MVT::i32)));
4540 // Mark exception register as live in.
4541 unsigned Reg = TLI.getExceptionAddressRegister();
4542 if (Reg) BB->addLiveIn(Reg);
4544 // Mark exception selector register as live in.
4545 Reg = TLI.getExceptionSelectorRegister();
4546 if (Reg) BB->addLiveIn(Reg);
4548 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4549 // function and list of typeids logically belong to the invoke (or, if you
4550 // like, the basic block containing the invoke), and need to be associated
4551 // with it in the dwarf exception handling tables. Currently however the
4552 // information is provided by an intrinsic (eh.selector) that can be moved
4553 // to unexpected places by the optimizers: if the unwind edge is critical,
4554 // then breaking it can result in the intrinsics being in the successor of
4555 // the landing pad, not the landing pad itself. This results in exceptions
4556 // not being caught because no typeids are associated with the invoke.
4557 // This may not be the only way things can go wrong, but it is the only way
4558 // we try to work around for the moment.
4559 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4561 if (Br && Br->isUnconditional()) { // Critical edge?
4562 BasicBlock::iterator I, E;
4563 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4568 // No catch info found - try to extract some from the successor.
4569 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4573 // Lower all of the non-terminator instructions.
4574 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4578 // Ensure that all instructions which are used outside of their defining
4579 // blocks are available as virtual registers. Invoke is handled elsewhere.
4580 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4581 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4582 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4583 if (VMI != FuncInfo.ValueMap.end())
4584 UnorderedChains.push_back(
4585 SDL.CopyValueToVirtualRegister(I, VMI->second));
4588 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4589 // ensure constants are generated when needed. Remember the virtual registers
4590 // that need to be added to the Machine PHI nodes as input. We cannot just
4591 // directly add them, because expansion might result in multiple MBB's for one
4592 // BB. As such, the start of the BB might correspond to a different MBB than
4595 TerminatorInst *TI = LLVMBB->getTerminator();
4597 // Emit constants only once even if used by multiple PHI nodes.
4598 std::map<Constant*, unsigned> ConstantsOut;
4600 // Vector bool would be better, but vector<bool> is really slow.
4601 std::vector<unsigned char> SuccsHandled;
4602 if (TI->getNumSuccessors())
4603 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4605 // Check successor nodes' PHI nodes that expect a constant to be available
4607 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4608 BasicBlock *SuccBB = TI->getSuccessor(succ);
4609 if (!isa<PHINode>(SuccBB->begin())) continue;
4610 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4612 // If this terminator has multiple identical successors (common for
4613 // switches), only handle each succ once.
4614 unsigned SuccMBBNo = SuccMBB->getNumber();
4615 if (SuccsHandled[SuccMBBNo]) continue;
4616 SuccsHandled[SuccMBBNo] = true;
4618 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4621 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4622 // nodes and Machine PHI nodes, but the incoming operands have not been
4624 for (BasicBlock::iterator I = SuccBB->begin();
4625 (PN = dyn_cast<PHINode>(I)); ++I) {
4626 // Ignore dead phi's.
4627 if (PN->use_empty()) continue;
4630 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4632 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4633 unsigned &RegOut = ConstantsOut[C];
4635 RegOut = FuncInfo.CreateRegForValue(C);
4636 UnorderedChains.push_back(
4637 SDL.CopyValueToVirtualRegister(C, RegOut));
4641 Reg = FuncInfo.ValueMap[PHIOp];
4643 assert(isa<AllocaInst>(PHIOp) &&
4644 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4645 "Didn't codegen value into a register!??");
4646 Reg = FuncInfo.CreateRegForValue(PHIOp);
4647 UnorderedChains.push_back(
4648 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4652 // Remember that this register needs to added to the machine PHI node as
4653 // the input for this MBB.
4654 MVT::ValueType VT = TLI.getValueType(PN->getType());
4655 unsigned NumRegisters = TLI.getNumRegisters(VT);
4656 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4657 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4660 ConstantsOut.clear();
4662 // Turn all of the unordered chains into one factored node.
4663 if (!UnorderedChains.empty()) {
4664 SDOperand Root = SDL.getRoot();
4665 if (Root.getOpcode() != ISD::EntryToken) {
4666 unsigned i = 0, e = UnorderedChains.size();
4667 for (; i != e; ++i) {
4668 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4669 if (UnorderedChains[i].Val->getOperand(0) == Root)
4670 break; // Don't add the root if we already indirectly depend on it.
4674 UnorderedChains.push_back(Root);
4676 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4677 &UnorderedChains[0], UnorderedChains.size()));
4680 // Lower the terminator after the copies are emitted.
4681 SDL.visit(*LLVMBB->getTerminator());
4683 // Copy over any CaseBlock records that may now exist due to SwitchInst
4684 // lowering, as well as any jump table information.
4685 SwitchCases.clear();
4686 SwitchCases = SDL.SwitchCases;
4688 JTCases = SDL.JTCases;
4689 BitTestCases.clear();
4690 BitTestCases = SDL.BitTestCases;
4692 // Make sure the root of the DAG is up-to-date.
4693 DAG.setRoot(SDL.getRoot());
4695 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4696 // with correct tailcall attribute so that the target can rely on the tailcall
4697 // attribute indicating whether the call is really eligible for tail call
4699 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4702 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4703 DOUT << "Lowered selection DAG:\n";
4706 // Run the DAG combiner in pre-legalize mode.
4707 DAG.Combine(false, *AA);
4709 DOUT << "Optimized lowered selection DAG:\n";
4712 // Second step, hack on the DAG until it only uses operations and types that
4713 // the target supports.
4714 #if 0 // Enable this some day.
4715 DAG.LegalizeTypes();
4716 // Someday even later, enable a dag combine pass here.
4720 DOUT << "Legalized selection DAG:\n";
4723 // Run the DAG combiner in post-legalize mode.
4724 DAG.Combine(true, *AA);
4726 DOUT << "Optimized legalized selection DAG:\n";
4729 if (ViewISelDAGs) DAG.viewGraph();
4731 // Third, instruction select all of the operations to machine code, adding the
4732 // code to the MachineBasicBlock.
4733 InstructionSelectBasicBlock(DAG);
4735 DOUT << "Selected machine code:\n";
4739 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4740 FunctionLoweringInfo &FuncInfo) {
4741 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4743 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4746 // First step, lower LLVM code to some DAG. This DAG may use operations and
4747 // types that are not supported by the target.
4748 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4750 // Second step, emit the lowered DAG as machine code.
4751 CodeGenAndEmitDAG(DAG);
4754 DOUT << "Total amount of phi nodes to update: "
4755 << PHINodesToUpdate.size() << "\n";
4756 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4757 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4758 << ", " << PHINodesToUpdate[i].second << ")\n";);
4760 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4761 // PHI nodes in successors.
4762 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4763 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4764 MachineInstr *PHI = PHINodesToUpdate[i].first;
4765 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4766 "This is not a machine PHI node that we are updating!");
4767 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4769 PHI->addOperand(MachineOperand::CreateMBB(BB));
4774 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4775 // Lower header first, if it wasn't already lowered
4776 if (!BitTestCases[i].Emitted) {
4777 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4779 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4780 // Set the current basic block to the mbb we wish to insert the code into
4781 BB = BitTestCases[i].Parent;
4782 HSDL.setCurrentBasicBlock(BB);
4784 HSDL.visitBitTestHeader(BitTestCases[i]);
4785 HSDAG.setRoot(HSDL.getRoot());
4786 CodeGenAndEmitDAG(HSDAG);
4789 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4790 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4792 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
4793 // Set the current basic block to the mbb we wish to insert the code into
4794 BB = BitTestCases[i].Cases[j].ThisBB;
4795 BSDL.setCurrentBasicBlock(BB);
4798 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4799 BitTestCases[i].Reg,
4800 BitTestCases[i].Cases[j]);
4802 BSDL.visitBitTestCase(BitTestCases[i].Default,
4803 BitTestCases[i].Reg,
4804 BitTestCases[i].Cases[j]);
4807 BSDAG.setRoot(BSDL.getRoot());
4808 CodeGenAndEmitDAG(BSDAG);
4812 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4813 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4814 MachineBasicBlock *PHIBB = PHI->getParent();
4815 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4816 "This is not a machine PHI node that we are updating!");
4817 // This is "default" BB. We have two jumps to it. From "header" BB and
4818 // from last "case" BB.
4819 if (PHIBB == BitTestCases[i].Default) {
4820 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4822 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
4823 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4825 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
4828 // One of "cases" BB.
4829 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4830 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4831 if (cBB->succ_end() !=
4832 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4833 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4835 PHI->addOperand(MachineOperand::CreateMBB(cBB));
4841 // If the JumpTable record is filled in, then we need to emit a jump table.
4842 // Updating the PHI nodes is tricky in this case, since we need to determine
4843 // whether the PHI is a successor of the range check MBB or the jump table MBB
4844 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4845 // Lower header first, if it wasn't already lowered
4846 if (!JTCases[i].first.Emitted) {
4847 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4849 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4850 // Set the current basic block to the mbb we wish to insert the code into
4851 BB = JTCases[i].first.HeaderBB;
4852 HSDL.setCurrentBasicBlock(BB);
4854 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4855 HSDAG.setRoot(HSDL.getRoot());
4856 CodeGenAndEmitDAG(HSDAG);
4859 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4861 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
4862 // Set the current basic block to the mbb we wish to insert the code into
4863 BB = JTCases[i].second.MBB;
4864 JSDL.setCurrentBasicBlock(BB);
4866 JSDL.visitJumpTable(JTCases[i].second);
4867 JSDAG.setRoot(JSDL.getRoot());
4868 CodeGenAndEmitDAG(JSDAG);
4871 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4872 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4873 MachineBasicBlock *PHIBB = PHI->getParent();
4874 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4875 "This is not a machine PHI node that we are updating!");
4876 // "default" BB. We can go there only from header BB.
4877 if (PHIBB == JTCases[i].second.Default) {
4878 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4880 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
4882 // JT BB. Just iterate over successors here
4883 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4884 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4886 PHI->addOperand(MachineOperand::CreateMBB(BB));
4891 // If the switch block involved a branch to one of the actual successors, we
4892 // need to update PHI nodes in that block.
4893 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4894 MachineInstr *PHI = PHINodesToUpdate[i].first;
4895 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4896 "This is not a machine PHI node that we are updating!");
4897 if (BB->isSuccessor(PHI->getParent())) {
4898 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4900 PHI->addOperand(MachineOperand::CreateMBB(BB));
4904 // If we generated any switch lowering information, build and codegen any
4905 // additional DAGs necessary.
4906 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4907 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4909 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
4911 // Set the current basic block to the mbb we wish to insert the code into
4912 BB = SwitchCases[i].ThisBB;
4913 SDL.setCurrentBasicBlock(BB);
4916 SDL.visitSwitchCase(SwitchCases[i]);
4917 SDAG.setRoot(SDL.getRoot());
4918 CodeGenAndEmitDAG(SDAG);
4920 // Handle any PHI nodes in successors of this chunk, as if we were coming
4921 // from the original BB before switch expansion. Note that PHI nodes can
4922 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4923 // handle them the right number of times.
4924 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4925 for (MachineBasicBlock::iterator Phi = BB->begin();
4926 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4927 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4928 for (unsigned pn = 0; ; ++pn) {
4929 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4930 if (PHINodesToUpdate[pn].first == Phi) {
4931 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
4933 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
4939 // Don't process RHS if same block as LHS.
4940 if (BB == SwitchCases[i].FalseBB)
4941 SwitchCases[i].FalseBB = 0;
4943 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4944 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4945 SwitchCases[i].FalseBB = 0;
4947 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4952 //===----------------------------------------------------------------------===//
4953 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4954 /// target node in the graph.
4955 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4956 if (ViewSchedDAGs) DAG.viewGraph();
4958 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4962 RegisterScheduler::setDefault(Ctor);
4965 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4968 if (ViewSUnitDAGs) SL->viewGraph();
4974 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4975 return new HazardRecognizer();
4978 //===----------------------------------------------------------------------===//
4979 // Helper functions used by the generated instruction selector.
4980 //===----------------------------------------------------------------------===//
4981 // Calls to these methods are generated by tblgen.
4983 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4984 /// the dag combiner simplified the 255, we still want to match. RHS is the
4985 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4986 /// specified in the .td file (e.g. 255).
4987 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4988 int64_t DesiredMaskS) const {
4989 uint64_t ActualMask = RHS->getValue();
4990 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4992 // If the actual mask exactly matches, success!
4993 if (ActualMask == DesiredMask)
4996 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4997 if (ActualMask & ~DesiredMask)
5000 // Otherwise, the DAG Combiner may have proven that the value coming in is
5001 // either already zero or is not demanded. Check for known zero input bits.
5002 uint64_t NeededMask = DesiredMask & ~ActualMask;
5003 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5006 // TODO: check to see if missing bits are just not demanded.
5008 // Otherwise, this pattern doesn't match.
5012 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5013 /// the dag combiner simplified the 255, we still want to match. RHS is the
5014 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5015 /// specified in the .td file (e.g. 255).
5016 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5017 int64_t DesiredMaskS) const {
5018 uint64_t ActualMask = RHS->getValue();
5019 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5021 // If the actual mask exactly matches, success!
5022 if (ActualMask == DesiredMask)
5025 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5026 if (ActualMask & ~DesiredMask)
5029 // Otherwise, the DAG Combiner may have proven that the value coming in is
5030 // either already zero or is not demanded. Check for known zero input bits.
5031 uint64_t NeededMask = DesiredMask & ~ActualMask;
5033 uint64_t KnownZero, KnownOne;
5034 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5036 // If all the missing bits in the or are already known to be set, match!
5037 if ((NeededMask & KnownOne) == NeededMask)
5040 // TODO: check to see if missing bits are just not demanded.
5042 // Otherwise, this pattern doesn't match.
5047 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5048 /// by tblgen. Others should not call it.
5049 void SelectionDAGISel::
5050 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5051 std::vector<SDOperand> InOps;
5052 std::swap(InOps, Ops);
5054 Ops.push_back(InOps[0]); // input chain.
5055 Ops.push_back(InOps[1]); // input asm string.
5057 unsigned i = 2, e = InOps.size();
5058 if (InOps[e-1].getValueType() == MVT::Flag)
5059 --e; // Don't process a flag operand if it is here.
5062 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5063 if ((Flags & 7) != 4 /*MEM*/) {
5064 // Just skip over this operand, copying the operands verbatim.
5065 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5066 i += (Flags >> 3) + 1;
5068 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5069 // Otherwise, this is a memory operand. Ask the target to select it.
5070 std::vector<SDOperand> SelOps;
5071 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5072 cerr << "Could not match memory address. Inline asm failure!\n";
5076 // Add this to the output node.
5077 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5078 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5080 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5085 // Add the flag input back if present.
5086 if (e != InOps.size())
5087 Ops.push_back(InOps.back());
5090 char SelectionDAGISel::ID = 0;