1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/CodeGen/DwarfWriter.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetIntrinsicInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetMachine.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/Timer.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/ADT/Statistic.h"
63 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
64 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
68 cl::desc("Enable verbose messages in the \"fast\" "
69 "instruction selector"));
71 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
72 cl::desc("Enable abort calls when \"fast\" instruction fails"));
74 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
75 cl::desc("Schedule copies of livein registers"),
80 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the first "
84 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
85 cl::desc("Pop up a window to show dags before legalize types"));
87 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
88 cl::desc("Pop up a window to show dags before legalize"));
90 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
91 cl::desc("Pop up a window to show dags before the second "
94 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
95 cl::desc("Pop up a window to show dags before the post legalize types"
96 " dag combine pass"));
98 ViewISelDAGs("view-isel-dags", cl::Hidden,
99 cl::desc("Pop up a window to show isel dags as they are selected"));
101 ViewSchedDAGs("view-sched-dags", cl::Hidden,
102 cl::desc("Pop up a window to show sched dags as they are processed"));
104 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
105 cl::desc("Pop up a window to show SUnit dags after they are processed"));
107 static const bool ViewDAGCombine1 = false,
108 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
109 ViewDAGCombine2 = false,
110 ViewDAGCombineLT = false,
111 ViewISelDAGs = false, ViewSchedDAGs = false,
112 ViewSUnitDAGs = false;
115 //===---------------------------------------------------------------------===//
117 /// RegisterScheduler class - Track the registration of instruction schedulers.
119 //===---------------------------------------------------------------------===//
120 MachinePassRegistry RegisterScheduler::Registry;
122 //===---------------------------------------------------------------------===//
124 /// ISHeuristic command line option for instruction schedulers.
126 //===---------------------------------------------------------------------===//
127 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
128 RegisterPassParser<RegisterScheduler> >
129 ISHeuristic("pre-RA-sched",
130 cl::init(&createDefaultScheduler),
131 cl::desc("Instruction schedulers available (before register"
134 static RegisterScheduler
135 defaultListDAGScheduler("default", "Best scheduler for the target",
136 createDefaultScheduler);
139 //===--------------------------------------------------------------------===//
140 /// createDefaultScheduler - This creates an instruction scheduler appropriate
142 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
143 CodeGenOpt::Level OptLevel) {
144 const TargetLowering &TLI = IS->getTargetLowering();
146 if (OptLevel == CodeGenOpt::None)
147 return createFastDAGScheduler(IS, OptLevel);
148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
149 return createTDListDAGScheduler(IS, OptLevel);
150 assert(TLI.getSchedulingPreference() ==
151 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
152 return createBURRListDAGScheduler(IS, OptLevel);
156 // EmitInstrWithCustomInserter - This method should be implemented by targets
157 // that mark instructions with the 'usesCustomInserter' flag. These
158 // instructions are special in various ways, which require special support to
159 // insert. The specified MachineInstr is created but not inserted into any
160 // basic blocks, and this method is called to expand it into a sequence of
161 // instructions, potentially also creating new basic blocks and control flow.
162 // When new basic blocks are inserted and the edges from MBB to its successors
163 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
165 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
166 MachineBasicBlock *MBB,
167 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
169 dbgs() << "If a target marks an instruction with "
170 "'usesCustomInserter', it must implement "
171 "TargetLowering::EmitInstrWithCustomInserter!";
177 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
178 /// physical register has only a single copy use, then coalesced the copy
180 static void EmitLiveInCopy(MachineBasicBlock *MBB,
181 MachineBasicBlock::iterator &InsertPos,
182 unsigned VirtReg, unsigned PhysReg,
183 const TargetRegisterClass *RC,
184 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
185 const MachineRegisterInfo &MRI,
186 const TargetRegisterInfo &TRI,
187 const TargetInstrInfo &TII) {
188 unsigned NumUses = 0;
189 MachineInstr *UseMI = NULL;
190 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
191 UE = MRI.use_end(); UI != UE; ++UI) {
197 // If the number of uses is not one, or the use is not a move instruction,
198 // don't coalesce. Also, only coalesce away a virtual register to virtual
200 bool Coalesced = false;
201 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
203 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
204 TargetRegisterInfo::isVirtualRegister(DstReg)) {
209 // Now find an ideal location to insert the copy.
210 MachineBasicBlock::iterator Pos = InsertPos;
211 while (Pos != MBB->begin()) {
212 MachineInstr *PrevMI = prior(Pos);
213 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
214 // copyRegToReg might emit multiple instructions to do a copy.
215 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
216 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
217 // This is what the BB looks like right now:
222 // We want to insert "r1025 = mov r1". Inserting this copy below the
223 // move to r1024 makes it impossible for that move to be coalesced.
230 break; // Woot! Found a good location.
234 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
235 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
238 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
240 if (&*InsertPos == UseMI) ++InsertPos;
245 /// EmitLiveInCopies - If this is the first basic block in the function,
246 /// and if it has live ins that need to be copied into vregs, emit the
247 /// copies into the block.
248 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
249 const MachineRegisterInfo &MRI,
250 const TargetRegisterInfo &TRI,
251 const TargetInstrInfo &TII) {
252 if (SchedLiveInCopies) {
253 // Emit the copies at a heuristically-determined location in the block.
254 DenseMap<MachineInstr*, unsigned> CopyRegMap;
255 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
256 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
257 E = MRI.livein_end(); LI != E; ++LI)
259 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
260 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
261 RC, CopyRegMap, MRI, TRI, TII);
264 // Emit the copies into the top of the block.
265 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
266 E = MRI.livein_end(); LI != E; ++LI)
268 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
269 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
270 LI->second, LI->first, RC, RC);
271 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
277 //===----------------------------------------------------------------------===//
278 // SelectionDAGISel code
279 //===----------------------------------------------------------------------===//
281 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
282 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
283 FuncInfo(new FunctionLoweringInfo(TLI)),
284 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
285 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
291 SelectionDAGISel::~SelectionDAGISel() {
297 unsigned SelectionDAGISel::MakeReg(EVT VT) {
298 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
301 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
302 AU.addRequired<AliasAnalysis>();
303 AU.addPreserved<AliasAnalysis>();
304 AU.addRequired<GCModuleInfo>();
305 AU.addPreserved<GCModuleInfo>();
306 AU.addRequired<DwarfWriter>();
307 AU.addPreserved<DwarfWriter>();
308 MachineFunctionPass::getAnalysisUsage(AU);
311 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
312 Function &Fn = *mf.getFunction();
314 // Do some sanity-checking on the command-line options.
315 assert((!EnableFastISelVerbose || EnableFastISel) &&
316 "-fast-isel-verbose requires -fast-isel");
317 assert((!EnableFastISelAbort || EnableFastISel) &&
318 "-fast-isel-abort requires -fast-isel");
320 // Get alias analysis for load/store combining.
321 AA = &getAnalysis<AliasAnalysis>();
324 const TargetInstrInfo &TII = *TM.getInstrInfo();
325 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
328 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
331 RegInfo = &MF->getRegInfo();
332 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
334 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
335 CurDAG->init(*MF, MMI);
336 FuncInfo->set(Fn, *MF, EnableFastISel);
339 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
340 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
342 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
344 SelectAllBasicBlocks(Fn, *MF, MMI, TII);
346 // If the first basic block in the function has live ins that need to be
347 // copied into vregs, emit the copies into the top of the block before
348 // emitting the code for the block.
349 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
351 // Add function live-ins to entry block live-in set.
352 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
353 E = RegInfo->livein_end(); I != E; ++I)
354 MF->begin()->addLiveIn(I->first);
357 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
358 "Not all catch info was assigned to a landing pad!");
366 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
367 /// attached with this instruction.
368 static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB,
369 FastISel *FastIS, MachineFunction *MF) {
370 DebugLoc DL = I->getDebugLoc();
371 if (DL.isUnknown()) return;
373 SDB->setCurDebugLoc(DL);
376 FastIS->setCurDebugLoc(DL);
378 // If the function doesn't have a default debug location yet, set
379 // it. This is kind of a hack.
380 if (MF->getDefaultDebugLoc().isUnknown())
381 MF->setDefaultDebugLoc(DL);
384 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
385 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
386 SDB->setCurDebugLoc(DebugLoc());
388 FastIS->setCurDebugLoc(DebugLoc());
391 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
392 BasicBlock::iterator Begin,
393 BasicBlock::iterator End,
395 SDB->setCurrentBasicBlock(BB);
397 // Lower all of the non-terminator instructions. If a call is emitted
398 // as a tail call, cease emitting nodes for this block.
399 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
400 SetDebugLoc(I, SDB, 0, MF);
402 if (!isa<TerminatorInst>(I)) {
405 // Set the current debug location back to "unknown" so that it doesn't
406 // spuriously apply to subsequent instructions.
407 ResetDebugLoc(SDB, 0);
411 if (!SDB->HasTailCall) {
412 // Ensure that all instructions which are used outside of their defining
413 // blocks are available as virtual registers. Invoke is handled elsewhere.
414 for (BasicBlock::iterator I = Begin; I != End; ++I)
415 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
416 SDB->CopyToExportRegsIfNeeded(I);
418 // Handle PHI nodes in successor blocks.
419 if (End == LLVMBB->end()) {
420 HandlePHINodesInSuccessorBlocks(LLVMBB);
422 // Lower the terminator after the copies are emitted.
423 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF);
424 SDB->visit(*LLVMBB->getTerminator());
425 ResetDebugLoc(SDB, 0);
429 // Make sure the root of the DAG is up-to-date.
430 CurDAG->setRoot(SDB->getControlRoot());
432 // Final step, emit the lowered DAG as machine code.
434 HadTailCall = SDB->HasTailCall;
439 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
440 /// nodes from the worklist.
441 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
442 SmallVector<SDNode*, 128> &Worklist;
443 SmallPtrSet<SDNode*, 128> &InWorklist;
445 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
446 SmallPtrSet<SDNode*, 128> &inwl)
447 : Worklist(wl), InWorklist(inwl) {}
449 void RemoveFromWorklist(SDNode *N) {
450 if (!InWorklist.erase(N)) return;
452 SmallVector<SDNode*, 128>::iterator I =
453 std::find(Worklist.begin(), Worklist.end(), N);
454 assert(I != Worklist.end() && "Not in worklist");
456 *I = Worklist.back();
460 virtual void NodeDeleted(SDNode *N, SDNode *E) {
461 RemoveFromWorklist(N);
464 virtual void NodeUpdated(SDNode *N) {
470 /// TrivialTruncElim - Eliminate some trivial nops that can result from
471 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
472 static bool TrivialTruncElim(SDValue Op,
473 TargetLowering::TargetLoweringOpt &TLO) {
474 SDValue N0 = Op.getOperand(0);
475 EVT VT = Op.getValueType();
476 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
477 N0.getOpcode() == ISD::SIGN_EXTEND ||
478 N0.getOpcode() == ISD::ANY_EXTEND) &&
479 N0.getOperand(0).getValueType() == VT) {
480 return TLO.CombineTo(Op, N0.getOperand(0));
485 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
486 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
487 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
488 void SelectionDAGISel::ShrinkDemandedOps() {
489 SmallVector<SDNode*, 128> Worklist;
490 SmallPtrSet<SDNode*, 128> InWorklist;
492 // Add all the dag nodes to the worklist.
493 Worklist.reserve(CurDAG->allnodes_size());
494 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
495 E = CurDAG->allnodes_end(); I != E; ++I) {
496 Worklist.push_back(I);
497 InWorklist.insert(I);
500 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
501 while (!Worklist.empty()) {
502 SDNode *N = Worklist.pop_back_val();
505 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
506 // Deleting this node may make its operands dead, add them to the worklist
507 // if they aren't already there.
508 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
509 if (InWorklist.insert(N->getOperand(i).getNode()))
510 Worklist.push_back(N->getOperand(i).getNode());
512 CurDAG->DeleteNode(N);
516 // Run ShrinkDemandedOp on scalar binary operations.
517 if (N->getNumValues() != 1 ||
518 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
521 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
522 APInt Demanded = APInt::getAllOnesValue(BitWidth);
523 APInt KnownZero, KnownOne;
524 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
525 KnownZero, KnownOne, TLO) &&
526 (N->getOpcode() != ISD::TRUNCATE ||
527 !TrivialTruncElim(SDValue(N, 0), TLO)))
531 assert(!InWorklist.count(N) && "Already in worklist");
532 Worklist.push_back(N);
533 InWorklist.insert(N);
535 // Replace the old value with the new one.
536 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
537 TLO.Old.getNode()->dump(CurDAG);
538 errs() << "\nWith: ";
539 TLO.New.getNode()->dump(CurDAG);
542 if (InWorklist.insert(TLO.New.getNode()))
543 Worklist.push_back(TLO.New.getNode());
545 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
546 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
548 if (!TLO.Old.getNode()->use_empty()) continue;
550 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
552 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
553 if (OpNode->hasOneUse()) {
554 // Add OpNode to the end of the list to revisit.
555 DeadNodes.RemoveFromWorklist(OpNode);
556 Worklist.push_back(OpNode);
557 InWorklist.insert(OpNode);
561 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
562 CurDAG->DeleteNode(TLO.Old.getNode());
566 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
567 SmallPtrSet<SDNode*, 128> VisitedNodes;
568 SmallVector<SDNode*, 128> Worklist;
570 Worklist.push_back(CurDAG->getRoot().getNode());
577 SDNode *N = Worklist.pop_back_val();
579 // If we've already seen this node, ignore it.
580 if (!VisitedNodes.insert(N))
583 // Otherwise, add all chain operands to the worklist.
584 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
585 if (N->getOperand(i).getValueType() == MVT::Other)
586 Worklist.push_back(N->getOperand(i).getNode());
588 // If this is a CopyToReg with a vreg dest, process it.
589 if (N->getOpcode() != ISD::CopyToReg)
592 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
593 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
596 // Ignore non-scalar or non-integer values.
597 SDValue Src = N->getOperand(2);
598 EVT SrcVT = Src.getValueType();
599 if (!SrcVT.isInteger() || SrcVT.isVector())
602 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
603 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
604 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
606 // Only install this information if it tells us something.
607 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
608 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
609 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
610 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
611 FunctionLoweringInfo::LiveOutInfo &LOI =
612 FuncInfo->LiveOutRegInfo[DestReg];
613 LOI.NumSignBits = NumSignBits;
614 LOI.KnownOne = KnownOne;
615 LOI.KnownZero = KnownZero;
617 } while (!Worklist.empty());
620 void SelectionDAGISel::CodeGenAndEmitDAG() {
621 std::string GroupName;
622 if (TimePassesIsEnabled)
623 GroupName = "Instruction Selection and Scheduling";
624 std::string BlockName;
625 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
626 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
628 BlockName = MF->getFunction()->getNameStr() + ":" +
629 BB->getBasicBlock()->getNameStr();
631 DEBUG(dbgs() << "Initial selection DAG:\n");
632 DEBUG(CurDAG->dump());
634 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
636 // Run the DAG combiner in pre-legalize mode.
637 if (TimePassesIsEnabled) {
638 NamedRegionTimer T("DAG Combining 1", GroupName);
639 CurDAG->Combine(Unrestricted, *AA, OptLevel);
641 CurDAG->Combine(Unrestricted, *AA, OptLevel);
644 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
645 DEBUG(CurDAG->dump());
647 // Second step, hack on the DAG until it only uses operations and types that
648 // the target supports.
649 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
653 if (TimePassesIsEnabled) {
654 NamedRegionTimer T("Type Legalization", GroupName);
655 Changed = CurDAG->LegalizeTypes();
657 Changed = CurDAG->LegalizeTypes();
660 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
661 DEBUG(CurDAG->dump());
664 if (ViewDAGCombineLT)
665 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
667 // Run the DAG combiner in post-type-legalize mode.
668 if (TimePassesIsEnabled) {
669 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
670 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
672 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
675 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
676 DEBUG(CurDAG->dump());
679 if (TimePassesIsEnabled) {
680 NamedRegionTimer T("Vector Legalization", GroupName);
681 Changed = CurDAG->LegalizeVectors();
683 Changed = CurDAG->LegalizeVectors();
687 if (TimePassesIsEnabled) {
688 NamedRegionTimer T("Type Legalization 2", GroupName);
689 CurDAG->LegalizeTypes();
691 CurDAG->LegalizeTypes();
694 if (ViewDAGCombineLT)
695 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
697 // Run the DAG combiner in post-type-legalize mode.
698 if (TimePassesIsEnabled) {
699 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
700 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
702 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
705 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
706 DEBUG(CurDAG->dump());
709 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
711 if (TimePassesIsEnabled) {
712 NamedRegionTimer T("DAG Legalization", GroupName);
713 CurDAG->Legalize(OptLevel);
715 CurDAG->Legalize(OptLevel);
718 DEBUG(dbgs() << "Legalized selection DAG:\n");
719 DEBUG(CurDAG->dump());
721 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
723 // Run the DAG combiner in post-legalize mode.
724 if (TimePassesIsEnabled) {
725 NamedRegionTimer T("DAG Combining 2", GroupName);
726 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
728 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
731 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
732 DEBUG(CurDAG->dump());
734 if (OptLevel != CodeGenOpt::None) {
736 ComputeLiveOutVRegInfo();
739 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
741 // Third, instruction select all of the operations to machine code, adding the
742 // code to the MachineBasicBlock.
743 if (TimePassesIsEnabled) {
744 NamedRegionTimer T("Instruction Selection", GroupName);
745 DoInstructionSelection();
747 DoInstructionSelection();
750 DEBUG(dbgs() << "Selected selection DAG:\n");
751 DEBUG(CurDAG->dump());
753 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
755 // Schedule machine code.
756 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
757 if (TimePassesIsEnabled) {
758 NamedRegionTimer T("Instruction Scheduling", GroupName);
759 Scheduler->Run(CurDAG, BB, BB->end());
761 Scheduler->Run(CurDAG, BB, BB->end());
764 if (ViewSUnitDAGs) Scheduler->viewGraph();
766 // Emit machine code to BB. This can change 'BB' to the last block being
768 if (TimePassesIsEnabled) {
769 NamedRegionTimer T("Instruction Creation", GroupName);
770 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
772 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
775 // Free the scheduler state.
776 if (TimePassesIsEnabled) {
777 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
783 DEBUG(dbgs() << "Selected machine code:\n");
787 void SelectionDAGISel::DoInstructionSelection() {
788 DEBUG(errs() << "===== Instruction selection begins:\n");
792 // Select target instructions for the DAG.
794 // Number all nodes with a topological order and set DAGSize.
795 DAGSize = CurDAG->AssignTopologicalOrder();
797 // Create a dummy node (which is not added to allnodes), that adds
798 // a reference to the root node, preventing it from being deleted,
799 // and tracking any changes of the root.
800 HandleSDNode Dummy(CurDAG->getRoot());
801 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
804 // The AllNodes list is now topological-sorted. Visit the
805 // nodes by starting at the end of the list (the root of the
806 // graph) and preceding back toward the beginning (the entry
808 while (ISelPosition != CurDAG->allnodes_begin()) {
809 SDNode *Node = --ISelPosition;
810 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
811 // but there are currently some corner cases that it misses. Also, this
812 // makes it theoretically possible to disable the DAGCombiner.
813 if (Node->use_empty())
816 SDNode *ResNode = Select(Node);
818 // FIXME: This is pretty gross. 'Select' should be changed to not return
819 // anything at all and this code should be nuked with a tactical strike.
821 // If node should not be replaced, continue with the next one.
822 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
826 ReplaceUses(Node, ResNode);
828 // If after the replacement this node is not used any more,
829 // remove this dead node.
830 if (Node->use_empty()) { // Don't delete EntryToken, etc.
831 ISelUpdater ISU(ISelPosition);
832 CurDAG->RemoveDeadNode(Node, &ISU);
836 CurDAG->setRoot(Dummy.getValue());
838 DEBUG(errs() << "===== Instruction selection ends:\n");
840 PostprocessISelDAG();
844 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
846 MachineModuleInfo *MMI,
847 const TargetInstrInfo &TII) {
848 // Initialize the Fast-ISel state, if needed.
849 FastISel *FastIS = 0;
851 FastIS = TLI.createFastISel(MF, MMI,
854 FuncInfo->StaticAllocaMap
856 , FuncInfo->CatchInfoLost
860 // Iterate over all basic blocks in the function.
861 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
862 BasicBlock *LLVMBB = &*I;
863 BB = FuncInfo->MBBMap[LLVMBB];
865 BasicBlock::iterator const Begin = LLVMBB->begin();
866 BasicBlock::iterator const End = LLVMBB->end();
867 BasicBlock::iterator BI = Begin;
869 // Lower any arguments needed in this block if this is the entry block.
870 bool SuppressFastISel = false;
871 if (LLVMBB == &Fn.getEntryBlock()) {
872 LowerArguments(LLVMBB);
874 // If any of the arguments has the byval attribute, forgo
875 // fast-isel in the entry block.
878 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
880 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
881 if (EnableFastISelVerbose || EnableFastISelAbort)
882 dbgs() << "FastISel skips entry block due to byval argument\n";
883 SuppressFastISel = true;
889 if (MMI && BB->isLandingPad()) {
890 // Add a label to mark the beginning of the landing pad. Deletion of the
891 // landing pad can thus be detected via the MachineModuleInfo.
892 MCSymbol *Label = MMI->addLandingPad(BB);
894 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
895 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
897 // Mark exception register as live in.
898 unsigned Reg = TLI.getExceptionAddressRegister();
899 if (Reg) BB->addLiveIn(Reg);
901 // Mark exception selector register as live in.
902 Reg = TLI.getExceptionSelectorRegister();
903 if (Reg) BB->addLiveIn(Reg);
905 // FIXME: Hack around an exception handling flaw (PR1508): the personality
906 // function and list of typeids logically belong to the invoke (or, if you
907 // like, the basic block containing the invoke), and need to be associated
908 // with it in the dwarf exception handling tables. Currently however the
909 // information is provided by an intrinsic (eh.selector) that can be moved
910 // to unexpected places by the optimizers: if the unwind edge is critical,
911 // then breaking it can result in the intrinsics being in the successor of
912 // the landing pad, not the landing pad itself. This results
913 // in exceptions not being caught because no typeids are associated with
914 // the invoke. This may not be the only way things can go wrong, but it
915 // is the only way we try to work around for the moment.
916 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
918 if (Br && Br->isUnconditional()) { // Critical edge?
919 BasicBlock::iterator I, E;
920 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
921 if (isa<EHSelectorInst>(I))
925 // No catch info found - try to extract some from the successor.
926 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
930 // Before doing SelectionDAG ISel, see if FastISel has been requested.
931 if (FastIS && !SuppressFastISel) {
932 // Emit code for any incoming arguments. This must happen before
933 // beginning FastISel on the entry block.
934 if (LLVMBB == &Fn.getEntryBlock()) {
935 CurDAG->setRoot(SDB->getControlRoot());
939 FastIS->startNewBlock(BB);
940 // Do FastISel on as many instructions as possible.
941 for (; BI != End; ++BI) {
942 // Just before the terminator instruction, insert instructions to
943 // feed PHI nodes in successor blocks.
944 if (isa<TerminatorInst>(BI))
945 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
946 ++NumFastIselFailures;
947 ResetDebugLoc(SDB, FastIS);
948 if (EnableFastISelVerbose || EnableFastISelAbort) {
949 dbgs() << "FastISel miss: ";
952 assert(!EnableFastISelAbort &&
953 "FastISel didn't handle a PHI in a successor");
957 SetDebugLoc(BI, SDB, FastIS, &MF);
959 // Try to select the instruction with FastISel.
960 if (FastIS->SelectInstruction(BI)) {
961 ResetDebugLoc(SDB, FastIS);
965 // Clear out the debug location so that it doesn't carry over to
966 // unrelated instructions.
967 ResetDebugLoc(SDB, FastIS);
969 // Then handle certain instructions as single-LLVM-Instruction blocks.
970 if (isa<CallInst>(BI)) {
971 ++NumFastIselFailures;
972 if (EnableFastISelVerbose || EnableFastISelAbort) {
973 dbgs() << "FastISel missed call: ";
977 if (!BI->getType()->isVoidTy()) {
978 unsigned &R = FuncInfo->ValueMap[BI];
980 R = FuncInfo->CreateRegForValue(BI);
983 bool HadTailCall = false;
984 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
986 // If the call was emitted as a tail call, we're done with the block.
992 // If the instruction was codegen'd with multiple blocks,
993 // inform the FastISel object where to resume inserting.
994 FastIS->setCurrentBlock(BB);
998 // Otherwise, give up on FastISel for the rest of the block.
999 // For now, be a little lenient about non-branch terminators.
1000 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
1001 ++NumFastIselFailures;
1002 if (EnableFastISelVerbose || EnableFastISelAbort) {
1003 dbgs() << "FastISel miss: ";
1006 if (EnableFastISelAbort)
1007 // The "fast" selector couldn't handle something and bailed.
1008 // For the purpose of debugging, just abort.
1009 llvm_unreachable("FastISel didn't select the entire block");
1015 // Run SelectionDAG instruction selection on the remainder of the block
1016 // not handled by FastISel. If FastISel is not run, this is the entire
1020 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
1030 SelectionDAGISel::FinishBasicBlock() {
1032 DEBUG(dbgs() << "Target-post-processed machine code:\n");
1035 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1036 << SDB->PHINodesToUpdate.size() << "\n");
1037 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
1038 dbgs() << "Node " << i << " : ("
1039 << SDB->PHINodesToUpdate[i].first
1040 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
1042 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1043 // PHI nodes in successors.
1044 if (SDB->SwitchCases.empty() &&
1045 SDB->JTCases.empty() &&
1046 SDB->BitTestCases.empty()) {
1047 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1048 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1049 assert(PHI->isPHI() &&
1050 "This is not a machine PHI node that we are updating!");
1051 if (!BB->isSuccessor(PHI->getParent()))
1053 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1055 PHI->addOperand(MachineOperand::CreateMBB(BB));
1057 SDB->PHINodesToUpdate.clear();
1061 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1062 // Lower header first, if it wasn't already lowered
1063 if (!SDB->BitTestCases[i].Emitted) {
1064 // Set the current basic block to the mbb we wish to insert the code into
1065 BB = SDB->BitTestCases[i].Parent;
1066 SDB->setCurrentBasicBlock(BB);
1068 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
1069 CurDAG->setRoot(SDB->getRoot());
1070 CodeGenAndEmitDAG();
1074 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1075 // Set the current basic block to the mbb we wish to insert the code into
1076 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
1077 SDB->setCurrentBasicBlock(BB);
1080 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1081 SDB->BitTestCases[i].Reg,
1082 SDB->BitTestCases[i].Cases[j]);
1084 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1085 SDB->BitTestCases[i].Reg,
1086 SDB->BitTestCases[i].Cases[j]);
1089 CurDAG->setRoot(SDB->getRoot());
1090 CodeGenAndEmitDAG();
1095 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1096 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1097 MachineBasicBlock *PHIBB = PHI->getParent();
1098 assert(PHI->isPHI() &&
1099 "This is not a machine PHI node that we are updating!");
1100 // This is "default" BB. We have two jumps to it. From "header" BB and
1101 // from last "case" BB.
1102 if (PHIBB == SDB->BitTestCases[i].Default) {
1103 PHI->addOperand(MachineOperand::
1104 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1105 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1106 PHI->addOperand(MachineOperand::
1107 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1108 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1111 // One of "cases" BB.
1112 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1114 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1115 if (cBB->isSuccessor(PHIBB)) {
1116 PHI->addOperand(MachineOperand::
1117 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1118 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1123 SDB->BitTestCases.clear();
1125 // If the JumpTable record is filled in, then we need to emit a jump table.
1126 // Updating the PHI nodes is tricky in this case, since we need to determine
1127 // whether the PHI is a successor of the range check MBB or the jump table MBB
1128 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1129 // Lower header first, if it wasn't already lowered
1130 if (!SDB->JTCases[i].first.Emitted) {
1131 // Set the current basic block to the mbb we wish to insert the code into
1132 BB = SDB->JTCases[i].first.HeaderBB;
1133 SDB->setCurrentBasicBlock(BB);
1135 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1136 CurDAG->setRoot(SDB->getRoot());
1137 CodeGenAndEmitDAG();
1141 // Set the current basic block to the mbb we wish to insert the code into
1142 BB = SDB->JTCases[i].second.MBB;
1143 SDB->setCurrentBasicBlock(BB);
1145 SDB->visitJumpTable(SDB->JTCases[i].second);
1146 CurDAG->setRoot(SDB->getRoot());
1147 CodeGenAndEmitDAG();
1151 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1152 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1153 MachineBasicBlock *PHIBB = PHI->getParent();
1154 assert(PHI->isPHI() &&
1155 "This is not a machine PHI node that we are updating!");
1156 // "default" BB. We can go there only from header BB.
1157 if (PHIBB == SDB->JTCases[i].second.Default) {
1159 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1161 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1163 // JT BB. Just iterate over successors here
1164 if (BB->isSuccessor(PHIBB)) {
1166 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1167 PHI->addOperand(MachineOperand::CreateMBB(BB));
1171 SDB->JTCases.clear();
1173 // If the switch block involved a branch to one of the actual successors, we
1174 // need to update PHI nodes in that block.
1175 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1176 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1177 assert(PHI->isPHI() &&
1178 "This is not a machine PHI node that we are updating!");
1179 if (BB->isSuccessor(PHI->getParent())) {
1180 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1182 PHI->addOperand(MachineOperand::CreateMBB(BB));
1186 // If we generated any switch lowering information, build and codegen any
1187 // additional DAGs necessary.
1188 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1189 // Set the current basic block to the mbb we wish to insert the code into
1190 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1191 SDB->setCurrentBasicBlock(BB);
1194 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1195 CurDAG->setRoot(SDB->getRoot());
1196 CodeGenAndEmitDAG();
1198 // Handle any PHI nodes in successors of this chunk, as if we were coming
1199 // from the original BB before switch expansion. Note that PHI nodes can
1200 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1201 // handle them the right number of times.
1202 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1203 // If new BB's are created during scheduling, the edges may have been
1204 // updated. That is, the edge from ThisBB to BB may have been split and
1205 // BB's predecessor is now another block.
1206 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1207 SDB->EdgeMapping.find(BB);
1208 if (EI != SDB->EdgeMapping.end())
1209 ThisBB = EI->second;
1211 // BB may have been removed from the CFG if a branch was constant folded.
1212 if (ThisBB->isSuccessor(BB)) {
1213 for (MachineBasicBlock::iterator Phi = BB->begin();
1214 Phi != BB->end() && Phi->isPHI();
1216 // This value for this PHI node is recorded in PHINodesToUpdate.
1217 for (unsigned pn = 0; ; ++pn) {
1218 assert(pn != SDB->PHINodesToUpdate.size() &&
1219 "Didn't find PHI entry!");
1220 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1221 Phi->addOperand(MachineOperand::
1222 CreateReg(SDB->PHINodesToUpdate[pn].second,
1224 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1231 // Don't process RHS if same block as LHS.
1232 if (BB == SDB->SwitchCases[i].FalseBB)
1233 SDB->SwitchCases[i].FalseBB = 0;
1235 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1236 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1237 SDB->SwitchCases[i].FalseBB = 0;
1239 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1242 SDB->SwitchCases.clear();
1244 SDB->PHINodesToUpdate.clear();
1248 /// Create the scheduler. If a specific scheduler was specified
1249 /// via the SchedulerRegistry, use it, otherwise select the
1250 /// one preferred by the target.
1252 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1253 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1257 RegisterScheduler::setDefault(Ctor);
1260 return Ctor(this, OptLevel);
1263 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1264 return new ScheduleHazardRecognizer();
1267 //===----------------------------------------------------------------------===//
1268 // Helper functions used by the generated instruction selector.
1269 //===----------------------------------------------------------------------===//
1270 // Calls to these methods are generated by tblgen.
1272 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1273 /// the dag combiner simplified the 255, we still want to match. RHS is the
1274 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1275 /// specified in the .td file (e.g. 255).
1276 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1277 int64_t DesiredMaskS) const {
1278 const APInt &ActualMask = RHS->getAPIntValue();
1279 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1281 // If the actual mask exactly matches, success!
1282 if (ActualMask == DesiredMask)
1285 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1286 if (ActualMask.intersects(~DesiredMask))
1289 // Otherwise, the DAG Combiner may have proven that the value coming in is
1290 // either already zero or is not demanded. Check for known zero input bits.
1291 APInt NeededMask = DesiredMask & ~ActualMask;
1292 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1295 // TODO: check to see if missing bits are just not demanded.
1297 // Otherwise, this pattern doesn't match.
1301 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1302 /// the dag combiner simplified the 255, we still want to match. RHS is the
1303 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1304 /// specified in the .td file (e.g. 255).
1305 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1306 int64_t DesiredMaskS) const {
1307 const APInt &ActualMask = RHS->getAPIntValue();
1308 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1310 // If the actual mask exactly matches, success!
1311 if (ActualMask == DesiredMask)
1314 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1315 if (ActualMask.intersects(~DesiredMask))
1318 // Otherwise, the DAG Combiner may have proven that the value coming in is
1319 // either already zero or is not demanded. Check for known zero input bits.
1320 APInt NeededMask = DesiredMask & ~ActualMask;
1322 APInt KnownZero, KnownOne;
1323 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1325 // If all the missing bits in the or are already known to be set, match!
1326 if ((NeededMask & KnownOne) == NeededMask)
1329 // TODO: check to see if missing bits are just not demanded.
1331 // Otherwise, this pattern doesn't match.
1336 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1337 /// by tblgen. Others should not call it.
1338 void SelectionDAGISel::
1339 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1340 std::vector<SDValue> InOps;
1341 std::swap(InOps, Ops);
1343 Ops.push_back(InOps[0]); // input chain.
1344 Ops.push_back(InOps[1]); // input asm string.
1346 unsigned i = 2, e = InOps.size();
1347 if (InOps[e-1].getValueType() == MVT::Flag)
1348 --e; // Don't process a flag operand if it is here.
1351 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1352 if ((Flags & 7) != 4 /*MEM*/) {
1353 // Just skip over this operand, copying the operands verbatim.
1354 Ops.insert(Ops.end(), InOps.begin()+i,
1355 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1356 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1358 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1359 "Memory operand with multiple values?");
1360 // Otherwise, this is a memory operand. Ask the target to select it.
1361 std::vector<SDValue> SelOps;
1362 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1363 llvm_report_error("Could not match memory address. Inline asm"
1367 // Add this to the output node.
1368 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1370 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1375 // Add the flag input back if present.
1376 if (e != InOps.size())
1377 Ops.push_back(InOps.back());
1380 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1383 static SDNode *findFlagUse(SDNode *N) {
1384 unsigned FlagResNo = N->getNumValues()-1;
1385 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1386 SDUse &Use = I.getUse();
1387 if (Use.getResNo() == FlagResNo)
1388 return Use.getUser();
1393 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1394 /// This function recursively traverses up the operand chain, ignoring
1396 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1397 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1398 bool IgnoreChains) {
1399 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1400 // greater than all of its (recursive) operands. If we scan to a point where
1401 // 'use' is smaller than the node we're scanning for, then we know we will
1404 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1405 // happen because we scan down to newly selected nodes in the case of flag
1407 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1410 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1411 // won't fail if we scan it again.
1412 if (!Visited.insert(Use))
1415 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1416 // Ignore chain uses, they are validated by HandleMergeInputChains.
1417 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1420 SDNode *N = Use->getOperand(i).getNode();
1422 if (Use == ImmedUse || Use == Root)
1423 continue; // We are not looking for immediate use.
1428 // Traverse up the operand chain.
1429 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1435 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1436 /// operand node N of U during instruction selection that starts at Root.
1437 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1438 SDNode *Root) const {
1439 if (OptLevel == CodeGenOpt::None) return false;
1440 return N.hasOneUse();
1443 /// IsLegalToFold - Returns true if the specific operand node N of
1444 /// U can be folded during instruction selection that starts at Root.
1445 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1446 bool IgnoreChains) const {
1447 if (OptLevel == CodeGenOpt::None) return false;
1449 // If Root use can somehow reach N through a path that that doesn't contain
1450 // U then folding N would create a cycle. e.g. In the following
1451 // diagram, Root can reach N through X. If N is folded into into Root, then
1452 // X is both a predecessor and a successor of U.
1463 // * indicates nodes to be folded together.
1465 // If Root produces a flag, then it gets (even more) interesting. Since it
1466 // will be "glued" together with its flag use in the scheduler, we need to
1467 // check if it might reach N.
1486 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1487 // (call it Fold), then X is a predecessor of FU and a successor of
1488 // Fold. But since Fold and FU are flagged together, this will create
1489 // a cycle in the scheduling graph.
1491 // If the node has flags, walk down the graph to the "lowest" node in the
1493 EVT VT = Root->getValueType(Root->getNumValues()-1);
1494 while (VT == MVT::Flag) {
1495 SDNode *FU = findFlagUse(Root);
1499 VT = Root->getValueType(Root->getNumValues()-1);
1501 // If our query node has a flag result with a use, we've walked up it. If
1502 // the user (which has already been selected) has a chain or indirectly uses
1503 // the chain, our WalkChainUsers predicate will not consider it. Because of
1504 // this, we cannot ignore chains in this predicate.
1505 IgnoreChains = false;
1509 SmallPtrSet<SDNode*, 16> Visited;
1510 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1513 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1514 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1515 SelectInlineAsmMemoryOperands(Ops);
1517 std::vector<EVT> VTs;
1518 VTs.push_back(MVT::Other);
1519 VTs.push_back(MVT::Flag);
1520 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1521 VTs, &Ops[0], Ops.size());
1523 return New.getNode();
1526 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1527 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1530 /// GetVBR - decode a vbr encoding whose top bit is set.
1531 ALWAYS_INLINE static uint64_t
1532 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1533 assert(Val >= 128 && "Not a VBR");
1534 Val &= 127; // Remove first vbr bit.
1539 NextBits = MatcherTable[Idx++];
1540 Val |= (NextBits&127) << Shift;
1542 } while (NextBits & 128);
1548 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1549 /// interior flag and chain results to use the new flag and chain results.
1550 void SelectionDAGISel::
1551 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1552 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1554 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1555 bool isMorphNodeTo) {
1556 SmallVector<SDNode*, 4> NowDeadNodes;
1558 ISelUpdater ISU(ISelPosition);
1560 // Now that all the normal results are replaced, we replace the chain and
1561 // flag results if present.
1562 if (!ChainNodesMatched.empty()) {
1563 assert(InputChain.getNode() != 0 &&
1564 "Matched input chains but didn't produce a chain");
1565 // Loop over all of the nodes we matched that produced a chain result.
1566 // Replace all the chain results with the final chain we ended up with.
1567 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1568 SDNode *ChainNode = ChainNodesMatched[i];
1570 // If this node was already deleted, don't look at it.
1571 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1574 // Don't replace the results of the root node if we're doing a
1576 if (ChainNode == NodeToMatch && isMorphNodeTo)
1579 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1580 if (ChainVal.getValueType() == MVT::Flag)
1581 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1582 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1583 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1585 // If the node became dead and we haven't already seen it, delete it.
1586 if (ChainNode->use_empty() &&
1587 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1588 NowDeadNodes.push_back(ChainNode);
1592 // If the result produces a flag, update any flag results in the matched
1593 // pattern with the flag result.
1594 if (InputFlag.getNode() != 0) {
1595 // Handle any interior nodes explicitly marked.
1596 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1597 SDNode *FRN = FlagResultNodesMatched[i];
1599 // If this node was already deleted, don't look at it.
1600 if (FRN->getOpcode() == ISD::DELETED_NODE)
1603 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1604 "Doesn't have a flag result");
1605 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1608 // If the node became dead and we haven't already seen it, delete it.
1609 if (FRN->use_empty() &&
1610 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1611 NowDeadNodes.push_back(FRN);
1615 if (!NowDeadNodes.empty())
1616 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1618 DEBUG(errs() << "ISEL: Match complete!\n");
1624 CR_LeadsToInteriorNode
1627 /// WalkChainUsers - Walk down the users of the specified chained node that is
1628 /// part of the pattern we're matching, looking at all of the users we find.
1629 /// This determines whether something is an interior node, whether we have a
1630 /// non-pattern node in between two pattern nodes (which prevent folding because
1631 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1632 /// between pattern nodes (in which case the TF becomes part of the pattern).
1634 /// The walk we do here is guaranteed to be small because we quickly get down to
1635 /// already selected nodes "below" us.
1637 WalkChainUsers(SDNode *ChainedNode,
1638 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1639 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1640 ChainResult Result = CR_Simple;
1642 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1643 E = ChainedNode->use_end(); UI != E; ++UI) {
1644 // Make sure the use is of the chain, not some other value we produce.
1645 if (UI.getUse().getValueType() != MVT::Other) continue;
1649 // If we see an already-selected machine node, then we've gone beyond the
1650 // pattern that we're selecting down into the already selected chunk of the
1652 if (User->isMachineOpcode() ||
1653 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1656 if (User->getOpcode() == ISD::CopyToReg ||
1657 User->getOpcode() == ISD::CopyFromReg ||
1658 User->getOpcode() == ISD::INLINEASM ||
1659 User->getOpcode() == ISD::EH_LABEL) {
1660 // If their node ID got reset to -1 then they've already been selected.
1661 // Treat them like a MachineOpcode.
1662 if (User->getNodeId() == -1)
1666 // If we have a TokenFactor, we handle it specially.
1667 if (User->getOpcode() != ISD::TokenFactor) {
1668 // If the node isn't a token factor and isn't part of our pattern, then it
1669 // must be a random chained node in between two nodes we're selecting.
1670 // This happens when we have something like:
1675 // Because we structurally match the load/store as a read/modify/write,
1676 // but the call is chained between them. We cannot fold in this case
1677 // because it would induce a cycle in the graph.
1678 if (!std::count(ChainedNodesInPattern.begin(),
1679 ChainedNodesInPattern.end(), User))
1680 return CR_InducesCycle;
1682 // Otherwise we found a node that is part of our pattern. For example in:
1686 // This would happen when we're scanning down from the load and see the
1687 // store as a user. Record that there is a use of ChainedNode that is
1688 // part of the pattern and keep scanning uses.
1689 Result = CR_LeadsToInteriorNode;
1690 InteriorChainedNodes.push_back(User);
1694 // If we found a TokenFactor, there are two cases to consider: first if the
1695 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1696 // uses of the TF are in our pattern) we just want to ignore it. Second,
1697 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1703 // | \ DAG's like cheese
1706 // [TokenFactor] [Op]
1713 // In this case, the TokenFactor becomes part of our match and we rewrite it
1714 // as a new TokenFactor.
1716 // To distinguish these two cases, do a recursive walk down the uses.
1717 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1719 // If the uses of the TokenFactor are just already-selected nodes, ignore
1720 // it, it is "below" our pattern.
1722 case CR_InducesCycle:
1723 // If the uses of the TokenFactor lead to nodes that are not part of our
1724 // pattern that are not selected, folding would turn this into a cycle,
1726 return CR_InducesCycle;
1727 case CR_LeadsToInteriorNode:
1728 break; // Otherwise, keep processing.
1731 // Okay, we know we're in the interesting interior case. The TokenFactor
1732 // is now going to be considered part of the pattern so that we rewrite its
1733 // uses (it may have uses that are not part of the pattern) with the
1734 // ultimate chain result of the generated code. We will also add its chain
1735 // inputs as inputs to the ultimate TokenFactor we create.
1736 Result = CR_LeadsToInteriorNode;
1737 ChainedNodesInPattern.push_back(User);
1738 InteriorChainedNodes.push_back(User);
1745 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1746 /// operation for when the pattern matched at least one node with a chains. The
1747 /// input vector contains a list of all of the chained nodes that we match. We
1748 /// must determine if this is a valid thing to cover (i.e. matching it won't
1749 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1750 /// be used as the input node chain for the generated nodes.
1752 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1753 SelectionDAG *CurDAG) {
1754 // Walk all of the chained nodes we've matched, recursively scanning down the
1755 // users of the chain result. This adds any TokenFactor nodes that are caught
1756 // in between chained nodes to the chained and interior nodes list.
1757 SmallVector<SDNode*, 3> InteriorChainedNodes;
1758 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1759 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1760 InteriorChainedNodes) == CR_InducesCycle)
1761 return SDValue(); // Would induce a cycle.
1764 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1765 // that we are interested in. Form our input TokenFactor node.
1766 SmallVector<SDValue, 3> InputChains;
1767 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1768 // Add the input chain of this node to the InputChains list (which will be
1769 // the operands of the generated TokenFactor) if it's not an interior node.
1770 SDNode *N = ChainNodesMatched[i];
1771 if (N->getOpcode() != ISD::TokenFactor) {
1772 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1775 // Otherwise, add the input chain.
1776 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1777 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1778 InputChains.push_back(InChain);
1782 // If we have a token factor, we want to add all inputs of the token factor
1783 // that are not part of the pattern we're matching.
1784 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1785 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1786 N->getOperand(op).getNode()))
1787 InputChains.push_back(N->getOperand(op));
1792 if (InputChains.size() == 1)
1793 return InputChains[0];
1794 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1795 MVT::Other, &InputChains[0], InputChains.size());
1798 /// MorphNode - Handle morphing a node in place for the selector.
1799 SDNode *SelectionDAGISel::
1800 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1801 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1802 // It is possible we're using MorphNodeTo to replace a node with no
1803 // normal results with one that has a normal result (or we could be
1804 // adding a chain) and the input could have flags and chains as well.
1805 // In this case we need to shift the operands down.
1806 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1807 // than the old isel though.
1808 int OldFlagResultNo = -1, OldChainResultNo = -1;
1810 unsigned NTMNumResults = Node->getNumValues();
1811 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1812 OldFlagResultNo = NTMNumResults-1;
1813 if (NTMNumResults != 1 &&
1814 Node->getValueType(NTMNumResults-2) == MVT::Other)
1815 OldChainResultNo = NTMNumResults-2;
1816 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1817 OldChainResultNo = NTMNumResults-1;
1819 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1820 // that this deletes operands of the old node that become dead.
1821 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1823 // MorphNodeTo can operate in two ways: if an existing node with the
1824 // specified operands exists, it can just return it. Otherwise, it
1825 // updates the node in place to have the requested operands.
1827 // If we updated the node in place, reset the node ID. To the isel,
1828 // this should be just like a newly allocated machine node.
1832 unsigned ResNumResults = Res->getNumValues();
1833 // Move the flag if needed.
1834 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1835 (unsigned)OldFlagResultNo != ResNumResults-1)
1836 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1837 SDValue(Res, ResNumResults-1));
1839 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1842 // Move the chain reference if needed.
1843 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1844 (unsigned)OldChainResultNo != ResNumResults-1)
1845 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1846 SDValue(Res, ResNumResults-1));
1848 // Otherwise, no replacement happened because the node already exists. Replace
1849 // Uses of the old node with the new one.
1851 CurDAG->ReplaceAllUsesWith(Node, Res);
1856 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1857 ALWAYS_INLINE static bool
1858 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1859 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1860 // Accept if it is exactly the same as a previously recorded node.
1861 unsigned RecNo = MatcherTable[MatcherIndex++];
1862 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1863 return N == RecordedNodes[RecNo];
1866 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1867 ALWAYS_INLINE static bool
1868 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1869 SelectionDAGISel &SDISel) {
1870 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1873 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1874 ALWAYS_INLINE static bool
1875 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1876 SelectionDAGISel &SDISel, SDNode *N) {
1877 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1880 ALWAYS_INLINE static bool
1881 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1883 uint16_t Opc = MatcherTable[MatcherIndex++];
1884 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1885 return N->getOpcode() == Opc;
1888 ALWAYS_INLINE static bool
1889 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1890 SDValue N, const TargetLowering &TLI) {
1891 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1892 if (N.getValueType() == VT) return true;
1894 // Handle the case when VT is iPTR.
1895 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1898 ALWAYS_INLINE static bool
1899 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1900 SDValue N, const TargetLowering &TLI,
1902 if (ChildNo >= N.getNumOperands())
1903 return false; // Match fails if out of range child #.
1904 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1908 ALWAYS_INLINE static bool
1909 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1911 return cast<CondCodeSDNode>(N)->get() ==
1912 (ISD::CondCode)MatcherTable[MatcherIndex++];
1915 ALWAYS_INLINE static bool
1916 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1917 SDValue N, const TargetLowering &TLI) {
1918 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1919 if (cast<VTSDNode>(N)->getVT() == VT)
1922 // Handle the case when VT is iPTR.
1923 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1926 ALWAYS_INLINE static bool
1927 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1929 int64_t Val = MatcherTable[MatcherIndex++];
1931 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1933 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1934 return C != 0 && C->getSExtValue() == Val;
1937 ALWAYS_INLINE static bool
1938 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1939 SDValue N, SelectionDAGISel &SDISel) {
1940 int64_t Val = MatcherTable[MatcherIndex++];
1942 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1944 if (N->getOpcode() != ISD::AND) return false;
1946 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1947 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1950 ALWAYS_INLINE static bool
1951 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1952 SDValue N, SelectionDAGISel &SDISel) {
1953 int64_t Val = MatcherTable[MatcherIndex++];
1955 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1957 if (N->getOpcode() != ISD::OR) return false;
1959 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1960 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1963 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1964 /// scope, evaluate the current node. If the current predicate is known to
1965 /// fail, set Result=true and return anything. If the current predicate is
1966 /// known to pass, set Result=false and return the MatcherIndex to continue
1967 /// with. If the current predicate is unknown, set Result=false and return the
1968 /// MatcherIndex to continue with.
1969 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1970 unsigned Index, SDValue N,
1971 bool &Result, SelectionDAGISel &SDISel,
1972 SmallVectorImpl<SDValue> &RecordedNodes){
1973 switch (Table[Index++]) {
1976 return Index-1; // Could not evaluate this predicate.
1977 case SelectionDAGISel::OPC_CheckSame:
1978 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1980 case SelectionDAGISel::OPC_CheckPatternPredicate:
1981 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1983 case SelectionDAGISel::OPC_CheckPredicate:
1984 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1986 case SelectionDAGISel::OPC_CheckOpcode:
1987 Result = !::CheckOpcode(Table, Index, N.getNode());
1989 case SelectionDAGISel::OPC_CheckType:
1990 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1992 case SelectionDAGISel::OPC_CheckChild0Type:
1993 case SelectionDAGISel::OPC_CheckChild1Type:
1994 case SelectionDAGISel::OPC_CheckChild2Type:
1995 case SelectionDAGISel::OPC_CheckChild3Type:
1996 case SelectionDAGISel::OPC_CheckChild4Type:
1997 case SelectionDAGISel::OPC_CheckChild5Type:
1998 case SelectionDAGISel::OPC_CheckChild6Type:
1999 case SelectionDAGISel::OPC_CheckChild7Type:
2000 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2001 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2003 case SelectionDAGISel::OPC_CheckCondCode:
2004 Result = !::CheckCondCode(Table, Index, N);
2006 case SelectionDAGISel::OPC_CheckValueType:
2007 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2009 case SelectionDAGISel::OPC_CheckInteger:
2010 Result = !::CheckInteger(Table, Index, N);
2012 case SelectionDAGISel::OPC_CheckAndImm:
2013 Result = !::CheckAndImm(Table, Index, N, SDISel);
2015 case SelectionDAGISel::OPC_CheckOrImm:
2016 Result = !::CheckOrImm(Table, Index, N, SDISel);
2023 /// FailIndex - If this match fails, this is the index to continue with.
2026 /// NodeStack - The node stack when the scope was formed.
2027 SmallVector<SDValue, 4> NodeStack;
2029 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2030 unsigned NumRecordedNodes;
2032 /// NumMatchedMemRefs - The number of matched memref entries.
2033 unsigned NumMatchedMemRefs;
2035 /// InputChain/InputFlag - The current chain/flag
2036 SDValue InputChain, InputFlag;
2038 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2039 bool HasChainNodesMatched, HasFlagResultNodesMatched;
2042 SDNode *SelectionDAGISel::
2043 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2044 unsigned TableSize) {
2045 // FIXME: Should these even be selected? Handle these cases in the caller?
2046 switch (NodeToMatch->getOpcode()) {
2049 case ISD::EntryToken: // These nodes remain the same.
2050 case ISD::BasicBlock:
2052 //case ISD::VALUETYPE:
2053 //case ISD::CONDCODE:
2054 case ISD::HANDLENODE:
2055 case ISD::TargetConstant:
2056 case ISD::TargetConstantFP:
2057 case ISD::TargetConstantPool:
2058 case ISD::TargetFrameIndex:
2059 case ISD::TargetExternalSymbol:
2060 case ISD::TargetBlockAddress:
2061 case ISD::TargetJumpTable:
2062 case ISD::TargetGlobalTLSAddress:
2063 case ISD::TargetGlobalAddress:
2064 case ISD::TokenFactor:
2065 case ISD::CopyFromReg:
2066 case ISD::CopyToReg:
2068 NodeToMatch->setNodeId(-1); // Mark selected.
2070 case ISD::AssertSext:
2071 case ISD::AssertZext:
2072 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2073 NodeToMatch->getOperand(0));
2075 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2076 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2079 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2081 // Set up the node stack with NodeToMatch as the only node on the stack.
2082 SmallVector<SDValue, 8> NodeStack;
2083 SDValue N = SDValue(NodeToMatch, 0);
2084 NodeStack.push_back(N);
2086 // MatchScopes - Scopes used when matching, if a match failure happens, this
2087 // indicates where to continue checking.
2088 SmallVector<MatchScope, 8> MatchScopes;
2090 // RecordedNodes - This is the set of nodes that have been recorded by the
2092 SmallVector<SDValue, 8> RecordedNodes;
2094 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2096 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2098 // These are the current input chain and flag for use when generating nodes.
2099 // Various Emit operations change these. For example, emitting a copytoreg
2100 // uses and updates these.
2101 SDValue InputChain, InputFlag;
2103 // ChainNodesMatched - If a pattern matches nodes that have input/output
2104 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2105 // which ones they are. The result is captured into this list so that we can
2106 // update the chain results when the pattern is complete.
2107 SmallVector<SDNode*, 3> ChainNodesMatched;
2108 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2110 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2111 NodeToMatch->dump(CurDAG);
2114 // Determine where to start the interpreter. Normally we start at opcode #0,
2115 // but if the state machine starts with an OPC_SwitchOpcode, then we
2116 // accelerate the first lookup (which is guaranteed to be hot) with the
2117 // OpcodeOffset table.
2118 unsigned MatcherIndex = 0;
2120 if (!OpcodeOffset.empty()) {
2121 // Already computed the OpcodeOffset table, just index into it.
2122 if (N.getOpcode() < OpcodeOffset.size())
2123 MatcherIndex = OpcodeOffset[N.getOpcode()];
2124 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2126 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2127 // Otherwise, the table isn't computed, but the state machine does start
2128 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2129 // is the first time we're selecting an instruction.
2132 // Get the size of this case.
2133 unsigned CaseSize = MatcherTable[Idx++];
2135 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2136 if (CaseSize == 0) break;
2138 // Get the opcode, add the index to the table.
2139 uint16_t Opc = MatcherTable[Idx++];
2140 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2141 if (Opc >= OpcodeOffset.size())
2142 OpcodeOffset.resize((Opc+1)*2);
2143 OpcodeOffset[Opc] = Idx;
2147 // Okay, do the lookup for the first opcode.
2148 if (N.getOpcode() < OpcodeOffset.size())
2149 MatcherIndex = OpcodeOffset[N.getOpcode()];
2153 assert(MatcherIndex < TableSize && "Invalid index");
2155 unsigned CurrentOpcodeIndex = MatcherIndex;
2157 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2160 // Okay, the semantics of this operation are that we should push a scope
2161 // then evaluate the first child. However, pushing a scope only to have
2162 // the first check fail (which then pops it) is inefficient. If we can
2163 // determine immediately that the first check (or first several) will
2164 // immediately fail, don't even bother pushing a scope for them.
2168 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2169 if (NumToSkip & 128)
2170 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2171 // Found the end of the scope with no match.
2172 if (NumToSkip == 0) {
2177 FailIndex = MatcherIndex+NumToSkip;
2179 unsigned MatcherIndexOfPredicate = MatcherIndex;
2180 (void)MatcherIndexOfPredicate; // silence warning.
2182 // If we can't evaluate this predicate without pushing a scope (e.g. if
2183 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2184 // push the scope and evaluate the full predicate chain.
2186 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2187 Result, *this, RecordedNodes);
2191 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2192 << "index " << MatcherIndexOfPredicate
2193 << ", continuing at " << FailIndex << "\n");
2194 ++NumDAGIselRetries;
2196 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2197 // move to the next case.
2198 MatcherIndex = FailIndex;
2201 // If the whole scope failed to match, bail.
2202 if (FailIndex == 0) break;
2204 // Push a MatchScope which indicates where to go if the first child fails
2206 MatchScope NewEntry;
2207 NewEntry.FailIndex = FailIndex;
2208 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2209 NewEntry.NumRecordedNodes = RecordedNodes.size();
2210 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2211 NewEntry.InputChain = InputChain;
2212 NewEntry.InputFlag = InputFlag;
2213 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2214 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2215 MatchScopes.push_back(NewEntry);
2218 case OPC_RecordNode:
2219 // Remember this node, it may end up being an operand in the pattern.
2220 RecordedNodes.push_back(N);
2223 case OPC_RecordChild0: case OPC_RecordChild1:
2224 case OPC_RecordChild2: case OPC_RecordChild3:
2225 case OPC_RecordChild4: case OPC_RecordChild5:
2226 case OPC_RecordChild6: case OPC_RecordChild7: {
2227 unsigned ChildNo = Opcode-OPC_RecordChild0;
2228 if (ChildNo >= N.getNumOperands())
2229 break; // Match fails if out of range child #.
2231 RecordedNodes.push_back(N->getOperand(ChildNo));
2234 case OPC_RecordMemRef:
2235 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2238 case OPC_CaptureFlagInput:
2239 // If the current node has an input flag, capture it in InputFlag.
2240 if (N->getNumOperands() != 0 &&
2241 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2242 InputFlag = N->getOperand(N->getNumOperands()-1);
2245 case OPC_MoveChild: {
2246 unsigned ChildNo = MatcherTable[MatcherIndex++];
2247 if (ChildNo >= N.getNumOperands())
2248 break; // Match fails if out of range child #.
2249 N = N.getOperand(ChildNo);
2250 NodeStack.push_back(N);
2254 case OPC_MoveParent:
2255 // Pop the current node off the NodeStack.
2256 NodeStack.pop_back();
2257 assert(!NodeStack.empty() && "Node stack imbalance!");
2258 N = NodeStack.back();
2262 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2264 case OPC_CheckPatternPredicate:
2265 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2267 case OPC_CheckPredicate:
2268 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2272 case OPC_CheckComplexPat: {
2273 unsigned CPNum = MatcherTable[MatcherIndex++];
2274 unsigned RecNo = MatcherTable[MatcherIndex++];
2275 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2276 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2281 case OPC_CheckOpcode:
2282 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2286 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2289 case OPC_SwitchOpcode: {
2290 unsigned CurNodeOpcode = N.getOpcode();
2291 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2294 // Get the size of this case.
2295 CaseSize = MatcherTable[MatcherIndex++];
2297 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2298 if (CaseSize == 0) break;
2300 uint16_t Opc = MatcherTable[MatcherIndex++];
2301 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2303 // If the opcode matches, then we will execute this case.
2304 if (CurNodeOpcode == Opc)
2307 // Otherwise, skip over this case.
2308 MatcherIndex += CaseSize;
2311 // If no cases matched, bail out.
2312 if (CaseSize == 0) break;
2314 // Otherwise, execute the case we found.
2315 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2316 << " to " << MatcherIndex << "\n");
2320 case OPC_SwitchType: {
2321 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2322 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2325 // Get the size of this case.
2326 CaseSize = MatcherTable[MatcherIndex++];
2328 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2329 if (CaseSize == 0) break;
2331 MVT::SimpleValueType CaseVT =
2332 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2333 if (CaseVT == MVT::iPTR)
2334 CaseVT = TLI.getPointerTy().SimpleTy;
2336 // If the VT matches, then we will execute this case.
2337 if (CurNodeVT == CaseVT)
2340 // Otherwise, skip over this case.
2341 MatcherIndex += CaseSize;
2344 // If no cases matched, bail out.
2345 if (CaseSize == 0) break;
2347 // Otherwise, execute the case we found.
2348 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2349 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2352 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2353 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2354 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2355 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2356 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2357 Opcode-OPC_CheckChild0Type))
2360 case OPC_CheckCondCode:
2361 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2363 case OPC_CheckValueType:
2364 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2366 case OPC_CheckInteger:
2367 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2369 case OPC_CheckAndImm:
2370 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2372 case OPC_CheckOrImm:
2373 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2376 case OPC_CheckFoldableChainNode: {
2377 assert(NodeStack.size() != 1 && "No parent node");
2378 // Verify that all intermediate nodes between the root and this one have
2380 bool HasMultipleUses = false;
2381 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2382 if (!NodeStack[i].hasOneUse()) {
2383 HasMultipleUses = true;
2386 if (HasMultipleUses) break;
2388 // Check to see that the target thinks this is profitable to fold and that
2389 // we can fold it without inducing cycles in the graph.
2390 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2392 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2393 NodeToMatch, true/*We validate our own chains*/))
2398 case OPC_EmitInteger: {
2399 MVT::SimpleValueType VT =
2400 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2401 int64_t Val = MatcherTable[MatcherIndex++];
2403 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2404 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2407 case OPC_EmitRegister: {
2408 MVT::SimpleValueType VT =
2409 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2410 unsigned RegNo = MatcherTable[MatcherIndex++];
2411 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2415 case OPC_EmitConvertToTarget: {
2416 // Convert from IMM/FPIMM to target version.
2417 unsigned RecNo = MatcherTable[MatcherIndex++];
2418 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2419 SDValue Imm = RecordedNodes[RecNo];
2421 if (Imm->getOpcode() == ISD::Constant) {
2422 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2423 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2424 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2425 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2426 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2429 RecordedNodes.push_back(Imm);
2433 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2434 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2435 // These are space-optimized forms of OPC_EmitMergeInputChains.
2436 assert(InputChain.getNode() == 0 &&
2437 "EmitMergeInputChains should be the first chain producing node");
2438 assert(ChainNodesMatched.empty() &&
2439 "Should only have one EmitMergeInputChains per match");
2441 // Read all of the chained nodes.
2442 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2443 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2444 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2446 // FIXME: What if other value results of the node have uses not matched
2448 if (ChainNodesMatched.back() != NodeToMatch &&
2449 !RecordedNodes[RecNo].hasOneUse()) {
2450 ChainNodesMatched.clear();
2454 // Merge the input chains if they are not intra-pattern references.
2455 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2457 if (InputChain.getNode() == 0)
2458 break; // Failed to merge.
2462 case OPC_EmitMergeInputChains: {
2463 assert(InputChain.getNode() == 0 &&
2464 "EmitMergeInputChains should be the first chain producing node");
2465 // This node gets a list of nodes we matched in the input that have
2466 // chains. We want to token factor all of the input chains to these nodes
2467 // together. However, if any of the input chains is actually one of the
2468 // nodes matched in this pattern, then we have an intra-match reference.
2469 // Ignore these because the newly token factored chain should not refer to
2471 unsigned NumChains = MatcherTable[MatcherIndex++];
2472 assert(NumChains != 0 && "Can't TF zero chains");
2474 assert(ChainNodesMatched.empty() &&
2475 "Should only have one EmitMergeInputChains per match");
2477 // Read all of the chained nodes.
2478 for (unsigned i = 0; i != NumChains; ++i) {
2479 unsigned RecNo = MatcherTable[MatcherIndex++];
2480 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2481 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2483 // FIXME: What if other value results of the node have uses not matched
2485 if (ChainNodesMatched.back() != NodeToMatch &&
2486 !RecordedNodes[RecNo].hasOneUse()) {
2487 ChainNodesMatched.clear();
2492 // If the inner loop broke out, the match fails.
2493 if (ChainNodesMatched.empty())
2496 // Merge the input chains if they are not intra-pattern references.
2497 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2499 if (InputChain.getNode() == 0)
2500 break; // Failed to merge.
2505 case OPC_EmitCopyToReg: {
2506 unsigned RecNo = MatcherTable[MatcherIndex++];
2507 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2508 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2510 if (InputChain.getNode() == 0)
2511 InputChain = CurDAG->getEntryNode();
2513 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2514 DestPhysReg, RecordedNodes[RecNo],
2517 InputFlag = InputChain.getValue(1);
2521 case OPC_EmitNodeXForm: {
2522 unsigned XFormNo = MatcherTable[MatcherIndex++];
2523 unsigned RecNo = MatcherTable[MatcherIndex++];
2524 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2525 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2530 case OPC_MorphNodeTo: {
2531 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2532 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2533 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2534 // Get the result VT list.
2535 unsigned NumVTs = MatcherTable[MatcherIndex++];
2536 SmallVector<EVT, 4> VTs;
2537 for (unsigned i = 0; i != NumVTs; ++i) {
2538 MVT::SimpleValueType VT =
2539 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2540 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2544 if (EmitNodeInfo & OPFL_Chain)
2545 VTs.push_back(MVT::Other);
2546 if (EmitNodeInfo & OPFL_FlagOutput)
2547 VTs.push_back(MVT::Flag);
2549 // This is hot code, so optimize the two most common cases of 1 and 2
2552 if (VTs.size() == 1)
2553 VTList = CurDAG->getVTList(VTs[0]);
2554 else if (VTs.size() == 2)
2555 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2557 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2559 // Get the operand list.
2560 unsigned NumOps = MatcherTable[MatcherIndex++];
2561 SmallVector<SDValue, 8> Ops;
2562 for (unsigned i = 0; i != NumOps; ++i) {
2563 unsigned RecNo = MatcherTable[MatcherIndex++];
2565 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2567 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2568 Ops.push_back(RecordedNodes[RecNo]);
2571 // If there are variadic operands to add, handle them now.
2572 if (EmitNodeInfo & OPFL_VariadicInfo) {
2573 // Determine the start index to copy from.
2574 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2575 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2576 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2577 "Invalid variadic node");
2578 // Copy all of the variadic operands, not including a potential flag
2580 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2582 SDValue V = NodeToMatch->getOperand(i);
2583 if (V.getValueType() == MVT::Flag) break;
2588 // If this has chain/flag inputs, add them.
2589 if (EmitNodeInfo & OPFL_Chain)
2590 Ops.push_back(InputChain);
2591 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2592 Ops.push_back(InputFlag);
2596 if (Opcode != OPC_MorphNodeTo) {
2597 // If this is a normal EmitNode command, just create the new node and
2598 // add the results to the RecordedNodes list.
2599 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2600 VTList, Ops.data(), Ops.size());
2602 // Add all the non-flag/non-chain results to the RecordedNodes list.
2603 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2604 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2605 RecordedNodes.push_back(SDValue(Res, i));
2609 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2613 // If the node had chain/flag results, update our notion of the current
2615 if (EmitNodeInfo & OPFL_FlagOutput) {
2616 InputFlag = SDValue(Res, VTs.size()-1);
2617 if (EmitNodeInfo & OPFL_Chain)
2618 InputChain = SDValue(Res, VTs.size()-2);
2619 } else if (EmitNodeInfo & OPFL_Chain)
2620 InputChain = SDValue(Res, VTs.size()-1);
2622 // If the OPFL_MemRefs flag is set on this node, slap all of the
2623 // accumulated memrefs onto it.
2625 // FIXME: This is vastly incorrect for patterns with multiple outputs
2626 // instructions that access memory and for ComplexPatterns that match
2628 if (EmitNodeInfo & OPFL_MemRefs) {
2629 MachineSDNode::mmo_iterator MemRefs =
2630 MF->allocateMemRefsArray(MatchedMemRefs.size());
2631 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2632 cast<MachineSDNode>(Res)
2633 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2637 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2638 << " node: "; Res->dump(CurDAG); errs() << "\n");
2640 // If this was a MorphNodeTo then we're completely done!
2641 if (Opcode == OPC_MorphNodeTo) {
2642 // Update chain and flag uses.
2643 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2644 InputFlag, FlagResultNodesMatched, true);
2651 case OPC_MarkFlagResults: {
2652 unsigned NumNodes = MatcherTable[MatcherIndex++];
2654 // Read and remember all the flag-result nodes.
2655 for (unsigned i = 0; i != NumNodes; ++i) {
2656 unsigned RecNo = MatcherTable[MatcherIndex++];
2658 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2660 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2661 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2666 case OPC_CompleteMatch: {
2667 // The match has been completed, and any new nodes (if any) have been
2668 // created. Patch up references to the matched dag to use the newly
2670 unsigned NumResults = MatcherTable[MatcherIndex++];
2672 for (unsigned i = 0; i != NumResults; ++i) {
2673 unsigned ResSlot = MatcherTable[MatcherIndex++];
2675 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2677 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2678 SDValue Res = RecordedNodes[ResSlot];
2680 assert(i < NodeToMatch->getNumValues() &&
2681 NodeToMatch->getValueType(i) != MVT::Other &&
2682 NodeToMatch->getValueType(i) != MVT::Flag &&
2683 "Invalid number of results to complete!");
2684 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2685 NodeToMatch->getValueType(i) == MVT::iPTR ||
2686 Res.getValueType() == MVT::iPTR ||
2687 NodeToMatch->getValueType(i).getSizeInBits() ==
2688 Res.getValueType().getSizeInBits()) &&
2689 "invalid replacement");
2690 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2693 // If the root node defines a flag, add it to the flag nodes to update
2695 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2696 FlagResultNodesMatched.push_back(NodeToMatch);
2698 // Update chain and flag uses.
2699 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2700 InputFlag, FlagResultNodesMatched, false);
2702 assert(NodeToMatch->use_empty() &&
2703 "Didn't replace all uses of the node?");
2705 // FIXME: We just return here, which interacts correctly with SelectRoot
2706 // above. We should fix this to not return an SDNode* anymore.
2711 // If the code reached this point, then the match failed. See if there is
2712 // another child to try in the current 'Scope', otherwise pop it until we
2713 // find a case to check.
2714 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2715 ++NumDAGIselRetries;
2717 if (MatchScopes.empty()) {
2718 CannotYetSelect(NodeToMatch);
2722 // Restore the interpreter state back to the point where the scope was
2724 MatchScope &LastScope = MatchScopes.back();
2725 RecordedNodes.resize(LastScope.NumRecordedNodes);
2727 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2728 N = NodeStack.back();
2730 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2731 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2732 MatcherIndex = LastScope.FailIndex;
2734 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2736 InputChain = LastScope.InputChain;
2737 InputFlag = LastScope.InputFlag;
2738 if (!LastScope.HasChainNodesMatched)
2739 ChainNodesMatched.clear();
2740 if (!LastScope.HasFlagResultNodesMatched)
2741 FlagResultNodesMatched.clear();
2743 // Check to see what the offset is at the new MatcherIndex. If it is zero
2744 // we have reached the end of this scope, otherwise we have another child
2745 // in the current scope to try.
2746 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2747 if (NumToSkip & 128)
2748 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2750 // If we have another child in this scope to match, update FailIndex and
2752 if (NumToSkip != 0) {
2753 LastScope.FailIndex = MatcherIndex+NumToSkip;
2757 // End of this scope, pop it and try the next child in the containing
2759 MatchScopes.pop_back();
2766 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2768 raw_string_ostream Msg(msg);
2769 Msg << "Cannot yet select: ";
2771 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2772 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2773 N->getOpcode() != ISD::INTRINSIC_VOID) {
2774 N->printrFull(Msg, CurDAG);
2776 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2778 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2779 if (iid < Intrinsic::num_intrinsics)
2780 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2781 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2782 Msg << "target intrinsic %" << TII->getName(iid);
2784 Msg << "unknown intrinsic #" << iid;
2786 llvm_report_error(Msg.str());
2789 char SelectionDAGISel::ID = 0;