1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/CodeGen/DwarfWriter.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetIntrinsicInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetMachine.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/Timer.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/ADT/Statistic.h"
63 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
64 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
68 cl::desc("Enable verbose messages in the \"fast\" "
69 "instruction selector"));
71 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
72 cl::desc("Enable abort calls when \"fast\" instruction fails"));
74 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
75 cl::desc("Schedule copies of livein registers"),
80 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the first "
84 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
85 cl::desc("Pop up a window to show dags before legalize types"));
87 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
88 cl::desc("Pop up a window to show dags before legalize"));
90 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
91 cl::desc("Pop up a window to show dags before the second "
94 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
95 cl::desc("Pop up a window to show dags before the post legalize types"
96 " dag combine pass"));
98 ViewISelDAGs("view-isel-dags", cl::Hidden,
99 cl::desc("Pop up a window to show isel dags as they are selected"));
101 ViewSchedDAGs("view-sched-dags", cl::Hidden,
102 cl::desc("Pop up a window to show sched dags as they are processed"));
104 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
105 cl::desc("Pop up a window to show SUnit dags after they are processed"));
107 static const bool ViewDAGCombine1 = false,
108 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
109 ViewDAGCombine2 = false,
110 ViewDAGCombineLT = false,
111 ViewISelDAGs = false, ViewSchedDAGs = false,
112 ViewSUnitDAGs = false;
115 //===---------------------------------------------------------------------===//
117 /// RegisterScheduler class - Track the registration of instruction schedulers.
119 //===---------------------------------------------------------------------===//
120 MachinePassRegistry RegisterScheduler::Registry;
122 //===---------------------------------------------------------------------===//
124 /// ISHeuristic command line option for instruction schedulers.
126 //===---------------------------------------------------------------------===//
127 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
128 RegisterPassParser<RegisterScheduler> >
129 ISHeuristic("pre-RA-sched",
130 cl::init(&createDefaultScheduler),
131 cl::desc("Instruction schedulers available (before register"
134 static RegisterScheduler
135 defaultListDAGScheduler("default", "Best scheduler for the target",
136 createDefaultScheduler);
139 //===--------------------------------------------------------------------===//
140 /// createDefaultScheduler - This creates an instruction scheduler appropriate
142 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
143 CodeGenOpt::Level OptLevel) {
144 const TargetLowering &TLI = IS->getTargetLowering();
146 if (OptLevel == CodeGenOpt::None)
147 return createFastDAGScheduler(IS, OptLevel);
148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
149 return createTDListDAGScheduler(IS, OptLevel);
150 assert(TLI.getSchedulingPreference() ==
151 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
152 return createBURRListDAGScheduler(IS, OptLevel);
156 // EmitInstrWithCustomInserter - This method should be implemented by targets
157 // that mark instructions with the 'usesCustomInserter' flag. These
158 // instructions are special in various ways, which require special support to
159 // insert. The specified MachineInstr is created but not inserted into any
160 // basic blocks, and this method is called to expand it into a sequence of
161 // instructions, potentially also creating new basic blocks and control flow.
162 // When new basic blocks are inserted and the edges from MBB to its successors
163 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
165 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
166 MachineBasicBlock *MBB,
167 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
169 dbgs() << "If a target marks an instruction with "
170 "'usesCustomInserter', it must implement "
171 "TargetLowering::EmitInstrWithCustomInserter!";
177 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
178 /// physical register has only a single copy use, then coalesced the copy
180 static void EmitLiveInCopy(MachineBasicBlock *MBB,
181 MachineBasicBlock::iterator &InsertPos,
182 unsigned VirtReg, unsigned PhysReg,
183 const TargetRegisterClass *RC,
184 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
185 const MachineRegisterInfo &MRI,
186 const TargetRegisterInfo &TRI,
187 const TargetInstrInfo &TII) {
188 unsigned NumUses = 0;
189 MachineInstr *UseMI = NULL;
190 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
191 UE = MRI.use_end(); UI != UE; ++UI) {
197 // If the number of uses is not one, or the use is not a move instruction,
198 // don't coalesce. Also, only coalesce away a virtual register to virtual
200 bool Coalesced = false;
201 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
203 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
204 TargetRegisterInfo::isVirtualRegister(DstReg)) {
209 // Now find an ideal location to insert the copy.
210 MachineBasicBlock::iterator Pos = InsertPos;
211 while (Pos != MBB->begin()) {
212 MachineInstr *PrevMI = prior(Pos);
213 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
214 // copyRegToReg might emit multiple instructions to do a copy.
215 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
216 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
217 // This is what the BB looks like right now:
222 // We want to insert "r1025 = mov r1". Inserting this copy below the
223 // move to r1024 makes it impossible for that move to be coalesced.
230 break; // Woot! Found a good location.
234 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
235 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
238 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
240 if (&*InsertPos == UseMI) ++InsertPos;
245 /// EmitLiveInCopies - If this is the first basic block in the function,
246 /// and if it has live ins that need to be copied into vregs, emit the
247 /// copies into the block.
248 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
249 const MachineRegisterInfo &MRI,
250 const TargetRegisterInfo &TRI,
251 const TargetInstrInfo &TII) {
252 if (SchedLiveInCopies) {
253 // Emit the copies at a heuristically-determined location in the block.
254 DenseMap<MachineInstr*, unsigned> CopyRegMap;
255 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
256 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
257 E = MRI.livein_end(); LI != E; ++LI)
259 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
260 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
261 RC, CopyRegMap, MRI, TRI, TII);
264 // Emit the copies into the top of the block.
265 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
266 E = MRI.livein_end(); LI != E; ++LI)
268 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
269 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
270 LI->second, LI->first, RC, RC);
271 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
277 //===----------------------------------------------------------------------===//
278 // SelectionDAGISel code
279 //===----------------------------------------------------------------------===//
281 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
282 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
283 FuncInfo(new FunctionLoweringInfo(TLI)),
284 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
285 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
291 SelectionDAGISel::~SelectionDAGISel() {
297 unsigned SelectionDAGISel::MakeReg(EVT VT) {
298 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
301 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
302 AU.addRequired<AliasAnalysis>();
303 AU.addPreserved<AliasAnalysis>();
304 AU.addRequired<GCModuleInfo>();
305 AU.addPreserved<GCModuleInfo>();
306 AU.addRequired<DwarfWriter>();
307 AU.addPreserved<DwarfWriter>();
308 MachineFunctionPass::getAnalysisUsage(AU);
311 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
312 Function &Fn = *mf.getFunction();
314 // Do some sanity-checking on the command-line options.
315 assert((!EnableFastISelVerbose || EnableFastISel) &&
316 "-fast-isel-verbose requires -fast-isel");
317 assert((!EnableFastISelAbort || EnableFastISel) &&
318 "-fast-isel-abort requires -fast-isel");
320 // Get alias analysis for load/store combining.
321 AA = &getAnalysis<AliasAnalysis>();
324 const TargetInstrInfo &TII = *TM.getInstrInfo();
325 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
328 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
331 RegInfo = &MF->getRegInfo();
332 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
334 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
335 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
336 CurDAG->init(*MF, MMI, DW);
337 FuncInfo->set(Fn, *MF, EnableFastISel);
340 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
341 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
343 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
345 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
347 // If the first basic block in the function has live ins that need to be
348 // copied into vregs, emit the copies into the top of the block before
349 // emitting the code for the block.
350 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
352 // Add function live-ins to entry block live-in set.
353 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
354 E = RegInfo->livein_end(); I != E; ++I)
355 MF->begin()->addLiveIn(I->first);
358 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
359 "Not all catch info was assigned to a landing pad!");
367 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
368 /// attached with this instruction.
369 static void SetDebugLoc(unsigned MDDbgKind, Instruction *I,
370 SelectionDAGBuilder *SDB,
371 FastISel *FastIS, MachineFunction *MF) {
372 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) {
373 DILocation DILoc(Dbg);
374 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
376 SDB->setCurDebugLoc(Loc);
379 FastIS->setCurDebugLoc(Loc);
381 // If the function doesn't have a default debug location yet, set
382 // it. This is kind of a hack.
383 if (MF->getDefaultDebugLoc().isUnknown())
384 MF->setDefaultDebugLoc(Loc);
388 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
389 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
390 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc());
392 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc());
395 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
396 BasicBlock::iterator Begin,
397 BasicBlock::iterator End,
399 SDB->setCurrentBasicBlock(BB);
400 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg");
402 // Lower all of the non-terminator instructions. If a call is emitted
403 // as a tail call, cease emitting nodes for this block.
404 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
405 SetDebugLoc(MDDbgKind, I, SDB, 0, MF);
407 if (!isa<TerminatorInst>(I)) {
410 // Set the current debug location back to "unknown" so that it doesn't
411 // spuriously apply to subsequent instructions.
412 ResetDebugLoc(SDB, 0);
416 if (!SDB->HasTailCall) {
417 // Ensure that all instructions which are used outside of their defining
418 // blocks are available as virtual registers. Invoke is handled elsewhere.
419 for (BasicBlock::iterator I = Begin; I != End; ++I)
420 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
421 SDB->CopyToExportRegsIfNeeded(I);
423 // Handle PHI nodes in successor blocks.
424 if (End == LLVMBB->end()) {
425 HandlePHINodesInSuccessorBlocks(LLVMBB);
427 // Lower the terminator after the copies are emitted.
428 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF);
429 SDB->visit(*LLVMBB->getTerminator());
430 ResetDebugLoc(SDB, 0);
434 // Make sure the root of the DAG is up-to-date.
435 CurDAG->setRoot(SDB->getControlRoot());
437 // Final step, emit the lowered DAG as machine code.
439 HadTailCall = SDB->HasTailCall;
444 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
445 /// nodes from the worklist.
446 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
447 SmallVector<SDNode*, 128> &Worklist;
448 SmallPtrSet<SDNode*, 128> &InWorklist;
450 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
451 SmallPtrSet<SDNode*, 128> &inwl)
452 : Worklist(wl), InWorklist(inwl) {}
454 void RemoveFromWorklist(SDNode *N) {
455 if (!InWorklist.erase(N)) return;
457 SmallVector<SDNode*, 128>::iterator I =
458 std::find(Worklist.begin(), Worklist.end(), N);
459 assert(I != Worklist.end() && "Not in worklist");
461 *I = Worklist.back();
465 virtual void NodeDeleted(SDNode *N, SDNode *E) {
466 RemoveFromWorklist(N);
469 virtual void NodeUpdated(SDNode *N) {
475 /// TrivialTruncElim - Eliminate some trivial nops that can result from
476 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
477 static bool TrivialTruncElim(SDValue Op,
478 TargetLowering::TargetLoweringOpt &TLO) {
479 SDValue N0 = Op.getOperand(0);
480 EVT VT = Op.getValueType();
481 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
482 N0.getOpcode() == ISD::SIGN_EXTEND ||
483 N0.getOpcode() == ISD::ANY_EXTEND) &&
484 N0.getOperand(0).getValueType() == VT) {
485 return TLO.CombineTo(Op, N0.getOperand(0));
490 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
491 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
492 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
493 void SelectionDAGISel::ShrinkDemandedOps() {
494 SmallVector<SDNode*, 128> Worklist;
495 SmallPtrSet<SDNode*, 128> InWorklist;
497 // Add all the dag nodes to the worklist.
498 Worklist.reserve(CurDAG->allnodes_size());
499 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
500 E = CurDAG->allnodes_end(); I != E; ++I) {
501 Worklist.push_back(I);
502 InWorklist.insert(I);
505 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
506 while (!Worklist.empty()) {
507 SDNode *N = Worklist.pop_back_val();
510 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
511 // Deleting this node may make its operands dead, add them to the worklist
512 // if they aren't already there.
513 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
514 if (InWorklist.insert(N->getOperand(i).getNode()))
515 Worklist.push_back(N->getOperand(i).getNode());
517 CurDAG->DeleteNode(N);
521 // Run ShrinkDemandedOp on scalar binary operations.
522 if (N->getNumValues() != 1 ||
523 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
526 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
527 APInt Demanded = APInt::getAllOnesValue(BitWidth);
528 APInt KnownZero, KnownOne;
529 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
530 KnownZero, KnownOne, TLO) &&
531 (N->getOpcode() != ISD::TRUNCATE ||
532 !TrivialTruncElim(SDValue(N, 0), TLO)))
536 assert(!InWorklist.count(N) && "Already in worklist");
537 Worklist.push_back(N);
538 InWorklist.insert(N);
540 // Replace the old value with the new one.
541 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
542 TLO.Old.getNode()->dump(CurDAG);
543 errs() << "\nWith: ";
544 TLO.New.getNode()->dump(CurDAG);
547 if (InWorklist.insert(TLO.New.getNode()))
548 Worklist.push_back(TLO.New.getNode());
550 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
551 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
553 if (!TLO.Old.getNode()->use_empty()) continue;
555 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
557 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
558 if (OpNode->hasOneUse()) {
559 // Add OpNode to the end of the list to revisit.
560 DeadNodes.RemoveFromWorklist(OpNode);
561 Worklist.push_back(OpNode);
562 InWorklist.insert(OpNode);
566 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
567 CurDAG->DeleteNode(TLO.Old.getNode());
571 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
572 SmallPtrSet<SDNode*, 128> VisitedNodes;
573 SmallVector<SDNode*, 128> Worklist;
575 Worklist.push_back(CurDAG->getRoot().getNode());
582 SDNode *N = Worklist.pop_back_val();
584 // If we've already seen this node, ignore it.
585 if (!VisitedNodes.insert(N))
588 // Otherwise, add all chain operands to the worklist.
589 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
590 if (N->getOperand(i).getValueType() == MVT::Other)
591 Worklist.push_back(N->getOperand(i).getNode());
593 // If this is a CopyToReg with a vreg dest, process it.
594 if (N->getOpcode() != ISD::CopyToReg)
597 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
598 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
601 // Ignore non-scalar or non-integer values.
602 SDValue Src = N->getOperand(2);
603 EVT SrcVT = Src.getValueType();
604 if (!SrcVT.isInteger() || SrcVT.isVector())
607 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
608 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
609 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
611 // Only install this information if it tells us something.
612 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
613 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
614 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
615 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
616 FunctionLoweringInfo::LiveOutInfo &LOI =
617 FuncInfo->LiveOutRegInfo[DestReg];
618 LOI.NumSignBits = NumSignBits;
619 LOI.KnownOne = KnownOne;
620 LOI.KnownZero = KnownZero;
622 } while (!Worklist.empty());
625 void SelectionDAGISel::CodeGenAndEmitDAG() {
626 std::string GroupName;
627 if (TimePassesIsEnabled)
628 GroupName = "Instruction Selection and Scheduling";
629 std::string BlockName;
630 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
631 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
633 BlockName = MF->getFunction()->getNameStr() + ":" +
634 BB->getBasicBlock()->getNameStr();
636 DEBUG(dbgs() << "Initial selection DAG:\n");
637 DEBUG(CurDAG->dump());
639 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
641 // Run the DAG combiner in pre-legalize mode.
642 if (TimePassesIsEnabled) {
643 NamedRegionTimer T("DAG Combining 1", GroupName);
644 CurDAG->Combine(Unrestricted, *AA, OptLevel);
646 CurDAG->Combine(Unrestricted, *AA, OptLevel);
649 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
650 DEBUG(CurDAG->dump());
652 // Second step, hack on the DAG until it only uses operations and types that
653 // the target supports.
654 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
658 if (TimePassesIsEnabled) {
659 NamedRegionTimer T("Type Legalization", GroupName);
660 Changed = CurDAG->LegalizeTypes();
662 Changed = CurDAG->LegalizeTypes();
665 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
666 DEBUG(CurDAG->dump());
669 if (ViewDAGCombineLT)
670 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
672 // Run the DAG combiner in post-type-legalize mode.
673 if (TimePassesIsEnabled) {
674 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
675 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
677 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
680 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
681 DEBUG(CurDAG->dump());
684 if (TimePassesIsEnabled) {
685 NamedRegionTimer T("Vector Legalization", GroupName);
686 Changed = CurDAG->LegalizeVectors();
688 Changed = CurDAG->LegalizeVectors();
692 if (TimePassesIsEnabled) {
693 NamedRegionTimer T("Type Legalization 2", GroupName);
694 CurDAG->LegalizeTypes();
696 CurDAG->LegalizeTypes();
699 if (ViewDAGCombineLT)
700 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
702 // Run the DAG combiner in post-type-legalize mode.
703 if (TimePassesIsEnabled) {
704 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
705 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
707 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
710 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
711 DEBUG(CurDAG->dump());
714 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
716 if (TimePassesIsEnabled) {
717 NamedRegionTimer T("DAG Legalization", GroupName);
718 CurDAG->Legalize(OptLevel);
720 CurDAG->Legalize(OptLevel);
723 DEBUG(dbgs() << "Legalized selection DAG:\n");
724 DEBUG(CurDAG->dump());
726 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
728 // Run the DAG combiner in post-legalize mode.
729 if (TimePassesIsEnabled) {
730 NamedRegionTimer T("DAG Combining 2", GroupName);
731 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
733 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
736 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
737 DEBUG(CurDAG->dump());
739 if (OptLevel != CodeGenOpt::None) {
741 ComputeLiveOutVRegInfo();
744 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
746 // Third, instruction select all of the operations to machine code, adding the
747 // code to the MachineBasicBlock.
748 if (TimePassesIsEnabled) {
749 NamedRegionTimer T("Instruction Selection", GroupName);
750 DoInstructionSelection();
752 DoInstructionSelection();
755 DEBUG(dbgs() << "Selected selection DAG:\n");
756 DEBUG(CurDAG->dump());
758 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
760 // Schedule machine code.
761 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
762 if (TimePassesIsEnabled) {
763 NamedRegionTimer T("Instruction Scheduling", GroupName);
764 Scheduler->Run(CurDAG, BB, BB->end());
766 Scheduler->Run(CurDAG, BB, BB->end());
769 if (ViewSUnitDAGs) Scheduler->viewGraph();
771 // Emit machine code to BB. This can change 'BB' to the last block being
773 if (TimePassesIsEnabled) {
774 NamedRegionTimer T("Instruction Creation", GroupName);
775 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
777 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
780 // Free the scheduler state.
781 if (TimePassesIsEnabled) {
782 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
788 DEBUG(dbgs() << "Selected machine code:\n");
792 void SelectionDAGISel::DoInstructionSelection() {
793 DEBUG(errs() << "===== Instruction selection begins:\n");
797 // Select target instructions for the DAG.
799 // Number all nodes with a topological order and set DAGSize.
800 DAGSize = CurDAG->AssignTopologicalOrder();
802 // Create a dummy node (which is not added to allnodes), that adds
803 // a reference to the root node, preventing it from being deleted,
804 // and tracking any changes of the root.
805 HandleSDNode Dummy(CurDAG->getRoot());
806 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
809 // The AllNodes list is now topological-sorted. Visit the
810 // nodes by starting at the end of the list (the root of the
811 // graph) and preceding back toward the beginning (the entry
813 while (ISelPosition != CurDAG->allnodes_begin()) {
814 SDNode *Node = --ISelPosition;
815 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
816 // but there are currently some corner cases that it misses. Also, this
817 // makes it theoretically possible to disable the DAGCombiner.
818 if (Node->use_empty())
821 SDNode *ResNode = Select(Node);
823 // FIXME: This is pretty gross. 'Select' should be changed to not return
824 // anything at all and this code should be nuked with a tactical strike.
826 // If node should not be replaced, continue with the next one.
827 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
831 ReplaceUses(Node, ResNode);
833 // If after the replacement this node is not used any more,
834 // remove this dead node.
835 if (Node->use_empty()) { // Don't delete EntryToken, etc.
836 ISelUpdater ISU(ISelPosition);
837 CurDAG->RemoveDeadNode(Node, &ISU);
841 CurDAG->setRoot(Dummy.getValue());
843 DEBUG(errs() << "===== Instruction selection ends:\n");
845 PostprocessISelDAG();
849 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
851 MachineModuleInfo *MMI,
853 const TargetInstrInfo &TII) {
854 // Initialize the Fast-ISel state, if needed.
855 FastISel *FastIS = 0;
857 FastIS = TLI.createFastISel(MF, MMI, DW,
860 FuncInfo->StaticAllocaMap
862 , FuncInfo->CatchInfoLost
866 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg");
868 // Iterate over all basic blocks in the function.
869 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
870 BasicBlock *LLVMBB = &*I;
871 BB = FuncInfo->MBBMap[LLVMBB];
873 BasicBlock::iterator const Begin = LLVMBB->begin();
874 BasicBlock::iterator const End = LLVMBB->end();
875 BasicBlock::iterator BI = Begin;
877 // Lower any arguments needed in this block if this is the entry block.
878 bool SuppressFastISel = false;
879 if (LLVMBB == &Fn.getEntryBlock()) {
880 LowerArguments(LLVMBB);
882 // If any of the arguments has the byval attribute, forgo
883 // fast-isel in the entry block.
886 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
888 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
889 if (EnableFastISelVerbose || EnableFastISelAbort)
890 dbgs() << "FastISel skips entry block due to byval argument\n";
891 SuppressFastISel = true;
897 if (MMI && BB->isLandingPad()) {
898 // Add a label to mark the beginning of the landing pad. Deletion of the
899 // landing pad can thus be detected via the MachineModuleInfo.
900 MCSymbol *Label = MMI->addLandingPad(BB);
902 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
903 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
905 // Mark exception register as live in.
906 unsigned Reg = TLI.getExceptionAddressRegister();
907 if (Reg) BB->addLiveIn(Reg);
909 // Mark exception selector register as live in.
910 Reg = TLI.getExceptionSelectorRegister();
911 if (Reg) BB->addLiveIn(Reg);
913 // FIXME: Hack around an exception handling flaw (PR1508): the personality
914 // function and list of typeids logically belong to the invoke (or, if you
915 // like, the basic block containing the invoke), and need to be associated
916 // with it in the dwarf exception handling tables. Currently however the
917 // information is provided by an intrinsic (eh.selector) that can be moved
918 // to unexpected places by the optimizers: if the unwind edge is critical,
919 // then breaking it can result in the intrinsics being in the successor of
920 // the landing pad, not the landing pad itself. This results
921 // in exceptions not being caught because no typeids are associated with
922 // the invoke. This may not be the only way things can go wrong, but it
923 // is the only way we try to work around for the moment.
924 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
926 if (Br && Br->isUnconditional()) { // Critical edge?
927 BasicBlock::iterator I, E;
928 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
929 if (isa<EHSelectorInst>(I))
933 // No catch info found - try to extract some from the successor.
934 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
938 // Before doing SelectionDAG ISel, see if FastISel has been requested.
939 if (FastIS && !SuppressFastISel) {
940 // Emit code for any incoming arguments. This must happen before
941 // beginning FastISel on the entry block.
942 if (LLVMBB == &Fn.getEntryBlock()) {
943 CurDAG->setRoot(SDB->getControlRoot());
947 FastIS->startNewBlock(BB);
948 // Do FastISel on as many instructions as possible.
949 for (; BI != End; ++BI) {
950 // Just before the terminator instruction, insert instructions to
951 // feed PHI nodes in successor blocks.
952 if (isa<TerminatorInst>(BI))
953 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
954 ++NumFastIselFailures;
955 ResetDebugLoc(SDB, FastIS);
956 if (EnableFastISelVerbose || EnableFastISelAbort) {
957 dbgs() << "FastISel miss: ";
960 assert(!EnableFastISelAbort &&
961 "FastISel didn't handle a PHI in a successor");
965 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF);
967 // Try to select the instruction with FastISel.
968 if (FastIS->SelectInstruction(BI)) {
969 ResetDebugLoc(SDB, FastIS);
973 // Clear out the debug location so that it doesn't carry over to
974 // unrelated instructions.
975 ResetDebugLoc(SDB, FastIS);
977 // Then handle certain instructions as single-LLVM-Instruction blocks.
978 if (isa<CallInst>(BI)) {
979 ++NumFastIselFailures;
980 if (EnableFastISelVerbose || EnableFastISelAbort) {
981 dbgs() << "FastISel missed call: ";
985 if (!BI->getType()->isVoidTy()) {
986 unsigned &R = FuncInfo->ValueMap[BI];
988 R = FuncInfo->CreateRegForValue(BI);
991 bool HadTailCall = false;
992 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
994 // If the call was emitted as a tail call, we're done with the block.
1000 // If the instruction was codegen'd with multiple blocks,
1001 // inform the FastISel object where to resume inserting.
1002 FastIS->setCurrentBlock(BB);
1006 // Otherwise, give up on FastISel for the rest of the block.
1007 // For now, be a little lenient about non-branch terminators.
1008 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
1009 ++NumFastIselFailures;
1010 if (EnableFastISelVerbose || EnableFastISelAbort) {
1011 dbgs() << "FastISel miss: ";
1014 if (EnableFastISelAbort)
1015 // The "fast" selector couldn't handle something and bailed.
1016 // For the purpose of debugging, just abort.
1017 llvm_unreachable("FastISel didn't select the entire block");
1023 // Run SelectionDAG instruction selection on the remainder of the block
1024 // not handled by FastISel. If FastISel is not run, this is the entire
1028 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
1038 SelectionDAGISel::FinishBasicBlock() {
1040 DEBUG(dbgs() << "Target-post-processed machine code:\n");
1043 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1044 << SDB->PHINodesToUpdate.size() << "\n");
1045 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
1046 dbgs() << "Node " << i << " : ("
1047 << SDB->PHINodesToUpdate[i].first
1048 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
1050 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1051 // PHI nodes in successors.
1052 if (SDB->SwitchCases.empty() &&
1053 SDB->JTCases.empty() &&
1054 SDB->BitTestCases.empty()) {
1055 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1056 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1057 assert(PHI->isPHI() &&
1058 "This is not a machine PHI node that we are updating!");
1059 if (!BB->isSuccessor(PHI->getParent()))
1061 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1063 PHI->addOperand(MachineOperand::CreateMBB(BB));
1065 SDB->PHINodesToUpdate.clear();
1069 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1070 // Lower header first, if it wasn't already lowered
1071 if (!SDB->BitTestCases[i].Emitted) {
1072 // Set the current basic block to the mbb we wish to insert the code into
1073 BB = SDB->BitTestCases[i].Parent;
1074 SDB->setCurrentBasicBlock(BB);
1076 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
1077 CurDAG->setRoot(SDB->getRoot());
1078 CodeGenAndEmitDAG();
1082 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1083 // Set the current basic block to the mbb we wish to insert the code into
1084 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
1085 SDB->setCurrentBasicBlock(BB);
1088 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1089 SDB->BitTestCases[i].Reg,
1090 SDB->BitTestCases[i].Cases[j]);
1092 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1093 SDB->BitTestCases[i].Reg,
1094 SDB->BitTestCases[i].Cases[j]);
1097 CurDAG->setRoot(SDB->getRoot());
1098 CodeGenAndEmitDAG();
1103 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1104 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1105 MachineBasicBlock *PHIBB = PHI->getParent();
1106 assert(PHI->isPHI() &&
1107 "This is not a machine PHI node that we are updating!");
1108 // This is "default" BB. We have two jumps to it. From "header" BB and
1109 // from last "case" BB.
1110 if (PHIBB == SDB->BitTestCases[i].Default) {
1111 PHI->addOperand(MachineOperand::
1112 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1113 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1114 PHI->addOperand(MachineOperand::
1115 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1116 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1119 // One of "cases" BB.
1120 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1122 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1123 if (cBB->isSuccessor(PHIBB)) {
1124 PHI->addOperand(MachineOperand::
1125 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1126 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1131 SDB->BitTestCases.clear();
1133 // If the JumpTable record is filled in, then we need to emit a jump table.
1134 // Updating the PHI nodes is tricky in this case, since we need to determine
1135 // whether the PHI is a successor of the range check MBB or the jump table MBB
1136 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1137 // Lower header first, if it wasn't already lowered
1138 if (!SDB->JTCases[i].first.Emitted) {
1139 // Set the current basic block to the mbb we wish to insert the code into
1140 BB = SDB->JTCases[i].first.HeaderBB;
1141 SDB->setCurrentBasicBlock(BB);
1143 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1144 CurDAG->setRoot(SDB->getRoot());
1145 CodeGenAndEmitDAG();
1149 // Set the current basic block to the mbb we wish to insert the code into
1150 BB = SDB->JTCases[i].second.MBB;
1151 SDB->setCurrentBasicBlock(BB);
1153 SDB->visitJumpTable(SDB->JTCases[i].second);
1154 CurDAG->setRoot(SDB->getRoot());
1155 CodeGenAndEmitDAG();
1159 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1160 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1161 MachineBasicBlock *PHIBB = PHI->getParent();
1162 assert(PHI->isPHI() &&
1163 "This is not a machine PHI node that we are updating!");
1164 // "default" BB. We can go there only from header BB.
1165 if (PHIBB == SDB->JTCases[i].second.Default) {
1167 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1169 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1171 // JT BB. Just iterate over successors here
1172 if (BB->isSuccessor(PHIBB)) {
1174 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1175 PHI->addOperand(MachineOperand::CreateMBB(BB));
1179 SDB->JTCases.clear();
1181 // If the switch block involved a branch to one of the actual successors, we
1182 // need to update PHI nodes in that block.
1183 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1184 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1185 assert(PHI->isPHI() &&
1186 "This is not a machine PHI node that we are updating!");
1187 if (BB->isSuccessor(PHI->getParent())) {
1188 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1190 PHI->addOperand(MachineOperand::CreateMBB(BB));
1194 // If we generated any switch lowering information, build and codegen any
1195 // additional DAGs necessary.
1196 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1197 // Set the current basic block to the mbb we wish to insert the code into
1198 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1199 SDB->setCurrentBasicBlock(BB);
1202 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1203 CurDAG->setRoot(SDB->getRoot());
1204 CodeGenAndEmitDAG();
1206 // Handle any PHI nodes in successors of this chunk, as if we were coming
1207 // from the original BB before switch expansion. Note that PHI nodes can
1208 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1209 // handle them the right number of times.
1210 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1211 // If new BB's are created during scheduling, the edges may have been
1212 // updated. That is, the edge from ThisBB to BB may have been split and
1213 // BB's predecessor is now another block.
1214 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1215 SDB->EdgeMapping.find(BB);
1216 if (EI != SDB->EdgeMapping.end())
1217 ThisBB = EI->second;
1219 // BB may have been removed from the CFG if a branch was constant folded.
1220 if (ThisBB->isSuccessor(BB)) {
1221 for (MachineBasicBlock::iterator Phi = BB->begin();
1222 Phi != BB->end() && Phi->isPHI();
1224 // This value for this PHI node is recorded in PHINodesToUpdate.
1225 for (unsigned pn = 0; ; ++pn) {
1226 assert(pn != SDB->PHINodesToUpdate.size() &&
1227 "Didn't find PHI entry!");
1228 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1229 Phi->addOperand(MachineOperand::
1230 CreateReg(SDB->PHINodesToUpdate[pn].second,
1232 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1239 // Don't process RHS if same block as LHS.
1240 if (BB == SDB->SwitchCases[i].FalseBB)
1241 SDB->SwitchCases[i].FalseBB = 0;
1243 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1244 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1245 SDB->SwitchCases[i].FalseBB = 0;
1247 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1250 SDB->SwitchCases.clear();
1252 SDB->PHINodesToUpdate.clear();
1256 /// Create the scheduler. If a specific scheduler was specified
1257 /// via the SchedulerRegistry, use it, otherwise select the
1258 /// one preferred by the target.
1260 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1261 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1265 RegisterScheduler::setDefault(Ctor);
1268 return Ctor(this, OptLevel);
1271 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1272 return new ScheduleHazardRecognizer();
1275 //===----------------------------------------------------------------------===//
1276 // Helper functions used by the generated instruction selector.
1277 //===----------------------------------------------------------------------===//
1278 // Calls to these methods are generated by tblgen.
1280 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1281 /// the dag combiner simplified the 255, we still want to match. RHS is the
1282 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1283 /// specified in the .td file (e.g. 255).
1284 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1285 int64_t DesiredMaskS) const {
1286 const APInt &ActualMask = RHS->getAPIntValue();
1287 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1289 // If the actual mask exactly matches, success!
1290 if (ActualMask == DesiredMask)
1293 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1294 if (ActualMask.intersects(~DesiredMask))
1297 // Otherwise, the DAG Combiner may have proven that the value coming in is
1298 // either already zero or is not demanded. Check for known zero input bits.
1299 APInt NeededMask = DesiredMask & ~ActualMask;
1300 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1303 // TODO: check to see if missing bits are just not demanded.
1305 // Otherwise, this pattern doesn't match.
1309 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1310 /// the dag combiner simplified the 255, we still want to match. RHS is the
1311 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1312 /// specified in the .td file (e.g. 255).
1313 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1314 int64_t DesiredMaskS) const {
1315 const APInt &ActualMask = RHS->getAPIntValue();
1316 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1318 // If the actual mask exactly matches, success!
1319 if (ActualMask == DesiredMask)
1322 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1323 if (ActualMask.intersects(~DesiredMask))
1326 // Otherwise, the DAG Combiner may have proven that the value coming in is
1327 // either already zero or is not demanded. Check for known zero input bits.
1328 APInt NeededMask = DesiredMask & ~ActualMask;
1330 APInt KnownZero, KnownOne;
1331 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1333 // If all the missing bits in the or are already known to be set, match!
1334 if ((NeededMask & KnownOne) == NeededMask)
1337 // TODO: check to see if missing bits are just not demanded.
1339 // Otherwise, this pattern doesn't match.
1344 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1345 /// by tblgen. Others should not call it.
1346 void SelectionDAGISel::
1347 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1348 std::vector<SDValue> InOps;
1349 std::swap(InOps, Ops);
1351 Ops.push_back(InOps[0]); // input chain.
1352 Ops.push_back(InOps[1]); // input asm string.
1354 unsigned i = 2, e = InOps.size();
1355 if (InOps[e-1].getValueType() == MVT::Flag)
1356 --e; // Don't process a flag operand if it is here.
1359 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1360 if ((Flags & 7) != 4 /*MEM*/) {
1361 // Just skip over this operand, copying the operands verbatim.
1362 Ops.insert(Ops.end(), InOps.begin()+i,
1363 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1364 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1366 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1367 "Memory operand with multiple values?");
1368 // Otherwise, this is a memory operand. Ask the target to select it.
1369 std::vector<SDValue> SelOps;
1370 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1371 llvm_report_error("Could not match memory address. Inline asm"
1375 // Add this to the output node.
1376 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1378 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1383 // Add the flag input back if present.
1384 if (e != InOps.size())
1385 Ops.push_back(InOps.back());
1388 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1391 static SDNode *findFlagUse(SDNode *N) {
1392 unsigned FlagResNo = N->getNumValues()-1;
1393 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1394 SDUse &Use = I.getUse();
1395 if (Use.getResNo() == FlagResNo)
1396 return Use.getUser();
1401 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1402 /// This function recursively traverses up the operand chain, ignoring
1404 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1405 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1406 bool IgnoreChains) {
1407 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1408 // greater than all of its (recursive) operands. If we scan to a point where
1409 // 'use' is smaller than the node we're scanning for, then we know we will
1412 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1413 // happen because we scan down to newly selected nodes in the case of flag
1415 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1418 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1419 // won't fail if we scan it again.
1420 if (!Visited.insert(Use))
1423 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1424 // Ignore chain uses, they are validated by HandleMergeInputChains.
1425 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1428 SDNode *N = Use->getOperand(i).getNode();
1430 if (Use == ImmedUse || Use == Root)
1431 continue; // We are not looking for immediate use.
1436 // Traverse up the operand chain.
1437 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1443 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1444 /// operand node N of U during instruction selection that starts at Root.
1445 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1446 SDNode *Root) const {
1447 if (OptLevel == CodeGenOpt::None) return false;
1448 return N.hasOneUse();
1451 /// IsLegalToFold - Returns true if the specific operand node N of
1452 /// U can be folded during instruction selection that starts at Root.
1453 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1454 bool IgnoreChains) const {
1455 if (OptLevel == CodeGenOpt::None) return false;
1457 // If Root use can somehow reach N through a path that that doesn't contain
1458 // U then folding N would create a cycle. e.g. In the following
1459 // diagram, Root can reach N through X. If N is folded into into Root, then
1460 // X is both a predecessor and a successor of U.
1471 // * indicates nodes to be folded together.
1473 // If Root produces a flag, then it gets (even more) interesting. Since it
1474 // will be "glued" together with its flag use in the scheduler, we need to
1475 // check if it might reach N.
1494 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1495 // (call it Fold), then X is a predecessor of FU and a successor of
1496 // Fold. But since Fold and FU are flagged together, this will create
1497 // a cycle in the scheduling graph.
1499 // If the node has flags, walk down the graph to the "lowest" node in the
1501 EVT VT = Root->getValueType(Root->getNumValues()-1);
1502 while (VT == MVT::Flag) {
1503 SDNode *FU = findFlagUse(Root);
1507 VT = Root->getValueType(Root->getNumValues()-1);
1509 // If our query node has a flag result with a use, we've walked up it. If
1510 // the user (which has already been selected) has a chain or indirectly uses
1511 // the chain, our WalkChainUsers predicate will not consider it. Because of
1512 // this, we cannot ignore chains in this predicate.
1513 IgnoreChains = false;
1517 SmallPtrSet<SDNode*, 16> Visited;
1518 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1521 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1522 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1523 SelectInlineAsmMemoryOperands(Ops);
1525 std::vector<EVT> VTs;
1526 VTs.push_back(MVT::Other);
1527 VTs.push_back(MVT::Flag);
1528 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1529 VTs, &Ops[0], Ops.size());
1531 return New.getNode();
1534 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1535 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1538 /// GetVBR - decode a vbr encoding whose top bit is set.
1539 ALWAYS_INLINE static uint64_t
1540 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1541 assert(Val >= 128 && "Not a VBR");
1542 Val &= 127; // Remove first vbr bit.
1547 NextBits = MatcherTable[Idx++];
1548 Val |= (NextBits&127) << Shift;
1550 } while (NextBits & 128);
1556 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1557 /// interior flag and chain results to use the new flag and chain results.
1558 void SelectionDAGISel::
1559 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1560 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1562 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1563 bool isMorphNodeTo) {
1564 SmallVector<SDNode*, 4> NowDeadNodes;
1566 ISelUpdater ISU(ISelPosition);
1568 // Now that all the normal results are replaced, we replace the chain and
1569 // flag results if present.
1570 if (!ChainNodesMatched.empty()) {
1571 assert(InputChain.getNode() != 0 &&
1572 "Matched input chains but didn't produce a chain");
1573 // Loop over all of the nodes we matched that produced a chain result.
1574 // Replace all the chain results with the final chain we ended up with.
1575 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1576 SDNode *ChainNode = ChainNodesMatched[i];
1578 // If this node was already deleted, don't look at it.
1579 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1582 // Don't replace the results of the root node if we're doing a
1584 if (ChainNode == NodeToMatch && isMorphNodeTo)
1587 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1588 if (ChainVal.getValueType() == MVT::Flag)
1589 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1590 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1591 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1593 // If the node became dead and we haven't already seen it, delete it.
1594 if (ChainNode->use_empty() &&
1595 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1596 NowDeadNodes.push_back(ChainNode);
1600 // If the result produces a flag, update any flag results in the matched
1601 // pattern with the flag result.
1602 if (InputFlag.getNode() != 0) {
1603 // Handle any interior nodes explicitly marked.
1604 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1605 SDNode *FRN = FlagResultNodesMatched[i];
1607 // If this node was already deleted, don't look at it.
1608 if (FRN->getOpcode() == ISD::DELETED_NODE)
1611 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1612 "Doesn't have a flag result");
1613 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1616 // If the node became dead and we haven't already seen it, delete it.
1617 if (FRN->use_empty() &&
1618 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1619 NowDeadNodes.push_back(FRN);
1623 if (!NowDeadNodes.empty())
1624 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1626 DEBUG(errs() << "ISEL: Match complete!\n");
1632 CR_LeadsToInteriorNode
1635 /// WalkChainUsers - Walk down the users of the specified chained node that is
1636 /// part of the pattern we're matching, looking at all of the users we find.
1637 /// This determines whether something is an interior node, whether we have a
1638 /// non-pattern node in between two pattern nodes (which prevent folding because
1639 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1640 /// between pattern nodes (in which case the TF becomes part of the pattern).
1642 /// The walk we do here is guaranteed to be small because we quickly get down to
1643 /// already selected nodes "below" us.
1645 WalkChainUsers(SDNode *ChainedNode,
1646 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1647 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1648 ChainResult Result = CR_Simple;
1650 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1651 E = ChainedNode->use_end(); UI != E; ++UI) {
1652 // Make sure the use is of the chain, not some other value we produce.
1653 if (UI.getUse().getValueType() != MVT::Other) continue;
1657 // If we see an already-selected machine node, then we've gone beyond the
1658 // pattern that we're selecting down into the already selected chunk of the
1660 if (User->isMachineOpcode() ||
1661 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1664 if (User->getOpcode() == ISD::CopyToReg ||
1665 User->getOpcode() == ISD::CopyFromReg ||
1666 User->getOpcode() == ISD::INLINEASM ||
1667 User->getOpcode() == ISD::EH_LABEL) {
1668 // If their node ID got reset to -1 then they've already been selected.
1669 // Treat them like a MachineOpcode.
1670 if (User->getNodeId() == -1)
1674 // If we have a TokenFactor, we handle it specially.
1675 if (User->getOpcode() != ISD::TokenFactor) {
1676 // If the node isn't a token factor and isn't part of our pattern, then it
1677 // must be a random chained node in between two nodes we're selecting.
1678 // This happens when we have something like:
1683 // Because we structurally match the load/store as a read/modify/write,
1684 // but the call is chained between them. We cannot fold in this case
1685 // because it would induce a cycle in the graph.
1686 if (!std::count(ChainedNodesInPattern.begin(),
1687 ChainedNodesInPattern.end(), User))
1688 return CR_InducesCycle;
1690 // Otherwise we found a node that is part of our pattern. For example in:
1694 // This would happen when we're scanning down from the load and see the
1695 // store as a user. Record that there is a use of ChainedNode that is
1696 // part of the pattern and keep scanning uses.
1697 Result = CR_LeadsToInteriorNode;
1698 InteriorChainedNodes.push_back(User);
1702 // If we found a TokenFactor, there are two cases to consider: first if the
1703 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1704 // uses of the TF are in our pattern) we just want to ignore it. Second,
1705 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1711 // | \ DAG's like cheese
1714 // [TokenFactor] [Op]
1721 // In this case, the TokenFactor becomes part of our match and we rewrite it
1722 // as a new TokenFactor.
1724 // To distinguish these two cases, do a recursive walk down the uses.
1725 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1727 // If the uses of the TokenFactor are just already-selected nodes, ignore
1728 // it, it is "below" our pattern.
1730 case CR_InducesCycle:
1731 // If the uses of the TokenFactor lead to nodes that are not part of our
1732 // pattern that are not selected, folding would turn this into a cycle,
1734 return CR_InducesCycle;
1735 case CR_LeadsToInteriorNode:
1736 break; // Otherwise, keep processing.
1739 // Okay, we know we're in the interesting interior case. The TokenFactor
1740 // is now going to be considered part of the pattern so that we rewrite its
1741 // uses (it may have uses that are not part of the pattern) with the
1742 // ultimate chain result of the generated code. We will also add its chain
1743 // inputs as inputs to the ultimate TokenFactor we create.
1744 Result = CR_LeadsToInteriorNode;
1745 ChainedNodesInPattern.push_back(User);
1746 InteriorChainedNodes.push_back(User);
1753 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1754 /// operation for when the pattern matched at least one node with a chains. The
1755 /// input vector contains a list of all of the chained nodes that we match. We
1756 /// must determine if this is a valid thing to cover (i.e. matching it won't
1757 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1758 /// be used as the input node chain for the generated nodes.
1760 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1761 SelectionDAG *CurDAG) {
1762 // Walk all of the chained nodes we've matched, recursively scanning down the
1763 // users of the chain result. This adds any TokenFactor nodes that are caught
1764 // in between chained nodes to the chained and interior nodes list.
1765 SmallVector<SDNode*, 3> InteriorChainedNodes;
1766 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1767 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1768 InteriorChainedNodes) == CR_InducesCycle)
1769 return SDValue(); // Would induce a cycle.
1772 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1773 // that we are interested in. Form our input TokenFactor node.
1774 SmallVector<SDValue, 3> InputChains;
1775 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1776 // Add the input chain of this node to the InputChains list (which will be
1777 // the operands of the generated TokenFactor) if it's not an interior node.
1778 SDNode *N = ChainNodesMatched[i];
1779 if (N->getOpcode() != ISD::TokenFactor) {
1780 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1783 // Otherwise, add the input chain.
1784 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1785 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1786 InputChains.push_back(InChain);
1790 // If we have a token factor, we want to add all inputs of the token factor
1791 // that are not part of the pattern we're matching.
1792 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1793 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1794 N->getOperand(op).getNode()))
1795 InputChains.push_back(N->getOperand(op));
1800 if (InputChains.size() == 1)
1801 return InputChains[0];
1802 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1803 MVT::Other, &InputChains[0], InputChains.size());
1806 /// MorphNode - Handle morphing a node in place for the selector.
1807 SDNode *SelectionDAGISel::
1808 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1809 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1810 // It is possible we're using MorphNodeTo to replace a node with no
1811 // normal results with one that has a normal result (or we could be
1812 // adding a chain) and the input could have flags and chains as well.
1813 // In this case we need to shift the operands down.
1814 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1815 // than the old isel though.
1816 int OldFlagResultNo = -1, OldChainResultNo = -1;
1818 unsigned NTMNumResults = Node->getNumValues();
1819 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1820 OldFlagResultNo = NTMNumResults-1;
1821 if (NTMNumResults != 1 &&
1822 Node->getValueType(NTMNumResults-2) == MVT::Other)
1823 OldChainResultNo = NTMNumResults-2;
1824 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1825 OldChainResultNo = NTMNumResults-1;
1827 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1828 // that this deletes operands of the old node that become dead.
1829 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1831 // MorphNodeTo can operate in two ways: if an existing node with the
1832 // specified operands exists, it can just return it. Otherwise, it
1833 // updates the node in place to have the requested operands.
1835 // If we updated the node in place, reset the node ID. To the isel,
1836 // this should be just like a newly allocated machine node.
1840 unsigned ResNumResults = Res->getNumValues();
1841 // Move the flag if needed.
1842 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1843 (unsigned)OldFlagResultNo != ResNumResults-1)
1844 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1845 SDValue(Res, ResNumResults-1));
1847 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1850 // Move the chain reference if needed.
1851 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1852 (unsigned)OldChainResultNo != ResNumResults-1)
1853 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1854 SDValue(Res, ResNumResults-1));
1856 // Otherwise, no replacement happened because the node already exists. Replace
1857 // Uses of the old node with the new one.
1859 CurDAG->ReplaceAllUsesWith(Node, Res);
1864 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1865 ALWAYS_INLINE static bool
1866 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1867 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1868 // Accept if it is exactly the same as a previously recorded node.
1869 unsigned RecNo = MatcherTable[MatcherIndex++];
1870 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1871 return N == RecordedNodes[RecNo];
1874 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1875 ALWAYS_INLINE static bool
1876 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1877 SelectionDAGISel &SDISel) {
1878 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1881 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1882 ALWAYS_INLINE static bool
1883 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1884 SelectionDAGISel &SDISel, SDNode *N) {
1885 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1888 ALWAYS_INLINE static bool
1889 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1891 uint16_t Opc = MatcherTable[MatcherIndex++];
1892 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1893 return N->getOpcode() == Opc;
1896 ALWAYS_INLINE static bool
1897 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1898 SDValue N, const TargetLowering &TLI) {
1899 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1900 if (N.getValueType() == VT) return true;
1902 // Handle the case when VT is iPTR.
1903 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1906 ALWAYS_INLINE static bool
1907 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1908 SDValue N, const TargetLowering &TLI,
1910 if (ChildNo >= N.getNumOperands())
1911 return false; // Match fails if out of range child #.
1912 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1916 ALWAYS_INLINE static bool
1917 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1919 return cast<CondCodeSDNode>(N)->get() ==
1920 (ISD::CondCode)MatcherTable[MatcherIndex++];
1923 ALWAYS_INLINE static bool
1924 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1925 SDValue N, const TargetLowering &TLI) {
1926 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1927 if (cast<VTSDNode>(N)->getVT() == VT)
1930 // Handle the case when VT is iPTR.
1931 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1934 ALWAYS_INLINE static bool
1935 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1937 int64_t Val = MatcherTable[MatcherIndex++];
1939 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1941 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1942 return C != 0 && C->getSExtValue() == Val;
1945 ALWAYS_INLINE static bool
1946 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1947 SDValue N, SelectionDAGISel &SDISel) {
1948 int64_t Val = MatcherTable[MatcherIndex++];
1950 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1952 if (N->getOpcode() != ISD::AND) return false;
1954 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1955 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1958 ALWAYS_INLINE static bool
1959 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1960 SDValue N, SelectionDAGISel &SDISel) {
1961 int64_t Val = MatcherTable[MatcherIndex++];
1963 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1965 if (N->getOpcode() != ISD::OR) return false;
1967 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1968 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1971 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1972 /// scope, evaluate the current node. If the current predicate is known to
1973 /// fail, set Result=true and return anything. If the current predicate is
1974 /// known to pass, set Result=false and return the MatcherIndex to continue
1975 /// with. If the current predicate is unknown, set Result=false and return the
1976 /// MatcherIndex to continue with.
1977 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1978 unsigned Index, SDValue N,
1979 bool &Result, SelectionDAGISel &SDISel,
1980 SmallVectorImpl<SDValue> &RecordedNodes){
1981 switch (Table[Index++]) {
1984 return Index-1; // Could not evaluate this predicate.
1985 case SelectionDAGISel::OPC_CheckSame:
1986 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1988 case SelectionDAGISel::OPC_CheckPatternPredicate:
1989 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1991 case SelectionDAGISel::OPC_CheckPredicate:
1992 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1994 case SelectionDAGISel::OPC_CheckOpcode:
1995 Result = !::CheckOpcode(Table, Index, N.getNode());
1997 case SelectionDAGISel::OPC_CheckType:
1998 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2000 case SelectionDAGISel::OPC_CheckChild0Type:
2001 case SelectionDAGISel::OPC_CheckChild1Type:
2002 case SelectionDAGISel::OPC_CheckChild2Type:
2003 case SelectionDAGISel::OPC_CheckChild3Type:
2004 case SelectionDAGISel::OPC_CheckChild4Type:
2005 case SelectionDAGISel::OPC_CheckChild5Type:
2006 case SelectionDAGISel::OPC_CheckChild6Type:
2007 case SelectionDAGISel::OPC_CheckChild7Type:
2008 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2009 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2011 case SelectionDAGISel::OPC_CheckCondCode:
2012 Result = !::CheckCondCode(Table, Index, N);
2014 case SelectionDAGISel::OPC_CheckValueType:
2015 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2017 case SelectionDAGISel::OPC_CheckInteger:
2018 Result = !::CheckInteger(Table, Index, N);
2020 case SelectionDAGISel::OPC_CheckAndImm:
2021 Result = !::CheckAndImm(Table, Index, N, SDISel);
2023 case SelectionDAGISel::OPC_CheckOrImm:
2024 Result = !::CheckOrImm(Table, Index, N, SDISel);
2031 /// FailIndex - If this match fails, this is the index to continue with.
2034 /// NodeStack - The node stack when the scope was formed.
2035 SmallVector<SDValue, 4> NodeStack;
2037 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2038 unsigned NumRecordedNodes;
2040 /// NumMatchedMemRefs - The number of matched memref entries.
2041 unsigned NumMatchedMemRefs;
2043 /// InputChain/InputFlag - The current chain/flag
2044 SDValue InputChain, InputFlag;
2046 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2047 bool HasChainNodesMatched, HasFlagResultNodesMatched;
2050 SDNode *SelectionDAGISel::
2051 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2052 unsigned TableSize) {
2053 // FIXME: Should these even be selected? Handle these cases in the caller?
2054 switch (NodeToMatch->getOpcode()) {
2057 case ISD::EntryToken: // These nodes remain the same.
2058 case ISD::BasicBlock:
2060 //case ISD::VALUETYPE:
2061 //case ISD::CONDCODE:
2062 case ISD::HANDLENODE:
2063 case ISD::TargetConstant:
2064 case ISD::TargetConstantFP:
2065 case ISD::TargetConstantPool:
2066 case ISD::TargetFrameIndex:
2067 case ISD::TargetExternalSymbol:
2068 case ISD::TargetBlockAddress:
2069 case ISD::TargetJumpTable:
2070 case ISD::TargetGlobalTLSAddress:
2071 case ISD::TargetGlobalAddress:
2072 case ISD::TokenFactor:
2073 case ISD::CopyFromReg:
2074 case ISD::CopyToReg:
2076 NodeToMatch->setNodeId(-1); // Mark selected.
2078 case ISD::AssertSext:
2079 case ISD::AssertZext:
2080 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2081 NodeToMatch->getOperand(0));
2083 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2084 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2087 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2089 // Set up the node stack with NodeToMatch as the only node on the stack.
2090 SmallVector<SDValue, 8> NodeStack;
2091 SDValue N = SDValue(NodeToMatch, 0);
2092 NodeStack.push_back(N);
2094 // MatchScopes - Scopes used when matching, if a match failure happens, this
2095 // indicates where to continue checking.
2096 SmallVector<MatchScope, 8> MatchScopes;
2098 // RecordedNodes - This is the set of nodes that have been recorded by the
2100 SmallVector<SDValue, 8> RecordedNodes;
2102 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2104 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2106 // These are the current input chain and flag for use when generating nodes.
2107 // Various Emit operations change these. For example, emitting a copytoreg
2108 // uses and updates these.
2109 SDValue InputChain, InputFlag;
2111 // ChainNodesMatched - If a pattern matches nodes that have input/output
2112 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2113 // which ones they are. The result is captured into this list so that we can
2114 // update the chain results when the pattern is complete.
2115 SmallVector<SDNode*, 3> ChainNodesMatched;
2116 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2118 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2119 NodeToMatch->dump(CurDAG);
2122 // Determine where to start the interpreter. Normally we start at opcode #0,
2123 // but if the state machine starts with an OPC_SwitchOpcode, then we
2124 // accelerate the first lookup (which is guaranteed to be hot) with the
2125 // OpcodeOffset table.
2126 unsigned MatcherIndex = 0;
2128 if (!OpcodeOffset.empty()) {
2129 // Already computed the OpcodeOffset table, just index into it.
2130 if (N.getOpcode() < OpcodeOffset.size())
2131 MatcherIndex = OpcodeOffset[N.getOpcode()];
2132 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2134 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2135 // Otherwise, the table isn't computed, but the state machine does start
2136 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2137 // is the first time we're selecting an instruction.
2140 // Get the size of this case.
2141 unsigned CaseSize = MatcherTable[Idx++];
2143 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2144 if (CaseSize == 0) break;
2146 // Get the opcode, add the index to the table.
2147 uint16_t Opc = MatcherTable[Idx++];
2148 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2149 if (Opc >= OpcodeOffset.size())
2150 OpcodeOffset.resize((Opc+1)*2);
2151 OpcodeOffset[Opc] = Idx;
2155 // Okay, do the lookup for the first opcode.
2156 if (N.getOpcode() < OpcodeOffset.size())
2157 MatcherIndex = OpcodeOffset[N.getOpcode()];
2161 assert(MatcherIndex < TableSize && "Invalid index");
2163 unsigned CurrentOpcodeIndex = MatcherIndex;
2165 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2168 // Okay, the semantics of this operation are that we should push a scope
2169 // then evaluate the first child. However, pushing a scope only to have
2170 // the first check fail (which then pops it) is inefficient. If we can
2171 // determine immediately that the first check (or first several) will
2172 // immediately fail, don't even bother pushing a scope for them.
2176 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2177 if (NumToSkip & 128)
2178 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2179 // Found the end of the scope with no match.
2180 if (NumToSkip == 0) {
2185 FailIndex = MatcherIndex+NumToSkip;
2187 unsigned MatcherIndexOfPredicate = MatcherIndex;
2188 (void)MatcherIndexOfPredicate; // silence warning.
2190 // If we can't evaluate this predicate without pushing a scope (e.g. if
2191 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2192 // push the scope and evaluate the full predicate chain.
2194 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2195 Result, *this, RecordedNodes);
2199 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2200 << "index " << MatcherIndexOfPredicate
2201 << ", continuing at " << FailIndex << "\n");
2202 ++NumDAGIselRetries;
2204 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2205 // move to the next case.
2206 MatcherIndex = FailIndex;
2209 // If the whole scope failed to match, bail.
2210 if (FailIndex == 0) break;
2212 // Push a MatchScope which indicates where to go if the first child fails
2214 MatchScope NewEntry;
2215 NewEntry.FailIndex = FailIndex;
2216 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2217 NewEntry.NumRecordedNodes = RecordedNodes.size();
2218 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2219 NewEntry.InputChain = InputChain;
2220 NewEntry.InputFlag = InputFlag;
2221 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2222 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2223 MatchScopes.push_back(NewEntry);
2226 case OPC_RecordNode:
2227 // Remember this node, it may end up being an operand in the pattern.
2228 RecordedNodes.push_back(N);
2231 case OPC_RecordChild0: case OPC_RecordChild1:
2232 case OPC_RecordChild2: case OPC_RecordChild3:
2233 case OPC_RecordChild4: case OPC_RecordChild5:
2234 case OPC_RecordChild6: case OPC_RecordChild7: {
2235 unsigned ChildNo = Opcode-OPC_RecordChild0;
2236 if (ChildNo >= N.getNumOperands())
2237 break; // Match fails if out of range child #.
2239 RecordedNodes.push_back(N->getOperand(ChildNo));
2242 case OPC_RecordMemRef:
2243 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2246 case OPC_CaptureFlagInput:
2247 // If the current node has an input flag, capture it in InputFlag.
2248 if (N->getNumOperands() != 0 &&
2249 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2250 InputFlag = N->getOperand(N->getNumOperands()-1);
2253 case OPC_MoveChild: {
2254 unsigned ChildNo = MatcherTable[MatcherIndex++];
2255 if (ChildNo >= N.getNumOperands())
2256 break; // Match fails if out of range child #.
2257 N = N.getOperand(ChildNo);
2258 NodeStack.push_back(N);
2262 case OPC_MoveParent:
2263 // Pop the current node off the NodeStack.
2264 NodeStack.pop_back();
2265 assert(!NodeStack.empty() && "Node stack imbalance!");
2266 N = NodeStack.back();
2270 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2272 case OPC_CheckPatternPredicate:
2273 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2275 case OPC_CheckPredicate:
2276 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2280 case OPC_CheckComplexPat: {
2281 unsigned CPNum = MatcherTable[MatcherIndex++];
2282 unsigned RecNo = MatcherTable[MatcherIndex++];
2283 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2284 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2289 case OPC_CheckOpcode:
2290 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2294 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2297 case OPC_SwitchOpcode: {
2298 unsigned CurNodeOpcode = N.getOpcode();
2299 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2302 // Get the size of this case.
2303 CaseSize = MatcherTable[MatcherIndex++];
2305 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2306 if (CaseSize == 0) break;
2308 uint16_t Opc = MatcherTable[MatcherIndex++];
2309 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2311 // If the opcode matches, then we will execute this case.
2312 if (CurNodeOpcode == Opc)
2315 // Otherwise, skip over this case.
2316 MatcherIndex += CaseSize;
2319 // If no cases matched, bail out.
2320 if (CaseSize == 0) break;
2322 // Otherwise, execute the case we found.
2323 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2324 << " to " << MatcherIndex << "\n");
2328 case OPC_SwitchType: {
2329 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2330 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2333 // Get the size of this case.
2334 CaseSize = MatcherTable[MatcherIndex++];
2336 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2337 if (CaseSize == 0) break;
2339 MVT::SimpleValueType CaseVT =
2340 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2341 if (CaseVT == MVT::iPTR)
2342 CaseVT = TLI.getPointerTy().SimpleTy;
2344 // If the VT matches, then we will execute this case.
2345 if (CurNodeVT == CaseVT)
2348 // Otherwise, skip over this case.
2349 MatcherIndex += CaseSize;
2352 // If no cases matched, bail out.
2353 if (CaseSize == 0) break;
2355 // Otherwise, execute the case we found.
2356 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2357 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2360 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2361 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2362 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2363 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2364 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2365 Opcode-OPC_CheckChild0Type))
2368 case OPC_CheckCondCode:
2369 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2371 case OPC_CheckValueType:
2372 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2374 case OPC_CheckInteger:
2375 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2377 case OPC_CheckAndImm:
2378 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2380 case OPC_CheckOrImm:
2381 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2384 case OPC_CheckFoldableChainNode: {
2385 assert(NodeStack.size() != 1 && "No parent node");
2386 // Verify that all intermediate nodes between the root and this one have
2388 bool HasMultipleUses = false;
2389 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2390 if (!NodeStack[i].hasOneUse()) {
2391 HasMultipleUses = true;
2394 if (HasMultipleUses) break;
2396 // Check to see that the target thinks this is profitable to fold and that
2397 // we can fold it without inducing cycles in the graph.
2398 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2400 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2401 NodeToMatch, true/*We validate our own chains*/))
2406 case OPC_EmitInteger: {
2407 MVT::SimpleValueType VT =
2408 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2409 int64_t Val = MatcherTable[MatcherIndex++];
2411 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2412 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2415 case OPC_EmitRegister: {
2416 MVT::SimpleValueType VT =
2417 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2418 unsigned RegNo = MatcherTable[MatcherIndex++];
2419 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2423 case OPC_EmitConvertToTarget: {
2424 // Convert from IMM/FPIMM to target version.
2425 unsigned RecNo = MatcherTable[MatcherIndex++];
2426 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2427 SDValue Imm = RecordedNodes[RecNo];
2429 if (Imm->getOpcode() == ISD::Constant) {
2430 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2431 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2432 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2433 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2434 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2437 RecordedNodes.push_back(Imm);
2441 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2442 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2443 // These are space-optimized forms of OPC_EmitMergeInputChains.
2444 assert(InputChain.getNode() == 0 &&
2445 "EmitMergeInputChains should be the first chain producing node");
2446 assert(ChainNodesMatched.empty() &&
2447 "Should only have one EmitMergeInputChains per match");
2449 // Read all of the chained nodes.
2450 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2451 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2452 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2454 // FIXME: What if other value results of the node have uses not matched
2456 if (ChainNodesMatched.back() != NodeToMatch &&
2457 !RecordedNodes[RecNo].hasOneUse()) {
2458 ChainNodesMatched.clear();
2462 // Merge the input chains if they are not intra-pattern references.
2463 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2465 if (InputChain.getNode() == 0)
2466 break; // Failed to merge.
2470 case OPC_EmitMergeInputChains: {
2471 assert(InputChain.getNode() == 0 &&
2472 "EmitMergeInputChains should be the first chain producing node");
2473 // This node gets a list of nodes we matched in the input that have
2474 // chains. We want to token factor all of the input chains to these nodes
2475 // together. However, if any of the input chains is actually one of the
2476 // nodes matched in this pattern, then we have an intra-match reference.
2477 // Ignore these because the newly token factored chain should not refer to
2479 unsigned NumChains = MatcherTable[MatcherIndex++];
2480 assert(NumChains != 0 && "Can't TF zero chains");
2482 assert(ChainNodesMatched.empty() &&
2483 "Should only have one EmitMergeInputChains per match");
2485 // Read all of the chained nodes.
2486 for (unsigned i = 0; i != NumChains; ++i) {
2487 unsigned RecNo = MatcherTable[MatcherIndex++];
2488 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2489 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2491 // FIXME: What if other value results of the node have uses not matched
2493 if (ChainNodesMatched.back() != NodeToMatch &&
2494 !RecordedNodes[RecNo].hasOneUse()) {
2495 ChainNodesMatched.clear();
2500 // If the inner loop broke out, the match fails.
2501 if (ChainNodesMatched.empty())
2504 // Merge the input chains if they are not intra-pattern references.
2505 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2507 if (InputChain.getNode() == 0)
2508 break; // Failed to merge.
2513 case OPC_EmitCopyToReg: {
2514 unsigned RecNo = MatcherTable[MatcherIndex++];
2515 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2516 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2518 if (InputChain.getNode() == 0)
2519 InputChain = CurDAG->getEntryNode();
2521 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2522 DestPhysReg, RecordedNodes[RecNo],
2525 InputFlag = InputChain.getValue(1);
2529 case OPC_EmitNodeXForm: {
2530 unsigned XFormNo = MatcherTable[MatcherIndex++];
2531 unsigned RecNo = MatcherTable[MatcherIndex++];
2532 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2533 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2538 case OPC_MorphNodeTo: {
2539 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2540 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2541 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2542 // Get the result VT list.
2543 unsigned NumVTs = MatcherTable[MatcherIndex++];
2544 SmallVector<EVT, 4> VTs;
2545 for (unsigned i = 0; i != NumVTs; ++i) {
2546 MVT::SimpleValueType VT =
2547 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2548 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2552 if (EmitNodeInfo & OPFL_Chain)
2553 VTs.push_back(MVT::Other);
2554 if (EmitNodeInfo & OPFL_FlagOutput)
2555 VTs.push_back(MVT::Flag);
2557 // This is hot code, so optimize the two most common cases of 1 and 2
2560 if (VTs.size() == 1)
2561 VTList = CurDAG->getVTList(VTs[0]);
2562 else if (VTs.size() == 2)
2563 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2565 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2567 // Get the operand list.
2568 unsigned NumOps = MatcherTable[MatcherIndex++];
2569 SmallVector<SDValue, 8> Ops;
2570 for (unsigned i = 0; i != NumOps; ++i) {
2571 unsigned RecNo = MatcherTable[MatcherIndex++];
2573 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2575 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2576 Ops.push_back(RecordedNodes[RecNo]);
2579 // If there are variadic operands to add, handle them now.
2580 if (EmitNodeInfo & OPFL_VariadicInfo) {
2581 // Determine the start index to copy from.
2582 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2583 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2584 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2585 "Invalid variadic node");
2586 // Copy all of the variadic operands, not including a potential flag
2588 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2590 SDValue V = NodeToMatch->getOperand(i);
2591 if (V.getValueType() == MVT::Flag) break;
2596 // If this has chain/flag inputs, add them.
2597 if (EmitNodeInfo & OPFL_Chain)
2598 Ops.push_back(InputChain);
2599 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2600 Ops.push_back(InputFlag);
2604 if (Opcode != OPC_MorphNodeTo) {
2605 // If this is a normal EmitNode command, just create the new node and
2606 // add the results to the RecordedNodes list.
2607 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2608 VTList, Ops.data(), Ops.size());
2610 // Add all the non-flag/non-chain results to the RecordedNodes list.
2611 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2612 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2613 RecordedNodes.push_back(SDValue(Res, i));
2617 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2621 // If the node had chain/flag results, update our notion of the current
2623 if (EmitNodeInfo & OPFL_FlagOutput) {
2624 InputFlag = SDValue(Res, VTs.size()-1);
2625 if (EmitNodeInfo & OPFL_Chain)
2626 InputChain = SDValue(Res, VTs.size()-2);
2627 } else if (EmitNodeInfo & OPFL_Chain)
2628 InputChain = SDValue(Res, VTs.size()-1);
2630 // If the OPFL_MemRefs flag is set on this node, slap all of the
2631 // accumulated memrefs onto it.
2633 // FIXME: This is vastly incorrect for patterns with multiple outputs
2634 // instructions that access memory and for ComplexPatterns that match
2636 if (EmitNodeInfo & OPFL_MemRefs) {
2637 MachineSDNode::mmo_iterator MemRefs =
2638 MF->allocateMemRefsArray(MatchedMemRefs.size());
2639 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2640 cast<MachineSDNode>(Res)
2641 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2645 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2646 << " node: "; Res->dump(CurDAG); errs() << "\n");
2648 // If this was a MorphNodeTo then we're completely done!
2649 if (Opcode == OPC_MorphNodeTo) {
2650 // Update chain and flag uses.
2651 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2652 InputFlag, FlagResultNodesMatched, true);
2659 case OPC_MarkFlagResults: {
2660 unsigned NumNodes = MatcherTable[MatcherIndex++];
2662 // Read and remember all the flag-result nodes.
2663 for (unsigned i = 0; i != NumNodes; ++i) {
2664 unsigned RecNo = MatcherTable[MatcherIndex++];
2666 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2668 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2669 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2674 case OPC_CompleteMatch: {
2675 // The match has been completed, and any new nodes (if any) have been
2676 // created. Patch up references to the matched dag to use the newly
2678 unsigned NumResults = MatcherTable[MatcherIndex++];
2680 for (unsigned i = 0; i != NumResults; ++i) {
2681 unsigned ResSlot = MatcherTable[MatcherIndex++];
2683 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2685 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2686 SDValue Res = RecordedNodes[ResSlot];
2688 assert(i < NodeToMatch->getNumValues() &&
2689 NodeToMatch->getValueType(i) != MVT::Other &&
2690 NodeToMatch->getValueType(i) != MVT::Flag &&
2691 "Invalid number of results to complete!");
2692 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2693 NodeToMatch->getValueType(i) == MVT::iPTR ||
2694 Res.getValueType() == MVT::iPTR ||
2695 NodeToMatch->getValueType(i).getSizeInBits() ==
2696 Res.getValueType().getSizeInBits()) &&
2697 "invalid replacement");
2698 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2701 // If the root node defines a flag, add it to the flag nodes to update
2703 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2704 FlagResultNodesMatched.push_back(NodeToMatch);
2706 // Update chain and flag uses.
2707 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2708 InputFlag, FlagResultNodesMatched, false);
2710 assert(NodeToMatch->use_empty() &&
2711 "Didn't replace all uses of the node?");
2713 // FIXME: We just return here, which interacts correctly with SelectRoot
2714 // above. We should fix this to not return an SDNode* anymore.
2719 // If the code reached this point, then the match failed. See if there is
2720 // another child to try in the current 'Scope', otherwise pop it until we
2721 // find a case to check.
2722 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2723 ++NumDAGIselRetries;
2725 if (MatchScopes.empty()) {
2726 CannotYetSelect(NodeToMatch);
2730 // Restore the interpreter state back to the point where the scope was
2732 MatchScope &LastScope = MatchScopes.back();
2733 RecordedNodes.resize(LastScope.NumRecordedNodes);
2735 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2736 N = NodeStack.back();
2738 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2739 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2740 MatcherIndex = LastScope.FailIndex;
2742 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2744 InputChain = LastScope.InputChain;
2745 InputFlag = LastScope.InputFlag;
2746 if (!LastScope.HasChainNodesMatched)
2747 ChainNodesMatched.clear();
2748 if (!LastScope.HasFlagResultNodesMatched)
2749 FlagResultNodesMatched.clear();
2751 // Check to see what the offset is at the new MatcherIndex. If it is zero
2752 // we have reached the end of this scope, otherwise we have another child
2753 // in the current scope to try.
2754 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2755 if (NumToSkip & 128)
2756 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2758 // If we have another child in this scope to match, update FailIndex and
2760 if (NumToSkip != 0) {
2761 LastScope.FailIndex = MatcherIndex+NumToSkip;
2765 // End of this scope, pop it and try the next child in the containing
2767 MatchScopes.pop_back();
2774 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2776 raw_string_ostream Msg(msg);
2777 Msg << "Cannot yet select: ";
2779 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2780 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2781 N->getOpcode() != ISD::INTRINSIC_VOID) {
2782 N->printrFull(Msg, CurDAG);
2784 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2786 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2787 if (iid < Intrinsic::num_intrinsics)
2788 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2789 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2790 Msg << "target intrinsic %" << TII->getName(iid);
2792 Msg << "unknown intrinsic #" << iid;
2794 llvm_report_error(Msg.str());
2797 char SelectionDAGISel::ID = 0;