1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineDebugInfoDesc.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/SchedulerRegistry.h"
38 #include "llvm/CodeGen/SelectionDAG.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetData.h"
41 #include "llvm/Target/TargetFrameInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/MathExtras.h"
49 #include "llvm/Support/Timer.h"
54 EnableValueProp("enable-value-prop", cl::Hidden, cl::init(false));
59 ViewISelDAGs("view-isel-dags", cl::Hidden,
60 cl::desc("Pop up a window to show isel dags as they are selected"));
62 ViewSchedDAGs("view-sched-dags", cl::Hidden,
63 cl::desc("Pop up a window to show sched dags as they are processed"));
65 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
66 cl::desc("Pop up a window to show SUnit dags after they are processed"));
68 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
71 //===---------------------------------------------------------------------===//
73 /// RegisterScheduler class - Track the registration of instruction schedulers.
75 //===---------------------------------------------------------------------===//
76 MachinePassRegistry RegisterScheduler::Registry;
78 //===---------------------------------------------------------------------===//
80 /// ISHeuristic command line option for instruction schedulers.
82 //===---------------------------------------------------------------------===//
83 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
84 RegisterPassParser<RegisterScheduler> >
85 ISHeuristic("pre-RA-sched",
86 cl::init(&createDefaultScheduler),
87 cl::desc("Instruction schedulers available (before register"
90 static RegisterScheduler
91 defaultListDAGScheduler("default", " Best scheduler for the target",
92 createDefaultScheduler);
94 namespace { struct SDISelAsmOperandInfo; }
96 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
97 /// insertvalue or extractvalue indices that identify a member, return
98 /// the linearized index of the start of the member.
100 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
101 const unsigned *Indices,
102 const unsigned *IndicesEnd,
103 unsigned CurIndex = 0) {
104 // Base case: We're done.
105 if (Indices && Indices == IndicesEnd)
108 // Given a struct type, recursively traverse the elements.
109 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
110 for (StructType::element_iterator EB = STy->element_begin(),
112 EE = STy->element_end();
114 if (Indices && *Indices == unsigned(EI - EB))
115 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
116 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
119 // Given an array type, recursively traverse the elements.
120 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
121 const Type *EltTy = ATy->getElementType();
122 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
123 if (Indices && *Indices == i)
124 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
125 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
128 // We haven't found the type we're looking for, so keep searching.
132 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
133 /// MVTs that represent all the individual underlying
134 /// non-aggregate types that comprise it.
136 /// If Offsets is non-null, it points to a vector to be filled in
137 /// with the in-memory offsets of each of the individual values.
139 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
140 SmallVectorImpl<MVT> &ValueVTs,
141 SmallVectorImpl<uint64_t> *Offsets = 0,
142 uint64_t StartingOffset = 0) {
143 // Given a struct type, recursively traverse the elements.
144 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
145 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
146 for (StructType::element_iterator EB = STy->element_begin(),
148 EE = STy->element_end();
150 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
151 StartingOffset + SL->getElementOffset(EI - EB));
154 // Given an array type, recursively traverse the elements.
155 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
156 const Type *EltTy = ATy->getElementType();
157 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
158 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
159 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
160 StartingOffset + i * EltSize);
163 // Base case: we can get an MVT for this LLVM IR type.
164 ValueVTs.push_back(TLI.getValueType(Ty));
166 Offsets->push_back(StartingOffset);
170 /// RegsForValue - This struct represents the registers (physical or virtual)
171 /// that a particular set of values is assigned, and the type information about
172 /// the value. The most common situation is to represent one value at a time,
173 /// but struct or array values are handled element-wise as multiple values.
174 /// The splitting of aggregates is performed recursively, so that we never
175 /// have aggregate-typed registers. The values at this point do not necessarily
176 /// have legal types, so each value may require one or more registers of some
179 struct VISIBILITY_HIDDEN RegsForValue {
180 /// TLI - The TargetLowering object.
182 const TargetLowering *TLI;
184 /// ValueVTs - The value types of the values, which may not be legal, and
185 /// may need be promoted or synthesized from one or more registers.
187 SmallVector<MVT, 4> ValueVTs;
189 /// RegVTs - The value types of the registers. This is the same size as
190 /// ValueVTs and it records, for each value, what the type of the assigned
191 /// register or registers are. (Individual values are never synthesized
192 /// from more than one type of register.)
194 /// With virtual registers, the contents of RegVTs is redundant with TLI's
195 /// getRegisterType member function, however when with physical registers
196 /// it is necessary to have a separate record of the types.
198 SmallVector<MVT, 4> RegVTs;
200 /// Regs - This list holds the registers assigned to the values.
201 /// Each legal or promoted value requires one register, and each
202 /// expanded value requires multiple registers.
204 SmallVector<unsigned, 4> Regs;
206 RegsForValue() : TLI(0) {}
208 RegsForValue(const TargetLowering &tli,
209 const SmallVector<unsigned, 4> ®s,
210 MVT regvt, MVT valuevt)
211 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
212 RegsForValue(const TargetLowering &tli,
213 const SmallVector<unsigned, 4> ®s,
214 const SmallVector<MVT, 4> ®vts,
215 const SmallVector<MVT, 4> &valuevts)
216 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
217 RegsForValue(const TargetLowering &tli,
218 unsigned Reg, const Type *Ty) : TLI(&tli) {
219 ComputeValueVTs(tli, Ty, ValueVTs);
221 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
222 MVT ValueVT = ValueVTs[Value];
223 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
224 MVT RegisterVT = TLI->getRegisterType(ValueVT);
225 for (unsigned i = 0; i != NumRegs; ++i)
226 Regs.push_back(Reg + i);
227 RegVTs.push_back(RegisterVT);
232 /// append - Add the specified values to this one.
233 void append(const RegsForValue &RHS) {
235 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
236 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
237 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
241 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
242 /// this value and returns the result as a ValueVTs value. This uses
243 /// Chain/Flag as the input and updates them for the output Chain/Flag.
244 /// If the Flag pointer is NULL, no flag is used.
245 SDOperand getCopyFromRegs(SelectionDAG &DAG,
246 SDOperand &Chain, SDOperand *Flag) const;
248 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
249 /// specified value into the registers specified by this object. This uses
250 /// Chain/Flag as the input and updates them for the output Chain/Flag.
251 /// If the Flag pointer is NULL, no flag is used.
252 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
253 SDOperand &Chain, SDOperand *Flag) const;
255 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
256 /// operand list. This adds the code marker and includes the number of
257 /// values added into it.
258 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
259 std::vector<SDOperand> &Ops) const;
264 //===--------------------------------------------------------------------===//
265 /// createDefaultScheduler - This creates an instruction scheduler appropriate
267 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
269 MachineBasicBlock *BB) {
270 TargetLowering &TLI = IS->getTargetLowering();
272 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
273 return createTDListDAGScheduler(IS, DAG, BB);
275 assert(TLI.getSchedulingPreference() ==
276 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
277 return createBURRListDAGScheduler(IS, DAG, BB);
282 //===--------------------------------------------------------------------===//
283 /// FunctionLoweringInfo - This contains information that is global to a
284 /// function that is used when lowering a region of the function.
285 class FunctionLoweringInfo {
290 MachineRegisterInfo &RegInfo;
292 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
294 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
295 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
297 /// ValueMap - Since we emit code for the function a basic block at a time,
298 /// we must remember which virtual registers hold the values for
299 /// cross-basic-block values.
300 DenseMap<const Value*, unsigned> ValueMap;
302 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
303 /// the entry block. This allows the allocas to be efficiently referenced
304 /// anywhere in the function.
305 std::map<const AllocaInst*, int> StaticAllocaMap;
308 SmallSet<Instruction*, 8> CatchInfoLost;
309 SmallSet<Instruction*, 8> CatchInfoFound;
312 unsigned MakeReg(MVT VT) {
313 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
316 /// isExportedInst - Return true if the specified value is an instruction
317 /// exported from its block.
318 bool isExportedInst(const Value *V) {
319 return ValueMap.count(V);
322 unsigned CreateRegForValue(const Value *V);
324 unsigned InitializeRegForValue(const Value *V) {
325 unsigned &R = ValueMap[V];
326 assert(R == 0 && "Already initialized this value register!");
327 return R = CreateRegForValue(V);
331 unsigned NumSignBits;
332 APInt KnownOne, KnownZero;
333 LiveOutInfo() : NumSignBits(0) {}
336 /// LiveOutRegInfo - Information about live out vregs, indexed by their
337 /// register number offset by 'FirstVirtualRegister'.
338 std::vector<LiveOutInfo> LiveOutRegInfo;
342 /// isSelector - Return true if this instruction is a call to the
343 /// eh.selector intrinsic.
344 static bool isSelector(Instruction *I) {
345 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
346 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
347 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
351 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
352 /// PHI nodes or outside of the basic block that defines it, or used by a
353 /// switch or atomic instruction, which may expand to multiple basic blocks.
354 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
355 if (isa<PHINode>(I)) return true;
356 BasicBlock *BB = I->getParent();
357 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
358 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
359 // FIXME: Remove switchinst special case.
360 isa<SwitchInst>(*UI))
365 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
366 /// entry block, return true. This includes arguments used by switches, since
367 /// the switch may expand into multiple basic blocks.
368 static bool isOnlyUsedInEntryBlock(Argument *A) {
369 BasicBlock *Entry = A->getParent()->begin();
370 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
371 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
372 return false; // Use not in entry block.
376 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
377 Function &fn, MachineFunction &mf)
378 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
380 // Create a vreg for each argument register that is not dead and is used
381 // outside of the entry block for the function.
382 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
384 if (!isOnlyUsedInEntryBlock(AI))
385 InitializeRegForValue(AI);
387 // Initialize the mapping of values to registers. This is only set up for
388 // instruction values that are used outside of the block that defines
390 Function::iterator BB = Fn.begin(), EB = Fn.end();
391 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
392 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
393 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
394 const Type *Ty = AI->getAllocatedType();
395 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
397 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
400 TySize *= CUI->getZExtValue(); // Get total allocated size.
401 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
402 StaticAllocaMap[AI] =
403 MF.getFrameInfo()->CreateStackObject(TySize, Align);
406 for (; BB != EB; ++BB)
407 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
408 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
409 if (!isa<AllocaInst>(I) ||
410 !StaticAllocaMap.count(cast<AllocaInst>(I)))
411 InitializeRegForValue(I);
413 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
414 // also creates the initial PHI MachineInstrs, though none of the input
415 // operands are populated.
416 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
417 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
419 MF.getBasicBlockList().push_back(MBB);
421 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
424 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
425 if (PN->use_empty()) continue;
427 MVT VT = TLI.getValueType(PN->getType());
428 unsigned NumRegisters = TLI.getNumRegisters(VT);
429 unsigned PHIReg = ValueMap[PN];
430 assert(PHIReg && "PHI node does not have an assigned virtual register!");
431 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
432 for (unsigned i = 0; i != NumRegisters; ++i)
433 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
438 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
439 /// the correctly promoted or expanded types. Assign these registers
440 /// consecutive vreg numbers and return the first assigned number.
442 /// In the case that the given value has struct or array type, this function
443 /// will assign registers for each member or element.
445 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
446 SmallVector<MVT, 4> ValueVTs;
447 ComputeValueVTs(TLI, V->getType(), ValueVTs);
449 unsigned FirstReg = 0;
450 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
451 MVT ValueVT = ValueVTs[Value];
452 MVT RegisterVT = TLI.getRegisterType(ValueVT);
454 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
455 for (unsigned i = 0; i != NumRegs; ++i) {
456 unsigned R = MakeReg(RegisterVT);
457 if (!FirstReg) FirstReg = R;
463 //===----------------------------------------------------------------------===//
464 /// SelectionDAGLowering - This is the common target-independent lowering
465 /// implementation that is parameterized by a TargetLowering object.
466 /// Also, targets can overload any lowering method.
469 class SelectionDAGLowering {
470 MachineBasicBlock *CurMBB;
472 DenseMap<const Value*, SDOperand> NodeMap;
474 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
475 /// them up and then emit token factor nodes when possible. This allows us to
476 /// get simple disambiguation between loads without worrying about alias
478 SmallVector<SDOperand, 8> PendingLoads;
480 /// PendingExports - CopyToReg nodes that copy values to virtual registers
481 /// for export to other blocks need to be emitted before any terminator
482 /// instruction, but they have no other ordering requirements. We bunch them
483 /// up and the emit a single tokenfactor for them just before terminator
485 std::vector<SDOperand> PendingExports;
487 /// Case - A struct to record the Value for a switch case, and the
488 /// case's target basic block.
492 MachineBasicBlock* BB;
494 Case() : Low(0), High(0), BB(0) { }
495 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
496 Low(low), High(high), BB(bb) { }
497 uint64_t size() const {
498 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
499 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
500 return (rHigh - rLow + 1ULL);
506 MachineBasicBlock* BB;
509 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
510 Mask(mask), BB(bb), Bits(bits) { }
513 typedef std::vector<Case> CaseVector;
514 typedef std::vector<CaseBits> CaseBitsVector;
515 typedef CaseVector::iterator CaseItr;
516 typedef std::pair<CaseItr, CaseItr> CaseRange;
518 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
519 /// of conditional branches.
521 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
522 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
524 /// CaseBB - The MBB in which to emit the compare and branch
525 MachineBasicBlock *CaseBB;
526 /// LT, GE - If nonzero, we know the current case value must be less-than or
527 /// greater-than-or-equal-to these Constants.
530 /// Range - A pair of iterators representing the range of case values to be
531 /// processed at this point in the binary search tree.
535 typedef std::vector<CaseRec> CaseRecVector;
537 /// The comparison function for sorting the switch case values in the vector.
538 /// WARNING: Case ranges should be disjoint!
540 bool operator () (const Case& C1, const Case& C2) {
541 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
542 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
543 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
544 return CI1->getValue().slt(CI2->getValue());
549 bool operator () (const CaseBits& C1, const CaseBits& C2) {
550 return C1.Bits > C2.Bits;
554 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
557 // TLI - This is information that describes the available target features we
558 // need for lowering. This indicates when operations are unavailable,
559 // implemented with a libcall, etc.
562 const TargetData *TD;
565 /// SwitchCases - Vector of CaseBlock structures used to communicate
566 /// SwitchInst code generation information.
567 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
568 /// JTCases - Vector of JumpTable structures used to communicate
569 /// SwitchInst code generation information.
570 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
571 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
573 /// FuncInfo - Information about the function as a whole.
575 FunctionLoweringInfo &FuncInfo;
577 /// GCI - Garbage collection metadata for the function.
578 CollectorMetadata *GCI;
580 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
582 FunctionLoweringInfo &funcinfo,
583 CollectorMetadata *gci)
584 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
585 FuncInfo(funcinfo), GCI(gci) {
588 /// getRoot - Return the current virtual root of the Selection DAG,
589 /// flushing any PendingLoad items. This must be done before emitting
590 /// a store or any other node that may need to be ordered after any
591 /// prior load instructions.
593 SDOperand getRoot() {
594 if (PendingLoads.empty())
595 return DAG.getRoot();
597 if (PendingLoads.size() == 1) {
598 SDOperand Root = PendingLoads[0];
600 PendingLoads.clear();
604 // Otherwise, we have to make a token factor node.
605 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
606 &PendingLoads[0], PendingLoads.size());
607 PendingLoads.clear();
612 /// getControlRoot - Similar to getRoot, but instead of flushing all the
613 /// PendingLoad items, flush all the PendingExports items. It is necessary
614 /// to do this before emitting a terminator instruction.
616 SDOperand getControlRoot() {
617 SDOperand Root = DAG.getRoot();
619 if (PendingExports.empty())
622 // Turn all of the CopyToReg chains into one factored node.
623 if (Root.getOpcode() != ISD::EntryToken) {
624 unsigned i = 0, e = PendingExports.size();
625 for (; i != e; ++i) {
626 assert(PendingExports[i].Val->getNumOperands() > 1);
627 if (PendingExports[i].Val->getOperand(0) == Root)
628 break; // Don't add the root if we already indirectly depend on it.
632 PendingExports.push_back(Root);
635 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
637 PendingExports.size());
638 PendingExports.clear();
643 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
645 void visit(Instruction &I) { visit(I.getOpcode(), I); }
647 void visit(unsigned Opcode, User &I) {
648 // Note: this doesn't use InstVisitor, because it has to work with
649 // ConstantExpr's in addition to instructions.
651 default: assert(0 && "Unknown instruction type encountered!");
653 // Build the switch statement using the Instruction.def file.
654 #define HANDLE_INST(NUM, OPCODE, CLASS) \
655 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
656 #include "llvm/Instruction.def"
660 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
662 SDOperand getValue(const Value *V);
664 void setValue(const Value *V, SDOperand NewN) {
665 SDOperand &N = NodeMap[V];
666 assert(N.Val == 0 && "Already set a value for this node!");
670 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
671 std::set<unsigned> &OutputRegs,
672 std::set<unsigned> &InputRegs);
674 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
675 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
677 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
678 void ExportFromCurrentBlock(Value *V);
679 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
680 MachineBasicBlock *LandingPad = NULL);
682 // Terminator instructions.
683 void visitRet(ReturnInst &I);
684 void visitBr(BranchInst &I);
685 void visitSwitch(SwitchInst &I);
686 void visitUnreachable(UnreachableInst &I) { /* noop */ }
688 // Helpers for visitSwitch
689 bool handleSmallSwitchRange(CaseRec& CR,
690 CaseRecVector& WorkList,
692 MachineBasicBlock* Default);
693 bool handleJTSwitchCase(CaseRec& CR,
694 CaseRecVector& WorkList,
696 MachineBasicBlock* Default);
697 bool handleBTSplitSwitchCase(CaseRec& CR,
698 CaseRecVector& WorkList,
700 MachineBasicBlock* Default);
701 bool handleBitTestsSwitchCase(CaseRec& CR,
702 CaseRecVector& WorkList,
704 MachineBasicBlock* Default);
705 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
706 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
707 void visitBitTestCase(MachineBasicBlock* NextMBB,
709 SelectionDAGISel::BitTestCase &B);
710 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
711 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
712 SelectionDAGISel::JumpTableHeader &JTH);
714 // These all get lowered before this pass.
715 void visitInvoke(InvokeInst &I);
716 void visitUnwind(UnwindInst &I);
718 void visitBinary(User &I, unsigned OpCode);
719 void visitShift(User &I, unsigned Opcode);
720 void visitAdd(User &I) {
721 if (I.getType()->isFPOrFPVector())
722 visitBinary(I, ISD::FADD);
724 visitBinary(I, ISD::ADD);
726 void visitSub(User &I);
727 void visitMul(User &I) {
728 if (I.getType()->isFPOrFPVector())
729 visitBinary(I, ISD::FMUL);
731 visitBinary(I, ISD::MUL);
733 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
734 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
735 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
736 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
737 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
738 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
739 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
740 void visitOr (User &I) { visitBinary(I, ISD::OR); }
741 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
742 void visitShl (User &I) { visitShift(I, ISD::SHL); }
743 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
744 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
745 void visitICmp(User &I);
746 void visitFCmp(User &I);
747 void visitVICmp(User &I);
748 void visitVFCmp(User &I);
749 // Visit the conversion instructions
750 void visitTrunc(User &I);
751 void visitZExt(User &I);
752 void visitSExt(User &I);
753 void visitFPTrunc(User &I);
754 void visitFPExt(User &I);
755 void visitFPToUI(User &I);
756 void visitFPToSI(User &I);
757 void visitUIToFP(User &I);
758 void visitSIToFP(User &I);
759 void visitPtrToInt(User &I);
760 void visitIntToPtr(User &I);
761 void visitBitCast(User &I);
763 void visitExtractElement(User &I);
764 void visitInsertElement(User &I);
765 void visitShuffleVector(User &I);
767 void visitExtractValue(ExtractValueInst &I);
768 void visitInsertValue(InsertValueInst &I);
770 void visitGetElementPtr(User &I);
771 void visitSelect(User &I);
773 void visitMalloc(MallocInst &I);
774 void visitFree(FreeInst &I);
775 void visitAlloca(AllocaInst &I);
776 void visitLoad(LoadInst &I);
777 void visitStore(StoreInst &I);
778 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
779 void visitCall(CallInst &I);
780 void visitInlineAsm(CallSite CS);
781 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
782 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
784 void visitVAStart(CallInst &I);
785 void visitVAArg(VAArgInst &I);
786 void visitVAEnd(CallInst &I);
787 void visitVACopy(CallInst &I);
789 void visitGetResult(GetResultInst &I);
791 void visitUserOp1(Instruction &I) {
792 assert(0 && "UserOp1 should not exist at instruction selection time!");
795 void visitUserOp2(Instruction &I) {
796 assert(0 && "UserOp2 should not exist at instruction selection time!");
801 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
804 } // end namespace llvm
807 /// getCopyFromParts - Create a value that contains the specified legal parts
808 /// combined into the value they represent. If the parts combine to a type
809 /// larger then ValueVT then AssertOp can be used to specify whether the extra
810 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
811 /// (ISD::AssertSext).
812 static SDOperand getCopyFromParts(SelectionDAG &DAG,
813 const SDOperand *Parts,
817 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
818 assert(NumParts > 0 && "No parts to assemble!");
819 TargetLowering &TLI = DAG.getTargetLoweringInfo();
820 SDOperand Val = Parts[0];
823 // Assemble the value from multiple parts.
824 if (!ValueVT.isVector()) {
825 unsigned PartBits = PartVT.getSizeInBits();
826 unsigned ValueBits = ValueVT.getSizeInBits();
828 // Assemble the power of 2 part.
829 unsigned RoundParts = NumParts & (NumParts - 1) ?
830 1 << Log2_32(NumParts) : NumParts;
831 unsigned RoundBits = PartBits * RoundParts;
832 MVT RoundVT = RoundBits == ValueBits ?
833 ValueVT : MVT::getIntegerVT(RoundBits);
836 if (RoundParts > 2) {
837 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
838 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
839 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
845 if (TLI.isBigEndian())
847 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
849 if (RoundParts < NumParts) {
850 // Assemble the trailing non-power-of-2 part.
851 unsigned OddParts = NumParts - RoundParts;
852 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
853 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
855 // Combine the round and odd parts.
857 if (TLI.isBigEndian())
859 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
860 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
861 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
862 DAG.getConstant(Lo.getValueType().getSizeInBits(),
863 TLI.getShiftAmountTy()));
864 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
865 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
868 // Handle a multi-element vector.
869 MVT IntermediateVT, RegisterVT;
870 unsigned NumIntermediates;
872 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
874 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
875 NumParts = NumRegs; // Silence a compiler warning.
876 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
877 assert(RegisterVT == Parts[0].getValueType() &&
878 "Part type doesn't match part!");
880 // Assemble the parts into intermediate operands.
881 SmallVector<SDOperand, 8> Ops(NumIntermediates);
882 if (NumIntermediates == NumParts) {
883 // If the register was not expanded, truncate or copy the value,
885 for (unsigned i = 0; i != NumParts; ++i)
886 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
887 PartVT, IntermediateVT);
888 } else if (NumParts > 0) {
889 // If the intermediate type was expanded, build the intermediate operands
891 assert(NumParts % NumIntermediates == 0 &&
892 "Must expand into a divisible number of parts!");
893 unsigned Factor = NumParts / NumIntermediates;
894 for (unsigned i = 0; i != NumIntermediates; ++i)
895 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
896 PartVT, IntermediateVT);
899 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
901 Val = DAG.getNode(IntermediateVT.isVector() ?
902 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
903 ValueVT, &Ops[0], NumIntermediates);
907 // There is now one part, held in Val. Correct it to match ValueVT.
908 PartVT = Val.getValueType();
910 if (PartVT == ValueVT)
913 if (PartVT.isVector()) {
914 assert(ValueVT.isVector() && "Unknown vector conversion!");
915 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
918 if (ValueVT.isVector()) {
919 assert(ValueVT.getVectorElementType() == PartVT &&
920 ValueVT.getVectorNumElements() == 1 &&
921 "Only trivial scalar-to-vector conversions should get here!");
922 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
925 if (PartVT.isInteger() &&
926 ValueVT.isInteger()) {
927 if (ValueVT.bitsLT(PartVT)) {
928 // For a truncate, see if we have any information to
929 // indicate whether the truncated bits will always be
930 // zero or sign-extension.
931 if (AssertOp != ISD::DELETED_NODE)
932 Val = DAG.getNode(AssertOp, PartVT, Val,
933 DAG.getValueType(ValueVT));
934 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
936 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
940 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
941 if (ValueVT.bitsLT(Val.getValueType()))
942 // FP_ROUND's are always exact here.
943 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
944 DAG.getIntPtrConstant(1));
945 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
948 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
949 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
951 assert(0 && "Unknown mismatch!");
955 /// getCopyToParts - Create a series of nodes that contain the specified value
956 /// split into legal parts. If the parts contain more bits than Val, then, for
957 /// integers, ExtendKind can be used to specify how to generate the extra bits.
958 static void getCopyToParts(SelectionDAG &DAG,
963 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
964 TargetLowering &TLI = DAG.getTargetLoweringInfo();
965 MVT PtrVT = TLI.getPointerTy();
966 MVT ValueVT = Val.getValueType();
967 unsigned PartBits = PartVT.getSizeInBits();
968 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
973 if (!ValueVT.isVector()) {
974 if (PartVT == ValueVT) {
975 assert(NumParts == 1 && "No-op copy with multiple parts!");
980 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
981 // If the parts cover more bits than the value has, promote the value.
982 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
983 assert(NumParts == 1 && "Do not know what to promote to!");
984 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
985 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
986 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
987 Val = DAG.getNode(ExtendKind, ValueVT, Val);
989 assert(0 && "Unknown mismatch!");
991 } else if (PartBits == ValueVT.getSizeInBits()) {
992 // Different types of the same size.
993 assert(NumParts == 1 && PartVT != ValueVT);
994 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
995 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
996 // If the parts cover less bits than value has, truncate the value.
997 if (PartVT.isInteger() && ValueVT.isInteger()) {
998 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
999 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1001 assert(0 && "Unknown mismatch!");
1005 // The value may have changed - recompute ValueVT.
1006 ValueVT = Val.getValueType();
1007 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1008 "Failed to tile the value with PartVT!");
1010 if (NumParts == 1) {
1011 assert(PartVT == ValueVT && "Type conversion failed!");
1016 // Expand the value into multiple parts.
1017 if (NumParts & (NumParts - 1)) {
1018 // The number of parts is not a power of 2. Split off and copy the tail.
1019 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1020 "Do not know what to expand to!");
1021 unsigned RoundParts = 1 << Log2_32(NumParts);
1022 unsigned RoundBits = RoundParts * PartBits;
1023 unsigned OddParts = NumParts - RoundParts;
1024 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1025 DAG.getConstant(RoundBits,
1026 TLI.getShiftAmountTy()));
1027 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1028 if (TLI.isBigEndian())
1029 // The odd parts were reversed by getCopyToParts - unreverse them.
1030 std::reverse(Parts + RoundParts, Parts + NumParts);
1031 NumParts = RoundParts;
1032 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1033 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1036 // The number of parts is a power of 2. Repeatedly bisect the value using
1038 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1039 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1041 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1042 for (unsigned i = 0; i < NumParts; i += StepSize) {
1043 unsigned ThisBits = StepSize * PartBits / 2;
1044 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1045 SDOperand &Part0 = Parts[i];
1046 SDOperand &Part1 = Parts[i+StepSize/2];
1048 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1049 DAG.getConstant(1, PtrVT));
1050 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1051 DAG.getConstant(0, PtrVT));
1053 if (ThisBits == PartBits && ThisVT != PartVT) {
1054 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1055 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1060 if (TLI.isBigEndian())
1061 std::reverse(Parts, Parts + NumParts);
1067 if (NumParts == 1) {
1068 if (PartVT != ValueVT) {
1069 if (PartVT.isVector()) {
1070 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1072 assert(ValueVT.getVectorElementType() == PartVT &&
1073 ValueVT.getVectorNumElements() == 1 &&
1074 "Only trivial vector-to-scalar conversions should get here!");
1075 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1076 DAG.getConstant(0, PtrVT));
1084 // Handle a multi-element vector.
1085 MVT IntermediateVT, RegisterVT;
1086 unsigned NumIntermediates;
1088 DAG.getTargetLoweringInfo()
1089 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1091 unsigned NumElements = ValueVT.getVectorNumElements();
1093 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1094 NumParts = NumRegs; // Silence a compiler warning.
1095 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1097 // Split the vector into intermediate operands.
1098 SmallVector<SDOperand, 8> Ops(NumIntermediates);
1099 for (unsigned i = 0; i != NumIntermediates; ++i)
1100 if (IntermediateVT.isVector())
1101 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1102 IntermediateVT, Val,
1103 DAG.getConstant(i * (NumElements / NumIntermediates),
1106 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1107 IntermediateVT, Val,
1108 DAG.getConstant(i, PtrVT));
1110 // Split the intermediate operands into legal parts.
1111 if (NumParts == NumIntermediates) {
1112 // If the register was not expanded, promote or copy the value,
1114 for (unsigned i = 0; i != NumParts; ++i)
1115 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1116 } else if (NumParts > 0) {
1117 // If the intermediate type was expanded, split each the value into
1119 assert(NumParts % NumIntermediates == 0 &&
1120 "Must expand into a divisible number of parts!");
1121 unsigned Factor = NumParts / NumIntermediates;
1122 for (unsigned i = 0; i != NumIntermediates; ++i)
1123 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1128 SDOperand SelectionDAGLowering::getValue(const Value *V) {
1129 SDOperand &N = NodeMap[V];
1130 if (N.Val) return N;
1132 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1133 MVT VT = TLI.getValueType(V->getType(), true);
1135 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1136 return N = DAG.getConstant(CI->getValue(), VT);
1138 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1139 return N = DAG.getGlobalAddress(GV, VT);
1141 if (isa<ConstantPointerNull>(C))
1142 return N = DAG.getConstant(0, TLI.getPointerTy());
1144 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1145 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1147 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1148 !V->getType()->isAggregateType())
1149 return N = DAG.getNode(ISD::UNDEF, VT);
1151 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1152 visit(CE->getOpcode(), *CE);
1153 SDOperand N1 = NodeMap[V];
1154 assert(N1.Val && "visit didn't populate the ValueMap!");
1158 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1159 SmallVector<SDOperand, 4> Constants;
1160 SmallVector<MVT, 4> ValueVTs;
1161 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1163 SDNode *Val = getValue(*OI).Val;
1164 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) {
1165 Constants.push_back(SDOperand(Val, i));
1166 ValueVTs.push_back(Val->getValueType(i));
1169 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1170 &Constants[0], Constants.size());
1173 if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) {
1174 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1175 "Unknown array constant!");
1176 unsigned NumElts = ATy->getNumElements();
1178 return SDOperand(); // empty array
1179 MVT EltVT = TLI.getValueType(ATy->getElementType());
1180 SmallVector<SDOperand, 4> Constants(NumElts);
1181 SmallVector<MVT, 4> ValueVTs(NumElts, EltVT);
1182 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1183 if (isa<UndefValue>(C))
1184 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1185 else if (EltVT.isFloatingPoint())
1186 Constants[i] = DAG.getConstantFP(0, EltVT);
1188 Constants[i] = DAG.getConstant(0, EltVT);
1190 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1191 &Constants[0], Constants.size());
1194 if (const StructType *STy = dyn_cast<StructType>(C->getType())) {
1195 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1196 "Unknown struct constant!");
1197 unsigned NumElts = STy->getNumElements();
1199 return SDOperand(); // empty struct
1200 SmallVector<SDOperand, 4> Constants(NumElts);
1201 SmallVector<MVT, 4> ValueVTs(NumElts);
1202 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1203 MVT EltVT = TLI.getValueType(STy->getElementType(i));
1204 ValueVTs[i] = EltVT;
1205 if (isa<UndefValue>(C))
1206 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1207 else if (EltVT.isFloatingPoint())
1208 Constants[i] = DAG.getConstantFP(0, EltVT);
1210 Constants[i] = DAG.getConstant(0, EltVT);
1212 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1213 &Constants[0], Constants.size());
1216 const VectorType *VecTy = cast<VectorType>(V->getType());
1217 unsigned NumElements = VecTy->getNumElements();
1219 // Now that we know the number and type of the elements, get that number of
1220 // elements into the Ops array based on what kind of constant it is.
1221 SmallVector<SDOperand, 16> Ops;
1222 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1223 for (unsigned i = 0; i != NumElements; ++i)
1224 Ops.push_back(getValue(CP->getOperand(i)));
1226 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1227 "Unknown vector constant!");
1228 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1231 if (isa<UndefValue>(C))
1232 Op = DAG.getNode(ISD::UNDEF, EltVT);
1233 else if (EltVT.isFloatingPoint())
1234 Op = DAG.getConstantFP(0, EltVT);
1236 Op = DAG.getConstant(0, EltVT);
1237 Ops.assign(NumElements, Op);
1240 // Create a BUILD_VECTOR node.
1241 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1244 // If this is a static alloca, generate it as the frameindex instead of
1246 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1247 std::map<const AllocaInst*, int>::iterator SI =
1248 FuncInfo.StaticAllocaMap.find(AI);
1249 if (SI != FuncInfo.StaticAllocaMap.end())
1250 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1253 unsigned InReg = FuncInfo.ValueMap[V];
1254 assert(InReg && "Value not in map!");
1256 RegsForValue RFV(TLI, InReg, V->getType());
1257 SDOperand Chain = DAG.getEntryNode();
1258 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1262 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1263 if (I.getNumOperands() == 0) {
1264 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1268 SmallVector<SDOperand, 8> NewValues;
1269 NewValues.push_back(getControlRoot());
1270 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1271 SDOperand RetOp = getValue(I.getOperand(i));
1273 SmallVector<MVT, 4> ValueVTs;
1274 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1275 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1276 MVT VT = ValueVTs[j];
1278 // FIXME: C calling convention requires the return type to be promoted to
1279 // at least 32-bit. But this is not necessary for non-C calling conventions.
1280 if (VT.isInteger()) {
1281 MVT MinVT = TLI.getRegisterType(MVT::i32);
1282 if (VT.bitsLT(MinVT))
1286 unsigned NumParts = TLI.getNumRegisters(VT);
1287 MVT PartVT = TLI.getRegisterType(VT);
1288 SmallVector<SDOperand, 4> Parts(NumParts);
1289 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1291 const Function *F = I.getParent()->getParent();
1292 if (F->paramHasAttr(0, ParamAttr::SExt))
1293 ExtendKind = ISD::SIGN_EXTEND;
1294 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1295 ExtendKind = ISD::ZERO_EXTEND;
1297 getCopyToParts(DAG, SDOperand(RetOp.Val, RetOp.ResNo + j),
1298 &Parts[0], NumParts, PartVT, ExtendKind);
1300 for (unsigned i = 0; i < NumParts; ++i) {
1301 NewValues.push_back(Parts[i]);
1302 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1306 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1307 &NewValues[0], NewValues.size()));
1310 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1311 /// the current basic block, add it to ValueMap now so that we'll get a
1313 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1314 // No need to export constants.
1315 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1317 // Already exported?
1318 if (FuncInfo.isExportedInst(V)) return;
1320 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1321 CopyValueToVirtualRegister(V, Reg);
1324 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1325 const BasicBlock *FromBB) {
1326 // The operands of the setcc have to be in this block. We don't know
1327 // how to export them from some other block.
1328 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1329 // Can export from current BB.
1330 if (VI->getParent() == FromBB)
1333 // Is already exported, noop.
1334 return FuncInfo.isExportedInst(V);
1337 // If this is an argument, we can export it if the BB is the entry block or
1338 // if it is already exported.
1339 if (isa<Argument>(V)) {
1340 if (FromBB == &FromBB->getParent()->getEntryBlock())
1343 // Otherwise, can only export this if it is already exported.
1344 return FuncInfo.isExportedInst(V);
1347 // Otherwise, constants can always be exported.
1351 static bool InBlock(const Value *V, const BasicBlock *BB) {
1352 if (const Instruction *I = dyn_cast<Instruction>(V))
1353 return I->getParent() == BB;
1357 /// FindMergedConditions - If Cond is an expression like
1358 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1359 MachineBasicBlock *TBB,
1360 MachineBasicBlock *FBB,
1361 MachineBasicBlock *CurBB,
1363 // If this node is not part of the or/and tree, emit it as a branch.
1364 Instruction *BOp = dyn_cast<Instruction>(Cond);
1366 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1367 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1368 BOp->getParent() != CurBB->getBasicBlock() ||
1369 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1370 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1371 const BasicBlock *BB = CurBB->getBasicBlock();
1373 // If the leaf of the tree is a comparison, merge the condition into
1375 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1376 // The operands of the cmp have to be in this block. We don't know
1377 // how to export them from some other block. If this is the first block
1378 // of the sequence, no exporting is needed.
1380 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1381 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1382 BOp = cast<Instruction>(Cond);
1383 ISD::CondCode Condition;
1384 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1385 switch (IC->getPredicate()) {
1386 default: assert(0 && "Unknown icmp predicate opcode!");
1387 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1388 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1389 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1390 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1391 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1392 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1393 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1394 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1395 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1396 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1398 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1399 ISD::CondCode FPC, FOC;
1400 switch (FC->getPredicate()) {
1401 default: assert(0 && "Unknown fcmp predicate opcode!");
1402 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1403 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1404 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1405 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1406 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1407 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1408 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1409 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1410 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1411 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1412 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1413 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1414 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1415 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1416 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1417 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1419 if (FiniteOnlyFPMath())
1424 Condition = ISD::SETEQ; // silence warning.
1425 assert(0 && "Unknown compare instruction");
1428 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1429 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1430 SwitchCases.push_back(CB);
1434 // Create a CaseBlock record representing this branch.
1435 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1436 NULL, TBB, FBB, CurBB);
1437 SwitchCases.push_back(CB);
1442 // Create TmpBB after CurBB.
1443 MachineFunction::iterator BBI = CurBB;
1444 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1445 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1447 if (Opc == Instruction::Or) {
1448 // Codegen X | Y as:
1456 // Emit the LHS condition.
1457 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1459 // Emit the RHS condition into TmpBB.
1460 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1462 assert(Opc == Instruction::And && "Unknown merge op!");
1463 // Codegen X & Y as:
1470 // This requires creation of TmpBB after CurBB.
1472 // Emit the LHS condition.
1473 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1475 // Emit the RHS condition into TmpBB.
1476 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1480 /// If the set of cases should be emitted as a series of branches, return true.
1481 /// If we should emit this as a bunch of and/or'd together conditions, return
1484 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1485 if (Cases.size() != 2) return true;
1487 // If this is two comparisons of the same values or'd or and'd together, they
1488 // will get folded into a single comparison, so don't emit two blocks.
1489 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1490 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1491 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1492 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1499 void SelectionDAGLowering::visitBr(BranchInst &I) {
1500 // Update machine-CFG edges.
1501 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1503 // Figure out which block is immediately after the current one.
1504 MachineBasicBlock *NextBlock = 0;
1505 MachineFunction::iterator BBI = CurMBB;
1506 if (++BBI != CurMBB->getParent()->end())
1509 if (I.isUnconditional()) {
1510 // Update machine-CFG edges.
1511 CurMBB->addSuccessor(Succ0MBB);
1513 // If this is not a fall-through branch, emit the branch.
1514 if (Succ0MBB != NextBlock)
1515 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1516 DAG.getBasicBlock(Succ0MBB)));
1520 // If this condition is one of the special cases we handle, do special stuff
1522 Value *CondVal = I.getCondition();
1523 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1525 // If this is a series of conditions that are or'd or and'd together, emit
1526 // this as a sequence of branches instead of setcc's with and/or operations.
1527 // For example, instead of something like:
1540 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1541 if (BOp->hasOneUse() &&
1542 (BOp->getOpcode() == Instruction::And ||
1543 BOp->getOpcode() == Instruction::Or)) {
1544 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1545 // If the compares in later blocks need to use values not currently
1546 // exported from this block, export them now. This block should always
1547 // be the first entry.
1548 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1550 // Allow some cases to be rejected.
1551 if (ShouldEmitAsBranches(SwitchCases)) {
1552 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1553 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1554 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1557 // Emit the branch for this block.
1558 visitSwitchCase(SwitchCases[0]);
1559 SwitchCases.erase(SwitchCases.begin());
1563 // Okay, we decided not to do this, remove any inserted MBB's and clear
1565 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1566 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1568 SwitchCases.clear();
1572 // Create a CaseBlock record representing this branch.
1573 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1574 NULL, Succ0MBB, Succ1MBB, CurMBB);
1575 // Use visitSwitchCase to actually insert the fast branch sequence for this
1577 visitSwitchCase(CB);
1580 /// visitSwitchCase - Emits the necessary code to represent a single node in
1581 /// the binary search tree resulting from lowering a switch instruction.
1582 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1584 SDOperand CondLHS = getValue(CB.CmpLHS);
1586 // Build the setcc now.
1587 if (CB.CmpMHS == NULL) {
1588 // Fold "(X == true)" to X and "(X == false)" to !X to
1589 // handle common cases produced by branch lowering.
1590 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1592 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1593 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1594 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1596 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1598 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1600 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1601 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1603 SDOperand CmpOp = getValue(CB.CmpMHS);
1604 MVT VT = CmpOp.getValueType();
1606 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1607 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1609 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1610 Cond = DAG.getSetCC(MVT::i1, SUB,
1611 DAG.getConstant(High-Low, VT), ISD::SETULE);
1615 // Update successor info
1616 CurMBB->addSuccessor(CB.TrueBB);
1617 CurMBB->addSuccessor(CB.FalseBB);
1619 // Set NextBlock to be the MBB immediately after the current one, if any.
1620 // This is used to avoid emitting unnecessary branches to the next block.
1621 MachineBasicBlock *NextBlock = 0;
1622 MachineFunction::iterator BBI = CurMBB;
1623 if (++BBI != CurMBB->getParent()->end())
1626 // If the lhs block is the next block, invert the condition so that we can
1627 // fall through to the lhs instead of the rhs block.
1628 if (CB.TrueBB == NextBlock) {
1629 std::swap(CB.TrueBB, CB.FalseBB);
1630 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1631 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1633 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1634 DAG.getBasicBlock(CB.TrueBB));
1635 if (CB.FalseBB == NextBlock)
1636 DAG.setRoot(BrCond);
1638 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1639 DAG.getBasicBlock(CB.FalseBB)));
1642 /// visitJumpTable - Emit JumpTable node in the current MBB
1643 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1644 // Emit the code for the jump table
1645 assert(JT.Reg != -1U && "Should lower JT Header first!");
1646 MVT PTy = TLI.getPointerTy();
1647 SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1648 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1649 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1654 /// visitJumpTableHeader - This function emits necessary code to produce index
1655 /// in the JumpTable from switch case.
1656 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1657 SelectionDAGISel::JumpTableHeader &JTH) {
1658 // Subtract the lowest switch case value from the value being switched on
1659 // and conditional branch to default mbb if the result is greater than the
1660 // difference between smallest and largest cases.
1661 SDOperand SwitchOp = getValue(JTH.SValue);
1662 MVT VT = SwitchOp.getValueType();
1663 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1664 DAG.getConstant(JTH.First, VT));
1666 // The SDNode we just created, which holds the value being switched on
1667 // minus the the smallest case value, needs to be copied to a virtual
1668 // register so it can be used as an index into the jump table in a
1669 // subsequent basic block. This value may be smaller or larger than the
1670 // target's pointer type, and therefore require extension or truncating.
1671 if (VT.bitsGT(TLI.getPointerTy()))
1672 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1674 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1676 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1677 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1678 JT.Reg = JumpTableReg;
1680 // Emit the range check for the jump table, and branch to the default
1681 // block for the switch statement if the value being switched on exceeds
1682 // the largest case in the switch.
1683 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1684 DAG.getConstant(JTH.Last-JTH.First,VT),
1687 // Set NextBlock to be the MBB immediately after the current one, if any.
1688 // This is used to avoid emitting unnecessary branches to the next block.
1689 MachineBasicBlock *NextBlock = 0;
1690 MachineFunction::iterator BBI = CurMBB;
1691 if (++BBI != CurMBB->getParent()->end())
1694 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1695 DAG.getBasicBlock(JT.Default));
1697 if (JT.MBB == NextBlock)
1698 DAG.setRoot(BrCond);
1700 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1701 DAG.getBasicBlock(JT.MBB)));
1706 /// visitBitTestHeader - This function emits necessary code to produce value
1707 /// suitable for "bit tests"
1708 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1709 // Subtract the minimum value
1710 SDOperand SwitchOp = getValue(B.SValue);
1711 MVT VT = SwitchOp.getValueType();
1712 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1713 DAG.getConstant(B.First, VT));
1716 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1717 DAG.getConstant(B.Range, VT),
1721 if (VT.bitsGT(TLI.getShiftAmountTy()))
1722 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1724 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1726 // Make desired shift
1727 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1728 DAG.getConstant(1, TLI.getPointerTy()),
1731 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1732 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1735 // Set NextBlock to be the MBB immediately after the current one, if any.
1736 // This is used to avoid emitting unnecessary branches to the next block.
1737 MachineBasicBlock *NextBlock = 0;
1738 MachineFunction::iterator BBI = CurMBB;
1739 if (++BBI != CurMBB->getParent()->end())
1742 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1744 CurMBB->addSuccessor(B.Default);
1745 CurMBB->addSuccessor(MBB);
1747 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1748 DAG.getBasicBlock(B.Default));
1750 if (MBB == NextBlock)
1751 DAG.setRoot(BrRange);
1753 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1754 DAG.getBasicBlock(MBB)));
1759 /// visitBitTestCase - this function produces one "bit test"
1760 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1762 SelectionDAGISel::BitTestCase &B) {
1763 // Emit bit tests and jumps
1764 SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1765 TLI.getPointerTy());
1767 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1768 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1769 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1770 DAG.getConstant(0, TLI.getPointerTy()),
1773 CurMBB->addSuccessor(B.TargetBB);
1774 CurMBB->addSuccessor(NextMBB);
1776 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1777 AndCmp, DAG.getBasicBlock(B.TargetBB));
1779 // Set NextBlock to be the MBB immediately after the current one, if any.
1780 // This is used to avoid emitting unnecessary branches to the next block.
1781 MachineBasicBlock *NextBlock = 0;
1782 MachineFunction::iterator BBI = CurMBB;
1783 if (++BBI != CurMBB->getParent()->end())
1786 if (NextMBB == NextBlock)
1789 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1790 DAG.getBasicBlock(NextMBB)));
1795 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1796 // Retrieve successors.
1797 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1798 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1800 if (isa<InlineAsm>(I.getCalledValue()))
1803 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1805 // If the value of the invoke is used outside of its defining block, make it
1806 // available as a virtual register.
1807 if (!I.use_empty()) {
1808 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1809 if (VMI != FuncInfo.ValueMap.end())
1810 CopyValueToVirtualRegister(&I, VMI->second);
1813 // Update successor info
1814 CurMBB->addSuccessor(Return);
1815 CurMBB->addSuccessor(LandingPad);
1817 // Drop into normal successor.
1818 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1819 DAG.getBasicBlock(Return)));
1822 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1825 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1826 /// small case ranges).
1827 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1828 CaseRecVector& WorkList,
1830 MachineBasicBlock* Default) {
1831 Case& BackCase = *(CR.Range.second-1);
1833 // Size is the number of Cases represented by this range.
1834 unsigned Size = CR.Range.second - CR.Range.first;
1838 // Get the MachineFunction which holds the current MBB. This is used when
1839 // inserting any additional MBBs necessary to represent the switch.
1840 MachineFunction *CurMF = CurMBB->getParent();
1842 // Figure out which block is immediately after the current one.
1843 MachineBasicBlock *NextBlock = 0;
1844 MachineFunction::iterator BBI = CR.CaseBB;
1846 if (++BBI != CurMBB->getParent()->end())
1849 // TODO: If any two of the cases has the same destination, and if one value
1850 // is the same as the other, but has one bit unset that the other has set,
1851 // use bit manipulation to do two compares at once. For example:
1852 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1854 // Rearrange the case blocks so that the last one falls through if possible.
1855 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1856 // The last case block won't fall through into 'NextBlock' if we emit the
1857 // branches in this order. See if rearranging a case value would help.
1858 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1859 if (I->BB == NextBlock) {
1860 std::swap(*I, BackCase);
1866 // Create a CaseBlock record representing a conditional branch to
1867 // the Case's target mbb if the value being switched on SV is equal
1869 MachineBasicBlock *CurBlock = CR.CaseBB;
1870 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1871 MachineBasicBlock *FallThrough;
1873 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1874 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1876 // If the last case doesn't match, go to the default block.
1877 FallThrough = Default;
1880 Value *RHS, *LHS, *MHS;
1882 if (I->High == I->Low) {
1883 // This is just small small case range :) containing exactly 1 case
1885 LHS = SV; RHS = I->High; MHS = NULL;
1888 LHS = I->Low; MHS = SV; RHS = I->High;
1890 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1891 I->BB, FallThrough, CurBlock);
1893 // If emitting the first comparison, just call visitSwitchCase to emit the
1894 // code into the current block. Otherwise, push the CaseBlock onto the
1895 // vector to be later processed by SDISel, and insert the node's MBB
1896 // before the next MBB.
1897 if (CurBlock == CurMBB)
1898 visitSwitchCase(CB);
1900 SwitchCases.push_back(CB);
1902 CurBlock = FallThrough;
1908 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1909 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1910 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1913 /// handleJTSwitchCase - Emit jumptable for current switch case range
1914 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1915 CaseRecVector& WorkList,
1917 MachineBasicBlock* Default) {
1918 Case& FrontCase = *CR.Range.first;
1919 Case& BackCase = *(CR.Range.second-1);
1921 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1922 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1925 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1929 if (!areJTsAllowed(TLI) || TSize <= 3)
1932 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1936 DOUT << "Lowering jump table\n"
1937 << "First entry: " << First << ". Last entry: " << Last << "\n"
1938 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1940 // Get the MachineFunction which holds the current MBB. This is used when
1941 // inserting any additional MBBs necessary to represent the switch.
1942 MachineFunction *CurMF = CurMBB->getParent();
1944 // Figure out which block is immediately after the current one.
1945 MachineBasicBlock *NextBlock = 0;
1946 MachineFunction::iterator BBI = CR.CaseBB;
1948 if (++BBI != CurMBB->getParent()->end())
1951 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1953 // Create a new basic block to hold the code for loading the address
1954 // of the jump table, and jumping to it. Update successor information;
1955 // we will either branch to the default case for the switch, or the jump
1957 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1958 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1959 CR.CaseBB->addSuccessor(Default);
1960 CR.CaseBB->addSuccessor(JumpTableBB);
1962 // Build a vector of destination BBs, corresponding to each target
1963 // of the jump table. If the value of the jump table slot corresponds to
1964 // a case statement, push the case's BB onto the vector, otherwise, push
1966 std::vector<MachineBasicBlock*> DestBBs;
1967 int64_t TEI = First;
1968 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1969 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1970 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1972 if ((Low <= TEI) && (TEI <= High)) {
1973 DestBBs.push_back(I->BB);
1977 DestBBs.push_back(Default);
1981 // Update successor info. Add one edge to each unique successor.
1982 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1983 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1984 E = DestBBs.end(); I != E; ++I) {
1985 if (!SuccsHandled[(*I)->getNumber()]) {
1986 SuccsHandled[(*I)->getNumber()] = true;
1987 JumpTableBB->addSuccessor(*I);
1991 // Create a jump table index for this jump table, or return an existing
1993 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1995 // Set the jump table information so that we can codegen it as a second
1996 // MachineBasicBlock
1997 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1998 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1999 (CR.CaseBB == CurMBB));
2000 if (CR.CaseBB == CurMBB)
2001 visitJumpTableHeader(JT, JTH);
2003 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2008 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2010 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2011 CaseRecVector& WorkList,
2013 MachineBasicBlock* Default) {
2014 // Get the MachineFunction which holds the current MBB. This is used when
2015 // inserting any additional MBBs necessary to represent the switch.
2016 MachineFunction *CurMF = CurMBB->getParent();
2018 // Figure out which block is immediately after the current one.
2019 MachineBasicBlock *NextBlock = 0;
2020 MachineFunction::iterator BBI = CR.CaseBB;
2022 if (++BBI != CurMBB->getParent()->end())
2025 Case& FrontCase = *CR.Range.first;
2026 Case& BackCase = *(CR.Range.second-1);
2027 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2029 // Size is the number of Cases represented by this range.
2030 unsigned Size = CR.Range.second - CR.Range.first;
2032 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2033 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2035 CaseItr Pivot = CR.Range.first + Size/2;
2037 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2038 // (heuristically) allow us to emit JumpTable's later.
2040 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2044 uint64_t LSize = FrontCase.size();
2045 uint64_t RSize = TSize-LSize;
2046 DOUT << "Selecting best pivot: \n"
2047 << "First: " << First << ", Last: " << Last <<"\n"
2048 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2049 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2051 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2052 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2053 assert((RBegin-LEnd>=1) && "Invalid case distance");
2054 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2055 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2056 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2057 // Should always split in some non-trivial place
2059 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2060 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2061 << "Metric: " << Metric << "\n";
2062 if (FMetric < Metric) {
2065 DOUT << "Current metric set to: " << FMetric << "\n";
2071 if (areJTsAllowed(TLI)) {
2072 // If our case is dense we *really* should handle it earlier!
2073 assert((FMetric > 0) && "Should handle dense range earlier!");
2075 Pivot = CR.Range.first + Size/2;
2078 CaseRange LHSR(CR.Range.first, Pivot);
2079 CaseRange RHSR(Pivot, CR.Range.second);
2080 Constant *C = Pivot->Low;
2081 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2083 // We know that we branch to the LHS if the Value being switched on is
2084 // less than the Pivot value, C. We use this to optimize our binary
2085 // tree a bit, by recognizing that if SV is greater than or equal to the
2086 // LHS's Case Value, and that Case Value is exactly one less than the
2087 // Pivot's Value, then we can branch directly to the LHS's Target,
2088 // rather than creating a leaf node for it.
2089 if ((LHSR.second - LHSR.first) == 1 &&
2090 LHSR.first->High == CR.GE &&
2091 cast<ConstantInt>(C)->getSExtValue() ==
2092 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2093 TrueBB = LHSR.first->BB;
2095 TrueBB = new MachineBasicBlock(LLVMBB);
2096 CurMF->getBasicBlockList().insert(BBI, TrueBB);
2097 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2100 // Similar to the optimization above, if the Value being switched on is
2101 // known to be less than the Constant CR.LT, and the current Case Value
2102 // is CR.LT - 1, then we can branch directly to the target block for
2103 // the current Case Value, rather than emitting a RHS leaf node for it.
2104 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2105 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2106 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2107 FalseBB = RHSR.first->BB;
2109 FalseBB = new MachineBasicBlock(LLVMBB);
2110 CurMF->getBasicBlockList().insert(BBI, FalseBB);
2111 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2114 // Create a CaseBlock record representing a conditional branch to
2115 // the LHS node if the value being switched on SV is less than C.
2116 // Otherwise, branch to LHS.
2117 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2118 TrueBB, FalseBB, CR.CaseBB);
2120 if (CR.CaseBB == CurMBB)
2121 visitSwitchCase(CB);
2123 SwitchCases.push_back(CB);
2128 /// handleBitTestsSwitchCase - if current case range has few destination and
2129 /// range span less, than machine word bitwidth, encode case range into series
2130 /// of masks and emit bit tests with these masks.
2131 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2132 CaseRecVector& WorkList,
2134 MachineBasicBlock* Default){
2135 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2137 Case& FrontCase = *CR.Range.first;
2138 Case& BackCase = *(CR.Range.second-1);
2140 // Get the MachineFunction which holds the current MBB. This is used when
2141 // inserting any additional MBBs necessary to represent the switch.
2142 MachineFunction *CurMF = CurMBB->getParent();
2144 unsigned numCmps = 0;
2145 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2147 // Single case counts one, case range - two.
2148 if (I->Low == I->High)
2154 // Count unique destinations
2155 SmallSet<MachineBasicBlock*, 4> Dests;
2156 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2157 Dests.insert(I->BB);
2158 if (Dests.size() > 3)
2159 // Don't bother the code below, if there are too much unique destinations
2162 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2163 << "Total number of comparisons: " << numCmps << "\n";
2165 // Compute span of values.
2166 Constant* minValue = FrontCase.Low;
2167 Constant* maxValue = BackCase.High;
2168 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2169 cast<ConstantInt>(minValue)->getSExtValue();
2170 DOUT << "Compare range: " << range << "\n"
2171 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2172 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2174 if (range>=IntPtrBits ||
2175 (!(Dests.size() == 1 && numCmps >= 3) &&
2176 !(Dests.size() == 2 && numCmps >= 5) &&
2177 !(Dests.size() >= 3 && numCmps >= 6)))
2180 DOUT << "Emitting bit tests\n";
2181 int64_t lowBound = 0;
2183 // Optimize the case where all the case values fit in a
2184 // word without having to subtract minValue. In this case,
2185 // we can optimize away the subtraction.
2186 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2187 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2188 range = cast<ConstantInt>(maxValue)->getSExtValue();
2190 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2193 CaseBitsVector CasesBits;
2194 unsigned i, count = 0;
2196 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2197 MachineBasicBlock* Dest = I->BB;
2198 for (i = 0; i < count; ++i)
2199 if (Dest == CasesBits[i].BB)
2203 assert((count < 3) && "Too much destinations to test!");
2204 CasesBits.push_back(CaseBits(0, Dest, 0));
2208 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2209 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2211 for (uint64_t j = lo; j <= hi; j++) {
2212 CasesBits[i].Mask |= 1ULL << j;
2213 CasesBits[i].Bits++;
2217 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2219 SelectionDAGISel::BitTestInfo BTC;
2221 // Figure out which block is immediately after the current one.
2222 MachineFunction::iterator BBI = CR.CaseBB;
2225 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2228 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2229 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2230 << ", BB: " << CasesBits[i].BB << "\n";
2232 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
2233 CurMF->getBasicBlockList().insert(BBI, CaseBB);
2234 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2239 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2240 -1U, (CR.CaseBB == CurMBB),
2241 CR.CaseBB, Default, BTC);
2243 if (CR.CaseBB == CurMBB)
2244 visitBitTestHeader(BTB);
2246 BitTestCases.push_back(BTB);
2252 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2253 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2254 const SwitchInst& SI) {
2255 unsigned numCmps = 0;
2257 // Start with "simple" cases
2258 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2259 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2260 Cases.push_back(Case(SI.getSuccessorValue(i),
2261 SI.getSuccessorValue(i),
2264 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2266 // Merge case into clusters
2267 if (Cases.size()>=2)
2268 // Must recompute end() each iteration because it may be
2269 // invalidated by erase if we hold on to it
2270 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2271 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2272 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2273 MachineBasicBlock* nextBB = J->BB;
2274 MachineBasicBlock* currentBB = I->BB;
2276 // If the two neighboring cases go to the same destination, merge them
2277 // into a single case.
2278 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2286 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2287 if (I->Low != I->High)
2288 // A range counts double, since it requires two compares.
2295 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2296 // Figure out which block is immediately after the current one.
2297 MachineBasicBlock *NextBlock = 0;
2298 MachineFunction::iterator BBI = CurMBB;
2300 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2302 // If there is only the default destination, branch to it if it is not the
2303 // next basic block. Otherwise, just fall through.
2304 if (SI.getNumOperands() == 2) {
2305 // Update machine-CFG edges.
2307 // If this is not a fall-through branch, emit the branch.
2308 CurMBB->addSuccessor(Default);
2309 if (Default != NextBlock)
2310 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2311 DAG.getBasicBlock(Default)));
2316 // If there are any non-default case statements, create a vector of Cases
2317 // representing each one, and sort the vector so that we can efficiently
2318 // create a binary search tree from them.
2320 unsigned numCmps = Clusterify(Cases, SI);
2321 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2322 << ". Total compares: " << numCmps << "\n";
2324 // Get the Value to be switched on and default basic blocks, which will be
2325 // inserted into CaseBlock records, representing basic blocks in the binary
2327 Value *SV = SI.getOperand(0);
2329 // Push the initial CaseRec onto the worklist
2330 CaseRecVector WorkList;
2331 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2333 while (!WorkList.empty()) {
2334 // Grab a record representing a case range to process off the worklist
2335 CaseRec CR = WorkList.back();
2336 WorkList.pop_back();
2338 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2341 // If the range has few cases (two or less) emit a series of specific
2343 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2346 // If the switch has more than 5 blocks, and at least 40% dense, and the
2347 // target supports indirect branches, then emit a jump table rather than
2348 // lowering the switch to a binary tree of conditional branches.
2349 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2352 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2353 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2354 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2359 void SelectionDAGLowering::visitSub(User &I) {
2360 // -0.0 - X --> fneg
2361 const Type *Ty = I.getType();
2362 if (isa<VectorType>(Ty)) {
2363 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2364 const VectorType *DestTy = cast<VectorType>(I.getType());
2365 const Type *ElTy = DestTy->getElementType();
2366 if (ElTy->isFloatingPoint()) {
2367 unsigned VL = DestTy->getNumElements();
2368 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2369 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2371 SDOperand Op2 = getValue(I.getOperand(1));
2372 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2378 if (Ty->isFloatingPoint()) {
2379 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2380 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2381 SDOperand Op2 = getValue(I.getOperand(1));
2382 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2387 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2390 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2391 SDOperand Op1 = getValue(I.getOperand(0));
2392 SDOperand Op2 = getValue(I.getOperand(1));
2394 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2397 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2398 SDOperand Op1 = getValue(I.getOperand(0));
2399 SDOperand Op2 = getValue(I.getOperand(1));
2401 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2402 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2403 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2404 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2406 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2409 void SelectionDAGLowering::visitICmp(User &I) {
2410 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2411 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2412 predicate = IC->getPredicate();
2413 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2414 predicate = ICmpInst::Predicate(IC->getPredicate());
2415 SDOperand Op1 = getValue(I.getOperand(0));
2416 SDOperand Op2 = getValue(I.getOperand(1));
2417 ISD::CondCode Opcode;
2418 switch (predicate) {
2419 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2420 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2421 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2422 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2423 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2424 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2425 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2426 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2427 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2428 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2430 assert(!"Invalid ICmp predicate value");
2431 Opcode = ISD::SETEQ;
2434 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2437 void SelectionDAGLowering::visitFCmp(User &I) {
2438 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2439 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2440 predicate = FC->getPredicate();
2441 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2442 predicate = FCmpInst::Predicate(FC->getPredicate());
2443 SDOperand Op1 = getValue(I.getOperand(0));
2444 SDOperand Op2 = getValue(I.getOperand(1));
2445 ISD::CondCode Condition, FOC, FPC;
2446 switch (predicate) {
2447 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2448 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2449 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2450 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2451 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2452 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2453 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2454 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2455 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2456 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2457 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2458 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2459 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2460 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2461 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2462 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2464 assert(!"Invalid FCmp predicate value");
2465 FOC = FPC = ISD::SETFALSE;
2468 if (FiniteOnlyFPMath())
2472 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2475 void SelectionDAGLowering::visitVICmp(User &I) {
2476 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2477 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2478 predicate = IC->getPredicate();
2479 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2480 predicate = ICmpInst::Predicate(IC->getPredicate());
2481 SDOperand Op1 = getValue(I.getOperand(0));
2482 SDOperand Op2 = getValue(I.getOperand(1));
2483 ISD::CondCode Opcode;
2484 switch (predicate) {
2485 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2486 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2487 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2488 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2489 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2490 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2491 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2492 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2493 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2494 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2496 assert(!"Invalid ICmp predicate value");
2497 Opcode = ISD::SETEQ;
2500 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2503 void SelectionDAGLowering::visitVFCmp(User &I) {
2504 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2505 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2506 predicate = FC->getPredicate();
2507 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2508 predicate = FCmpInst::Predicate(FC->getPredicate());
2509 SDOperand Op1 = getValue(I.getOperand(0));
2510 SDOperand Op2 = getValue(I.getOperand(1));
2511 ISD::CondCode Condition, FOC, FPC;
2512 switch (predicate) {
2513 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2514 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2515 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2516 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2517 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2518 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2519 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2520 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2521 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2522 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2523 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2524 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2525 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2526 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2527 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2528 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2530 assert(!"Invalid VFCmp predicate value");
2531 FOC = FPC = ISD::SETFALSE;
2534 if (FiniteOnlyFPMath())
2539 MVT DestVT = TLI.getValueType(I.getType());
2541 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2544 void SelectionDAGLowering::visitSelect(User &I) {
2545 SDOperand Cond = getValue(I.getOperand(0));
2546 SDOperand TrueVal = getValue(I.getOperand(1));
2547 SDOperand FalseVal = getValue(I.getOperand(2));
2548 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2549 TrueVal, FalseVal));
2553 void SelectionDAGLowering::visitTrunc(User &I) {
2554 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2555 SDOperand N = getValue(I.getOperand(0));
2556 MVT DestVT = TLI.getValueType(I.getType());
2557 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2560 void SelectionDAGLowering::visitZExt(User &I) {
2561 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2562 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2563 SDOperand N = getValue(I.getOperand(0));
2564 MVT DestVT = TLI.getValueType(I.getType());
2565 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2568 void SelectionDAGLowering::visitSExt(User &I) {
2569 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2570 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2571 SDOperand N = getValue(I.getOperand(0));
2572 MVT DestVT = TLI.getValueType(I.getType());
2573 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2576 void SelectionDAGLowering::visitFPTrunc(User &I) {
2577 // FPTrunc is never a no-op cast, no need to check
2578 SDOperand N = getValue(I.getOperand(0));
2579 MVT DestVT = TLI.getValueType(I.getType());
2580 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2583 void SelectionDAGLowering::visitFPExt(User &I){
2584 // FPTrunc is never a no-op cast, no need to check
2585 SDOperand N = getValue(I.getOperand(0));
2586 MVT DestVT = TLI.getValueType(I.getType());
2587 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2590 void SelectionDAGLowering::visitFPToUI(User &I) {
2591 // FPToUI is never a no-op cast, no need to check
2592 SDOperand N = getValue(I.getOperand(0));
2593 MVT DestVT = TLI.getValueType(I.getType());
2594 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2597 void SelectionDAGLowering::visitFPToSI(User &I) {
2598 // FPToSI is never a no-op cast, no need to check
2599 SDOperand N = getValue(I.getOperand(0));
2600 MVT DestVT = TLI.getValueType(I.getType());
2601 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2604 void SelectionDAGLowering::visitUIToFP(User &I) {
2605 // UIToFP is never a no-op cast, no need to check
2606 SDOperand N = getValue(I.getOperand(0));
2607 MVT DestVT = TLI.getValueType(I.getType());
2608 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2611 void SelectionDAGLowering::visitSIToFP(User &I){
2612 // UIToFP is never a no-op cast, no need to check
2613 SDOperand N = getValue(I.getOperand(0));
2614 MVT DestVT = TLI.getValueType(I.getType());
2615 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2618 void SelectionDAGLowering::visitPtrToInt(User &I) {
2619 // What to do depends on the size of the integer and the size of the pointer.
2620 // We can either truncate, zero extend, or no-op, accordingly.
2621 SDOperand N = getValue(I.getOperand(0));
2622 MVT SrcVT = N.getValueType();
2623 MVT DestVT = TLI.getValueType(I.getType());
2625 if (DestVT.bitsLT(SrcVT))
2626 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2628 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2629 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2630 setValue(&I, Result);
2633 void SelectionDAGLowering::visitIntToPtr(User &I) {
2634 // What to do depends on the size of the integer and the size of the pointer.
2635 // We can either truncate, zero extend, or no-op, accordingly.
2636 SDOperand N = getValue(I.getOperand(0));
2637 MVT SrcVT = N.getValueType();
2638 MVT DestVT = TLI.getValueType(I.getType());
2639 if (DestVT.bitsLT(SrcVT))
2640 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2642 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2643 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2646 void SelectionDAGLowering::visitBitCast(User &I) {
2647 SDOperand N = getValue(I.getOperand(0));
2648 MVT DestVT = TLI.getValueType(I.getType());
2650 // BitCast assures us that source and destination are the same size so this
2651 // is either a BIT_CONVERT or a no-op.
2652 if (DestVT != N.getValueType())
2653 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2655 setValue(&I, N); // noop cast.
2658 void SelectionDAGLowering::visitInsertElement(User &I) {
2659 SDOperand InVec = getValue(I.getOperand(0));
2660 SDOperand InVal = getValue(I.getOperand(1));
2661 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2662 getValue(I.getOperand(2)));
2664 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2665 TLI.getValueType(I.getType()),
2666 InVec, InVal, InIdx));
2669 void SelectionDAGLowering::visitExtractElement(User &I) {
2670 SDOperand InVec = getValue(I.getOperand(0));
2671 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2672 getValue(I.getOperand(1)));
2673 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2674 TLI.getValueType(I.getType()), InVec, InIdx));
2677 void SelectionDAGLowering::visitShuffleVector(User &I) {
2678 SDOperand V1 = getValue(I.getOperand(0));
2679 SDOperand V2 = getValue(I.getOperand(1));
2680 SDOperand Mask = getValue(I.getOperand(2));
2682 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2683 TLI.getValueType(I.getType()),
2687 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2688 const Value *Op0 = I.getOperand(0);
2689 const Value *Op1 = I.getOperand(1);
2690 const Type *AggTy = I.getType();
2691 const Type *ValTy = Op1->getType();
2692 bool IntoUndef = isa<UndefValue>(Op0);
2693 bool FromUndef = isa<UndefValue>(Op1);
2695 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2696 I.idx_begin(), I.idx_end());
2698 SmallVector<MVT, 4> AggValueVTs;
2699 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2700 SmallVector<MVT, 4> ValValueVTs;
2701 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2703 unsigned NumAggValues = AggValueVTs.size();
2704 unsigned NumValValues = ValValueVTs.size();
2705 SmallVector<SDOperand, 4> Values(NumAggValues);
2707 SDOperand Agg = getValue(Op0);
2708 SDOperand Val = getValue(Op1);
2710 // Copy the beginning value(s) from the original aggregate.
2711 for (; i != LinearIndex; ++i)
2712 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2713 SDOperand(Agg.Val, Agg.ResNo + i);
2714 // Copy values from the inserted value(s).
2715 for (; i != LinearIndex + NumValValues; ++i)
2716 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2717 SDOperand(Val.Val, Val.ResNo + i - LinearIndex);
2718 // Copy remaining value(s) from the original aggregate.
2719 for (; i != NumAggValues; ++i)
2720 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2721 SDOperand(Agg.Val, Agg.ResNo + i);
2723 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2724 &Values[0], NumAggValues));
2727 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2728 const Value *Op0 = I.getOperand(0);
2729 const Type *AggTy = Op0->getType();
2730 const Type *ValTy = I.getType();
2731 bool OutOfUndef = isa<UndefValue>(Op0);
2733 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2734 I.idx_begin(), I.idx_end());
2736 SmallVector<MVT, 4> ValValueVTs;
2737 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2739 unsigned NumValValues = ValValueVTs.size();
2740 SmallVector<SDOperand, 4> Values(NumValValues);
2742 SDOperand Agg = getValue(Op0);
2743 // Copy out the selected value(s).
2744 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2745 Values[i - LinearIndex] =
2746 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2747 SDOperand(Agg.Val, Agg.ResNo + i);
2749 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2750 &Values[0], NumValValues));
2754 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2755 SDOperand N = getValue(I.getOperand(0));
2756 const Type *Ty = I.getOperand(0)->getType();
2758 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2761 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2762 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2765 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2766 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2767 DAG.getIntPtrConstant(Offset));
2769 Ty = StTy->getElementType(Field);
2771 Ty = cast<SequentialType>(Ty)->getElementType();
2773 // If this is a constant subscript, handle it quickly.
2774 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2775 if (CI->getZExtValue() == 0) continue;
2777 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2778 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2779 DAG.getIntPtrConstant(Offs));
2783 // N = N + Idx * ElementSize;
2784 uint64_t ElementSize = TD->getABITypeSize(Ty);
2785 SDOperand IdxN = getValue(Idx);
2787 // If the index is smaller or larger than intptr_t, truncate or extend
2789 if (IdxN.getValueType().bitsLT(N.getValueType())) {
2790 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2791 } else if (IdxN.getValueType().bitsGT(N.getValueType()))
2792 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2794 // If this is a multiply by a power of two, turn it into a shl
2795 // immediately. This is a very common case.
2796 if (isPowerOf2_64(ElementSize)) {
2797 unsigned Amt = Log2_64(ElementSize);
2798 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2799 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2800 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2804 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2805 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2806 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2812 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2813 // If this is a fixed sized alloca in the entry block of the function,
2814 // allocate it statically on the stack.
2815 if (FuncInfo.StaticAllocaMap.count(&I))
2816 return; // getValue will auto-populate this.
2818 const Type *Ty = I.getAllocatedType();
2819 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2821 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2824 SDOperand AllocSize = getValue(I.getArraySize());
2825 MVT IntPtr = TLI.getPointerTy();
2826 if (IntPtr.bitsLT(AllocSize.getValueType()))
2827 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2828 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2829 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2831 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2832 DAG.getIntPtrConstant(TySize));
2834 // Handle alignment. If the requested alignment is less than or equal to
2835 // the stack alignment, ignore it. If the size is greater than or equal to
2836 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2837 unsigned StackAlign =
2838 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2839 if (Align <= StackAlign)
2842 // Round the size of the allocation up to the stack alignment size
2843 // by add SA-1 to the size.
2844 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2845 DAG.getIntPtrConstant(StackAlign-1));
2846 // Mask out the low bits for alignment purposes.
2847 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2848 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2850 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2851 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2853 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2855 DAG.setRoot(DSA.getValue(1));
2857 // Inform the Frame Information that we have just allocated a variable-sized
2859 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2862 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2863 const Value *SV = I.getOperand(0);
2864 SDOperand Ptr = getValue(SV);
2866 const Type *Ty = I.getType();
2867 bool isVolatile = I.isVolatile();
2868 unsigned Alignment = I.getAlignment();
2870 SmallVector<MVT, 4> ValueVTs;
2871 SmallVector<uint64_t, 4> Offsets;
2872 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2873 unsigned NumValues = ValueVTs.size();
2881 // Do not serialize non-volatile loads against each other.
2882 Root = DAG.getRoot();
2885 SmallVector<SDOperand, 4> Values(NumValues);
2886 SmallVector<SDOperand, 4> Chains(NumValues);
2887 MVT PtrVT = Ptr.getValueType();
2888 for (unsigned i = 0; i != NumValues; ++i) {
2889 SDOperand L = DAG.getLoad(ValueVTs[i], Root,
2890 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2891 DAG.getConstant(Offsets[i], PtrVT)),
2893 isVolatile, Alignment);
2895 Chains[i] = L.getValue(1);
2898 SDOperand Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2899 &Chains[0], NumValues);
2903 PendingLoads.push_back(Chain);
2905 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2906 &Values[0], NumValues));
2910 void SelectionDAGLowering::visitStore(StoreInst &I) {
2911 Value *SrcV = I.getOperand(0);
2912 SDOperand Src = getValue(SrcV);
2913 Value *PtrV = I.getOperand(1);
2914 SDOperand Ptr = getValue(PtrV);
2916 SmallVector<MVT, 4> ValueVTs;
2917 SmallVector<uint64_t, 4> Offsets;
2918 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2919 unsigned NumValues = ValueVTs.size();
2923 SDOperand Root = getRoot();
2924 SmallVector<SDOperand, 4> Chains(NumValues);
2925 MVT PtrVT = Ptr.getValueType();
2926 bool isVolatile = I.isVolatile();
2927 unsigned Alignment = I.getAlignment();
2928 for (unsigned i = 0; i != NumValues; ++i)
2929 Chains[i] = DAG.getStore(Root, SDOperand(Src.Val, Src.ResNo + i),
2930 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2931 DAG.getConstant(Offsets[i], PtrVT)),
2933 isVolatile, Alignment);
2935 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2938 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2940 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2941 unsigned Intrinsic) {
2942 bool HasChain = !I.doesNotAccessMemory();
2943 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2945 // Build the operand list.
2946 SmallVector<SDOperand, 8> Ops;
2947 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2949 // We don't need to serialize loads against other loads.
2950 Ops.push_back(DAG.getRoot());
2952 Ops.push_back(getRoot());
2956 // Add the intrinsic ID as an integer operand.
2957 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2959 // Add all operands of the call to the operand list.
2960 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2961 SDOperand Op = getValue(I.getOperand(i));
2962 assert(TLI.isTypeLegal(Op.getValueType()) &&
2963 "Intrinsic uses a non-legal type?");
2967 std::vector<MVT> VTs;
2968 if (I.getType() != Type::VoidTy) {
2969 MVT VT = TLI.getValueType(I.getType());
2970 if (VT.isVector()) {
2971 const VectorType *DestTy = cast<VectorType>(I.getType());
2972 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2974 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2975 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2978 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2982 VTs.push_back(MVT::Other);
2984 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2989 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2990 &Ops[0], Ops.size());
2991 else if (I.getType() != Type::VoidTy)
2992 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2993 &Ops[0], Ops.size());
2995 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2996 &Ops[0], Ops.size());
2999 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
3001 PendingLoads.push_back(Chain);
3005 if (I.getType() != Type::VoidTy) {
3006 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3007 MVT VT = TLI.getValueType(PTy);
3008 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3010 setValue(&I, Result);
3014 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3015 static GlobalVariable *ExtractTypeInfo (Value *V) {
3016 V = V->stripPointerCasts();
3017 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3018 assert ((GV || isa<ConstantPointerNull>(V)) &&
3019 "TypeInfo must be a global variable or NULL");
3023 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3024 /// call, and add them to the specified machine basic block.
3025 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3026 MachineBasicBlock *MBB) {
3027 // Inform the MachineModuleInfo of the personality for this landing pad.
3028 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3029 assert(CE->getOpcode() == Instruction::BitCast &&
3030 isa<Function>(CE->getOperand(0)) &&
3031 "Personality should be a function");
3032 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3034 // Gather all the type infos for this landing pad and pass them along to
3035 // MachineModuleInfo.
3036 std::vector<GlobalVariable *> TyInfo;
3037 unsigned N = I.getNumOperands();
3039 for (unsigned i = N - 1; i > 2; --i) {
3040 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3041 unsigned FilterLength = CI->getZExtValue();
3042 unsigned FirstCatch = i + FilterLength + !FilterLength;
3043 assert (FirstCatch <= N && "Invalid filter length");
3045 if (FirstCatch < N) {
3046 TyInfo.reserve(N - FirstCatch);
3047 for (unsigned j = FirstCatch; j < N; ++j)
3048 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3049 MMI->addCatchTypeInfo(MBB, TyInfo);
3053 if (!FilterLength) {
3055 MMI->addCleanup(MBB);
3058 TyInfo.reserve(FilterLength - 1);
3059 for (unsigned j = i + 1; j < FirstCatch; ++j)
3060 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3061 MMI->addFilterTypeInfo(MBB, TyInfo);
3070 TyInfo.reserve(N - 3);
3071 for (unsigned j = 3; j < N; ++j)
3072 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3073 MMI->addCatchTypeInfo(MBB, TyInfo);
3078 /// Inlined utility function to implement binary input atomic intrinsics for
3079 // visitIntrinsicCall: I is a call instruction
3080 // Op is the associated NodeType for I
3082 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3083 SDOperand Root = getRoot();
3084 SDOperand L = DAG.getAtomic(Op, Root,
3085 getValue(I.getOperand(1)),
3086 getValue(I.getOperand(2)),
3089 DAG.setRoot(L.getValue(1));
3093 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3094 /// we want to emit this as a call to a named external function, return the name
3095 /// otherwise lower it and return null.
3097 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3098 switch (Intrinsic) {
3100 // By default, turn this into a target intrinsic node.
3101 visitTargetIntrinsic(I, Intrinsic);
3103 case Intrinsic::vastart: visitVAStart(I); return 0;
3104 case Intrinsic::vaend: visitVAEnd(I); return 0;
3105 case Intrinsic::vacopy: visitVACopy(I); return 0;
3106 case Intrinsic::returnaddress:
3107 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3108 getValue(I.getOperand(1))));
3110 case Intrinsic::frameaddress:
3111 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3112 getValue(I.getOperand(1))));
3114 case Intrinsic::setjmp:
3115 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3117 case Intrinsic::longjmp:
3118 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3120 case Intrinsic::memcpy_i32:
3121 case Intrinsic::memcpy_i64: {
3122 SDOperand Op1 = getValue(I.getOperand(1));
3123 SDOperand Op2 = getValue(I.getOperand(2));
3124 SDOperand Op3 = getValue(I.getOperand(3));
3125 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3126 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3127 I.getOperand(1), 0, I.getOperand(2), 0));
3130 case Intrinsic::memset_i32:
3131 case Intrinsic::memset_i64: {
3132 SDOperand Op1 = getValue(I.getOperand(1));
3133 SDOperand Op2 = getValue(I.getOperand(2));
3134 SDOperand Op3 = getValue(I.getOperand(3));
3135 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3136 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3137 I.getOperand(1), 0));
3140 case Intrinsic::memmove_i32:
3141 case Intrinsic::memmove_i64: {
3142 SDOperand Op1 = getValue(I.getOperand(1));
3143 SDOperand Op2 = getValue(I.getOperand(2));
3144 SDOperand Op3 = getValue(I.getOperand(3));
3145 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3147 // If the source and destination are known to not be aliases, we can
3148 // lower memmove as memcpy.
3149 uint64_t Size = -1ULL;
3150 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3151 Size = C->getValue();
3152 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3153 AliasAnalysis::NoAlias) {
3154 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3155 I.getOperand(1), 0, I.getOperand(2), 0));
3159 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3160 I.getOperand(1), 0, I.getOperand(2), 0));
3163 case Intrinsic::dbg_stoppoint: {
3164 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3165 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3166 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3170 Ops[1] = getValue(SPI.getLineValue());
3171 Ops[2] = getValue(SPI.getColumnValue());
3173 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3174 assert(DD && "Not a debug information descriptor");
3175 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
3177 Ops[3] = DAG.getString(CompileUnit->getFileName());
3178 Ops[4] = DAG.getString(CompileUnit->getDirectory());
3180 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
3185 case Intrinsic::dbg_region_start: {
3186 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3187 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3188 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3189 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3190 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3191 DAG.getConstant(LabelID, MVT::i32),
3192 DAG.getConstant(0, MVT::i32)));
3197 case Intrinsic::dbg_region_end: {
3198 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3199 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3200 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3201 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3202 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3203 DAG.getConstant(LabelID, MVT::i32),
3204 DAG.getConstant(0, MVT::i32)));
3209 case Intrinsic::dbg_func_start: {
3210 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3212 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3213 Value *SP = FSI.getSubprogram();
3214 if (SP && MMI->Verify(SP)) {
3215 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3216 // what (most?) gdb expects.
3217 DebugInfoDesc *DD = MMI->getDescFor(SP);
3218 assert(DD && "Not a debug information descriptor");
3219 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3220 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3221 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
3222 CompileUnit->getFileName());
3223 // Record the source line but does create a label. It will be emitted
3224 // at asm emission time.
3225 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3230 case Intrinsic::dbg_declare: {
3231 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3232 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3233 Value *Variable = DI.getVariable();
3234 if (MMI && Variable && MMI->Verify(Variable))
3235 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3236 getValue(DI.getAddress()), getValue(Variable)));
3240 case Intrinsic::eh_exception: {
3241 if (!CurMBB->isLandingPad()) {
3242 // FIXME: Mark exception register as live in. Hack for PR1508.
3243 unsigned Reg = TLI.getExceptionAddressRegister();
3244 if (Reg) CurMBB->addLiveIn(Reg);
3246 // Insert the EXCEPTIONADDR instruction.
3247 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3249 Ops[0] = DAG.getRoot();
3250 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3252 DAG.setRoot(Op.getValue(1));
3256 case Intrinsic::eh_selector_i32:
3257 case Intrinsic::eh_selector_i64: {
3258 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3259 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3260 MVT::i32 : MVT::i64);
3263 if (CurMBB->isLandingPad())
3264 addCatchInfo(I, MMI, CurMBB);
3267 FuncInfo.CatchInfoLost.insert(&I);
3269 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3270 unsigned Reg = TLI.getExceptionSelectorRegister();
3271 if (Reg) CurMBB->addLiveIn(Reg);
3274 // Insert the EHSELECTION instruction.
3275 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3277 Ops[0] = getValue(I.getOperand(1));
3279 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3281 DAG.setRoot(Op.getValue(1));
3283 setValue(&I, DAG.getConstant(0, VT));
3289 case Intrinsic::eh_typeid_for_i32:
3290 case Intrinsic::eh_typeid_for_i64: {
3291 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3292 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3293 MVT::i32 : MVT::i64);
3296 // Find the type id for the given typeinfo.
3297 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3299 unsigned TypeID = MMI->getTypeIDFor(GV);
3300 setValue(&I, DAG.getConstant(TypeID, VT));
3302 // Return something different to eh_selector.
3303 setValue(&I, DAG.getConstant(1, VT));
3309 case Intrinsic::eh_return: {
3310 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3313 MMI->setCallsEHReturn(true);
3314 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3317 getValue(I.getOperand(1)),
3318 getValue(I.getOperand(2))));
3320 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3326 case Intrinsic::eh_unwind_init: {
3327 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3328 MMI->setCallsUnwindInit(true);
3334 case Intrinsic::eh_dwarf_cfa: {
3335 MVT VT = getValue(I.getOperand(1)).getValueType();
3337 if (VT.bitsGT(TLI.getPointerTy()))
3338 CfaArg = DAG.getNode(ISD::TRUNCATE,
3339 TLI.getPointerTy(), getValue(I.getOperand(1)));
3341 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3342 TLI.getPointerTy(), getValue(I.getOperand(1)));
3344 SDOperand Offset = DAG.getNode(ISD::ADD,
3346 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3347 TLI.getPointerTy()),
3349 setValue(&I, DAG.getNode(ISD::ADD,
3351 DAG.getNode(ISD::FRAMEADDR,
3354 TLI.getPointerTy())),
3359 case Intrinsic::sqrt:
3360 setValue(&I, DAG.getNode(ISD::FSQRT,
3361 getValue(I.getOperand(1)).getValueType(),
3362 getValue(I.getOperand(1))));
3364 case Intrinsic::powi:
3365 setValue(&I, DAG.getNode(ISD::FPOWI,
3366 getValue(I.getOperand(1)).getValueType(),
3367 getValue(I.getOperand(1)),
3368 getValue(I.getOperand(2))));
3370 case Intrinsic::sin:
3371 setValue(&I, DAG.getNode(ISD::FSIN,
3372 getValue(I.getOperand(1)).getValueType(),
3373 getValue(I.getOperand(1))));
3375 case Intrinsic::cos:
3376 setValue(&I, DAG.getNode(ISD::FCOS,
3377 getValue(I.getOperand(1)).getValueType(),
3378 getValue(I.getOperand(1))));
3380 case Intrinsic::pow:
3381 setValue(&I, DAG.getNode(ISD::FPOW,
3382 getValue(I.getOperand(1)).getValueType(),
3383 getValue(I.getOperand(1)),
3384 getValue(I.getOperand(2))));
3386 case Intrinsic::pcmarker: {
3387 SDOperand Tmp = getValue(I.getOperand(1));
3388 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3391 case Intrinsic::readcyclecounter: {
3392 SDOperand Op = getRoot();
3393 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3394 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3397 DAG.setRoot(Tmp.getValue(1));
3400 case Intrinsic::part_select: {
3401 // Currently not implemented: just abort
3402 assert(0 && "part_select intrinsic not implemented");
3405 case Intrinsic::part_set: {
3406 // Currently not implemented: just abort
3407 assert(0 && "part_set intrinsic not implemented");
3410 case Intrinsic::bswap:
3411 setValue(&I, DAG.getNode(ISD::BSWAP,
3412 getValue(I.getOperand(1)).getValueType(),
3413 getValue(I.getOperand(1))));
3415 case Intrinsic::cttz: {
3416 SDOperand Arg = getValue(I.getOperand(1));
3417 MVT Ty = Arg.getValueType();
3418 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3419 setValue(&I, result);
3422 case Intrinsic::ctlz: {
3423 SDOperand Arg = getValue(I.getOperand(1));
3424 MVT Ty = Arg.getValueType();
3425 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3426 setValue(&I, result);
3429 case Intrinsic::ctpop: {
3430 SDOperand Arg = getValue(I.getOperand(1));
3431 MVT Ty = Arg.getValueType();
3432 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3433 setValue(&I, result);
3436 case Intrinsic::stacksave: {
3437 SDOperand Op = getRoot();
3438 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
3439 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3441 DAG.setRoot(Tmp.getValue(1));
3444 case Intrinsic::stackrestore: {
3445 SDOperand Tmp = getValue(I.getOperand(1));
3446 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3449 case Intrinsic::var_annotation:
3450 // Discard annotate attributes
3453 case Intrinsic::init_trampoline: {
3454 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3458 Ops[1] = getValue(I.getOperand(1));
3459 Ops[2] = getValue(I.getOperand(2));
3460 Ops[3] = getValue(I.getOperand(3));
3461 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3462 Ops[5] = DAG.getSrcValue(F);
3464 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3465 DAG.getNodeValueTypes(TLI.getPointerTy(),
3470 DAG.setRoot(Tmp.getValue(1));
3474 case Intrinsic::gcroot:
3476 Value *Alloca = I.getOperand(1);
3477 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3479 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3480 GCI->addStackRoot(FI->getIndex(), TypeMap);
3484 case Intrinsic::gcread:
3485 case Intrinsic::gcwrite:
3486 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3489 case Intrinsic::flt_rounds: {
3490 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3494 case Intrinsic::trap: {
3495 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3498 case Intrinsic::prefetch: {
3501 Ops[1] = getValue(I.getOperand(1));
3502 Ops[2] = getValue(I.getOperand(2));
3503 Ops[3] = getValue(I.getOperand(3));
3504 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3508 case Intrinsic::memory_barrier: {
3511 for (int x = 1; x < 6; ++x)
3512 Ops[x] = getValue(I.getOperand(x));
3514 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3517 case Intrinsic::atomic_cmp_swap: {
3518 SDOperand Root = getRoot();
3519 SDOperand L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
3520 getValue(I.getOperand(1)),
3521 getValue(I.getOperand(2)),
3522 getValue(I.getOperand(3)),
3525 DAG.setRoot(L.getValue(1));
3528 case Intrinsic::atomic_load_add:
3529 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3530 case Intrinsic::atomic_load_sub:
3531 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
3532 case Intrinsic::atomic_load_and:
3533 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3534 case Intrinsic::atomic_load_or:
3535 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3536 case Intrinsic::atomic_load_xor:
3537 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3538 case Intrinsic::atomic_load_nand:
3539 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3540 case Intrinsic::atomic_load_min:
3541 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3542 case Intrinsic::atomic_load_max:
3543 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3544 case Intrinsic::atomic_load_umin:
3545 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3546 case Intrinsic::atomic_load_umax:
3547 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3548 case Intrinsic::atomic_swap:
3549 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3554 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3556 MachineBasicBlock *LandingPad) {
3557 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3558 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3559 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3560 unsigned BeginLabel = 0, EndLabel = 0;
3562 TargetLowering::ArgListTy Args;
3563 TargetLowering::ArgListEntry Entry;
3564 Args.reserve(CS.arg_size());
3565 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3567 SDOperand ArgNode = getValue(*i);
3568 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3570 unsigned attrInd = i - CS.arg_begin() + 1;
3571 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3572 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3573 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3574 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3575 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3576 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3577 Entry.Alignment = CS.getParamAlignment(attrInd);
3578 Args.push_back(Entry);
3581 if (LandingPad && MMI) {
3582 // Insert a label before the invoke call to mark the try range. This can be
3583 // used to detect deletion of the invoke via the MachineModuleInfo.
3584 BeginLabel = MMI->NextLabelID();
3585 // Both PendingLoads and PendingExports must be flushed here;
3586 // this call might not return.
3588 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getControlRoot(),
3589 DAG.getConstant(BeginLabel, MVT::i32),
3590 DAG.getConstant(1, MVT::i32)));
3593 std::pair<SDOperand,SDOperand> Result =
3594 TLI.LowerCallTo(getRoot(), CS.getType(),
3595 CS.paramHasAttr(0, ParamAttr::SExt),
3596 CS.paramHasAttr(0, ParamAttr::ZExt),
3597 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3599 if (CS.getType() != Type::VoidTy)
3600 setValue(CS.getInstruction(), Result.first);
3601 DAG.setRoot(Result.second);
3603 if (LandingPad && MMI) {
3604 // Insert a label at the end of the invoke call to mark the try range. This
3605 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3606 EndLabel = MMI->NextLabelID();
3607 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3608 DAG.getConstant(EndLabel, MVT::i32),
3609 DAG.getConstant(1, MVT::i32)));
3611 // Inform MachineModuleInfo of range.
3612 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3617 void SelectionDAGLowering::visitCall(CallInst &I) {
3618 const char *RenameFn = 0;
3619 if (Function *F = I.getCalledFunction()) {
3620 if (F->isDeclaration()) {
3621 if (unsigned IID = F->getIntrinsicID()) {
3622 RenameFn = visitIntrinsicCall(I, IID);
3628 // Check for well-known libc/libm calls. If the function is internal, it
3629 // can't be a library call.
3630 unsigned NameLen = F->getNameLen();
3631 if (!F->hasInternalLinkage() && NameLen) {
3632 const char *NameStr = F->getNameStart();
3633 if (NameStr[0] == 'c' &&
3634 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3635 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3636 if (I.getNumOperands() == 3 && // Basic sanity checks.
3637 I.getOperand(1)->getType()->isFloatingPoint() &&
3638 I.getType() == I.getOperand(1)->getType() &&
3639 I.getType() == I.getOperand(2)->getType()) {
3640 SDOperand LHS = getValue(I.getOperand(1));
3641 SDOperand RHS = getValue(I.getOperand(2));
3642 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3646 } else if (NameStr[0] == 'f' &&
3647 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3648 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3649 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3650 if (I.getNumOperands() == 2 && // Basic sanity checks.
3651 I.getOperand(1)->getType()->isFloatingPoint() &&
3652 I.getType() == I.getOperand(1)->getType()) {
3653 SDOperand Tmp = getValue(I.getOperand(1));
3654 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3657 } else if (NameStr[0] == 's' &&
3658 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3659 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3660 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3661 if (I.getNumOperands() == 2 && // Basic sanity checks.
3662 I.getOperand(1)->getType()->isFloatingPoint() &&
3663 I.getType() == I.getOperand(1)->getType()) {
3664 SDOperand Tmp = getValue(I.getOperand(1));
3665 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3668 } else if (NameStr[0] == 'c' &&
3669 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3670 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3671 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3672 if (I.getNumOperands() == 2 && // Basic sanity checks.
3673 I.getOperand(1)->getType()->isFloatingPoint() &&
3674 I.getType() == I.getOperand(1)->getType()) {
3675 SDOperand Tmp = getValue(I.getOperand(1));
3676 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3681 } else if (isa<InlineAsm>(I.getOperand(0))) {
3688 Callee = getValue(I.getOperand(0));
3690 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3692 LowerCallTo(&I, Callee, I.isTailCall());
3696 void SelectionDAGLowering::visitGetResult(GetResultInst &I) {
3697 if (isa<UndefValue>(I.getOperand(0))) {
3698 SDOperand Undef = DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType()));
3699 setValue(&I, Undef);
3703 // To add support for individual return values with aggregate types,
3704 // we'd need a way to take a getresult index and determine which
3705 // values of the Call SDNode are associated with it.
3706 assert(TLI.getValueType(I.getType(), true) != MVT::Other &&
3707 "Individual return values must not be aggregates!");
3709 SDOperand Call = getValue(I.getOperand(0));
3710 setValue(&I, SDOperand(Call.Val, I.getIndex()));
3714 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3715 /// this value and returns the result as a ValueVT value. This uses
3716 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3717 /// If the Flag pointer is NULL, no flag is used.
3718 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3720 SDOperand *Flag) const {
3721 // Assemble the legal parts into the final values.
3722 SmallVector<SDOperand, 4> Values(ValueVTs.size());
3723 SmallVector<SDOperand, 8> Parts;
3724 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3725 // Copy the legal parts from the registers.
3726 MVT ValueVT = ValueVTs[Value];
3727 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3728 MVT RegisterVT = RegVTs[Value];
3730 Parts.resize(NumRegs);
3731 for (unsigned i = 0; i != NumRegs; ++i) {
3734 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3736 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3737 *Flag = P.getValue(2);
3739 Chain = P.getValue(1);
3741 // If the source register was virtual and if we know something about it,
3742 // add an assert node.
3743 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3744 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3745 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3746 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3747 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3748 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3750 unsigned RegSize = RegisterVT.getSizeInBits();
3751 unsigned NumSignBits = LOI.NumSignBits;
3752 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3754 // FIXME: We capture more information than the dag can represent. For
3755 // now, just use the tightest assertzext/assertsext possible.
3757 MVT FromVT(MVT::Other);
3758 if (NumSignBits == RegSize)
3759 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3760 else if (NumZeroBits >= RegSize-1)
3761 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3762 else if (NumSignBits > RegSize-8)
3763 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3764 else if (NumZeroBits >= RegSize-9)
3765 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3766 else if (NumSignBits > RegSize-16)
3767 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3768 else if (NumZeroBits >= RegSize-17)
3769 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3770 else if (NumSignBits > RegSize-32)
3771 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3772 else if (NumZeroBits >= RegSize-33)
3773 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3775 if (FromVT != MVT::Other) {
3776 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3777 RegisterVT, P, DAG.getValueType(FromVT));
3786 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3791 if (ValueVTs.size() == 1)
3794 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3795 &Values[0], ValueVTs.size());
3798 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3799 /// specified value into the registers specified by this object. This uses
3800 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3801 /// If the Flag pointer is NULL, no flag is used.
3802 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3803 SDOperand &Chain, SDOperand *Flag) const {
3804 // Get the list of the values's legal parts.
3805 unsigned NumRegs = Regs.size();
3806 SmallVector<SDOperand, 8> Parts(NumRegs);
3807 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3808 MVT ValueVT = ValueVTs[Value];
3809 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3810 MVT RegisterVT = RegVTs[Value];
3812 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3813 &Parts[Part], NumParts, RegisterVT);
3817 // Copy the parts into the registers.
3818 SmallVector<SDOperand, 8> Chains(NumRegs);
3819 for (unsigned i = 0; i != NumRegs; ++i) {
3822 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3824 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3825 *Flag = Part.getValue(1);
3827 Chains[i] = Part.getValue(0);
3830 if (NumRegs == 1 || Flag)
3831 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3832 // flagged to it. That is the CopyToReg nodes and the user are considered
3833 // a single scheduling unit. If we create a TokenFactor and return it as
3834 // chain, then the TokenFactor is both a predecessor (operand) of the
3835 // user as well as a successor (the TF operands are flagged to the user).
3836 // c1, f1 = CopyToReg
3837 // c2, f2 = CopyToReg
3838 // c3 = TokenFactor c1, c2
3841 Chain = Chains[NumRegs-1];
3843 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3846 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3847 /// operand list. This adds the code marker and includes the number of
3848 /// values added into it.
3849 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3850 std::vector<SDOperand> &Ops) const {
3851 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3852 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3853 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3854 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3855 MVT RegisterVT = RegVTs[Value];
3856 for (unsigned i = 0; i != NumRegs; ++i)
3857 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3861 /// isAllocatableRegister - If the specified register is safe to allocate,
3862 /// i.e. it isn't a stack pointer or some other special register, return the
3863 /// register class for the register. Otherwise, return null.
3864 static const TargetRegisterClass *
3865 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3866 const TargetLowering &TLI,
3867 const TargetRegisterInfo *TRI) {
3868 MVT FoundVT = MVT::Other;
3869 const TargetRegisterClass *FoundRC = 0;
3870 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3871 E = TRI->regclass_end(); RCI != E; ++RCI) {
3872 MVT ThisVT = MVT::Other;
3874 const TargetRegisterClass *RC = *RCI;
3875 // If none of the the value types for this register class are valid, we
3876 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3877 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3879 if (TLI.isTypeLegal(*I)) {
3880 // If we have already found this register in a different register class,
3881 // choose the one with the largest VT specified. For example, on
3882 // PowerPC, we favor f64 register classes over f32.
3883 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3890 if (ThisVT == MVT::Other) continue;
3892 // NOTE: This isn't ideal. In particular, this might allocate the
3893 // frame pointer in functions that need it (due to them not being taken
3894 // out of allocation, because a variable sized allocation hasn't been seen
3895 // yet). This is a slight code pessimization, but should still work.
3896 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3897 E = RC->allocation_order_end(MF); I != E; ++I)
3899 // We found a matching register class. Keep looking at others in case
3900 // we find one with larger registers that this physreg is also in.
3911 /// AsmOperandInfo - This contains information for each constraint that we are
3913 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3914 /// CallOperand - If this is the result output operand or a clobber
3915 /// this is null, otherwise it is the incoming operand to the CallInst.
3916 /// This gets modified as the asm is processed.
3917 SDOperand CallOperand;
3919 /// AssignedRegs - If this is a register or register class operand, this
3920 /// contains the set of register corresponding to the operand.
3921 RegsForValue AssignedRegs;
3923 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3924 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3927 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3928 /// busy in OutputRegs/InputRegs.
3929 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3930 std::set<unsigned> &OutputRegs,
3931 std::set<unsigned> &InputRegs,
3932 const TargetRegisterInfo &TRI) const {
3934 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3935 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3938 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3939 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3944 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3946 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3947 const TargetRegisterInfo &TRI) {
3948 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3950 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3951 for (; *Aliases; ++Aliases)
3952 Regs.insert(*Aliases);
3955 } // end anon namespace.
3958 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3959 /// specified operand. We prefer to assign virtual registers, to allow the
3960 /// register allocator handle the assignment process. However, if the asm uses
3961 /// features that we can't model on machineinstrs, we have SDISel do the
3962 /// allocation. This produces generally horrible, but correct, code.
3964 /// OpInfo describes the operand.
3965 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3966 /// or any explicitly clobbered registers.
3967 /// Input and OutputRegs are the set of already allocated physical registers.
3969 void SelectionDAGLowering::
3970 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3971 std::set<unsigned> &OutputRegs,
3972 std::set<unsigned> &InputRegs) {
3973 // Compute whether this value requires an input register, an output register,
3975 bool isOutReg = false;
3976 bool isInReg = false;
3977 switch (OpInfo.Type) {
3978 case InlineAsm::isOutput:
3981 // If this is an early-clobber output, or if there is an input
3982 // constraint that matches this, we need to reserve the input register
3983 // so no other inputs allocate to it.
3984 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3986 case InlineAsm::isInput:
3990 case InlineAsm::isClobber:
3997 MachineFunction &MF = DAG.getMachineFunction();
3998 SmallVector<unsigned, 4> Regs;
4000 // If this is a constraint for a single physreg, or a constraint for a
4001 // register class, find it.
4002 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4003 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4004 OpInfo.ConstraintVT);
4006 unsigned NumRegs = 1;
4007 if (OpInfo.ConstraintVT != MVT::Other)
4008 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4010 MVT ValueVT = OpInfo.ConstraintVT;
4013 // If this is a constraint for a specific physical register, like {r17},
4015 if (PhysReg.first) {
4016 if (OpInfo.ConstraintVT == MVT::Other)
4017 ValueVT = *PhysReg.second->vt_begin();
4019 // Get the actual register value type. This is important, because the user
4020 // may have asked for (e.g.) the AX register in i32 type. We need to
4021 // remember that AX is actually i16 to get the right extension.
4022 RegVT = *PhysReg.second->vt_begin();
4024 // This is a explicit reference to a physical register.
4025 Regs.push_back(PhysReg.first);
4027 // If this is an expanded reference, add the rest of the regs to Regs.
4029 TargetRegisterClass::iterator I = PhysReg.second->begin();
4030 for (; *I != PhysReg.first; ++I)
4031 assert(I != PhysReg.second->end() && "Didn't find reg!");
4033 // Already added the first reg.
4035 for (; NumRegs; --NumRegs, ++I) {
4036 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4040 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4041 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4042 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4046 // Otherwise, if this was a reference to an LLVM register class, create vregs
4047 // for this reference.
4048 std::vector<unsigned> RegClassRegs;
4049 const TargetRegisterClass *RC = PhysReg.second;
4051 // If this is an early clobber or tied register, our regalloc doesn't know
4052 // how to maintain the constraint. If it isn't, go ahead and create vreg
4053 // and let the regalloc do the right thing.
4054 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4055 // If there is some other early clobber and this is an input register,
4056 // then we are forced to pre-allocate the input reg so it doesn't
4057 // conflict with the earlyclobber.
4058 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4059 RegVT = *PhysReg.second->vt_begin();
4061 if (OpInfo.ConstraintVT == MVT::Other)
4064 // Create the appropriate number of virtual registers.
4065 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4066 for (; NumRegs; --NumRegs)
4067 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4069 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4073 // Otherwise, we can't allocate it. Let the code below figure out how to
4074 // maintain these constraints.
4075 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4078 // This is a reference to a register class that doesn't directly correspond
4079 // to an LLVM register class. Allocate NumRegs consecutive, available,
4080 // registers from the class.
4081 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4082 OpInfo.ConstraintVT);
4085 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4086 unsigned NumAllocated = 0;
4087 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4088 unsigned Reg = RegClassRegs[i];
4089 // See if this register is available.
4090 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4091 (isInReg && InputRegs.count(Reg))) { // Already used.
4092 // Make sure we find consecutive registers.
4097 // Check to see if this register is allocatable (i.e. don't give out the
4100 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4101 if (!RC) { // Couldn't allocate this register.
4102 // Reset NumAllocated to make sure we return consecutive registers.
4108 // Okay, this register is good, we can use it.
4111 // If we allocated enough consecutive registers, succeed.
4112 if (NumAllocated == NumRegs) {
4113 unsigned RegStart = (i-NumAllocated)+1;
4114 unsigned RegEnd = i+1;
4115 // Mark all of the allocated registers used.
4116 for (unsigned i = RegStart; i != RegEnd; ++i)
4117 Regs.push_back(RegClassRegs[i]);
4119 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4120 OpInfo.ConstraintVT);
4121 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4126 // Otherwise, we couldn't allocate enough registers for this.
4130 /// visitInlineAsm - Handle a call to an InlineAsm object.
4132 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4133 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4135 /// ConstraintOperands - Information about all of the constraints.
4136 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4138 SDOperand Chain = getRoot();
4141 std::set<unsigned> OutputRegs, InputRegs;
4143 // Do a prepass over the constraints, canonicalizing them, and building up the
4144 // ConstraintOperands list.
4145 std::vector<InlineAsm::ConstraintInfo>
4146 ConstraintInfos = IA->ParseConstraints();
4148 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4149 // constraint. If so, we can't let the register allocator allocate any input
4150 // registers, because it will not know to avoid the earlyclobbered output reg.
4151 bool SawEarlyClobber = false;
4153 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4154 unsigned ResNo = 0; // ResNo - The result number of the next output.
4155 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4156 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4157 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4159 MVT OpVT = MVT::Other;
4161 // Compute the value type for each operand.
4162 switch (OpInfo.Type) {
4163 case InlineAsm::isOutput:
4164 // Indirect outputs just consume an argument.
4165 if (OpInfo.isIndirect) {
4166 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4169 // The return value of the call is this value. As such, there is no
4170 // corresponding argument.
4171 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4172 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4173 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4175 assert(ResNo == 0 && "Asm only has one result!");
4176 OpVT = TLI.getValueType(CS.getType());
4180 case InlineAsm::isInput:
4181 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4183 case InlineAsm::isClobber:
4188 // If this is an input or an indirect output, process the call argument.
4189 // BasicBlocks are labels, currently appearing only in asm's.
4190 if (OpInfo.CallOperandVal) {
4191 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4192 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4194 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4195 const Type *OpTy = OpInfo.CallOperandVal->getType();
4196 // If this is an indirect operand, the operand is a pointer to the
4198 if (OpInfo.isIndirect)
4199 OpTy = cast<PointerType>(OpTy)->getElementType();
4201 // If OpTy is not a single value, it may be a struct/union that we
4202 // can tile with integers.
4203 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4204 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4212 OpTy = IntegerType::get(BitSize);
4217 OpVT = TLI.getValueType(OpTy, true);
4221 OpInfo.ConstraintVT = OpVT;
4223 // Compute the constraint code and ConstraintType to use.
4224 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4226 // Keep track of whether we see an earlyclobber.
4227 SawEarlyClobber |= OpInfo.isEarlyClobber;
4229 // If we see a clobber of a register, it is an early clobber.
4230 if (!SawEarlyClobber &&
4231 OpInfo.Type == InlineAsm::isClobber &&
4232 OpInfo.ConstraintType == TargetLowering::C_Register) {
4233 // Note that we want to ignore things that we don't trick here, like
4234 // dirflag, fpsr, flags, etc.
4235 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4236 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4237 OpInfo.ConstraintVT);
4238 if (PhysReg.first || PhysReg.second) {
4239 // This is a register we know of.
4240 SawEarlyClobber = true;
4244 // If this is a memory input, and if the operand is not indirect, do what we
4245 // need to to provide an address for the memory input.
4246 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4247 !OpInfo.isIndirect) {
4248 assert(OpInfo.Type == InlineAsm::isInput &&
4249 "Can only indirectify direct input operands!");
4251 // Memory operands really want the address of the value. If we don't have
4252 // an indirect input, put it in the constpool if we can, otherwise spill
4253 // it to a stack slot.
4255 // If the operand is a float, integer, or vector constant, spill to a
4256 // constant pool entry to get its address.
4257 Value *OpVal = OpInfo.CallOperandVal;
4258 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4259 isa<ConstantVector>(OpVal)) {
4260 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4261 TLI.getPointerTy());
4263 // Otherwise, create a stack slot and emit a store to it before the
4265 const Type *Ty = OpVal->getType();
4266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4267 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4268 MachineFunction &MF = DAG.getMachineFunction();
4269 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4270 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4271 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4272 OpInfo.CallOperand = StackSlot;
4275 // There is no longer a Value* corresponding to this operand.
4276 OpInfo.CallOperandVal = 0;
4277 // It is now an indirect operand.
4278 OpInfo.isIndirect = true;
4281 // If this constraint is for a specific register, allocate it before
4283 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4284 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4286 ConstraintInfos.clear();
4289 // Second pass - Loop over all of the operands, assigning virtual or physregs
4290 // to registerclass operands.
4291 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4292 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4294 // C_Register operands have already been allocated, Other/Memory don't need
4296 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4297 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4300 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4301 std::vector<SDOperand> AsmNodeOperands;
4302 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
4303 AsmNodeOperands.push_back(
4304 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4307 // Loop over all of the inputs, copying the operand values into the
4308 // appropriate registers and processing the output regs.
4309 RegsForValue RetValRegs;
4311 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4312 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4314 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4315 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4317 switch (OpInfo.Type) {
4318 case InlineAsm::isOutput: {
4319 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4320 OpInfo.ConstraintType != TargetLowering::C_Register) {
4321 // Memory output, or 'other' output (e.g. 'X' constraint).
4322 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4324 // Add information to the INLINEASM node to know about this output.
4325 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4326 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4327 TLI.getPointerTy()));
4328 AsmNodeOperands.push_back(OpInfo.CallOperand);
4332 // Otherwise, this is a register or register class output.
4334 // Copy the output from the appropriate register. Find a register that
4336 if (OpInfo.AssignedRegs.Regs.empty()) {
4337 cerr << "Couldn't allocate output reg for constraint '"
4338 << OpInfo.ConstraintCode << "'!\n";
4342 // If this is an indirect operand, store through the pointer after the
4344 if (OpInfo.isIndirect) {
4345 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4346 OpInfo.CallOperandVal));
4348 // This is the result value of the call.
4349 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4350 // Concatenate this output onto the outputs list.
4351 RetValRegs.append(OpInfo.AssignedRegs);
4354 // Add information to the INLINEASM node to know that this register is
4356 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4360 case InlineAsm::isInput: {
4361 SDOperand InOperandVal = OpInfo.CallOperand;
4363 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4364 // If this is required to match an output register we have already set,
4365 // just use its register.
4366 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4368 // Scan until we find the definition we already emitted of this operand.
4369 // When we find it, create a RegsForValue operand.
4370 unsigned CurOp = 2; // The first operand.
4371 for (; OperandNo; --OperandNo) {
4372 // Advance to the next operand.
4374 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4375 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4376 (NumOps & 7) == 4 /*MEM*/) &&
4377 "Skipped past definitions?");
4378 CurOp += (NumOps>>3)+1;
4382 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4383 if ((NumOps & 7) == 2 /*REGDEF*/) {
4384 // Add NumOps>>3 registers to MatchedRegs.
4385 RegsForValue MatchedRegs;
4386 MatchedRegs.TLI = &TLI;
4387 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4388 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4389 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4391 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4392 MatchedRegs.Regs.push_back(Reg);
4395 // Use the produced MatchedRegs object to
4396 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4397 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4400 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4401 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4402 // Add information to the INLINEASM node to know about this input.
4403 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4404 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4405 TLI.getPointerTy()));
4406 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4411 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4412 assert(!OpInfo.isIndirect &&
4413 "Don't know how to handle indirect other inputs yet!");
4415 std::vector<SDOperand> Ops;
4416 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4419 cerr << "Invalid operand for inline asm constraint '"
4420 << OpInfo.ConstraintCode << "'!\n";
4424 // Add information to the INLINEASM node to know about this input.
4425 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4426 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4427 TLI.getPointerTy()));
4428 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4430 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4431 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4432 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4433 "Memory operands expect pointer values");
4435 // Add information to the INLINEASM node to know about this input.
4436 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4437 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4438 TLI.getPointerTy()));
4439 AsmNodeOperands.push_back(InOperandVal);
4443 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4444 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4445 "Unknown constraint type!");
4446 assert(!OpInfo.isIndirect &&
4447 "Don't know how to handle indirect register inputs yet!");
4449 // Copy the input into the appropriate registers.
4450 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4451 "Couldn't allocate input reg!");
4453 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4455 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4459 case InlineAsm::isClobber: {
4460 // Add the clobbered value to the operand list, so that the register
4461 // allocator is aware that the physreg got clobbered.
4462 if (!OpInfo.AssignedRegs.Regs.empty())
4463 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4470 // Finish up input operands.
4471 AsmNodeOperands[0] = Chain;
4472 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4474 Chain = DAG.getNode(ISD::INLINEASM,
4475 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4476 &AsmNodeOperands[0], AsmNodeOperands.size());
4477 Flag = Chain.getValue(1);
4479 // If this asm returns a register value, copy the result from that register
4480 // and set it as the value of the call.
4481 if (!RetValRegs.Regs.empty()) {
4482 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4484 // If any of the results of the inline asm is a vector, it may have the
4485 // wrong width/num elts. This can happen for register classes that can
4486 // contain multiple different value types. The preg or vreg allocated may
4487 // not have the same VT as was expected. Convert it to the right type with
4489 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4490 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4491 if (Val.Val->getValueType(i).isVector())
4492 Val = DAG.getNode(ISD::BIT_CONVERT,
4493 TLI.getValueType(ResSTy->getElementType(i)), Val);
4496 if (Val.getValueType().isVector())
4497 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4501 setValue(CS.getInstruction(), Val);
4504 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
4506 // Process indirect outputs, first output all of the flagged copies out of
4508 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4509 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4510 Value *Ptr = IndirectStoresToEmit[i].second;
4511 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4512 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4515 // Emit the non-flagged stores from the physregs.
4516 SmallVector<SDOperand, 8> OutChains;
4517 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4518 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4519 getValue(StoresToEmit[i].second),
4520 StoresToEmit[i].second, 0));
4521 if (!OutChains.empty())
4522 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4523 &OutChains[0], OutChains.size());
4528 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4529 SDOperand Src = getValue(I.getOperand(0));
4531 MVT IntPtr = TLI.getPointerTy();
4533 if (IntPtr.bitsLT(Src.getValueType()))
4534 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4535 else if (IntPtr.bitsGT(Src.getValueType()))
4536 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4538 // Scale the source by the type size.
4539 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4540 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4541 Src, DAG.getIntPtrConstant(ElementSize));
4543 TargetLowering::ArgListTy Args;
4544 TargetLowering::ArgListEntry Entry;
4546 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4547 Args.push_back(Entry);
4549 std::pair<SDOperand,SDOperand> Result =
4550 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4551 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4552 setValue(&I, Result.first); // Pointers always fit in registers
4553 DAG.setRoot(Result.second);
4556 void SelectionDAGLowering::visitFree(FreeInst &I) {
4557 TargetLowering::ArgListTy Args;
4558 TargetLowering::ArgListEntry Entry;
4559 Entry.Node = getValue(I.getOperand(0));
4560 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4561 Args.push_back(Entry);
4562 MVT IntPtr = TLI.getPointerTy();
4563 std::pair<SDOperand,SDOperand> Result =
4564 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4565 CallingConv::C, true,
4566 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4567 DAG.setRoot(Result.second);
4570 // EmitInstrWithCustomInserter - This method should be implemented by targets
4571 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4572 // instructions are special in various ways, which require special support to
4573 // insert. The specified MachineInstr is created but not inserted into any
4574 // basic blocks, and the scheduler passes ownership of it to this method.
4575 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4576 MachineBasicBlock *MBB) {
4577 cerr << "If a target marks an instruction with "
4578 << "'usesCustomDAGSchedInserter', it must implement "
4579 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4584 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4585 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4586 getValue(I.getOperand(1)),
4587 DAG.getSrcValue(I.getOperand(1))));
4590 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4591 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4592 getValue(I.getOperand(0)),
4593 DAG.getSrcValue(I.getOperand(0)));
4595 DAG.setRoot(V.getValue(1));
4598 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4599 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4600 getValue(I.getOperand(1)),
4601 DAG.getSrcValue(I.getOperand(1))));
4604 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4605 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4606 getValue(I.getOperand(1)),
4607 getValue(I.getOperand(2)),
4608 DAG.getSrcValue(I.getOperand(1)),
4609 DAG.getSrcValue(I.getOperand(2))));
4612 /// TargetLowering::LowerArguments - This is the default LowerArguments
4613 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4614 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4615 /// integrated into SDISel.
4616 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4617 SmallVectorImpl<SDOperand> &ArgValues) {
4618 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4619 SmallVector<SDOperand, 3+16> Ops;
4620 Ops.push_back(DAG.getRoot());
4621 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4622 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4624 // Add one result value for each formal argument.
4625 SmallVector<MVT, 16> RetVals;
4627 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4629 SmallVector<MVT, 4> ValueVTs;
4630 ComputeValueVTs(*this, I->getType(), ValueVTs);
4631 for (unsigned Value = 0, NumValues = ValueVTs.size();
4632 Value != NumValues; ++Value) {
4633 MVT VT = ValueVTs[Value];
4634 const Type *ArgTy = VT.getTypeForMVT();
4635 ISD::ArgFlagsTy Flags;
4636 unsigned OriginalAlignment =
4637 getTargetData()->getABITypeAlignment(ArgTy);
4639 if (F.paramHasAttr(j, ParamAttr::ZExt))
4641 if (F.paramHasAttr(j, ParamAttr::SExt))
4643 if (F.paramHasAttr(j, ParamAttr::InReg))
4645 if (F.paramHasAttr(j, ParamAttr::StructRet))
4647 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4649 const PointerType *Ty = cast<PointerType>(I->getType());
4650 const Type *ElementTy = Ty->getElementType();
4651 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4652 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4653 // For ByVal, alignment should be passed from FE. BE will guess if
4654 // this info is not there but there are cases it cannot get right.
4655 if (F.getParamAlignment(j))
4656 FrameAlign = F.getParamAlignment(j);
4657 Flags.setByValAlign(FrameAlign);
4658 Flags.setByValSize(FrameSize);
4660 if (F.paramHasAttr(j, ParamAttr::Nest))
4662 Flags.setOrigAlign(OriginalAlignment);
4664 MVT RegisterVT = getRegisterType(VT);
4665 unsigned NumRegs = getNumRegisters(VT);
4666 for (unsigned i = 0; i != NumRegs; ++i) {
4667 RetVals.push_back(RegisterVT);
4668 ISD::ArgFlagsTy MyFlags = Flags;
4669 if (NumRegs > 1 && i == 0)
4671 // if it isn't first piece, alignment must be 1
4673 MyFlags.setOrigAlign(1);
4674 Ops.push_back(DAG.getArgFlags(MyFlags));
4679 RetVals.push_back(MVT::Other);
4682 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4683 DAG.getVTList(&RetVals[0], RetVals.size()),
4684 &Ops[0], Ops.size()).Val;
4686 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4687 // allows exposing the loads that may be part of the argument access to the
4688 // first DAGCombiner pass.
4689 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4691 // The number of results should match up, except that the lowered one may have
4692 // an extra flag result.
4693 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4694 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4695 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4696 && "Lowering produced unexpected number of results!");
4697 Result = TmpRes.Val;
4699 unsigned NumArgRegs = Result->getNumValues() - 1;
4700 DAG.setRoot(SDOperand(Result, NumArgRegs));
4702 // Set up the return result vector.
4705 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4707 SmallVector<MVT, 4> ValueVTs;
4708 ComputeValueVTs(*this, I->getType(), ValueVTs);
4709 for (unsigned Value = 0, NumValues = ValueVTs.size();
4710 Value != NumValues; ++Value) {
4711 MVT VT = ValueVTs[Value];
4712 MVT PartVT = getRegisterType(VT);
4714 unsigned NumParts = getNumRegisters(VT);
4715 SmallVector<SDOperand, 4> Parts(NumParts);
4716 for (unsigned j = 0; j != NumParts; ++j)
4717 Parts[j] = SDOperand(Result, i++);
4719 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4720 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4721 AssertOp = ISD::AssertSext;
4722 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4723 AssertOp = ISD::AssertZext;
4725 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4729 assert(i == NumArgRegs && "Argument register count mismatch!");
4733 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4734 /// implementation, which just inserts an ISD::CALL node, which is later custom
4735 /// lowered by the target to something concrete. FIXME: When all targets are
4736 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4737 std::pair<SDOperand, SDOperand>
4738 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4739 bool RetSExt, bool RetZExt, bool isVarArg,
4740 unsigned CallingConv, bool isTailCall,
4742 ArgListTy &Args, SelectionDAG &DAG) {
4743 SmallVector<SDOperand, 32> Ops;
4744 Ops.push_back(Chain); // Op#0 - Chain
4745 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4746 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4747 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4748 Ops.push_back(Callee);
4750 // Handle all of the outgoing arguments.
4751 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4752 SmallVector<MVT, 4> ValueVTs;
4753 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4754 for (unsigned Value = 0, NumValues = ValueVTs.size();
4755 Value != NumValues; ++Value) {
4756 MVT VT = ValueVTs[Value];
4757 const Type *ArgTy = VT.getTypeForMVT();
4758 SDOperand Op = SDOperand(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4759 ISD::ArgFlagsTy Flags;
4760 unsigned OriginalAlignment =
4761 getTargetData()->getABITypeAlignment(ArgTy);
4767 if (Args[i].isInReg)
4771 if (Args[i].isByVal) {
4773 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4774 const Type *ElementTy = Ty->getElementType();
4775 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4776 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4777 // For ByVal, alignment should come from FE. BE will guess if this
4778 // info is not there but there are cases it cannot get right.
4779 if (Args[i].Alignment)
4780 FrameAlign = Args[i].Alignment;
4781 Flags.setByValAlign(FrameAlign);
4782 Flags.setByValSize(FrameSize);
4786 Flags.setOrigAlign(OriginalAlignment);
4788 MVT PartVT = getRegisterType(VT);
4789 unsigned NumParts = getNumRegisters(VT);
4790 SmallVector<SDOperand, 4> Parts(NumParts);
4791 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4794 ExtendKind = ISD::SIGN_EXTEND;
4795 else if (Args[i].isZExt)
4796 ExtendKind = ISD::ZERO_EXTEND;
4798 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4800 for (unsigned i = 0; i != NumParts; ++i) {
4801 // if it isn't first piece, alignment must be 1
4802 ISD::ArgFlagsTy MyFlags = Flags;
4803 if (NumParts > 1 && i == 0)
4806 MyFlags.setOrigAlign(1);
4808 Ops.push_back(Parts[i]);
4809 Ops.push_back(DAG.getArgFlags(MyFlags));
4814 // Figure out the result value types. We start by making a list of
4815 // the potentially illegal return value types.
4816 SmallVector<MVT, 4> LoweredRetTys;
4817 SmallVector<MVT, 4> RetTys;
4818 ComputeValueVTs(*this, RetTy, RetTys);
4820 // Then we translate that to a list of legal types.
4821 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4823 MVT RegisterVT = getRegisterType(VT);
4824 unsigned NumRegs = getNumRegisters(VT);
4825 for (unsigned i = 0; i != NumRegs; ++i)
4826 LoweredRetTys.push_back(RegisterVT);
4829 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4831 // Create the CALL node.
4832 SDOperand Res = DAG.getNode(ISD::CALL,
4833 DAG.getVTList(&LoweredRetTys[0],
4834 LoweredRetTys.size()),
4835 &Ops[0], Ops.size());
4836 Chain = Res.getValue(LoweredRetTys.size() - 1);
4838 // Gather up the call result into a single value.
4839 if (RetTy != Type::VoidTy) {
4840 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4843 AssertOp = ISD::AssertSext;
4845 AssertOp = ISD::AssertZext;
4847 SmallVector<SDOperand, 4> ReturnValues;
4849 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4851 MVT RegisterVT = getRegisterType(VT);
4852 unsigned NumRegs = getNumRegisters(VT);
4853 unsigned RegNoEnd = NumRegs + RegNo;
4854 SmallVector<SDOperand, 4> Results;
4855 for (; RegNo != RegNoEnd; ++RegNo)
4856 Results.push_back(Res.getValue(RegNo));
4857 SDOperand ReturnValue =
4858 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4860 ReturnValues.push_back(ReturnValue);
4862 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4863 &ReturnValues[0], ReturnValues.size());
4866 return std::make_pair(Res, Chain);
4869 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4870 assert(0 && "LowerOperation not implemented for this target!");
4875 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4876 SelectionDAG &DAG) {
4877 assert(0 && "CustomPromoteOperation not implemented for this target!");
4882 //===----------------------------------------------------------------------===//
4883 // SelectionDAGISel code
4884 //===----------------------------------------------------------------------===//
4886 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4887 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4890 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4891 AU.addRequired<AliasAnalysis>();
4892 AU.addRequired<CollectorModuleMetadata>();
4893 AU.setPreservesAll();
4896 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4897 // Get alias analysis for load/store combining.
4898 AA = &getAnalysis<AliasAnalysis>();
4900 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4901 if (MF.getFunction()->hasCollector())
4902 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4905 RegInfo = &MF.getRegInfo();
4906 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4908 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4910 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4911 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4912 // Mark landing pad.
4913 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4915 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4916 SelectBasicBlock(I, MF, FuncInfo);
4918 // Add function live-ins to entry block live-in set.
4919 BasicBlock *EntryBB = &Fn.getEntryBlock();
4920 BB = FuncInfo.MBBMap[EntryBB];
4921 if (!RegInfo->livein_empty())
4922 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4923 E = RegInfo->livein_end(); I != E; ++I)
4924 BB->addLiveIn(I->first);
4927 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4928 "Not all catch info was assigned to a landing pad!");
4934 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4935 SDOperand Op = getValue(V);
4936 assert((Op.getOpcode() != ISD::CopyFromReg ||
4937 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4938 "Copy from a reg to the same reg!");
4939 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4941 RegsForValue RFV(TLI, Reg, V->getType());
4942 SDOperand Chain = DAG.getEntryNode();
4943 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4944 PendingExports.push_back(Chain);
4947 void SelectionDAGISel::
4948 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4949 // If this is the entry block, emit arguments.
4950 Function &F = *LLVMBB->getParent();
4951 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4952 SDOperand OldRoot = SDL.DAG.getRoot();
4953 SmallVector<SDOperand, 16> Args;
4954 TLI.LowerArguments(F, SDL.DAG, Args);
4957 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4959 SmallVector<MVT, 4> ValueVTs;
4960 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4961 unsigned NumValues = ValueVTs.size();
4962 if (!AI->use_empty()) {
4963 SmallVector<MVT, 4> LegalValueVTs(NumValues);
4964 for (unsigned VI = 0; VI != NumValues; ++VI)
4965 LegalValueVTs[VI] = Args[a + VI].getValueType();
4967 SDL.DAG.getMergeValues(SDL.DAG.getVTList(&LegalValueVTs[0],
4969 &Args[a], NumValues));
4970 // If this argument is live outside of the entry block, insert a copy from
4971 // whereever we got it to the vreg that other BB's will reference it as.
4972 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4973 if (VMI != FuncInfo.ValueMap.end()) {
4974 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4980 // Finally, if the target has anything special to do, allow it to do so.
4981 // FIXME: this should insert code into the DAG!
4982 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4985 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4986 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4987 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4988 if (isSelector(I)) {
4989 // Apply the catch info to DestBB.
4990 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4992 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4993 FLI.CatchInfoFound.insert(I);
4998 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4999 /// whether object offset >= 0.
5001 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDOperand Op) {
5002 if (!isa<FrameIndexSDNode>(Op)) return false;
5004 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
5005 int FrameIdx = FrameIdxNode->getIndex();
5006 return MFI->isFixedObjectIndex(FrameIdx) &&
5007 MFI->getObjectOffset(FrameIdx) >= 0;
5010 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
5011 /// possibly be overwritten when lowering the outgoing arguments in a tail
5012 /// call. Currently the implementation of this call is very conservative and
5013 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
5014 /// virtual registers would be overwritten by direct lowering.
5015 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
5016 MachineFrameInfo * MFI) {
5017 RegisterSDNode * OpReg = NULL;
5018 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
5019 (Op.getOpcode()== ISD::CopyFromReg &&
5020 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
5021 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
5022 (Op.getOpcode() == ISD::LOAD &&
5023 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
5024 (Op.getOpcode() == ISD::MERGE_VALUES &&
5025 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
5026 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
5032 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
5033 /// DAG and fixes their tailcall attribute operand.
5034 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
5035 TargetLowering& TLI) {
5036 SDNode * Ret = NULL;
5037 SDOperand Terminator = DAG.getRoot();
5040 if (Terminator.getOpcode() == ISD::RET) {
5041 Ret = Terminator.Val;
5044 // Fix tail call attribute of CALL nodes.
5045 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5046 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
5047 if (BI->getOpcode() == ISD::CALL) {
5048 SDOperand OpRet(Ret, 0);
5049 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
5050 bool isMarkedTailCall =
5051 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5052 // If CALL node has tail call attribute set to true and the call is not
5053 // eligible (no RET or the target rejects) the attribute is fixed to
5054 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5055 // must correctly identify tail call optimizable calls.
5056 if (!isMarkedTailCall) continue;
5058 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5059 // Not eligible. Mark CALL node as non tail call.
5060 SmallVector<SDOperand, 32> Ops;
5062 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5063 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5067 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5069 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5071 // Look for tail call clobbered arguments. Emit a series of
5072 // copyto/copyfrom virtual register nodes to protect them.
5073 SmallVector<SDOperand, 32> Ops;
5074 SDOperand Chain = OpCall.getOperand(0), InFlag;
5076 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5077 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5079 if (idx > 4 && (idx % 2)) {
5080 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5081 getArgFlags().isByVal();
5082 MachineFunction &MF = DAG.getMachineFunction();
5083 MachineFrameInfo *MFI = MF.getFrameInfo();
5085 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5086 MVT VT = Arg.getValueType();
5087 unsigned VReg = MF.getRegInfo().
5088 createVirtualRegister(TLI.getRegClassFor(VT));
5089 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5090 InFlag = Chain.getValue(1);
5091 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5092 Chain = Arg.getValue(1);
5093 InFlag = Arg.getValue(2);
5098 // Link in chain of CopyTo/CopyFromReg.
5100 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5106 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5107 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5108 FunctionLoweringInfo &FuncInfo) {
5109 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
5111 // Lower any arguments needed in this block if this is the entry block.
5112 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5113 LowerArguments(LLVMBB, SDL);
5115 BB = FuncInfo.MBBMap[LLVMBB];
5116 SDL.setCurrentBasicBlock(BB);
5118 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5120 if (MMI && BB->isLandingPad()) {
5121 // Add a label to mark the beginning of the landing pad. Deletion of the
5122 // landing pad can thus be detected via the MachineModuleInfo.
5123 unsigned LabelID = MMI->addLandingPad(BB);
5124 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
5125 DAG.getConstant(LabelID, MVT::i32),
5126 DAG.getConstant(1, MVT::i32)));
5128 // Mark exception register as live in.
5129 unsigned Reg = TLI.getExceptionAddressRegister();
5130 if (Reg) BB->addLiveIn(Reg);
5132 // Mark exception selector register as live in.
5133 Reg = TLI.getExceptionSelectorRegister();
5134 if (Reg) BB->addLiveIn(Reg);
5136 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5137 // function and list of typeids logically belong to the invoke (or, if you
5138 // like, the basic block containing the invoke), and need to be associated
5139 // with it in the dwarf exception handling tables. Currently however the
5140 // information is provided by an intrinsic (eh.selector) that can be moved
5141 // to unexpected places by the optimizers: if the unwind edge is critical,
5142 // then breaking it can result in the intrinsics being in the successor of
5143 // the landing pad, not the landing pad itself. This results in exceptions
5144 // not being caught because no typeids are associated with the invoke.
5145 // This may not be the only way things can go wrong, but it is the only way
5146 // we try to work around for the moment.
5147 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5149 if (Br && Br->isUnconditional()) { // Critical edge?
5150 BasicBlock::iterator I, E;
5151 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5156 // No catch info found - try to extract some from the successor.
5157 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5161 // Lower all of the non-terminator instructions.
5162 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
5166 // Ensure that all instructions which are used outside of their defining
5167 // blocks are available as virtual registers. Invoke is handled elsewhere.
5168 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
5169 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5170 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5171 if (VMI != FuncInfo.ValueMap.end())
5172 SDL.CopyValueToVirtualRegister(I, VMI->second);
5175 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5176 // ensure constants are generated when needed. Remember the virtual registers
5177 // that need to be added to the Machine PHI nodes as input. We cannot just
5178 // directly add them, because expansion might result in multiple MBB's for one
5179 // BB. As such, the start of the BB might correspond to a different MBB than
5182 TerminatorInst *TI = LLVMBB->getTerminator();
5184 // Emit constants only once even if used by multiple PHI nodes.
5185 std::map<Constant*, unsigned> ConstantsOut;
5187 // Vector bool would be better, but vector<bool> is really slow.
5188 std::vector<unsigned char> SuccsHandled;
5189 if (TI->getNumSuccessors())
5190 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5192 // Check successor nodes' PHI nodes that expect a constant to be available
5194 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5195 BasicBlock *SuccBB = TI->getSuccessor(succ);
5196 if (!isa<PHINode>(SuccBB->begin())) continue;
5197 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5199 // If this terminator has multiple identical successors (common for
5200 // switches), only handle each succ once.
5201 unsigned SuccMBBNo = SuccMBB->getNumber();
5202 if (SuccsHandled[SuccMBBNo]) continue;
5203 SuccsHandled[SuccMBBNo] = true;
5205 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5208 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5209 // nodes and Machine PHI nodes, but the incoming operands have not been
5211 for (BasicBlock::iterator I = SuccBB->begin();
5212 (PN = dyn_cast<PHINode>(I)); ++I) {
5213 // Ignore dead phi's.
5214 if (PN->use_empty()) continue;
5217 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5219 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5220 unsigned &RegOut = ConstantsOut[C];
5222 RegOut = FuncInfo.CreateRegForValue(C);
5223 SDL.CopyValueToVirtualRegister(C, RegOut);
5227 Reg = FuncInfo.ValueMap[PHIOp];
5229 assert(isa<AllocaInst>(PHIOp) &&
5230 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5231 "Didn't codegen value into a register!??");
5232 Reg = FuncInfo.CreateRegForValue(PHIOp);
5233 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5237 // Remember that this register needs to added to the machine PHI node as
5238 // the input for this MBB.
5239 MVT VT = TLI.getValueType(PN->getType());
5240 unsigned NumRegisters = TLI.getNumRegisters(VT);
5241 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5242 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5245 ConstantsOut.clear();
5247 // Lower the terminator after the copies are emitted.
5248 SDL.visit(*LLVMBB->getTerminator());
5250 // Copy over any CaseBlock records that may now exist due to SwitchInst
5251 // lowering, as well as any jump table information.
5252 SwitchCases.clear();
5253 SwitchCases = SDL.SwitchCases;
5255 JTCases = SDL.JTCases;
5256 BitTestCases.clear();
5257 BitTestCases = SDL.BitTestCases;
5259 // Make sure the root of the DAG is up-to-date.
5260 DAG.setRoot(SDL.getControlRoot());
5262 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5263 // with correct tailcall attribute so that the target can rely on the tailcall
5264 // attribute indicating whether the call is really eligible for tail call
5266 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5269 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5270 SmallPtrSet<SDNode*, 128> VisitedNodes;
5271 SmallVector<SDNode*, 128> Worklist;
5273 Worklist.push_back(DAG.getRoot().Val);
5279 while (!Worklist.empty()) {
5280 SDNode *N = Worklist.back();
5281 Worklist.pop_back();
5283 // If we've already seen this node, ignore it.
5284 if (!VisitedNodes.insert(N))
5287 // Otherwise, add all chain operands to the worklist.
5288 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5289 if (N->getOperand(i).getValueType() == MVT::Other)
5290 Worklist.push_back(N->getOperand(i).Val);
5292 // If this is a CopyToReg with a vreg dest, process it.
5293 if (N->getOpcode() != ISD::CopyToReg)
5296 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5297 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5300 // Ignore non-scalar or non-integer values.
5301 SDOperand Src = N->getOperand(2);
5302 MVT SrcVT = Src.getValueType();
5303 if (!SrcVT.isInteger() || SrcVT.isVector())
5306 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5307 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5308 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5310 // Only install this information if it tells us something.
5311 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5312 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5313 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5314 if (DestReg >= FLI.LiveOutRegInfo.size())
5315 FLI.LiveOutRegInfo.resize(DestReg+1);
5316 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5317 LOI.NumSignBits = NumSignBits;
5318 LOI.KnownOne = NumSignBits;
5319 LOI.KnownZero = NumSignBits;
5324 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5325 DOUT << "Lowered selection DAG:\n";
5328 // Run the DAG combiner in pre-legalize mode.
5329 DAG.Combine(false, *AA);
5331 DOUT << "Optimized lowered selection DAG:\n";
5334 // Second step, hack on the DAG until it only uses operations and types that
5335 // the target supports.
5336 #if 0 // Enable this some day.
5337 DAG.LegalizeTypes();
5338 // Someday even later, enable a dag combine pass here.
5342 DOUT << "Legalized selection DAG:\n";
5345 // Run the DAG combiner in post-legalize mode.
5346 DAG.Combine(true, *AA);
5348 DOUT << "Optimized legalized selection DAG:\n";
5351 if (ViewISelDAGs) DAG.viewGraph();
5353 if (EnableValueProp) // FIXME: Only do this if !fast.
5354 ComputeLiveOutVRegInfo(DAG);
5356 // Third, instruction select all of the operations to machine code, adding the
5357 // code to the MachineBasicBlock.
5358 InstructionSelect(DAG);
5360 // Emit machine code to BB. This can change 'BB' to the last block being
5362 ScheduleAndEmitDAG(DAG);
5364 // Perform target specific isel post processing.
5365 InstructionSelectPostProcessing(DAG);
5367 DOUT << "Selected machine code:\n";
5371 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5372 FunctionLoweringInfo &FuncInfo) {
5373 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5375 SelectionDAG DAG(TLI, MF, FuncInfo,
5376 getAnalysisToUpdate<MachineModuleInfo>());
5379 // First step, lower LLVM code to some DAG. This DAG may use operations and
5380 // types that are not supported by the target.
5381 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5383 // Second step, emit the lowered DAG as machine code.
5384 CodeGenAndEmitDAG(DAG);
5387 DOUT << "Total amount of phi nodes to update: "
5388 << PHINodesToUpdate.size() << "\n";
5389 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5390 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5391 << ", " << PHINodesToUpdate[i].second << ")\n";);
5393 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5394 // PHI nodes in successors.
5395 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5396 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5397 MachineInstr *PHI = PHINodesToUpdate[i].first;
5398 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5399 "This is not a machine PHI node that we are updating!");
5400 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5402 PHI->addOperand(MachineOperand::CreateMBB(BB));
5407 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5408 // Lower header first, if it wasn't already lowered
5409 if (!BitTestCases[i].Emitted) {
5410 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5411 getAnalysisToUpdate<MachineModuleInfo>());
5413 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5414 // Set the current basic block to the mbb we wish to insert the code into
5415 BB = BitTestCases[i].Parent;
5416 HSDL.setCurrentBasicBlock(BB);
5418 HSDL.visitBitTestHeader(BitTestCases[i]);
5419 HSDAG.setRoot(HSDL.getRoot());
5420 CodeGenAndEmitDAG(HSDAG);
5423 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5424 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5425 getAnalysisToUpdate<MachineModuleInfo>());
5427 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5428 // Set the current basic block to the mbb we wish to insert the code into
5429 BB = BitTestCases[i].Cases[j].ThisBB;
5430 BSDL.setCurrentBasicBlock(BB);
5433 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5434 BitTestCases[i].Reg,
5435 BitTestCases[i].Cases[j]);
5437 BSDL.visitBitTestCase(BitTestCases[i].Default,
5438 BitTestCases[i].Reg,
5439 BitTestCases[i].Cases[j]);
5442 BSDAG.setRoot(BSDL.getRoot());
5443 CodeGenAndEmitDAG(BSDAG);
5447 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5448 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5449 MachineBasicBlock *PHIBB = PHI->getParent();
5450 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5451 "This is not a machine PHI node that we are updating!");
5452 // This is "default" BB. We have two jumps to it. From "header" BB and
5453 // from last "case" BB.
5454 if (PHIBB == BitTestCases[i].Default) {
5455 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5457 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5458 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5460 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5463 // One of "cases" BB.
5464 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5465 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5466 if (cBB->succ_end() !=
5467 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5468 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5470 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5476 // If the JumpTable record is filled in, then we need to emit a jump table.
5477 // Updating the PHI nodes is tricky in this case, since we need to determine
5478 // whether the PHI is a successor of the range check MBB or the jump table MBB
5479 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5480 // Lower header first, if it wasn't already lowered
5481 if (!JTCases[i].first.Emitted) {
5482 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5483 getAnalysisToUpdate<MachineModuleInfo>());
5485 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5486 // Set the current basic block to the mbb we wish to insert the code into
5487 BB = JTCases[i].first.HeaderBB;
5488 HSDL.setCurrentBasicBlock(BB);
5490 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5491 HSDAG.setRoot(HSDL.getRoot());
5492 CodeGenAndEmitDAG(HSDAG);
5495 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5496 getAnalysisToUpdate<MachineModuleInfo>());
5498 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5499 // Set the current basic block to the mbb we wish to insert the code into
5500 BB = JTCases[i].second.MBB;
5501 JSDL.setCurrentBasicBlock(BB);
5503 JSDL.visitJumpTable(JTCases[i].second);
5504 JSDAG.setRoot(JSDL.getRoot());
5505 CodeGenAndEmitDAG(JSDAG);
5508 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5509 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5510 MachineBasicBlock *PHIBB = PHI->getParent();
5511 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5512 "This is not a machine PHI node that we are updating!");
5513 // "default" BB. We can go there only from header BB.
5514 if (PHIBB == JTCases[i].second.Default) {
5515 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5517 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5519 // JT BB. Just iterate over successors here
5520 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5521 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5523 PHI->addOperand(MachineOperand::CreateMBB(BB));
5528 // If the switch block involved a branch to one of the actual successors, we
5529 // need to update PHI nodes in that block.
5530 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5531 MachineInstr *PHI = PHINodesToUpdate[i].first;
5532 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5533 "This is not a machine PHI node that we are updating!");
5534 if (BB->isSuccessor(PHI->getParent())) {
5535 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5537 PHI->addOperand(MachineOperand::CreateMBB(BB));
5541 // If we generated any switch lowering information, build and codegen any
5542 // additional DAGs necessary.
5543 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5544 SelectionDAG SDAG(TLI, MF, FuncInfo,
5545 getAnalysisToUpdate<MachineModuleInfo>());
5547 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5549 // Set the current basic block to the mbb we wish to insert the code into
5550 BB = SwitchCases[i].ThisBB;
5551 SDL.setCurrentBasicBlock(BB);
5554 SDL.visitSwitchCase(SwitchCases[i]);
5555 SDAG.setRoot(SDL.getRoot());
5556 CodeGenAndEmitDAG(SDAG);
5558 // Handle any PHI nodes in successors of this chunk, as if we were coming
5559 // from the original BB before switch expansion. Note that PHI nodes can
5560 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5561 // handle them the right number of times.
5562 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5563 for (MachineBasicBlock::iterator Phi = BB->begin();
5564 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5565 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5566 for (unsigned pn = 0; ; ++pn) {
5567 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5568 if (PHINodesToUpdate[pn].first == Phi) {
5569 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5571 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5577 // Don't process RHS if same block as LHS.
5578 if (BB == SwitchCases[i].FalseBB)
5579 SwitchCases[i].FalseBB = 0;
5581 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5582 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5583 SwitchCases[i].FalseBB = 0;
5585 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5590 //===----------------------------------------------------------------------===//
5591 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5592 /// target node in the graph.
5593 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5594 if (ViewSchedDAGs) DAG.viewGraph();
5596 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5600 RegisterScheduler::setDefault(Ctor);
5603 ScheduleDAG *SL = Ctor(this, &DAG, BB);
5606 if (ViewSUnitDAGs) SL->viewGraph();
5612 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5613 return new HazardRecognizer();
5616 //===----------------------------------------------------------------------===//
5617 // Helper functions used by the generated instruction selector.
5618 //===----------------------------------------------------------------------===//
5619 // Calls to these methods are generated by tblgen.
5621 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5622 /// the dag combiner simplified the 255, we still want to match. RHS is the
5623 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5624 /// specified in the .td file (e.g. 255).
5625 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5626 int64_t DesiredMaskS) const {
5627 const APInt &ActualMask = RHS->getAPIntValue();
5628 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5630 // If the actual mask exactly matches, success!
5631 if (ActualMask == DesiredMask)
5634 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5635 if (ActualMask.intersects(~DesiredMask))
5638 // Otherwise, the DAG Combiner may have proven that the value coming in is
5639 // either already zero or is not demanded. Check for known zero input bits.
5640 APInt NeededMask = DesiredMask & ~ActualMask;
5641 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5644 // TODO: check to see if missing bits are just not demanded.
5646 // Otherwise, this pattern doesn't match.
5650 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5651 /// the dag combiner simplified the 255, we still want to match. RHS is the
5652 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5653 /// specified in the .td file (e.g. 255).
5654 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5655 int64_t DesiredMaskS) const {
5656 const APInt &ActualMask = RHS->getAPIntValue();
5657 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5659 // If the actual mask exactly matches, success!
5660 if (ActualMask == DesiredMask)
5663 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5664 if (ActualMask.intersects(~DesiredMask))
5667 // Otherwise, the DAG Combiner may have proven that the value coming in is
5668 // either already zero or is not demanded. Check for known zero input bits.
5669 APInt NeededMask = DesiredMask & ~ActualMask;
5671 APInt KnownZero, KnownOne;
5672 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5674 // If all the missing bits in the or are already known to be set, match!
5675 if ((NeededMask & KnownOne) == NeededMask)
5678 // TODO: check to see if missing bits are just not demanded.
5680 // Otherwise, this pattern doesn't match.
5685 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5686 /// by tblgen. Others should not call it.
5687 void SelectionDAGISel::
5688 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5689 std::vector<SDOperand> InOps;
5690 std::swap(InOps, Ops);
5692 Ops.push_back(InOps[0]); // input chain.
5693 Ops.push_back(InOps[1]); // input asm string.
5695 unsigned i = 2, e = InOps.size();
5696 if (InOps[e-1].getValueType() == MVT::Flag)
5697 --e; // Don't process a flag operand if it is here.
5700 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5701 if ((Flags & 7) != 4 /*MEM*/) {
5702 // Just skip over this operand, copying the operands verbatim.
5703 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5704 i += (Flags >> 3) + 1;
5706 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5707 // Otherwise, this is a memory operand. Ask the target to select it.
5708 std::vector<SDOperand> SelOps;
5709 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5710 cerr << "Could not match memory address. Inline asm failure!\n";
5714 // Add this to the output node.
5715 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5716 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5718 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5723 // Add the flag input back if present.
5724 if (e != InOps.size())
5725 Ops.push_back(InOps.back());
5728 char SelectionDAGISel::ID = 0;