1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
66 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
67 STATISTIC(NumFastIselFailLowerArguments,
68 "Number of entry blocks where fast isel failed to lower arguments");
72 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
73 cl::desc("Enable extra verbose messages in the \"fast\" "
74 "instruction selector"));
77 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
78 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
79 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
80 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
81 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
82 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
83 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
85 // Standard binary operators...
86 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
87 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
88 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
89 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
90 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
91 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
92 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
93 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
94 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
95 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
96 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
97 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
99 // Logical operators...
100 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
101 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
102 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
104 // Memory instructions...
105 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
106 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
107 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
108 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
109 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
110 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
111 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
113 // Convert instructions...
114 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
115 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
116 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
117 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
118 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
119 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
120 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
121 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
122 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
123 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
124 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
125 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
127 // Other instructions...
128 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
129 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
130 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
131 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
132 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
133 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
134 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
135 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
136 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
137 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
138 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
139 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
140 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
141 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
142 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
146 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
147 cl::desc("Enable verbose messages in the \"fast\" "
148 "instruction selector"));
150 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
151 cl::desc("Enable abort calls when \"fast\" instruction selection "
152 "fails to lower an instruction"));
154 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
155 cl::desc("Enable abort calls when \"fast\" instruction selection "
156 "fails to lower a formal argument"));
160 cl::desc("use Machine Branch Probability Info"),
161 cl::init(true), cl::Hidden);
165 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before the first "
167 "dag combine pass"));
169 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
170 cl::desc("Pop up a window to show dags before legalize types"));
172 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
173 cl::desc("Pop up a window to show dags before legalize"));
175 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
176 cl::desc("Pop up a window to show dags before the second "
177 "dag combine pass"));
179 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
180 cl::desc("Pop up a window to show dags before the post legalize types"
181 " dag combine pass"));
183 ViewISelDAGs("view-isel-dags", cl::Hidden,
184 cl::desc("Pop up a window to show isel dags as they are selected"));
186 ViewSchedDAGs("view-sched-dags", cl::Hidden,
187 cl::desc("Pop up a window to show sched dags as they are processed"));
189 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
190 cl::desc("Pop up a window to show SUnit dags after they are processed"));
192 static const bool ViewDAGCombine1 = false,
193 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
194 ViewDAGCombine2 = false,
195 ViewDAGCombineLT = false,
196 ViewISelDAGs = false, ViewSchedDAGs = false,
197 ViewSUnitDAGs = false;
200 //===---------------------------------------------------------------------===//
202 /// RegisterScheduler class - Track the registration of instruction schedulers.
204 //===---------------------------------------------------------------------===//
205 MachinePassRegistry RegisterScheduler::Registry;
207 //===---------------------------------------------------------------------===//
209 /// ISHeuristic command line option for instruction schedulers.
211 //===---------------------------------------------------------------------===//
212 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
213 RegisterPassParser<RegisterScheduler> >
214 ISHeuristic("pre-RA-sched",
215 cl::init(&createDefaultScheduler),
216 cl::desc("Instruction schedulers available (before register"
219 static RegisterScheduler
220 defaultListDAGScheduler("default", "Best scheduler for the target",
221 createDefaultScheduler);
224 //===--------------------------------------------------------------------===//
225 /// createDefaultScheduler - This creates an instruction scheduler appropriate
227 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
228 CodeGenOpt::Level OptLevel) {
229 const TargetLowering &TLI = IS->getTargetLowering();
230 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
232 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
233 TLI.getSchedulingPreference() == Sched::Source)
234 return createSourceListDAGScheduler(IS, OptLevel);
235 if (TLI.getSchedulingPreference() == Sched::RegPressure)
236 return createBURRListDAGScheduler(IS, OptLevel);
237 if (TLI.getSchedulingPreference() == Sched::Hybrid)
238 return createHybridListDAGScheduler(IS, OptLevel);
239 if (TLI.getSchedulingPreference() == Sched::VLIW)
240 return createVLIWDAGScheduler(IS, OptLevel);
241 assert(TLI.getSchedulingPreference() == Sched::ILP &&
242 "Unknown sched type!");
243 return createILPListDAGScheduler(IS, OptLevel);
247 // EmitInstrWithCustomInserter - This method should be implemented by targets
248 // that mark instructions with the 'usesCustomInserter' flag. These
249 // instructions are special in various ways, which require special support to
250 // insert. The specified MachineInstr is created but not inserted into any
251 // basic blocks, and this method is called to expand it into a sequence of
252 // instructions, potentially also creating new basic blocks and control flow.
253 // When new basic blocks are inserted and the edges from MBB to its successors
254 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
257 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
258 MachineBasicBlock *MBB) const {
260 dbgs() << "If a target marks an instruction with "
261 "'usesCustomInserter', it must implement "
262 "TargetLowering::EmitInstrWithCustomInserter!";
267 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
268 SDNode *Node) const {
269 assert(!MI->hasPostISelHook() &&
270 "If a target marks an instruction with 'hasPostISelHook', "
271 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
274 //===----------------------------------------------------------------------===//
275 // SelectionDAGISel code
276 //===----------------------------------------------------------------------===//
278 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
279 CodeGenOpt::Level OL) :
280 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
281 FuncInfo(new FunctionLoweringInfo(TLI)),
282 CurDAG(new SelectionDAG(tm, OL)),
283 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
287 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
288 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
289 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
290 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
293 SelectionDAGISel::~SelectionDAGISel() {
299 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
300 AU.addRequired<AliasAnalysis>();
301 AU.addPreserved<AliasAnalysis>();
302 AU.addRequired<GCModuleInfo>();
303 AU.addPreserved<GCModuleInfo>();
304 AU.addRequired<TargetLibraryInfo>();
305 if (UseMBPI && OptLevel != CodeGenOpt::None)
306 AU.addRequired<BranchProbabilityInfo>();
307 MachineFunctionPass::getAnalysisUsage(AU);
310 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
311 /// may trap on it. In this case we have to split the edge so that the path
312 /// through the predecessor block that doesn't go to the phi block doesn't
313 /// execute the possibly trapping instruction.
315 /// This is required for correctness, so it must be done at -O0.
317 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
318 // Loop for blocks with phi nodes.
319 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
320 PHINode *PN = dyn_cast<PHINode>(BB->begin());
321 if (PN == 0) continue;
324 // For each block with a PHI node, check to see if any of the input values
325 // are potentially trapping constant expressions. Constant expressions are
326 // the only potentially trapping value that can occur as the argument to a
328 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
329 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
330 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
331 if (CE == 0 || !CE->canTrap()) continue;
333 // The only case we have to worry about is when the edge is critical.
334 // Since this block has a PHI Node, we assume it has multiple input
335 // edges: check to see if the pred has multiple successors.
336 BasicBlock *Pred = PN->getIncomingBlock(i);
337 if (Pred->getTerminator()->getNumSuccessors() == 1)
340 // Okay, we have to split this edge.
341 SplitCriticalEdge(Pred->getTerminator(),
342 GetSuccessorNumber(Pred, BB), SDISel, true);
348 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
349 // Do some sanity-checking on the command-line options.
350 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
351 "-fast-isel-verbose requires -fast-isel");
352 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
353 "-fast-isel-abort requires -fast-isel");
355 const Function &Fn = *mf.getFunction();
356 const TargetInstrInfo &TII = *TM.getInstrInfo();
357 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
360 RegInfo = &MF->getRegInfo();
361 AA = &getAnalysis<AliasAnalysis>();
362 LibInfo = &getAnalysis<TargetLibraryInfo>();
363 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
364 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
366 TargetSubtargetInfo &ST =
367 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
368 ST.resetSubtargetFeatures(MF);
369 TM.resetTargetOptions(MF);
371 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
373 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
375 CurDAG->init(*MF, TTI);
376 FuncInfo->set(Fn, *MF);
378 if (UseMBPI && OptLevel != CodeGenOpt::None)
379 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
383 SDB->init(GFI, *AA, LibInfo);
385 MF->setHasMSInlineAsm(false);
386 SelectAllBasicBlocks(Fn);
388 // If the first basic block in the function has live ins that need to be
389 // copied into vregs, emit the copies into the top of the block before
390 // emitting the code for the block.
391 MachineBasicBlock *EntryMBB = MF->begin();
392 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
394 DenseMap<unsigned, unsigned> LiveInMap;
395 if (!FuncInfo->ArgDbgValues.empty())
396 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
397 E = RegInfo->livein_end(); LI != E; ++LI)
399 LiveInMap.insert(std::make_pair(LI->first, LI->second));
401 // Insert DBG_VALUE instructions for function arguments to the entry block.
402 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
403 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
404 unsigned Reg = MI->getOperand(0).getReg();
405 if (TargetRegisterInfo::isPhysicalRegister(Reg))
406 EntryMBB->insert(EntryMBB->begin(), MI);
408 MachineInstr *Def = RegInfo->getVRegDef(Reg);
409 MachineBasicBlock::iterator InsertPos = Def;
410 // FIXME: VR def may not be in entry block.
411 Def->getParent()->insert(llvm::next(InsertPos), MI);
414 // If Reg is live-in then update debug info to track its copy in a vreg.
415 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
416 if (LDI != LiveInMap.end()) {
417 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
418 MachineBasicBlock::iterator InsertPos = Def;
419 const MDNode *Variable =
420 MI->getOperand(MI->getNumOperands()-1).getMetadata();
421 unsigned Offset = MI->getOperand(1).getImm();
422 // Def is never a terminator here, so it is ok to increment InsertPos.
423 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
424 TII.get(TargetOpcode::DBG_VALUE))
425 .addReg(LDI->second, RegState::Debug)
426 .addImm(Offset).addMetadata(Variable);
428 // If this vreg is directly copied into an exported register then
429 // that COPY instructions also need DBG_VALUE, if it is the only
430 // user of LDI->second.
431 MachineInstr *CopyUseMI = NULL;
432 for (MachineRegisterInfo::use_iterator
433 UI = RegInfo->use_begin(LDI->second);
434 MachineInstr *UseMI = UI.skipInstruction();) {
435 if (UseMI->isDebugValue()) continue;
436 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
437 CopyUseMI = UseMI; continue;
439 // Otherwise this is another use or second copy use.
440 CopyUseMI = NULL; break;
443 MachineInstr *NewMI =
444 BuildMI(*MF, CopyUseMI->getDebugLoc(),
445 TII.get(TargetOpcode::DBG_VALUE))
446 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
447 .addImm(Offset).addMetadata(Variable);
448 MachineBasicBlock::iterator Pos = CopyUseMI;
449 EntryMBB->insertAfter(Pos, NewMI);
454 // Determine if there are any calls in this machine function.
455 MachineFrameInfo *MFI = MF->getFrameInfo();
456 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
459 if (MFI->hasCalls() && MF->hasMSInlineAsm())
462 const MachineBasicBlock *MBB = I;
463 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
465 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
466 if ((MCID.isCall() && !MCID.isReturn()) ||
467 II->isStackAligningInlineAsm()) {
468 MFI->setHasCalls(true);
470 if (II->isMSInlineAsm()) {
471 MF->setHasMSInlineAsm(true);
476 // Determine if there is a call to setjmp in the machine function.
477 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
479 // Replace forward-declared registers with the registers containing
480 // the desired value.
481 MachineRegisterInfo &MRI = MF->getRegInfo();
482 for (DenseMap<unsigned, unsigned>::iterator
483 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
485 unsigned From = I->first;
486 unsigned To = I->second;
487 // If To is also scheduled to be replaced, find what its ultimate
490 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
495 MRI.replaceRegWith(From, To);
498 // Freeze the set of reserved registers now that MachineFrameInfo has been
499 // set up. All the information required by getReservedRegs() should be
501 MRI.freezeReservedRegs(*MF);
503 // Release function-specific state. SDB and CurDAG are already cleared
510 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
511 BasicBlock::const_iterator End,
513 // Lower all of the non-terminator instructions. If a call is emitted
514 // as a tail call, cease emitting nodes for this block. Terminators
515 // are handled below.
516 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
519 // Make sure the root of the DAG is up-to-date.
520 CurDAG->setRoot(SDB->getControlRoot());
521 HadTailCall = SDB->HasTailCall;
524 // Final step, emit the lowered DAG as machine code.
528 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
529 SmallPtrSet<SDNode*, 128> VisitedNodes;
530 SmallVector<SDNode*, 128> Worklist;
532 Worklist.push_back(CurDAG->getRoot().getNode());
538 SDNode *N = Worklist.pop_back_val();
540 // If we've already seen this node, ignore it.
541 if (!VisitedNodes.insert(N))
544 // Otherwise, add all chain operands to the worklist.
545 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
546 if (N->getOperand(i).getValueType() == MVT::Other)
547 Worklist.push_back(N->getOperand(i).getNode());
549 // If this is a CopyToReg with a vreg dest, process it.
550 if (N->getOpcode() != ISD::CopyToReg)
553 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
554 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
557 // Ignore non-scalar or non-integer values.
558 SDValue Src = N->getOperand(2);
559 EVT SrcVT = Src.getValueType();
560 if (!SrcVT.isInteger() || SrcVT.isVector())
563 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
564 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
565 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
566 } while (!Worklist.empty());
569 void SelectionDAGISel::CodeGenAndEmitDAG() {
570 std::string GroupName;
571 if (TimePassesIsEnabled)
572 GroupName = "Instruction Selection and Scheduling";
573 std::string BlockName;
574 int BlockNumber = -1;
577 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
578 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
582 BlockNumber = FuncInfo->MBB->getNumber();
583 BlockName = MF->getName().str() + ":" +
584 FuncInfo->MBB->getBasicBlock()->getName().str();
586 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
587 << " '" << BlockName << "'\n"; CurDAG->dump());
589 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
591 // Run the DAG combiner in pre-legalize mode.
593 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
594 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
597 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
598 << " '" << BlockName << "'\n"; CurDAG->dump());
600 // Second step, hack on the DAG until it only uses operations and types that
601 // the target supports.
602 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
607 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
608 Changed = CurDAG->LegalizeTypes();
611 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
612 << " '" << BlockName << "'\n"; CurDAG->dump());
615 if (ViewDAGCombineLT)
616 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
618 // Run the DAG combiner in post-type-legalize mode.
620 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
621 TimePassesIsEnabled);
622 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
625 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
626 << " '" << BlockName << "'\n"; CurDAG->dump());
631 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
632 Changed = CurDAG->LegalizeVectors();
637 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
638 CurDAG->LegalizeTypes();
641 if (ViewDAGCombineLT)
642 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
644 // Run the DAG combiner in post-type-legalize mode.
646 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
647 TimePassesIsEnabled);
648 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
651 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
652 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
655 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
658 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
662 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
663 << " '" << BlockName << "'\n"; CurDAG->dump());
665 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
667 // Run the DAG combiner in post-legalize mode.
669 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
670 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
673 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
674 << " '" << BlockName << "'\n"; CurDAG->dump());
676 if (OptLevel != CodeGenOpt::None)
677 ComputeLiveOutVRegInfo();
679 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
681 // Third, instruction select all of the operations to machine code, adding the
682 // code to the MachineBasicBlock.
684 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
685 DoInstructionSelection();
688 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
689 << " '" << BlockName << "'\n"; CurDAG->dump());
691 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
693 // Schedule machine code.
694 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
696 NamedRegionTimer T("Instruction Scheduling", GroupName,
697 TimePassesIsEnabled);
698 Scheduler->Run(CurDAG, FuncInfo->MBB);
701 if (ViewSUnitDAGs) Scheduler->viewGraph();
703 // Emit machine code to BB. This can change 'BB' to the last block being
705 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
707 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
709 // FuncInfo->InsertPt is passed by reference and set to the end of the
710 // scheduled instructions.
711 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
714 // If the block was split, make sure we update any references that are used to
715 // update PHI nodes later on.
716 if (FirstMBB != LastMBB)
717 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
719 // Free the scheduler state.
721 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
722 TimePassesIsEnabled);
726 // Free the SelectionDAG state, now that we're finished with it.
731 /// ISelUpdater - helper class to handle updates of the instruction selection
733 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
734 SelectionDAG::allnodes_iterator &ISelPosition;
736 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
737 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
739 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
740 /// deleted is the current ISelPosition node, update ISelPosition.
742 virtual void NodeDeleted(SDNode *N, SDNode *E) {
743 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
747 } // end anonymous namespace
749 void SelectionDAGISel::DoInstructionSelection() {
750 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
751 << FuncInfo->MBB->getNumber()
752 << " '" << FuncInfo->MBB->getName() << "'\n");
756 // Select target instructions for the DAG.
758 // Number all nodes with a topological order and set DAGSize.
759 DAGSize = CurDAG->AssignTopologicalOrder();
761 // Create a dummy node (which is not added to allnodes), that adds
762 // a reference to the root node, preventing it from being deleted,
763 // and tracking any changes of the root.
764 HandleSDNode Dummy(CurDAG->getRoot());
765 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
768 // Make sure that ISelPosition gets properly updated when nodes are deleted
769 // in calls made from this function.
770 ISelUpdater ISU(*CurDAG, ISelPosition);
772 // The AllNodes list is now topological-sorted. Visit the
773 // nodes by starting at the end of the list (the root of the
774 // graph) and preceding back toward the beginning (the entry
776 while (ISelPosition != CurDAG->allnodes_begin()) {
777 SDNode *Node = --ISelPosition;
778 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
779 // but there are currently some corner cases that it misses. Also, this
780 // makes it theoretically possible to disable the DAGCombiner.
781 if (Node->use_empty())
784 SDNode *ResNode = Select(Node);
786 // FIXME: This is pretty gross. 'Select' should be changed to not return
787 // anything at all and this code should be nuked with a tactical strike.
789 // If node should not be replaced, continue with the next one.
790 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
794 ReplaceUses(Node, ResNode);
797 // If after the replacement this node is not used any more,
798 // remove this dead node.
799 if (Node->use_empty()) // Don't delete EntryToken, etc.
800 CurDAG->RemoveDeadNode(Node);
803 CurDAG->setRoot(Dummy.getValue());
806 DEBUG(dbgs() << "===== Instruction selection ends:\n");
808 PostprocessISelDAG();
811 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
812 /// do other setup for EH landing-pad blocks.
813 void SelectionDAGISel::PrepareEHLandingPad() {
814 MachineBasicBlock *MBB = FuncInfo->MBB;
816 // Add a label to mark the beginning of the landing pad. Deletion of the
817 // landing pad can thus be detected via the MachineModuleInfo.
818 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
820 // Assign the call site to the landing pad's begin label.
821 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
823 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
824 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
827 // Mark exception register as live in.
828 unsigned Reg = TLI.getExceptionPointerRegister();
829 if (Reg) MBB->addLiveIn(Reg);
831 // Mark exception selector register as live in.
832 Reg = TLI.getExceptionSelectorRegister();
833 if (Reg) MBB->addLiveIn(Reg);
836 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
837 /// side-effect free and is either dead or folded into a generated instruction.
838 /// Return false if it needs to be emitted.
839 static bool isFoldedOrDeadInstruction(const Instruction *I,
840 FunctionLoweringInfo *FuncInfo) {
841 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
842 !isa<TerminatorInst>(I) && // Terminators aren't folded.
843 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
844 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
845 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
849 // Collect per Instruction statistics for fast-isel misses. Only those
850 // instructions that cause the bail are accounted for. It does not account for
851 // instructions higher in the block. Thus, summing the per instructions stats
852 // will not add up to what is reported by NumFastIselFailures.
853 static void collectFailStats(const Instruction *I) {
854 switch (I->getOpcode()) {
855 default: assert (0 && "<Invalid operator> ");
858 case Instruction::Ret: NumFastIselFailRet++; return;
859 case Instruction::Br: NumFastIselFailBr++; return;
860 case Instruction::Switch: NumFastIselFailSwitch++; return;
861 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
862 case Instruction::Invoke: NumFastIselFailInvoke++; return;
863 case Instruction::Resume: NumFastIselFailResume++; return;
864 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
866 // Standard binary operators...
867 case Instruction::Add: NumFastIselFailAdd++; return;
868 case Instruction::FAdd: NumFastIselFailFAdd++; return;
869 case Instruction::Sub: NumFastIselFailSub++; return;
870 case Instruction::FSub: NumFastIselFailFSub++; return;
871 case Instruction::Mul: NumFastIselFailMul++; return;
872 case Instruction::FMul: NumFastIselFailFMul++; return;
873 case Instruction::UDiv: NumFastIselFailUDiv++; return;
874 case Instruction::SDiv: NumFastIselFailSDiv++; return;
875 case Instruction::FDiv: NumFastIselFailFDiv++; return;
876 case Instruction::URem: NumFastIselFailURem++; return;
877 case Instruction::SRem: NumFastIselFailSRem++; return;
878 case Instruction::FRem: NumFastIselFailFRem++; return;
880 // Logical operators...
881 case Instruction::And: NumFastIselFailAnd++; return;
882 case Instruction::Or: NumFastIselFailOr++; return;
883 case Instruction::Xor: NumFastIselFailXor++; return;
885 // Memory instructions...
886 case Instruction::Alloca: NumFastIselFailAlloca++; return;
887 case Instruction::Load: NumFastIselFailLoad++; return;
888 case Instruction::Store: NumFastIselFailStore++; return;
889 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
890 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
891 case Instruction::Fence: NumFastIselFailFence++; return;
892 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
894 // Convert instructions...
895 case Instruction::Trunc: NumFastIselFailTrunc++; return;
896 case Instruction::ZExt: NumFastIselFailZExt++; return;
897 case Instruction::SExt: NumFastIselFailSExt++; return;
898 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
899 case Instruction::FPExt: NumFastIselFailFPExt++; return;
900 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
901 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
902 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
903 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
904 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
905 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
906 case Instruction::BitCast: NumFastIselFailBitCast++; return;
908 // Other instructions...
909 case Instruction::ICmp: NumFastIselFailICmp++; return;
910 case Instruction::FCmp: NumFastIselFailFCmp++; return;
911 case Instruction::PHI: NumFastIselFailPHI++; return;
912 case Instruction::Select: NumFastIselFailSelect++; return;
913 case Instruction::Call: NumFastIselFailCall++; return;
914 case Instruction::Shl: NumFastIselFailShl++; return;
915 case Instruction::LShr: NumFastIselFailLShr++; return;
916 case Instruction::AShr: NumFastIselFailAShr++; return;
917 case Instruction::VAArg: NumFastIselFailVAArg++; return;
918 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
919 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
920 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
921 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
922 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
923 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
928 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
929 // Initialize the Fast-ISel state, if needed.
930 FastISel *FastIS = 0;
931 if (TM.Options.EnableFastISel)
932 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
934 // Iterate over all basic blocks in the function.
935 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
936 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
937 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
938 const BasicBlock *LLVMBB = *I;
940 if (OptLevel != CodeGenOpt::None) {
941 bool AllPredsVisited = true;
942 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
944 if (!FuncInfo->VisitedBBs.count(*PI)) {
945 AllPredsVisited = false;
950 if (AllPredsVisited) {
951 for (BasicBlock::const_iterator I = LLVMBB->begin();
952 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
953 FuncInfo->ComputePHILiveOutRegInfo(PN);
955 for (BasicBlock::const_iterator I = LLVMBB->begin();
956 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
957 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
960 FuncInfo->VisitedBBs.insert(LLVMBB);
963 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
964 BasicBlock::const_iterator const End = LLVMBB->end();
965 BasicBlock::const_iterator BI = End;
967 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
968 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
970 // Setup an EH landing-pad block.
971 if (FuncInfo->MBB->isLandingPad())
972 PrepareEHLandingPad();
974 // Before doing SelectionDAG ISel, see if FastISel has been requested.
976 FastIS->startNewBlock();
978 // Emit code for any incoming arguments. This must happen before
979 // beginning FastISel on the entry block.
980 if (LLVMBB == &Fn.getEntryBlock()) {
983 // Lower any arguments needed in this block if this is the entry block.
984 if (!FastIS->LowerArguments()) {
985 // Fast isel failed to lower these arguments
986 ++NumFastIselFailLowerArguments;
987 if (EnableFastISelAbortArgs)
988 llvm_unreachable("FastISel didn't lower all arguments");
990 // Use SelectionDAG argument lowering
992 CurDAG->setRoot(SDB->getControlRoot());
997 // If we inserted any instructions at the beginning, make a note of
998 // where they are, so we can be sure to emit subsequent instructions
1000 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1001 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1003 FastIS->setLastLocalValue(0);
1006 unsigned NumFastIselRemaining = std::distance(Begin, End);
1007 // Do FastISel on as many instructions as possible.
1008 for (; BI != Begin; --BI) {
1009 const Instruction *Inst = llvm::prior(BI);
1011 // If we no longer require this instruction, skip it.
1012 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1013 --NumFastIselRemaining;
1017 // Bottom-up: reset the insert pos at the top, after any local-value
1019 FastIS->recomputeInsertPt();
1021 // Try to select the instruction with FastISel.
1022 if (FastIS->SelectInstruction(Inst)) {
1023 --NumFastIselRemaining;
1024 ++NumFastIselSuccess;
1025 // If fast isel succeeded, skip over all the folded instructions, and
1026 // then see if there is a load right before the selected instructions.
1027 // Try to fold the load if so.
1028 const Instruction *BeforeInst = Inst;
1029 while (BeforeInst != Begin) {
1030 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1031 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1034 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1035 BeforeInst->hasOneUse() &&
1036 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1037 // If we succeeded, don't re-select the load.
1038 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1039 --NumFastIselRemaining;
1040 ++NumFastIselSuccess;
1046 if (EnableFastISelVerbose2)
1047 collectFailStats(Inst);
1050 // Then handle certain instructions as single-LLVM-Instruction blocks.
1051 if (isa<CallInst>(Inst)) {
1053 if (EnableFastISelVerbose || EnableFastISelAbort) {
1054 dbgs() << "FastISel missed call: ";
1058 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1059 unsigned &R = FuncInfo->ValueMap[Inst];
1061 R = FuncInfo->CreateRegs(Inst->getType());
1064 bool HadTailCall = false;
1065 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1066 SelectBasicBlock(Inst, BI, HadTailCall);
1068 // If the call was emitted as a tail call, we're done with the block.
1069 // We also need to delete any previously emitted instructions.
1071 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1076 // Recompute NumFastIselRemaining as Selection DAG instruction
1077 // selection may have handled the call, input args, etc.
1078 unsigned RemainingNow = std::distance(Begin, BI);
1079 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1080 NumFastIselRemaining = RemainingNow;
1084 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1085 // Don't abort, and use a different message for terminator misses.
1086 NumFastIselFailures += NumFastIselRemaining;
1087 if (EnableFastISelVerbose || EnableFastISelAbort) {
1088 dbgs() << "FastISel missed terminator: ";
1092 NumFastIselFailures += NumFastIselRemaining;
1093 if (EnableFastISelVerbose || EnableFastISelAbort) {
1094 dbgs() << "FastISel miss: ";
1097 if (EnableFastISelAbort)
1098 // The "fast" selector couldn't handle something and bailed.
1099 // For the purpose of debugging, just abort.
1100 llvm_unreachable("FastISel didn't select the entire block");
1105 FastIS->recomputeInsertPt();
1107 // Lower any arguments needed in this block if this is the entry block.
1108 if (LLVMBB == &Fn.getEntryBlock()) {
1117 ++NumFastIselBlocks;
1120 // Run SelectionDAG instruction selection on the remainder of the block
1121 // not handled by FastISel. If FastISel is not run, this is the entire
1124 SelectBasicBlock(Begin, BI, HadTailCall);
1128 FuncInfo->PHINodesToUpdate.clear();
1132 SDB->clearDanglingDebugInfo();
1136 SelectionDAGISel::FinishBasicBlock() {
1138 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1139 << FuncInfo->PHINodesToUpdate.size() << "\n";
1140 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1141 dbgs() << "Node " << i << " : ("
1142 << FuncInfo->PHINodesToUpdate[i].first
1143 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1145 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1146 // PHI nodes in successors.
1147 if (SDB->SwitchCases.empty() &&
1148 SDB->JTCases.empty() &&
1149 SDB->BitTestCases.empty()) {
1150 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1151 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1152 assert(PHI->isPHI() &&
1153 "This is not a machine PHI node that we are updating!");
1154 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1156 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1161 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1162 // Lower header first, if it wasn't already lowered
1163 if (!SDB->BitTestCases[i].Emitted) {
1164 // Set the current basic block to the mbb we wish to insert the code into
1165 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1166 FuncInfo->InsertPt = FuncInfo->MBB->end();
1168 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1169 CurDAG->setRoot(SDB->getRoot());
1171 CodeGenAndEmitDAG();
1174 uint32_t UnhandledWeight = 0;
1175 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1176 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1178 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1179 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1180 // Set the current basic block to the mbb we wish to insert the code into
1181 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1182 FuncInfo->InsertPt = FuncInfo->MBB->end();
1185 SDB->visitBitTestCase(SDB->BitTestCases[i],
1186 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1188 SDB->BitTestCases[i].Reg,
1189 SDB->BitTestCases[i].Cases[j],
1192 SDB->visitBitTestCase(SDB->BitTestCases[i],
1193 SDB->BitTestCases[i].Default,
1195 SDB->BitTestCases[i].Reg,
1196 SDB->BitTestCases[i].Cases[j],
1200 CurDAG->setRoot(SDB->getRoot());
1202 CodeGenAndEmitDAG();
1206 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1208 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1209 MachineBasicBlock *PHIBB = PHI->getParent();
1210 assert(PHI->isPHI() &&
1211 "This is not a machine PHI node that we are updating!");
1212 // This is "default" BB. We have two jumps to it. From "header" BB and
1213 // from last "case" BB.
1214 if (PHIBB == SDB->BitTestCases[i].Default)
1215 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1216 .addMBB(SDB->BitTestCases[i].Parent)
1217 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1218 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1219 // One of "cases" BB.
1220 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1222 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1223 if (cBB->isSuccessor(PHIBB))
1224 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1228 SDB->BitTestCases.clear();
1230 // If the JumpTable record is filled in, then we need to emit a jump table.
1231 // Updating the PHI nodes is tricky in this case, since we need to determine
1232 // whether the PHI is a successor of the range check MBB or the jump table MBB
1233 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1234 // Lower header first, if it wasn't already lowered
1235 if (!SDB->JTCases[i].first.Emitted) {
1236 // Set the current basic block to the mbb we wish to insert the code into
1237 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1238 FuncInfo->InsertPt = FuncInfo->MBB->end();
1240 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1242 CurDAG->setRoot(SDB->getRoot());
1244 CodeGenAndEmitDAG();
1247 // Set the current basic block to the mbb we wish to insert the code into
1248 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1249 FuncInfo->InsertPt = FuncInfo->MBB->end();
1251 SDB->visitJumpTable(SDB->JTCases[i].second);
1252 CurDAG->setRoot(SDB->getRoot());
1254 CodeGenAndEmitDAG();
1257 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1259 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1260 MachineBasicBlock *PHIBB = PHI->getParent();
1261 assert(PHI->isPHI() &&
1262 "This is not a machine PHI node that we are updating!");
1263 // "default" BB. We can go there only from header BB.
1264 if (PHIBB == SDB->JTCases[i].second.Default)
1265 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1266 .addMBB(SDB->JTCases[i].first.HeaderBB);
1267 // JT BB. Just iterate over successors here
1268 if (FuncInfo->MBB->isSuccessor(PHIBB))
1269 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1272 SDB->JTCases.clear();
1274 // If the switch block involved a branch to one of the actual successors, we
1275 // need to update PHI nodes in that block.
1276 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1277 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1278 assert(PHI->isPHI() &&
1279 "This is not a machine PHI node that we are updating!");
1280 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1281 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1284 // If we generated any switch lowering information, build and codegen any
1285 // additional DAGs necessary.
1286 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1287 // Set the current basic block to the mbb we wish to insert the code into
1288 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1289 FuncInfo->InsertPt = FuncInfo->MBB->end();
1291 // Determine the unique successors.
1292 SmallVector<MachineBasicBlock *, 2> Succs;
1293 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1294 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1295 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1297 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1298 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1299 CurDAG->setRoot(SDB->getRoot());
1301 CodeGenAndEmitDAG();
1303 // Remember the last block, now that any splitting is done, for use in
1304 // populating PHI nodes in successors.
1305 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1307 // Handle any PHI nodes in successors of this chunk, as if we were coming
1308 // from the original BB before switch expansion. Note that PHI nodes can
1309 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1310 // handle them the right number of times.
1311 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1312 FuncInfo->MBB = Succs[i];
1313 FuncInfo->InsertPt = FuncInfo->MBB->end();
1314 // FuncInfo->MBB may have been removed from the CFG if a branch was
1316 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1317 for (MachineBasicBlock::iterator
1318 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1319 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1320 MachineInstrBuilder PHI(*MF, MBBI);
1321 // This value for this PHI node is recorded in PHINodesToUpdate.
1322 for (unsigned pn = 0; ; ++pn) {
1323 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1324 "Didn't find PHI entry!");
1325 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1326 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1334 SDB->SwitchCases.clear();
1338 /// Create the scheduler. If a specific scheduler was specified
1339 /// via the SchedulerRegistry, use it, otherwise select the
1340 /// one preferred by the target.
1342 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1343 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1347 RegisterScheduler::setDefault(Ctor);
1350 return Ctor(this, OptLevel);
1353 //===----------------------------------------------------------------------===//
1354 // Helper functions used by the generated instruction selector.
1355 //===----------------------------------------------------------------------===//
1356 // Calls to these methods are generated by tblgen.
1358 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1359 /// the dag combiner simplified the 255, we still want to match. RHS is the
1360 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1361 /// specified in the .td file (e.g. 255).
1362 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1363 int64_t DesiredMaskS) const {
1364 const APInt &ActualMask = RHS->getAPIntValue();
1365 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1367 // If the actual mask exactly matches, success!
1368 if (ActualMask == DesiredMask)
1371 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1372 if (ActualMask.intersects(~DesiredMask))
1375 // Otherwise, the DAG Combiner may have proven that the value coming in is
1376 // either already zero or is not demanded. Check for known zero input bits.
1377 APInt NeededMask = DesiredMask & ~ActualMask;
1378 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1381 // TODO: check to see if missing bits are just not demanded.
1383 // Otherwise, this pattern doesn't match.
1387 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1388 /// the dag combiner simplified the 255, we still want to match. RHS is the
1389 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1390 /// specified in the .td file (e.g. 255).
1391 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1392 int64_t DesiredMaskS) const {
1393 const APInt &ActualMask = RHS->getAPIntValue();
1394 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1396 // If the actual mask exactly matches, success!
1397 if (ActualMask == DesiredMask)
1400 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1401 if (ActualMask.intersects(~DesiredMask))
1404 // Otherwise, the DAG Combiner may have proven that the value coming in is
1405 // either already zero or is not demanded. Check for known zero input bits.
1406 APInt NeededMask = DesiredMask & ~ActualMask;
1408 APInt KnownZero, KnownOne;
1409 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1411 // If all the missing bits in the or are already known to be set, match!
1412 if ((NeededMask & KnownOne) == NeededMask)
1415 // TODO: check to see if missing bits are just not demanded.
1417 // Otherwise, this pattern doesn't match.
1422 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1423 /// by tblgen. Others should not call it.
1424 void SelectionDAGISel::
1425 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1426 std::vector<SDValue> InOps;
1427 std::swap(InOps, Ops);
1429 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1430 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1431 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1432 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1434 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1435 if (InOps[e-1].getValueType() == MVT::Glue)
1436 --e; // Don't process a glue operand if it is here.
1439 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1440 if (!InlineAsm::isMemKind(Flags)) {
1441 // Just skip over this operand, copying the operands verbatim.
1442 Ops.insert(Ops.end(), InOps.begin()+i,
1443 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1444 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1446 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1447 "Memory operand with multiple values?");
1448 // Otherwise, this is a memory operand. Ask the target to select it.
1449 std::vector<SDValue> SelOps;
1450 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1451 report_fatal_error("Could not match memory address. Inline asm"
1454 // Add this to the output node.
1456 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1457 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1458 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1463 // Add the glue input back if present.
1464 if (e != InOps.size())
1465 Ops.push_back(InOps.back());
1468 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1471 static SDNode *findGlueUse(SDNode *N) {
1472 unsigned FlagResNo = N->getNumValues()-1;
1473 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1474 SDUse &Use = I.getUse();
1475 if (Use.getResNo() == FlagResNo)
1476 return Use.getUser();
1481 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1482 /// This function recursively traverses up the operand chain, ignoring
1484 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1485 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1486 bool IgnoreChains) {
1487 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1488 // greater than all of its (recursive) operands. If we scan to a point where
1489 // 'use' is smaller than the node we're scanning for, then we know we will
1492 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1493 // happen because we scan down to newly selected nodes in the case of glue
1495 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1498 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1499 // won't fail if we scan it again.
1500 if (!Visited.insert(Use))
1503 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1504 // Ignore chain uses, they are validated by HandleMergeInputChains.
1505 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1508 SDNode *N = Use->getOperand(i).getNode();
1510 if (Use == ImmedUse || Use == Root)
1511 continue; // We are not looking for immediate use.
1516 // Traverse up the operand chain.
1517 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1523 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1524 /// operand node N of U during instruction selection that starts at Root.
1525 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1526 SDNode *Root) const {
1527 if (OptLevel == CodeGenOpt::None) return false;
1528 return N.hasOneUse();
1531 /// IsLegalToFold - Returns true if the specific operand node N of
1532 /// U can be folded during instruction selection that starts at Root.
1533 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1534 CodeGenOpt::Level OptLevel,
1535 bool IgnoreChains) {
1536 if (OptLevel == CodeGenOpt::None) return false;
1538 // If Root use can somehow reach N through a path that that doesn't contain
1539 // U then folding N would create a cycle. e.g. In the following
1540 // diagram, Root can reach N through X. If N is folded into into Root, then
1541 // X is both a predecessor and a successor of U.
1552 // * indicates nodes to be folded together.
1554 // If Root produces glue, then it gets (even more) interesting. Since it
1555 // will be "glued" together with its glue use in the scheduler, we need to
1556 // check if it might reach N.
1575 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1576 // (call it Fold), then X is a predecessor of GU and a successor of
1577 // Fold. But since Fold and GU are glued together, this will create
1578 // a cycle in the scheduling graph.
1580 // If the node has glue, walk down the graph to the "lowest" node in the
1582 EVT VT = Root->getValueType(Root->getNumValues()-1);
1583 while (VT == MVT::Glue) {
1584 SDNode *GU = findGlueUse(Root);
1588 VT = Root->getValueType(Root->getNumValues()-1);
1590 // If our query node has a glue result with a use, we've walked up it. If
1591 // the user (which has already been selected) has a chain or indirectly uses
1592 // the chain, our WalkChainUsers predicate will not consider it. Because of
1593 // this, we cannot ignore chains in this predicate.
1594 IgnoreChains = false;
1598 SmallPtrSet<SDNode*, 16> Visited;
1599 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1602 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1603 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1604 SelectInlineAsmMemoryOperands(Ops);
1606 EVT VTs[] = { MVT::Other, MVT::Glue };
1607 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1608 VTs, &Ops[0], Ops.size());
1610 return New.getNode();
1613 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1614 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1617 /// GetVBR - decode a vbr encoding whose top bit is set.
1618 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1619 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1620 assert(Val >= 128 && "Not a VBR");
1621 Val &= 127; // Remove first vbr bit.
1626 NextBits = MatcherTable[Idx++];
1627 Val |= (NextBits&127) << Shift;
1629 } while (NextBits & 128);
1635 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1636 /// interior glue and chain results to use the new glue and chain results.
1637 void SelectionDAGISel::
1638 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1639 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1641 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1642 bool isMorphNodeTo) {
1643 SmallVector<SDNode*, 4> NowDeadNodes;
1645 // Now that all the normal results are replaced, we replace the chain and
1646 // glue results if present.
1647 if (!ChainNodesMatched.empty()) {
1648 assert(InputChain.getNode() != 0 &&
1649 "Matched input chains but didn't produce a chain");
1650 // Loop over all of the nodes we matched that produced a chain result.
1651 // Replace all the chain results with the final chain we ended up with.
1652 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1653 SDNode *ChainNode = ChainNodesMatched[i];
1655 // If this node was already deleted, don't look at it.
1656 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1659 // Don't replace the results of the root node if we're doing a
1661 if (ChainNode == NodeToMatch && isMorphNodeTo)
1664 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1665 if (ChainVal.getValueType() == MVT::Glue)
1666 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1667 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1668 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1670 // If the node became dead and we haven't already seen it, delete it.
1671 if (ChainNode->use_empty() &&
1672 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1673 NowDeadNodes.push_back(ChainNode);
1677 // If the result produces glue, update any glue results in the matched
1678 // pattern with the glue result.
1679 if (InputGlue.getNode() != 0) {
1680 // Handle any interior nodes explicitly marked.
1681 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1682 SDNode *FRN = GlueResultNodesMatched[i];
1684 // If this node was already deleted, don't look at it.
1685 if (FRN->getOpcode() == ISD::DELETED_NODE)
1688 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1689 "Doesn't have a glue result");
1690 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1693 // If the node became dead and we haven't already seen it, delete it.
1694 if (FRN->use_empty() &&
1695 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1696 NowDeadNodes.push_back(FRN);
1700 if (!NowDeadNodes.empty())
1701 CurDAG->RemoveDeadNodes(NowDeadNodes);
1703 DEBUG(dbgs() << "ISEL: Match complete!\n");
1709 CR_LeadsToInteriorNode
1712 /// WalkChainUsers - Walk down the users of the specified chained node that is
1713 /// part of the pattern we're matching, looking at all of the users we find.
1714 /// This determines whether something is an interior node, whether we have a
1715 /// non-pattern node in between two pattern nodes (which prevent folding because
1716 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1717 /// between pattern nodes (in which case the TF becomes part of the pattern).
1719 /// The walk we do here is guaranteed to be small because we quickly get down to
1720 /// already selected nodes "below" us.
1722 WalkChainUsers(const SDNode *ChainedNode,
1723 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1724 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1725 ChainResult Result = CR_Simple;
1727 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1728 E = ChainedNode->use_end(); UI != E; ++UI) {
1729 // Make sure the use is of the chain, not some other value we produce.
1730 if (UI.getUse().getValueType() != MVT::Other) continue;
1734 // If we see an already-selected machine node, then we've gone beyond the
1735 // pattern that we're selecting down into the already selected chunk of the
1737 if (User->isMachineOpcode() ||
1738 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1741 unsigned UserOpcode = User->getOpcode();
1742 if (UserOpcode == ISD::CopyToReg ||
1743 UserOpcode == ISD::CopyFromReg ||
1744 UserOpcode == ISD::INLINEASM ||
1745 UserOpcode == ISD::EH_LABEL ||
1746 UserOpcode == ISD::LIFETIME_START ||
1747 UserOpcode == ISD::LIFETIME_END) {
1748 // If their node ID got reset to -1 then they've already been selected.
1749 // Treat them like a MachineOpcode.
1750 if (User->getNodeId() == -1)
1754 // If we have a TokenFactor, we handle it specially.
1755 if (User->getOpcode() != ISD::TokenFactor) {
1756 // If the node isn't a token factor and isn't part of our pattern, then it
1757 // must be a random chained node in between two nodes we're selecting.
1758 // This happens when we have something like:
1763 // Because we structurally match the load/store as a read/modify/write,
1764 // but the call is chained between them. We cannot fold in this case
1765 // because it would induce a cycle in the graph.
1766 if (!std::count(ChainedNodesInPattern.begin(),
1767 ChainedNodesInPattern.end(), User))
1768 return CR_InducesCycle;
1770 // Otherwise we found a node that is part of our pattern. For example in:
1774 // This would happen when we're scanning down from the load and see the
1775 // store as a user. Record that there is a use of ChainedNode that is
1776 // part of the pattern and keep scanning uses.
1777 Result = CR_LeadsToInteriorNode;
1778 InteriorChainedNodes.push_back(User);
1782 // If we found a TokenFactor, there are two cases to consider: first if the
1783 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1784 // uses of the TF are in our pattern) we just want to ignore it. Second,
1785 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1791 // | \ DAG's like cheese
1794 // [TokenFactor] [Op]
1801 // In this case, the TokenFactor becomes part of our match and we rewrite it
1802 // as a new TokenFactor.
1804 // To distinguish these two cases, do a recursive walk down the uses.
1805 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1807 // If the uses of the TokenFactor are just already-selected nodes, ignore
1808 // it, it is "below" our pattern.
1810 case CR_InducesCycle:
1811 // If the uses of the TokenFactor lead to nodes that are not part of our
1812 // pattern that are not selected, folding would turn this into a cycle,
1814 return CR_InducesCycle;
1815 case CR_LeadsToInteriorNode:
1816 break; // Otherwise, keep processing.
1819 // Okay, we know we're in the interesting interior case. The TokenFactor
1820 // is now going to be considered part of the pattern so that we rewrite its
1821 // uses (it may have uses that are not part of the pattern) with the
1822 // ultimate chain result of the generated code. We will also add its chain
1823 // inputs as inputs to the ultimate TokenFactor we create.
1824 Result = CR_LeadsToInteriorNode;
1825 ChainedNodesInPattern.push_back(User);
1826 InteriorChainedNodes.push_back(User);
1833 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1834 /// operation for when the pattern matched at least one node with a chains. The
1835 /// input vector contains a list of all of the chained nodes that we match. We
1836 /// must determine if this is a valid thing to cover (i.e. matching it won't
1837 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1838 /// be used as the input node chain for the generated nodes.
1840 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1841 SelectionDAG *CurDAG) {
1842 // Walk all of the chained nodes we've matched, recursively scanning down the
1843 // users of the chain result. This adds any TokenFactor nodes that are caught
1844 // in between chained nodes to the chained and interior nodes list.
1845 SmallVector<SDNode*, 3> InteriorChainedNodes;
1846 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1847 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1848 InteriorChainedNodes) == CR_InducesCycle)
1849 return SDValue(); // Would induce a cycle.
1852 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1853 // that we are interested in. Form our input TokenFactor node.
1854 SmallVector<SDValue, 3> InputChains;
1855 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1856 // Add the input chain of this node to the InputChains list (which will be
1857 // the operands of the generated TokenFactor) if it's not an interior node.
1858 SDNode *N = ChainNodesMatched[i];
1859 if (N->getOpcode() != ISD::TokenFactor) {
1860 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1863 // Otherwise, add the input chain.
1864 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1865 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1866 InputChains.push_back(InChain);
1870 // If we have a token factor, we want to add all inputs of the token factor
1871 // that are not part of the pattern we're matching.
1872 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1873 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1874 N->getOperand(op).getNode()))
1875 InputChains.push_back(N->getOperand(op));
1880 if (InputChains.size() == 1)
1881 return InputChains[0];
1882 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
1883 MVT::Other, &InputChains[0], InputChains.size());
1886 /// MorphNode - Handle morphing a node in place for the selector.
1887 SDNode *SelectionDAGISel::
1888 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1889 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1890 // It is possible we're using MorphNodeTo to replace a node with no
1891 // normal results with one that has a normal result (or we could be
1892 // adding a chain) and the input could have glue and chains as well.
1893 // In this case we need to shift the operands down.
1894 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1895 // than the old isel though.
1896 int OldGlueResultNo = -1, OldChainResultNo = -1;
1898 unsigned NTMNumResults = Node->getNumValues();
1899 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1900 OldGlueResultNo = NTMNumResults-1;
1901 if (NTMNumResults != 1 &&
1902 Node->getValueType(NTMNumResults-2) == MVT::Other)
1903 OldChainResultNo = NTMNumResults-2;
1904 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1905 OldChainResultNo = NTMNumResults-1;
1907 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1908 // that this deletes operands of the old node that become dead.
1909 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1911 // MorphNodeTo can operate in two ways: if an existing node with the
1912 // specified operands exists, it can just return it. Otherwise, it
1913 // updates the node in place to have the requested operands.
1915 // If we updated the node in place, reset the node ID. To the isel,
1916 // this should be just like a newly allocated machine node.
1920 unsigned ResNumResults = Res->getNumValues();
1921 // Move the glue if needed.
1922 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1923 (unsigned)OldGlueResultNo != ResNumResults-1)
1924 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1925 SDValue(Res, ResNumResults-1));
1927 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1930 // Move the chain reference if needed.
1931 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1932 (unsigned)OldChainResultNo != ResNumResults-1)
1933 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1934 SDValue(Res, ResNumResults-1));
1936 // Otherwise, no replacement happened because the node already exists. Replace
1937 // Uses of the old node with the new one.
1939 CurDAG->ReplaceAllUsesWith(Node, Res);
1944 /// CheckSame - Implements OP_CheckSame.
1945 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1946 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1948 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1949 // Accept if it is exactly the same as a previously recorded node.
1950 unsigned RecNo = MatcherTable[MatcherIndex++];
1951 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1952 return N == RecordedNodes[RecNo].first;
1955 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1956 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1957 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1958 const SelectionDAGISel &SDISel) {
1959 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1962 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1963 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1964 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1965 const SelectionDAGISel &SDISel, SDNode *N) {
1966 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1969 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1970 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1972 uint16_t Opc = MatcherTable[MatcherIndex++];
1973 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1974 return N->getOpcode() == Opc;
1977 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1978 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1979 SDValue N, const TargetLowering &TLI) {
1980 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1981 if (N.getValueType() == VT) return true;
1983 // Handle the case when VT is iPTR.
1984 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1987 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1988 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1989 SDValue N, const TargetLowering &TLI,
1991 if (ChildNo >= N.getNumOperands())
1992 return false; // Match fails if out of range child #.
1993 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1997 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1998 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2000 return cast<CondCodeSDNode>(N)->get() ==
2001 (ISD::CondCode)MatcherTable[MatcherIndex++];
2004 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2005 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2006 SDValue N, const TargetLowering &TLI) {
2007 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2008 if (cast<VTSDNode>(N)->getVT() == VT)
2011 // Handle the case when VT is iPTR.
2012 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2015 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2016 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2018 int64_t Val = MatcherTable[MatcherIndex++];
2020 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2022 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2023 return C != 0 && C->getSExtValue() == Val;
2026 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2027 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2028 SDValue N, const SelectionDAGISel &SDISel) {
2029 int64_t Val = MatcherTable[MatcherIndex++];
2031 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2033 if (N->getOpcode() != ISD::AND) return false;
2035 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2036 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2039 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2040 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2041 SDValue N, const SelectionDAGISel &SDISel) {
2042 int64_t Val = MatcherTable[MatcherIndex++];
2044 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2046 if (N->getOpcode() != ISD::OR) return false;
2048 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2049 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2052 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2053 /// scope, evaluate the current node. If the current predicate is known to
2054 /// fail, set Result=true and return anything. If the current predicate is
2055 /// known to pass, set Result=false and return the MatcherIndex to continue
2056 /// with. If the current predicate is unknown, set Result=false and return the
2057 /// MatcherIndex to continue with.
2058 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2059 unsigned Index, SDValue N,
2061 const SelectionDAGISel &SDISel,
2062 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2063 switch (Table[Index++]) {
2066 return Index-1; // Could not evaluate this predicate.
2067 case SelectionDAGISel::OPC_CheckSame:
2068 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2070 case SelectionDAGISel::OPC_CheckPatternPredicate:
2071 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2073 case SelectionDAGISel::OPC_CheckPredicate:
2074 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2076 case SelectionDAGISel::OPC_CheckOpcode:
2077 Result = !::CheckOpcode(Table, Index, N.getNode());
2079 case SelectionDAGISel::OPC_CheckType:
2080 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2082 case SelectionDAGISel::OPC_CheckChild0Type:
2083 case SelectionDAGISel::OPC_CheckChild1Type:
2084 case SelectionDAGISel::OPC_CheckChild2Type:
2085 case SelectionDAGISel::OPC_CheckChild3Type:
2086 case SelectionDAGISel::OPC_CheckChild4Type:
2087 case SelectionDAGISel::OPC_CheckChild5Type:
2088 case SelectionDAGISel::OPC_CheckChild6Type:
2089 case SelectionDAGISel::OPC_CheckChild7Type:
2090 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2091 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2093 case SelectionDAGISel::OPC_CheckCondCode:
2094 Result = !::CheckCondCode(Table, Index, N);
2096 case SelectionDAGISel::OPC_CheckValueType:
2097 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2099 case SelectionDAGISel::OPC_CheckInteger:
2100 Result = !::CheckInteger(Table, Index, N);
2102 case SelectionDAGISel::OPC_CheckAndImm:
2103 Result = !::CheckAndImm(Table, Index, N, SDISel);
2105 case SelectionDAGISel::OPC_CheckOrImm:
2106 Result = !::CheckOrImm(Table, Index, N, SDISel);
2114 /// FailIndex - If this match fails, this is the index to continue with.
2117 /// NodeStack - The node stack when the scope was formed.
2118 SmallVector<SDValue, 4> NodeStack;
2120 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2121 unsigned NumRecordedNodes;
2123 /// NumMatchedMemRefs - The number of matched memref entries.
2124 unsigned NumMatchedMemRefs;
2126 /// InputChain/InputGlue - The current chain/glue
2127 SDValue InputChain, InputGlue;
2129 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2130 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2135 SDNode *SelectionDAGISel::
2136 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2137 unsigned TableSize) {
2138 // FIXME: Should these even be selected? Handle these cases in the caller?
2139 switch (NodeToMatch->getOpcode()) {
2142 case ISD::EntryToken: // These nodes remain the same.
2143 case ISD::BasicBlock:
2145 case ISD::RegisterMask:
2146 //case ISD::VALUETYPE:
2147 //case ISD::CONDCODE:
2148 case ISD::HANDLENODE:
2149 case ISD::MDNODE_SDNODE:
2150 case ISD::TargetConstant:
2151 case ISD::TargetConstantFP:
2152 case ISD::TargetConstantPool:
2153 case ISD::TargetFrameIndex:
2154 case ISD::TargetExternalSymbol:
2155 case ISD::TargetBlockAddress:
2156 case ISD::TargetJumpTable:
2157 case ISD::TargetGlobalTLSAddress:
2158 case ISD::TargetGlobalAddress:
2159 case ISD::TokenFactor:
2160 case ISD::CopyFromReg:
2161 case ISD::CopyToReg:
2163 case ISD::LIFETIME_START:
2164 case ISD::LIFETIME_END:
2165 NodeToMatch->setNodeId(-1); // Mark selected.
2167 case ISD::AssertSext:
2168 case ISD::AssertZext:
2169 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2170 NodeToMatch->getOperand(0));
2172 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2173 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2176 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2178 // Set up the node stack with NodeToMatch as the only node on the stack.
2179 SmallVector<SDValue, 8> NodeStack;
2180 SDValue N = SDValue(NodeToMatch, 0);
2181 NodeStack.push_back(N);
2183 // MatchScopes - Scopes used when matching, if a match failure happens, this
2184 // indicates where to continue checking.
2185 SmallVector<MatchScope, 8> MatchScopes;
2187 // RecordedNodes - This is the set of nodes that have been recorded by the
2188 // state machine. The second value is the parent of the node, or null if the
2189 // root is recorded.
2190 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2192 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2194 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2196 // These are the current input chain and glue for use when generating nodes.
2197 // Various Emit operations change these. For example, emitting a copytoreg
2198 // uses and updates these.
2199 SDValue InputChain, InputGlue;
2201 // ChainNodesMatched - If a pattern matches nodes that have input/output
2202 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2203 // which ones they are. The result is captured into this list so that we can
2204 // update the chain results when the pattern is complete.
2205 SmallVector<SDNode*, 3> ChainNodesMatched;
2206 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2208 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2209 NodeToMatch->dump(CurDAG);
2212 // Determine where to start the interpreter. Normally we start at opcode #0,
2213 // but if the state machine starts with an OPC_SwitchOpcode, then we
2214 // accelerate the first lookup (which is guaranteed to be hot) with the
2215 // OpcodeOffset table.
2216 unsigned MatcherIndex = 0;
2218 if (!OpcodeOffset.empty()) {
2219 // Already computed the OpcodeOffset table, just index into it.
2220 if (N.getOpcode() < OpcodeOffset.size())
2221 MatcherIndex = OpcodeOffset[N.getOpcode()];
2222 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2224 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2225 // Otherwise, the table isn't computed, but the state machine does start
2226 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2227 // is the first time we're selecting an instruction.
2230 // Get the size of this case.
2231 unsigned CaseSize = MatcherTable[Idx++];
2233 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2234 if (CaseSize == 0) break;
2236 // Get the opcode, add the index to the table.
2237 uint16_t Opc = MatcherTable[Idx++];
2238 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2239 if (Opc >= OpcodeOffset.size())
2240 OpcodeOffset.resize((Opc+1)*2);
2241 OpcodeOffset[Opc] = Idx;
2245 // Okay, do the lookup for the first opcode.
2246 if (N.getOpcode() < OpcodeOffset.size())
2247 MatcherIndex = OpcodeOffset[N.getOpcode()];
2251 assert(MatcherIndex < TableSize && "Invalid index");
2253 unsigned CurrentOpcodeIndex = MatcherIndex;
2255 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2258 // Okay, the semantics of this operation are that we should push a scope
2259 // then evaluate the first child. However, pushing a scope only to have
2260 // the first check fail (which then pops it) is inefficient. If we can
2261 // determine immediately that the first check (or first several) will
2262 // immediately fail, don't even bother pushing a scope for them.
2266 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2267 if (NumToSkip & 128)
2268 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2269 // Found the end of the scope with no match.
2270 if (NumToSkip == 0) {
2275 FailIndex = MatcherIndex+NumToSkip;
2277 unsigned MatcherIndexOfPredicate = MatcherIndex;
2278 (void)MatcherIndexOfPredicate; // silence warning.
2280 // If we can't evaluate this predicate without pushing a scope (e.g. if
2281 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2282 // push the scope and evaluate the full predicate chain.
2284 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2285 Result, *this, RecordedNodes);
2289 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2290 << "index " << MatcherIndexOfPredicate
2291 << ", continuing at " << FailIndex << "\n");
2292 ++NumDAGIselRetries;
2294 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2295 // move to the next case.
2296 MatcherIndex = FailIndex;
2299 // If the whole scope failed to match, bail.
2300 if (FailIndex == 0) break;
2302 // Push a MatchScope which indicates where to go if the first child fails
2304 MatchScope NewEntry;
2305 NewEntry.FailIndex = FailIndex;
2306 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2307 NewEntry.NumRecordedNodes = RecordedNodes.size();
2308 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2309 NewEntry.InputChain = InputChain;
2310 NewEntry.InputGlue = InputGlue;
2311 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2312 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2313 MatchScopes.push_back(NewEntry);
2316 case OPC_RecordNode: {
2317 // Remember this node, it may end up being an operand in the pattern.
2319 if (NodeStack.size() > 1)
2320 Parent = NodeStack[NodeStack.size()-2].getNode();
2321 RecordedNodes.push_back(std::make_pair(N, Parent));
2325 case OPC_RecordChild0: case OPC_RecordChild1:
2326 case OPC_RecordChild2: case OPC_RecordChild3:
2327 case OPC_RecordChild4: case OPC_RecordChild5:
2328 case OPC_RecordChild6: case OPC_RecordChild7: {
2329 unsigned ChildNo = Opcode-OPC_RecordChild0;
2330 if (ChildNo >= N.getNumOperands())
2331 break; // Match fails if out of range child #.
2333 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2337 case OPC_RecordMemRef:
2338 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2341 case OPC_CaptureGlueInput:
2342 // If the current node has an input glue, capture it in InputGlue.
2343 if (N->getNumOperands() != 0 &&
2344 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2345 InputGlue = N->getOperand(N->getNumOperands()-1);
2348 case OPC_MoveChild: {
2349 unsigned ChildNo = MatcherTable[MatcherIndex++];
2350 if (ChildNo >= N.getNumOperands())
2351 break; // Match fails if out of range child #.
2352 N = N.getOperand(ChildNo);
2353 NodeStack.push_back(N);
2357 case OPC_MoveParent:
2358 // Pop the current node off the NodeStack.
2359 NodeStack.pop_back();
2360 assert(!NodeStack.empty() && "Node stack imbalance!");
2361 N = NodeStack.back();
2365 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2367 case OPC_CheckPatternPredicate:
2368 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2370 case OPC_CheckPredicate:
2371 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2375 case OPC_CheckComplexPat: {
2376 unsigned CPNum = MatcherTable[MatcherIndex++];
2377 unsigned RecNo = MatcherTable[MatcherIndex++];
2378 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2379 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2380 RecordedNodes[RecNo].first, CPNum,
2385 case OPC_CheckOpcode:
2386 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2390 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2393 case OPC_SwitchOpcode: {
2394 unsigned CurNodeOpcode = N.getOpcode();
2395 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2398 // Get the size of this case.
2399 CaseSize = MatcherTable[MatcherIndex++];
2401 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2402 if (CaseSize == 0) break;
2404 uint16_t Opc = MatcherTable[MatcherIndex++];
2405 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2407 // If the opcode matches, then we will execute this case.
2408 if (CurNodeOpcode == Opc)
2411 // Otherwise, skip over this case.
2412 MatcherIndex += CaseSize;
2415 // If no cases matched, bail out.
2416 if (CaseSize == 0) break;
2418 // Otherwise, execute the case we found.
2419 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2420 << " to " << MatcherIndex << "\n");
2424 case OPC_SwitchType: {
2425 MVT CurNodeVT = N.getValueType().getSimpleVT();
2426 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2429 // Get the size of this case.
2430 CaseSize = MatcherTable[MatcherIndex++];
2432 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2433 if (CaseSize == 0) break;
2435 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2436 if (CaseVT == MVT::iPTR)
2437 CaseVT = TLI.getPointerTy();
2439 // If the VT matches, then we will execute this case.
2440 if (CurNodeVT == CaseVT)
2443 // Otherwise, skip over this case.
2444 MatcherIndex += CaseSize;
2447 // If no cases matched, bail out.
2448 if (CaseSize == 0) break;
2450 // Otherwise, execute the case we found.
2451 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2452 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2455 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2456 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2457 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2458 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2459 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2460 Opcode-OPC_CheckChild0Type))
2463 case OPC_CheckCondCode:
2464 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2466 case OPC_CheckValueType:
2467 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2469 case OPC_CheckInteger:
2470 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2472 case OPC_CheckAndImm:
2473 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2475 case OPC_CheckOrImm:
2476 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2479 case OPC_CheckFoldableChainNode: {
2480 assert(NodeStack.size() != 1 && "No parent node");
2481 // Verify that all intermediate nodes between the root and this one have
2483 bool HasMultipleUses = false;
2484 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2485 if (!NodeStack[i].hasOneUse()) {
2486 HasMultipleUses = true;
2489 if (HasMultipleUses) break;
2491 // Check to see that the target thinks this is profitable to fold and that
2492 // we can fold it without inducing cycles in the graph.
2493 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2495 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2496 NodeToMatch, OptLevel,
2497 true/*We validate our own chains*/))
2502 case OPC_EmitInteger: {
2503 MVT::SimpleValueType VT =
2504 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2505 int64_t Val = MatcherTable[MatcherIndex++];
2507 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2508 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2509 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2512 case OPC_EmitRegister: {
2513 MVT::SimpleValueType VT =
2514 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2515 unsigned RegNo = MatcherTable[MatcherIndex++];
2516 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2517 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2520 case OPC_EmitRegister2: {
2521 // For targets w/ more than 256 register names, the register enum
2522 // values are stored in two bytes in the matcher table (just like
2524 MVT::SimpleValueType VT =
2525 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2526 unsigned RegNo = MatcherTable[MatcherIndex++];
2527 RegNo |= MatcherTable[MatcherIndex++] << 8;
2528 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2529 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2533 case OPC_EmitConvertToTarget: {
2534 // Convert from IMM/FPIMM to target version.
2535 unsigned RecNo = MatcherTable[MatcherIndex++];
2536 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2537 SDValue Imm = RecordedNodes[RecNo].first;
2539 if (Imm->getOpcode() == ISD::Constant) {
2540 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2541 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2542 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2543 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2544 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2547 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2551 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2552 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2553 // These are space-optimized forms of OPC_EmitMergeInputChains.
2554 assert(InputChain.getNode() == 0 &&
2555 "EmitMergeInputChains should be the first chain producing node");
2556 assert(ChainNodesMatched.empty() &&
2557 "Should only have one EmitMergeInputChains per match");
2559 // Read all of the chained nodes.
2560 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2561 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2562 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2564 // FIXME: What if other value results of the node have uses not matched
2566 if (ChainNodesMatched.back() != NodeToMatch &&
2567 !RecordedNodes[RecNo].first.hasOneUse()) {
2568 ChainNodesMatched.clear();
2572 // Merge the input chains if they are not intra-pattern references.
2573 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2575 if (InputChain.getNode() == 0)
2576 break; // Failed to merge.
2580 case OPC_EmitMergeInputChains: {
2581 assert(InputChain.getNode() == 0 &&
2582 "EmitMergeInputChains should be the first chain producing node");
2583 // This node gets a list of nodes we matched in the input that have
2584 // chains. We want to token factor all of the input chains to these nodes
2585 // together. However, if any of the input chains is actually one of the
2586 // nodes matched in this pattern, then we have an intra-match reference.
2587 // Ignore these because the newly token factored chain should not refer to
2589 unsigned NumChains = MatcherTable[MatcherIndex++];
2590 assert(NumChains != 0 && "Can't TF zero chains");
2592 assert(ChainNodesMatched.empty() &&
2593 "Should only have one EmitMergeInputChains per match");
2595 // Read all of the chained nodes.
2596 for (unsigned i = 0; i != NumChains; ++i) {
2597 unsigned RecNo = MatcherTable[MatcherIndex++];
2598 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2599 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2601 // FIXME: What if other value results of the node have uses not matched
2603 if (ChainNodesMatched.back() != NodeToMatch &&
2604 !RecordedNodes[RecNo].first.hasOneUse()) {
2605 ChainNodesMatched.clear();
2610 // If the inner loop broke out, the match fails.
2611 if (ChainNodesMatched.empty())
2614 // Merge the input chains if they are not intra-pattern references.
2615 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2617 if (InputChain.getNode() == 0)
2618 break; // Failed to merge.
2623 case OPC_EmitCopyToReg: {
2624 unsigned RecNo = MatcherTable[MatcherIndex++];
2625 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2626 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2628 if (InputChain.getNode() == 0)
2629 InputChain = CurDAG->getEntryNode();
2631 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2632 DestPhysReg, RecordedNodes[RecNo].first,
2635 InputGlue = InputChain.getValue(1);
2639 case OPC_EmitNodeXForm: {
2640 unsigned XFormNo = MatcherTable[MatcherIndex++];
2641 unsigned RecNo = MatcherTable[MatcherIndex++];
2642 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2643 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2644 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2649 case OPC_MorphNodeTo: {
2650 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2651 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2652 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2653 // Get the result VT list.
2654 unsigned NumVTs = MatcherTable[MatcherIndex++];
2655 SmallVector<EVT, 4> VTs;
2656 for (unsigned i = 0; i != NumVTs; ++i) {
2657 MVT::SimpleValueType VT =
2658 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2659 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2663 if (EmitNodeInfo & OPFL_Chain)
2664 VTs.push_back(MVT::Other);
2665 if (EmitNodeInfo & OPFL_GlueOutput)
2666 VTs.push_back(MVT::Glue);
2668 // This is hot code, so optimize the two most common cases of 1 and 2
2671 if (VTs.size() == 1)
2672 VTList = CurDAG->getVTList(VTs[0]);
2673 else if (VTs.size() == 2)
2674 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2676 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2678 // Get the operand list.
2679 unsigned NumOps = MatcherTable[MatcherIndex++];
2680 SmallVector<SDValue, 8> Ops;
2681 for (unsigned i = 0; i != NumOps; ++i) {
2682 unsigned RecNo = MatcherTable[MatcherIndex++];
2684 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2686 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2687 Ops.push_back(RecordedNodes[RecNo].first);
2690 // If there are variadic operands to add, handle them now.
2691 if (EmitNodeInfo & OPFL_VariadicInfo) {
2692 // Determine the start index to copy from.
2693 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2694 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2695 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2696 "Invalid variadic node");
2697 // Copy all of the variadic operands, not including a potential glue
2699 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2701 SDValue V = NodeToMatch->getOperand(i);
2702 if (V.getValueType() == MVT::Glue) break;
2707 // If this has chain/glue inputs, add them.
2708 if (EmitNodeInfo & OPFL_Chain)
2709 Ops.push_back(InputChain);
2710 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2711 Ops.push_back(InputGlue);
2715 if (Opcode != OPC_MorphNodeTo) {
2716 // If this is a normal EmitNode command, just create the new node and
2717 // add the results to the RecordedNodes list.
2718 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2721 // Add all the non-glue/non-chain results to the RecordedNodes list.
2722 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2723 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2724 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2728 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2729 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2732 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2733 // We will visit the equivalent node later.
2734 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2738 // If the node had chain/glue results, update our notion of the current
2740 if (EmitNodeInfo & OPFL_GlueOutput) {
2741 InputGlue = SDValue(Res, VTs.size()-1);
2742 if (EmitNodeInfo & OPFL_Chain)
2743 InputChain = SDValue(Res, VTs.size()-2);
2744 } else if (EmitNodeInfo & OPFL_Chain)
2745 InputChain = SDValue(Res, VTs.size()-1);
2747 // If the OPFL_MemRefs glue is set on this node, slap all of the
2748 // accumulated memrefs onto it.
2750 // FIXME: This is vastly incorrect for patterns with multiple outputs
2751 // instructions that access memory and for ComplexPatterns that match
2753 if (EmitNodeInfo & OPFL_MemRefs) {
2754 // Only attach load or store memory operands if the generated
2755 // instruction may load or store.
2756 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2757 bool mayLoad = MCID.mayLoad();
2758 bool mayStore = MCID.mayStore();
2760 unsigned NumMemRefs = 0;
2761 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2762 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2763 if ((*I)->isLoad()) {
2766 } else if ((*I)->isStore()) {
2774 MachineSDNode::mmo_iterator MemRefs =
2775 MF->allocateMemRefsArray(NumMemRefs);
2777 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2778 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2779 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2780 if ((*I)->isLoad()) {
2783 } else if ((*I)->isStore()) {
2791 cast<MachineSDNode>(Res)
2792 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2796 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2797 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
2799 // If this was a MorphNodeTo then we're completely done!
2800 if (Opcode == OPC_MorphNodeTo) {
2801 // Update chain and glue uses.
2802 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2803 InputGlue, GlueResultNodesMatched, true);
2810 case OPC_MarkGlueResults: {
2811 unsigned NumNodes = MatcherTable[MatcherIndex++];
2813 // Read and remember all the glue-result nodes.
2814 for (unsigned i = 0; i != NumNodes; ++i) {
2815 unsigned RecNo = MatcherTable[MatcherIndex++];
2817 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2819 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2820 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2825 case OPC_CompleteMatch: {
2826 // The match has been completed, and any new nodes (if any) have been
2827 // created. Patch up references to the matched dag to use the newly
2829 unsigned NumResults = MatcherTable[MatcherIndex++];
2831 for (unsigned i = 0; i != NumResults; ++i) {
2832 unsigned ResSlot = MatcherTable[MatcherIndex++];
2834 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2836 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2837 SDValue Res = RecordedNodes[ResSlot].first;
2839 assert(i < NodeToMatch->getNumValues() &&
2840 NodeToMatch->getValueType(i) != MVT::Other &&
2841 NodeToMatch->getValueType(i) != MVT::Glue &&
2842 "Invalid number of results to complete!");
2843 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2844 NodeToMatch->getValueType(i) == MVT::iPTR ||
2845 Res.getValueType() == MVT::iPTR ||
2846 NodeToMatch->getValueType(i).getSizeInBits() ==
2847 Res.getValueType().getSizeInBits()) &&
2848 "invalid replacement");
2849 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2852 // If the root node defines glue, add it to the glue nodes to update list.
2853 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2854 GlueResultNodesMatched.push_back(NodeToMatch);
2856 // Update chain and glue uses.
2857 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2858 InputGlue, GlueResultNodesMatched, false);
2860 assert(NodeToMatch->use_empty() &&
2861 "Didn't replace all uses of the node?");
2863 // FIXME: We just return here, which interacts correctly with SelectRoot
2864 // above. We should fix this to not return an SDNode* anymore.
2869 // If the code reached this point, then the match failed. See if there is
2870 // another child to try in the current 'Scope', otherwise pop it until we
2871 // find a case to check.
2872 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2873 ++NumDAGIselRetries;
2875 if (MatchScopes.empty()) {
2876 CannotYetSelect(NodeToMatch);
2880 // Restore the interpreter state back to the point where the scope was
2882 MatchScope &LastScope = MatchScopes.back();
2883 RecordedNodes.resize(LastScope.NumRecordedNodes);
2885 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2886 N = NodeStack.back();
2888 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2889 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2890 MatcherIndex = LastScope.FailIndex;
2892 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
2894 InputChain = LastScope.InputChain;
2895 InputGlue = LastScope.InputGlue;
2896 if (!LastScope.HasChainNodesMatched)
2897 ChainNodesMatched.clear();
2898 if (!LastScope.HasGlueResultNodesMatched)
2899 GlueResultNodesMatched.clear();
2901 // Check to see what the offset is at the new MatcherIndex. If it is zero
2902 // we have reached the end of this scope, otherwise we have another child
2903 // in the current scope to try.
2904 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2905 if (NumToSkip & 128)
2906 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2908 // If we have another child in this scope to match, update FailIndex and
2910 if (NumToSkip != 0) {
2911 LastScope.FailIndex = MatcherIndex+NumToSkip;
2915 // End of this scope, pop it and try the next child in the containing
2917 MatchScopes.pop_back();
2924 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2926 raw_string_ostream Msg(msg);
2927 Msg << "Cannot select: ";
2929 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2930 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2931 N->getOpcode() != ISD::INTRINSIC_VOID) {
2932 N->printrFull(Msg, CurDAG);
2933 Msg << "\nIn function: " << MF->getName();
2935 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2937 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2938 if (iid < Intrinsic::num_intrinsics)
2939 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2940 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2941 Msg << "target intrinsic %" << TII->getName(iid);
2943 Msg << "unknown intrinsic #" << iid;
2945 report_fatal_error(Msg.str());
2948 char SelectionDAGISel::ID = 0;