1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/CodeGen/DwarfWriter.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetIntrinsicInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetMachine.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/Timer.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/ADT/Statistic.h"
63 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
64 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
68 cl::desc("Enable verbose messages in the \"fast\" "
69 "instruction selector"));
71 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
72 cl::desc("Enable abort calls when \"fast\" instruction fails"));
74 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
75 cl::desc("Schedule copies of livein registers"),
80 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the first "
84 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
85 cl::desc("Pop up a window to show dags before legalize types"));
87 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
88 cl::desc("Pop up a window to show dags before legalize"));
90 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
91 cl::desc("Pop up a window to show dags before the second "
94 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
95 cl::desc("Pop up a window to show dags before the post legalize types"
96 " dag combine pass"));
98 ViewISelDAGs("view-isel-dags", cl::Hidden,
99 cl::desc("Pop up a window to show isel dags as they are selected"));
101 ViewSchedDAGs("view-sched-dags", cl::Hidden,
102 cl::desc("Pop up a window to show sched dags as they are processed"));
104 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
105 cl::desc("Pop up a window to show SUnit dags after they are processed"));
107 static const bool ViewDAGCombine1 = false,
108 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
109 ViewDAGCombine2 = false,
110 ViewDAGCombineLT = false,
111 ViewISelDAGs = false, ViewSchedDAGs = false,
112 ViewSUnitDAGs = false;
115 //===---------------------------------------------------------------------===//
117 /// RegisterScheduler class - Track the registration of instruction schedulers.
119 //===---------------------------------------------------------------------===//
120 MachinePassRegistry RegisterScheduler::Registry;
122 //===---------------------------------------------------------------------===//
124 /// ISHeuristic command line option for instruction schedulers.
126 //===---------------------------------------------------------------------===//
127 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
128 RegisterPassParser<RegisterScheduler> >
129 ISHeuristic("pre-RA-sched",
130 cl::init(&createDefaultScheduler),
131 cl::desc("Instruction schedulers available (before register"
134 static RegisterScheduler
135 defaultListDAGScheduler("default", "Best scheduler for the target",
136 createDefaultScheduler);
139 //===--------------------------------------------------------------------===//
140 /// createDefaultScheduler - This creates an instruction scheduler appropriate
142 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
143 CodeGenOpt::Level OptLevel) {
144 const TargetLowering &TLI = IS->getTargetLowering();
146 if (OptLevel == CodeGenOpt::None)
147 return createFastDAGScheduler(IS, OptLevel);
148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
149 return createTDListDAGScheduler(IS, OptLevel);
150 assert(TLI.getSchedulingPreference() ==
151 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
152 return createBURRListDAGScheduler(IS, OptLevel);
156 // EmitInstrWithCustomInserter - This method should be implemented by targets
157 // that mark instructions with the 'usesCustomInserter' flag. These
158 // instructions are special in various ways, which require special support to
159 // insert. The specified MachineInstr is created but not inserted into any
160 // basic blocks, and this method is called to expand it into a sequence of
161 // instructions, potentially also creating new basic blocks and control flow.
162 // When new basic blocks are inserted and the edges from MBB to its successors
163 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
165 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
166 MachineBasicBlock *MBB,
167 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
169 dbgs() << "If a target marks an instruction with "
170 "'usesCustomInserter', it must implement "
171 "TargetLowering::EmitInstrWithCustomInserter!";
177 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
178 /// physical register has only a single copy use, then coalesced the copy
180 static void EmitLiveInCopy(MachineBasicBlock *MBB,
181 MachineBasicBlock::iterator &InsertPos,
182 unsigned VirtReg, unsigned PhysReg,
183 const TargetRegisterClass *RC,
184 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
185 const MachineRegisterInfo &MRI,
186 const TargetRegisterInfo &TRI,
187 const TargetInstrInfo &TII) {
188 unsigned NumUses = 0;
189 MachineInstr *UseMI = NULL;
190 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
191 UE = MRI.use_end(); UI != UE; ++UI) {
197 // If the number of uses is not one, or the use is not a move instruction,
198 // don't coalesce. Also, only coalesce away a virtual register to virtual
200 bool Coalesced = false;
201 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
203 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
204 TargetRegisterInfo::isVirtualRegister(DstReg)) {
209 // Now find an ideal location to insert the copy.
210 MachineBasicBlock::iterator Pos = InsertPos;
211 while (Pos != MBB->begin()) {
212 MachineInstr *PrevMI = prior(Pos);
213 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
214 // copyRegToReg might emit multiple instructions to do a copy.
215 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
216 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
217 // This is what the BB looks like right now:
222 // We want to insert "r1025 = mov r1". Inserting this copy below the
223 // move to r1024 makes it impossible for that move to be coalesced.
230 break; // Woot! Found a good location.
234 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
235 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
238 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
240 if (&*InsertPos == UseMI) ++InsertPos;
245 /// EmitLiveInCopies - If this is the first basic block in the function,
246 /// and if it has live ins that need to be copied into vregs, emit the
247 /// copies into the block.
248 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
249 const MachineRegisterInfo &MRI,
250 const TargetRegisterInfo &TRI,
251 const TargetInstrInfo &TII) {
252 if (SchedLiveInCopies) {
253 // Emit the copies at a heuristically-determined location in the block.
254 DenseMap<MachineInstr*, unsigned> CopyRegMap;
255 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
256 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
257 E = MRI.livein_end(); LI != E; ++LI)
259 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
260 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
261 RC, CopyRegMap, MRI, TRI, TII);
264 // Emit the copies into the top of the block.
265 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
266 E = MRI.livein_end(); LI != E; ++LI)
268 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
269 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
270 LI->second, LI->first, RC, RC);
271 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
277 //===----------------------------------------------------------------------===//
278 // SelectionDAGISel code
279 //===----------------------------------------------------------------------===//
281 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
282 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
283 FuncInfo(new FunctionLoweringInfo(TLI)),
284 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
285 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
291 SelectionDAGISel::~SelectionDAGISel() {
297 unsigned SelectionDAGISel::MakeReg(EVT VT) {
298 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
301 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
302 AU.addRequired<AliasAnalysis>();
303 AU.addPreserved<AliasAnalysis>();
304 AU.addRequired<GCModuleInfo>();
305 AU.addPreserved<GCModuleInfo>();
306 AU.addRequired<DwarfWriter>();
307 AU.addPreserved<DwarfWriter>();
308 MachineFunctionPass::getAnalysisUsage(AU);
311 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
312 Function &Fn = *mf.getFunction();
314 // Do some sanity-checking on the command-line options.
315 assert((!EnableFastISelVerbose || EnableFastISel) &&
316 "-fast-isel-verbose requires -fast-isel");
317 assert((!EnableFastISelAbort || EnableFastISel) &&
318 "-fast-isel-abort requires -fast-isel");
320 // Get alias analysis for load/store combining.
321 AA = &getAnalysis<AliasAnalysis>();
324 const TargetInstrInfo &TII = *TM.getInstrInfo();
325 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
328 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
331 RegInfo = &MF->getRegInfo();
332 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
334 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
335 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
336 CurDAG->init(*MF, MMI, DW);
337 FuncInfo->set(Fn, *MF, EnableFastISel);
340 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
341 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
343 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
345 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
347 // If the first basic block in the function has live ins that need to be
348 // copied into vregs, emit the copies into the top of the block before
349 // emitting the code for the block.
350 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
352 // Add function live-ins to entry block live-in set.
353 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
354 E = RegInfo->livein_end(); I != E; ++I)
355 MF->begin()->addLiveIn(I->first);
358 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
359 "Not all catch info was assigned to a landing pad!");
367 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
368 /// attached with this instruction.
369 static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB,
370 FastISel *FastIS, MachineFunction *MF) {
371 DebugLoc DL = I->getDebugLoc();
372 if (DL.isUnknown()) return;
374 SDB->setCurDebugLoc(DL);
377 FastIS->setCurDebugLoc(DL);
379 // If the function doesn't have a default debug location yet, set
380 // it. This is kind of a hack.
381 if (MF->getDefaultDebugLoc().isUnknown())
382 MF->setDefaultDebugLoc(DL);
385 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
386 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
387 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc());
389 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc());
392 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
393 BasicBlock::iterator Begin,
394 BasicBlock::iterator End,
396 SDB->setCurrentBasicBlock(BB);
398 // Lower all of the non-terminator instructions. If a call is emitted
399 // as a tail call, cease emitting nodes for this block.
400 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
401 SetDebugLoc(I, SDB, 0, MF);
403 if (!isa<TerminatorInst>(I)) {
406 // Set the current debug location back to "unknown" so that it doesn't
407 // spuriously apply to subsequent instructions.
408 ResetDebugLoc(SDB, 0);
412 if (!SDB->HasTailCall) {
413 // Ensure that all instructions which are used outside of their defining
414 // blocks are available as virtual registers. Invoke is handled elsewhere.
415 for (BasicBlock::iterator I = Begin; I != End; ++I)
416 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
417 SDB->CopyToExportRegsIfNeeded(I);
419 // Handle PHI nodes in successor blocks.
420 if (End == LLVMBB->end()) {
421 HandlePHINodesInSuccessorBlocks(LLVMBB);
423 // Lower the terminator after the copies are emitted.
424 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF);
425 SDB->visit(*LLVMBB->getTerminator());
426 ResetDebugLoc(SDB, 0);
430 // Make sure the root of the DAG is up-to-date.
431 CurDAG->setRoot(SDB->getControlRoot());
433 // Final step, emit the lowered DAG as machine code.
435 HadTailCall = SDB->HasTailCall;
440 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
441 /// nodes from the worklist.
442 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
443 SmallVector<SDNode*, 128> &Worklist;
444 SmallPtrSet<SDNode*, 128> &InWorklist;
446 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
447 SmallPtrSet<SDNode*, 128> &inwl)
448 : Worklist(wl), InWorklist(inwl) {}
450 void RemoveFromWorklist(SDNode *N) {
451 if (!InWorklist.erase(N)) return;
453 SmallVector<SDNode*, 128>::iterator I =
454 std::find(Worklist.begin(), Worklist.end(), N);
455 assert(I != Worklist.end() && "Not in worklist");
457 *I = Worklist.back();
461 virtual void NodeDeleted(SDNode *N, SDNode *E) {
462 RemoveFromWorklist(N);
465 virtual void NodeUpdated(SDNode *N) {
471 /// TrivialTruncElim - Eliminate some trivial nops that can result from
472 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
473 static bool TrivialTruncElim(SDValue Op,
474 TargetLowering::TargetLoweringOpt &TLO) {
475 SDValue N0 = Op.getOperand(0);
476 EVT VT = Op.getValueType();
477 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
478 N0.getOpcode() == ISD::SIGN_EXTEND ||
479 N0.getOpcode() == ISD::ANY_EXTEND) &&
480 N0.getOperand(0).getValueType() == VT) {
481 return TLO.CombineTo(Op, N0.getOperand(0));
486 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
487 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
488 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
489 void SelectionDAGISel::ShrinkDemandedOps() {
490 SmallVector<SDNode*, 128> Worklist;
491 SmallPtrSet<SDNode*, 128> InWorklist;
493 // Add all the dag nodes to the worklist.
494 Worklist.reserve(CurDAG->allnodes_size());
495 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
496 E = CurDAG->allnodes_end(); I != E; ++I) {
497 Worklist.push_back(I);
498 InWorklist.insert(I);
501 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
502 while (!Worklist.empty()) {
503 SDNode *N = Worklist.pop_back_val();
506 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
507 // Deleting this node may make its operands dead, add them to the worklist
508 // if they aren't already there.
509 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
510 if (InWorklist.insert(N->getOperand(i).getNode()))
511 Worklist.push_back(N->getOperand(i).getNode());
513 CurDAG->DeleteNode(N);
517 // Run ShrinkDemandedOp on scalar binary operations.
518 if (N->getNumValues() != 1 ||
519 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
522 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
523 APInt Demanded = APInt::getAllOnesValue(BitWidth);
524 APInt KnownZero, KnownOne;
525 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
526 KnownZero, KnownOne, TLO) &&
527 (N->getOpcode() != ISD::TRUNCATE ||
528 !TrivialTruncElim(SDValue(N, 0), TLO)))
532 assert(!InWorklist.count(N) && "Already in worklist");
533 Worklist.push_back(N);
534 InWorklist.insert(N);
536 // Replace the old value with the new one.
537 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
538 TLO.Old.getNode()->dump(CurDAG);
539 errs() << "\nWith: ";
540 TLO.New.getNode()->dump(CurDAG);
543 if (InWorklist.insert(TLO.New.getNode()))
544 Worklist.push_back(TLO.New.getNode());
546 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
547 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
549 if (!TLO.Old.getNode()->use_empty()) continue;
551 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
553 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
554 if (OpNode->hasOneUse()) {
555 // Add OpNode to the end of the list to revisit.
556 DeadNodes.RemoveFromWorklist(OpNode);
557 Worklist.push_back(OpNode);
558 InWorklist.insert(OpNode);
562 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
563 CurDAG->DeleteNode(TLO.Old.getNode());
567 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
568 SmallPtrSet<SDNode*, 128> VisitedNodes;
569 SmallVector<SDNode*, 128> Worklist;
571 Worklist.push_back(CurDAG->getRoot().getNode());
578 SDNode *N = Worklist.pop_back_val();
580 // If we've already seen this node, ignore it.
581 if (!VisitedNodes.insert(N))
584 // Otherwise, add all chain operands to the worklist.
585 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
586 if (N->getOperand(i).getValueType() == MVT::Other)
587 Worklist.push_back(N->getOperand(i).getNode());
589 // If this is a CopyToReg with a vreg dest, process it.
590 if (N->getOpcode() != ISD::CopyToReg)
593 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
594 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
597 // Ignore non-scalar or non-integer values.
598 SDValue Src = N->getOperand(2);
599 EVT SrcVT = Src.getValueType();
600 if (!SrcVT.isInteger() || SrcVT.isVector())
603 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
604 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
605 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
607 // Only install this information if it tells us something.
608 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
609 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
610 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
611 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
612 FunctionLoweringInfo::LiveOutInfo &LOI =
613 FuncInfo->LiveOutRegInfo[DestReg];
614 LOI.NumSignBits = NumSignBits;
615 LOI.KnownOne = KnownOne;
616 LOI.KnownZero = KnownZero;
618 } while (!Worklist.empty());
621 void SelectionDAGISel::CodeGenAndEmitDAG() {
622 std::string GroupName;
623 if (TimePassesIsEnabled)
624 GroupName = "Instruction Selection and Scheduling";
625 std::string BlockName;
626 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
627 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
629 BlockName = MF->getFunction()->getNameStr() + ":" +
630 BB->getBasicBlock()->getNameStr();
632 DEBUG(dbgs() << "Initial selection DAG:\n");
633 DEBUG(CurDAG->dump());
635 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
637 // Run the DAG combiner in pre-legalize mode.
638 if (TimePassesIsEnabled) {
639 NamedRegionTimer T("DAG Combining 1", GroupName);
640 CurDAG->Combine(Unrestricted, *AA, OptLevel);
642 CurDAG->Combine(Unrestricted, *AA, OptLevel);
645 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
646 DEBUG(CurDAG->dump());
648 // Second step, hack on the DAG until it only uses operations and types that
649 // the target supports.
650 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
654 if (TimePassesIsEnabled) {
655 NamedRegionTimer T("Type Legalization", GroupName);
656 Changed = CurDAG->LegalizeTypes();
658 Changed = CurDAG->LegalizeTypes();
661 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
662 DEBUG(CurDAG->dump());
665 if (ViewDAGCombineLT)
666 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
668 // Run the DAG combiner in post-type-legalize mode.
669 if (TimePassesIsEnabled) {
670 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
671 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
673 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
676 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
677 DEBUG(CurDAG->dump());
680 if (TimePassesIsEnabled) {
681 NamedRegionTimer T("Vector Legalization", GroupName);
682 Changed = CurDAG->LegalizeVectors();
684 Changed = CurDAG->LegalizeVectors();
688 if (TimePassesIsEnabled) {
689 NamedRegionTimer T("Type Legalization 2", GroupName);
690 CurDAG->LegalizeTypes();
692 CurDAG->LegalizeTypes();
695 if (ViewDAGCombineLT)
696 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
698 // Run the DAG combiner in post-type-legalize mode.
699 if (TimePassesIsEnabled) {
700 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
701 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
703 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
706 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
707 DEBUG(CurDAG->dump());
710 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
712 if (TimePassesIsEnabled) {
713 NamedRegionTimer T("DAG Legalization", GroupName);
714 CurDAG->Legalize(OptLevel);
716 CurDAG->Legalize(OptLevel);
719 DEBUG(dbgs() << "Legalized selection DAG:\n");
720 DEBUG(CurDAG->dump());
722 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
724 // Run the DAG combiner in post-legalize mode.
725 if (TimePassesIsEnabled) {
726 NamedRegionTimer T("DAG Combining 2", GroupName);
727 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
729 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
732 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
733 DEBUG(CurDAG->dump());
735 if (OptLevel != CodeGenOpt::None) {
737 ComputeLiveOutVRegInfo();
740 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
742 // Third, instruction select all of the operations to machine code, adding the
743 // code to the MachineBasicBlock.
744 if (TimePassesIsEnabled) {
745 NamedRegionTimer T("Instruction Selection", GroupName);
746 DoInstructionSelection();
748 DoInstructionSelection();
751 DEBUG(dbgs() << "Selected selection DAG:\n");
752 DEBUG(CurDAG->dump());
754 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
756 // Schedule machine code.
757 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
758 if (TimePassesIsEnabled) {
759 NamedRegionTimer T("Instruction Scheduling", GroupName);
760 Scheduler->Run(CurDAG, BB, BB->end());
762 Scheduler->Run(CurDAG, BB, BB->end());
765 if (ViewSUnitDAGs) Scheduler->viewGraph();
767 // Emit machine code to BB. This can change 'BB' to the last block being
769 if (TimePassesIsEnabled) {
770 NamedRegionTimer T("Instruction Creation", GroupName);
771 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
773 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
776 // Free the scheduler state.
777 if (TimePassesIsEnabled) {
778 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
784 DEBUG(dbgs() << "Selected machine code:\n");
788 void SelectionDAGISel::DoInstructionSelection() {
789 DEBUG(errs() << "===== Instruction selection begins:\n");
793 // Select target instructions for the DAG.
795 // Number all nodes with a topological order and set DAGSize.
796 DAGSize = CurDAG->AssignTopologicalOrder();
798 // Create a dummy node (which is not added to allnodes), that adds
799 // a reference to the root node, preventing it from being deleted,
800 // and tracking any changes of the root.
801 HandleSDNode Dummy(CurDAG->getRoot());
802 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
805 // The AllNodes list is now topological-sorted. Visit the
806 // nodes by starting at the end of the list (the root of the
807 // graph) and preceding back toward the beginning (the entry
809 while (ISelPosition != CurDAG->allnodes_begin()) {
810 SDNode *Node = --ISelPosition;
811 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
812 // but there are currently some corner cases that it misses. Also, this
813 // makes it theoretically possible to disable the DAGCombiner.
814 if (Node->use_empty())
817 SDNode *ResNode = Select(Node);
819 // FIXME: This is pretty gross. 'Select' should be changed to not return
820 // anything at all and this code should be nuked with a tactical strike.
822 // If node should not be replaced, continue with the next one.
823 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
827 ReplaceUses(Node, ResNode);
829 // If after the replacement this node is not used any more,
830 // remove this dead node.
831 if (Node->use_empty()) { // Don't delete EntryToken, etc.
832 ISelUpdater ISU(ISelPosition);
833 CurDAG->RemoveDeadNode(Node, &ISU);
837 CurDAG->setRoot(Dummy.getValue());
839 DEBUG(errs() << "===== Instruction selection ends:\n");
841 PostprocessISelDAG();
845 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
847 MachineModuleInfo *MMI,
849 const TargetInstrInfo &TII) {
850 // Initialize the Fast-ISel state, if needed.
851 FastISel *FastIS = 0;
853 FastIS = TLI.createFastISel(MF, MMI, DW,
856 FuncInfo->StaticAllocaMap
858 , FuncInfo->CatchInfoLost
862 // Iterate over all basic blocks in the function.
863 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
864 BasicBlock *LLVMBB = &*I;
865 BB = FuncInfo->MBBMap[LLVMBB];
867 BasicBlock::iterator const Begin = LLVMBB->begin();
868 BasicBlock::iterator const End = LLVMBB->end();
869 BasicBlock::iterator BI = Begin;
871 // Lower any arguments needed in this block if this is the entry block.
872 bool SuppressFastISel = false;
873 if (LLVMBB == &Fn.getEntryBlock()) {
874 LowerArguments(LLVMBB);
876 // If any of the arguments has the byval attribute, forgo
877 // fast-isel in the entry block.
880 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
882 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
883 if (EnableFastISelVerbose || EnableFastISelAbort)
884 dbgs() << "FastISel skips entry block due to byval argument\n";
885 SuppressFastISel = true;
891 if (MMI && BB->isLandingPad()) {
892 // Add a label to mark the beginning of the landing pad. Deletion of the
893 // landing pad can thus be detected via the MachineModuleInfo.
894 MCSymbol *Label = MMI->addLandingPad(BB);
896 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
897 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
899 // Mark exception register as live in.
900 unsigned Reg = TLI.getExceptionAddressRegister();
901 if (Reg) BB->addLiveIn(Reg);
903 // Mark exception selector register as live in.
904 Reg = TLI.getExceptionSelectorRegister();
905 if (Reg) BB->addLiveIn(Reg);
907 // FIXME: Hack around an exception handling flaw (PR1508): the personality
908 // function and list of typeids logically belong to the invoke (or, if you
909 // like, the basic block containing the invoke), and need to be associated
910 // with it in the dwarf exception handling tables. Currently however the
911 // information is provided by an intrinsic (eh.selector) that can be moved
912 // to unexpected places by the optimizers: if the unwind edge is critical,
913 // then breaking it can result in the intrinsics being in the successor of
914 // the landing pad, not the landing pad itself. This results
915 // in exceptions not being caught because no typeids are associated with
916 // the invoke. This may not be the only way things can go wrong, but it
917 // is the only way we try to work around for the moment.
918 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
920 if (Br && Br->isUnconditional()) { // Critical edge?
921 BasicBlock::iterator I, E;
922 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
923 if (isa<EHSelectorInst>(I))
927 // No catch info found - try to extract some from the successor.
928 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
932 // Before doing SelectionDAG ISel, see if FastISel has been requested.
933 if (FastIS && !SuppressFastISel) {
934 // Emit code for any incoming arguments. This must happen before
935 // beginning FastISel on the entry block.
936 if (LLVMBB == &Fn.getEntryBlock()) {
937 CurDAG->setRoot(SDB->getControlRoot());
941 FastIS->startNewBlock(BB);
942 // Do FastISel on as many instructions as possible.
943 for (; BI != End; ++BI) {
944 // Just before the terminator instruction, insert instructions to
945 // feed PHI nodes in successor blocks.
946 if (isa<TerminatorInst>(BI))
947 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
948 ++NumFastIselFailures;
949 ResetDebugLoc(SDB, FastIS);
950 if (EnableFastISelVerbose || EnableFastISelAbort) {
951 dbgs() << "FastISel miss: ";
954 assert(!EnableFastISelAbort &&
955 "FastISel didn't handle a PHI in a successor");
959 SetDebugLoc(BI, SDB, FastIS, &MF);
961 // Try to select the instruction with FastISel.
962 if (FastIS->SelectInstruction(BI)) {
963 ResetDebugLoc(SDB, FastIS);
967 // Clear out the debug location so that it doesn't carry over to
968 // unrelated instructions.
969 ResetDebugLoc(SDB, FastIS);
971 // Then handle certain instructions as single-LLVM-Instruction blocks.
972 if (isa<CallInst>(BI)) {
973 ++NumFastIselFailures;
974 if (EnableFastISelVerbose || EnableFastISelAbort) {
975 dbgs() << "FastISel missed call: ";
979 if (!BI->getType()->isVoidTy()) {
980 unsigned &R = FuncInfo->ValueMap[BI];
982 R = FuncInfo->CreateRegForValue(BI);
985 bool HadTailCall = false;
986 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
988 // If the call was emitted as a tail call, we're done with the block.
994 // If the instruction was codegen'd with multiple blocks,
995 // inform the FastISel object where to resume inserting.
996 FastIS->setCurrentBlock(BB);
1000 // Otherwise, give up on FastISel for the rest of the block.
1001 // For now, be a little lenient about non-branch terminators.
1002 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
1003 ++NumFastIselFailures;
1004 if (EnableFastISelVerbose || EnableFastISelAbort) {
1005 dbgs() << "FastISel miss: ";
1008 if (EnableFastISelAbort)
1009 // The "fast" selector couldn't handle something and bailed.
1010 // For the purpose of debugging, just abort.
1011 llvm_unreachable("FastISel didn't select the entire block");
1017 // Run SelectionDAG instruction selection on the remainder of the block
1018 // not handled by FastISel. If FastISel is not run, this is the entire
1022 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
1032 SelectionDAGISel::FinishBasicBlock() {
1034 DEBUG(dbgs() << "Target-post-processed machine code:\n");
1037 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1038 << SDB->PHINodesToUpdate.size() << "\n");
1039 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
1040 dbgs() << "Node " << i << " : ("
1041 << SDB->PHINodesToUpdate[i].first
1042 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
1044 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1045 // PHI nodes in successors.
1046 if (SDB->SwitchCases.empty() &&
1047 SDB->JTCases.empty() &&
1048 SDB->BitTestCases.empty()) {
1049 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1050 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1051 assert(PHI->isPHI() &&
1052 "This is not a machine PHI node that we are updating!");
1053 if (!BB->isSuccessor(PHI->getParent()))
1055 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1057 PHI->addOperand(MachineOperand::CreateMBB(BB));
1059 SDB->PHINodesToUpdate.clear();
1063 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1064 // Lower header first, if it wasn't already lowered
1065 if (!SDB->BitTestCases[i].Emitted) {
1066 // Set the current basic block to the mbb we wish to insert the code into
1067 BB = SDB->BitTestCases[i].Parent;
1068 SDB->setCurrentBasicBlock(BB);
1070 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
1071 CurDAG->setRoot(SDB->getRoot());
1072 CodeGenAndEmitDAG();
1076 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1077 // Set the current basic block to the mbb we wish to insert the code into
1078 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
1079 SDB->setCurrentBasicBlock(BB);
1082 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1083 SDB->BitTestCases[i].Reg,
1084 SDB->BitTestCases[i].Cases[j]);
1086 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1087 SDB->BitTestCases[i].Reg,
1088 SDB->BitTestCases[i].Cases[j]);
1091 CurDAG->setRoot(SDB->getRoot());
1092 CodeGenAndEmitDAG();
1097 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1098 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1099 MachineBasicBlock *PHIBB = PHI->getParent();
1100 assert(PHI->isPHI() &&
1101 "This is not a machine PHI node that we are updating!");
1102 // This is "default" BB. We have two jumps to it. From "header" BB and
1103 // from last "case" BB.
1104 if (PHIBB == SDB->BitTestCases[i].Default) {
1105 PHI->addOperand(MachineOperand::
1106 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1107 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1108 PHI->addOperand(MachineOperand::
1109 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1110 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1113 // One of "cases" BB.
1114 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1116 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1117 if (cBB->isSuccessor(PHIBB)) {
1118 PHI->addOperand(MachineOperand::
1119 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1120 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1125 SDB->BitTestCases.clear();
1127 // If the JumpTable record is filled in, then we need to emit a jump table.
1128 // Updating the PHI nodes is tricky in this case, since we need to determine
1129 // whether the PHI is a successor of the range check MBB or the jump table MBB
1130 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1131 // Lower header first, if it wasn't already lowered
1132 if (!SDB->JTCases[i].first.Emitted) {
1133 // Set the current basic block to the mbb we wish to insert the code into
1134 BB = SDB->JTCases[i].first.HeaderBB;
1135 SDB->setCurrentBasicBlock(BB);
1137 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1138 CurDAG->setRoot(SDB->getRoot());
1139 CodeGenAndEmitDAG();
1143 // Set the current basic block to the mbb we wish to insert the code into
1144 BB = SDB->JTCases[i].second.MBB;
1145 SDB->setCurrentBasicBlock(BB);
1147 SDB->visitJumpTable(SDB->JTCases[i].second);
1148 CurDAG->setRoot(SDB->getRoot());
1149 CodeGenAndEmitDAG();
1153 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1154 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1155 MachineBasicBlock *PHIBB = PHI->getParent();
1156 assert(PHI->isPHI() &&
1157 "This is not a machine PHI node that we are updating!");
1158 // "default" BB. We can go there only from header BB.
1159 if (PHIBB == SDB->JTCases[i].second.Default) {
1161 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1163 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1165 // JT BB. Just iterate over successors here
1166 if (BB->isSuccessor(PHIBB)) {
1168 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1169 PHI->addOperand(MachineOperand::CreateMBB(BB));
1173 SDB->JTCases.clear();
1175 // If the switch block involved a branch to one of the actual successors, we
1176 // need to update PHI nodes in that block.
1177 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1178 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1179 assert(PHI->isPHI() &&
1180 "This is not a machine PHI node that we are updating!");
1181 if (BB->isSuccessor(PHI->getParent())) {
1182 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1184 PHI->addOperand(MachineOperand::CreateMBB(BB));
1188 // If we generated any switch lowering information, build and codegen any
1189 // additional DAGs necessary.
1190 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1191 // Set the current basic block to the mbb we wish to insert the code into
1192 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1193 SDB->setCurrentBasicBlock(BB);
1196 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1197 CurDAG->setRoot(SDB->getRoot());
1198 CodeGenAndEmitDAG();
1200 // Handle any PHI nodes in successors of this chunk, as if we were coming
1201 // from the original BB before switch expansion. Note that PHI nodes can
1202 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1203 // handle them the right number of times.
1204 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1205 // If new BB's are created during scheduling, the edges may have been
1206 // updated. That is, the edge from ThisBB to BB may have been split and
1207 // BB's predecessor is now another block.
1208 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1209 SDB->EdgeMapping.find(BB);
1210 if (EI != SDB->EdgeMapping.end())
1211 ThisBB = EI->second;
1213 // BB may have been removed from the CFG if a branch was constant folded.
1214 if (ThisBB->isSuccessor(BB)) {
1215 for (MachineBasicBlock::iterator Phi = BB->begin();
1216 Phi != BB->end() && Phi->isPHI();
1218 // This value for this PHI node is recorded in PHINodesToUpdate.
1219 for (unsigned pn = 0; ; ++pn) {
1220 assert(pn != SDB->PHINodesToUpdate.size() &&
1221 "Didn't find PHI entry!");
1222 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1223 Phi->addOperand(MachineOperand::
1224 CreateReg(SDB->PHINodesToUpdate[pn].second,
1226 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1233 // Don't process RHS if same block as LHS.
1234 if (BB == SDB->SwitchCases[i].FalseBB)
1235 SDB->SwitchCases[i].FalseBB = 0;
1237 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1238 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1239 SDB->SwitchCases[i].FalseBB = 0;
1241 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1244 SDB->SwitchCases.clear();
1246 SDB->PHINodesToUpdate.clear();
1250 /// Create the scheduler. If a specific scheduler was specified
1251 /// via the SchedulerRegistry, use it, otherwise select the
1252 /// one preferred by the target.
1254 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1255 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1259 RegisterScheduler::setDefault(Ctor);
1262 return Ctor(this, OptLevel);
1265 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1266 return new ScheduleHazardRecognizer();
1269 //===----------------------------------------------------------------------===//
1270 // Helper functions used by the generated instruction selector.
1271 //===----------------------------------------------------------------------===//
1272 // Calls to these methods are generated by tblgen.
1274 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1275 /// the dag combiner simplified the 255, we still want to match. RHS is the
1276 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1277 /// specified in the .td file (e.g. 255).
1278 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1279 int64_t DesiredMaskS) const {
1280 const APInt &ActualMask = RHS->getAPIntValue();
1281 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1283 // If the actual mask exactly matches, success!
1284 if (ActualMask == DesiredMask)
1287 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1288 if (ActualMask.intersects(~DesiredMask))
1291 // Otherwise, the DAG Combiner may have proven that the value coming in is
1292 // either already zero or is not demanded. Check for known zero input bits.
1293 APInt NeededMask = DesiredMask & ~ActualMask;
1294 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1297 // TODO: check to see if missing bits are just not demanded.
1299 // Otherwise, this pattern doesn't match.
1303 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1304 /// the dag combiner simplified the 255, we still want to match. RHS is the
1305 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1306 /// specified in the .td file (e.g. 255).
1307 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1308 int64_t DesiredMaskS) const {
1309 const APInt &ActualMask = RHS->getAPIntValue();
1310 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1312 // If the actual mask exactly matches, success!
1313 if (ActualMask == DesiredMask)
1316 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1317 if (ActualMask.intersects(~DesiredMask))
1320 // Otherwise, the DAG Combiner may have proven that the value coming in is
1321 // either already zero or is not demanded. Check for known zero input bits.
1322 APInt NeededMask = DesiredMask & ~ActualMask;
1324 APInt KnownZero, KnownOne;
1325 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1327 // If all the missing bits in the or are already known to be set, match!
1328 if ((NeededMask & KnownOne) == NeededMask)
1331 // TODO: check to see if missing bits are just not demanded.
1333 // Otherwise, this pattern doesn't match.
1338 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1339 /// by tblgen. Others should not call it.
1340 void SelectionDAGISel::
1341 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1342 std::vector<SDValue> InOps;
1343 std::swap(InOps, Ops);
1345 Ops.push_back(InOps[0]); // input chain.
1346 Ops.push_back(InOps[1]); // input asm string.
1348 unsigned i = 2, e = InOps.size();
1349 if (InOps[e-1].getValueType() == MVT::Flag)
1350 --e; // Don't process a flag operand if it is here.
1353 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1354 if ((Flags & 7) != 4 /*MEM*/) {
1355 // Just skip over this operand, copying the operands verbatim.
1356 Ops.insert(Ops.end(), InOps.begin()+i,
1357 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1358 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1360 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1361 "Memory operand with multiple values?");
1362 // Otherwise, this is a memory operand. Ask the target to select it.
1363 std::vector<SDValue> SelOps;
1364 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1365 llvm_report_error("Could not match memory address. Inline asm"
1369 // Add this to the output node.
1370 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1372 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1377 // Add the flag input back if present.
1378 if (e != InOps.size())
1379 Ops.push_back(InOps.back());
1382 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1385 static SDNode *findFlagUse(SDNode *N) {
1386 unsigned FlagResNo = N->getNumValues()-1;
1387 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1388 SDUse &Use = I.getUse();
1389 if (Use.getResNo() == FlagResNo)
1390 return Use.getUser();
1395 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1396 /// This function recursively traverses up the operand chain, ignoring
1398 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1399 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1400 bool IgnoreChains) {
1401 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1402 // greater than all of its (recursive) operands. If we scan to a point where
1403 // 'use' is smaller than the node we're scanning for, then we know we will
1406 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1407 // happen because we scan down to newly selected nodes in the case of flag
1409 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1412 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1413 // won't fail if we scan it again.
1414 if (!Visited.insert(Use))
1417 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1418 // Ignore chain uses, they are validated by HandleMergeInputChains.
1419 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1422 SDNode *N = Use->getOperand(i).getNode();
1424 if (Use == ImmedUse || Use == Root)
1425 continue; // We are not looking for immediate use.
1430 // Traverse up the operand chain.
1431 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1437 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1438 /// operand node N of U during instruction selection that starts at Root.
1439 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1440 SDNode *Root) const {
1441 if (OptLevel == CodeGenOpt::None) return false;
1442 return N.hasOneUse();
1445 /// IsLegalToFold - Returns true if the specific operand node N of
1446 /// U can be folded during instruction selection that starts at Root.
1447 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1448 bool IgnoreChains) const {
1449 if (OptLevel == CodeGenOpt::None) return false;
1451 // If Root use can somehow reach N through a path that that doesn't contain
1452 // U then folding N would create a cycle. e.g. In the following
1453 // diagram, Root can reach N through X. If N is folded into into Root, then
1454 // X is both a predecessor and a successor of U.
1465 // * indicates nodes to be folded together.
1467 // If Root produces a flag, then it gets (even more) interesting. Since it
1468 // will be "glued" together with its flag use in the scheduler, we need to
1469 // check if it might reach N.
1488 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1489 // (call it Fold), then X is a predecessor of FU and a successor of
1490 // Fold. But since Fold and FU are flagged together, this will create
1491 // a cycle in the scheduling graph.
1493 // If the node has flags, walk down the graph to the "lowest" node in the
1495 EVT VT = Root->getValueType(Root->getNumValues()-1);
1496 while (VT == MVT::Flag) {
1497 SDNode *FU = findFlagUse(Root);
1501 VT = Root->getValueType(Root->getNumValues()-1);
1503 // If our query node has a flag result with a use, we've walked up it. If
1504 // the user (which has already been selected) has a chain or indirectly uses
1505 // the chain, our WalkChainUsers predicate will not consider it. Because of
1506 // this, we cannot ignore chains in this predicate.
1507 IgnoreChains = false;
1511 SmallPtrSet<SDNode*, 16> Visited;
1512 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1515 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1516 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1517 SelectInlineAsmMemoryOperands(Ops);
1519 std::vector<EVT> VTs;
1520 VTs.push_back(MVT::Other);
1521 VTs.push_back(MVT::Flag);
1522 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1523 VTs, &Ops[0], Ops.size());
1525 return New.getNode();
1528 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1529 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1532 /// GetVBR - decode a vbr encoding whose top bit is set.
1533 ALWAYS_INLINE static uint64_t
1534 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1535 assert(Val >= 128 && "Not a VBR");
1536 Val &= 127; // Remove first vbr bit.
1541 NextBits = MatcherTable[Idx++];
1542 Val |= (NextBits&127) << Shift;
1544 } while (NextBits & 128);
1550 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1551 /// interior flag and chain results to use the new flag and chain results.
1552 void SelectionDAGISel::
1553 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1554 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1556 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1557 bool isMorphNodeTo) {
1558 SmallVector<SDNode*, 4> NowDeadNodes;
1560 ISelUpdater ISU(ISelPosition);
1562 // Now that all the normal results are replaced, we replace the chain and
1563 // flag results if present.
1564 if (!ChainNodesMatched.empty()) {
1565 assert(InputChain.getNode() != 0 &&
1566 "Matched input chains but didn't produce a chain");
1567 // Loop over all of the nodes we matched that produced a chain result.
1568 // Replace all the chain results with the final chain we ended up with.
1569 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1570 SDNode *ChainNode = ChainNodesMatched[i];
1572 // If this node was already deleted, don't look at it.
1573 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1576 // Don't replace the results of the root node if we're doing a
1578 if (ChainNode == NodeToMatch && isMorphNodeTo)
1581 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1582 if (ChainVal.getValueType() == MVT::Flag)
1583 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1584 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1585 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1587 // If the node became dead and we haven't already seen it, delete it.
1588 if (ChainNode->use_empty() &&
1589 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1590 NowDeadNodes.push_back(ChainNode);
1594 // If the result produces a flag, update any flag results in the matched
1595 // pattern with the flag result.
1596 if (InputFlag.getNode() != 0) {
1597 // Handle any interior nodes explicitly marked.
1598 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1599 SDNode *FRN = FlagResultNodesMatched[i];
1601 // If this node was already deleted, don't look at it.
1602 if (FRN->getOpcode() == ISD::DELETED_NODE)
1605 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1606 "Doesn't have a flag result");
1607 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1610 // If the node became dead and we haven't already seen it, delete it.
1611 if (FRN->use_empty() &&
1612 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1613 NowDeadNodes.push_back(FRN);
1617 if (!NowDeadNodes.empty())
1618 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1620 DEBUG(errs() << "ISEL: Match complete!\n");
1626 CR_LeadsToInteriorNode
1629 /// WalkChainUsers - Walk down the users of the specified chained node that is
1630 /// part of the pattern we're matching, looking at all of the users we find.
1631 /// This determines whether something is an interior node, whether we have a
1632 /// non-pattern node in between two pattern nodes (which prevent folding because
1633 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1634 /// between pattern nodes (in which case the TF becomes part of the pattern).
1636 /// The walk we do here is guaranteed to be small because we quickly get down to
1637 /// already selected nodes "below" us.
1639 WalkChainUsers(SDNode *ChainedNode,
1640 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1641 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1642 ChainResult Result = CR_Simple;
1644 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1645 E = ChainedNode->use_end(); UI != E; ++UI) {
1646 // Make sure the use is of the chain, not some other value we produce.
1647 if (UI.getUse().getValueType() != MVT::Other) continue;
1651 // If we see an already-selected machine node, then we've gone beyond the
1652 // pattern that we're selecting down into the already selected chunk of the
1654 if (User->isMachineOpcode() ||
1655 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1658 if (User->getOpcode() == ISD::CopyToReg ||
1659 User->getOpcode() == ISD::CopyFromReg ||
1660 User->getOpcode() == ISD::INLINEASM ||
1661 User->getOpcode() == ISD::EH_LABEL) {
1662 // If their node ID got reset to -1 then they've already been selected.
1663 // Treat them like a MachineOpcode.
1664 if (User->getNodeId() == -1)
1668 // If we have a TokenFactor, we handle it specially.
1669 if (User->getOpcode() != ISD::TokenFactor) {
1670 // If the node isn't a token factor and isn't part of our pattern, then it
1671 // must be a random chained node in between two nodes we're selecting.
1672 // This happens when we have something like:
1677 // Because we structurally match the load/store as a read/modify/write,
1678 // but the call is chained between them. We cannot fold in this case
1679 // because it would induce a cycle in the graph.
1680 if (!std::count(ChainedNodesInPattern.begin(),
1681 ChainedNodesInPattern.end(), User))
1682 return CR_InducesCycle;
1684 // Otherwise we found a node that is part of our pattern. For example in:
1688 // This would happen when we're scanning down from the load and see the
1689 // store as a user. Record that there is a use of ChainedNode that is
1690 // part of the pattern and keep scanning uses.
1691 Result = CR_LeadsToInteriorNode;
1692 InteriorChainedNodes.push_back(User);
1696 // If we found a TokenFactor, there are two cases to consider: first if the
1697 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1698 // uses of the TF are in our pattern) we just want to ignore it. Second,
1699 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1705 // | \ DAG's like cheese
1708 // [TokenFactor] [Op]
1715 // In this case, the TokenFactor becomes part of our match and we rewrite it
1716 // as a new TokenFactor.
1718 // To distinguish these two cases, do a recursive walk down the uses.
1719 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1721 // If the uses of the TokenFactor are just already-selected nodes, ignore
1722 // it, it is "below" our pattern.
1724 case CR_InducesCycle:
1725 // If the uses of the TokenFactor lead to nodes that are not part of our
1726 // pattern that are not selected, folding would turn this into a cycle,
1728 return CR_InducesCycle;
1729 case CR_LeadsToInteriorNode:
1730 break; // Otherwise, keep processing.
1733 // Okay, we know we're in the interesting interior case. The TokenFactor
1734 // is now going to be considered part of the pattern so that we rewrite its
1735 // uses (it may have uses that are not part of the pattern) with the
1736 // ultimate chain result of the generated code. We will also add its chain
1737 // inputs as inputs to the ultimate TokenFactor we create.
1738 Result = CR_LeadsToInteriorNode;
1739 ChainedNodesInPattern.push_back(User);
1740 InteriorChainedNodes.push_back(User);
1747 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1748 /// operation for when the pattern matched at least one node with a chains. The
1749 /// input vector contains a list of all of the chained nodes that we match. We
1750 /// must determine if this is a valid thing to cover (i.e. matching it won't
1751 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1752 /// be used as the input node chain for the generated nodes.
1754 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1755 SelectionDAG *CurDAG) {
1756 // Walk all of the chained nodes we've matched, recursively scanning down the
1757 // users of the chain result. This adds any TokenFactor nodes that are caught
1758 // in between chained nodes to the chained and interior nodes list.
1759 SmallVector<SDNode*, 3> InteriorChainedNodes;
1760 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1761 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1762 InteriorChainedNodes) == CR_InducesCycle)
1763 return SDValue(); // Would induce a cycle.
1766 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1767 // that we are interested in. Form our input TokenFactor node.
1768 SmallVector<SDValue, 3> InputChains;
1769 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1770 // Add the input chain of this node to the InputChains list (which will be
1771 // the operands of the generated TokenFactor) if it's not an interior node.
1772 SDNode *N = ChainNodesMatched[i];
1773 if (N->getOpcode() != ISD::TokenFactor) {
1774 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1777 // Otherwise, add the input chain.
1778 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1779 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1780 InputChains.push_back(InChain);
1784 // If we have a token factor, we want to add all inputs of the token factor
1785 // that are not part of the pattern we're matching.
1786 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1787 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1788 N->getOperand(op).getNode()))
1789 InputChains.push_back(N->getOperand(op));
1794 if (InputChains.size() == 1)
1795 return InputChains[0];
1796 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1797 MVT::Other, &InputChains[0], InputChains.size());
1800 /// MorphNode - Handle morphing a node in place for the selector.
1801 SDNode *SelectionDAGISel::
1802 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1803 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1804 // It is possible we're using MorphNodeTo to replace a node with no
1805 // normal results with one that has a normal result (or we could be
1806 // adding a chain) and the input could have flags and chains as well.
1807 // In this case we need to shift the operands down.
1808 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1809 // than the old isel though.
1810 int OldFlagResultNo = -1, OldChainResultNo = -1;
1812 unsigned NTMNumResults = Node->getNumValues();
1813 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1814 OldFlagResultNo = NTMNumResults-1;
1815 if (NTMNumResults != 1 &&
1816 Node->getValueType(NTMNumResults-2) == MVT::Other)
1817 OldChainResultNo = NTMNumResults-2;
1818 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1819 OldChainResultNo = NTMNumResults-1;
1821 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1822 // that this deletes operands of the old node that become dead.
1823 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1825 // MorphNodeTo can operate in two ways: if an existing node with the
1826 // specified operands exists, it can just return it. Otherwise, it
1827 // updates the node in place to have the requested operands.
1829 // If we updated the node in place, reset the node ID. To the isel,
1830 // this should be just like a newly allocated machine node.
1834 unsigned ResNumResults = Res->getNumValues();
1835 // Move the flag if needed.
1836 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1837 (unsigned)OldFlagResultNo != ResNumResults-1)
1838 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1839 SDValue(Res, ResNumResults-1));
1841 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1844 // Move the chain reference if needed.
1845 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1846 (unsigned)OldChainResultNo != ResNumResults-1)
1847 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1848 SDValue(Res, ResNumResults-1));
1850 // Otherwise, no replacement happened because the node already exists. Replace
1851 // Uses of the old node with the new one.
1853 CurDAG->ReplaceAllUsesWith(Node, Res);
1858 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1859 ALWAYS_INLINE static bool
1860 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1861 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1862 // Accept if it is exactly the same as a previously recorded node.
1863 unsigned RecNo = MatcherTable[MatcherIndex++];
1864 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1865 return N == RecordedNodes[RecNo];
1868 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1869 ALWAYS_INLINE static bool
1870 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1871 SelectionDAGISel &SDISel) {
1872 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1875 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1876 ALWAYS_INLINE static bool
1877 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1878 SelectionDAGISel &SDISel, SDNode *N) {
1879 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1882 ALWAYS_INLINE static bool
1883 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1885 uint16_t Opc = MatcherTable[MatcherIndex++];
1886 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1887 return N->getOpcode() == Opc;
1890 ALWAYS_INLINE static bool
1891 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1892 SDValue N, const TargetLowering &TLI) {
1893 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1894 if (N.getValueType() == VT) return true;
1896 // Handle the case when VT is iPTR.
1897 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1900 ALWAYS_INLINE static bool
1901 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1902 SDValue N, const TargetLowering &TLI,
1904 if (ChildNo >= N.getNumOperands())
1905 return false; // Match fails if out of range child #.
1906 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1910 ALWAYS_INLINE static bool
1911 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1913 return cast<CondCodeSDNode>(N)->get() ==
1914 (ISD::CondCode)MatcherTable[MatcherIndex++];
1917 ALWAYS_INLINE static bool
1918 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1919 SDValue N, const TargetLowering &TLI) {
1920 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1921 if (cast<VTSDNode>(N)->getVT() == VT)
1924 // Handle the case when VT is iPTR.
1925 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1928 ALWAYS_INLINE static bool
1929 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1931 int64_t Val = MatcherTable[MatcherIndex++];
1933 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1935 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1936 return C != 0 && C->getSExtValue() == Val;
1939 ALWAYS_INLINE static bool
1940 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1941 SDValue N, SelectionDAGISel &SDISel) {
1942 int64_t Val = MatcherTable[MatcherIndex++];
1944 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1946 if (N->getOpcode() != ISD::AND) return false;
1948 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1949 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1952 ALWAYS_INLINE static bool
1953 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1954 SDValue N, SelectionDAGISel &SDISel) {
1955 int64_t Val = MatcherTable[MatcherIndex++];
1957 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1959 if (N->getOpcode() != ISD::OR) return false;
1961 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1962 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1965 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1966 /// scope, evaluate the current node. If the current predicate is known to
1967 /// fail, set Result=true and return anything. If the current predicate is
1968 /// known to pass, set Result=false and return the MatcherIndex to continue
1969 /// with. If the current predicate is unknown, set Result=false and return the
1970 /// MatcherIndex to continue with.
1971 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1972 unsigned Index, SDValue N,
1973 bool &Result, SelectionDAGISel &SDISel,
1974 SmallVectorImpl<SDValue> &RecordedNodes){
1975 switch (Table[Index++]) {
1978 return Index-1; // Could not evaluate this predicate.
1979 case SelectionDAGISel::OPC_CheckSame:
1980 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1982 case SelectionDAGISel::OPC_CheckPatternPredicate:
1983 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1985 case SelectionDAGISel::OPC_CheckPredicate:
1986 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1988 case SelectionDAGISel::OPC_CheckOpcode:
1989 Result = !::CheckOpcode(Table, Index, N.getNode());
1991 case SelectionDAGISel::OPC_CheckType:
1992 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1994 case SelectionDAGISel::OPC_CheckChild0Type:
1995 case SelectionDAGISel::OPC_CheckChild1Type:
1996 case SelectionDAGISel::OPC_CheckChild2Type:
1997 case SelectionDAGISel::OPC_CheckChild3Type:
1998 case SelectionDAGISel::OPC_CheckChild4Type:
1999 case SelectionDAGISel::OPC_CheckChild5Type:
2000 case SelectionDAGISel::OPC_CheckChild6Type:
2001 case SelectionDAGISel::OPC_CheckChild7Type:
2002 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2003 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2005 case SelectionDAGISel::OPC_CheckCondCode:
2006 Result = !::CheckCondCode(Table, Index, N);
2008 case SelectionDAGISel::OPC_CheckValueType:
2009 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2011 case SelectionDAGISel::OPC_CheckInteger:
2012 Result = !::CheckInteger(Table, Index, N);
2014 case SelectionDAGISel::OPC_CheckAndImm:
2015 Result = !::CheckAndImm(Table, Index, N, SDISel);
2017 case SelectionDAGISel::OPC_CheckOrImm:
2018 Result = !::CheckOrImm(Table, Index, N, SDISel);
2025 /// FailIndex - If this match fails, this is the index to continue with.
2028 /// NodeStack - The node stack when the scope was formed.
2029 SmallVector<SDValue, 4> NodeStack;
2031 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2032 unsigned NumRecordedNodes;
2034 /// NumMatchedMemRefs - The number of matched memref entries.
2035 unsigned NumMatchedMemRefs;
2037 /// InputChain/InputFlag - The current chain/flag
2038 SDValue InputChain, InputFlag;
2040 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2041 bool HasChainNodesMatched, HasFlagResultNodesMatched;
2044 SDNode *SelectionDAGISel::
2045 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2046 unsigned TableSize) {
2047 // FIXME: Should these even be selected? Handle these cases in the caller?
2048 switch (NodeToMatch->getOpcode()) {
2051 case ISD::EntryToken: // These nodes remain the same.
2052 case ISD::BasicBlock:
2054 //case ISD::VALUETYPE:
2055 //case ISD::CONDCODE:
2056 case ISD::HANDLENODE:
2057 case ISD::TargetConstant:
2058 case ISD::TargetConstantFP:
2059 case ISD::TargetConstantPool:
2060 case ISD::TargetFrameIndex:
2061 case ISD::TargetExternalSymbol:
2062 case ISD::TargetBlockAddress:
2063 case ISD::TargetJumpTable:
2064 case ISD::TargetGlobalTLSAddress:
2065 case ISD::TargetGlobalAddress:
2066 case ISD::TokenFactor:
2067 case ISD::CopyFromReg:
2068 case ISD::CopyToReg:
2070 NodeToMatch->setNodeId(-1); // Mark selected.
2072 case ISD::AssertSext:
2073 case ISD::AssertZext:
2074 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2075 NodeToMatch->getOperand(0));
2077 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2078 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2081 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2083 // Set up the node stack with NodeToMatch as the only node on the stack.
2084 SmallVector<SDValue, 8> NodeStack;
2085 SDValue N = SDValue(NodeToMatch, 0);
2086 NodeStack.push_back(N);
2088 // MatchScopes - Scopes used when matching, if a match failure happens, this
2089 // indicates where to continue checking.
2090 SmallVector<MatchScope, 8> MatchScopes;
2092 // RecordedNodes - This is the set of nodes that have been recorded by the
2094 SmallVector<SDValue, 8> RecordedNodes;
2096 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2098 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2100 // These are the current input chain and flag for use when generating nodes.
2101 // Various Emit operations change these. For example, emitting a copytoreg
2102 // uses and updates these.
2103 SDValue InputChain, InputFlag;
2105 // ChainNodesMatched - If a pattern matches nodes that have input/output
2106 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2107 // which ones they are. The result is captured into this list so that we can
2108 // update the chain results when the pattern is complete.
2109 SmallVector<SDNode*, 3> ChainNodesMatched;
2110 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2112 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2113 NodeToMatch->dump(CurDAG);
2116 // Determine where to start the interpreter. Normally we start at opcode #0,
2117 // but if the state machine starts with an OPC_SwitchOpcode, then we
2118 // accelerate the first lookup (which is guaranteed to be hot) with the
2119 // OpcodeOffset table.
2120 unsigned MatcherIndex = 0;
2122 if (!OpcodeOffset.empty()) {
2123 // Already computed the OpcodeOffset table, just index into it.
2124 if (N.getOpcode() < OpcodeOffset.size())
2125 MatcherIndex = OpcodeOffset[N.getOpcode()];
2126 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2128 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2129 // Otherwise, the table isn't computed, but the state machine does start
2130 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2131 // is the first time we're selecting an instruction.
2134 // Get the size of this case.
2135 unsigned CaseSize = MatcherTable[Idx++];
2137 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2138 if (CaseSize == 0) break;
2140 // Get the opcode, add the index to the table.
2141 uint16_t Opc = MatcherTable[Idx++];
2142 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2143 if (Opc >= OpcodeOffset.size())
2144 OpcodeOffset.resize((Opc+1)*2);
2145 OpcodeOffset[Opc] = Idx;
2149 // Okay, do the lookup for the first opcode.
2150 if (N.getOpcode() < OpcodeOffset.size())
2151 MatcherIndex = OpcodeOffset[N.getOpcode()];
2155 assert(MatcherIndex < TableSize && "Invalid index");
2157 unsigned CurrentOpcodeIndex = MatcherIndex;
2159 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2162 // Okay, the semantics of this operation are that we should push a scope
2163 // then evaluate the first child. However, pushing a scope only to have
2164 // the first check fail (which then pops it) is inefficient. If we can
2165 // determine immediately that the first check (or first several) will
2166 // immediately fail, don't even bother pushing a scope for them.
2170 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2171 if (NumToSkip & 128)
2172 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2173 // Found the end of the scope with no match.
2174 if (NumToSkip == 0) {
2179 FailIndex = MatcherIndex+NumToSkip;
2181 unsigned MatcherIndexOfPredicate = MatcherIndex;
2182 (void)MatcherIndexOfPredicate; // silence warning.
2184 // If we can't evaluate this predicate without pushing a scope (e.g. if
2185 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2186 // push the scope and evaluate the full predicate chain.
2188 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2189 Result, *this, RecordedNodes);
2193 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2194 << "index " << MatcherIndexOfPredicate
2195 << ", continuing at " << FailIndex << "\n");
2196 ++NumDAGIselRetries;
2198 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2199 // move to the next case.
2200 MatcherIndex = FailIndex;
2203 // If the whole scope failed to match, bail.
2204 if (FailIndex == 0) break;
2206 // Push a MatchScope which indicates where to go if the first child fails
2208 MatchScope NewEntry;
2209 NewEntry.FailIndex = FailIndex;
2210 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2211 NewEntry.NumRecordedNodes = RecordedNodes.size();
2212 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2213 NewEntry.InputChain = InputChain;
2214 NewEntry.InputFlag = InputFlag;
2215 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2216 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2217 MatchScopes.push_back(NewEntry);
2220 case OPC_RecordNode:
2221 // Remember this node, it may end up being an operand in the pattern.
2222 RecordedNodes.push_back(N);
2225 case OPC_RecordChild0: case OPC_RecordChild1:
2226 case OPC_RecordChild2: case OPC_RecordChild3:
2227 case OPC_RecordChild4: case OPC_RecordChild5:
2228 case OPC_RecordChild6: case OPC_RecordChild7: {
2229 unsigned ChildNo = Opcode-OPC_RecordChild0;
2230 if (ChildNo >= N.getNumOperands())
2231 break; // Match fails if out of range child #.
2233 RecordedNodes.push_back(N->getOperand(ChildNo));
2236 case OPC_RecordMemRef:
2237 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2240 case OPC_CaptureFlagInput:
2241 // If the current node has an input flag, capture it in InputFlag.
2242 if (N->getNumOperands() != 0 &&
2243 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2244 InputFlag = N->getOperand(N->getNumOperands()-1);
2247 case OPC_MoveChild: {
2248 unsigned ChildNo = MatcherTable[MatcherIndex++];
2249 if (ChildNo >= N.getNumOperands())
2250 break; // Match fails if out of range child #.
2251 N = N.getOperand(ChildNo);
2252 NodeStack.push_back(N);
2256 case OPC_MoveParent:
2257 // Pop the current node off the NodeStack.
2258 NodeStack.pop_back();
2259 assert(!NodeStack.empty() && "Node stack imbalance!");
2260 N = NodeStack.back();
2264 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2266 case OPC_CheckPatternPredicate:
2267 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2269 case OPC_CheckPredicate:
2270 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2274 case OPC_CheckComplexPat: {
2275 unsigned CPNum = MatcherTable[MatcherIndex++];
2276 unsigned RecNo = MatcherTable[MatcherIndex++];
2277 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2278 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2283 case OPC_CheckOpcode:
2284 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2288 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2291 case OPC_SwitchOpcode: {
2292 unsigned CurNodeOpcode = N.getOpcode();
2293 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2296 // Get the size of this case.
2297 CaseSize = MatcherTable[MatcherIndex++];
2299 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2300 if (CaseSize == 0) break;
2302 uint16_t Opc = MatcherTable[MatcherIndex++];
2303 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2305 // If the opcode matches, then we will execute this case.
2306 if (CurNodeOpcode == Opc)
2309 // Otherwise, skip over this case.
2310 MatcherIndex += CaseSize;
2313 // If no cases matched, bail out.
2314 if (CaseSize == 0) break;
2316 // Otherwise, execute the case we found.
2317 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2318 << " to " << MatcherIndex << "\n");
2322 case OPC_SwitchType: {
2323 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2324 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2327 // Get the size of this case.
2328 CaseSize = MatcherTable[MatcherIndex++];
2330 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2331 if (CaseSize == 0) break;
2333 MVT::SimpleValueType CaseVT =
2334 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2335 if (CaseVT == MVT::iPTR)
2336 CaseVT = TLI.getPointerTy().SimpleTy;
2338 // If the VT matches, then we will execute this case.
2339 if (CurNodeVT == CaseVT)
2342 // Otherwise, skip over this case.
2343 MatcherIndex += CaseSize;
2346 // If no cases matched, bail out.
2347 if (CaseSize == 0) break;
2349 // Otherwise, execute the case we found.
2350 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2351 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2354 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2355 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2356 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2357 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2358 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2359 Opcode-OPC_CheckChild0Type))
2362 case OPC_CheckCondCode:
2363 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2365 case OPC_CheckValueType:
2366 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2368 case OPC_CheckInteger:
2369 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2371 case OPC_CheckAndImm:
2372 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2374 case OPC_CheckOrImm:
2375 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2378 case OPC_CheckFoldableChainNode: {
2379 assert(NodeStack.size() != 1 && "No parent node");
2380 // Verify that all intermediate nodes between the root and this one have
2382 bool HasMultipleUses = false;
2383 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2384 if (!NodeStack[i].hasOneUse()) {
2385 HasMultipleUses = true;
2388 if (HasMultipleUses) break;
2390 // Check to see that the target thinks this is profitable to fold and that
2391 // we can fold it without inducing cycles in the graph.
2392 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2394 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2395 NodeToMatch, true/*We validate our own chains*/))
2400 case OPC_EmitInteger: {
2401 MVT::SimpleValueType VT =
2402 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2403 int64_t Val = MatcherTable[MatcherIndex++];
2405 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2406 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2409 case OPC_EmitRegister: {
2410 MVT::SimpleValueType VT =
2411 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2412 unsigned RegNo = MatcherTable[MatcherIndex++];
2413 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2417 case OPC_EmitConvertToTarget: {
2418 // Convert from IMM/FPIMM to target version.
2419 unsigned RecNo = MatcherTable[MatcherIndex++];
2420 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2421 SDValue Imm = RecordedNodes[RecNo];
2423 if (Imm->getOpcode() == ISD::Constant) {
2424 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2425 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2426 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2427 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2428 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2431 RecordedNodes.push_back(Imm);
2435 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2436 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2437 // These are space-optimized forms of OPC_EmitMergeInputChains.
2438 assert(InputChain.getNode() == 0 &&
2439 "EmitMergeInputChains should be the first chain producing node");
2440 assert(ChainNodesMatched.empty() &&
2441 "Should only have one EmitMergeInputChains per match");
2443 // Read all of the chained nodes.
2444 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2445 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2446 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2448 // FIXME: What if other value results of the node have uses not matched
2450 if (ChainNodesMatched.back() != NodeToMatch &&
2451 !RecordedNodes[RecNo].hasOneUse()) {
2452 ChainNodesMatched.clear();
2456 // Merge the input chains if they are not intra-pattern references.
2457 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2459 if (InputChain.getNode() == 0)
2460 break; // Failed to merge.
2464 case OPC_EmitMergeInputChains: {
2465 assert(InputChain.getNode() == 0 &&
2466 "EmitMergeInputChains should be the first chain producing node");
2467 // This node gets a list of nodes we matched in the input that have
2468 // chains. We want to token factor all of the input chains to these nodes
2469 // together. However, if any of the input chains is actually one of the
2470 // nodes matched in this pattern, then we have an intra-match reference.
2471 // Ignore these because the newly token factored chain should not refer to
2473 unsigned NumChains = MatcherTable[MatcherIndex++];
2474 assert(NumChains != 0 && "Can't TF zero chains");
2476 assert(ChainNodesMatched.empty() &&
2477 "Should only have one EmitMergeInputChains per match");
2479 // Read all of the chained nodes.
2480 for (unsigned i = 0; i != NumChains; ++i) {
2481 unsigned RecNo = MatcherTable[MatcherIndex++];
2482 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2483 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2485 // FIXME: What if other value results of the node have uses not matched
2487 if (ChainNodesMatched.back() != NodeToMatch &&
2488 !RecordedNodes[RecNo].hasOneUse()) {
2489 ChainNodesMatched.clear();
2494 // If the inner loop broke out, the match fails.
2495 if (ChainNodesMatched.empty())
2498 // Merge the input chains if they are not intra-pattern references.
2499 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2501 if (InputChain.getNode() == 0)
2502 break; // Failed to merge.
2507 case OPC_EmitCopyToReg: {
2508 unsigned RecNo = MatcherTable[MatcherIndex++];
2509 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2510 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2512 if (InputChain.getNode() == 0)
2513 InputChain = CurDAG->getEntryNode();
2515 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2516 DestPhysReg, RecordedNodes[RecNo],
2519 InputFlag = InputChain.getValue(1);
2523 case OPC_EmitNodeXForm: {
2524 unsigned XFormNo = MatcherTable[MatcherIndex++];
2525 unsigned RecNo = MatcherTable[MatcherIndex++];
2526 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2527 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2532 case OPC_MorphNodeTo: {
2533 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2534 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2535 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2536 // Get the result VT list.
2537 unsigned NumVTs = MatcherTable[MatcherIndex++];
2538 SmallVector<EVT, 4> VTs;
2539 for (unsigned i = 0; i != NumVTs; ++i) {
2540 MVT::SimpleValueType VT =
2541 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2542 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2546 if (EmitNodeInfo & OPFL_Chain)
2547 VTs.push_back(MVT::Other);
2548 if (EmitNodeInfo & OPFL_FlagOutput)
2549 VTs.push_back(MVT::Flag);
2551 // This is hot code, so optimize the two most common cases of 1 and 2
2554 if (VTs.size() == 1)
2555 VTList = CurDAG->getVTList(VTs[0]);
2556 else if (VTs.size() == 2)
2557 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2559 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2561 // Get the operand list.
2562 unsigned NumOps = MatcherTable[MatcherIndex++];
2563 SmallVector<SDValue, 8> Ops;
2564 for (unsigned i = 0; i != NumOps; ++i) {
2565 unsigned RecNo = MatcherTable[MatcherIndex++];
2567 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2569 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2570 Ops.push_back(RecordedNodes[RecNo]);
2573 // If there are variadic operands to add, handle them now.
2574 if (EmitNodeInfo & OPFL_VariadicInfo) {
2575 // Determine the start index to copy from.
2576 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2577 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2578 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2579 "Invalid variadic node");
2580 // Copy all of the variadic operands, not including a potential flag
2582 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2584 SDValue V = NodeToMatch->getOperand(i);
2585 if (V.getValueType() == MVT::Flag) break;
2590 // If this has chain/flag inputs, add them.
2591 if (EmitNodeInfo & OPFL_Chain)
2592 Ops.push_back(InputChain);
2593 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2594 Ops.push_back(InputFlag);
2598 if (Opcode != OPC_MorphNodeTo) {
2599 // If this is a normal EmitNode command, just create the new node and
2600 // add the results to the RecordedNodes list.
2601 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2602 VTList, Ops.data(), Ops.size());
2604 // Add all the non-flag/non-chain results to the RecordedNodes list.
2605 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2606 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2607 RecordedNodes.push_back(SDValue(Res, i));
2611 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2615 // If the node had chain/flag results, update our notion of the current
2617 if (EmitNodeInfo & OPFL_FlagOutput) {
2618 InputFlag = SDValue(Res, VTs.size()-1);
2619 if (EmitNodeInfo & OPFL_Chain)
2620 InputChain = SDValue(Res, VTs.size()-2);
2621 } else if (EmitNodeInfo & OPFL_Chain)
2622 InputChain = SDValue(Res, VTs.size()-1);
2624 // If the OPFL_MemRefs flag is set on this node, slap all of the
2625 // accumulated memrefs onto it.
2627 // FIXME: This is vastly incorrect for patterns with multiple outputs
2628 // instructions that access memory and for ComplexPatterns that match
2630 if (EmitNodeInfo & OPFL_MemRefs) {
2631 MachineSDNode::mmo_iterator MemRefs =
2632 MF->allocateMemRefsArray(MatchedMemRefs.size());
2633 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2634 cast<MachineSDNode>(Res)
2635 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2639 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2640 << " node: "; Res->dump(CurDAG); errs() << "\n");
2642 // If this was a MorphNodeTo then we're completely done!
2643 if (Opcode == OPC_MorphNodeTo) {
2644 // Update chain and flag uses.
2645 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2646 InputFlag, FlagResultNodesMatched, true);
2653 case OPC_MarkFlagResults: {
2654 unsigned NumNodes = MatcherTable[MatcherIndex++];
2656 // Read and remember all the flag-result nodes.
2657 for (unsigned i = 0; i != NumNodes; ++i) {
2658 unsigned RecNo = MatcherTable[MatcherIndex++];
2660 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2662 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2663 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2668 case OPC_CompleteMatch: {
2669 // The match has been completed, and any new nodes (if any) have been
2670 // created. Patch up references to the matched dag to use the newly
2672 unsigned NumResults = MatcherTable[MatcherIndex++];
2674 for (unsigned i = 0; i != NumResults; ++i) {
2675 unsigned ResSlot = MatcherTable[MatcherIndex++];
2677 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2679 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2680 SDValue Res = RecordedNodes[ResSlot];
2682 assert(i < NodeToMatch->getNumValues() &&
2683 NodeToMatch->getValueType(i) != MVT::Other &&
2684 NodeToMatch->getValueType(i) != MVT::Flag &&
2685 "Invalid number of results to complete!");
2686 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2687 NodeToMatch->getValueType(i) == MVT::iPTR ||
2688 Res.getValueType() == MVT::iPTR ||
2689 NodeToMatch->getValueType(i).getSizeInBits() ==
2690 Res.getValueType().getSizeInBits()) &&
2691 "invalid replacement");
2692 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2695 // If the root node defines a flag, add it to the flag nodes to update
2697 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2698 FlagResultNodesMatched.push_back(NodeToMatch);
2700 // Update chain and flag uses.
2701 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2702 InputFlag, FlagResultNodesMatched, false);
2704 assert(NodeToMatch->use_empty() &&
2705 "Didn't replace all uses of the node?");
2707 // FIXME: We just return here, which interacts correctly with SelectRoot
2708 // above. We should fix this to not return an SDNode* anymore.
2713 // If the code reached this point, then the match failed. See if there is
2714 // another child to try in the current 'Scope', otherwise pop it until we
2715 // find a case to check.
2716 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2717 ++NumDAGIselRetries;
2719 if (MatchScopes.empty()) {
2720 CannotYetSelect(NodeToMatch);
2724 // Restore the interpreter state back to the point where the scope was
2726 MatchScope &LastScope = MatchScopes.back();
2727 RecordedNodes.resize(LastScope.NumRecordedNodes);
2729 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2730 N = NodeStack.back();
2732 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2733 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2734 MatcherIndex = LastScope.FailIndex;
2736 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2738 InputChain = LastScope.InputChain;
2739 InputFlag = LastScope.InputFlag;
2740 if (!LastScope.HasChainNodesMatched)
2741 ChainNodesMatched.clear();
2742 if (!LastScope.HasFlagResultNodesMatched)
2743 FlagResultNodesMatched.clear();
2745 // Check to see what the offset is at the new MatcherIndex. If it is zero
2746 // we have reached the end of this scope, otherwise we have another child
2747 // in the current scope to try.
2748 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2749 if (NumToSkip & 128)
2750 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2752 // If we have another child in this scope to match, update FailIndex and
2754 if (NumToSkip != 0) {
2755 LastScope.FailIndex = MatcherIndex+NumToSkip;
2759 // End of this scope, pop it and try the next child in the containing
2761 MatchScopes.pop_back();
2768 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2770 raw_string_ostream Msg(msg);
2771 Msg << "Cannot yet select: ";
2773 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2774 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2775 N->getOpcode() != ISD::INTRINSIC_VOID) {
2776 N->printrFull(Msg, CurDAG);
2778 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2780 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2781 if (iid < Intrinsic::num_intrinsics)
2782 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2783 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2784 Msg << "target intrinsic %" << TII->getName(iid);
2786 Msg << "unknown intrinsic #" << iid;
2788 llvm_report_error(Msg.str());
2791 char SelectionDAGISel::ID = 0;