1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAGISel.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/TargetLibraryInfo.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DebugInfo.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/LLVMContext.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/Target/TargetInstrInfo.h"
52 #include "llvm/Target/TargetIntrinsicInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 #define DEBUG_TYPE "isel"
64 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
65 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
66 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
67 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
68 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
70 STATISTIC(NumFastIselFailLowerArguments,
71 "Number of entry blocks where fast isel failed to lower arguments");
75 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
76 cl::desc("Enable extra verbose messages in the \"fast\" "
77 "instruction selector"));
80 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
81 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
82 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
83 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
84 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
85 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
86 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
88 // Standard binary operators...
89 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
90 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
91 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
92 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
93 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
94 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
95 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
96 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
97 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
98 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
99 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
100 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
102 // Logical operators...
103 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
104 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
105 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
107 // Memory instructions...
108 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
109 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
110 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
111 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
112 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
113 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
114 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
116 // Convert instructions...
117 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
118 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
119 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
120 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
121 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
122 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
123 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
124 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
125 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
126 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
127 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
128 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
130 // Other instructions...
131 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
132 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
133 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
134 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
135 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
136 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
137 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
138 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
139 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
140 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
141 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
142 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
143 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
144 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
145 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 // Intrinsic instructions...
148 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
149 STATISTIC(NumFastIselFailSAddWithOverflow,
150 "Fast isel fails on sadd.with.overflow");
151 STATISTIC(NumFastIselFailUAddWithOverflow,
152 "Fast isel fails on uadd.with.overflow");
153 STATISTIC(NumFastIselFailSSubWithOverflow,
154 "Fast isel fails on ssub.with.overflow");
155 STATISTIC(NumFastIselFailUSubWithOverflow,
156 "Fast isel fails on usub.with.overflow");
157 STATISTIC(NumFastIselFailSMulWithOverflow,
158 "Fast isel fails on smul.with.overflow");
159 STATISTIC(NumFastIselFailUMulWithOverflow,
160 "Fast isel fails on umul.with.overflow");
161 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
162 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
163 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
164 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
168 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
169 cl::desc("Enable verbose messages in the \"fast\" "
170 "instruction selector"));
172 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
173 cl::desc("Enable abort calls when \"fast\" instruction selection "
174 "fails to lower an instruction"));
176 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
177 cl::desc("Enable abort calls when \"fast\" instruction selection "
178 "fails to lower a formal argument"));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
297 TLI->getSchedulingPreference() == Sched::Source)
298 return createSourceListDAGScheduler(IS, OptLevel);
299 if (TLI->getSchedulingPreference() == Sched::RegPressure)
300 return createBURRListDAGScheduler(IS, OptLevel);
301 if (TLI->getSchedulingPreference() == Sched::Hybrid)
302 return createHybridListDAGScheduler(IS, OptLevel);
303 if (TLI->getSchedulingPreference() == Sched::VLIW)
304 return createVLIWDAGScheduler(IS, OptLevel);
305 assert(TLI->getSchedulingPreference() == Sched::ILP &&
306 "Unknown sched type!");
307 return createILPListDAGScheduler(IS, OptLevel);
311 // EmitInstrWithCustomInserter - This method should be implemented by targets
312 // that mark instructions with the 'usesCustomInserter' flag. These
313 // instructions are special in various ways, which require special support to
314 // insert. The specified MachineInstr is created but not inserted into any
315 // basic blocks, and this method is called to expand it into a sequence of
316 // instructions, potentially also creating new basic blocks and control flow.
317 // When new basic blocks are inserted and the edges from MBB to its successors
318 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
321 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
322 MachineBasicBlock *MBB) const {
324 dbgs() << "If a target marks an instruction with "
325 "'usesCustomInserter', it must implement "
326 "TargetLowering::EmitInstrWithCustomInserter!";
328 llvm_unreachable(nullptr);
331 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
332 SDNode *Node) const {
333 assert(!MI->hasPostISelHook() &&
334 "If a target marks an instruction with 'hasPostISelHook', "
335 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
338 //===----------------------------------------------------------------------===//
339 // SelectionDAGISel code
340 //===----------------------------------------------------------------------===//
342 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
343 CodeGenOpt::Level OL) :
344 MachineFunctionPass(ID), TM(tm),
345 FuncInfo(new FunctionLoweringInfo()),
346 CurDAG(new SelectionDAG(tm, OL)),
347 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
351 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
352 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
353 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
354 initializeTargetLibraryInfoWrapperPassPass(
355 *PassRegistry::getPassRegistry());
358 SelectionDAGISel::~SelectionDAGISel() {
364 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
365 AU.addRequired<AliasAnalysis>();
366 AU.addPreserved<AliasAnalysis>();
367 AU.addRequired<GCModuleInfo>();
368 AU.addPreserved<GCModuleInfo>();
369 AU.addRequired<TargetLibraryInfoWrapperPass>();
370 if (UseMBPI && OptLevel != CodeGenOpt::None)
371 AU.addRequired<BranchProbabilityInfo>();
372 MachineFunctionPass::getAnalysisUsage(AU);
375 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
376 /// may trap on it. In this case we have to split the edge so that the path
377 /// through the predecessor block that doesn't go to the phi block doesn't
378 /// execute the possibly trapping instruction.
380 /// This is required for correctness, so it must be done at -O0.
382 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
383 // Loop for blocks with phi nodes.
384 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
385 PHINode *PN = dyn_cast<PHINode>(BB->begin());
389 // For each block with a PHI node, check to see if any of the input values
390 // are potentially trapping constant expressions. Constant expressions are
391 // the only potentially trapping value that can occur as the argument to a
393 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
394 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
395 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
396 if (!CE || !CE->canTrap()) continue;
398 // The only case we have to worry about is when the edge is critical.
399 // Since this block has a PHI Node, we assume it has multiple input
400 // edges: check to see if the pred has multiple successors.
401 BasicBlock *Pred = PN->getIncomingBlock(i);
402 if (Pred->getTerminator()->getNumSuccessors() == 1)
405 // Okay, we have to split this edge.
406 SplitCriticalEdge(Pred->getTerminator(),
407 GetSuccessorNumber(Pred, BB), SDISel, true);
413 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
414 // Do some sanity-checking on the command-line options.
415 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
416 "-fast-isel-verbose requires -fast-isel");
417 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
418 "-fast-isel-abort requires -fast-isel");
420 const Function &Fn = *mf.getFunction();
423 // Reset the target options before resetting the optimization
425 // FIXME: This is a horrible hack and should be processed via
426 // codegen looking at the optimization level explicitly when
427 // it wants to look at it.
428 TM.resetTargetOptions(Fn);
429 // Reset OptLevel to None for optnone functions.
430 CodeGenOpt::Level NewOptLevel = OptLevel;
431 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
432 NewOptLevel = CodeGenOpt::None;
433 OptLevelChanger OLC(*this, NewOptLevel);
435 TII = MF->getSubtarget().getInstrInfo();
436 TLI = MF->getSubtarget().getTargetLowering();
437 RegInfo = &MF->getRegInfo();
438 AA = &getAnalysis<AliasAnalysis>();
439 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
440 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
442 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
444 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
447 FuncInfo->set(Fn, *MF, CurDAG);
449 if (UseMBPI && OptLevel != CodeGenOpt::None)
450 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
452 FuncInfo->BPI = nullptr;
454 SDB->init(GFI, *AA, LibInfo);
456 MF->setHasInlineAsm(false);
458 SelectAllBasicBlocks(Fn);
460 // If the first basic block in the function has live ins that need to be
461 // copied into vregs, emit the copies into the top of the block before
462 // emitting the code for the block.
463 MachineBasicBlock *EntryMBB = MF->begin();
464 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
465 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
467 DenseMap<unsigned, unsigned> LiveInMap;
468 if (!FuncInfo->ArgDbgValues.empty())
469 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
470 E = RegInfo->livein_end(); LI != E; ++LI)
472 LiveInMap.insert(std::make_pair(LI->first, LI->second));
474 // Insert DBG_VALUE instructions for function arguments to the entry block.
475 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
476 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
477 bool hasFI = MI->getOperand(0).isFI();
479 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
480 if (TargetRegisterInfo::isPhysicalRegister(Reg))
481 EntryMBB->insert(EntryMBB->begin(), MI);
483 MachineInstr *Def = RegInfo->getVRegDef(Reg);
485 MachineBasicBlock::iterator InsertPos = Def;
486 // FIXME: VR def may not be in entry block.
487 Def->getParent()->insert(std::next(InsertPos), MI);
489 DEBUG(dbgs() << "Dropping debug info for dead vreg"
490 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
493 // If Reg is live-in then update debug info to track its copy in a vreg.
494 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
495 if (LDI != LiveInMap.end()) {
496 assert(!hasFI && "There's no handling of frame pointer updating here yet "
498 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
499 MachineBasicBlock::iterator InsertPos = Def;
500 const MDNode *Variable = MI->getDebugVariable();
501 const MDNode *Expr = MI->getDebugExpression();
502 bool IsIndirect = MI->isIndirectDebugValue();
503 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
504 // Def is never a terminator here, so it is ok to increment InsertPos.
505 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
506 TII->get(TargetOpcode::DBG_VALUE), IsIndirect, LDI->second, Offset,
509 // If this vreg is directly copied into an exported register then
510 // that COPY instructions also need DBG_VALUE, if it is the only
511 // user of LDI->second.
512 MachineInstr *CopyUseMI = nullptr;
513 for (MachineRegisterInfo::use_instr_iterator
514 UI = RegInfo->use_instr_begin(LDI->second),
515 E = RegInfo->use_instr_end(); UI != E; ) {
516 MachineInstr *UseMI = &*(UI++);
517 if (UseMI->isDebugValue()) continue;
518 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
519 CopyUseMI = UseMI; continue;
521 // Otherwise this is another use or second copy use.
522 CopyUseMI = nullptr; break;
525 MachineInstr *NewMI =
526 BuildMI(*MF, CopyUseMI->getDebugLoc(),
527 TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
528 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
529 MachineBasicBlock::iterator Pos = CopyUseMI;
530 EntryMBB->insertAfter(Pos, NewMI);
535 // Determine if there are any calls in this machine function.
536 MachineFrameInfo *MFI = MF->getFrameInfo();
537 for (const auto &MBB : *MF) {
538 if (MFI->hasCalls() && MF->hasInlineAsm())
541 for (const auto &MI : MBB) {
542 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
543 if ((MCID.isCall() && !MCID.isReturn()) ||
544 MI.isStackAligningInlineAsm()) {
545 MFI->setHasCalls(true);
547 if (MI.isInlineAsm()) {
548 MF->setHasInlineAsm(true);
553 // Determine if there is a call to setjmp in the machine function.
554 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
556 // Replace forward-declared registers with the registers containing
557 // the desired value.
558 MachineRegisterInfo &MRI = MF->getRegInfo();
559 for (DenseMap<unsigned, unsigned>::iterator
560 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
562 unsigned From = I->first;
563 unsigned To = I->second;
564 // If To is also scheduled to be replaced, find what its ultimate
567 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
571 // Make sure the new register has a sufficiently constrained register class.
572 if (TargetRegisterInfo::isVirtualRegister(From) &&
573 TargetRegisterInfo::isVirtualRegister(To))
574 MRI.constrainRegClass(To, MRI.getRegClass(From));
576 MRI.replaceRegWith(From, To);
579 // Freeze the set of reserved registers now that MachineFrameInfo has been
580 // set up. All the information required by getReservedRegs() should be
582 MRI.freezeReservedRegs(*MF);
584 // Release function-specific state. SDB and CurDAG are already cleared
588 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
589 DEBUG(MF->print(dbgs()));
594 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
595 BasicBlock::const_iterator End,
597 // Lower all of the non-terminator instructions. If a call is emitted
598 // as a tail call, cease emitting nodes for this block. Terminators
599 // are handled below.
600 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
603 // Make sure the root of the DAG is up-to-date.
604 CurDAG->setRoot(SDB->getControlRoot());
605 HadTailCall = SDB->HasTailCall;
608 // Final step, emit the lowered DAG as machine code.
612 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
613 SmallPtrSet<SDNode*, 128> VisitedNodes;
614 SmallVector<SDNode*, 128> Worklist;
616 Worklist.push_back(CurDAG->getRoot().getNode());
622 SDNode *N = Worklist.pop_back_val();
624 // If we've already seen this node, ignore it.
625 if (!VisitedNodes.insert(N).second)
628 // Otherwise, add all chain operands to the worklist.
629 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
630 if (N->getOperand(i).getValueType() == MVT::Other)
631 Worklist.push_back(N->getOperand(i).getNode());
633 // If this is a CopyToReg with a vreg dest, process it.
634 if (N->getOpcode() != ISD::CopyToReg)
637 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
638 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
641 // Ignore non-scalar or non-integer values.
642 SDValue Src = N->getOperand(2);
643 EVT SrcVT = Src.getValueType();
644 if (!SrcVT.isInteger() || SrcVT.isVector())
647 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
648 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
649 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
650 } while (!Worklist.empty());
653 void SelectionDAGISel::CodeGenAndEmitDAG() {
654 std::string GroupName;
655 if (TimePassesIsEnabled)
656 GroupName = "Instruction Selection and Scheduling";
657 std::string BlockName;
658 int BlockNumber = -1;
660 bool MatchFilterBB = false; (void)MatchFilterBB;
662 MatchFilterBB = (!FilterDAGBasicBlockName.empty() &&
663 FilterDAGBasicBlockName ==
664 FuncInfo->MBB->getBasicBlock()->getName().str());
667 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
668 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
672 BlockNumber = FuncInfo->MBB->getNumber();
673 BlockName = MF->getName().str() + ":" +
674 FuncInfo->MBB->getBasicBlock()->getName().str();
676 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
677 << " '" << BlockName << "'\n"; CurDAG->dump());
679 if (ViewDAGCombine1 && MatchFilterBB)
680 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
682 // Run the DAG combiner in pre-legalize mode.
684 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
685 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
688 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
689 << " '" << BlockName << "'\n"; CurDAG->dump());
691 // Second step, hack on the DAG until it only uses operations and types that
692 // the target supports.
693 if (ViewLegalizeTypesDAGs && MatchFilterBB)
694 CurDAG->viewGraph("legalize-types input for " + BlockName);
698 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
699 Changed = CurDAG->LegalizeTypes();
702 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
703 << " '" << BlockName << "'\n"; CurDAG->dump());
705 CurDAG->NewNodesMustHaveLegalTypes = true;
708 if (ViewDAGCombineLT && MatchFilterBB)
709 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
711 // Run the DAG combiner in post-type-legalize mode.
713 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
714 TimePassesIsEnabled);
715 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
718 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
719 << " '" << BlockName << "'\n"; CurDAG->dump());
724 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
725 Changed = CurDAG->LegalizeVectors();
730 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
731 CurDAG->LegalizeTypes();
734 if (ViewDAGCombineLT && MatchFilterBB)
735 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
737 // Run the DAG combiner in post-type-legalize mode.
739 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
740 TimePassesIsEnabled);
741 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
744 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
745 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
748 if (ViewLegalizeDAGs && MatchFilterBB)
749 CurDAG->viewGraph("legalize input for " + BlockName);
752 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
756 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
757 << " '" << BlockName << "'\n"; CurDAG->dump());
759 if (ViewDAGCombine2 && MatchFilterBB)
760 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
762 // Run the DAG combiner in post-legalize mode.
764 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
765 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
768 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
769 << " '" << BlockName << "'\n"; CurDAG->dump());
771 if (OptLevel != CodeGenOpt::None)
772 ComputeLiveOutVRegInfo();
774 if (ViewISelDAGs && MatchFilterBB)
775 CurDAG->viewGraph("isel input for " + BlockName);
777 // Third, instruction select all of the operations to machine code, adding the
778 // code to the MachineBasicBlock.
780 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
781 DoInstructionSelection();
784 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
785 << " '" << BlockName << "'\n"; CurDAG->dump());
787 if (ViewSchedDAGs && MatchFilterBB)
788 CurDAG->viewGraph("scheduler input for " + BlockName);
790 // Schedule machine code.
791 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
793 NamedRegionTimer T("Instruction Scheduling", GroupName,
794 TimePassesIsEnabled);
795 Scheduler->Run(CurDAG, FuncInfo->MBB);
798 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
800 // Emit machine code to BB. This can change 'BB' to the last block being
802 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
804 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
806 // FuncInfo->InsertPt is passed by reference and set to the end of the
807 // scheduled instructions.
808 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
811 // If the block was split, make sure we update any references that are used to
812 // update PHI nodes later on.
813 if (FirstMBB != LastMBB)
814 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
816 // Free the scheduler state.
818 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
819 TimePassesIsEnabled);
823 // Free the SelectionDAG state, now that we're finished with it.
828 /// ISelUpdater - helper class to handle updates of the instruction selection
830 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
831 SelectionDAG::allnodes_iterator &ISelPosition;
833 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
834 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
836 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
837 /// deleted is the current ISelPosition node, update ISelPosition.
839 void NodeDeleted(SDNode *N, SDNode *E) override {
840 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
844 } // end anonymous namespace
846 void SelectionDAGISel::DoInstructionSelection() {
847 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
848 << FuncInfo->MBB->getNumber()
849 << " '" << FuncInfo->MBB->getName() << "'\n");
853 // Select target instructions for the DAG.
855 // Number all nodes with a topological order and set DAGSize.
856 DAGSize = CurDAG->AssignTopologicalOrder();
858 // Create a dummy node (which is not added to allnodes), that adds
859 // a reference to the root node, preventing it from being deleted,
860 // and tracking any changes of the root.
861 HandleSDNode Dummy(CurDAG->getRoot());
862 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
865 // Make sure that ISelPosition gets properly updated when nodes are deleted
866 // in calls made from this function.
867 ISelUpdater ISU(*CurDAG, ISelPosition);
869 // The AllNodes list is now topological-sorted. Visit the
870 // nodes by starting at the end of the list (the root of the
871 // graph) and preceding back toward the beginning (the entry
873 while (ISelPosition != CurDAG->allnodes_begin()) {
874 SDNode *Node = --ISelPosition;
875 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
876 // but there are currently some corner cases that it misses. Also, this
877 // makes it theoretically possible to disable the DAGCombiner.
878 if (Node->use_empty())
881 SDNode *ResNode = Select(Node);
883 // FIXME: This is pretty gross. 'Select' should be changed to not return
884 // anything at all and this code should be nuked with a tactical strike.
886 // If node should not be replaced, continue with the next one.
887 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
891 ReplaceUses(Node, ResNode);
894 // If after the replacement this node is not used any more,
895 // remove this dead node.
896 if (Node->use_empty()) // Don't delete EntryToken, etc.
897 CurDAG->RemoveDeadNode(Node);
900 CurDAG->setRoot(Dummy.getValue());
903 DEBUG(dbgs() << "===== Instruction selection ends:\n");
905 PostprocessISelDAG();
908 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
909 /// do other setup for EH landing-pad blocks.
910 void SelectionDAGISel::PrepareEHLandingPad() {
911 MachineBasicBlock *MBB = FuncInfo->MBB;
913 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
915 // Add a label to mark the beginning of the landing pad. Deletion of the
916 // landing pad can thus be detected via the MachineModuleInfo.
917 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
919 // Assign the call site to the landing pad's begin label.
920 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
922 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
923 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
926 if (TM.getMCAsmInfo()->getExceptionHandlingType() ==
927 ExceptionHandling::MSVC) {
928 // Make virtual registers and a series of labels that fill in values for the
930 auto &RI = MF->getRegInfo();
931 FuncInfo->ExceptionSelectorVirtReg = RI.createVirtualRegister(PtrRC);
933 // Get all invoke BBs that will unwind into the clause BBs.
934 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
937 // Emit separate machine basic blocks with separate labels for each clause
938 // before the main landing pad block.
939 const BasicBlock *LLVMBB = MBB->getBasicBlock();
940 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
941 MachineInstrBuilder SelectorPHI = BuildMI(
942 *MBB, MBB->begin(), SDB->getCurDebugLoc(), TII->get(TargetOpcode::PHI),
943 FuncInfo->ExceptionSelectorVirtReg);
944 for (unsigned I = 0, E = LPadInst->getNumClauses(); I != E; ++I) {
945 // Skip filter clauses, we can't implement them yet.
946 if (LPadInst->isFilter(I))
949 MachineBasicBlock *ClauseBB = MF->CreateMachineBasicBlock(LLVMBB);
950 MF->insert(MBB, ClauseBB);
952 // Add the edge from the invoke to the clause.
953 for (MachineBasicBlock *InvokeBB : InvokeBBs)
954 InvokeBB->addSuccessor(ClauseBB);
956 // Mark the clause as a landing pad or MI passes will delete it.
957 ClauseBB->setIsLandingPad();
959 GlobalValue *ClauseGV = ExtractTypeInfo(LPadInst->getClause(I));
961 // Start the BB with a label.
962 MCSymbol *ClauseLabel = MF->getMMI().addClauseForLandingPad(MBB);
963 BuildMI(*ClauseBB, ClauseBB->begin(), SDB->getCurDebugLoc(), II)
964 .addSym(ClauseLabel);
966 // Construct a simple BB that defines a register with the typeid constant.
967 FuncInfo->MBB = ClauseBB;
968 FuncInfo->InsertPt = ClauseBB->end();
969 unsigned VReg = SDB->visitLandingPadClauseBB(ClauseGV, MBB);
970 CurDAG->setRoot(SDB->getRoot());
974 // Add the typeid virtual register to the phi in the main landing pad.
975 SelectorPHI.addReg(VReg).addMBB(ClauseBB);
978 // Remove the edge from the invoke to the lpad.
979 for (MachineBasicBlock *InvokeBB : InvokeBBs)
980 InvokeBB->removeSuccessor(MBB);
982 // Restore FuncInfo back to its previous state and select the main landing
985 FuncInfo->InsertPt = MBB->end();
989 // Mark exception register as live in.
990 if (unsigned Reg = TLI->getExceptionPointerRegister())
991 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
993 // Mark exception selector register as live in.
994 if (unsigned Reg = TLI->getExceptionSelectorRegister())
995 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
998 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
999 /// side-effect free and is either dead or folded into a generated instruction.
1000 /// Return false if it needs to be emitted.
1001 static bool isFoldedOrDeadInstruction(const Instruction *I,
1002 FunctionLoweringInfo *FuncInfo) {
1003 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1004 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1005 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1006 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
1007 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1011 // Collect per Instruction statistics for fast-isel misses. Only those
1012 // instructions that cause the bail are accounted for. It does not account for
1013 // instructions higher in the block. Thus, summing the per instructions stats
1014 // will not add up to what is reported by NumFastIselFailures.
1015 static void collectFailStats(const Instruction *I) {
1016 switch (I->getOpcode()) {
1017 default: assert (0 && "<Invalid operator> ");
1020 case Instruction::Ret: NumFastIselFailRet++; return;
1021 case Instruction::Br: NumFastIselFailBr++; return;
1022 case Instruction::Switch: NumFastIselFailSwitch++; return;
1023 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1024 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1025 case Instruction::Resume: NumFastIselFailResume++; return;
1026 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1028 // Standard binary operators...
1029 case Instruction::Add: NumFastIselFailAdd++; return;
1030 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1031 case Instruction::Sub: NumFastIselFailSub++; return;
1032 case Instruction::FSub: NumFastIselFailFSub++; return;
1033 case Instruction::Mul: NumFastIselFailMul++; return;
1034 case Instruction::FMul: NumFastIselFailFMul++; return;
1035 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1036 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1037 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1038 case Instruction::URem: NumFastIselFailURem++; return;
1039 case Instruction::SRem: NumFastIselFailSRem++; return;
1040 case Instruction::FRem: NumFastIselFailFRem++; return;
1042 // Logical operators...
1043 case Instruction::And: NumFastIselFailAnd++; return;
1044 case Instruction::Or: NumFastIselFailOr++; return;
1045 case Instruction::Xor: NumFastIselFailXor++; return;
1047 // Memory instructions...
1048 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1049 case Instruction::Load: NumFastIselFailLoad++; return;
1050 case Instruction::Store: NumFastIselFailStore++; return;
1051 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1052 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1053 case Instruction::Fence: NumFastIselFailFence++; return;
1054 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1056 // Convert instructions...
1057 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1058 case Instruction::ZExt: NumFastIselFailZExt++; return;
1059 case Instruction::SExt: NumFastIselFailSExt++; return;
1060 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1061 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1062 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1063 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1064 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1065 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1066 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1067 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1068 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1070 // Other instructions...
1071 case Instruction::ICmp: NumFastIselFailICmp++; return;
1072 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1073 case Instruction::PHI: NumFastIselFailPHI++; return;
1074 case Instruction::Select: NumFastIselFailSelect++; return;
1075 case Instruction::Call: {
1076 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1077 switch (Intrinsic->getIntrinsicID()) {
1079 NumFastIselFailIntrinsicCall++; return;
1080 case Intrinsic::sadd_with_overflow:
1081 NumFastIselFailSAddWithOverflow++; return;
1082 case Intrinsic::uadd_with_overflow:
1083 NumFastIselFailUAddWithOverflow++; return;
1084 case Intrinsic::ssub_with_overflow:
1085 NumFastIselFailSSubWithOverflow++; return;
1086 case Intrinsic::usub_with_overflow:
1087 NumFastIselFailUSubWithOverflow++; return;
1088 case Intrinsic::smul_with_overflow:
1089 NumFastIselFailSMulWithOverflow++; return;
1090 case Intrinsic::umul_with_overflow:
1091 NumFastIselFailUMulWithOverflow++; return;
1092 case Intrinsic::frameaddress:
1093 NumFastIselFailFrameaddress++; return;
1094 case Intrinsic::sqrt:
1095 NumFastIselFailSqrt++; return;
1096 case Intrinsic::experimental_stackmap:
1097 NumFastIselFailStackMap++; return;
1098 case Intrinsic::experimental_patchpoint_void: // fall-through
1099 case Intrinsic::experimental_patchpoint_i64:
1100 NumFastIselFailPatchPoint++; return;
1103 NumFastIselFailCall++;
1106 case Instruction::Shl: NumFastIselFailShl++; return;
1107 case Instruction::LShr: NumFastIselFailLShr++; return;
1108 case Instruction::AShr: NumFastIselFailAShr++; return;
1109 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1110 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1111 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1112 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1113 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1114 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1115 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1120 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1121 // Initialize the Fast-ISel state, if needed.
1122 FastISel *FastIS = nullptr;
1123 if (TM.Options.EnableFastISel)
1124 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1126 // Iterate over all basic blocks in the function.
1127 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1128 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1129 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1130 const BasicBlock *LLVMBB = *I;
1132 if (OptLevel != CodeGenOpt::None) {
1133 bool AllPredsVisited = true;
1134 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1136 if (!FuncInfo->VisitedBBs.count(*PI)) {
1137 AllPredsVisited = false;
1142 if (AllPredsVisited) {
1143 for (BasicBlock::const_iterator I = LLVMBB->begin();
1144 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1145 FuncInfo->ComputePHILiveOutRegInfo(PN);
1147 for (BasicBlock::const_iterator I = LLVMBB->begin();
1148 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1149 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1152 FuncInfo->VisitedBBs.insert(LLVMBB);
1155 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1156 BasicBlock::const_iterator const End = LLVMBB->end();
1157 BasicBlock::const_iterator BI = End;
1159 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1160 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1162 // Setup an EH landing-pad block.
1163 FuncInfo->ExceptionPointerVirtReg = 0;
1164 FuncInfo->ExceptionSelectorVirtReg = 0;
1165 if (FuncInfo->MBB->isLandingPad())
1166 PrepareEHLandingPad();
1168 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1170 FastIS->startNewBlock();
1172 // Emit code for any incoming arguments. This must happen before
1173 // beginning FastISel on the entry block.
1174 if (LLVMBB == &Fn.getEntryBlock()) {
1177 // Lower any arguments needed in this block if this is the entry block.
1178 if (!FastIS->lowerArguments()) {
1179 // Fast isel failed to lower these arguments
1180 ++NumFastIselFailLowerArguments;
1181 if (EnableFastISelAbortArgs)
1182 llvm_unreachable("FastISel didn't lower all arguments");
1184 // Use SelectionDAG argument lowering
1186 CurDAG->setRoot(SDB->getControlRoot());
1188 CodeGenAndEmitDAG();
1191 // If we inserted any instructions at the beginning, make a note of
1192 // where they are, so we can be sure to emit subsequent instructions
1194 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1195 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1197 FastIS->setLastLocalValue(nullptr);
1200 unsigned NumFastIselRemaining = std::distance(Begin, End);
1201 // Do FastISel on as many instructions as possible.
1202 for (; BI != Begin; --BI) {
1203 const Instruction *Inst = std::prev(BI);
1205 // If we no longer require this instruction, skip it.
1206 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1207 --NumFastIselRemaining;
1211 // Bottom-up: reset the insert pos at the top, after any local-value
1213 FastIS->recomputeInsertPt();
1215 // Try to select the instruction with FastISel.
1216 if (FastIS->selectInstruction(Inst)) {
1217 --NumFastIselRemaining;
1218 ++NumFastIselSuccess;
1219 // If fast isel succeeded, skip over all the folded instructions, and
1220 // then see if there is a load right before the selected instructions.
1221 // Try to fold the load if so.
1222 const Instruction *BeforeInst = Inst;
1223 while (BeforeInst != Begin) {
1224 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1225 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1228 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1229 BeforeInst->hasOneUse() &&
1230 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1231 // If we succeeded, don't re-select the load.
1232 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1233 --NumFastIselRemaining;
1234 ++NumFastIselSuccess;
1240 if (EnableFastISelVerbose2)
1241 collectFailStats(Inst);
1244 // Then handle certain instructions as single-LLVM-Instruction blocks.
1245 if (isa<CallInst>(Inst)) {
1247 if (EnableFastISelVerbose || EnableFastISelAbort) {
1248 dbgs() << "FastISel missed call: ";
1252 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1253 unsigned &R = FuncInfo->ValueMap[Inst];
1255 R = FuncInfo->CreateRegs(Inst->getType());
1258 bool HadTailCall = false;
1259 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1260 SelectBasicBlock(Inst, BI, HadTailCall);
1262 // If the call was emitted as a tail call, we're done with the block.
1263 // We also need to delete any previously emitted instructions.
1265 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1270 // Recompute NumFastIselRemaining as Selection DAG instruction
1271 // selection may have handled the call, input args, etc.
1272 unsigned RemainingNow = std::distance(Begin, BI);
1273 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1274 NumFastIselRemaining = RemainingNow;
1278 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1279 // Don't abort, and use a different message for terminator misses.
1280 NumFastIselFailures += NumFastIselRemaining;
1281 if (EnableFastISelVerbose || EnableFastISelAbort) {
1282 dbgs() << "FastISel missed terminator: ";
1286 NumFastIselFailures += NumFastIselRemaining;
1287 if (EnableFastISelVerbose || EnableFastISelAbort) {
1288 dbgs() << "FastISel miss: ";
1291 if (EnableFastISelAbort)
1292 // The "fast" selector couldn't handle something and bailed.
1293 // For the purpose of debugging, just abort.
1294 llvm_unreachable("FastISel didn't select the entire block");
1299 FastIS->recomputeInsertPt();
1301 // Lower any arguments needed in this block if this is the entry block.
1302 if (LLVMBB == &Fn.getEntryBlock()) {
1311 ++NumFastIselBlocks;
1314 // Run SelectionDAG instruction selection on the remainder of the block
1315 // not handled by FastISel. If FastISel is not run, this is the entire
1318 SelectBasicBlock(Begin, BI, HadTailCall);
1322 FuncInfo->PHINodesToUpdate.clear();
1326 SDB->clearDanglingDebugInfo();
1327 SDB->SPDescriptor.resetPerFunctionState();
1330 /// Given that the input MI is before a partial terminator sequence TSeq, return
1331 /// true if M + TSeq also a partial terminator sequence.
1333 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1334 /// lowering copy vregs into physical registers, which are then passed into
1335 /// terminator instructors so we can satisfy ABI constraints. A partial
1336 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1337 /// may be the whole terminator sequence).
1338 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1339 // If we do not have a copy or an implicit def, we return true if and only if
1340 // MI is a debug value.
1341 if (!MI->isCopy() && !MI->isImplicitDef())
1342 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1343 // physical registers if there is debug info associated with the terminator
1344 // of our mbb. We want to include said debug info in our terminator
1345 // sequence, so we return true in that case.
1346 return MI->isDebugValue();
1348 // We have left the terminator sequence if we are not doing one of the
1351 // 1. Copying a vreg into a physical register.
1352 // 2. Copying a vreg into a vreg.
1353 // 3. Defining a register via an implicit def.
1355 // OPI should always be a register definition...
1356 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1357 if (!OPI->isReg() || !OPI->isDef())
1360 // Defining any register via an implicit def is always ok.
1361 if (MI->isImplicitDef())
1364 // Grab the copy source...
1365 MachineInstr::const_mop_iterator OPI2 = OPI;
1367 assert(OPI2 != MI->operands_end()
1368 && "Should have a copy implying we should have 2 arguments.");
1370 // Make sure that the copy dest is not a vreg when the copy source is a
1371 // physical register.
1372 if (!OPI2->isReg() ||
1373 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1374 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1380 /// Find the split point at which to splice the end of BB into its success stack
1381 /// protector check machine basic block.
1383 /// On many platforms, due to ABI constraints, terminators, even before register
1384 /// allocation, use physical registers. This creates an issue for us since
1385 /// physical registers at this point can not travel across basic
1386 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1387 /// when they enter functions and moves them through a sequence of copies back
1388 /// into the physical registers right before the terminator creating a
1389 /// ``Terminator Sequence''. This function is searching for the beginning of the
1390 /// terminator sequence so that we can ensure that we splice off not just the
1391 /// terminator, but additionally the copies that move the vregs into the
1392 /// physical registers.
1393 static MachineBasicBlock::iterator
1394 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1395 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1397 if (SplitPoint == BB->begin())
1400 MachineBasicBlock::iterator Start = BB->begin();
1401 MachineBasicBlock::iterator Previous = SplitPoint;
1404 while (MIIsInTerminatorSequence(Previous)) {
1405 SplitPoint = Previous;
1406 if (Previous == Start)
1415 SelectionDAGISel::FinishBasicBlock() {
1417 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1418 << FuncInfo->PHINodesToUpdate.size() << "\n";
1419 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1420 dbgs() << "Node " << i << " : ("
1421 << FuncInfo->PHINodesToUpdate[i].first
1422 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1424 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1425 SDB->JTCases.empty() &&
1426 SDB->BitTestCases.empty();
1428 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1429 // PHI nodes in successors.
1430 if (MustUpdatePHINodes) {
1431 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1432 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1433 assert(PHI->isPHI() &&
1434 "This is not a machine PHI node that we are updating!");
1435 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1437 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1441 // Handle stack protector.
1442 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1443 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1444 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1446 // Find the split point to split the parent mbb. At the same time copy all
1447 // physical registers used in the tail of parent mbb into virtual registers
1448 // before the split point and back into physical registers after the split
1449 // point. This prevents us needing to deal with Live-ins and many other
1450 // register allocation issues caused by us splitting the parent mbb. The
1451 // register allocator will clean up said virtual copies later on.
1452 MachineBasicBlock::iterator SplitPoint =
1453 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1455 // Splice the terminator of ParentMBB into SuccessMBB.
1456 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1460 // Add compare/jump on neq/jump to the parent BB.
1461 FuncInfo->MBB = ParentMBB;
1462 FuncInfo->InsertPt = ParentMBB->end();
1463 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1464 CurDAG->setRoot(SDB->getRoot());
1466 CodeGenAndEmitDAG();
1468 // CodeGen Failure MBB if we have not codegened it yet.
1469 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1470 if (!FailureMBB->size()) {
1471 FuncInfo->MBB = FailureMBB;
1472 FuncInfo->InsertPt = FailureMBB->end();
1473 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1474 CurDAG->setRoot(SDB->getRoot());
1476 CodeGenAndEmitDAG();
1479 // Clear the Per-BB State.
1480 SDB->SPDescriptor.resetPerBBState();
1483 // If we updated PHI Nodes, return early.
1484 if (MustUpdatePHINodes)
1487 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1488 // Lower header first, if it wasn't already lowered
1489 if (!SDB->BitTestCases[i].Emitted) {
1490 // Set the current basic block to the mbb we wish to insert the code into
1491 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1492 FuncInfo->InsertPt = FuncInfo->MBB->end();
1494 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1495 CurDAG->setRoot(SDB->getRoot());
1497 CodeGenAndEmitDAG();
1500 uint32_t UnhandledWeight = 0;
1501 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1502 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1504 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1505 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1506 // Set the current basic block to the mbb we wish to insert the code into
1507 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1508 FuncInfo->InsertPt = FuncInfo->MBB->end();
1511 SDB->visitBitTestCase(SDB->BitTestCases[i],
1512 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1514 SDB->BitTestCases[i].Reg,
1515 SDB->BitTestCases[i].Cases[j],
1518 SDB->visitBitTestCase(SDB->BitTestCases[i],
1519 SDB->BitTestCases[i].Default,
1521 SDB->BitTestCases[i].Reg,
1522 SDB->BitTestCases[i].Cases[j],
1526 CurDAG->setRoot(SDB->getRoot());
1528 CodeGenAndEmitDAG();
1532 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1534 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1535 MachineBasicBlock *PHIBB = PHI->getParent();
1536 assert(PHI->isPHI() &&
1537 "This is not a machine PHI node that we are updating!");
1538 // This is "default" BB. We have two jumps to it. From "header" BB and
1539 // from last "case" BB.
1540 if (PHIBB == SDB->BitTestCases[i].Default)
1541 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1542 .addMBB(SDB->BitTestCases[i].Parent)
1543 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1544 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1545 // One of "cases" BB.
1546 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1548 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1549 if (cBB->isSuccessor(PHIBB))
1550 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1554 SDB->BitTestCases.clear();
1556 // If the JumpTable record is filled in, then we need to emit a jump table.
1557 // Updating the PHI nodes is tricky in this case, since we need to determine
1558 // whether the PHI is a successor of the range check MBB or the jump table MBB
1559 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1560 // Lower header first, if it wasn't already lowered
1561 if (!SDB->JTCases[i].first.Emitted) {
1562 // Set the current basic block to the mbb we wish to insert the code into
1563 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1564 FuncInfo->InsertPt = FuncInfo->MBB->end();
1566 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1568 CurDAG->setRoot(SDB->getRoot());
1570 CodeGenAndEmitDAG();
1573 // Set the current basic block to the mbb we wish to insert the code into
1574 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1575 FuncInfo->InsertPt = FuncInfo->MBB->end();
1577 SDB->visitJumpTable(SDB->JTCases[i].second);
1578 CurDAG->setRoot(SDB->getRoot());
1580 CodeGenAndEmitDAG();
1583 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1585 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1586 MachineBasicBlock *PHIBB = PHI->getParent();
1587 assert(PHI->isPHI() &&
1588 "This is not a machine PHI node that we are updating!");
1589 // "default" BB. We can go there only from header BB.
1590 if (PHIBB == SDB->JTCases[i].second.Default)
1591 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1592 .addMBB(SDB->JTCases[i].first.HeaderBB);
1593 // JT BB. Just iterate over successors here
1594 if (FuncInfo->MBB->isSuccessor(PHIBB))
1595 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1598 SDB->JTCases.clear();
1600 // If the switch block involved a branch to one of the actual successors, we
1601 // need to update PHI nodes in that block.
1602 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1603 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1604 assert(PHI->isPHI() &&
1605 "This is not a machine PHI node that we are updating!");
1606 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1607 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1610 // If we generated any switch lowering information, build and codegen any
1611 // additional DAGs necessary.
1612 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1613 // Set the current basic block to the mbb we wish to insert the code into
1614 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1615 FuncInfo->InsertPt = FuncInfo->MBB->end();
1617 // Determine the unique successors.
1618 SmallVector<MachineBasicBlock *, 2> Succs;
1619 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1620 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1621 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1623 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1624 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1625 CurDAG->setRoot(SDB->getRoot());
1627 CodeGenAndEmitDAG();
1629 // Remember the last block, now that any splitting is done, for use in
1630 // populating PHI nodes in successors.
1631 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1633 // Handle any PHI nodes in successors of this chunk, as if we were coming
1634 // from the original BB before switch expansion. Note that PHI nodes can
1635 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1636 // handle them the right number of times.
1637 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1638 FuncInfo->MBB = Succs[i];
1639 FuncInfo->InsertPt = FuncInfo->MBB->end();
1640 // FuncInfo->MBB may have been removed from the CFG if a branch was
1642 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1643 for (MachineBasicBlock::iterator
1644 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1645 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1646 MachineInstrBuilder PHI(*MF, MBBI);
1647 // This value for this PHI node is recorded in PHINodesToUpdate.
1648 for (unsigned pn = 0; ; ++pn) {
1649 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1650 "Didn't find PHI entry!");
1651 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1652 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1660 SDB->SwitchCases.clear();
1664 /// Create the scheduler. If a specific scheduler was specified
1665 /// via the SchedulerRegistry, use it, otherwise select the
1666 /// one preferred by the target.
1668 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1669 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1673 RegisterScheduler::setDefault(Ctor);
1676 return Ctor(this, OptLevel);
1679 //===----------------------------------------------------------------------===//
1680 // Helper functions used by the generated instruction selector.
1681 //===----------------------------------------------------------------------===//
1682 // Calls to these methods are generated by tblgen.
1684 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1685 /// the dag combiner simplified the 255, we still want to match. RHS is the
1686 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1687 /// specified in the .td file (e.g. 255).
1688 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1689 int64_t DesiredMaskS) const {
1690 const APInt &ActualMask = RHS->getAPIntValue();
1691 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1693 // If the actual mask exactly matches, success!
1694 if (ActualMask == DesiredMask)
1697 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1698 if (ActualMask.intersects(~DesiredMask))
1701 // Otherwise, the DAG Combiner may have proven that the value coming in is
1702 // either already zero or is not demanded. Check for known zero input bits.
1703 APInt NeededMask = DesiredMask & ~ActualMask;
1704 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1707 // TODO: check to see if missing bits are just not demanded.
1709 // Otherwise, this pattern doesn't match.
1713 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1714 /// the dag combiner simplified the 255, we still want to match. RHS is the
1715 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1716 /// specified in the .td file (e.g. 255).
1717 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1718 int64_t DesiredMaskS) const {
1719 const APInt &ActualMask = RHS->getAPIntValue();
1720 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1722 // If the actual mask exactly matches, success!
1723 if (ActualMask == DesiredMask)
1726 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1727 if (ActualMask.intersects(~DesiredMask))
1730 // Otherwise, the DAG Combiner may have proven that the value coming in is
1731 // either already zero or is not demanded. Check for known zero input bits.
1732 APInt NeededMask = DesiredMask & ~ActualMask;
1734 APInt KnownZero, KnownOne;
1735 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1737 // If all the missing bits in the or are already known to be set, match!
1738 if ((NeededMask & KnownOne) == NeededMask)
1741 // TODO: check to see if missing bits are just not demanded.
1743 // Otherwise, this pattern doesn't match.
1748 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1749 /// by tblgen. Others should not call it.
1750 void SelectionDAGISel::
1751 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1752 std::vector<SDValue> InOps;
1753 std::swap(InOps, Ops);
1755 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1756 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1757 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1758 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1760 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1761 if (InOps[e-1].getValueType() == MVT::Glue)
1762 --e; // Don't process a glue operand if it is here.
1765 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1766 if (!InlineAsm::isMemKind(Flags)) {
1767 // Just skip over this operand, copying the operands verbatim.
1768 Ops.insert(Ops.end(), InOps.begin()+i,
1769 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1770 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1772 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1773 "Memory operand with multiple values?");
1774 // Otherwise, this is a memory operand. Ask the target to select it.
1775 std::vector<SDValue> SelOps;
1776 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1777 report_fatal_error("Could not match memory address. Inline asm"
1780 // Add this to the output node.
1782 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1783 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1784 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1789 // Add the glue input back if present.
1790 if (e != InOps.size())
1791 Ops.push_back(InOps.back());
1794 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1797 static SDNode *findGlueUse(SDNode *N) {
1798 unsigned FlagResNo = N->getNumValues()-1;
1799 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1800 SDUse &Use = I.getUse();
1801 if (Use.getResNo() == FlagResNo)
1802 return Use.getUser();
1807 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1808 /// This function recursively traverses up the operand chain, ignoring
1810 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1811 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1812 bool IgnoreChains) {
1813 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1814 // greater than all of its (recursive) operands. If we scan to a point where
1815 // 'use' is smaller than the node we're scanning for, then we know we will
1818 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1819 // happen because we scan down to newly selected nodes in the case of glue
1821 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1824 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1825 // won't fail if we scan it again.
1826 if (!Visited.insert(Use).second)
1829 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1830 // Ignore chain uses, they are validated by HandleMergeInputChains.
1831 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1834 SDNode *N = Use->getOperand(i).getNode();
1836 if (Use == ImmedUse || Use == Root)
1837 continue; // We are not looking for immediate use.
1842 // Traverse up the operand chain.
1843 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1849 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1850 /// operand node N of U during instruction selection that starts at Root.
1851 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1852 SDNode *Root) const {
1853 if (OptLevel == CodeGenOpt::None) return false;
1854 return N.hasOneUse();
1857 /// IsLegalToFold - Returns true if the specific operand node N of
1858 /// U can be folded during instruction selection that starts at Root.
1859 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1860 CodeGenOpt::Level OptLevel,
1861 bool IgnoreChains) {
1862 if (OptLevel == CodeGenOpt::None) return false;
1864 // If Root use can somehow reach N through a path that that doesn't contain
1865 // U then folding N would create a cycle. e.g. In the following
1866 // diagram, Root can reach N through X. If N is folded into into Root, then
1867 // X is both a predecessor and a successor of U.
1878 // * indicates nodes to be folded together.
1880 // If Root produces glue, then it gets (even more) interesting. Since it
1881 // will be "glued" together with its glue use in the scheduler, we need to
1882 // check if it might reach N.
1901 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1902 // (call it Fold), then X is a predecessor of GU and a successor of
1903 // Fold. But since Fold and GU are glued together, this will create
1904 // a cycle in the scheduling graph.
1906 // If the node has glue, walk down the graph to the "lowest" node in the
1908 EVT VT = Root->getValueType(Root->getNumValues()-1);
1909 while (VT == MVT::Glue) {
1910 SDNode *GU = findGlueUse(Root);
1914 VT = Root->getValueType(Root->getNumValues()-1);
1916 // If our query node has a glue result with a use, we've walked up it. If
1917 // the user (which has already been selected) has a chain or indirectly uses
1918 // the chain, our WalkChainUsers predicate will not consider it. Because of
1919 // this, we cannot ignore chains in this predicate.
1920 IgnoreChains = false;
1924 SmallPtrSet<SDNode*, 16> Visited;
1925 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1928 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1929 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1930 SelectInlineAsmMemoryOperands(Ops);
1932 EVT VTs[] = { MVT::Other, MVT::Glue };
1933 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1935 return New.getNode();
1939 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1941 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1942 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1944 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1945 SDValue New = CurDAG->getCopyFromReg(
1946 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1948 return New.getNode();
1952 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1954 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1955 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1956 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1957 Op->getOperand(2).getValueType());
1958 SDValue New = CurDAG->getCopyToReg(
1959 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
1961 return New.getNode();
1966 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1967 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1970 /// GetVBR - decode a vbr encoding whose top bit is set.
1971 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1972 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1973 assert(Val >= 128 && "Not a VBR");
1974 Val &= 127; // Remove first vbr bit.
1979 NextBits = MatcherTable[Idx++];
1980 Val |= (NextBits&127) << Shift;
1982 } while (NextBits & 128);
1988 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1989 /// interior glue and chain results to use the new glue and chain results.
1990 void SelectionDAGISel::
1991 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1992 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1994 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1995 bool isMorphNodeTo) {
1996 SmallVector<SDNode*, 4> NowDeadNodes;
1998 // Now that all the normal results are replaced, we replace the chain and
1999 // glue results if present.
2000 if (!ChainNodesMatched.empty()) {
2001 assert(InputChain.getNode() &&
2002 "Matched input chains but didn't produce a chain");
2003 // Loop over all of the nodes we matched that produced a chain result.
2004 // Replace all the chain results with the final chain we ended up with.
2005 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2006 SDNode *ChainNode = ChainNodesMatched[i];
2008 // If this node was already deleted, don't look at it.
2009 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2012 // Don't replace the results of the root node if we're doing a
2014 if (ChainNode == NodeToMatch && isMorphNodeTo)
2017 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2018 if (ChainVal.getValueType() == MVT::Glue)
2019 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2020 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2021 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2023 // If the node became dead and we haven't already seen it, delete it.
2024 if (ChainNode->use_empty() &&
2025 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2026 NowDeadNodes.push_back(ChainNode);
2030 // If the result produces glue, update any glue results in the matched
2031 // pattern with the glue result.
2032 if (InputGlue.getNode()) {
2033 // Handle any interior nodes explicitly marked.
2034 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2035 SDNode *FRN = GlueResultNodesMatched[i];
2037 // If this node was already deleted, don't look at it.
2038 if (FRN->getOpcode() == ISD::DELETED_NODE)
2041 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2042 "Doesn't have a glue result");
2043 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2046 // If the node became dead and we haven't already seen it, delete it.
2047 if (FRN->use_empty() &&
2048 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2049 NowDeadNodes.push_back(FRN);
2053 if (!NowDeadNodes.empty())
2054 CurDAG->RemoveDeadNodes(NowDeadNodes);
2056 DEBUG(dbgs() << "ISEL: Match complete!\n");
2062 CR_LeadsToInteriorNode
2065 /// WalkChainUsers - Walk down the users of the specified chained node that is
2066 /// part of the pattern we're matching, looking at all of the users we find.
2067 /// This determines whether something is an interior node, whether we have a
2068 /// non-pattern node in between two pattern nodes (which prevent folding because
2069 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2070 /// between pattern nodes (in which case the TF becomes part of the pattern).
2072 /// The walk we do here is guaranteed to be small because we quickly get down to
2073 /// already selected nodes "below" us.
2075 WalkChainUsers(const SDNode *ChainedNode,
2076 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2077 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2078 ChainResult Result = CR_Simple;
2080 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2081 E = ChainedNode->use_end(); UI != E; ++UI) {
2082 // Make sure the use is of the chain, not some other value we produce.
2083 if (UI.getUse().getValueType() != MVT::Other) continue;
2087 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2090 // If we see an already-selected machine node, then we've gone beyond the
2091 // pattern that we're selecting down into the already selected chunk of the
2093 unsigned UserOpcode = User->getOpcode();
2094 if (User->isMachineOpcode() ||
2095 UserOpcode == ISD::CopyToReg ||
2096 UserOpcode == ISD::CopyFromReg ||
2097 UserOpcode == ISD::INLINEASM ||
2098 UserOpcode == ISD::EH_LABEL ||
2099 UserOpcode == ISD::LIFETIME_START ||
2100 UserOpcode == ISD::LIFETIME_END) {
2101 // If their node ID got reset to -1 then they've already been selected.
2102 // Treat them like a MachineOpcode.
2103 if (User->getNodeId() == -1)
2107 // If we have a TokenFactor, we handle it specially.
2108 if (User->getOpcode() != ISD::TokenFactor) {
2109 // If the node isn't a token factor and isn't part of our pattern, then it
2110 // must be a random chained node in between two nodes we're selecting.
2111 // This happens when we have something like:
2116 // Because we structurally match the load/store as a read/modify/write,
2117 // but the call is chained between them. We cannot fold in this case
2118 // because it would induce a cycle in the graph.
2119 if (!std::count(ChainedNodesInPattern.begin(),
2120 ChainedNodesInPattern.end(), User))
2121 return CR_InducesCycle;
2123 // Otherwise we found a node that is part of our pattern. For example in:
2127 // This would happen when we're scanning down from the load and see the
2128 // store as a user. Record that there is a use of ChainedNode that is
2129 // part of the pattern and keep scanning uses.
2130 Result = CR_LeadsToInteriorNode;
2131 InteriorChainedNodes.push_back(User);
2135 // If we found a TokenFactor, there are two cases to consider: first if the
2136 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2137 // uses of the TF are in our pattern) we just want to ignore it. Second,
2138 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2144 // | \ DAG's like cheese
2147 // [TokenFactor] [Op]
2154 // In this case, the TokenFactor becomes part of our match and we rewrite it
2155 // as a new TokenFactor.
2157 // To distinguish these two cases, do a recursive walk down the uses.
2158 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2160 // If the uses of the TokenFactor are just already-selected nodes, ignore
2161 // it, it is "below" our pattern.
2163 case CR_InducesCycle:
2164 // If the uses of the TokenFactor lead to nodes that are not part of our
2165 // pattern that are not selected, folding would turn this into a cycle,
2167 return CR_InducesCycle;
2168 case CR_LeadsToInteriorNode:
2169 break; // Otherwise, keep processing.
2172 // Okay, we know we're in the interesting interior case. The TokenFactor
2173 // is now going to be considered part of the pattern so that we rewrite its
2174 // uses (it may have uses that are not part of the pattern) with the
2175 // ultimate chain result of the generated code. We will also add its chain
2176 // inputs as inputs to the ultimate TokenFactor we create.
2177 Result = CR_LeadsToInteriorNode;
2178 ChainedNodesInPattern.push_back(User);
2179 InteriorChainedNodes.push_back(User);
2186 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2187 /// operation for when the pattern matched at least one node with a chains. The
2188 /// input vector contains a list of all of the chained nodes that we match. We
2189 /// must determine if this is a valid thing to cover (i.e. matching it won't
2190 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2191 /// be used as the input node chain for the generated nodes.
2193 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2194 SelectionDAG *CurDAG) {
2195 // Walk all of the chained nodes we've matched, recursively scanning down the
2196 // users of the chain result. This adds any TokenFactor nodes that are caught
2197 // in between chained nodes to the chained and interior nodes list.
2198 SmallVector<SDNode*, 3> InteriorChainedNodes;
2199 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2200 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2201 InteriorChainedNodes) == CR_InducesCycle)
2202 return SDValue(); // Would induce a cycle.
2205 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2206 // that we are interested in. Form our input TokenFactor node.
2207 SmallVector<SDValue, 3> InputChains;
2208 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2209 // Add the input chain of this node to the InputChains list (which will be
2210 // the operands of the generated TokenFactor) if it's not an interior node.
2211 SDNode *N = ChainNodesMatched[i];
2212 if (N->getOpcode() != ISD::TokenFactor) {
2213 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2216 // Otherwise, add the input chain.
2217 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2218 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2219 InputChains.push_back(InChain);
2223 // If we have a token factor, we want to add all inputs of the token factor
2224 // that are not part of the pattern we're matching.
2225 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2226 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2227 N->getOperand(op).getNode()))
2228 InputChains.push_back(N->getOperand(op));
2232 if (InputChains.size() == 1)
2233 return InputChains[0];
2234 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2235 MVT::Other, InputChains);
2238 /// MorphNode - Handle morphing a node in place for the selector.
2239 SDNode *SelectionDAGISel::
2240 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2241 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2242 // It is possible we're using MorphNodeTo to replace a node with no
2243 // normal results with one that has a normal result (or we could be
2244 // adding a chain) and the input could have glue and chains as well.
2245 // In this case we need to shift the operands down.
2246 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2247 // than the old isel though.
2248 int OldGlueResultNo = -1, OldChainResultNo = -1;
2250 unsigned NTMNumResults = Node->getNumValues();
2251 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2252 OldGlueResultNo = NTMNumResults-1;
2253 if (NTMNumResults != 1 &&
2254 Node->getValueType(NTMNumResults-2) == MVT::Other)
2255 OldChainResultNo = NTMNumResults-2;
2256 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2257 OldChainResultNo = NTMNumResults-1;
2259 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2260 // that this deletes operands of the old node that become dead.
2261 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2263 // MorphNodeTo can operate in two ways: if an existing node with the
2264 // specified operands exists, it can just return it. Otherwise, it
2265 // updates the node in place to have the requested operands.
2267 // If we updated the node in place, reset the node ID. To the isel,
2268 // this should be just like a newly allocated machine node.
2272 unsigned ResNumResults = Res->getNumValues();
2273 // Move the glue if needed.
2274 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2275 (unsigned)OldGlueResultNo != ResNumResults-1)
2276 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2277 SDValue(Res, ResNumResults-1));
2279 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2282 // Move the chain reference if needed.
2283 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2284 (unsigned)OldChainResultNo != ResNumResults-1)
2285 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2286 SDValue(Res, ResNumResults-1));
2288 // Otherwise, no replacement happened because the node already exists. Replace
2289 // Uses of the old node with the new one.
2291 CurDAG->ReplaceAllUsesWith(Node, Res);
2296 /// CheckSame - Implements OP_CheckSame.
2297 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2298 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2300 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2301 // Accept if it is exactly the same as a previously recorded node.
2302 unsigned RecNo = MatcherTable[MatcherIndex++];
2303 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2304 return N == RecordedNodes[RecNo].first;
2307 /// CheckChildSame - Implements OP_CheckChildXSame.
2308 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2309 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2311 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2313 if (ChildNo >= N.getNumOperands())
2314 return false; // Match fails if out of range child #.
2315 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2319 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2320 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2321 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2322 const SelectionDAGISel &SDISel) {
2323 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2326 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2327 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2328 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2329 const SelectionDAGISel &SDISel, SDNode *N) {
2330 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2333 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2334 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2336 uint16_t Opc = MatcherTable[MatcherIndex++];
2337 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2338 return N->getOpcode() == Opc;
2341 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2342 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2343 SDValue N, const TargetLowering *TLI) {
2344 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2345 if (N.getValueType() == VT) return true;
2347 // Handle the case when VT is iPTR.
2348 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2351 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2352 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2353 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2354 if (ChildNo >= N.getNumOperands())
2355 return false; // Match fails if out of range child #.
2356 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2359 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2360 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2362 return cast<CondCodeSDNode>(N)->get() ==
2363 (ISD::CondCode)MatcherTable[MatcherIndex++];
2366 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2367 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2368 SDValue N, const TargetLowering *TLI) {
2369 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2370 if (cast<VTSDNode>(N)->getVT() == VT)
2373 // Handle the case when VT is iPTR.
2374 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2377 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2378 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2380 int64_t Val = MatcherTable[MatcherIndex++];
2382 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2384 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2385 return C && C->getSExtValue() == Val;
2388 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2389 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2390 SDValue N, unsigned ChildNo) {
2391 if (ChildNo >= N.getNumOperands())
2392 return false; // Match fails if out of range child #.
2393 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2396 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2397 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2398 SDValue N, const SelectionDAGISel &SDISel) {
2399 int64_t Val = MatcherTable[MatcherIndex++];
2401 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2403 if (N->getOpcode() != ISD::AND) return false;
2405 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2406 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2409 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2410 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2411 SDValue N, const SelectionDAGISel &SDISel) {
2412 int64_t Val = MatcherTable[MatcherIndex++];
2414 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2416 if (N->getOpcode() != ISD::OR) return false;
2418 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2419 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2422 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2423 /// scope, evaluate the current node. If the current predicate is known to
2424 /// fail, set Result=true and return anything. If the current predicate is
2425 /// known to pass, set Result=false and return the MatcherIndex to continue
2426 /// with. If the current predicate is unknown, set Result=false and return the
2427 /// MatcherIndex to continue with.
2428 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2429 unsigned Index, SDValue N,
2431 const SelectionDAGISel &SDISel,
2432 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2433 switch (Table[Index++]) {
2436 return Index-1; // Could not evaluate this predicate.
2437 case SelectionDAGISel::OPC_CheckSame:
2438 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2440 case SelectionDAGISel::OPC_CheckChild0Same:
2441 case SelectionDAGISel::OPC_CheckChild1Same:
2442 case SelectionDAGISel::OPC_CheckChild2Same:
2443 case SelectionDAGISel::OPC_CheckChild3Same:
2444 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2445 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2447 case SelectionDAGISel::OPC_CheckPatternPredicate:
2448 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2450 case SelectionDAGISel::OPC_CheckPredicate:
2451 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2453 case SelectionDAGISel::OPC_CheckOpcode:
2454 Result = !::CheckOpcode(Table, Index, N.getNode());
2456 case SelectionDAGISel::OPC_CheckType:
2457 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2459 case SelectionDAGISel::OPC_CheckChild0Type:
2460 case SelectionDAGISel::OPC_CheckChild1Type:
2461 case SelectionDAGISel::OPC_CheckChild2Type:
2462 case SelectionDAGISel::OPC_CheckChild3Type:
2463 case SelectionDAGISel::OPC_CheckChild4Type:
2464 case SelectionDAGISel::OPC_CheckChild5Type:
2465 case SelectionDAGISel::OPC_CheckChild6Type:
2466 case SelectionDAGISel::OPC_CheckChild7Type:
2467 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2469 SelectionDAGISel::OPC_CheckChild0Type);
2471 case SelectionDAGISel::OPC_CheckCondCode:
2472 Result = !::CheckCondCode(Table, Index, N);
2474 case SelectionDAGISel::OPC_CheckValueType:
2475 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2477 case SelectionDAGISel::OPC_CheckInteger:
2478 Result = !::CheckInteger(Table, Index, N);
2480 case SelectionDAGISel::OPC_CheckChild0Integer:
2481 case SelectionDAGISel::OPC_CheckChild1Integer:
2482 case SelectionDAGISel::OPC_CheckChild2Integer:
2483 case SelectionDAGISel::OPC_CheckChild3Integer:
2484 case SelectionDAGISel::OPC_CheckChild4Integer:
2485 Result = !::CheckChildInteger(Table, Index, N,
2486 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2488 case SelectionDAGISel::OPC_CheckAndImm:
2489 Result = !::CheckAndImm(Table, Index, N, SDISel);
2491 case SelectionDAGISel::OPC_CheckOrImm:
2492 Result = !::CheckOrImm(Table, Index, N, SDISel);
2500 /// FailIndex - If this match fails, this is the index to continue with.
2503 /// NodeStack - The node stack when the scope was formed.
2504 SmallVector<SDValue, 4> NodeStack;
2506 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2507 unsigned NumRecordedNodes;
2509 /// NumMatchedMemRefs - The number of matched memref entries.
2510 unsigned NumMatchedMemRefs;
2512 /// InputChain/InputGlue - The current chain/glue
2513 SDValue InputChain, InputGlue;
2515 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2516 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2519 /// \\brief A DAG update listener to keep the matching state
2520 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2521 /// change the DAG while matching. X86 addressing mode matcher is an example
2523 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2525 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2526 SmallVectorImpl<MatchScope> &MatchScopes;
2528 MatchStateUpdater(SelectionDAG &DAG,
2529 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2530 SmallVectorImpl<MatchScope> &MS) :
2531 SelectionDAG::DAGUpdateListener(DAG),
2532 RecordedNodes(RN), MatchScopes(MS) { }
2534 void NodeDeleted(SDNode *N, SDNode *E) {
2535 // Some early-returns here to avoid the search if we deleted the node or
2536 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2537 // do, so it's unnecessary to update matching state at that point).
2538 // Neither of these can occur currently because we only install this
2539 // update listener during matching a complex patterns.
2540 if (!E || E->isMachineOpcode())
2542 // Performing linear search here does not matter because we almost never
2543 // run this code. You'd have to have a CSE during complex pattern
2545 for (auto &I : RecordedNodes)
2546 if (I.first.getNode() == N)
2549 for (auto &I : MatchScopes)
2550 for (auto &J : I.NodeStack)
2551 if (J.getNode() == N)
2557 SDNode *SelectionDAGISel::
2558 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2559 unsigned TableSize) {
2560 // FIXME: Should these even be selected? Handle these cases in the caller?
2561 switch (NodeToMatch->getOpcode()) {
2564 case ISD::EntryToken: // These nodes remain the same.
2565 case ISD::BasicBlock:
2567 case ISD::RegisterMask:
2568 case ISD::HANDLENODE:
2569 case ISD::MDNODE_SDNODE:
2570 case ISD::TargetConstant:
2571 case ISD::TargetConstantFP:
2572 case ISD::TargetConstantPool:
2573 case ISD::TargetFrameIndex:
2574 case ISD::TargetExternalSymbol:
2575 case ISD::TargetBlockAddress:
2576 case ISD::TargetJumpTable:
2577 case ISD::TargetGlobalTLSAddress:
2578 case ISD::TargetGlobalAddress:
2579 case ISD::TokenFactor:
2580 case ISD::CopyFromReg:
2581 case ISD::CopyToReg:
2583 case ISD::LIFETIME_START:
2584 case ISD::LIFETIME_END:
2585 NodeToMatch->setNodeId(-1); // Mark selected.
2587 case ISD::AssertSext:
2588 case ISD::AssertZext:
2589 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2590 NodeToMatch->getOperand(0));
2592 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2593 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2594 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2595 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2598 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2600 // Set up the node stack with NodeToMatch as the only node on the stack.
2601 SmallVector<SDValue, 8> NodeStack;
2602 SDValue N = SDValue(NodeToMatch, 0);
2603 NodeStack.push_back(N);
2605 // MatchScopes - Scopes used when matching, if a match failure happens, this
2606 // indicates where to continue checking.
2607 SmallVector<MatchScope, 8> MatchScopes;
2609 // RecordedNodes - This is the set of nodes that have been recorded by the
2610 // state machine. The second value is the parent of the node, or null if the
2611 // root is recorded.
2612 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2614 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2616 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2618 // These are the current input chain and glue for use when generating nodes.
2619 // Various Emit operations change these. For example, emitting a copytoreg
2620 // uses and updates these.
2621 SDValue InputChain, InputGlue;
2623 // ChainNodesMatched - If a pattern matches nodes that have input/output
2624 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2625 // which ones they are. The result is captured into this list so that we can
2626 // update the chain results when the pattern is complete.
2627 SmallVector<SDNode*, 3> ChainNodesMatched;
2628 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2630 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2631 NodeToMatch->dump(CurDAG);
2634 // Determine where to start the interpreter. Normally we start at opcode #0,
2635 // but if the state machine starts with an OPC_SwitchOpcode, then we
2636 // accelerate the first lookup (which is guaranteed to be hot) with the
2637 // OpcodeOffset table.
2638 unsigned MatcherIndex = 0;
2640 if (!OpcodeOffset.empty()) {
2641 // Already computed the OpcodeOffset table, just index into it.
2642 if (N.getOpcode() < OpcodeOffset.size())
2643 MatcherIndex = OpcodeOffset[N.getOpcode()];
2644 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2646 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2647 // Otherwise, the table isn't computed, but the state machine does start
2648 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2649 // is the first time we're selecting an instruction.
2652 // Get the size of this case.
2653 unsigned CaseSize = MatcherTable[Idx++];
2655 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2656 if (CaseSize == 0) break;
2658 // Get the opcode, add the index to the table.
2659 uint16_t Opc = MatcherTable[Idx++];
2660 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2661 if (Opc >= OpcodeOffset.size())
2662 OpcodeOffset.resize((Opc+1)*2);
2663 OpcodeOffset[Opc] = Idx;
2667 // Okay, do the lookup for the first opcode.
2668 if (N.getOpcode() < OpcodeOffset.size())
2669 MatcherIndex = OpcodeOffset[N.getOpcode()];
2673 assert(MatcherIndex < TableSize && "Invalid index");
2675 unsigned CurrentOpcodeIndex = MatcherIndex;
2677 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2680 // Okay, the semantics of this operation are that we should push a scope
2681 // then evaluate the first child. However, pushing a scope only to have
2682 // the first check fail (which then pops it) is inefficient. If we can
2683 // determine immediately that the first check (or first several) will
2684 // immediately fail, don't even bother pushing a scope for them.
2688 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2689 if (NumToSkip & 128)
2690 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2691 // Found the end of the scope with no match.
2692 if (NumToSkip == 0) {
2697 FailIndex = MatcherIndex+NumToSkip;
2699 unsigned MatcherIndexOfPredicate = MatcherIndex;
2700 (void)MatcherIndexOfPredicate; // silence warning.
2702 // If we can't evaluate this predicate without pushing a scope (e.g. if
2703 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2704 // push the scope and evaluate the full predicate chain.
2706 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2707 Result, *this, RecordedNodes);
2711 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2712 << "index " << MatcherIndexOfPredicate
2713 << ", continuing at " << FailIndex << "\n");
2714 ++NumDAGIselRetries;
2716 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2717 // move to the next case.
2718 MatcherIndex = FailIndex;
2721 // If the whole scope failed to match, bail.
2722 if (FailIndex == 0) break;
2724 // Push a MatchScope which indicates where to go if the first child fails
2726 MatchScope NewEntry;
2727 NewEntry.FailIndex = FailIndex;
2728 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2729 NewEntry.NumRecordedNodes = RecordedNodes.size();
2730 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2731 NewEntry.InputChain = InputChain;
2732 NewEntry.InputGlue = InputGlue;
2733 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2734 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2735 MatchScopes.push_back(NewEntry);
2738 case OPC_RecordNode: {
2739 // Remember this node, it may end up being an operand in the pattern.
2740 SDNode *Parent = nullptr;
2741 if (NodeStack.size() > 1)
2742 Parent = NodeStack[NodeStack.size()-2].getNode();
2743 RecordedNodes.push_back(std::make_pair(N, Parent));
2747 case OPC_RecordChild0: case OPC_RecordChild1:
2748 case OPC_RecordChild2: case OPC_RecordChild3:
2749 case OPC_RecordChild4: case OPC_RecordChild5:
2750 case OPC_RecordChild6: case OPC_RecordChild7: {
2751 unsigned ChildNo = Opcode-OPC_RecordChild0;
2752 if (ChildNo >= N.getNumOperands())
2753 break; // Match fails if out of range child #.
2755 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2759 case OPC_RecordMemRef:
2760 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2763 case OPC_CaptureGlueInput:
2764 // If the current node has an input glue, capture it in InputGlue.
2765 if (N->getNumOperands() != 0 &&
2766 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2767 InputGlue = N->getOperand(N->getNumOperands()-1);
2770 case OPC_MoveChild: {
2771 unsigned ChildNo = MatcherTable[MatcherIndex++];
2772 if (ChildNo >= N.getNumOperands())
2773 break; // Match fails if out of range child #.
2774 N = N.getOperand(ChildNo);
2775 NodeStack.push_back(N);
2779 case OPC_MoveParent:
2780 // Pop the current node off the NodeStack.
2781 NodeStack.pop_back();
2782 assert(!NodeStack.empty() && "Node stack imbalance!");
2783 N = NodeStack.back();
2787 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2790 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2791 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2792 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2793 Opcode-OPC_CheckChild0Same))
2797 case OPC_CheckPatternPredicate:
2798 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2800 case OPC_CheckPredicate:
2801 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2805 case OPC_CheckComplexPat: {
2806 unsigned CPNum = MatcherTable[MatcherIndex++];
2807 unsigned RecNo = MatcherTable[MatcherIndex++];
2808 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2810 // If target can modify DAG during matching, keep the matching state
2812 std::unique_ptr<MatchStateUpdater> MSU;
2813 if (ComplexPatternFuncMutatesDAG())
2814 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2817 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2818 RecordedNodes[RecNo].first, CPNum,
2823 case OPC_CheckOpcode:
2824 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2828 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2832 case OPC_SwitchOpcode: {
2833 unsigned CurNodeOpcode = N.getOpcode();
2834 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2837 // Get the size of this case.
2838 CaseSize = MatcherTable[MatcherIndex++];
2840 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2841 if (CaseSize == 0) break;
2843 uint16_t Opc = MatcherTable[MatcherIndex++];
2844 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2846 // If the opcode matches, then we will execute this case.
2847 if (CurNodeOpcode == Opc)
2850 // Otherwise, skip over this case.
2851 MatcherIndex += CaseSize;
2854 // If no cases matched, bail out.
2855 if (CaseSize == 0) break;
2857 // Otherwise, execute the case we found.
2858 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2859 << " to " << MatcherIndex << "\n");
2863 case OPC_SwitchType: {
2864 MVT CurNodeVT = N.getSimpleValueType();
2865 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2868 // Get the size of this case.
2869 CaseSize = MatcherTable[MatcherIndex++];
2871 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2872 if (CaseSize == 0) break;
2874 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2875 if (CaseVT == MVT::iPTR)
2876 CaseVT = TLI->getPointerTy();
2878 // If the VT matches, then we will execute this case.
2879 if (CurNodeVT == CaseVT)
2882 // Otherwise, skip over this case.
2883 MatcherIndex += CaseSize;
2886 // If no cases matched, bail out.
2887 if (CaseSize == 0) break;
2889 // Otherwise, execute the case we found.
2890 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2891 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2894 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2895 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2896 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2897 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2898 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2899 Opcode-OPC_CheckChild0Type))
2902 case OPC_CheckCondCode:
2903 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2905 case OPC_CheckValueType:
2906 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2909 case OPC_CheckInteger:
2910 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2912 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2913 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2914 case OPC_CheckChild4Integer:
2915 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2916 Opcode-OPC_CheckChild0Integer)) break;
2918 case OPC_CheckAndImm:
2919 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2921 case OPC_CheckOrImm:
2922 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2925 case OPC_CheckFoldableChainNode: {
2926 assert(NodeStack.size() != 1 && "No parent node");
2927 // Verify that all intermediate nodes between the root and this one have
2929 bool HasMultipleUses = false;
2930 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2931 if (!NodeStack[i].hasOneUse()) {
2932 HasMultipleUses = true;
2935 if (HasMultipleUses) break;
2937 // Check to see that the target thinks this is profitable to fold and that
2938 // we can fold it without inducing cycles in the graph.
2939 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2941 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2942 NodeToMatch, OptLevel,
2943 true/*We validate our own chains*/))
2948 case OPC_EmitInteger: {
2949 MVT::SimpleValueType VT =
2950 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2951 int64_t Val = MatcherTable[MatcherIndex++];
2953 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2954 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2955 CurDAG->getTargetConstant(Val, VT), nullptr));
2958 case OPC_EmitRegister: {
2959 MVT::SimpleValueType VT =
2960 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2961 unsigned RegNo = MatcherTable[MatcherIndex++];
2962 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2963 CurDAG->getRegister(RegNo, VT), nullptr));
2966 case OPC_EmitRegister2: {
2967 // For targets w/ more than 256 register names, the register enum
2968 // values are stored in two bytes in the matcher table (just like
2970 MVT::SimpleValueType VT =
2971 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2972 unsigned RegNo = MatcherTable[MatcherIndex++];
2973 RegNo |= MatcherTable[MatcherIndex++] << 8;
2974 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2975 CurDAG->getRegister(RegNo, VT), nullptr));
2979 case OPC_EmitConvertToTarget: {
2980 // Convert from IMM/FPIMM to target version.
2981 unsigned RecNo = MatcherTable[MatcherIndex++];
2982 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2983 SDValue Imm = RecordedNodes[RecNo].first;
2985 if (Imm->getOpcode() == ISD::Constant) {
2986 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2987 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2988 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2989 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2990 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2993 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2997 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2998 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2999 // These are space-optimized forms of OPC_EmitMergeInputChains.
3000 assert(!InputChain.getNode() &&
3001 "EmitMergeInputChains should be the first chain producing node");
3002 assert(ChainNodesMatched.empty() &&
3003 "Should only have one EmitMergeInputChains per match");
3005 // Read all of the chained nodes.
3006 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3007 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3008 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3010 // FIXME: What if other value results of the node have uses not matched
3012 if (ChainNodesMatched.back() != NodeToMatch &&
3013 !RecordedNodes[RecNo].first.hasOneUse()) {
3014 ChainNodesMatched.clear();
3018 // Merge the input chains if they are not intra-pattern references.
3019 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3021 if (!InputChain.getNode())
3022 break; // Failed to merge.
3026 case OPC_EmitMergeInputChains: {
3027 assert(!InputChain.getNode() &&
3028 "EmitMergeInputChains should be the first chain producing node");
3029 // This node gets a list of nodes we matched in the input that have
3030 // chains. We want to token factor all of the input chains to these nodes
3031 // together. However, if any of the input chains is actually one of the
3032 // nodes matched in this pattern, then we have an intra-match reference.
3033 // Ignore these because the newly token factored chain should not refer to
3035 unsigned NumChains = MatcherTable[MatcherIndex++];
3036 assert(NumChains != 0 && "Can't TF zero chains");
3038 assert(ChainNodesMatched.empty() &&
3039 "Should only have one EmitMergeInputChains per match");
3041 // Read all of the chained nodes.
3042 for (unsigned i = 0; i != NumChains; ++i) {
3043 unsigned RecNo = MatcherTable[MatcherIndex++];
3044 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3045 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3047 // FIXME: What if other value results of the node have uses not matched
3049 if (ChainNodesMatched.back() != NodeToMatch &&
3050 !RecordedNodes[RecNo].first.hasOneUse()) {
3051 ChainNodesMatched.clear();
3056 // If the inner loop broke out, the match fails.
3057 if (ChainNodesMatched.empty())
3060 // Merge the input chains if they are not intra-pattern references.
3061 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3063 if (!InputChain.getNode())
3064 break; // Failed to merge.
3069 case OPC_EmitCopyToReg: {
3070 unsigned RecNo = MatcherTable[MatcherIndex++];
3071 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3072 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3074 if (!InputChain.getNode())
3075 InputChain = CurDAG->getEntryNode();
3077 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3078 DestPhysReg, RecordedNodes[RecNo].first,
3081 InputGlue = InputChain.getValue(1);
3085 case OPC_EmitNodeXForm: {
3086 unsigned XFormNo = MatcherTable[MatcherIndex++];
3087 unsigned RecNo = MatcherTable[MatcherIndex++];
3088 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3089 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3090 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3095 case OPC_MorphNodeTo: {
3096 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3097 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3098 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3099 // Get the result VT list.
3100 unsigned NumVTs = MatcherTable[MatcherIndex++];
3101 SmallVector<EVT, 4> VTs;
3102 for (unsigned i = 0; i != NumVTs; ++i) {
3103 MVT::SimpleValueType VT =
3104 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3105 if (VT == MVT::iPTR)
3106 VT = TLI->getPointerTy().SimpleTy;
3110 if (EmitNodeInfo & OPFL_Chain)
3111 VTs.push_back(MVT::Other);
3112 if (EmitNodeInfo & OPFL_GlueOutput)
3113 VTs.push_back(MVT::Glue);
3115 // This is hot code, so optimize the two most common cases of 1 and 2
3118 if (VTs.size() == 1)
3119 VTList = CurDAG->getVTList(VTs[0]);
3120 else if (VTs.size() == 2)
3121 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3123 VTList = CurDAG->getVTList(VTs);
3125 // Get the operand list.
3126 unsigned NumOps = MatcherTable[MatcherIndex++];
3127 SmallVector<SDValue, 8> Ops;
3128 for (unsigned i = 0; i != NumOps; ++i) {
3129 unsigned RecNo = MatcherTable[MatcherIndex++];
3131 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3133 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3134 Ops.push_back(RecordedNodes[RecNo].first);
3137 // If there are variadic operands to add, handle them now.
3138 if (EmitNodeInfo & OPFL_VariadicInfo) {
3139 // Determine the start index to copy from.
3140 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3141 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3142 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3143 "Invalid variadic node");
3144 // Copy all of the variadic operands, not including a potential glue
3146 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3148 SDValue V = NodeToMatch->getOperand(i);
3149 if (V.getValueType() == MVT::Glue) break;
3154 // If this has chain/glue inputs, add them.
3155 if (EmitNodeInfo & OPFL_Chain)
3156 Ops.push_back(InputChain);
3157 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3158 Ops.push_back(InputGlue);
3161 SDNode *Res = nullptr;
3162 if (Opcode != OPC_MorphNodeTo) {
3163 // If this is a normal EmitNode command, just create the new node and
3164 // add the results to the RecordedNodes list.
3165 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3168 // Add all the non-glue/non-chain results to the RecordedNodes list.
3169 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3170 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3171 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3175 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3176 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3178 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3179 // We will visit the equivalent node later.
3180 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3184 // If the node had chain/glue results, update our notion of the current
3186 if (EmitNodeInfo & OPFL_GlueOutput) {
3187 InputGlue = SDValue(Res, VTs.size()-1);
3188 if (EmitNodeInfo & OPFL_Chain)
3189 InputChain = SDValue(Res, VTs.size()-2);
3190 } else if (EmitNodeInfo & OPFL_Chain)
3191 InputChain = SDValue(Res, VTs.size()-1);
3193 // If the OPFL_MemRefs glue is set on this node, slap all of the
3194 // accumulated memrefs onto it.
3196 // FIXME: This is vastly incorrect for patterns with multiple outputs
3197 // instructions that access memory and for ComplexPatterns that match
3199 if (EmitNodeInfo & OPFL_MemRefs) {
3200 // Only attach load or store memory operands if the generated
3201 // instruction may load or store.
3202 const MCInstrDesc &MCID = TII->get(TargetOpc);
3203 bool mayLoad = MCID.mayLoad();
3204 bool mayStore = MCID.mayStore();
3206 unsigned NumMemRefs = 0;
3207 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3208 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3209 if ((*I)->isLoad()) {
3212 } else if ((*I)->isStore()) {
3220 MachineSDNode::mmo_iterator MemRefs =
3221 MF->allocateMemRefsArray(NumMemRefs);
3223 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3224 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3225 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3226 if ((*I)->isLoad()) {
3229 } else if ((*I)->isStore()) {
3237 cast<MachineSDNode>(Res)
3238 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3242 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3243 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3245 // If this was a MorphNodeTo then we're completely done!
3246 if (Opcode == OPC_MorphNodeTo) {
3247 // Update chain and glue uses.
3248 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3249 InputGlue, GlueResultNodesMatched, true);
3256 case OPC_MarkGlueResults: {
3257 unsigned NumNodes = MatcherTable[MatcherIndex++];
3259 // Read and remember all the glue-result nodes.
3260 for (unsigned i = 0; i != NumNodes; ++i) {
3261 unsigned RecNo = MatcherTable[MatcherIndex++];
3263 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3265 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3266 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3271 case OPC_CompleteMatch: {
3272 // The match has been completed, and any new nodes (if any) have been
3273 // created. Patch up references to the matched dag to use the newly
3275 unsigned NumResults = MatcherTable[MatcherIndex++];
3277 for (unsigned i = 0; i != NumResults; ++i) {
3278 unsigned ResSlot = MatcherTable[MatcherIndex++];
3280 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3282 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3283 SDValue Res = RecordedNodes[ResSlot].first;
3285 assert(i < NodeToMatch->getNumValues() &&
3286 NodeToMatch->getValueType(i) != MVT::Other &&
3287 NodeToMatch->getValueType(i) != MVT::Glue &&
3288 "Invalid number of results to complete!");
3289 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3290 NodeToMatch->getValueType(i) == MVT::iPTR ||
3291 Res.getValueType() == MVT::iPTR ||
3292 NodeToMatch->getValueType(i).getSizeInBits() ==
3293 Res.getValueType().getSizeInBits()) &&
3294 "invalid replacement");
3295 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3298 // If the root node defines glue, add it to the glue nodes to update list.
3299 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3300 GlueResultNodesMatched.push_back(NodeToMatch);
3302 // Update chain and glue uses.
3303 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3304 InputGlue, GlueResultNodesMatched, false);
3306 assert(NodeToMatch->use_empty() &&
3307 "Didn't replace all uses of the node?");
3309 // FIXME: We just return here, which interacts correctly with SelectRoot
3310 // above. We should fix this to not return an SDNode* anymore.
3315 // If the code reached this point, then the match failed. See if there is
3316 // another child to try in the current 'Scope', otherwise pop it until we
3317 // find a case to check.
3318 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3319 ++NumDAGIselRetries;
3321 if (MatchScopes.empty()) {
3322 CannotYetSelect(NodeToMatch);
3326 // Restore the interpreter state back to the point where the scope was
3328 MatchScope &LastScope = MatchScopes.back();
3329 RecordedNodes.resize(LastScope.NumRecordedNodes);
3331 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3332 N = NodeStack.back();
3334 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3335 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3336 MatcherIndex = LastScope.FailIndex;
3338 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3340 InputChain = LastScope.InputChain;
3341 InputGlue = LastScope.InputGlue;
3342 if (!LastScope.HasChainNodesMatched)
3343 ChainNodesMatched.clear();
3344 if (!LastScope.HasGlueResultNodesMatched)
3345 GlueResultNodesMatched.clear();
3347 // Check to see what the offset is at the new MatcherIndex. If it is zero
3348 // we have reached the end of this scope, otherwise we have another child
3349 // in the current scope to try.
3350 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3351 if (NumToSkip & 128)
3352 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3354 // If we have another child in this scope to match, update FailIndex and
3356 if (NumToSkip != 0) {
3357 LastScope.FailIndex = MatcherIndex+NumToSkip;
3361 // End of this scope, pop it and try the next child in the containing
3363 MatchScopes.pop_back();
3370 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3372 raw_string_ostream Msg(msg);
3373 Msg << "Cannot select: ";
3375 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3376 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3377 N->getOpcode() != ISD::INTRINSIC_VOID) {
3378 N->printrFull(Msg, CurDAG);
3379 Msg << "\nIn function: " << MF->getName();
3381 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3383 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3384 if (iid < Intrinsic::num_intrinsics)
3385 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3386 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3387 Msg << "target intrinsic %" << TII->getName(iid);
3389 Msg << "unknown intrinsic #" << iid;
3391 report_fatal_error(Msg.str());
3394 char SelectionDAGISel::ID = 0;