1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLibraryInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/Timer.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/ADT/PostOrderIterator.h"
55 #include "llvm/ADT/Statistic.h"
59 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
60 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
61 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
62 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
63 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
68 cl::desc("Enable extra verbose messages in the \"fast\" "
69 "instruction selector"));
71 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
72 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
73 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
74 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
75 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
76 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
77 STATISTIC(NumFastIselFailUnwind,"Fast isel fails on Unwind");
78 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
80 // Standard binary operators...
81 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
82 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
83 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
84 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
85 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
86 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
87 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
88 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
89 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
90 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
91 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
92 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
94 // Logical operators...
95 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
96 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
97 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
99 // Memory instructions...
100 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
101 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
102 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
103 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
104 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
105 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
106 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
108 // Convert instructions...
109 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
110 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
111 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
112 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
113 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
114 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
115 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
116 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
117 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
118 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
119 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
120 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
122 // Other instructions...
123 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
124 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
125 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
126 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
127 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
128 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
129 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
130 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
131 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
132 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
133 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
134 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
135 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
136 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
137 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
141 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
142 cl::desc("Enable verbose messages in the \"fast\" "
143 "instruction selector"));
145 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
146 cl::desc("Enable abort calls when \"fast\" instruction fails"));
150 cl::desc("use Machine Branch Probability Info"),
151 cl::init(true), cl::Hidden);
155 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
156 cl::desc("Pop up a window to show dags before the first "
157 "dag combine pass"));
159 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
160 cl::desc("Pop up a window to show dags before legalize types"));
162 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
163 cl::desc("Pop up a window to show dags before legalize"));
165 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before the second "
167 "dag combine pass"));
169 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
170 cl::desc("Pop up a window to show dags before the post legalize types"
171 " dag combine pass"));
173 ViewISelDAGs("view-isel-dags", cl::Hidden,
174 cl::desc("Pop up a window to show isel dags as they are selected"));
176 ViewSchedDAGs("view-sched-dags", cl::Hidden,
177 cl::desc("Pop up a window to show sched dags as they are processed"));
179 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
180 cl::desc("Pop up a window to show SUnit dags after they are processed"));
182 static const bool ViewDAGCombine1 = false,
183 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
184 ViewDAGCombine2 = false,
185 ViewDAGCombineLT = false,
186 ViewISelDAGs = false, ViewSchedDAGs = false,
187 ViewSUnitDAGs = false;
190 //===---------------------------------------------------------------------===//
192 /// RegisterScheduler class - Track the registration of instruction schedulers.
194 //===---------------------------------------------------------------------===//
195 MachinePassRegistry RegisterScheduler::Registry;
197 //===---------------------------------------------------------------------===//
199 /// ISHeuristic command line option for instruction schedulers.
201 //===---------------------------------------------------------------------===//
202 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
203 RegisterPassParser<RegisterScheduler> >
204 ISHeuristic("pre-RA-sched",
205 cl::init(&createDefaultScheduler),
206 cl::desc("Instruction schedulers available (before register"
209 static RegisterScheduler
210 defaultListDAGScheduler("default", "Best scheduler for the target",
211 createDefaultScheduler);
214 //===--------------------------------------------------------------------===//
215 /// createDefaultScheduler - This creates an instruction scheduler appropriate
217 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
218 CodeGenOpt::Level OptLevel) {
219 const TargetLowering &TLI = IS->getTargetLowering();
221 if (OptLevel == CodeGenOpt::None)
222 return createSourceListDAGScheduler(IS, OptLevel);
223 if (TLI.getSchedulingPreference() == Sched::RegPressure)
224 return createBURRListDAGScheduler(IS, OptLevel);
225 if (TLI.getSchedulingPreference() == Sched::Hybrid)
226 return createHybridListDAGScheduler(IS, OptLevel);
227 assert(TLI.getSchedulingPreference() == Sched::ILP &&
228 "Unknown sched type!");
229 return createILPListDAGScheduler(IS, OptLevel);
233 // EmitInstrWithCustomInserter - This method should be implemented by targets
234 // that mark instructions with the 'usesCustomInserter' flag. These
235 // instructions are special in various ways, which require special support to
236 // insert. The specified MachineInstr is created but not inserted into any
237 // basic blocks, and this method is called to expand it into a sequence of
238 // instructions, potentially also creating new basic blocks and control flow.
239 // When new basic blocks are inserted and the edges from MBB to its successors
240 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
243 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
244 MachineBasicBlock *MBB) const {
246 dbgs() << "If a target marks an instruction with "
247 "'usesCustomInserter', it must implement "
248 "TargetLowering::EmitInstrWithCustomInserter!";
254 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
255 SDNode *Node) const {
256 assert(!MI->hasPostISelHook() &&
257 "If a target marks an instruction with 'hasPostISelHook', "
258 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
261 //===----------------------------------------------------------------------===//
262 // SelectionDAGISel code
263 //===----------------------------------------------------------------------===//
265 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
266 CodeGenOpt::Level OL) :
267 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
268 FuncInfo(new FunctionLoweringInfo(TLI)),
269 CurDAG(new SelectionDAG(tm)),
270 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
274 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
275 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
276 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
277 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
280 SelectionDAGISel::~SelectionDAGISel() {
286 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
287 AU.addRequired<AliasAnalysis>();
288 AU.addPreserved<AliasAnalysis>();
289 AU.addRequired<GCModuleInfo>();
290 AU.addPreserved<GCModuleInfo>();
291 AU.addRequired<TargetLibraryInfo>();
292 if (UseMBPI && OptLevel != CodeGenOpt::None)
293 AU.addRequired<BranchProbabilityInfo>();
294 MachineFunctionPass::getAnalysisUsage(AU);
297 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
298 /// may trap on it. In this case we have to split the edge so that the path
299 /// through the predecessor block that doesn't go to the phi block doesn't
300 /// execute the possibly trapping instruction.
302 /// This is required for correctness, so it must be done at -O0.
304 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
305 // Loop for blocks with phi nodes.
306 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
307 PHINode *PN = dyn_cast<PHINode>(BB->begin());
308 if (PN == 0) continue;
311 // For each block with a PHI node, check to see if any of the input values
312 // are potentially trapping constant expressions. Constant expressions are
313 // the only potentially trapping value that can occur as the argument to a
315 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
316 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
317 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
318 if (CE == 0 || !CE->canTrap()) continue;
320 // The only case we have to worry about is when the edge is critical.
321 // Since this block has a PHI Node, we assume it has multiple input
322 // edges: check to see if the pred has multiple successors.
323 BasicBlock *Pred = PN->getIncomingBlock(i);
324 if (Pred->getTerminator()->getNumSuccessors() == 1)
327 // Okay, we have to split this edge.
328 SplitCriticalEdge(Pred->getTerminator(),
329 GetSuccessorNumber(Pred, BB), SDISel, true);
335 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
336 // Do some sanity-checking on the command-line options.
337 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
338 "-fast-isel-verbose requires -fast-isel");
339 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
340 "-fast-isel-abort requires -fast-isel");
342 const Function &Fn = *mf.getFunction();
343 const TargetInstrInfo &TII = *TM.getInstrInfo();
344 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
347 RegInfo = &MF->getRegInfo();
348 AA = &getAnalysis<AliasAnalysis>();
349 LibInfo = &getAnalysis<TargetLibraryInfo>();
350 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
352 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
354 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
357 FuncInfo->set(Fn, *MF);
359 if (UseMBPI && OptLevel != CodeGenOpt::None)
360 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
364 SDB->init(GFI, *AA, LibInfo);
366 SelectAllBasicBlocks(Fn);
368 // If the first basic block in the function has live ins that need to be
369 // copied into vregs, emit the copies into the top of the block before
370 // emitting the code for the block.
371 MachineBasicBlock *EntryMBB = MF->begin();
372 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
374 DenseMap<unsigned, unsigned> LiveInMap;
375 if (!FuncInfo->ArgDbgValues.empty())
376 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
377 E = RegInfo->livein_end(); LI != E; ++LI)
379 LiveInMap.insert(std::make_pair(LI->first, LI->second));
381 // Insert DBG_VALUE instructions for function arguments to the entry block.
382 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
383 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
384 unsigned Reg = MI->getOperand(0).getReg();
385 if (TargetRegisterInfo::isPhysicalRegister(Reg))
386 EntryMBB->insert(EntryMBB->begin(), MI);
388 MachineInstr *Def = RegInfo->getVRegDef(Reg);
389 MachineBasicBlock::iterator InsertPos = Def;
390 // FIXME: VR def may not be in entry block.
391 Def->getParent()->insert(llvm::next(InsertPos), MI);
394 // If Reg is live-in then update debug info to track its copy in a vreg.
395 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
396 if (LDI != LiveInMap.end()) {
397 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
398 MachineBasicBlock::iterator InsertPos = Def;
399 const MDNode *Variable =
400 MI->getOperand(MI->getNumOperands()-1).getMetadata();
401 unsigned Offset = MI->getOperand(1).getImm();
402 // Def is never a terminator here, so it is ok to increment InsertPos.
403 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
404 TII.get(TargetOpcode::DBG_VALUE))
405 .addReg(LDI->second, RegState::Debug)
406 .addImm(Offset).addMetadata(Variable);
408 // If this vreg is directly copied into an exported register then
409 // that COPY instructions also need DBG_VALUE, if it is the only
410 // user of LDI->second.
411 MachineInstr *CopyUseMI = NULL;
412 for (MachineRegisterInfo::use_iterator
413 UI = RegInfo->use_begin(LDI->second);
414 MachineInstr *UseMI = UI.skipInstruction();) {
415 if (UseMI->isDebugValue()) continue;
416 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
417 CopyUseMI = UseMI; continue;
419 // Otherwise this is another use or second copy use.
420 CopyUseMI = NULL; break;
423 MachineInstr *NewMI =
424 BuildMI(*MF, CopyUseMI->getDebugLoc(),
425 TII.get(TargetOpcode::DBG_VALUE))
426 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
427 .addImm(Offset).addMetadata(Variable);
428 MachineBasicBlock::iterator Pos = CopyUseMI;
429 EntryMBB->insertAfter(Pos, NewMI);
434 // Determine if there are any calls in this machine function.
435 MachineFrameInfo *MFI = MF->getFrameInfo();
436 if (!MFI->hasCalls()) {
437 for (MachineFunction::const_iterator
438 I = MF->begin(), E = MF->end(); I != E; ++I) {
439 const MachineBasicBlock *MBB = I;
440 for (MachineBasicBlock::const_iterator
441 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
442 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
444 if ((MCID.isCall() && !MCID.isReturn()) ||
445 II->isStackAligningInlineAsm()) {
446 MFI->setHasCalls(true);
454 // Determine if there is a call to setjmp in the machine function.
455 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice());
457 // Replace forward-declared registers with the registers containing
458 // the desired value.
459 MachineRegisterInfo &MRI = MF->getRegInfo();
460 for (DenseMap<unsigned, unsigned>::iterator
461 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
463 unsigned From = I->first;
464 unsigned To = I->second;
465 // If To is also scheduled to be replaced, find what its ultimate
468 DenseMap<unsigned, unsigned>::iterator J =
469 FuncInfo->RegFixups.find(To);
474 MRI.replaceRegWith(From, To);
477 // Release function-specific state. SDB and CurDAG are already cleared
484 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
485 BasicBlock::const_iterator End,
487 // Lower all of the non-terminator instructions. If a call is emitted
488 // as a tail call, cease emitting nodes for this block. Terminators
489 // are handled below.
490 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
493 // Make sure the root of the DAG is up-to-date.
494 CurDAG->setRoot(SDB->getControlRoot());
495 HadTailCall = SDB->HasTailCall;
498 // Final step, emit the lowered DAG as machine code.
502 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
503 SmallPtrSet<SDNode*, 128> VisitedNodes;
504 SmallVector<SDNode*, 128> Worklist;
506 Worklist.push_back(CurDAG->getRoot().getNode());
513 SDNode *N = Worklist.pop_back_val();
515 // If we've already seen this node, ignore it.
516 if (!VisitedNodes.insert(N))
519 // Otherwise, add all chain operands to the worklist.
520 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
521 if (N->getOperand(i).getValueType() == MVT::Other)
522 Worklist.push_back(N->getOperand(i).getNode());
524 // If this is a CopyToReg with a vreg dest, process it.
525 if (N->getOpcode() != ISD::CopyToReg)
528 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
529 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
532 // Ignore non-scalar or non-integer values.
533 SDValue Src = N->getOperand(2);
534 EVT SrcVT = Src.getValueType();
535 if (!SrcVT.isInteger() || SrcVT.isVector())
538 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
539 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
540 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
541 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
542 } while (!Worklist.empty());
545 void SelectionDAGISel::CodeGenAndEmitDAG() {
546 std::string GroupName;
547 if (TimePassesIsEnabled)
548 GroupName = "Instruction Selection and Scheduling";
549 std::string BlockName;
550 int BlockNumber = -1;
553 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
554 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
558 BlockNumber = FuncInfo->MBB->getNumber();
559 BlockName = MF->getFunction()->getName().str() + ":" +
560 FuncInfo->MBB->getBasicBlock()->getName().str();
562 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
563 << " '" << BlockName << "'\n"; CurDAG->dump());
565 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
567 // Run the DAG combiner in pre-legalize mode.
569 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
570 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
573 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
574 << " '" << BlockName << "'\n"; CurDAG->dump());
576 // Second step, hack on the DAG until it only uses operations and types that
577 // the target supports.
578 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
583 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
584 Changed = CurDAG->LegalizeTypes();
587 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
588 << " '" << BlockName << "'\n"; CurDAG->dump());
591 if (ViewDAGCombineLT)
592 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
594 // Run the DAG combiner in post-type-legalize mode.
596 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
597 TimePassesIsEnabled);
598 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
601 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
602 << " '" << BlockName << "'\n"; CurDAG->dump());
606 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
607 Changed = CurDAG->LegalizeVectors();
612 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
613 CurDAG->LegalizeTypes();
616 if (ViewDAGCombineLT)
617 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
619 // Run the DAG combiner in post-type-legalize mode.
621 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
622 TimePassesIsEnabled);
623 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
626 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
627 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
630 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
633 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
637 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
638 << " '" << BlockName << "'\n"; CurDAG->dump());
640 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
642 // Run the DAG combiner in post-legalize mode.
644 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
645 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
648 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
649 << " '" << BlockName << "'\n"; CurDAG->dump());
651 if (OptLevel != CodeGenOpt::None)
652 ComputeLiveOutVRegInfo();
654 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
656 // Third, instruction select all of the operations to machine code, adding the
657 // code to the MachineBasicBlock.
659 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
660 DoInstructionSelection();
663 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
664 << " '" << BlockName << "'\n"; CurDAG->dump());
666 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
668 // Schedule machine code.
669 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
671 NamedRegionTimer T("Instruction Scheduling", GroupName,
672 TimePassesIsEnabled);
673 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
676 if (ViewSUnitDAGs) Scheduler->viewGraph();
678 // Emit machine code to BB. This can change 'BB' to the last block being
680 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
682 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
684 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
685 FuncInfo->InsertPt = Scheduler->InsertPos;
688 // If the block was split, make sure we update any references that are used to
689 // update PHI nodes later on.
690 if (FirstMBB != LastMBB)
691 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
693 // Free the scheduler state.
695 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
696 TimePassesIsEnabled);
700 // Free the SelectionDAG state, now that we're finished with it.
704 void SelectionDAGISel::DoInstructionSelection() {
705 DEBUG(errs() << "===== Instruction selection begins: BB#"
706 << FuncInfo->MBB->getNumber()
707 << " '" << FuncInfo->MBB->getName() << "'\n");
711 // Select target instructions for the DAG.
713 // Number all nodes with a topological order and set DAGSize.
714 DAGSize = CurDAG->AssignTopologicalOrder();
716 // Create a dummy node (which is not added to allnodes), that adds
717 // a reference to the root node, preventing it from being deleted,
718 // and tracking any changes of the root.
719 HandleSDNode Dummy(CurDAG->getRoot());
720 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
723 // The AllNodes list is now topological-sorted. Visit the
724 // nodes by starting at the end of the list (the root of the
725 // graph) and preceding back toward the beginning (the entry
727 while (ISelPosition != CurDAG->allnodes_begin()) {
728 SDNode *Node = --ISelPosition;
729 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
730 // but there are currently some corner cases that it misses. Also, this
731 // makes it theoretically possible to disable the DAGCombiner.
732 if (Node->use_empty())
735 SDNode *ResNode = Select(Node);
737 // FIXME: This is pretty gross. 'Select' should be changed to not return
738 // anything at all and this code should be nuked with a tactical strike.
740 // If node should not be replaced, continue with the next one.
741 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
745 ReplaceUses(Node, ResNode);
747 // If after the replacement this node is not used any more,
748 // remove this dead node.
749 if (Node->use_empty()) { // Don't delete EntryToken, etc.
750 ISelUpdater ISU(ISelPosition);
751 CurDAG->RemoveDeadNode(Node, &ISU);
755 CurDAG->setRoot(Dummy.getValue());
758 DEBUG(errs() << "===== Instruction selection ends:\n");
760 PostprocessISelDAG();
763 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
764 /// do other setup for EH landing-pad blocks.
765 void SelectionDAGISel::PrepareEHLandingPad() {
766 MachineBasicBlock *MBB = FuncInfo->MBB;
768 // Add a label to mark the beginning of the landing pad. Deletion of the
769 // landing pad can thus be detected via the MachineModuleInfo.
770 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
772 // Assign the call site to the landing pad's begin label.
773 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
775 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
776 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
779 // Mark exception register as live in.
780 unsigned Reg = TLI.getExceptionAddressRegister();
781 if (Reg) MBB->addLiveIn(Reg);
783 // Mark exception selector register as live in.
784 Reg = TLI.getExceptionSelectorRegister();
785 if (Reg) MBB->addLiveIn(Reg);
787 // FIXME: Hack around an exception handling flaw (PR1508): the personality
788 // function and list of typeids logically belong to the invoke (or, if you
789 // like, the basic block containing the invoke), and need to be associated
790 // with it in the dwarf exception handling tables. Currently however the
791 // information is provided by an intrinsic (eh.selector) that can be moved
792 // to unexpected places by the optimizers: if the unwind edge is critical,
793 // then breaking it can result in the intrinsics being in the successor of
794 // the landing pad, not the landing pad itself. This results
795 // in exceptions not being caught because no typeids are associated with
796 // the invoke. This may not be the only way things can go wrong, but it
797 // is the only way we try to work around for the moment.
798 const BasicBlock *LLVMBB = MBB->getBasicBlock();
799 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
801 if (Br && Br->isUnconditional()) { // Critical edge?
802 BasicBlock::const_iterator I, E;
803 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
804 if (isa<EHSelectorInst>(I))
808 // No catch info found - try to extract some from the successor.
809 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
813 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
814 /// load into the specified FoldInst. Note that we could have a sequence where
815 /// multiple LLVM IR instructions are folded into the same machineinstr. For
816 /// example we could have:
817 /// A: x = load i32 *P
818 /// B: y = icmp A, 42
821 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
822 /// any other folded instructions) because it is between A and C.
824 /// If we succeed in folding the load into the operation, return true.
826 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
827 const Instruction *FoldInst,
829 // We know that the load has a single use, but don't know what it is. If it
830 // isn't one of the folded instructions, then we can't succeed here. Handle
831 // this by scanning the single-use users of the load until we get to FoldInst.
832 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
834 const Instruction *TheUser = LI->use_back();
835 while (TheUser != FoldInst && // Scan up until we find FoldInst.
836 // Stay in the right block.
837 TheUser->getParent() == FoldInst->getParent() &&
838 --MaxUsers) { // Don't scan too far.
839 // If there are multiple or no uses of this instruction, then bail out.
840 if (!TheUser->hasOneUse())
843 TheUser = TheUser->use_back();
846 // If we didn't find the fold instruction, then we failed to collapse the
848 if (TheUser != FoldInst)
851 // Don't try to fold volatile loads. Target has to deal with alignment
853 if (LI->isVolatile()) return false;
855 // Figure out which vreg this is going into. If there is no assigned vreg yet
856 // then there actually was no reference to it. Perhaps the load is referenced
857 // by a dead instruction.
858 unsigned LoadReg = FastIS->getRegForValue(LI);
862 // Check to see what the uses of this vreg are. If it has no uses, or more
863 // than one use (at the machine instr level) then we can't fold it.
864 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
865 if (RI == RegInfo->reg_end())
868 // See if there is exactly one use of the vreg. If there are multiple uses,
869 // then the instruction got lowered to multiple machine instructions or the
870 // use of the loaded value ended up being multiple operands of the result, in
871 // either case, we can't fold this.
872 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
873 if (PostRI != RegInfo->reg_end())
876 assert(RI.getOperand().isUse() &&
877 "The only use of the vreg must be a use, we haven't emitted the def!");
879 MachineInstr *User = &*RI;
881 // Set the insertion point properly. Folding the load can cause generation of
882 // other random instructions (like sign extends) for addressing modes, make
883 // sure they get inserted in a logical place before the new instruction.
884 FuncInfo->InsertPt = User;
885 FuncInfo->MBB = User->getParent();
887 // Ask the target to try folding the load.
888 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
891 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
892 /// side-effect free and is either dead or folded into a generated instruction.
893 /// Return false if it needs to be emitted.
894 static bool isFoldedOrDeadInstruction(const Instruction *I,
895 FunctionLoweringInfo *FuncInfo) {
896 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
897 !isa<TerminatorInst>(I) && // Terminators aren't folded.
898 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
899 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
900 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
904 static void collectFailStats(const Instruction *I) {
905 switch (I->getOpcode()) {
906 default: assert (0 && "<Invalid operator> ");
909 case Instruction::Ret: NumFastIselFailRet++; return;
910 case Instruction::Br: NumFastIselFailBr++; return;
911 case Instruction::Switch: NumFastIselFailSwitch++; return;
912 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
913 case Instruction::Invoke: NumFastIselFailInvoke++; return;
914 case Instruction::Resume: NumFastIselFailResume++; return;
915 case Instruction::Unwind: NumFastIselFailUnwind++; return;
916 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
918 // Standard binary operators...
919 case Instruction::Add: NumFastIselFailAdd++; return;
920 case Instruction::FAdd: NumFastIselFailFAdd++; return;
921 case Instruction::Sub: NumFastIselFailSub++; return;
922 case Instruction::FSub: NumFastIselFailFSub++; return;
923 case Instruction::Mul: NumFastIselFailMul++; return;
924 case Instruction::FMul: NumFastIselFailFMul++; return;
925 case Instruction::UDiv: NumFastIselFailUDiv++; return;
926 case Instruction::SDiv: NumFastIselFailSDiv++; return;
927 case Instruction::FDiv: NumFastIselFailFDiv++; return;
928 case Instruction::URem: NumFastIselFailURem++; return;
929 case Instruction::SRem: NumFastIselFailSRem++; return;
930 case Instruction::FRem: NumFastIselFailFRem++; return;
932 // Logical operators...
933 case Instruction::And: NumFastIselFailAnd++; return;
934 case Instruction::Or: NumFastIselFailOr++; return;
935 case Instruction::Xor: NumFastIselFailXor++; return;
937 // Memory instructions...
938 case Instruction::Alloca: NumFastIselFailAlloca++; return;
939 case Instruction::Load: NumFastIselFailLoad++; return;
940 case Instruction::Store: NumFastIselFailStore++; return;
941 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
942 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
943 case Instruction::Fence: NumFastIselFailFence++; return;
944 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
946 // Convert instructions...
947 case Instruction::Trunc: NumFastIselFailTrunc++; return;
948 case Instruction::ZExt: NumFastIselFailZExt++; return;
949 case Instruction::SExt: NumFastIselFailSExt++; return;
950 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
951 case Instruction::FPExt: NumFastIselFailFPExt++; return;
952 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
953 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
954 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
955 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
956 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
957 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
958 case Instruction::BitCast: NumFastIselFailBitCast++; return;
960 // Other instructions...
961 case Instruction::ICmp: NumFastIselFailICmp++; return;
962 case Instruction::FCmp: NumFastIselFailFCmp++; return;
963 case Instruction::PHI: NumFastIselFailPHI++; return;
964 case Instruction::Select: NumFastIselFailSelect++; return;
965 case Instruction::Call: NumFastIselFailCall++; return;
966 case Instruction::Shl: NumFastIselFailShl++; return;
967 case Instruction::LShr: NumFastIselFailLShr++; return;
968 case Instruction::AShr: NumFastIselFailAShr++; return;
969 case Instruction::VAArg: NumFastIselFailVAArg++; return;
970 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
971 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
972 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
973 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
974 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
975 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
981 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
982 // Initialize the Fast-ISel state, if needed.
983 FastISel *FastIS = 0;
984 if (TM.Options.EnableFastISel)
985 FastIS = TLI.createFastISel(*FuncInfo);
987 // Iterate over all basic blocks in the function.
988 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
989 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
990 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
991 const BasicBlock *LLVMBB = *I;
993 if (OptLevel != CodeGenOpt::None) {
994 bool AllPredsVisited = true;
995 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
997 if (!FuncInfo->VisitedBBs.count(*PI)) {
998 AllPredsVisited = false;
1003 if (AllPredsVisited) {
1004 for (BasicBlock::const_iterator I = LLVMBB->begin();
1005 isa<PHINode>(I); ++I)
1006 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
1008 for (BasicBlock::const_iterator I = LLVMBB->begin();
1009 isa<PHINode>(I); ++I)
1010 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
1013 FuncInfo->VisitedBBs.insert(LLVMBB);
1016 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1017 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1019 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1020 BasicBlock::const_iterator const End = LLVMBB->end();
1021 BasicBlock::const_iterator BI = End;
1023 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1025 // Setup an EH landing-pad block.
1026 if (FuncInfo->MBB->isLandingPad())
1027 PrepareEHLandingPad();
1029 // Lower any arguments needed in this block if this is the entry block.
1030 if (LLVMBB == &Fn.getEntryBlock())
1031 LowerArguments(LLVMBB);
1033 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1035 FastIS->startNewBlock();
1037 // Emit code for any incoming arguments. This must happen before
1038 // beginning FastISel on the entry block.
1039 if (LLVMBB == &Fn.getEntryBlock()) {
1040 CurDAG->setRoot(SDB->getControlRoot());
1042 CodeGenAndEmitDAG();
1044 // If we inserted any instructions at the beginning, make a note of
1045 // where they are, so we can be sure to emit subsequent instructions
1047 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1048 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1050 FastIS->setLastLocalValue(0);
1053 unsigned NumFastIselRemaining = std::distance(Begin, End);
1054 // Do FastISel on as many instructions as possible.
1055 for (; BI != Begin; --BI) {
1056 const Instruction *Inst = llvm::prior(BI);
1058 // If we no longer require this instruction, skip it.
1059 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1060 --NumFastIselRemaining;
1064 // Bottom-up: reset the insert pos at the top, after any local-value
1066 FastIS->recomputeInsertPt();
1068 // Try to select the instruction with FastISel.
1069 if (FastIS->SelectInstruction(Inst)) {
1070 --NumFastIselRemaining;
1071 ++NumFastIselSuccess;
1072 // If fast isel succeeded, skip over all the folded instructions, and
1073 // then see if there is a load right before the selected instructions.
1074 // Try to fold the load if so.
1075 const Instruction *BeforeInst = Inst;
1076 while (BeforeInst != Begin) {
1077 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1078 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1081 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1082 BeforeInst->hasOneUse() &&
1083 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1084 // If we succeeded, don't re-select the load.
1085 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1086 --NumFastIselRemaining;
1087 ++NumFastIselSuccess;
1093 if (EnableFastISelVerbose2)
1094 collectFailStats(Inst);
1097 // Then handle certain instructions as single-LLVM-Instruction blocks.
1098 if (isa<CallInst>(Inst)) {
1100 if (EnableFastISelVerbose || EnableFastISelAbort) {
1101 dbgs() << "FastISel missed call: ";
1105 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1106 unsigned &R = FuncInfo->ValueMap[Inst];
1108 R = FuncInfo->CreateRegs(Inst->getType());
1111 bool HadTailCall = false;
1112 SelectBasicBlock(Inst, BI, HadTailCall);
1114 // Recompute NumFastIselRemaining as Selection DAG instruction
1115 // selection may have handled the call, input args, etc.
1116 unsigned RemainingNow = std::distance(Begin, BI);
1117 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1119 // If the call was emitted as a tail call, we're done with the block.
1125 NumFastIselRemaining = RemainingNow;
1129 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1130 // Don't abort, and use a different message for terminator misses.
1131 NumFastIselFailures += NumFastIselRemaining;
1132 if (EnableFastISelVerbose || EnableFastISelAbort) {
1133 dbgs() << "FastISel missed terminator: ";
1137 NumFastIselFailures += NumFastIselRemaining;
1138 if (EnableFastISelVerbose || EnableFastISelAbort) {
1139 dbgs() << "FastISel miss: ";
1142 if (EnableFastISelAbort)
1143 // The "fast" selector couldn't handle something and bailed.
1144 // For the purpose of debugging, just abort.
1145 llvm_unreachable("FastISel didn't select the entire block");
1150 FastIS->recomputeInsertPt();
1156 ++NumFastIselBlocks;
1159 // Run SelectionDAG instruction selection on the remainder of the block
1160 // not handled by FastISel. If FastISel is not run, this is the entire
1163 SelectBasicBlock(Begin, BI, HadTailCall);
1167 FuncInfo->PHINodesToUpdate.clear();
1171 SDB->clearDanglingDebugInfo();
1175 SelectionDAGISel::FinishBasicBlock() {
1177 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1178 << FuncInfo->PHINodesToUpdate.size() << "\n";
1179 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1180 dbgs() << "Node " << i << " : ("
1181 << FuncInfo->PHINodesToUpdate[i].first
1182 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1184 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1185 // PHI nodes in successors.
1186 if (SDB->SwitchCases.empty() &&
1187 SDB->JTCases.empty() &&
1188 SDB->BitTestCases.empty()) {
1189 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1190 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1191 assert(PHI->isPHI() &&
1192 "This is not a machine PHI node that we are updating!");
1193 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1196 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1197 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1202 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1203 // Lower header first, if it wasn't already lowered
1204 if (!SDB->BitTestCases[i].Emitted) {
1205 // Set the current basic block to the mbb we wish to insert the code into
1206 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1207 FuncInfo->InsertPt = FuncInfo->MBB->end();
1209 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1210 CurDAG->setRoot(SDB->getRoot());
1212 CodeGenAndEmitDAG();
1215 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1216 // Set the current basic block to the mbb we wish to insert the code into
1217 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1218 FuncInfo->InsertPt = FuncInfo->MBB->end();
1221 SDB->visitBitTestCase(SDB->BitTestCases[i],
1222 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1223 SDB->BitTestCases[i].Reg,
1224 SDB->BitTestCases[i].Cases[j],
1227 SDB->visitBitTestCase(SDB->BitTestCases[i],
1228 SDB->BitTestCases[i].Default,
1229 SDB->BitTestCases[i].Reg,
1230 SDB->BitTestCases[i].Cases[j],
1234 CurDAG->setRoot(SDB->getRoot());
1236 CodeGenAndEmitDAG();
1240 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1242 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1243 MachineBasicBlock *PHIBB = PHI->getParent();
1244 assert(PHI->isPHI() &&
1245 "This is not a machine PHI node that we are updating!");
1246 // This is "default" BB. We have two jumps to it. From "header" BB and
1247 // from last "case" BB.
1248 if (PHIBB == SDB->BitTestCases[i].Default) {
1249 PHI->addOperand(MachineOperand::
1250 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1252 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1253 PHI->addOperand(MachineOperand::
1254 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1256 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1259 // One of "cases" BB.
1260 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1262 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1263 if (cBB->isSuccessor(PHIBB)) {
1264 PHI->addOperand(MachineOperand::
1265 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1267 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1272 SDB->BitTestCases.clear();
1274 // If the JumpTable record is filled in, then we need to emit a jump table.
1275 // Updating the PHI nodes is tricky in this case, since we need to determine
1276 // whether the PHI is a successor of the range check MBB or the jump table MBB
1277 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1278 // Lower header first, if it wasn't already lowered
1279 if (!SDB->JTCases[i].first.Emitted) {
1280 // Set the current basic block to the mbb we wish to insert the code into
1281 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1282 FuncInfo->InsertPt = FuncInfo->MBB->end();
1284 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1286 CurDAG->setRoot(SDB->getRoot());
1288 CodeGenAndEmitDAG();
1291 // Set the current basic block to the mbb we wish to insert the code into
1292 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1293 FuncInfo->InsertPt = FuncInfo->MBB->end();
1295 SDB->visitJumpTable(SDB->JTCases[i].second);
1296 CurDAG->setRoot(SDB->getRoot());
1298 CodeGenAndEmitDAG();
1301 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1303 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1304 MachineBasicBlock *PHIBB = PHI->getParent();
1305 assert(PHI->isPHI() &&
1306 "This is not a machine PHI node that we are updating!");
1307 // "default" BB. We can go there only from header BB.
1308 if (PHIBB == SDB->JTCases[i].second.Default) {
1310 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1313 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1315 // JT BB. Just iterate over successors here
1316 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1318 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1320 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1324 SDB->JTCases.clear();
1326 // If the switch block involved a branch to one of the actual successors, we
1327 // need to update PHI nodes in that block.
1328 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1329 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1330 assert(PHI->isPHI() &&
1331 "This is not a machine PHI node that we are updating!");
1332 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1334 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1335 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1339 // If we generated any switch lowering information, build and codegen any
1340 // additional DAGs necessary.
1341 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1342 // Set the current basic block to the mbb we wish to insert the code into
1343 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1344 FuncInfo->InsertPt = FuncInfo->MBB->end();
1346 // Determine the unique successors.
1347 SmallVector<MachineBasicBlock *, 2> Succs;
1348 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1349 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1350 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1352 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1353 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1354 CurDAG->setRoot(SDB->getRoot());
1356 CodeGenAndEmitDAG();
1358 // Remember the last block, now that any splitting is done, for use in
1359 // populating PHI nodes in successors.
1360 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1362 // Handle any PHI nodes in successors of this chunk, as if we were coming
1363 // from the original BB before switch expansion. Note that PHI nodes can
1364 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1365 // handle them the right number of times.
1366 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1367 FuncInfo->MBB = Succs[i];
1368 FuncInfo->InsertPt = FuncInfo->MBB->end();
1369 // FuncInfo->MBB may have been removed from the CFG if a branch was
1371 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1372 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1373 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1375 // This value for this PHI node is recorded in PHINodesToUpdate.
1376 for (unsigned pn = 0; ; ++pn) {
1377 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1378 "Didn't find PHI entry!");
1379 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1380 Phi->addOperand(MachineOperand::
1381 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1383 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1391 SDB->SwitchCases.clear();
1395 /// Create the scheduler. If a specific scheduler was specified
1396 /// via the SchedulerRegistry, use it, otherwise select the
1397 /// one preferred by the target.
1399 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1400 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1404 RegisterScheduler::setDefault(Ctor);
1407 return Ctor(this, OptLevel);
1410 //===----------------------------------------------------------------------===//
1411 // Helper functions used by the generated instruction selector.
1412 //===----------------------------------------------------------------------===//
1413 // Calls to these methods are generated by tblgen.
1415 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1416 /// the dag combiner simplified the 255, we still want to match. RHS is the
1417 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1418 /// specified in the .td file (e.g. 255).
1419 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1420 int64_t DesiredMaskS) const {
1421 const APInt &ActualMask = RHS->getAPIntValue();
1422 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1424 // If the actual mask exactly matches, success!
1425 if (ActualMask == DesiredMask)
1428 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1429 if (ActualMask.intersects(~DesiredMask))
1432 // Otherwise, the DAG Combiner may have proven that the value coming in is
1433 // either already zero or is not demanded. Check for known zero input bits.
1434 APInt NeededMask = DesiredMask & ~ActualMask;
1435 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1438 // TODO: check to see if missing bits are just not demanded.
1440 // Otherwise, this pattern doesn't match.
1444 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1445 /// the dag combiner simplified the 255, we still want to match. RHS is the
1446 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1447 /// specified in the .td file (e.g. 255).
1448 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1449 int64_t DesiredMaskS) const {
1450 const APInt &ActualMask = RHS->getAPIntValue();
1451 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1453 // If the actual mask exactly matches, success!
1454 if (ActualMask == DesiredMask)
1457 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1458 if (ActualMask.intersects(~DesiredMask))
1461 // Otherwise, the DAG Combiner may have proven that the value coming in is
1462 // either already zero or is not demanded. Check for known zero input bits.
1463 APInt NeededMask = DesiredMask & ~ActualMask;
1465 APInt KnownZero, KnownOne;
1466 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1468 // If all the missing bits in the or are already known to be set, match!
1469 if ((NeededMask & KnownOne) == NeededMask)
1472 // TODO: check to see if missing bits are just not demanded.
1474 // Otherwise, this pattern doesn't match.
1479 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1480 /// by tblgen. Others should not call it.
1481 void SelectionDAGISel::
1482 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1483 std::vector<SDValue> InOps;
1484 std::swap(InOps, Ops);
1486 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1487 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1488 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1489 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1491 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1492 if (InOps[e-1].getValueType() == MVT::Glue)
1493 --e; // Don't process a glue operand if it is here.
1496 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1497 if (!InlineAsm::isMemKind(Flags)) {
1498 // Just skip over this operand, copying the operands verbatim.
1499 Ops.insert(Ops.end(), InOps.begin()+i,
1500 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1501 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1503 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1504 "Memory operand with multiple values?");
1505 // Otherwise, this is a memory operand. Ask the target to select it.
1506 std::vector<SDValue> SelOps;
1507 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1508 report_fatal_error("Could not match memory address. Inline asm"
1511 // Add this to the output node.
1513 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1514 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1515 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1520 // Add the glue input back if present.
1521 if (e != InOps.size())
1522 Ops.push_back(InOps.back());
1525 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1528 static SDNode *findGlueUse(SDNode *N) {
1529 unsigned FlagResNo = N->getNumValues()-1;
1530 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1531 SDUse &Use = I.getUse();
1532 if (Use.getResNo() == FlagResNo)
1533 return Use.getUser();
1538 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1539 /// This function recursively traverses up the operand chain, ignoring
1541 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1542 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1543 bool IgnoreChains) {
1544 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1545 // greater than all of its (recursive) operands. If we scan to a point where
1546 // 'use' is smaller than the node we're scanning for, then we know we will
1549 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1550 // happen because we scan down to newly selected nodes in the case of glue
1552 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1555 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1556 // won't fail if we scan it again.
1557 if (!Visited.insert(Use))
1560 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1561 // Ignore chain uses, they are validated by HandleMergeInputChains.
1562 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1565 SDNode *N = Use->getOperand(i).getNode();
1567 if (Use == ImmedUse || Use == Root)
1568 continue; // We are not looking for immediate use.
1573 // Traverse up the operand chain.
1574 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1580 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1581 /// operand node N of U during instruction selection that starts at Root.
1582 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1583 SDNode *Root) const {
1584 if (OptLevel == CodeGenOpt::None) return false;
1585 return N.hasOneUse();
1588 /// IsLegalToFold - Returns true if the specific operand node N of
1589 /// U can be folded during instruction selection that starts at Root.
1590 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1591 CodeGenOpt::Level OptLevel,
1592 bool IgnoreChains) {
1593 if (OptLevel == CodeGenOpt::None) return false;
1595 // If Root use can somehow reach N through a path that that doesn't contain
1596 // U then folding N would create a cycle. e.g. In the following
1597 // diagram, Root can reach N through X. If N is folded into into Root, then
1598 // X is both a predecessor and a successor of U.
1609 // * indicates nodes to be folded together.
1611 // If Root produces glue, then it gets (even more) interesting. Since it
1612 // will be "glued" together with its glue use in the scheduler, we need to
1613 // check if it might reach N.
1632 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1633 // (call it Fold), then X is a predecessor of GU and a successor of
1634 // Fold. But since Fold and GU are glued together, this will create
1635 // a cycle in the scheduling graph.
1637 // If the node has glue, walk down the graph to the "lowest" node in the
1639 EVT VT = Root->getValueType(Root->getNumValues()-1);
1640 while (VT == MVT::Glue) {
1641 SDNode *GU = findGlueUse(Root);
1645 VT = Root->getValueType(Root->getNumValues()-1);
1647 // If our query node has a glue result with a use, we've walked up it. If
1648 // the user (which has already been selected) has a chain or indirectly uses
1649 // the chain, our WalkChainUsers predicate will not consider it. Because of
1650 // this, we cannot ignore chains in this predicate.
1651 IgnoreChains = false;
1655 SmallPtrSet<SDNode*, 16> Visited;
1656 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1659 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1660 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1661 SelectInlineAsmMemoryOperands(Ops);
1663 std::vector<EVT> VTs;
1664 VTs.push_back(MVT::Other);
1665 VTs.push_back(MVT::Glue);
1666 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1667 VTs, &Ops[0], Ops.size());
1669 return New.getNode();
1672 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1673 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1676 /// GetVBR - decode a vbr encoding whose top bit is set.
1677 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1678 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1679 assert(Val >= 128 && "Not a VBR");
1680 Val &= 127; // Remove first vbr bit.
1685 NextBits = MatcherTable[Idx++];
1686 Val |= (NextBits&127) << Shift;
1688 } while (NextBits & 128);
1694 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1695 /// interior glue and chain results to use the new glue and chain results.
1696 void SelectionDAGISel::
1697 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1698 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1700 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1701 bool isMorphNodeTo) {
1702 SmallVector<SDNode*, 4> NowDeadNodes;
1704 ISelUpdater ISU(ISelPosition);
1706 // Now that all the normal results are replaced, we replace the chain and
1707 // glue results if present.
1708 if (!ChainNodesMatched.empty()) {
1709 assert(InputChain.getNode() != 0 &&
1710 "Matched input chains but didn't produce a chain");
1711 // Loop over all of the nodes we matched that produced a chain result.
1712 // Replace all the chain results with the final chain we ended up with.
1713 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1714 SDNode *ChainNode = ChainNodesMatched[i];
1716 // If this node was already deleted, don't look at it.
1717 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1720 // Don't replace the results of the root node if we're doing a
1722 if (ChainNode == NodeToMatch && isMorphNodeTo)
1725 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1726 if (ChainVal.getValueType() == MVT::Glue)
1727 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1728 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1729 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1731 // If the node became dead and we haven't already seen it, delete it.
1732 if (ChainNode->use_empty() &&
1733 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1734 NowDeadNodes.push_back(ChainNode);
1738 // If the result produces glue, update any glue results in the matched
1739 // pattern with the glue result.
1740 if (InputGlue.getNode() != 0) {
1741 // Handle any interior nodes explicitly marked.
1742 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1743 SDNode *FRN = GlueResultNodesMatched[i];
1745 // If this node was already deleted, don't look at it.
1746 if (FRN->getOpcode() == ISD::DELETED_NODE)
1749 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1750 "Doesn't have a glue result");
1751 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1754 // If the node became dead and we haven't already seen it, delete it.
1755 if (FRN->use_empty() &&
1756 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1757 NowDeadNodes.push_back(FRN);
1761 if (!NowDeadNodes.empty())
1762 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1764 DEBUG(errs() << "ISEL: Match complete!\n");
1770 CR_LeadsToInteriorNode
1773 /// WalkChainUsers - Walk down the users of the specified chained node that is
1774 /// part of the pattern we're matching, looking at all of the users we find.
1775 /// This determines whether something is an interior node, whether we have a
1776 /// non-pattern node in between two pattern nodes (which prevent folding because
1777 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1778 /// between pattern nodes (in which case the TF becomes part of the pattern).
1780 /// The walk we do here is guaranteed to be small because we quickly get down to
1781 /// already selected nodes "below" us.
1783 WalkChainUsers(SDNode *ChainedNode,
1784 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1785 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1786 ChainResult Result = CR_Simple;
1788 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1789 E = ChainedNode->use_end(); UI != E; ++UI) {
1790 // Make sure the use is of the chain, not some other value we produce.
1791 if (UI.getUse().getValueType() != MVT::Other) continue;
1795 // If we see an already-selected machine node, then we've gone beyond the
1796 // pattern that we're selecting down into the already selected chunk of the
1798 if (User->isMachineOpcode() ||
1799 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1802 if (User->getOpcode() == ISD::CopyToReg ||
1803 User->getOpcode() == ISD::CopyFromReg ||
1804 User->getOpcode() == ISD::INLINEASM ||
1805 User->getOpcode() == ISD::EH_LABEL) {
1806 // If their node ID got reset to -1 then they've already been selected.
1807 // Treat them like a MachineOpcode.
1808 if (User->getNodeId() == -1)
1812 // If we have a TokenFactor, we handle it specially.
1813 if (User->getOpcode() != ISD::TokenFactor) {
1814 // If the node isn't a token factor and isn't part of our pattern, then it
1815 // must be a random chained node in between two nodes we're selecting.
1816 // This happens when we have something like:
1821 // Because we structurally match the load/store as a read/modify/write,
1822 // but the call is chained between them. We cannot fold in this case
1823 // because it would induce a cycle in the graph.
1824 if (!std::count(ChainedNodesInPattern.begin(),
1825 ChainedNodesInPattern.end(), User))
1826 return CR_InducesCycle;
1828 // Otherwise we found a node that is part of our pattern. For example in:
1832 // This would happen when we're scanning down from the load and see the
1833 // store as a user. Record that there is a use of ChainedNode that is
1834 // part of the pattern and keep scanning uses.
1835 Result = CR_LeadsToInteriorNode;
1836 InteriorChainedNodes.push_back(User);
1840 // If we found a TokenFactor, there are two cases to consider: first if the
1841 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1842 // uses of the TF are in our pattern) we just want to ignore it. Second,
1843 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1849 // | \ DAG's like cheese
1852 // [TokenFactor] [Op]
1859 // In this case, the TokenFactor becomes part of our match and we rewrite it
1860 // as a new TokenFactor.
1862 // To distinguish these two cases, do a recursive walk down the uses.
1863 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1865 // If the uses of the TokenFactor are just already-selected nodes, ignore
1866 // it, it is "below" our pattern.
1868 case CR_InducesCycle:
1869 // If the uses of the TokenFactor lead to nodes that are not part of our
1870 // pattern that are not selected, folding would turn this into a cycle,
1872 return CR_InducesCycle;
1873 case CR_LeadsToInteriorNode:
1874 break; // Otherwise, keep processing.
1877 // Okay, we know we're in the interesting interior case. The TokenFactor
1878 // is now going to be considered part of the pattern so that we rewrite its
1879 // uses (it may have uses that are not part of the pattern) with the
1880 // ultimate chain result of the generated code. We will also add its chain
1881 // inputs as inputs to the ultimate TokenFactor we create.
1882 Result = CR_LeadsToInteriorNode;
1883 ChainedNodesInPattern.push_back(User);
1884 InteriorChainedNodes.push_back(User);
1891 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1892 /// operation for when the pattern matched at least one node with a chains. The
1893 /// input vector contains a list of all of the chained nodes that we match. We
1894 /// must determine if this is a valid thing to cover (i.e. matching it won't
1895 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1896 /// be used as the input node chain for the generated nodes.
1898 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1899 SelectionDAG *CurDAG) {
1900 // Walk all of the chained nodes we've matched, recursively scanning down the
1901 // users of the chain result. This adds any TokenFactor nodes that are caught
1902 // in between chained nodes to the chained and interior nodes list.
1903 SmallVector<SDNode*, 3> InteriorChainedNodes;
1904 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1905 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1906 InteriorChainedNodes) == CR_InducesCycle)
1907 return SDValue(); // Would induce a cycle.
1910 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1911 // that we are interested in. Form our input TokenFactor node.
1912 SmallVector<SDValue, 3> InputChains;
1913 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1914 // Add the input chain of this node to the InputChains list (which will be
1915 // the operands of the generated TokenFactor) if it's not an interior node.
1916 SDNode *N = ChainNodesMatched[i];
1917 if (N->getOpcode() != ISD::TokenFactor) {
1918 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1921 // Otherwise, add the input chain.
1922 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1923 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1924 InputChains.push_back(InChain);
1928 // If we have a token factor, we want to add all inputs of the token factor
1929 // that are not part of the pattern we're matching.
1930 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1931 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1932 N->getOperand(op).getNode()))
1933 InputChains.push_back(N->getOperand(op));
1938 if (InputChains.size() == 1)
1939 return InputChains[0];
1940 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1941 MVT::Other, &InputChains[0], InputChains.size());
1944 /// MorphNode - Handle morphing a node in place for the selector.
1945 SDNode *SelectionDAGISel::
1946 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1947 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1948 // It is possible we're using MorphNodeTo to replace a node with no
1949 // normal results with one that has a normal result (or we could be
1950 // adding a chain) and the input could have glue and chains as well.
1951 // In this case we need to shift the operands down.
1952 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1953 // than the old isel though.
1954 int OldGlueResultNo = -1, OldChainResultNo = -1;
1956 unsigned NTMNumResults = Node->getNumValues();
1957 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1958 OldGlueResultNo = NTMNumResults-1;
1959 if (NTMNumResults != 1 &&
1960 Node->getValueType(NTMNumResults-2) == MVT::Other)
1961 OldChainResultNo = NTMNumResults-2;
1962 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1963 OldChainResultNo = NTMNumResults-1;
1965 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1966 // that this deletes operands of the old node that become dead.
1967 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1969 // MorphNodeTo can operate in two ways: if an existing node with the
1970 // specified operands exists, it can just return it. Otherwise, it
1971 // updates the node in place to have the requested operands.
1973 // If we updated the node in place, reset the node ID. To the isel,
1974 // this should be just like a newly allocated machine node.
1978 unsigned ResNumResults = Res->getNumValues();
1979 // Move the glue if needed.
1980 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1981 (unsigned)OldGlueResultNo != ResNumResults-1)
1982 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1983 SDValue(Res, ResNumResults-1));
1985 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1988 // Move the chain reference if needed.
1989 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1990 (unsigned)OldChainResultNo != ResNumResults-1)
1991 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1992 SDValue(Res, ResNumResults-1));
1994 // Otherwise, no replacement happened because the node already exists. Replace
1995 // Uses of the old node with the new one.
1997 CurDAG->ReplaceAllUsesWith(Node, Res);
2002 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2003 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2004 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2006 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2007 // Accept if it is exactly the same as a previously recorded node.
2008 unsigned RecNo = MatcherTable[MatcherIndex++];
2009 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2010 return N == RecordedNodes[RecNo].first;
2013 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2014 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2015 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2016 SelectionDAGISel &SDISel) {
2017 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2020 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2021 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2022 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2023 SelectionDAGISel &SDISel, SDNode *N) {
2024 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2027 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2028 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2030 uint16_t Opc = MatcherTable[MatcherIndex++];
2031 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2032 return N->getOpcode() == Opc;
2035 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2036 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2037 SDValue N, const TargetLowering &TLI) {
2038 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2039 if (N.getValueType() == VT) return true;
2041 // Handle the case when VT is iPTR.
2042 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2045 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2046 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2047 SDValue N, const TargetLowering &TLI,
2049 if (ChildNo >= N.getNumOperands())
2050 return false; // Match fails if out of range child #.
2051 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2055 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2056 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2058 return cast<CondCodeSDNode>(N)->get() ==
2059 (ISD::CondCode)MatcherTable[MatcherIndex++];
2062 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2063 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2064 SDValue N, const TargetLowering &TLI) {
2065 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2066 if (cast<VTSDNode>(N)->getVT() == VT)
2069 // Handle the case when VT is iPTR.
2070 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2073 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2074 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2076 int64_t Val = MatcherTable[MatcherIndex++];
2078 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2080 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2081 return C != 0 && C->getSExtValue() == Val;
2084 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2085 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2086 SDValue N, SelectionDAGISel &SDISel) {
2087 int64_t Val = MatcherTable[MatcherIndex++];
2089 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2091 if (N->getOpcode() != ISD::AND) return false;
2093 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2094 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2097 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2098 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2099 SDValue N, SelectionDAGISel &SDISel) {
2100 int64_t Val = MatcherTable[MatcherIndex++];
2102 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2104 if (N->getOpcode() != ISD::OR) return false;
2106 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2107 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2110 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2111 /// scope, evaluate the current node. If the current predicate is known to
2112 /// fail, set Result=true and return anything. If the current predicate is
2113 /// known to pass, set Result=false and return the MatcherIndex to continue
2114 /// with. If the current predicate is unknown, set Result=false and return the
2115 /// MatcherIndex to continue with.
2116 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2117 unsigned Index, SDValue N,
2118 bool &Result, SelectionDAGISel &SDISel,
2119 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2120 switch (Table[Index++]) {
2123 return Index-1; // Could not evaluate this predicate.
2124 case SelectionDAGISel::OPC_CheckSame:
2125 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2127 case SelectionDAGISel::OPC_CheckPatternPredicate:
2128 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2130 case SelectionDAGISel::OPC_CheckPredicate:
2131 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2133 case SelectionDAGISel::OPC_CheckOpcode:
2134 Result = !::CheckOpcode(Table, Index, N.getNode());
2136 case SelectionDAGISel::OPC_CheckType:
2137 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2139 case SelectionDAGISel::OPC_CheckChild0Type:
2140 case SelectionDAGISel::OPC_CheckChild1Type:
2141 case SelectionDAGISel::OPC_CheckChild2Type:
2142 case SelectionDAGISel::OPC_CheckChild3Type:
2143 case SelectionDAGISel::OPC_CheckChild4Type:
2144 case SelectionDAGISel::OPC_CheckChild5Type:
2145 case SelectionDAGISel::OPC_CheckChild6Type:
2146 case SelectionDAGISel::OPC_CheckChild7Type:
2147 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2148 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2150 case SelectionDAGISel::OPC_CheckCondCode:
2151 Result = !::CheckCondCode(Table, Index, N);
2153 case SelectionDAGISel::OPC_CheckValueType:
2154 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2156 case SelectionDAGISel::OPC_CheckInteger:
2157 Result = !::CheckInteger(Table, Index, N);
2159 case SelectionDAGISel::OPC_CheckAndImm:
2160 Result = !::CheckAndImm(Table, Index, N, SDISel);
2162 case SelectionDAGISel::OPC_CheckOrImm:
2163 Result = !::CheckOrImm(Table, Index, N, SDISel);
2171 /// FailIndex - If this match fails, this is the index to continue with.
2174 /// NodeStack - The node stack when the scope was formed.
2175 SmallVector<SDValue, 4> NodeStack;
2177 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2178 unsigned NumRecordedNodes;
2180 /// NumMatchedMemRefs - The number of matched memref entries.
2181 unsigned NumMatchedMemRefs;
2183 /// InputChain/InputGlue - The current chain/glue
2184 SDValue InputChain, InputGlue;
2186 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2187 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2192 SDNode *SelectionDAGISel::
2193 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2194 unsigned TableSize) {
2195 // FIXME: Should these even be selected? Handle these cases in the caller?
2196 switch (NodeToMatch->getOpcode()) {
2199 case ISD::EntryToken: // These nodes remain the same.
2200 case ISD::BasicBlock:
2202 //case ISD::VALUETYPE:
2203 //case ISD::CONDCODE:
2204 case ISD::HANDLENODE:
2205 case ISD::MDNODE_SDNODE:
2206 case ISD::TargetConstant:
2207 case ISD::TargetConstantFP:
2208 case ISD::TargetConstantPool:
2209 case ISD::TargetFrameIndex:
2210 case ISD::TargetExternalSymbol:
2211 case ISD::TargetBlockAddress:
2212 case ISD::TargetJumpTable:
2213 case ISD::TargetGlobalTLSAddress:
2214 case ISD::TargetGlobalAddress:
2215 case ISD::TokenFactor:
2216 case ISD::CopyFromReg:
2217 case ISD::CopyToReg:
2219 NodeToMatch->setNodeId(-1); // Mark selected.
2221 case ISD::AssertSext:
2222 case ISD::AssertZext:
2223 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2224 NodeToMatch->getOperand(0));
2226 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2227 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2230 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2232 // Set up the node stack with NodeToMatch as the only node on the stack.
2233 SmallVector<SDValue, 8> NodeStack;
2234 SDValue N = SDValue(NodeToMatch, 0);
2235 NodeStack.push_back(N);
2237 // MatchScopes - Scopes used when matching, if a match failure happens, this
2238 // indicates where to continue checking.
2239 SmallVector<MatchScope, 8> MatchScopes;
2241 // RecordedNodes - This is the set of nodes that have been recorded by the
2242 // state machine. The second value is the parent of the node, or null if the
2243 // root is recorded.
2244 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2246 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2248 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2250 // These are the current input chain and glue for use when generating nodes.
2251 // Various Emit operations change these. For example, emitting a copytoreg
2252 // uses and updates these.
2253 SDValue InputChain, InputGlue;
2255 // ChainNodesMatched - If a pattern matches nodes that have input/output
2256 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2257 // which ones they are. The result is captured into this list so that we can
2258 // update the chain results when the pattern is complete.
2259 SmallVector<SDNode*, 3> ChainNodesMatched;
2260 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2262 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2263 NodeToMatch->dump(CurDAG);
2266 // Determine where to start the interpreter. Normally we start at opcode #0,
2267 // but if the state machine starts with an OPC_SwitchOpcode, then we
2268 // accelerate the first lookup (which is guaranteed to be hot) with the
2269 // OpcodeOffset table.
2270 unsigned MatcherIndex = 0;
2272 if (!OpcodeOffset.empty()) {
2273 // Already computed the OpcodeOffset table, just index into it.
2274 if (N.getOpcode() < OpcodeOffset.size())
2275 MatcherIndex = OpcodeOffset[N.getOpcode()];
2276 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2278 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2279 // Otherwise, the table isn't computed, but the state machine does start
2280 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2281 // is the first time we're selecting an instruction.
2284 // Get the size of this case.
2285 unsigned CaseSize = MatcherTable[Idx++];
2287 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2288 if (CaseSize == 0) break;
2290 // Get the opcode, add the index to the table.
2291 uint16_t Opc = MatcherTable[Idx++];
2292 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2293 if (Opc >= OpcodeOffset.size())
2294 OpcodeOffset.resize((Opc+1)*2);
2295 OpcodeOffset[Opc] = Idx;
2299 // Okay, do the lookup for the first opcode.
2300 if (N.getOpcode() < OpcodeOffset.size())
2301 MatcherIndex = OpcodeOffset[N.getOpcode()];
2305 assert(MatcherIndex < TableSize && "Invalid index");
2307 unsigned CurrentOpcodeIndex = MatcherIndex;
2309 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2312 // Okay, the semantics of this operation are that we should push a scope
2313 // then evaluate the first child. However, pushing a scope only to have
2314 // the first check fail (which then pops it) is inefficient. If we can
2315 // determine immediately that the first check (or first several) will
2316 // immediately fail, don't even bother pushing a scope for them.
2320 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2321 if (NumToSkip & 128)
2322 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2323 // Found the end of the scope with no match.
2324 if (NumToSkip == 0) {
2329 FailIndex = MatcherIndex+NumToSkip;
2331 unsigned MatcherIndexOfPredicate = MatcherIndex;
2332 (void)MatcherIndexOfPredicate; // silence warning.
2334 // If we can't evaluate this predicate without pushing a scope (e.g. if
2335 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2336 // push the scope and evaluate the full predicate chain.
2338 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2339 Result, *this, RecordedNodes);
2343 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2344 << "index " << MatcherIndexOfPredicate
2345 << ", continuing at " << FailIndex << "\n");
2346 ++NumDAGIselRetries;
2348 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2349 // move to the next case.
2350 MatcherIndex = FailIndex;
2353 // If the whole scope failed to match, bail.
2354 if (FailIndex == 0) break;
2356 // Push a MatchScope which indicates where to go if the first child fails
2358 MatchScope NewEntry;
2359 NewEntry.FailIndex = FailIndex;
2360 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2361 NewEntry.NumRecordedNodes = RecordedNodes.size();
2362 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2363 NewEntry.InputChain = InputChain;
2364 NewEntry.InputGlue = InputGlue;
2365 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2366 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2367 MatchScopes.push_back(NewEntry);
2370 case OPC_RecordNode: {
2371 // Remember this node, it may end up being an operand in the pattern.
2373 if (NodeStack.size() > 1)
2374 Parent = NodeStack[NodeStack.size()-2].getNode();
2375 RecordedNodes.push_back(std::make_pair(N, Parent));
2379 case OPC_RecordChild0: case OPC_RecordChild1:
2380 case OPC_RecordChild2: case OPC_RecordChild3:
2381 case OPC_RecordChild4: case OPC_RecordChild5:
2382 case OPC_RecordChild6: case OPC_RecordChild7: {
2383 unsigned ChildNo = Opcode-OPC_RecordChild0;
2384 if (ChildNo >= N.getNumOperands())
2385 break; // Match fails if out of range child #.
2387 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2391 case OPC_RecordMemRef:
2392 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2395 case OPC_CaptureGlueInput:
2396 // If the current node has an input glue, capture it in InputGlue.
2397 if (N->getNumOperands() != 0 &&
2398 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2399 InputGlue = N->getOperand(N->getNumOperands()-1);
2402 case OPC_MoveChild: {
2403 unsigned ChildNo = MatcherTable[MatcherIndex++];
2404 if (ChildNo >= N.getNumOperands())
2405 break; // Match fails if out of range child #.
2406 N = N.getOperand(ChildNo);
2407 NodeStack.push_back(N);
2411 case OPC_MoveParent:
2412 // Pop the current node off the NodeStack.
2413 NodeStack.pop_back();
2414 assert(!NodeStack.empty() && "Node stack imbalance!");
2415 N = NodeStack.back();
2419 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2421 case OPC_CheckPatternPredicate:
2422 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2424 case OPC_CheckPredicate:
2425 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2429 case OPC_CheckComplexPat: {
2430 unsigned CPNum = MatcherTable[MatcherIndex++];
2431 unsigned RecNo = MatcherTable[MatcherIndex++];
2432 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2433 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2434 RecordedNodes[RecNo].first, CPNum,
2439 case OPC_CheckOpcode:
2440 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2444 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2447 case OPC_SwitchOpcode: {
2448 unsigned CurNodeOpcode = N.getOpcode();
2449 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2452 // Get the size of this case.
2453 CaseSize = MatcherTable[MatcherIndex++];
2455 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2456 if (CaseSize == 0) break;
2458 uint16_t Opc = MatcherTable[MatcherIndex++];
2459 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2461 // If the opcode matches, then we will execute this case.
2462 if (CurNodeOpcode == Opc)
2465 // Otherwise, skip over this case.
2466 MatcherIndex += CaseSize;
2469 // If no cases matched, bail out.
2470 if (CaseSize == 0) break;
2472 // Otherwise, execute the case we found.
2473 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2474 << " to " << MatcherIndex << "\n");
2478 case OPC_SwitchType: {
2479 MVT CurNodeVT = N.getValueType().getSimpleVT();
2480 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2483 // Get the size of this case.
2484 CaseSize = MatcherTable[MatcherIndex++];
2486 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2487 if (CaseSize == 0) break;
2489 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2490 if (CaseVT == MVT::iPTR)
2491 CaseVT = TLI.getPointerTy();
2493 // If the VT matches, then we will execute this case.
2494 if (CurNodeVT == CaseVT)
2497 // Otherwise, skip over this case.
2498 MatcherIndex += CaseSize;
2501 // If no cases matched, bail out.
2502 if (CaseSize == 0) break;
2504 // Otherwise, execute the case we found.
2505 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2506 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2509 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2510 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2511 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2512 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2513 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2514 Opcode-OPC_CheckChild0Type))
2517 case OPC_CheckCondCode:
2518 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2520 case OPC_CheckValueType:
2521 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2523 case OPC_CheckInteger:
2524 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2526 case OPC_CheckAndImm:
2527 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2529 case OPC_CheckOrImm:
2530 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2533 case OPC_CheckFoldableChainNode: {
2534 assert(NodeStack.size() != 1 && "No parent node");
2535 // Verify that all intermediate nodes between the root and this one have
2537 bool HasMultipleUses = false;
2538 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2539 if (!NodeStack[i].hasOneUse()) {
2540 HasMultipleUses = true;
2543 if (HasMultipleUses) break;
2545 // Check to see that the target thinks this is profitable to fold and that
2546 // we can fold it without inducing cycles in the graph.
2547 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2549 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2550 NodeToMatch, OptLevel,
2551 true/*We validate our own chains*/))
2556 case OPC_EmitInteger: {
2557 MVT::SimpleValueType VT =
2558 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2559 int64_t Val = MatcherTable[MatcherIndex++];
2561 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2562 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2563 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2566 case OPC_EmitRegister: {
2567 MVT::SimpleValueType VT =
2568 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2569 unsigned RegNo = MatcherTable[MatcherIndex++];
2570 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2571 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2574 case OPC_EmitRegister2: {
2575 // For targets w/ more than 256 register names, the register enum
2576 // values are stored in two bytes in the matcher table (just like
2578 MVT::SimpleValueType VT =
2579 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2580 unsigned RegNo = MatcherTable[MatcherIndex++];
2581 RegNo |= MatcherTable[MatcherIndex++] << 8;
2582 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2583 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2587 case OPC_EmitConvertToTarget: {
2588 // Convert from IMM/FPIMM to target version.
2589 unsigned RecNo = MatcherTable[MatcherIndex++];
2590 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2591 SDValue Imm = RecordedNodes[RecNo].first;
2593 if (Imm->getOpcode() == ISD::Constant) {
2594 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2595 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2596 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2597 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2598 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2601 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2605 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2606 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2607 // These are space-optimized forms of OPC_EmitMergeInputChains.
2608 assert(InputChain.getNode() == 0 &&
2609 "EmitMergeInputChains should be the first chain producing node");
2610 assert(ChainNodesMatched.empty() &&
2611 "Should only have one EmitMergeInputChains per match");
2613 // Read all of the chained nodes.
2614 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2615 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2616 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2618 // FIXME: What if other value results of the node have uses not matched
2620 if (ChainNodesMatched.back() != NodeToMatch &&
2621 !RecordedNodes[RecNo].first.hasOneUse()) {
2622 ChainNodesMatched.clear();
2626 // Merge the input chains if they are not intra-pattern references.
2627 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2629 if (InputChain.getNode() == 0)
2630 break; // Failed to merge.
2634 case OPC_EmitMergeInputChains: {
2635 assert(InputChain.getNode() == 0 &&
2636 "EmitMergeInputChains should be the first chain producing node");
2637 // This node gets a list of nodes we matched in the input that have
2638 // chains. We want to token factor all of the input chains to these nodes
2639 // together. However, if any of the input chains is actually one of the
2640 // nodes matched in this pattern, then we have an intra-match reference.
2641 // Ignore these because the newly token factored chain should not refer to
2643 unsigned NumChains = MatcherTable[MatcherIndex++];
2644 assert(NumChains != 0 && "Can't TF zero chains");
2646 assert(ChainNodesMatched.empty() &&
2647 "Should only have one EmitMergeInputChains per match");
2649 // Read all of the chained nodes.
2650 for (unsigned i = 0; i != NumChains; ++i) {
2651 unsigned RecNo = MatcherTable[MatcherIndex++];
2652 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2653 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2655 // FIXME: What if other value results of the node have uses not matched
2657 if (ChainNodesMatched.back() != NodeToMatch &&
2658 !RecordedNodes[RecNo].first.hasOneUse()) {
2659 ChainNodesMatched.clear();
2664 // If the inner loop broke out, the match fails.
2665 if (ChainNodesMatched.empty())
2668 // Merge the input chains if they are not intra-pattern references.
2669 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2671 if (InputChain.getNode() == 0)
2672 break; // Failed to merge.
2677 case OPC_EmitCopyToReg: {
2678 unsigned RecNo = MatcherTable[MatcherIndex++];
2679 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2680 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2682 if (InputChain.getNode() == 0)
2683 InputChain = CurDAG->getEntryNode();
2685 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2686 DestPhysReg, RecordedNodes[RecNo].first,
2689 InputGlue = InputChain.getValue(1);
2693 case OPC_EmitNodeXForm: {
2694 unsigned XFormNo = MatcherTable[MatcherIndex++];
2695 unsigned RecNo = MatcherTable[MatcherIndex++];
2696 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2697 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2698 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2703 case OPC_MorphNodeTo: {
2704 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2705 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2706 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2707 // Get the result VT list.
2708 unsigned NumVTs = MatcherTable[MatcherIndex++];
2709 SmallVector<EVT, 4> VTs;
2710 for (unsigned i = 0; i != NumVTs; ++i) {
2711 MVT::SimpleValueType VT =
2712 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2713 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2717 if (EmitNodeInfo & OPFL_Chain)
2718 VTs.push_back(MVT::Other);
2719 if (EmitNodeInfo & OPFL_GlueOutput)
2720 VTs.push_back(MVT::Glue);
2722 // This is hot code, so optimize the two most common cases of 1 and 2
2725 if (VTs.size() == 1)
2726 VTList = CurDAG->getVTList(VTs[0]);
2727 else if (VTs.size() == 2)
2728 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2730 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2732 // Get the operand list.
2733 unsigned NumOps = MatcherTable[MatcherIndex++];
2734 SmallVector<SDValue, 8> Ops;
2735 for (unsigned i = 0; i != NumOps; ++i) {
2736 unsigned RecNo = MatcherTable[MatcherIndex++];
2738 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2740 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2741 Ops.push_back(RecordedNodes[RecNo].first);
2744 // If there are variadic operands to add, handle them now.
2745 if (EmitNodeInfo & OPFL_VariadicInfo) {
2746 // Determine the start index to copy from.
2747 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2748 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2749 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2750 "Invalid variadic node");
2751 // Copy all of the variadic operands, not including a potential glue
2753 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2755 SDValue V = NodeToMatch->getOperand(i);
2756 if (V.getValueType() == MVT::Glue) break;
2761 // If this has chain/glue inputs, add them.
2762 if (EmitNodeInfo & OPFL_Chain)
2763 Ops.push_back(InputChain);
2764 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2765 Ops.push_back(InputGlue);
2769 if (Opcode != OPC_MorphNodeTo) {
2770 // If this is a normal EmitNode command, just create the new node and
2771 // add the results to the RecordedNodes list.
2772 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2773 VTList, Ops.data(), Ops.size());
2775 // Add all the non-glue/non-chain results to the RecordedNodes list.
2776 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2777 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2778 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2783 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2787 // If the node had chain/glue results, update our notion of the current
2789 if (EmitNodeInfo & OPFL_GlueOutput) {
2790 InputGlue = SDValue(Res, VTs.size()-1);
2791 if (EmitNodeInfo & OPFL_Chain)
2792 InputChain = SDValue(Res, VTs.size()-2);
2793 } else if (EmitNodeInfo & OPFL_Chain)
2794 InputChain = SDValue(Res, VTs.size()-1);
2796 // If the OPFL_MemRefs glue is set on this node, slap all of the
2797 // accumulated memrefs onto it.
2799 // FIXME: This is vastly incorrect for patterns with multiple outputs
2800 // instructions that access memory and for ComplexPatterns that match
2802 if (EmitNodeInfo & OPFL_MemRefs) {
2803 // Only attach load or store memory operands if the generated
2804 // instruction may load or store.
2805 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2806 bool mayLoad = MCID.mayLoad();
2807 bool mayStore = MCID.mayStore();
2809 unsigned NumMemRefs = 0;
2810 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2811 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2812 if ((*I)->isLoad()) {
2815 } else if ((*I)->isStore()) {
2823 MachineSDNode::mmo_iterator MemRefs =
2824 MF->allocateMemRefsArray(NumMemRefs);
2826 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2827 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2828 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2829 if ((*I)->isLoad()) {
2832 } else if ((*I)->isStore()) {
2840 cast<MachineSDNode>(Res)
2841 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2845 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2846 << " node: "; Res->dump(CurDAG); errs() << "\n");
2848 // If this was a MorphNodeTo then we're completely done!
2849 if (Opcode == OPC_MorphNodeTo) {
2850 // Update chain and glue uses.
2851 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2852 InputGlue, GlueResultNodesMatched, true);
2859 case OPC_MarkGlueResults: {
2860 unsigned NumNodes = MatcherTable[MatcherIndex++];
2862 // Read and remember all the glue-result nodes.
2863 for (unsigned i = 0; i != NumNodes; ++i) {
2864 unsigned RecNo = MatcherTable[MatcherIndex++];
2866 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2868 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2869 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2874 case OPC_CompleteMatch: {
2875 // The match has been completed, and any new nodes (if any) have been
2876 // created. Patch up references to the matched dag to use the newly
2878 unsigned NumResults = MatcherTable[MatcherIndex++];
2880 for (unsigned i = 0; i != NumResults; ++i) {
2881 unsigned ResSlot = MatcherTable[MatcherIndex++];
2883 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2885 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2886 SDValue Res = RecordedNodes[ResSlot].first;
2888 assert(i < NodeToMatch->getNumValues() &&
2889 NodeToMatch->getValueType(i) != MVT::Other &&
2890 NodeToMatch->getValueType(i) != MVT::Glue &&
2891 "Invalid number of results to complete!");
2892 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2893 NodeToMatch->getValueType(i) == MVT::iPTR ||
2894 Res.getValueType() == MVT::iPTR ||
2895 NodeToMatch->getValueType(i).getSizeInBits() ==
2896 Res.getValueType().getSizeInBits()) &&
2897 "invalid replacement");
2898 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2901 // If the root node defines glue, add it to the glue nodes to update list.
2902 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2903 GlueResultNodesMatched.push_back(NodeToMatch);
2905 // Update chain and glue uses.
2906 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2907 InputGlue, GlueResultNodesMatched, false);
2909 assert(NodeToMatch->use_empty() &&
2910 "Didn't replace all uses of the node?");
2912 // FIXME: We just return here, which interacts correctly with SelectRoot
2913 // above. We should fix this to not return an SDNode* anymore.
2918 // If the code reached this point, then the match failed. See if there is
2919 // another child to try in the current 'Scope', otherwise pop it until we
2920 // find a case to check.
2921 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2922 ++NumDAGIselRetries;
2924 if (MatchScopes.empty()) {
2925 CannotYetSelect(NodeToMatch);
2929 // Restore the interpreter state back to the point where the scope was
2931 MatchScope &LastScope = MatchScopes.back();
2932 RecordedNodes.resize(LastScope.NumRecordedNodes);
2934 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2935 N = NodeStack.back();
2937 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2938 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2939 MatcherIndex = LastScope.FailIndex;
2941 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2943 InputChain = LastScope.InputChain;
2944 InputGlue = LastScope.InputGlue;
2945 if (!LastScope.HasChainNodesMatched)
2946 ChainNodesMatched.clear();
2947 if (!LastScope.HasGlueResultNodesMatched)
2948 GlueResultNodesMatched.clear();
2950 // Check to see what the offset is at the new MatcherIndex. If it is zero
2951 // we have reached the end of this scope, otherwise we have another child
2952 // in the current scope to try.
2953 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2954 if (NumToSkip & 128)
2955 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2957 // If we have another child in this scope to match, update FailIndex and
2959 if (NumToSkip != 0) {
2960 LastScope.FailIndex = MatcherIndex+NumToSkip;
2964 // End of this scope, pop it and try the next child in the containing
2966 MatchScopes.pop_back();
2973 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2975 raw_string_ostream Msg(msg);
2976 Msg << "Cannot select: ";
2978 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2979 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2980 N->getOpcode() != ISD::INTRINSIC_VOID) {
2981 N->printrFull(Msg, CurDAG);
2983 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2985 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2986 if (iid < Intrinsic::num_intrinsics)
2987 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2988 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2989 Msg << "target intrinsic %" << TII->getName(iid);
2991 Msg << "unknown intrinsic #" << iid;
2993 report_fatal_error(Msg.str());
2996 char SelectionDAGISel::ID = 0;