1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/Constants.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Instructions.h"
20 #include "llvm/Intrinsics.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
39 ViewDAGs("view-isel-dags", cl::Hidden,
40 cl::desc("Pop up a window to show isel dags as they are selected"));
42 static const bool ViewDAGS = 0;
46 //===--------------------------------------------------------------------===//
47 /// FunctionLoweringInfo - This contains information that is global to a
48 /// function that is used when lowering a region of the function.
49 class FunctionLoweringInfo {
56 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
58 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
59 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
61 /// ValueMap - Since we emit code for the function a basic block at a time,
62 /// we must remember which virtual registers hold the values for
63 /// cross-basic-block values.
64 std::map<const Value*, unsigned> ValueMap;
66 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
67 /// the entry block. This allows the allocas to be efficiently referenced
68 /// anywhere in the function.
69 std::map<const AllocaInst*, int> StaticAllocaMap;
71 /// BlockLocalArguments - If any arguments are only used in a single basic
72 /// block, and if the target can access the arguments without side-effects,
73 /// avoid emitting CopyToReg nodes for those arguments. This map keeps
74 /// track of which arguments are local to each BB.
75 std::multimap<BasicBlock*, std::pair<Argument*,
76 unsigned> > BlockLocalArguments;
79 unsigned MakeReg(MVT::ValueType VT) {
80 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
83 unsigned CreateRegForValue(const Value *V) {
84 MVT::ValueType VT = TLI.getValueType(V->getType());
85 // The common case is that we will only create one register for this
86 // value. If we have that case, create and return the virtual register.
87 unsigned NV = TLI.getNumElements(VT);
89 // If we are promoting this value, pick the next largest supported type.
90 return MakeReg(TLI.getTypeToTransformTo(VT));
93 // If this value is represented with multiple target registers, make sure
94 // to create enough consequtive registers of the right (smaller) type.
95 unsigned NT = VT-1; // Find the type to use.
96 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
99 unsigned R = MakeReg((MVT::ValueType)NT);
100 for (unsigned i = 1; i != NV; ++i)
101 MakeReg((MVT::ValueType)NT);
105 unsigned InitializeRegForValue(const Value *V) {
106 unsigned &R = ValueMap[V];
107 assert(R == 0 && "Already initialized this value register!");
108 return R = CreateRegForValue(V);
113 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
114 /// PHI nodes or outside of the basic block that defines it.
115 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
116 if (isa<PHINode>(I)) return true;
117 BasicBlock *BB = I->getParent();
118 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
119 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
124 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
125 Function &fn, MachineFunction &mf)
126 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
128 // Initialize the mapping of values to registers. This is only set up for
129 // instruction values that are used outside of the block that defines
131 for (Function::aiterator AI = Fn.abegin(), E = Fn.aend(); AI != E; ++AI)
132 InitializeRegForValue(AI);
134 Function::iterator BB = Fn.begin(), E = Fn.end();
135 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
136 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
137 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
138 const Type *Ty = AI->getAllocatedType();
139 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
140 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
141 TySize *= CUI->getValue(); // Get total allocated size.
142 StaticAllocaMap[AI] =
143 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
146 for (; BB != E; ++BB)
147 for (BasicBlock::iterator I = BB->begin(), e = BB->end(); I != e; ++I)
148 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
149 if (!isa<AllocaInst>(I) ||
150 !StaticAllocaMap.count(cast<AllocaInst>(I)))
151 InitializeRegForValue(I);
153 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
154 // also creates the initial PHI MachineInstrs, though none of the input
155 // operands are populated.
156 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
157 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
159 MF.getBasicBlockList().push_back(MBB);
161 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
164 for (BasicBlock::iterator I = BB->begin();
165 (PN = dyn_cast<PHINode>(I)); ++I)
166 if (!PN->use_empty()) {
167 unsigned NumElements =
168 TLI.getNumElements(TLI.getValueType(PN->getType()));
169 unsigned PHIReg = ValueMap[PN];
170 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
171 for (unsigned i = 0; i != NumElements; ++i)
172 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
179 //===----------------------------------------------------------------------===//
180 /// SelectionDAGLowering - This is the common target-independent lowering
181 /// implementation that is parameterized by a TargetLowering object.
182 /// Also, targets can overload any lowering method.
185 class SelectionDAGLowering {
186 MachineBasicBlock *CurMBB;
188 std::map<const Value*, SDOperand> NodeMap;
190 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
191 /// them up and then emit token factor nodes when possible. This allows us to
192 /// get simple disambiguation between loads without worrying about alias
194 std::vector<SDOperand> PendingLoads;
197 // TLI - This is information that describes the available target features we
198 // need for lowering. This indicates when operations are unavailable,
199 // implemented with a libcall, etc.
202 const TargetData &TD;
204 /// FuncInfo - Information about the function as a whole.
206 FunctionLoweringInfo &FuncInfo;
208 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
209 FunctionLoweringInfo &funcinfo)
210 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
214 /// getRoot - Return the current virtual root of the Selection DAG.
216 SDOperand getRoot() {
217 if (PendingLoads.empty())
218 return DAG.getRoot();
220 if (PendingLoads.size() == 1) {
221 SDOperand Root = PendingLoads[0];
223 PendingLoads.clear();
227 // Otherwise, we have to make a token factor node.
228 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
229 PendingLoads.clear();
234 void visit(Instruction &I) { visit(I.getOpcode(), I); }
236 void visit(unsigned Opcode, User &I) {
238 default: assert(0 && "Unknown instruction type encountered!");
240 // Build the switch statement using the Instruction.def file.
241 #define HANDLE_INST(NUM, OPCODE, CLASS) \
242 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
243 #include "llvm/Instruction.def"
247 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
250 SDOperand getIntPtrConstant(uint64_t Val) {
251 return DAG.getConstant(Val, TLI.getPointerTy());
254 SDOperand getValue(const Value *V) {
255 SDOperand &N = NodeMap[V];
258 MVT::ValueType VT = TLI.getValueType(V->getType());
259 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V)))
260 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
261 visit(CE->getOpcode(), *CE);
262 assert(N.Val && "visit didn't populate the ValueMap!");
264 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
265 return N = DAG.getGlobalAddress(GV, VT);
266 } else if (isa<ConstantPointerNull>(C)) {
267 return N = DAG.getConstant(0, TLI.getPointerTy());
268 } else if (isa<UndefValue>(C)) {
269 /// FIXME: Implement UNDEFVALUE better.
270 if (MVT::isInteger(VT))
271 return N = DAG.getConstant(0, VT);
272 else if (MVT::isFloatingPoint(VT))
273 return N = DAG.getConstantFP(0, VT);
275 assert(0 && "Unknown value type!");
277 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
278 return N = DAG.getConstantFP(CFP->getValue(), VT);
280 // Canonicalize all constant ints to be unsigned.
281 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
284 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
285 std::map<const AllocaInst*, int>::iterator SI =
286 FuncInfo.StaticAllocaMap.find(AI);
287 if (SI != FuncInfo.StaticAllocaMap.end())
288 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
291 std::map<const Value*, unsigned>::const_iterator VMI =
292 FuncInfo.ValueMap.find(V);
293 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
295 MVT::ValueType RegVT = VT;
296 if (TLI.getTypeAction(VT) == 1) // Must promote this value?
297 RegVT = TLI.getTypeToTransformTo(VT);
299 N = DAG.getCopyFromReg(VMI->second, RegVT, DAG.getEntryNode());
302 if (MVT::isFloatingPoint(VT))
303 N = DAG.getNode(ISD::FP_ROUND, VT, N);
305 N = DAG.getNode(ISD::TRUNCATE, VT, N);
310 const SDOperand &setValue(const Value *V, SDOperand NewN) {
311 SDOperand &N = NodeMap[V];
312 assert(N.Val == 0 && "Already set a value for this node!");
316 // Terminator instructions.
317 void visitRet(ReturnInst &I);
318 void visitBr(BranchInst &I);
319 void visitUnreachable(UnreachableInst &I) { /* noop */ }
321 // These all get lowered before this pass.
322 void visitSwitch(SwitchInst &I) { assert(0 && "TODO"); }
323 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
324 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
327 void visitBinary(User &I, unsigned Opcode);
328 void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
329 void visitSub(User &I) { visitBinary(I, ISD::SUB); }
330 void visitMul(User &I) { visitBinary(I, ISD::MUL); }
331 void visitDiv(User &I) {
332 visitBinary(I, I.getType()->isUnsigned() ? ISD::UDIV : ISD::SDIV);
334 void visitRem(User &I) {
335 visitBinary(I, I.getType()->isUnsigned() ? ISD::UREM : ISD::SREM);
337 void visitAnd(User &I) { visitBinary(I, ISD::AND); }
338 void visitOr (User &I) { visitBinary(I, ISD::OR); }
339 void visitXor(User &I) { visitBinary(I, ISD::XOR); }
340 void visitShl(User &I) { visitBinary(I, ISD::SHL); }
341 void visitShr(User &I) {
342 visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
345 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
346 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ); }
347 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE); }
348 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE); }
349 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE); }
350 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
351 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
353 void visitGetElementPtr(User &I);
354 void visitCast(User &I);
355 void visitSelect(User &I);
358 void visitMalloc(MallocInst &I);
359 void visitFree(FreeInst &I);
360 void visitAlloca(AllocaInst &I);
361 void visitLoad(LoadInst &I);
362 void visitStore(StoreInst &I);
363 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
364 void visitCall(CallInst &I);
366 void visitVAStart(CallInst &I);
367 void visitVANext(VANextInst &I);
368 void visitVAArg(VAArgInst &I);
369 void visitVAEnd(CallInst &I);
370 void visitVACopy(CallInst &I);
371 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
373 void visitMemIntrinsic(CallInst &I, unsigned Op);
375 void visitUserOp1(Instruction &I) {
376 assert(0 && "UserOp1 should not exist at instruction selection time!");
379 void visitUserOp2(Instruction &I) {
380 assert(0 && "UserOp2 should not exist at instruction selection time!");
384 } // end namespace llvm
386 void SelectionDAGLowering::visitRet(ReturnInst &I) {
387 if (I.getNumOperands() == 0) {
388 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
392 SDOperand Op1 = getValue(I.getOperand(0));
393 switch (Op1.getValueType()) {
394 default: assert(0 && "Unknown value type!");
398 // Extend integer types to 32-bits.
399 if (I.getOperand(0)->getType()->isSigned())
400 Op1 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Op1);
402 Op1 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op1);
405 // Extend float to double.
406 Op1 = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op1);
411 break; // No extension needed!
414 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot(), Op1));
417 void SelectionDAGLowering::visitBr(BranchInst &I) {
418 // Update machine-CFG edges.
419 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
420 CurMBB->addSuccessor(Succ0MBB);
422 // Figure out which block is immediately after the current one.
423 MachineBasicBlock *NextBlock = 0;
424 MachineFunction::iterator BBI = CurMBB;
425 if (++BBI != CurMBB->getParent()->end())
428 if (I.isUnconditional()) {
429 // If this is not a fall-through branch, emit the branch.
430 if (Succ0MBB != NextBlock)
431 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
432 DAG.getBasicBlock(Succ0MBB)));
434 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
435 CurMBB->addSuccessor(Succ1MBB);
437 SDOperand Cond = getValue(I.getCondition());
439 if (Succ1MBB == NextBlock) {
440 // If the condition is false, fall through. This means we should branch
441 // if the condition is true to Succ #0.
442 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
443 Cond, DAG.getBasicBlock(Succ0MBB)));
444 } else if (Succ0MBB == NextBlock) {
445 // If the condition is true, fall through. This means we should branch if
446 // the condition is false to Succ #1. Invert the condition first.
447 SDOperand True = DAG.getConstant(1, Cond.getValueType());
448 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
449 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
450 Cond, DAG.getBasicBlock(Succ1MBB)));
452 // Neither edge is a fall through. If the comparison is true, jump to
453 // Succ#0, otherwise branch unconditionally to succ #1.
454 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
455 Cond, DAG.getBasicBlock(Succ0MBB)));
456 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
457 DAG.getBasicBlock(Succ1MBB)));
462 void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode) {
463 SDOperand Op1 = getValue(I.getOperand(0));
464 SDOperand Op2 = getValue(I.getOperand(1));
465 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
468 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
469 ISD::CondCode UnsignedOpcode) {
470 SDOperand Op1 = getValue(I.getOperand(0));
471 SDOperand Op2 = getValue(I.getOperand(1));
472 ISD::CondCode Opcode = SignedOpcode;
473 if (I.getOperand(0)->getType()->isUnsigned())
474 Opcode = UnsignedOpcode;
475 setValue(&I, DAG.getSetCC(Opcode, MVT::i1, Op1, Op2));
478 void SelectionDAGLowering::visitSelect(User &I) {
479 SDOperand Cond = getValue(I.getOperand(0));
480 SDOperand TrueVal = getValue(I.getOperand(1));
481 SDOperand FalseVal = getValue(I.getOperand(2));
482 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
486 void SelectionDAGLowering::visitCast(User &I) {
487 SDOperand N = getValue(I.getOperand(0));
488 MVT::ValueType SrcTy = TLI.getValueType(I.getOperand(0)->getType());
489 MVT::ValueType DestTy = TLI.getValueType(I.getType());
491 if (N.getValueType() == DestTy) {
492 setValue(&I, N); // noop cast.
493 } else if (isInteger(SrcTy)) {
494 if (isInteger(DestTy)) { // Int -> Int cast
495 if (DestTy < SrcTy) // Truncating cast?
496 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestTy, N));
497 else if (I.getOperand(0)->getType()->isSigned())
498 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestTy, N));
500 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestTy, N));
501 } else { // Int -> FP cast
502 if (I.getOperand(0)->getType()->isSigned())
503 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestTy, N));
505 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestTy, N));
508 assert(isFloatingPoint(SrcTy) && "Unknown value type!");
509 if (isFloatingPoint(DestTy)) { // FP -> FP cast
510 if (DestTy < SrcTy) // Rounding cast?
511 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestTy, N));
513 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestTy, N));
514 } else { // FP -> Int cast.
515 if (I.getType()->isSigned())
516 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestTy, N));
518 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestTy, N));
523 void SelectionDAGLowering::visitGetElementPtr(User &I) {
524 SDOperand N = getValue(I.getOperand(0));
525 const Type *Ty = I.getOperand(0)->getType();
526 const Type *UIntPtrTy = TD.getIntPtrType();
528 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
531 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
532 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
535 uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field];
536 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
537 getIntPtrConstant(Offset));
539 Ty = StTy->getElementType(Field);
541 Ty = cast<SequentialType>(Ty)->getElementType();
542 if (!isa<Constant>(Idx) || !cast<Constant>(Idx)->isNullValue()) {
543 // N = N + Idx * ElementSize;
544 uint64_t ElementSize = TD.getTypeSize(Ty);
545 SDOperand IdxN = getValue(Idx), Scale = getIntPtrConstant(ElementSize);
547 // If the index is smaller or larger than intptr_t, truncate or extend
549 if (IdxN.getValueType() < Scale.getValueType()) {
550 if (Idx->getType()->isSigned())
551 IdxN = DAG.getNode(ISD::SIGN_EXTEND, Scale.getValueType(), IdxN);
553 IdxN = DAG.getNode(ISD::ZERO_EXTEND, Scale.getValueType(), IdxN);
554 } else if (IdxN.getValueType() > Scale.getValueType())
555 IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN);
557 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
559 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
566 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
567 // If this is a fixed sized alloca in the entry block of the function,
568 // allocate it statically on the stack.
569 if (FuncInfo.StaticAllocaMap.count(&I))
570 return; // getValue will auto-populate this.
572 const Type *Ty = I.getAllocatedType();
573 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
574 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
576 SDOperand AllocSize = getValue(I.getArraySize());
578 assert(AllocSize.getValueType() == TLI.getPointerTy() &&
579 "FIXME: should extend or truncate to pointer size!");
581 AllocSize = DAG.getNode(ISD::MUL, TLI.getPointerTy(), AllocSize,
582 getIntPtrConstant(TySize));
584 // Handle alignment. If the requested alignment is less than or equal to the
585 // stack alignment, ignore it and round the size of the allocation up to the
586 // stack alignment size. If the size is greater than the stack alignment, we
587 // note this in the DYNAMIC_STACKALLOC node.
588 unsigned StackAlign =
589 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
590 if (Align <= StackAlign) {
592 // Add SA-1 to the size.
593 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
594 getIntPtrConstant(StackAlign-1));
595 // Mask out the low bits for alignment purposes.
596 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
597 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
600 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, AllocSize.getValueType(),
601 getRoot(), AllocSize,
602 getIntPtrConstant(Align));
603 DAG.setRoot(setValue(&I, DSA).getValue(1));
605 // Inform the Frame Information that we have just allocated a variable-sized
607 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
611 void SelectionDAGLowering::visitLoad(LoadInst &I) {
612 SDOperand Ptr = getValue(I.getOperand(0));
618 // Do not serialize non-volatile loads against each other.
619 Root = DAG.getRoot();
622 SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr);
626 DAG.setRoot(L.getValue(1));
628 PendingLoads.push_back(L.getValue(1));
632 void SelectionDAGLowering::visitStore(StoreInst &I) {
633 Value *SrcV = I.getOperand(0);
634 SDOperand Src = getValue(SrcV);
635 SDOperand Ptr = getValue(I.getOperand(1));
636 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr));
639 void SelectionDAGLowering::visitCall(CallInst &I) {
640 const char *RenameFn = 0;
641 if (Function *F = I.getCalledFunction())
642 switch (F->getIntrinsicID()) {
643 case 0: break; // Not an intrinsic.
644 case Intrinsic::vastart: visitVAStart(I); return;
645 case Intrinsic::vaend: visitVAEnd(I); return;
646 case Intrinsic::vacopy: visitVACopy(I); return;
647 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return;
648 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return;
650 // FIXME: IMPLEMENT THESE.
651 // readport, writeport, readio, writeio
652 assert(0 && "This intrinsic is not implemented yet!");
654 case Intrinsic::setjmp: RenameFn = "setjmp"; break;
655 case Intrinsic::longjmp: RenameFn = "longjmp"; break;
656 case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return;
657 case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return;
658 case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
660 case Intrinsic::isunordered:
661 setValue(&I, DAG.getSetCC(ISD::SETUO, MVT::i1, getValue(I.getOperand(1)),
662 getValue(I.getOperand(2))));
668 Callee = getValue(I.getOperand(0));
670 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
671 std::vector<std::pair<SDOperand, const Type*> > Args;
673 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
674 Value *Arg = I.getOperand(i);
675 SDOperand ArgNode = getValue(Arg);
676 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
679 std::pair<SDOperand,SDOperand> Result =
680 TLI.LowerCallTo(getRoot(), I.getType(), Callee, Args, DAG);
681 if (I.getType() != Type::VoidTy)
682 setValue(&I, Result.first);
683 DAG.setRoot(Result.second);
686 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
687 SDOperand Src = getValue(I.getOperand(0));
689 MVT::ValueType IntPtr = TLI.getPointerTy();
690 // FIXME: Extend or truncate to the intptr size.
691 assert(Src.getValueType() == IntPtr && "Need to adjust the amount!");
693 // Scale the source by the type size.
694 uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType());
695 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
696 Src, getIntPtrConstant(ElementSize));
698 std::vector<std::pair<SDOperand, const Type*> > Args;
699 Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
701 std::pair<SDOperand,SDOperand> Result =
702 TLI.LowerCallTo(getRoot(), I.getType(),
703 DAG.getExternalSymbol("malloc", IntPtr),
705 setValue(&I, Result.first); // Pointers always fit in registers
706 DAG.setRoot(Result.second);
709 void SelectionDAGLowering::visitFree(FreeInst &I) {
710 std::vector<std::pair<SDOperand, const Type*> > Args;
711 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
712 TLI.getTargetData().getIntPtrType()));
713 MVT::ValueType IntPtr = TLI.getPointerTy();
714 std::pair<SDOperand,SDOperand> Result =
715 TLI.LowerCallTo(getRoot(), Type::VoidTy,
716 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
717 DAG.setRoot(Result.second);
720 std::pair<SDOperand, SDOperand>
721 TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
722 // We have no sane default behavior, just emit a useful error message and bail
724 std::cerr << "Variable arguments handling not implemented on this target!\n";
728 SDOperand TargetLowering::LowerVAEnd(SDOperand Chain, SDOperand L,
730 // Default to a noop.
734 std::pair<SDOperand,SDOperand>
735 TargetLowering::LowerVACopy(SDOperand Chain, SDOperand L, SelectionDAG &DAG) {
736 // Default to returning the input list.
737 return std::make_pair(L, Chain);
740 std::pair<SDOperand,SDOperand>
741 TargetLowering::LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
742 const Type *ArgTy, SelectionDAG &DAG) {
743 // We have no sane default behavior, just emit a useful error message and bail
745 std::cerr << "Variable arguments handling not implemented on this target!\n";
750 void SelectionDAGLowering::visitVAStart(CallInst &I) {
751 std::pair<SDOperand,SDOperand> Result = TLI.LowerVAStart(getRoot(), DAG);
752 setValue(&I, Result.first);
753 DAG.setRoot(Result.second);
756 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
757 std::pair<SDOperand,SDOperand> Result =
758 TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)),
760 setValue(&I, Result.first);
761 DAG.setRoot(Result.second);
764 void SelectionDAGLowering::visitVANext(VANextInst &I) {
765 std::pair<SDOperand,SDOperand> Result =
766 TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)),
767 I.getArgType(), DAG);
768 setValue(&I, Result.first);
769 DAG.setRoot(Result.second);
772 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
773 DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)), DAG));
776 void SelectionDAGLowering::visitVACopy(CallInst &I) {
777 std::pair<SDOperand,SDOperand> Result =
778 TLI.LowerVACopy(getRoot(), getValue(I.getOperand(1)), DAG);
779 setValue(&I, Result.first);
780 DAG.setRoot(Result.second);
784 // It is always conservatively correct for llvm.returnaddress and
785 // llvm.frameaddress to return 0.
786 std::pair<SDOperand, SDOperand>
787 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
788 unsigned Depth, SelectionDAG &DAG) {
789 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
792 SDOperand TargetLowering::LowerOperation(SDOperand Op) {
793 assert(0 && "LowerOperation not implemented for this target!");
797 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
798 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
799 std::pair<SDOperand,SDOperand> Result =
800 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
801 setValue(&I, Result.first);
802 DAG.setRoot(Result.second);
805 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
806 std::vector<SDOperand> Ops;
807 Ops.push_back(getRoot());
808 Ops.push_back(getValue(I.getOperand(1)));
809 Ops.push_back(getValue(I.getOperand(2)));
810 Ops.push_back(getValue(I.getOperand(3)));
811 Ops.push_back(getValue(I.getOperand(4)));
812 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
815 //===----------------------------------------------------------------------===//
816 // SelectionDAGISel code
817 //===----------------------------------------------------------------------===//
819 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
820 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
825 bool SelectionDAGISel::runOnFunction(Function &Fn) {
826 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
827 RegMap = MF.getSSARegMap();
828 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
830 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
832 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
833 SelectBasicBlock(I, MF, FuncInfo);
839 SDOperand SelectionDAGISel::
840 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
841 SelectionDAG &DAG = SDL.DAG;
842 SDOperand Op = SDL.getValue(V);
843 assert((Op.getOpcode() != ISD::CopyFromReg ||
844 cast<RegSDNode>(Op)->getReg() != Reg) &&
845 "Copy from a reg to the same reg!");
846 MVT::ValueType VT = Op.getValueType();
847 if (TLI.getTypeAction(VT) == 1) { // Must promote this value?
848 if (MVT::isFloatingPoint(VT))
849 Op = DAG.getNode(ISD::FP_EXTEND, TLI.getTypeToTransformTo(VT), Op);
851 Op = DAG.getNode(ISD::ZERO_EXTEND, TLI.getTypeToTransformTo(VT), Op);
854 return DAG.getCopyToReg(SDL.getRoot(), Op, Reg);
857 /// IsOnlyUsedInOneBasicBlock - If the specified argument is only used in a
858 /// single basic block, return that block. Otherwise, return a null pointer.
859 static BasicBlock *IsOnlyUsedInOneBasicBlock(Argument *A) {
860 if (A->use_empty()) return 0;
861 BasicBlock *BB = cast<Instruction>(A->use_back())->getParent();
862 for (Argument::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E;
864 if (isa<PHINode>(*UI) || cast<Instruction>(*UI)->getParent() != BB)
865 return 0; // Disagreement among the users?
869 void SelectionDAGISel::
870 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
871 std::vector<SDOperand> &UnorderedChains) {
872 // If this is the entry block, emit arguments.
873 Function &F = *BB->getParent();
874 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
876 if (BB == &F.front()) {
877 SDOperand OldRoot = SDL.DAG.getRoot();
879 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
881 // If there were side effects accessing the argument list, do not do
883 if (OldRoot != SDL.DAG.getRoot()) {
885 for (Function::aiterator AI = F.abegin(), E = F.aend(); AI != E; ++AI,++a)
886 if (!AI->use_empty()) {
887 SDL.setValue(AI, Args[a]);
889 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
890 UnorderedChains.push_back(Copy);
893 // Otherwise, if any argument is only accessed in a single basic block,
894 // emit that argument only to that basic block.
896 for (Function::aiterator AI = F.abegin(), E = F.aend(); AI != E; ++AI,++a)
897 if (!AI->use_empty()) {
898 if (BasicBlock *BBU = IsOnlyUsedInOneBasicBlock(AI)) {
899 FuncInfo.BlockLocalArguments.insert(std::make_pair(BBU,
900 std::make_pair(AI, a)));
902 SDL.setValue(AI, Args[a]);
904 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
905 UnorderedChains.push_back(Copy);
911 // See if there are any block-local arguments that need to be emitted in this
914 if (!FuncInfo.BlockLocalArguments.empty()) {
915 std::multimap<BasicBlock*, std::pair<Argument*, unsigned> >::iterator BLAI =
916 FuncInfo.BlockLocalArguments.lower_bound(BB);
917 if (BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB) {
918 // Lower the arguments into this block.
919 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
921 // Set up the value mapping for the local arguments.
922 for (; BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB;
924 SDL.setValue(BLAI->second.first, Args[BLAI->second.second]);
926 // Any dead arguments will just be ignored here.
932 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
933 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
934 FunctionLoweringInfo &FuncInfo) {
935 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
937 std::vector<SDOperand> UnorderedChains;
939 // Lower any arguments needed in this block.
940 LowerArguments(LLVMBB, SDL, UnorderedChains);
942 BB = FuncInfo.MBBMap[LLVMBB];
943 SDL.setCurrentBasicBlock(BB);
945 // Lower all of the non-terminator instructions.
946 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
950 // Ensure that all instructions which are used outside of their defining
951 // blocks are available as virtual registers.
952 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
953 if (!I->use_empty() && !isa<PHINode>(I)) {
954 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
955 if (VMI != FuncInfo.ValueMap.end())
956 UnorderedChains.push_back(
957 CopyValueToVirtualRegister(SDL, I, VMI->second));
960 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
961 // ensure constants are generated when needed. Remember the virtual registers
962 // that need to be added to the Machine PHI nodes as input. We cannot just
963 // directly add them, because expansion might result in multiple MBB's for one
964 // BB. As such, the start of the BB might correspond to a different MBB than
968 // Emit constants only once even if used by multiple PHI nodes.
969 std::map<Constant*, unsigned> ConstantsOut;
971 // Check successor nodes PHI nodes that expect a constant to be available from
973 TerminatorInst *TI = LLVMBB->getTerminator();
974 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
975 BasicBlock *SuccBB = TI->getSuccessor(succ);
976 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
979 // At this point we know that there is a 1-1 correspondence between LLVM PHI
980 // nodes and Machine PHI nodes, but the incoming operands have not been
982 for (BasicBlock::iterator I = SuccBB->begin();
983 (PN = dyn_cast<PHINode>(I)); ++I)
984 if (!PN->use_empty()) {
986 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
987 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
988 unsigned &RegOut = ConstantsOut[C];
990 RegOut = FuncInfo.CreateRegForValue(C);
991 UnorderedChains.push_back(
992 CopyValueToVirtualRegister(SDL, C, RegOut));
996 Reg = FuncInfo.ValueMap[PHIOp];
998 assert(isa<AllocaInst>(PHIOp) &&
999 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
1000 "Didn't codegen value into a register!??");
1001 Reg = FuncInfo.CreateRegForValue(PHIOp);
1002 UnorderedChains.push_back(
1003 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
1007 // Remember that this register needs to added to the machine PHI node as
1008 // the input for this MBB.
1009 unsigned NumElements =
1010 TLI.getNumElements(TLI.getValueType(PN->getType()));
1011 for (unsigned i = 0, e = NumElements; i != e; ++i)
1012 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
1015 ConstantsOut.clear();
1017 // Turn all of the unordered chains into one factored node.
1018 if (!UnorderedChains.empty()) {
1019 UnorderedChains.push_back(SDL.getRoot());
1020 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
1023 // Lower the terminator after the copies are emitted.
1024 SDL.visit(*LLVMBB->getTerminator());
1026 // Make sure the root of the DAG is up-to-date.
1027 DAG.setRoot(SDL.getRoot());
1030 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
1031 FunctionLoweringInfo &FuncInfo) {
1032 SelectionDAG DAG(TLI.getTargetMachine(), MF);
1034 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
1036 // First step, lower LLVM code to some DAG. This DAG may use operations and
1037 // types that are not supported by the target.
1038 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
1040 DEBUG(std::cerr << "Lowered selection DAG:\n");
1043 // Second step, hack on the DAG until it only uses operations and types that
1044 // the target supports.
1047 DEBUG(std::cerr << "Legalized selection DAG:\n");
1050 // Finally, instruction select all of the operations to machine code, adding
1051 // the code to the MachineBasicBlock.
1052 InstructionSelectBasicBlock(DAG);
1054 if (ViewDAGs) DAG.viewGraph();
1056 DEBUG(std::cerr << "Selected machine code:\n");
1059 // Finally, now that we know what the last MBB the LLVM BB expanded is, update
1060 // PHI nodes in successors.
1061 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
1062 MachineInstr *PHI = PHINodesToUpdate[i].first;
1063 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
1064 "This is not a machine PHI node that we are updating!");
1065 PHI->addRegOperand(PHINodesToUpdate[i].second);
1066 PHI->addMachineBasicBlockOperand(BB);