1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Constants.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/ParameterAttributes.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleDAG.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetData.h"
42 #include "llvm/Target/TargetFrameInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/Timer.h"
55 EnableValueProp("enable-value-prop", cl::Hidden);
57 EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
59 EnableFastISel("fast-isel", cl::Hidden,
60 cl::desc("Enable the experimental \"fast\" instruction selector"));
62 DisableFastISelAbort("fast-isel-no-abort", cl::Hidden,
63 cl::desc("Use the SelectionDAGISel when \"fast\" instruction "
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewISelDAGs("view-isel-dags", cl::Hidden,
83 cl::desc("Pop up a window to show isel dags as they are selected"));
85 ViewSchedDAGs("view-sched-dags", cl::Hidden,
86 cl::desc("Pop up a window to show sched dags as they are processed"));
88 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
89 cl::desc("Pop up a window to show SUnit dags after they are processed"));
91 static const bool ViewDAGCombine1 = false,
92 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
93 ViewDAGCombine2 = false,
94 ViewISelDAGs = false, ViewSchedDAGs = false,
95 ViewSUnitDAGs = false;
98 //===---------------------------------------------------------------------===//
100 /// RegisterScheduler class - Track the registration of instruction schedulers.
102 //===---------------------------------------------------------------------===//
103 MachinePassRegistry RegisterScheduler::Registry;
105 //===---------------------------------------------------------------------===//
107 /// ISHeuristic command line option for instruction schedulers.
109 //===---------------------------------------------------------------------===//
110 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
111 RegisterPassParser<RegisterScheduler> >
112 ISHeuristic("pre-RA-sched",
113 cl::init(&createDefaultScheduler),
114 cl::desc("Instruction schedulers available (before register"
117 static RegisterScheduler
118 defaultListDAGScheduler("default", " Best scheduler for the target",
119 createDefaultScheduler);
121 namespace { struct SDISelAsmOperandInfo; }
123 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
124 /// insertvalue or extractvalue indices that identify a member, return
125 /// the linearized index of the start of the member.
127 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
128 const unsigned *Indices,
129 const unsigned *IndicesEnd,
130 unsigned CurIndex = 0) {
131 // Base case: We're done.
132 if (Indices && Indices == IndicesEnd)
135 // Given a struct type, recursively traverse the elements.
136 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
137 for (StructType::element_iterator EB = STy->element_begin(),
139 EE = STy->element_end();
141 if (Indices && *Indices == unsigned(EI - EB))
142 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
143 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
146 // Given an array type, recursively traverse the elements.
147 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
148 const Type *EltTy = ATy->getElementType();
149 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
150 if (Indices && *Indices == i)
151 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
152 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
155 // We haven't found the type we're looking for, so keep searching.
159 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
160 /// MVTs that represent all the individual underlying
161 /// non-aggregate types that comprise it.
163 /// If Offsets is non-null, it points to a vector to be filled in
164 /// with the in-memory offsets of each of the individual values.
166 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
167 SmallVectorImpl<MVT> &ValueVTs,
168 SmallVectorImpl<uint64_t> *Offsets = 0,
169 uint64_t StartingOffset = 0) {
170 // Given a struct type, recursively traverse the elements.
171 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
172 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
173 for (StructType::element_iterator EB = STy->element_begin(),
175 EE = STy->element_end();
177 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
178 StartingOffset + SL->getElementOffset(EI - EB));
181 // Given an array type, recursively traverse the elements.
182 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
183 const Type *EltTy = ATy->getElementType();
184 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
185 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
186 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
187 StartingOffset + i * EltSize);
190 // Base case: we can get an MVT for this LLVM IR type.
191 ValueVTs.push_back(TLI.getValueType(Ty));
193 Offsets->push_back(StartingOffset);
197 /// RegsForValue - This struct represents the registers (physical or virtual)
198 /// that a particular set of values is assigned, and the type information about
199 /// the value. The most common situation is to represent one value at a time,
200 /// but struct or array values are handled element-wise as multiple values.
201 /// The splitting of aggregates is performed recursively, so that we never
202 /// have aggregate-typed registers. The values at this point do not necessarily
203 /// have legal types, so each value may require one or more registers of some
206 struct VISIBILITY_HIDDEN RegsForValue {
207 /// TLI - The TargetLowering object.
209 const TargetLowering *TLI;
211 /// ValueVTs - The value types of the values, which may not be legal, and
212 /// may need be promoted or synthesized from one or more registers.
214 SmallVector<MVT, 4> ValueVTs;
216 /// RegVTs - The value types of the registers. This is the same size as
217 /// ValueVTs and it records, for each value, what the type of the assigned
218 /// register or registers are. (Individual values are never synthesized
219 /// from more than one type of register.)
221 /// With virtual registers, the contents of RegVTs is redundant with TLI's
222 /// getRegisterType member function, however when with physical registers
223 /// it is necessary to have a separate record of the types.
225 SmallVector<MVT, 4> RegVTs;
227 /// Regs - This list holds the registers assigned to the values.
228 /// Each legal or promoted value requires one register, and each
229 /// expanded value requires multiple registers.
231 SmallVector<unsigned, 4> Regs;
233 RegsForValue() : TLI(0) {}
235 RegsForValue(const TargetLowering &tli,
236 const SmallVector<unsigned, 4> ®s,
237 MVT regvt, MVT valuevt)
238 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
239 RegsForValue(const TargetLowering &tli,
240 const SmallVector<unsigned, 4> ®s,
241 const SmallVector<MVT, 4> ®vts,
242 const SmallVector<MVT, 4> &valuevts)
243 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
244 RegsForValue(const TargetLowering &tli,
245 unsigned Reg, const Type *Ty) : TLI(&tli) {
246 ComputeValueVTs(tli, Ty, ValueVTs);
248 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
249 MVT ValueVT = ValueVTs[Value];
250 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
251 MVT RegisterVT = TLI->getRegisterType(ValueVT);
252 for (unsigned i = 0; i != NumRegs; ++i)
253 Regs.push_back(Reg + i);
254 RegVTs.push_back(RegisterVT);
259 /// append - Add the specified values to this one.
260 void append(const RegsForValue &RHS) {
262 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
263 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
264 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
268 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
269 /// this value and returns the result as a ValueVTs value. This uses
270 /// Chain/Flag as the input and updates them for the output Chain/Flag.
271 /// If the Flag pointer is NULL, no flag is used.
272 SDValue getCopyFromRegs(SelectionDAG &DAG,
273 SDValue &Chain, SDValue *Flag) const;
275 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
276 /// specified value into the registers specified by this object. This uses
277 /// Chain/Flag as the input and updates them for the output Chain/Flag.
278 /// If the Flag pointer is NULL, no flag is used.
279 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
280 SDValue &Chain, SDValue *Flag) const;
282 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
283 /// operand list. This adds the code marker and includes the number of
284 /// values added into it.
285 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
286 std::vector<SDValue> &Ops) const;
291 //===--------------------------------------------------------------------===//
292 /// createDefaultScheduler - This creates an instruction scheduler appropriate
294 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
296 MachineBasicBlock *BB,
298 TargetLowering &TLI = IS->getTargetLowering();
300 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
301 return createTDListDAGScheduler(IS, DAG, BB, Fast);
303 assert(TLI.getSchedulingPreference() ==
304 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
305 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
310 //===--------------------------------------------------------------------===//
311 /// FunctionLoweringInfo - This contains information that is global to a
312 /// function that is used when lowering a region of the function.
313 class FunctionLoweringInfo {
318 MachineRegisterInfo &RegInfo;
320 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
322 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
323 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
325 /// ValueMap - Since we emit code for the function a basic block at a time,
326 /// we must remember which virtual registers hold the values for
327 /// cross-basic-block values.
328 DenseMap<const Value*, unsigned> ValueMap;
330 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
331 /// the entry block. This allows the allocas to be efficiently referenced
332 /// anywhere in the function.
333 std::map<const AllocaInst*, int> StaticAllocaMap;
336 SmallSet<Instruction*, 8> CatchInfoLost;
337 SmallSet<Instruction*, 8> CatchInfoFound;
340 unsigned MakeReg(MVT VT) {
341 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
344 /// isExportedInst - Return true if the specified value is an instruction
345 /// exported from its block.
346 bool isExportedInst(const Value *V) {
347 return ValueMap.count(V);
350 unsigned CreateRegForValue(const Value *V);
352 unsigned InitializeRegForValue(const Value *V) {
353 unsigned &R = ValueMap[V];
354 assert(R == 0 && "Already initialized this value register!");
355 return R = CreateRegForValue(V);
359 unsigned NumSignBits;
360 APInt KnownOne, KnownZero;
361 LiveOutInfo() : NumSignBits(0) {}
364 /// LiveOutRegInfo - Information about live out vregs, indexed by their
365 /// register number offset by 'FirstVirtualRegister'.
366 std::vector<LiveOutInfo> LiveOutRegInfo;
370 /// isSelector - Return true if this instruction is a call to the
371 /// eh.selector intrinsic.
372 static bool isSelector(Instruction *I) {
373 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
374 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
375 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
379 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
380 /// PHI nodes or outside of the basic block that defines it, or used by a
381 /// switch or atomic instruction, which may expand to multiple basic blocks.
382 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
383 if (isa<PHINode>(I)) return true;
384 BasicBlock *BB = I->getParent();
385 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
386 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
387 // FIXME: Remove switchinst special case.
388 isa<SwitchInst>(*UI))
393 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
394 /// entry block, return true. This includes arguments used by switches, since
395 /// the switch may expand into multiple basic blocks.
396 static bool isOnlyUsedInEntryBlock(Argument *A) {
397 // With FastISel active, we may be splitting blocks, so force creation
398 // of virtual registers for all non-dead arguments.
400 return A->use_empty();
402 BasicBlock *Entry = A->getParent()->begin();
403 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
404 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
405 return false; // Use not in entry block.
409 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
410 Function &fn, MachineFunction &mf)
411 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
413 // Create a vreg for each argument register that is not dead and is used
414 // outside of the entry block for the function.
415 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
417 if (!isOnlyUsedInEntryBlock(AI))
418 InitializeRegForValue(AI);
420 // Initialize the mapping of values to registers. This is only set up for
421 // instruction values that are used outside of the block that defines
423 Function::iterator BB = Fn.begin(), EB = Fn.end();
424 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
425 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
426 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
427 const Type *Ty = AI->getAllocatedType();
428 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
430 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
433 TySize *= CUI->getZExtValue(); // Get total allocated size.
434 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
435 StaticAllocaMap[AI] =
436 MF.getFrameInfo()->CreateStackObject(TySize, Align);
439 for (; BB != EB; ++BB)
440 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
441 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
442 if (!isa<AllocaInst>(I) ||
443 !StaticAllocaMap.count(cast<AllocaInst>(I)))
444 InitializeRegForValue(I);
446 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
447 // also creates the initial PHI MachineInstrs, though none of the input
448 // operands are populated.
449 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
450 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
454 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
457 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
458 if (PN->use_empty()) continue;
460 unsigned PHIReg = ValueMap[PN];
461 assert(PHIReg && "PHI node does not have an assigned virtual register!");
463 SmallVector<MVT, 4> ValueVTs;
464 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
465 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
466 MVT VT = ValueVTs[vti];
467 unsigned NumRegisters = TLI.getNumRegisters(VT);
468 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
469 for (unsigned i = 0; i != NumRegisters; ++i)
470 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
471 PHIReg += NumRegisters;
477 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
478 /// the correctly promoted or expanded types. Assign these registers
479 /// consecutive vreg numbers and return the first assigned number.
481 /// In the case that the given value has struct or array type, this function
482 /// will assign registers for each member or element.
484 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
485 SmallVector<MVT, 4> ValueVTs;
486 ComputeValueVTs(TLI, V->getType(), ValueVTs);
488 unsigned FirstReg = 0;
489 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
490 MVT ValueVT = ValueVTs[Value];
491 MVT RegisterVT = TLI.getRegisterType(ValueVT);
493 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
494 for (unsigned i = 0; i != NumRegs; ++i) {
495 unsigned R = MakeReg(RegisterVT);
496 if (!FirstReg) FirstReg = R;
502 //===----------------------------------------------------------------------===//
503 /// SelectionDAGLowering - This is the common target-independent lowering
504 /// implementation that is parameterized by a TargetLowering object.
505 /// Also, targets can overload any lowering method.
508 class SelectionDAGLowering {
509 MachineBasicBlock *CurMBB;
511 DenseMap<const Value*, SDValue> NodeMap;
513 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
514 /// them up and then emit token factor nodes when possible. This allows us to
515 /// get simple disambiguation between loads without worrying about alias
517 SmallVector<SDValue, 8> PendingLoads;
519 /// PendingExports - CopyToReg nodes that copy values to virtual registers
520 /// for export to other blocks need to be emitted before any terminator
521 /// instruction, but they have no other ordering requirements. We bunch them
522 /// up and the emit a single tokenfactor for them just before terminator
524 std::vector<SDValue> PendingExports;
526 /// Case - A struct to record the Value for a switch case, and the
527 /// case's target basic block.
531 MachineBasicBlock* BB;
533 Case() : Low(0), High(0), BB(0) { }
534 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
535 Low(low), High(high), BB(bb) { }
536 uint64_t size() const {
537 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
538 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
539 return (rHigh - rLow + 1ULL);
545 MachineBasicBlock* BB;
548 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
549 Mask(mask), BB(bb), Bits(bits) { }
552 typedef std::vector<Case> CaseVector;
553 typedef std::vector<CaseBits> CaseBitsVector;
554 typedef CaseVector::iterator CaseItr;
555 typedef std::pair<CaseItr, CaseItr> CaseRange;
557 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
558 /// of conditional branches.
560 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
561 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
563 /// CaseBB - The MBB in which to emit the compare and branch
564 MachineBasicBlock *CaseBB;
565 /// LT, GE - If nonzero, we know the current case value must be less-than or
566 /// greater-than-or-equal-to these Constants.
569 /// Range - A pair of iterators representing the range of case values to be
570 /// processed at this point in the binary search tree.
574 typedef std::vector<CaseRec> CaseRecVector;
576 /// The comparison function for sorting the switch case values in the vector.
577 /// WARNING: Case ranges should be disjoint!
579 bool operator () (const Case& C1, const Case& C2) {
580 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
581 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
582 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
583 return CI1->getValue().slt(CI2->getValue());
588 bool operator () (const CaseBits& C1, const CaseBits& C2) {
589 return C1.Bits > C2.Bits;
593 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
596 // TLI - This is information that describes the available target features we
597 // need for lowering. This indicates when operations are unavailable,
598 // implemented with a libcall, etc.
601 const TargetData *TD;
604 /// SwitchCases - Vector of CaseBlock structures used to communicate
605 /// SwitchInst code generation information.
606 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
607 /// JTCases - Vector of JumpTable structures used to communicate
608 /// SwitchInst code generation information.
609 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
610 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
612 /// FuncInfo - Information about the function as a whole.
614 FunctionLoweringInfo &FuncInfo;
616 /// GFI - Garbage collection metadata for the function.
619 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
621 FunctionLoweringInfo &funcinfo,
623 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
624 FuncInfo(funcinfo), GFI(gfi) {
627 /// getRoot - Return the current virtual root of the Selection DAG,
628 /// flushing any PendingLoad items. This must be done before emitting
629 /// a store or any other node that may need to be ordered after any
630 /// prior load instructions.
633 if (PendingLoads.empty())
634 return DAG.getRoot();
636 if (PendingLoads.size() == 1) {
637 SDValue Root = PendingLoads[0];
639 PendingLoads.clear();
643 // Otherwise, we have to make a token factor node.
644 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
645 &PendingLoads[0], PendingLoads.size());
646 PendingLoads.clear();
651 /// getControlRoot - Similar to getRoot, but instead of flushing all the
652 /// PendingLoad items, flush all the PendingExports items. It is necessary
653 /// to do this before emitting a terminator instruction.
655 SDValue getControlRoot() {
656 SDValue Root = DAG.getRoot();
658 if (PendingExports.empty())
661 // Turn all of the CopyToReg chains into one factored node.
662 if (Root.getOpcode() != ISD::EntryToken) {
663 unsigned i = 0, e = PendingExports.size();
664 for (; i != e; ++i) {
665 assert(PendingExports[i].Val->getNumOperands() > 1);
666 if (PendingExports[i].Val->getOperand(0) == Root)
667 break; // Don't add the root if we already indirectly depend on it.
671 PendingExports.push_back(Root);
674 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
676 PendingExports.size());
677 PendingExports.clear();
682 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
684 void visit(Instruction &I) { visit(I.getOpcode(), I); }
686 void visit(unsigned Opcode, User &I) {
687 // Note: this doesn't use InstVisitor, because it has to work with
688 // ConstantExpr's in addition to instructions.
690 default: assert(0 && "Unknown instruction type encountered!");
692 // Build the switch statement using the Instruction.def file.
693 #define HANDLE_INST(NUM, OPCODE, CLASS) \
694 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
695 #include "llvm/Instruction.def"
699 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
701 SDValue getValue(const Value *V);
703 void setValue(const Value *V, SDValue NewN) {
704 SDValue &N = NodeMap[V];
705 assert(N.Val == 0 && "Already set a value for this node!");
709 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
710 std::set<unsigned> &OutputRegs,
711 std::set<unsigned> &InputRegs);
713 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
714 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
716 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
717 void ExportFromCurrentBlock(Value *V);
718 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
719 MachineBasicBlock *LandingPad = NULL);
721 // Terminator instructions.
722 void visitRet(ReturnInst &I);
723 void visitBr(BranchInst &I);
724 void visitSwitch(SwitchInst &I);
725 void visitUnreachable(UnreachableInst &I) { /* noop */ }
727 // Helpers for visitSwitch
728 bool handleSmallSwitchRange(CaseRec& CR,
729 CaseRecVector& WorkList,
731 MachineBasicBlock* Default);
732 bool handleJTSwitchCase(CaseRec& CR,
733 CaseRecVector& WorkList,
735 MachineBasicBlock* Default);
736 bool handleBTSplitSwitchCase(CaseRec& CR,
737 CaseRecVector& WorkList,
739 MachineBasicBlock* Default);
740 bool handleBitTestsSwitchCase(CaseRec& CR,
741 CaseRecVector& WorkList,
743 MachineBasicBlock* Default);
744 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
745 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
746 void visitBitTestCase(MachineBasicBlock* NextMBB,
748 SelectionDAGISel::BitTestCase &B);
749 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
750 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
751 SelectionDAGISel::JumpTableHeader &JTH);
753 // These all get lowered before this pass.
754 void visitInvoke(InvokeInst &I);
755 void visitUnwind(UnwindInst &I);
757 void visitBinary(User &I, unsigned OpCode);
758 void visitShift(User &I, unsigned Opcode);
759 void visitAdd(User &I) {
760 if (I.getType()->isFPOrFPVector())
761 visitBinary(I, ISD::FADD);
763 visitBinary(I, ISD::ADD);
765 void visitSub(User &I);
766 void visitMul(User &I) {
767 if (I.getType()->isFPOrFPVector())
768 visitBinary(I, ISD::FMUL);
770 visitBinary(I, ISD::MUL);
772 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
773 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
774 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
775 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
776 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
777 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
778 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
779 void visitOr (User &I) { visitBinary(I, ISD::OR); }
780 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
781 void visitShl (User &I) { visitShift(I, ISD::SHL); }
782 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
783 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
784 void visitICmp(User &I);
785 void visitFCmp(User &I);
786 void visitVICmp(User &I);
787 void visitVFCmp(User &I);
788 // Visit the conversion instructions
789 void visitTrunc(User &I);
790 void visitZExt(User &I);
791 void visitSExt(User &I);
792 void visitFPTrunc(User &I);
793 void visitFPExt(User &I);
794 void visitFPToUI(User &I);
795 void visitFPToSI(User &I);
796 void visitUIToFP(User &I);
797 void visitSIToFP(User &I);
798 void visitPtrToInt(User &I);
799 void visitIntToPtr(User &I);
800 void visitBitCast(User &I);
802 void visitExtractElement(User &I);
803 void visitInsertElement(User &I);
804 void visitShuffleVector(User &I);
806 void visitExtractValue(ExtractValueInst &I);
807 void visitInsertValue(InsertValueInst &I);
809 void visitGetElementPtr(User &I);
810 void visitSelect(User &I);
812 void visitMalloc(MallocInst &I);
813 void visitFree(FreeInst &I);
814 void visitAlloca(AllocaInst &I);
815 void visitLoad(LoadInst &I);
816 void visitStore(StoreInst &I);
817 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
818 void visitCall(CallInst &I);
819 void visitInlineAsm(CallSite CS);
820 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
821 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
823 void visitVAStart(CallInst &I);
824 void visitVAArg(VAArgInst &I);
825 void visitVAEnd(CallInst &I);
826 void visitVACopy(CallInst &I);
828 void visitUserOp1(Instruction &I) {
829 assert(0 && "UserOp1 should not exist at instruction selection time!");
832 void visitUserOp2(Instruction &I) {
833 assert(0 && "UserOp2 should not exist at instruction selection time!");
838 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
841 } // end namespace llvm
844 /// getCopyFromParts - Create a value that contains the specified legal parts
845 /// combined into the value they represent. If the parts combine to a type
846 /// larger then ValueVT then AssertOp can be used to specify whether the extra
847 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
848 /// (ISD::AssertSext).
849 static SDValue getCopyFromParts(SelectionDAG &DAG,
850 const SDValue *Parts,
854 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
855 assert(NumParts > 0 && "No parts to assemble!");
856 TargetLowering &TLI = DAG.getTargetLoweringInfo();
857 SDValue Val = Parts[0];
860 // Assemble the value from multiple parts.
861 if (!ValueVT.isVector()) {
862 unsigned PartBits = PartVT.getSizeInBits();
863 unsigned ValueBits = ValueVT.getSizeInBits();
865 // Assemble the power of 2 part.
866 unsigned RoundParts = NumParts & (NumParts - 1) ?
867 1 << Log2_32(NumParts) : NumParts;
868 unsigned RoundBits = PartBits * RoundParts;
869 MVT RoundVT = RoundBits == ValueBits ?
870 ValueVT : MVT::getIntegerVT(RoundBits);
873 if (RoundParts > 2) {
874 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
875 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
876 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
882 if (TLI.isBigEndian())
884 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
886 if (RoundParts < NumParts) {
887 // Assemble the trailing non-power-of-2 part.
888 unsigned OddParts = NumParts - RoundParts;
889 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
890 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
892 // Combine the round and odd parts.
894 if (TLI.isBigEndian())
896 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
897 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
898 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
899 DAG.getConstant(Lo.getValueType().getSizeInBits(),
900 TLI.getShiftAmountTy()));
901 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
902 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
905 // Handle a multi-element vector.
906 MVT IntermediateVT, RegisterVT;
907 unsigned NumIntermediates;
909 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
911 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
912 NumParts = NumRegs; // Silence a compiler warning.
913 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
914 assert(RegisterVT == Parts[0].getValueType() &&
915 "Part type doesn't match part!");
917 // Assemble the parts into intermediate operands.
918 SmallVector<SDValue, 8> Ops(NumIntermediates);
919 if (NumIntermediates == NumParts) {
920 // If the register was not expanded, truncate or copy the value,
922 for (unsigned i = 0; i != NumParts; ++i)
923 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
924 PartVT, IntermediateVT);
925 } else if (NumParts > 0) {
926 // If the intermediate type was expanded, build the intermediate operands
928 assert(NumParts % NumIntermediates == 0 &&
929 "Must expand into a divisible number of parts!");
930 unsigned Factor = NumParts / NumIntermediates;
931 for (unsigned i = 0; i != NumIntermediates; ++i)
932 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
933 PartVT, IntermediateVT);
936 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
938 Val = DAG.getNode(IntermediateVT.isVector() ?
939 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
940 ValueVT, &Ops[0], NumIntermediates);
944 // There is now one part, held in Val. Correct it to match ValueVT.
945 PartVT = Val.getValueType();
947 if (PartVT == ValueVT)
950 if (PartVT.isVector()) {
951 assert(ValueVT.isVector() && "Unknown vector conversion!");
952 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
955 if (ValueVT.isVector()) {
956 assert(ValueVT.getVectorElementType() == PartVT &&
957 ValueVT.getVectorNumElements() == 1 &&
958 "Only trivial scalar-to-vector conversions should get here!");
959 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
962 if (PartVT.isInteger() &&
963 ValueVT.isInteger()) {
964 if (ValueVT.bitsLT(PartVT)) {
965 // For a truncate, see if we have any information to
966 // indicate whether the truncated bits will always be
967 // zero or sign-extension.
968 if (AssertOp != ISD::DELETED_NODE)
969 Val = DAG.getNode(AssertOp, PartVT, Val,
970 DAG.getValueType(ValueVT));
971 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
973 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
977 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
978 if (ValueVT.bitsLT(Val.getValueType()))
979 // FP_ROUND's are always exact here.
980 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
981 DAG.getIntPtrConstant(1));
982 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
985 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
986 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
988 assert(0 && "Unknown mismatch!");
992 /// getCopyToParts - Create a series of nodes that contain the specified value
993 /// split into legal parts. If the parts contain more bits than Val, then, for
994 /// integers, ExtendKind can be used to specify how to generate the extra bits.
995 static void getCopyToParts(SelectionDAG &DAG,
1000 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
1001 TargetLowering &TLI = DAG.getTargetLoweringInfo();
1002 MVT PtrVT = TLI.getPointerTy();
1003 MVT ValueVT = Val.getValueType();
1004 unsigned PartBits = PartVT.getSizeInBits();
1005 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
1010 if (!ValueVT.isVector()) {
1011 if (PartVT == ValueVT) {
1012 assert(NumParts == 1 && "No-op copy with multiple parts!");
1017 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
1018 // If the parts cover more bits than the value has, promote the value.
1019 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
1020 assert(NumParts == 1 && "Do not know what to promote to!");
1021 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
1022 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
1023 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1024 Val = DAG.getNode(ExtendKind, ValueVT, Val);
1026 assert(0 && "Unknown mismatch!");
1028 } else if (PartBits == ValueVT.getSizeInBits()) {
1029 // Different types of the same size.
1030 assert(NumParts == 1 && PartVT != ValueVT);
1031 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1032 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
1033 // If the parts cover less bits than value has, truncate the value.
1034 if (PartVT.isInteger() && ValueVT.isInteger()) {
1035 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1036 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1038 assert(0 && "Unknown mismatch!");
1042 // The value may have changed - recompute ValueVT.
1043 ValueVT = Val.getValueType();
1044 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1045 "Failed to tile the value with PartVT!");
1047 if (NumParts == 1) {
1048 assert(PartVT == ValueVT && "Type conversion failed!");
1053 // Expand the value into multiple parts.
1054 if (NumParts & (NumParts - 1)) {
1055 // The number of parts is not a power of 2. Split off and copy the tail.
1056 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1057 "Do not know what to expand to!");
1058 unsigned RoundParts = 1 << Log2_32(NumParts);
1059 unsigned RoundBits = RoundParts * PartBits;
1060 unsigned OddParts = NumParts - RoundParts;
1061 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1062 DAG.getConstant(RoundBits,
1063 TLI.getShiftAmountTy()));
1064 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1065 if (TLI.isBigEndian())
1066 // The odd parts were reversed by getCopyToParts - unreverse them.
1067 std::reverse(Parts + RoundParts, Parts + NumParts);
1068 NumParts = RoundParts;
1069 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1070 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1073 // The number of parts is a power of 2. Repeatedly bisect the value using
1075 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1076 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1078 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1079 for (unsigned i = 0; i < NumParts; i += StepSize) {
1080 unsigned ThisBits = StepSize * PartBits / 2;
1081 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1082 SDValue &Part0 = Parts[i];
1083 SDValue &Part1 = Parts[i+StepSize/2];
1085 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1086 DAG.getConstant(1, PtrVT));
1087 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1088 DAG.getConstant(0, PtrVT));
1090 if (ThisBits == PartBits && ThisVT != PartVT) {
1091 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1092 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1097 if (TLI.isBigEndian())
1098 std::reverse(Parts, Parts + NumParts);
1104 if (NumParts == 1) {
1105 if (PartVT != ValueVT) {
1106 if (PartVT.isVector()) {
1107 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1109 assert(ValueVT.getVectorElementType() == PartVT &&
1110 ValueVT.getVectorNumElements() == 1 &&
1111 "Only trivial vector-to-scalar conversions should get here!");
1112 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1113 DAG.getConstant(0, PtrVT));
1121 // Handle a multi-element vector.
1122 MVT IntermediateVT, RegisterVT;
1123 unsigned NumIntermediates;
1125 DAG.getTargetLoweringInfo()
1126 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1128 unsigned NumElements = ValueVT.getVectorNumElements();
1130 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1131 NumParts = NumRegs; // Silence a compiler warning.
1132 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1134 // Split the vector into intermediate operands.
1135 SmallVector<SDValue, 8> Ops(NumIntermediates);
1136 for (unsigned i = 0; i != NumIntermediates; ++i)
1137 if (IntermediateVT.isVector())
1138 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1139 IntermediateVT, Val,
1140 DAG.getConstant(i * (NumElements / NumIntermediates),
1143 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1144 IntermediateVT, Val,
1145 DAG.getConstant(i, PtrVT));
1147 // Split the intermediate operands into legal parts.
1148 if (NumParts == NumIntermediates) {
1149 // If the register was not expanded, promote or copy the value,
1151 for (unsigned i = 0; i != NumParts; ++i)
1152 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1153 } else if (NumParts > 0) {
1154 // If the intermediate type was expanded, split each the value into
1156 assert(NumParts % NumIntermediates == 0 &&
1157 "Must expand into a divisible number of parts!");
1158 unsigned Factor = NumParts / NumIntermediates;
1159 for (unsigned i = 0; i != NumIntermediates; ++i)
1160 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1165 SDValue SelectionDAGLowering::getValue(const Value *V) {
1166 SDValue &N = NodeMap[V];
1167 if (N.Val) return N;
1169 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1170 MVT VT = TLI.getValueType(V->getType(), true);
1172 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1173 return N = DAG.getConstant(CI->getValue(), VT);
1175 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1176 return N = DAG.getGlobalAddress(GV, VT);
1178 if (isa<ConstantPointerNull>(C))
1179 return N = DAG.getConstant(0, TLI.getPointerTy());
1181 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1182 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1184 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1185 !V->getType()->isAggregateType())
1186 return N = DAG.getNode(ISD::UNDEF, VT);
1188 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1189 visit(CE->getOpcode(), *CE);
1190 SDValue N1 = NodeMap[V];
1191 assert(N1.Val && "visit didn't populate the ValueMap!");
1195 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1196 SmallVector<SDValue, 4> Constants;
1197 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1199 SDNode *Val = getValue(*OI).Val;
1200 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1201 Constants.push_back(SDValue(Val, i));
1203 return DAG.getMergeValues(&Constants[0], Constants.size());
1206 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
1207 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1208 "Unknown struct or array constant!");
1210 SmallVector<MVT, 4> ValueVTs;
1211 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1212 unsigned NumElts = ValueVTs.size();
1214 return SDValue(); // empty struct
1215 SmallVector<SDValue, 4> Constants(NumElts);
1216 for (unsigned i = 0; i != NumElts; ++i) {
1217 MVT EltVT = ValueVTs[i];
1218 if (isa<UndefValue>(C))
1219 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1220 else if (EltVT.isFloatingPoint())
1221 Constants[i] = DAG.getConstantFP(0, EltVT);
1223 Constants[i] = DAG.getConstant(0, EltVT);
1225 return DAG.getMergeValues(&Constants[0], NumElts);
1228 const VectorType *VecTy = cast<VectorType>(V->getType());
1229 unsigned NumElements = VecTy->getNumElements();
1231 // Now that we know the number and type of the elements, get that number of
1232 // elements into the Ops array based on what kind of constant it is.
1233 SmallVector<SDValue, 16> Ops;
1234 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1235 for (unsigned i = 0; i != NumElements; ++i)
1236 Ops.push_back(getValue(CP->getOperand(i)));
1238 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1239 "Unknown vector constant!");
1240 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1243 if (isa<UndefValue>(C))
1244 Op = DAG.getNode(ISD::UNDEF, EltVT);
1245 else if (EltVT.isFloatingPoint())
1246 Op = DAG.getConstantFP(0, EltVT);
1248 Op = DAG.getConstant(0, EltVT);
1249 Ops.assign(NumElements, Op);
1252 // Create a BUILD_VECTOR node.
1253 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1256 // If this is a static alloca, generate it as the frameindex instead of
1258 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1259 std::map<const AllocaInst*, int>::iterator SI =
1260 FuncInfo.StaticAllocaMap.find(AI);
1261 if (SI != FuncInfo.StaticAllocaMap.end())
1262 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1265 unsigned InReg = FuncInfo.ValueMap[V];
1266 assert(InReg && "Value not in map!");
1268 RegsForValue RFV(TLI, InReg, V->getType());
1269 SDValue Chain = DAG.getEntryNode();
1270 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1274 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1275 if (I.getNumOperands() == 0) {
1276 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1280 SmallVector<SDValue, 8> NewValues;
1281 NewValues.push_back(getControlRoot());
1282 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1283 SDValue RetOp = getValue(I.getOperand(i));
1285 SmallVector<MVT, 4> ValueVTs;
1286 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1287 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1288 MVT VT = ValueVTs[j];
1290 // FIXME: C calling convention requires the return type to be promoted to
1291 // at least 32-bit. But this is not necessary for non-C calling conventions.
1292 if (VT.isInteger()) {
1293 MVT MinVT = TLI.getRegisterType(MVT::i32);
1294 if (VT.bitsLT(MinVT))
1298 unsigned NumParts = TLI.getNumRegisters(VT);
1299 MVT PartVT = TLI.getRegisterType(VT);
1300 SmallVector<SDValue, 4> Parts(NumParts);
1301 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1303 const Function *F = I.getParent()->getParent();
1304 if (F->paramHasAttr(0, ParamAttr::SExt))
1305 ExtendKind = ISD::SIGN_EXTEND;
1306 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1307 ExtendKind = ISD::ZERO_EXTEND;
1309 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
1310 &Parts[0], NumParts, PartVT, ExtendKind);
1312 for (unsigned i = 0; i < NumParts; ++i) {
1313 NewValues.push_back(Parts[i]);
1314 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1318 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1319 &NewValues[0], NewValues.size()));
1322 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1323 /// the current basic block, add it to ValueMap now so that we'll get a
1325 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1326 // No need to export constants.
1327 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1329 // Already exported?
1330 if (FuncInfo.isExportedInst(V)) return;
1332 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1333 CopyValueToVirtualRegister(V, Reg);
1336 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1337 const BasicBlock *FromBB) {
1338 // The operands of the setcc have to be in this block. We don't know
1339 // how to export them from some other block.
1340 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1341 // Can export from current BB.
1342 if (VI->getParent() == FromBB)
1345 // Is already exported, noop.
1346 return FuncInfo.isExportedInst(V);
1349 // If this is an argument, we can export it if the BB is the entry block or
1350 // if it is already exported.
1351 if (isa<Argument>(V)) {
1352 if (FromBB == &FromBB->getParent()->getEntryBlock())
1355 // Otherwise, can only export this if it is already exported.
1356 return FuncInfo.isExportedInst(V);
1359 // Otherwise, constants can always be exported.
1363 static bool InBlock(const Value *V, const BasicBlock *BB) {
1364 if (const Instruction *I = dyn_cast<Instruction>(V))
1365 return I->getParent() == BB;
1369 /// FindMergedConditions - If Cond is an expression like
1370 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1371 MachineBasicBlock *TBB,
1372 MachineBasicBlock *FBB,
1373 MachineBasicBlock *CurBB,
1375 // If this node is not part of the or/and tree, emit it as a branch.
1376 Instruction *BOp = dyn_cast<Instruction>(Cond);
1378 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1379 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1380 BOp->getParent() != CurBB->getBasicBlock() ||
1381 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1382 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1383 const BasicBlock *BB = CurBB->getBasicBlock();
1385 // If the leaf of the tree is a comparison, merge the condition into
1387 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1388 // The operands of the cmp have to be in this block. We don't know
1389 // how to export them from some other block. If this is the first block
1390 // of the sequence, no exporting is needed.
1392 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1393 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1394 BOp = cast<Instruction>(Cond);
1395 ISD::CondCode Condition;
1396 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1397 switch (IC->getPredicate()) {
1398 default: assert(0 && "Unknown icmp predicate opcode!");
1399 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1400 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1401 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1402 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1403 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1404 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1405 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1406 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1407 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1408 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1410 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1411 ISD::CondCode FPC, FOC;
1412 switch (FC->getPredicate()) {
1413 default: assert(0 && "Unknown fcmp predicate opcode!");
1414 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1415 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1416 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1417 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1418 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1419 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1420 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1421 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1422 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1423 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1424 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1425 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1426 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1427 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1428 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1429 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1431 if (FiniteOnlyFPMath())
1436 Condition = ISD::SETEQ; // silence warning.
1437 assert(0 && "Unknown compare instruction");
1440 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1441 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1442 SwitchCases.push_back(CB);
1446 // Create a CaseBlock record representing this branch.
1447 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1448 NULL, TBB, FBB, CurBB);
1449 SwitchCases.push_back(CB);
1454 // Create TmpBB after CurBB.
1455 MachineFunction::iterator BBI = CurBB;
1456 MachineFunction &MF = DAG.getMachineFunction();
1457 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1458 CurBB->getParent()->insert(++BBI, TmpBB);
1460 if (Opc == Instruction::Or) {
1461 // Codegen X | Y as:
1469 // Emit the LHS condition.
1470 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1472 // Emit the RHS condition into TmpBB.
1473 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1475 assert(Opc == Instruction::And && "Unknown merge op!");
1476 // Codegen X & Y as:
1483 // This requires creation of TmpBB after CurBB.
1485 // Emit the LHS condition.
1486 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1488 // Emit the RHS condition into TmpBB.
1489 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1493 /// If the set of cases should be emitted as a series of branches, return true.
1494 /// If we should emit this as a bunch of and/or'd together conditions, return
1497 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1498 if (Cases.size() != 2) return true;
1500 // If this is two comparisons of the same values or'd or and'd together, they
1501 // will get folded into a single comparison, so don't emit two blocks.
1502 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1503 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1504 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1505 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1512 void SelectionDAGLowering::visitBr(BranchInst &I) {
1513 // Update machine-CFG edges.
1514 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1516 // Figure out which block is immediately after the current one.
1517 MachineBasicBlock *NextBlock = 0;
1518 MachineFunction::iterator BBI = CurMBB;
1519 if (++BBI != CurMBB->getParent()->end())
1522 if (I.isUnconditional()) {
1523 // Update machine-CFG edges.
1524 CurMBB->addSuccessor(Succ0MBB);
1526 // If this is not a fall-through branch, emit the branch.
1527 if (Succ0MBB != NextBlock)
1528 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1529 DAG.getBasicBlock(Succ0MBB)));
1533 // If this condition is one of the special cases we handle, do special stuff
1535 Value *CondVal = I.getCondition();
1536 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1538 // If this is a series of conditions that are or'd or and'd together, emit
1539 // this as a sequence of branches instead of setcc's with and/or operations.
1540 // For example, instead of something like:
1553 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1554 if (BOp->hasOneUse() &&
1555 (BOp->getOpcode() == Instruction::And ||
1556 BOp->getOpcode() == Instruction::Or)) {
1557 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1558 // If the compares in later blocks need to use values not currently
1559 // exported from this block, export them now. This block should always
1560 // be the first entry.
1561 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1563 // Allow some cases to be rejected.
1564 if (ShouldEmitAsBranches(SwitchCases)) {
1565 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1566 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1567 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1570 // Emit the branch for this block.
1571 visitSwitchCase(SwitchCases[0]);
1572 SwitchCases.erase(SwitchCases.begin());
1576 // Okay, we decided not to do this, remove any inserted MBB's and clear
1578 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1579 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1581 SwitchCases.clear();
1585 // Create a CaseBlock record representing this branch.
1586 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1587 NULL, Succ0MBB, Succ1MBB, CurMBB);
1588 // Use visitSwitchCase to actually insert the fast branch sequence for this
1590 visitSwitchCase(CB);
1593 /// visitSwitchCase - Emits the necessary code to represent a single node in
1594 /// the binary search tree resulting from lowering a switch instruction.
1595 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1597 SDValue CondLHS = getValue(CB.CmpLHS);
1599 // Build the setcc now.
1600 if (CB.CmpMHS == NULL) {
1601 // Fold "(X == true)" to X and "(X == false)" to !X to
1602 // handle common cases produced by branch lowering.
1603 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1605 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1606 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1607 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1609 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1611 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1613 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1614 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1616 SDValue CmpOp = getValue(CB.CmpMHS);
1617 MVT VT = CmpOp.getValueType();
1619 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1620 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1622 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1623 Cond = DAG.getSetCC(MVT::i1, SUB,
1624 DAG.getConstant(High-Low, VT), ISD::SETULE);
1628 // Update successor info
1629 CurMBB->addSuccessor(CB.TrueBB);
1630 CurMBB->addSuccessor(CB.FalseBB);
1632 // Set NextBlock to be the MBB immediately after the current one, if any.
1633 // This is used to avoid emitting unnecessary branches to the next block.
1634 MachineBasicBlock *NextBlock = 0;
1635 MachineFunction::iterator BBI = CurMBB;
1636 if (++BBI != CurMBB->getParent()->end())
1639 // If the lhs block is the next block, invert the condition so that we can
1640 // fall through to the lhs instead of the rhs block.
1641 if (CB.TrueBB == NextBlock) {
1642 std::swap(CB.TrueBB, CB.FalseBB);
1643 SDValue True = DAG.getConstant(1, Cond.getValueType());
1644 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1646 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1647 DAG.getBasicBlock(CB.TrueBB));
1649 // If the branch was constant folded, fix up the CFG.
1650 if (BrCond.getOpcode() == ISD::BR) {
1651 CurMBB->removeSuccessor(CB.FalseBB);
1652 DAG.setRoot(BrCond);
1654 // Otherwise, go ahead and insert the false branch.
1655 if (BrCond == getControlRoot())
1656 CurMBB->removeSuccessor(CB.TrueBB);
1658 if (CB.FalseBB == NextBlock)
1659 DAG.setRoot(BrCond);
1661 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1662 DAG.getBasicBlock(CB.FalseBB)));
1666 /// visitJumpTable - Emit JumpTable node in the current MBB
1667 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1668 // Emit the code for the jump table
1669 assert(JT.Reg != -1U && "Should lower JT Header first!");
1670 MVT PTy = TLI.getPointerTy();
1671 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1672 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1673 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1678 /// visitJumpTableHeader - This function emits necessary code to produce index
1679 /// in the JumpTable from switch case.
1680 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1681 SelectionDAGISel::JumpTableHeader &JTH) {
1682 // Subtract the lowest switch case value from the value being switched on
1683 // and conditional branch to default mbb if the result is greater than the
1684 // difference between smallest and largest cases.
1685 SDValue SwitchOp = getValue(JTH.SValue);
1686 MVT VT = SwitchOp.getValueType();
1687 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1688 DAG.getConstant(JTH.First, VT));
1690 // The SDNode we just created, which holds the value being switched on
1691 // minus the the smallest case value, needs to be copied to a virtual
1692 // register so it can be used as an index into the jump table in a
1693 // subsequent basic block. This value may be smaller or larger than the
1694 // target's pointer type, and therefore require extension or truncating.
1695 if (VT.bitsGT(TLI.getPointerTy()))
1696 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1698 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1700 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1701 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1702 JT.Reg = JumpTableReg;
1704 // Emit the range check for the jump table, and branch to the default
1705 // block for the switch statement if the value being switched on exceeds
1706 // the largest case in the switch.
1707 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1708 DAG.getConstant(JTH.Last-JTH.First,VT),
1711 // Set NextBlock to be the MBB immediately after the current one, if any.
1712 // This is used to avoid emitting unnecessary branches to the next block.
1713 MachineBasicBlock *NextBlock = 0;
1714 MachineFunction::iterator BBI = CurMBB;
1715 if (++BBI != CurMBB->getParent()->end())
1718 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1719 DAG.getBasicBlock(JT.Default));
1721 if (JT.MBB == NextBlock)
1722 DAG.setRoot(BrCond);
1724 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1725 DAG.getBasicBlock(JT.MBB)));
1730 /// visitBitTestHeader - This function emits necessary code to produce value
1731 /// suitable for "bit tests"
1732 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1733 // Subtract the minimum value
1734 SDValue SwitchOp = getValue(B.SValue);
1735 MVT VT = SwitchOp.getValueType();
1736 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1737 DAG.getConstant(B.First, VT));
1740 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1741 DAG.getConstant(B.Range, VT),
1745 if (VT.bitsGT(TLI.getShiftAmountTy()))
1746 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1748 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1750 // Make desired shift
1751 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1752 DAG.getConstant(1, TLI.getPointerTy()),
1755 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1756 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1759 // Set NextBlock to be the MBB immediately after the current one, if any.
1760 // This is used to avoid emitting unnecessary branches to the next block.
1761 MachineBasicBlock *NextBlock = 0;
1762 MachineFunction::iterator BBI = CurMBB;
1763 if (++BBI != CurMBB->getParent()->end())
1766 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1768 CurMBB->addSuccessor(B.Default);
1769 CurMBB->addSuccessor(MBB);
1771 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1772 DAG.getBasicBlock(B.Default));
1774 if (MBB == NextBlock)
1775 DAG.setRoot(BrRange);
1777 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1778 DAG.getBasicBlock(MBB)));
1783 /// visitBitTestCase - this function produces one "bit test"
1784 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1786 SelectionDAGISel::BitTestCase &B) {
1787 // Emit bit tests and jumps
1788 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1789 TLI.getPointerTy());
1791 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1792 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1793 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1794 DAG.getConstant(0, TLI.getPointerTy()),
1797 CurMBB->addSuccessor(B.TargetBB);
1798 CurMBB->addSuccessor(NextMBB);
1800 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1801 AndCmp, DAG.getBasicBlock(B.TargetBB));
1803 // Set NextBlock to be the MBB immediately after the current one, if any.
1804 // This is used to avoid emitting unnecessary branches to the next block.
1805 MachineBasicBlock *NextBlock = 0;
1806 MachineFunction::iterator BBI = CurMBB;
1807 if (++BBI != CurMBB->getParent()->end())
1810 if (NextMBB == NextBlock)
1813 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1814 DAG.getBasicBlock(NextMBB)));
1819 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1820 // Retrieve successors.
1821 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1822 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1824 if (isa<InlineAsm>(I.getCalledValue()))
1827 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1829 // If the value of the invoke is used outside of its defining block, make it
1830 // available as a virtual register.
1831 if (!I.use_empty()) {
1832 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1833 if (VMI != FuncInfo.ValueMap.end())
1834 CopyValueToVirtualRegister(&I, VMI->second);
1837 // Update successor info
1838 CurMBB->addSuccessor(Return);
1839 CurMBB->addSuccessor(LandingPad);
1841 // Drop into normal successor.
1842 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1843 DAG.getBasicBlock(Return)));
1846 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1849 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1850 /// small case ranges).
1851 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1852 CaseRecVector& WorkList,
1854 MachineBasicBlock* Default) {
1855 Case& BackCase = *(CR.Range.second-1);
1857 // Size is the number of Cases represented by this range.
1858 unsigned Size = CR.Range.second - CR.Range.first;
1862 // Get the MachineFunction which holds the current MBB. This is used when
1863 // inserting any additional MBBs necessary to represent the switch.
1864 MachineFunction *CurMF = CurMBB->getParent();
1866 // Figure out which block is immediately after the current one.
1867 MachineBasicBlock *NextBlock = 0;
1868 MachineFunction::iterator BBI = CR.CaseBB;
1870 if (++BBI != CurMBB->getParent()->end())
1873 // TODO: If any two of the cases has the same destination, and if one value
1874 // is the same as the other, but has one bit unset that the other has set,
1875 // use bit manipulation to do two compares at once. For example:
1876 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1878 // Rearrange the case blocks so that the last one falls through if possible.
1879 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1880 // The last case block won't fall through into 'NextBlock' if we emit the
1881 // branches in this order. See if rearranging a case value would help.
1882 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1883 if (I->BB == NextBlock) {
1884 std::swap(*I, BackCase);
1890 // Create a CaseBlock record representing a conditional branch to
1891 // the Case's target mbb if the value being switched on SV is equal
1893 MachineBasicBlock *CurBlock = CR.CaseBB;
1894 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1895 MachineBasicBlock *FallThrough;
1897 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1898 CurMF->insert(BBI, FallThrough);
1900 // If the last case doesn't match, go to the default block.
1901 FallThrough = Default;
1904 Value *RHS, *LHS, *MHS;
1906 if (I->High == I->Low) {
1907 // This is just small small case range :) containing exactly 1 case
1909 LHS = SV; RHS = I->High; MHS = NULL;
1912 LHS = I->Low; MHS = SV; RHS = I->High;
1914 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1915 I->BB, FallThrough, CurBlock);
1917 // If emitting the first comparison, just call visitSwitchCase to emit the
1918 // code into the current block. Otherwise, push the CaseBlock onto the
1919 // vector to be later processed by SDISel, and insert the node's MBB
1920 // before the next MBB.
1921 if (CurBlock == CurMBB)
1922 visitSwitchCase(CB);
1924 SwitchCases.push_back(CB);
1926 CurBlock = FallThrough;
1932 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1933 return !DisableJumpTables &&
1934 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1935 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1938 /// handleJTSwitchCase - Emit jumptable for current switch case range
1939 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1940 CaseRecVector& WorkList,
1942 MachineBasicBlock* Default) {
1943 Case& FrontCase = *CR.Range.first;
1944 Case& BackCase = *(CR.Range.second-1);
1946 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1947 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1950 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1954 if (!areJTsAllowed(TLI) || TSize <= 3)
1957 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1961 DOUT << "Lowering jump table\n"
1962 << "First entry: " << First << ". Last entry: " << Last << "\n"
1963 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1965 // Get the MachineFunction which holds the current MBB. This is used when
1966 // inserting any additional MBBs necessary to represent the switch.
1967 MachineFunction *CurMF = CurMBB->getParent();
1969 // Figure out which block is immediately after the current one.
1970 MachineBasicBlock *NextBlock = 0;
1971 MachineFunction::iterator BBI = CR.CaseBB;
1973 if (++BBI != CurMBB->getParent()->end())
1976 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1978 // Create a new basic block to hold the code for loading the address
1979 // of the jump table, and jumping to it. Update successor information;
1980 // we will either branch to the default case for the switch, or the jump
1982 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1983 CurMF->insert(BBI, JumpTableBB);
1984 CR.CaseBB->addSuccessor(Default);
1985 CR.CaseBB->addSuccessor(JumpTableBB);
1987 // Build a vector of destination BBs, corresponding to each target
1988 // of the jump table. If the value of the jump table slot corresponds to
1989 // a case statement, push the case's BB onto the vector, otherwise, push
1991 std::vector<MachineBasicBlock*> DestBBs;
1992 int64_t TEI = First;
1993 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1994 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1995 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1997 if ((Low <= TEI) && (TEI <= High)) {
1998 DestBBs.push_back(I->BB);
2002 DestBBs.push_back(Default);
2006 // Update successor info. Add one edge to each unique successor.
2007 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2008 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2009 E = DestBBs.end(); I != E; ++I) {
2010 if (!SuccsHandled[(*I)->getNumber()]) {
2011 SuccsHandled[(*I)->getNumber()] = true;
2012 JumpTableBB->addSuccessor(*I);
2016 // Create a jump table index for this jump table, or return an existing
2018 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
2020 // Set the jump table information so that we can codegen it as a second
2021 // MachineBasicBlock
2022 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
2023 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
2024 (CR.CaseBB == CurMBB));
2025 if (CR.CaseBB == CurMBB)
2026 visitJumpTableHeader(JT, JTH);
2028 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2033 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2035 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2036 CaseRecVector& WorkList,
2038 MachineBasicBlock* Default) {
2039 // Get the MachineFunction which holds the current MBB. This is used when
2040 // inserting any additional MBBs necessary to represent the switch.
2041 MachineFunction *CurMF = CurMBB->getParent();
2043 // Figure out which block is immediately after the current one.
2044 MachineBasicBlock *NextBlock = 0;
2045 MachineFunction::iterator BBI = CR.CaseBB;
2047 if (++BBI != CurMBB->getParent()->end())
2050 Case& FrontCase = *CR.Range.first;
2051 Case& BackCase = *(CR.Range.second-1);
2052 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2054 // Size is the number of Cases represented by this range.
2055 unsigned Size = CR.Range.second - CR.Range.first;
2057 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2058 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2060 CaseItr Pivot = CR.Range.first + Size/2;
2062 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2063 // (heuristically) allow us to emit JumpTable's later.
2065 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2069 uint64_t LSize = FrontCase.size();
2070 uint64_t RSize = TSize-LSize;
2071 DOUT << "Selecting best pivot: \n"
2072 << "First: " << First << ", Last: " << Last <<"\n"
2073 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2074 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2076 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2077 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2078 assert((RBegin-LEnd>=1) && "Invalid case distance");
2079 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2080 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2081 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2082 // Should always split in some non-trivial place
2084 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2085 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2086 << "Metric: " << Metric << "\n";
2087 if (FMetric < Metric) {
2090 DOUT << "Current metric set to: " << FMetric << "\n";
2096 if (areJTsAllowed(TLI)) {
2097 // If our case is dense we *really* should handle it earlier!
2098 assert((FMetric > 0) && "Should handle dense range earlier!");
2100 Pivot = CR.Range.first + Size/2;
2103 CaseRange LHSR(CR.Range.first, Pivot);
2104 CaseRange RHSR(Pivot, CR.Range.second);
2105 Constant *C = Pivot->Low;
2106 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2108 // We know that we branch to the LHS if the Value being switched on is
2109 // less than the Pivot value, C. We use this to optimize our binary
2110 // tree a bit, by recognizing that if SV is greater than or equal to the
2111 // LHS's Case Value, and that Case Value is exactly one less than the
2112 // Pivot's Value, then we can branch directly to the LHS's Target,
2113 // rather than creating a leaf node for it.
2114 if ((LHSR.second - LHSR.first) == 1 &&
2115 LHSR.first->High == CR.GE &&
2116 cast<ConstantInt>(C)->getSExtValue() ==
2117 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2118 TrueBB = LHSR.first->BB;
2120 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2121 CurMF->insert(BBI, TrueBB);
2122 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2125 // Similar to the optimization above, if the Value being switched on is
2126 // known to be less than the Constant CR.LT, and the current Case Value
2127 // is CR.LT - 1, then we can branch directly to the target block for
2128 // the current Case Value, rather than emitting a RHS leaf node for it.
2129 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2130 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2131 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2132 FalseBB = RHSR.first->BB;
2134 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2135 CurMF->insert(BBI, FalseBB);
2136 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2139 // Create a CaseBlock record representing a conditional branch to
2140 // the LHS node if the value being switched on SV is less than C.
2141 // Otherwise, branch to LHS.
2142 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2143 TrueBB, FalseBB, CR.CaseBB);
2145 if (CR.CaseBB == CurMBB)
2146 visitSwitchCase(CB);
2148 SwitchCases.push_back(CB);
2153 /// handleBitTestsSwitchCase - if current case range has few destination and
2154 /// range span less, than machine word bitwidth, encode case range into series
2155 /// of masks and emit bit tests with these masks.
2156 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2157 CaseRecVector& WorkList,
2159 MachineBasicBlock* Default){
2160 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2162 Case& FrontCase = *CR.Range.first;
2163 Case& BackCase = *(CR.Range.second-1);
2165 // Get the MachineFunction which holds the current MBB. This is used when
2166 // inserting any additional MBBs necessary to represent the switch.
2167 MachineFunction *CurMF = CurMBB->getParent();
2169 unsigned numCmps = 0;
2170 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2172 // Single case counts one, case range - two.
2173 if (I->Low == I->High)
2179 // Count unique destinations
2180 SmallSet<MachineBasicBlock*, 4> Dests;
2181 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2182 Dests.insert(I->BB);
2183 if (Dests.size() > 3)
2184 // Don't bother the code below, if there are too much unique destinations
2187 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2188 << "Total number of comparisons: " << numCmps << "\n";
2190 // Compute span of values.
2191 Constant* minValue = FrontCase.Low;
2192 Constant* maxValue = BackCase.High;
2193 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2194 cast<ConstantInt>(minValue)->getSExtValue();
2195 DOUT << "Compare range: " << range << "\n"
2196 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2197 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2199 if (range>=IntPtrBits ||
2200 (!(Dests.size() == 1 && numCmps >= 3) &&
2201 !(Dests.size() == 2 && numCmps >= 5) &&
2202 !(Dests.size() >= 3 && numCmps >= 6)))
2205 DOUT << "Emitting bit tests\n";
2206 int64_t lowBound = 0;
2208 // Optimize the case where all the case values fit in a
2209 // word without having to subtract minValue. In this case,
2210 // we can optimize away the subtraction.
2211 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2212 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2213 range = cast<ConstantInt>(maxValue)->getSExtValue();
2215 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2218 CaseBitsVector CasesBits;
2219 unsigned i, count = 0;
2221 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2222 MachineBasicBlock* Dest = I->BB;
2223 for (i = 0; i < count; ++i)
2224 if (Dest == CasesBits[i].BB)
2228 assert((count < 3) && "Too much destinations to test!");
2229 CasesBits.push_back(CaseBits(0, Dest, 0));
2233 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2234 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2236 for (uint64_t j = lo; j <= hi; j++) {
2237 CasesBits[i].Mask |= 1ULL << j;
2238 CasesBits[i].Bits++;
2242 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2244 SelectionDAGISel::BitTestInfo BTC;
2246 // Figure out which block is immediately after the current one.
2247 MachineFunction::iterator BBI = CR.CaseBB;
2250 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2253 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2254 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2255 << ", BB: " << CasesBits[i].BB << "\n";
2257 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2258 CurMF->insert(BBI, CaseBB);
2259 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2264 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2265 -1U, (CR.CaseBB == CurMBB),
2266 CR.CaseBB, Default, BTC);
2268 if (CR.CaseBB == CurMBB)
2269 visitBitTestHeader(BTB);
2271 BitTestCases.push_back(BTB);
2277 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2278 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2279 const SwitchInst& SI) {
2280 unsigned numCmps = 0;
2282 // Start with "simple" cases
2283 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2284 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2285 Cases.push_back(Case(SI.getSuccessorValue(i),
2286 SI.getSuccessorValue(i),
2289 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2291 // Merge case into clusters
2292 if (Cases.size()>=2)
2293 // Must recompute end() each iteration because it may be
2294 // invalidated by erase if we hold on to it
2295 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2296 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2297 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2298 MachineBasicBlock* nextBB = J->BB;
2299 MachineBasicBlock* currentBB = I->BB;
2301 // If the two neighboring cases go to the same destination, merge them
2302 // into a single case.
2303 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2311 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2312 if (I->Low != I->High)
2313 // A range counts double, since it requires two compares.
2320 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2321 // Figure out which block is immediately after the current one.
2322 MachineBasicBlock *NextBlock = 0;
2323 MachineFunction::iterator BBI = CurMBB;
2325 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2327 // If there is only the default destination, branch to it if it is not the
2328 // next basic block. Otherwise, just fall through.
2329 if (SI.getNumOperands() == 2) {
2330 // Update machine-CFG edges.
2332 // If this is not a fall-through branch, emit the branch.
2333 CurMBB->addSuccessor(Default);
2334 if (Default != NextBlock)
2335 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2336 DAG.getBasicBlock(Default)));
2341 // If there are any non-default case statements, create a vector of Cases
2342 // representing each one, and sort the vector so that we can efficiently
2343 // create a binary search tree from them.
2345 unsigned numCmps = Clusterify(Cases, SI);
2346 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2347 << ". Total compares: " << numCmps << "\n";
2349 // Get the Value to be switched on and default basic blocks, which will be
2350 // inserted into CaseBlock records, representing basic blocks in the binary
2352 Value *SV = SI.getOperand(0);
2354 // Push the initial CaseRec onto the worklist
2355 CaseRecVector WorkList;
2356 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2358 while (!WorkList.empty()) {
2359 // Grab a record representing a case range to process off the worklist
2360 CaseRec CR = WorkList.back();
2361 WorkList.pop_back();
2363 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2366 // If the range has few cases (two or less) emit a series of specific
2368 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2371 // If the switch has more than 5 blocks, and at least 40% dense, and the
2372 // target supports indirect branches, then emit a jump table rather than
2373 // lowering the switch to a binary tree of conditional branches.
2374 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2377 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2378 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2379 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2384 void SelectionDAGLowering::visitSub(User &I) {
2385 // -0.0 - X --> fneg
2386 const Type *Ty = I.getType();
2387 if (isa<VectorType>(Ty)) {
2388 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2389 const VectorType *DestTy = cast<VectorType>(I.getType());
2390 const Type *ElTy = DestTy->getElementType();
2391 if (ElTy->isFloatingPoint()) {
2392 unsigned VL = DestTy->getNumElements();
2393 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2394 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2396 SDValue Op2 = getValue(I.getOperand(1));
2397 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2403 if (Ty->isFloatingPoint()) {
2404 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2405 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2406 SDValue Op2 = getValue(I.getOperand(1));
2407 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2412 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2415 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2416 SDValue Op1 = getValue(I.getOperand(0));
2417 SDValue Op2 = getValue(I.getOperand(1));
2419 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2422 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2423 SDValue Op1 = getValue(I.getOperand(0));
2424 SDValue Op2 = getValue(I.getOperand(1));
2425 if (!isa<VectorType>(I.getType())) {
2426 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2427 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2428 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2429 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2432 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2435 void SelectionDAGLowering::visitICmp(User &I) {
2436 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2437 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2438 predicate = IC->getPredicate();
2439 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2440 predicate = ICmpInst::Predicate(IC->getPredicate());
2441 SDValue Op1 = getValue(I.getOperand(0));
2442 SDValue Op2 = getValue(I.getOperand(1));
2443 ISD::CondCode Opcode;
2444 switch (predicate) {
2445 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2446 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2447 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2448 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2449 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2450 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2451 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2452 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2453 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2454 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2456 assert(!"Invalid ICmp predicate value");
2457 Opcode = ISD::SETEQ;
2460 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2463 void SelectionDAGLowering::visitFCmp(User &I) {
2464 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2465 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2466 predicate = FC->getPredicate();
2467 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2468 predicate = FCmpInst::Predicate(FC->getPredicate());
2469 SDValue Op1 = getValue(I.getOperand(0));
2470 SDValue Op2 = getValue(I.getOperand(1));
2471 ISD::CondCode Condition, FOC, FPC;
2472 switch (predicate) {
2473 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2474 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2475 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2476 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2477 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2478 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2479 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2480 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2481 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2482 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2483 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2484 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2485 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2486 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2487 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2488 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2490 assert(!"Invalid FCmp predicate value");
2491 FOC = FPC = ISD::SETFALSE;
2494 if (FiniteOnlyFPMath())
2498 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2501 void SelectionDAGLowering::visitVICmp(User &I) {
2502 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2503 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2504 predicate = IC->getPredicate();
2505 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2506 predicate = ICmpInst::Predicate(IC->getPredicate());
2507 SDValue Op1 = getValue(I.getOperand(0));
2508 SDValue Op2 = getValue(I.getOperand(1));
2509 ISD::CondCode Opcode;
2510 switch (predicate) {
2511 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2512 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2513 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2514 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2515 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2516 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2517 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2518 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2519 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2520 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2522 assert(!"Invalid ICmp predicate value");
2523 Opcode = ISD::SETEQ;
2526 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2529 void SelectionDAGLowering::visitVFCmp(User &I) {
2530 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2531 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2532 predicate = FC->getPredicate();
2533 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2534 predicate = FCmpInst::Predicate(FC->getPredicate());
2535 SDValue Op1 = getValue(I.getOperand(0));
2536 SDValue Op2 = getValue(I.getOperand(1));
2537 ISD::CondCode Condition, FOC, FPC;
2538 switch (predicate) {
2539 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2540 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2541 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2542 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2543 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2544 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2545 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2546 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2547 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2548 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2549 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2550 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2551 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2552 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2553 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2554 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2556 assert(!"Invalid VFCmp predicate value");
2557 FOC = FPC = ISD::SETFALSE;
2560 if (FiniteOnlyFPMath())
2565 MVT DestVT = TLI.getValueType(I.getType());
2567 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2570 void SelectionDAGLowering::visitSelect(User &I) {
2571 SDValue Cond = getValue(I.getOperand(0));
2572 SDValue TrueVal = getValue(I.getOperand(1));
2573 SDValue FalseVal = getValue(I.getOperand(2));
2574 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2575 TrueVal, FalseVal));
2579 void SelectionDAGLowering::visitTrunc(User &I) {
2580 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2581 SDValue N = getValue(I.getOperand(0));
2582 MVT DestVT = TLI.getValueType(I.getType());
2583 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2586 void SelectionDAGLowering::visitZExt(User &I) {
2587 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2588 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2589 SDValue N = getValue(I.getOperand(0));
2590 MVT DestVT = TLI.getValueType(I.getType());
2591 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2594 void SelectionDAGLowering::visitSExt(User &I) {
2595 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2596 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2597 SDValue N = getValue(I.getOperand(0));
2598 MVT DestVT = TLI.getValueType(I.getType());
2599 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2602 void SelectionDAGLowering::visitFPTrunc(User &I) {
2603 // FPTrunc is never a no-op cast, no need to check
2604 SDValue N = getValue(I.getOperand(0));
2605 MVT DestVT = TLI.getValueType(I.getType());
2606 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2609 void SelectionDAGLowering::visitFPExt(User &I){
2610 // FPTrunc is never a no-op cast, no need to check
2611 SDValue N = getValue(I.getOperand(0));
2612 MVT DestVT = TLI.getValueType(I.getType());
2613 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2616 void SelectionDAGLowering::visitFPToUI(User &I) {
2617 // FPToUI is never a no-op cast, no need to check
2618 SDValue N = getValue(I.getOperand(0));
2619 MVT DestVT = TLI.getValueType(I.getType());
2620 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2623 void SelectionDAGLowering::visitFPToSI(User &I) {
2624 // FPToSI is never a no-op cast, no need to check
2625 SDValue N = getValue(I.getOperand(0));
2626 MVT DestVT = TLI.getValueType(I.getType());
2627 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2630 void SelectionDAGLowering::visitUIToFP(User &I) {
2631 // UIToFP is never a no-op cast, no need to check
2632 SDValue N = getValue(I.getOperand(0));
2633 MVT DestVT = TLI.getValueType(I.getType());
2634 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2637 void SelectionDAGLowering::visitSIToFP(User &I){
2638 // UIToFP is never a no-op cast, no need to check
2639 SDValue N = getValue(I.getOperand(0));
2640 MVT DestVT = TLI.getValueType(I.getType());
2641 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2644 void SelectionDAGLowering::visitPtrToInt(User &I) {
2645 // What to do depends on the size of the integer and the size of the pointer.
2646 // We can either truncate, zero extend, or no-op, accordingly.
2647 SDValue N = getValue(I.getOperand(0));
2648 MVT SrcVT = N.getValueType();
2649 MVT DestVT = TLI.getValueType(I.getType());
2651 if (DestVT.bitsLT(SrcVT))
2652 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2654 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2655 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2656 setValue(&I, Result);
2659 void SelectionDAGLowering::visitIntToPtr(User &I) {
2660 // What to do depends on the size of the integer and the size of the pointer.
2661 // We can either truncate, zero extend, or no-op, accordingly.
2662 SDValue N = getValue(I.getOperand(0));
2663 MVT SrcVT = N.getValueType();
2664 MVT DestVT = TLI.getValueType(I.getType());
2665 if (DestVT.bitsLT(SrcVT))
2666 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2668 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2669 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2672 void SelectionDAGLowering::visitBitCast(User &I) {
2673 SDValue N = getValue(I.getOperand(0));
2674 MVT DestVT = TLI.getValueType(I.getType());
2676 // BitCast assures us that source and destination are the same size so this
2677 // is either a BIT_CONVERT or a no-op.
2678 if (DestVT != N.getValueType())
2679 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2681 setValue(&I, N); // noop cast.
2684 void SelectionDAGLowering::visitInsertElement(User &I) {
2685 SDValue InVec = getValue(I.getOperand(0));
2686 SDValue InVal = getValue(I.getOperand(1));
2687 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2688 getValue(I.getOperand(2)));
2690 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2691 TLI.getValueType(I.getType()),
2692 InVec, InVal, InIdx));
2695 void SelectionDAGLowering::visitExtractElement(User &I) {
2696 SDValue InVec = getValue(I.getOperand(0));
2697 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2698 getValue(I.getOperand(1)));
2699 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2700 TLI.getValueType(I.getType()), InVec, InIdx));
2703 void SelectionDAGLowering::visitShuffleVector(User &I) {
2704 SDValue V1 = getValue(I.getOperand(0));
2705 SDValue V2 = getValue(I.getOperand(1));
2706 SDValue Mask = getValue(I.getOperand(2));
2708 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2709 TLI.getValueType(I.getType()),
2713 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2714 const Value *Op0 = I.getOperand(0);
2715 const Value *Op1 = I.getOperand(1);
2716 const Type *AggTy = I.getType();
2717 const Type *ValTy = Op1->getType();
2718 bool IntoUndef = isa<UndefValue>(Op0);
2719 bool FromUndef = isa<UndefValue>(Op1);
2721 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2722 I.idx_begin(), I.idx_end());
2724 SmallVector<MVT, 4> AggValueVTs;
2725 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2726 SmallVector<MVT, 4> ValValueVTs;
2727 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2729 unsigned NumAggValues = AggValueVTs.size();
2730 unsigned NumValValues = ValValueVTs.size();
2731 SmallVector<SDValue, 4> Values(NumAggValues);
2733 SDValue Agg = getValue(Op0);
2734 SDValue Val = getValue(Op1);
2736 // Copy the beginning value(s) from the original aggregate.
2737 for (; i != LinearIndex; ++i)
2738 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2739 SDValue(Agg.Val, Agg.ResNo + i);
2740 // Copy values from the inserted value(s).
2741 for (; i != LinearIndex + NumValValues; ++i)
2742 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2743 SDValue(Val.Val, Val.ResNo + i - LinearIndex);
2744 // Copy remaining value(s) from the original aggregate.
2745 for (; i != NumAggValues; ++i)
2746 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2747 SDValue(Agg.Val, Agg.ResNo + i);
2749 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2750 &Values[0], NumAggValues));
2753 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2754 const Value *Op0 = I.getOperand(0);
2755 const Type *AggTy = Op0->getType();
2756 const Type *ValTy = I.getType();
2757 bool OutOfUndef = isa<UndefValue>(Op0);
2759 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2760 I.idx_begin(), I.idx_end());
2762 SmallVector<MVT, 4> ValValueVTs;
2763 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2765 unsigned NumValValues = ValValueVTs.size();
2766 SmallVector<SDValue, 4> Values(NumValValues);
2768 SDValue Agg = getValue(Op0);
2769 // Copy out the selected value(s).
2770 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2771 Values[i - LinearIndex] =
2772 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2773 SDValue(Agg.Val, Agg.ResNo + i);
2775 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2776 &Values[0], NumValValues));
2780 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2781 SDValue N = getValue(I.getOperand(0));
2782 const Type *Ty = I.getOperand(0)->getType();
2784 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2787 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2788 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2791 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2792 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2793 DAG.getIntPtrConstant(Offset));
2795 Ty = StTy->getElementType(Field);
2797 Ty = cast<SequentialType>(Ty)->getElementType();
2799 // If this is a constant subscript, handle it quickly.
2800 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2801 if (CI->getZExtValue() == 0) continue;
2803 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2804 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2805 DAG.getIntPtrConstant(Offs));
2809 // N = N + Idx * ElementSize;
2810 uint64_t ElementSize = TD->getABITypeSize(Ty);
2811 SDValue IdxN = getValue(Idx);
2813 // If the index is smaller or larger than intptr_t, truncate or extend
2815 if (IdxN.getValueType().bitsLT(N.getValueType()))
2816 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2817 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2818 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2820 // If this is a multiply by a power of two, turn it into a shl
2821 // immediately. This is a very common case.
2822 if (ElementSize != 1) {
2823 if (isPowerOf2_64(ElementSize)) {
2824 unsigned Amt = Log2_64(ElementSize);
2825 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2826 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2828 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2829 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2833 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2839 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2840 // If this is a fixed sized alloca in the entry block of the function,
2841 // allocate it statically on the stack.
2842 if (FuncInfo.StaticAllocaMap.count(&I))
2843 return; // getValue will auto-populate this.
2845 const Type *Ty = I.getAllocatedType();
2846 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2848 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2851 SDValue AllocSize = getValue(I.getArraySize());
2852 MVT IntPtr = TLI.getPointerTy();
2853 if (IntPtr.bitsLT(AllocSize.getValueType()))
2854 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2855 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2856 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2858 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2859 DAG.getIntPtrConstant(TySize));
2861 // Handle alignment. If the requested alignment is less than or equal to
2862 // the stack alignment, ignore it. If the size is greater than or equal to
2863 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2864 unsigned StackAlign =
2865 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2866 if (Align <= StackAlign)
2869 // Round the size of the allocation up to the stack alignment size
2870 // by add SA-1 to the size.
2871 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2872 DAG.getIntPtrConstant(StackAlign-1));
2873 // Mask out the low bits for alignment purposes.
2874 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2875 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2877 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2878 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2880 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2882 DAG.setRoot(DSA.getValue(1));
2884 // Inform the Frame Information that we have just allocated a variable-sized
2886 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2889 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2890 const Value *SV = I.getOperand(0);
2891 SDValue Ptr = getValue(SV);
2893 const Type *Ty = I.getType();
2894 bool isVolatile = I.isVolatile();
2895 unsigned Alignment = I.getAlignment();
2897 SmallVector<MVT, 4> ValueVTs;
2898 SmallVector<uint64_t, 4> Offsets;
2899 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2900 unsigned NumValues = ValueVTs.size();
2905 bool ConstantMemory = false;
2907 // Serialize volatile loads with other side effects.
2909 else if (AA.pointsToConstantMemory(SV)) {
2910 // Do not serialize (non-volatile) loads of constant memory with anything.
2911 Root = DAG.getEntryNode();
2912 ConstantMemory = true;
2914 // Do not serialize non-volatile loads against each other.
2915 Root = DAG.getRoot();
2918 SmallVector<SDValue, 4> Values(NumValues);
2919 SmallVector<SDValue, 4> Chains(NumValues);
2920 MVT PtrVT = Ptr.getValueType();
2921 for (unsigned i = 0; i != NumValues; ++i) {
2922 SDValue L = DAG.getLoad(ValueVTs[i], Root,
2923 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2924 DAG.getConstant(Offsets[i], PtrVT)),
2926 isVolatile, Alignment);
2928 Chains[i] = L.getValue(1);
2931 if (!ConstantMemory) {
2932 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2933 &Chains[0], NumValues);
2937 PendingLoads.push_back(Chain);
2940 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2941 &Values[0], NumValues));
2945 void SelectionDAGLowering::visitStore(StoreInst &I) {
2946 Value *SrcV = I.getOperand(0);
2947 Value *PtrV = I.getOperand(1);
2949 SmallVector<MVT, 4> ValueVTs;
2950 SmallVector<uint64_t, 4> Offsets;
2951 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2952 unsigned NumValues = ValueVTs.size();
2956 // Get the lowered operands. Note that we do this after
2957 // checking if NumResults is zero, because with zero results
2958 // the operands won't have values in the map.
2959 SDValue Src = getValue(SrcV);
2960 SDValue Ptr = getValue(PtrV);
2962 SDValue Root = getRoot();
2963 SmallVector<SDValue, 4> Chains(NumValues);
2964 MVT PtrVT = Ptr.getValueType();
2965 bool isVolatile = I.isVolatile();
2966 unsigned Alignment = I.getAlignment();
2967 for (unsigned i = 0; i != NumValues; ++i)
2968 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
2969 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2970 DAG.getConstant(Offsets[i], PtrVT)),
2972 isVolatile, Alignment);
2974 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2977 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2979 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2980 unsigned Intrinsic) {
2981 bool HasChain = !I.doesNotAccessMemory();
2982 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2984 // Build the operand list.
2985 SmallVector<SDValue, 8> Ops;
2986 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2988 // We don't need to serialize loads against other loads.
2989 Ops.push_back(DAG.getRoot());
2991 Ops.push_back(getRoot());
2995 // Add the intrinsic ID as an integer operand.
2996 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2998 // Add all operands of the call to the operand list.
2999 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
3000 SDValue Op = getValue(I.getOperand(i));
3001 assert(TLI.isTypeLegal(Op.getValueType()) &&
3002 "Intrinsic uses a non-legal type?");
3006 std::vector<MVT> VTs;
3007 if (I.getType() != Type::VoidTy) {
3008 MVT VT = TLI.getValueType(I.getType());
3009 if (VT.isVector()) {
3010 const VectorType *DestTy = cast<VectorType>(I.getType());
3011 MVT EltVT = TLI.getValueType(DestTy->getElementType());
3013 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
3014 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
3017 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
3021 VTs.push_back(MVT::Other);
3023 const MVT *VTList = DAG.getNodeValueTypes(VTs);
3028 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
3029 &Ops[0], Ops.size());
3030 else if (I.getType() != Type::VoidTy)
3031 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
3032 &Ops[0], Ops.size());
3034 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
3035 &Ops[0], Ops.size());
3038 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
3040 PendingLoads.push_back(Chain);
3044 if (I.getType() != Type::VoidTy) {
3045 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3046 MVT VT = TLI.getValueType(PTy);
3047 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3049 setValue(&I, Result);
3053 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3054 static GlobalVariable *ExtractTypeInfo (Value *V) {
3055 V = V->stripPointerCasts();
3056 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3057 assert ((GV || isa<ConstantPointerNull>(V)) &&
3058 "TypeInfo must be a global variable or NULL");
3062 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3063 /// call, and add them to the specified machine basic block.
3064 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3065 MachineBasicBlock *MBB) {
3066 // Inform the MachineModuleInfo of the personality for this landing pad.
3067 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3068 assert(CE->getOpcode() == Instruction::BitCast &&
3069 isa<Function>(CE->getOperand(0)) &&
3070 "Personality should be a function");
3071 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3073 // Gather all the type infos for this landing pad and pass them along to
3074 // MachineModuleInfo.
3075 std::vector<GlobalVariable *> TyInfo;
3076 unsigned N = I.getNumOperands();
3078 for (unsigned i = N - 1; i > 2; --i) {
3079 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3080 unsigned FilterLength = CI->getZExtValue();
3081 unsigned FirstCatch = i + FilterLength + !FilterLength;
3082 assert (FirstCatch <= N && "Invalid filter length");
3084 if (FirstCatch < N) {
3085 TyInfo.reserve(N - FirstCatch);
3086 for (unsigned j = FirstCatch; j < N; ++j)
3087 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3088 MMI->addCatchTypeInfo(MBB, TyInfo);
3092 if (!FilterLength) {
3094 MMI->addCleanup(MBB);
3097 TyInfo.reserve(FilterLength - 1);
3098 for (unsigned j = i + 1; j < FirstCatch; ++j)
3099 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3100 MMI->addFilterTypeInfo(MBB, TyInfo);
3109 TyInfo.reserve(N - 3);
3110 for (unsigned j = 3; j < N; ++j)
3111 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3112 MMI->addCatchTypeInfo(MBB, TyInfo);
3117 /// Inlined utility function to implement binary input atomic intrinsics for
3118 // visitIntrinsicCall: I is a call instruction
3119 // Op is the associated NodeType for I
3121 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3122 SDValue Root = getRoot();
3123 SDValue L = DAG.getAtomic(Op, Root,
3124 getValue(I.getOperand(1)),
3125 getValue(I.getOperand(2)),
3128 DAG.setRoot(L.getValue(1));
3132 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3133 /// we want to emit this as a call to a named external function, return the name
3134 /// otherwise lower it and return null.
3136 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3137 switch (Intrinsic) {
3139 // By default, turn this into a target intrinsic node.
3140 visitTargetIntrinsic(I, Intrinsic);
3142 case Intrinsic::vastart: visitVAStart(I); return 0;
3143 case Intrinsic::vaend: visitVAEnd(I); return 0;
3144 case Intrinsic::vacopy: visitVACopy(I); return 0;
3145 case Intrinsic::returnaddress:
3146 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3147 getValue(I.getOperand(1))));
3149 case Intrinsic::frameaddress:
3150 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3151 getValue(I.getOperand(1))));
3153 case Intrinsic::setjmp:
3154 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3156 case Intrinsic::longjmp:
3157 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3159 case Intrinsic::memcpy_i32:
3160 case Intrinsic::memcpy_i64: {
3161 SDValue Op1 = getValue(I.getOperand(1));
3162 SDValue Op2 = getValue(I.getOperand(2));
3163 SDValue Op3 = getValue(I.getOperand(3));
3164 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3165 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3166 I.getOperand(1), 0, I.getOperand(2), 0));
3169 case Intrinsic::memset_i32:
3170 case Intrinsic::memset_i64: {
3171 SDValue Op1 = getValue(I.getOperand(1));
3172 SDValue Op2 = getValue(I.getOperand(2));
3173 SDValue Op3 = getValue(I.getOperand(3));
3174 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3175 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3176 I.getOperand(1), 0));
3179 case Intrinsic::memmove_i32:
3180 case Intrinsic::memmove_i64: {
3181 SDValue Op1 = getValue(I.getOperand(1));
3182 SDValue Op2 = getValue(I.getOperand(2));
3183 SDValue Op3 = getValue(I.getOperand(3));
3184 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3186 // If the source and destination are known to not be aliases, we can
3187 // lower memmove as memcpy.
3188 uint64_t Size = -1ULL;
3189 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3190 Size = C->getValue();
3191 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3192 AliasAnalysis::NoAlias) {
3193 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3194 I.getOperand(1), 0, I.getOperand(2), 0));
3198 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3199 I.getOperand(1), 0, I.getOperand(2), 0));
3202 case Intrinsic::dbg_stoppoint: {
3203 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3204 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3205 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3206 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3207 assert(DD && "Not a debug information descriptor");
3208 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3211 cast<CompileUnitDesc>(DD)));
3216 case Intrinsic::dbg_region_start: {
3217 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3218 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3219 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3220 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3221 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3226 case Intrinsic::dbg_region_end: {
3227 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3228 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3229 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3230 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3231 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3236 case Intrinsic::dbg_func_start: {
3237 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3239 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3240 Value *SP = FSI.getSubprogram();
3241 if (SP && MMI->Verify(SP)) {
3242 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3243 // what (most?) gdb expects.
3244 DebugInfoDesc *DD = MMI->getDescFor(SP);
3245 assert(DD && "Not a debug information descriptor");
3246 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3247 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3248 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3249 // Record the source line but does create a label. It will be emitted
3250 // at asm emission time.
3251 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3256 case Intrinsic::dbg_declare: {
3257 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3258 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3259 Value *Variable = DI.getVariable();
3260 if (MMI && Variable && MMI->Verify(Variable))
3261 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3262 getValue(DI.getAddress()), getValue(Variable)));
3266 case Intrinsic::eh_exception: {
3267 if (!CurMBB->isLandingPad()) {
3268 // FIXME: Mark exception register as live in. Hack for PR1508.
3269 unsigned Reg = TLI.getExceptionAddressRegister();
3270 if (Reg) CurMBB->addLiveIn(Reg);
3272 // Insert the EXCEPTIONADDR instruction.
3273 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3275 Ops[0] = DAG.getRoot();
3276 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3278 DAG.setRoot(Op.getValue(1));
3282 case Intrinsic::eh_selector_i32:
3283 case Intrinsic::eh_selector_i64: {
3284 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3285 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3286 MVT::i32 : MVT::i64);
3289 if (CurMBB->isLandingPad())
3290 addCatchInfo(I, MMI, CurMBB);
3293 FuncInfo.CatchInfoLost.insert(&I);
3295 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3296 unsigned Reg = TLI.getExceptionSelectorRegister();
3297 if (Reg) CurMBB->addLiveIn(Reg);
3300 // Insert the EHSELECTION instruction.
3301 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3303 Ops[0] = getValue(I.getOperand(1));
3305 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3307 DAG.setRoot(Op.getValue(1));
3309 setValue(&I, DAG.getConstant(0, VT));
3315 case Intrinsic::eh_typeid_for_i32:
3316 case Intrinsic::eh_typeid_for_i64: {
3317 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3318 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3319 MVT::i32 : MVT::i64);
3322 // Find the type id for the given typeinfo.
3323 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3325 unsigned TypeID = MMI->getTypeIDFor(GV);
3326 setValue(&I, DAG.getConstant(TypeID, VT));
3328 // Return something different to eh_selector.
3329 setValue(&I, DAG.getConstant(1, VT));
3335 case Intrinsic::eh_return: {
3336 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3339 MMI->setCallsEHReturn(true);
3340 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3343 getValue(I.getOperand(1)),
3344 getValue(I.getOperand(2))));
3346 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3352 case Intrinsic::eh_unwind_init: {
3353 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3354 MMI->setCallsUnwindInit(true);
3360 case Intrinsic::eh_dwarf_cfa: {
3361 MVT VT = getValue(I.getOperand(1)).getValueType();
3363 if (VT.bitsGT(TLI.getPointerTy()))
3364 CfaArg = DAG.getNode(ISD::TRUNCATE,
3365 TLI.getPointerTy(), getValue(I.getOperand(1)));
3367 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3368 TLI.getPointerTy(), getValue(I.getOperand(1)));
3370 SDValue Offset = DAG.getNode(ISD::ADD,
3372 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3373 TLI.getPointerTy()),
3375 setValue(&I, DAG.getNode(ISD::ADD,
3377 DAG.getNode(ISD::FRAMEADDR,
3380 TLI.getPointerTy())),
3385 case Intrinsic::sqrt:
3386 setValue(&I, DAG.getNode(ISD::FSQRT,
3387 getValue(I.getOperand(1)).getValueType(),
3388 getValue(I.getOperand(1))));
3390 case Intrinsic::powi:
3391 setValue(&I, DAG.getNode(ISD::FPOWI,
3392 getValue(I.getOperand(1)).getValueType(),
3393 getValue(I.getOperand(1)),
3394 getValue(I.getOperand(2))));
3396 case Intrinsic::sin:
3397 setValue(&I, DAG.getNode(ISD::FSIN,
3398 getValue(I.getOperand(1)).getValueType(),
3399 getValue(I.getOperand(1))));
3401 case Intrinsic::cos:
3402 setValue(&I, DAG.getNode(ISD::FCOS,
3403 getValue(I.getOperand(1)).getValueType(),
3404 getValue(I.getOperand(1))));
3406 case Intrinsic::pow:
3407 setValue(&I, DAG.getNode(ISD::FPOW,
3408 getValue(I.getOperand(1)).getValueType(),
3409 getValue(I.getOperand(1)),
3410 getValue(I.getOperand(2))));
3412 case Intrinsic::pcmarker: {
3413 SDValue Tmp = getValue(I.getOperand(1));
3414 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3417 case Intrinsic::readcyclecounter: {
3418 SDValue Op = getRoot();
3419 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3420 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3423 DAG.setRoot(Tmp.getValue(1));
3426 case Intrinsic::part_select: {
3427 // Currently not implemented: just abort
3428 assert(0 && "part_select intrinsic not implemented");
3431 case Intrinsic::part_set: {
3432 // Currently not implemented: just abort
3433 assert(0 && "part_set intrinsic not implemented");
3436 case Intrinsic::bswap:
3437 setValue(&I, DAG.getNode(ISD::BSWAP,
3438 getValue(I.getOperand(1)).getValueType(),
3439 getValue(I.getOperand(1))));
3441 case Intrinsic::cttz: {
3442 SDValue Arg = getValue(I.getOperand(1));
3443 MVT Ty = Arg.getValueType();
3444 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3445 setValue(&I, result);
3448 case Intrinsic::ctlz: {
3449 SDValue Arg = getValue(I.getOperand(1));
3450 MVT Ty = Arg.getValueType();
3451 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3452 setValue(&I, result);
3455 case Intrinsic::ctpop: {
3456 SDValue Arg = getValue(I.getOperand(1));
3457 MVT Ty = Arg.getValueType();
3458 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3459 setValue(&I, result);
3462 case Intrinsic::stacksave: {
3463 SDValue Op = getRoot();
3464 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
3465 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3467 DAG.setRoot(Tmp.getValue(1));
3470 case Intrinsic::stackrestore: {
3471 SDValue Tmp = getValue(I.getOperand(1));
3472 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3475 case Intrinsic::var_annotation:
3476 // Discard annotate attributes
3479 case Intrinsic::init_trampoline: {
3480 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3484 Ops[1] = getValue(I.getOperand(1));
3485 Ops[2] = getValue(I.getOperand(2));
3486 Ops[3] = getValue(I.getOperand(3));
3487 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3488 Ops[5] = DAG.getSrcValue(F);
3490 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
3491 DAG.getNodeValueTypes(TLI.getPointerTy(),
3496 DAG.setRoot(Tmp.getValue(1));
3500 case Intrinsic::gcroot:
3502 Value *Alloca = I.getOperand(1);
3503 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3505 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3506 GFI->addStackRoot(FI->getIndex(), TypeMap);
3510 case Intrinsic::gcread:
3511 case Intrinsic::gcwrite:
3512 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
3515 case Intrinsic::flt_rounds: {
3516 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3520 case Intrinsic::trap: {
3521 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3524 case Intrinsic::prefetch: {
3527 Ops[1] = getValue(I.getOperand(1));
3528 Ops[2] = getValue(I.getOperand(2));
3529 Ops[3] = getValue(I.getOperand(3));
3530 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3534 case Intrinsic::memory_barrier: {
3537 for (int x = 1; x < 6; ++x)
3538 Ops[x] = getValue(I.getOperand(x));
3540 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3543 case Intrinsic::atomic_cmp_swap: {
3544 SDValue Root = getRoot();
3545 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
3546 getValue(I.getOperand(1)),
3547 getValue(I.getOperand(2)),
3548 getValue(I.getOperand(3)),
3551 DAG.setRoot(L.getValue(1));
3554 case Intrinsic::atomic_load_add:
3555 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3556 case Intrinsic::atomic_load_sub:
3557 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
3558 case Intrinsic::atomic_load_and:
3559 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3560 case Intrinsic::atomic_load_or:
3561 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3562 case Intrinsic::atomic_load_xor:
3563 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3564 case Intrinsic::atomic_load_nand:
3565 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3566 case Intrinsic::atomic_load_min:
3567 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3568 case Intrinsic::atomic_load_max:
3569 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3570 case Intrinsic::atomic_load_umin:
3571 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3572 case Intrinsic::atomic_load_umax:
3573 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3574 case Intrinsic::atomic_swap:
3575 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3580 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
3582 MachineBasicBlock *LandingPad) {
3583 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3584 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3585 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3586 unsigned BeginLabel = 0, EndLabel = 0;
3588 TargetLowering::ArgListTy Args;
3589 TargetLowering::ArgListEntry Entry;
3590 Args.reserve(CS.arg_size());
3591 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3593 SDValue ArgNode = getValue(*i);
3594 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3596 unsigned attrInd = i - CS.arg_begin() + 1;
3597 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3598 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3599 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3600 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3601 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3602 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3603 Entry.Alignment = CS.getParamAlignment(attrInd);
3604 Args.push_back(Entry);
3607 if (LandingPad && MMI) {
3608 // Insert a label before the invoke call to mark the try range. This can be
3609 // used to detect deletion of the invoke via the MachineModuleInfo.
3610 BeginLabel = MMI->NextLabelID();
3611 // Both PendingLoads and PendingExports must be flushed here;
3612 // this call might not return.
3614 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
3617 std::pair<SDValue,SDValue> Result =
3618 TLI.LowerCallTo(getRoot(), CS.getType(),
3619 CS.paramHasAttr(0, ParamAttr::SExt),
3620 CS.paramHasAttr(0, ParamAttr::ZExt),
3621 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3623 if (CS.getType() != Type::VoidTy)
3624 setValue(CS.getInstruction(), Result.first);
3625 DAG.setRoot(Result.second);
3627 if (LandingPad && MMI) {
3628 // Insert a label at the end of the invoke call to mark the try range. This
3629 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3630 EndLabel = MMI->NextLabelID();
3631 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
3633 // Inform MachineModuleInfo of range.
3634 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3639 void SelectionDAGLowering::visitCall(CallInst &I) {
3640 const char *RenameFn = 0;
3641 if (Function *F = I.getCalledFunction()) {
3642 if (F->isDeclaration()) {
3643 if (unsigned IID = F->getIntrinsicID()) {
3644 RenameFn = visitIntrinsicCall(I, IID);
3650 // Check for well-known libc/libm calls. If the function is internal, it
3651 // can't be a library call.
3652 unsigned NameLen = F->getNameLen();
3653 if (!F->hasInternalLinkage() && NameLen) {
3654 const char *NameStr = F->getNameStart();
3655 if (NameStr[0] == 'c' &&
3656 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3657 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3658 if (I.getNumOperands() == 3 && // Basic sanity checks.
3659 I.getOperand(1)->getType()->isFloatingPoint() &&
3660 I.getType() == I.getOperand(1)->getType() &&
3661 I.getType() == I.getOperand(2)->getType()) {
3662 SDValue LHS = getValue(I.getOperand(1));
3663 SDValue RHS = getValue(I.getOperand(2));
3664 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3668 } else if (NameStr[0] == 'f' &&
3669 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3670 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3671 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3672 if (I.getNumOperands() == 2 && // Basic sanity checks.
3673 I.getOperand(1)->getType()->isFloatingPoint() &&
3674 I.getType() == I.getOperand(1)->getType()) {
3675 SDValue Tmp = getValue(I.getOperand(1));
3676 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3679 } else if (NameStr[0] == 's' &&
3680 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3681 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3682 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3683 if (I.getNumOperands() == 2 && // Basic sanity checks.
3684 I.getOperand(1)->getType()->isFloatingPoint() &&
3685 I.getType() == I.getOperand(1)->getType()) {
3686 SDValue Tmp = getValue(I.getOperand(1));
3687 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3690 } else if (NameStr[0] == 'c' &&
3691 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3692 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3693 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3694 if (I.getNumOperands() == 2 && // Basic sanity checks.
3695 I.getOperand(1)->getType()->isFloatingPoint() &&
3696 I.getType() == I.getOperand(1)->getType()) {
3697 SDValue Tmp = getValue(I.getOperand(1));
3698 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3703 } else if (isa<InlineAsm>(I.getOperand(0))) {
3710 Callee = getValue(I.getOperand(0));
3712 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3714 LowerCallTo(&I, Callee, I.isTailCall());
3718 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3719 /// this value and returns the result as a ValueVT value. This uses
3720 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3721 /// If the Flag pointer is NULL, no flag is used.
3722 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3724 SDValue *Flag) const {
3725 // Assemble the legal parts into the final values.
3726 SmallVector<SDValue, 4> Values(ValueVTs.size());
3727 SmallVector<SDValue, 8> Parts;
3728 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3729 // Copy the legal parts from the registers.
3730 MVT ValueVT = ValueVTs[Value];
3731 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3732 MVT RegisterVT = RegVTs[Value];
3734 Parts.resize(NumRegs);
3735 for (unsigned i = 0; i != NumRegs; ++i) {
3738 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3740 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3741 *Flag = P.getValue(2);
3743 Chain = P.getValue(1);
3745 // If the source register was virtual and if we know something about it,
3746 // add an assert node.
3747 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3748 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3749 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3750 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3751 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3752 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3754 unsigned RegSize = RegisterVT.getSizeInBits();
3755 unsigned NumSignBits = LOI.NumSignBits;
3756 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3758 // FIXME: We capture more information than the dag can represent. For
3759 // now, just use the tightest assertzext/assertsext possible.
3761 MVT FromVT(MVT::Other);
3762 if (NumSignBits == RegSize)
3763 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3764 else if (NumZeroBits >= RegSize-1)
3765 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3766 else if (NumSignBits > RegSize-8)
3767 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3768 else if (NumZeroBits >= RegSize-9)
3769 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3770 else if (NumSignBits > RegSize-16)
3771 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3772 else if (NumZeroBits >= RegSize-17)
3773 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3774 else if (NumSignBits > RegSize-32)
3775 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3776 else if (NumZeroBits >= RegSize-33)
3777 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3779 if (FromVT != MVT::Other) {
3780 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3781 RegisterVT, P, DAG.getValueType(FromVT));
3790 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3795 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3796 &Values[0], ValueVTs.size());
3799 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3800 /// specified value into the registers specified by this object. This uses
3801 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3802 /// If the Flag pointer is NULL, no flag is used.
3803 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
3804 SDValue &Chain, SDValue *Flag) const {
3805 // Get the list of the values's legal parts.
3806 unsigned NumRegs = Regs.size();
3807 SmallVector<SDValue, 8> Parts(NumRegs);
3808 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3809 MVT ValueVT = ValueVTs[Value];
3810 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3811 MVT RegisterVT = RegVTs[Value];
3813 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3814 &Parts[Part], NumParts, RegisterVT);
3818 // Copy the parts into the registers.
3819 SmallVector<SDValue, 8> Chains(NumRegs);
3820 for (unsigned i = 0; i != NumRegs; ++i) {
3823 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3825 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3826 *Flag = Part.getValue(1);
3828 Chains[i] = Part.getValue(0);
3831 if (NumRegs == 1 || Flag)
3832 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3833 // flagged to it. That is the CopyToReg nodes and the user are considered
3834 // a single scheduling unit. If we create a TokenFactor and return it as
3835 // chain, then the TokenFactor is both a predecessor (operand) of the
3836 // user as well as a successor (the TF operands are flagged to the user).
3837 // c1, f1 = CopyToReg
3838 // c2, f2 = CopyToReg
3839 // c3 = TokenFactor c1, c2
3842 Chain = Chains[NumRegs-1];
3844 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3847 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3848 /// operand list. This adds the code marker and includes the number of
3849 /// values added into it.
3850 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3851 std::vector<SDValue> &Ops) const {
3852 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3853 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3854 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3855 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3856 MVT RegisterVT = RegVTs[Value];
3857 for (unsigned i = 0; i != NumRegs; ++i)
3858 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3862 /// isAllocatableRegister - If the specified register is safe to allocate,
3863 /// i.e. it isn't a stack pointer or some other special register, return the
3864 /// register class for the register. Otherwise, return null.
3865 static const TargetRegisterClass *
3866 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3867 const TargetLowering &TLI,
3868 const TargetRegisterInfo *TRI) {
3869 MVT FoundVT = MVT::Other;
3870 const TargetRegisterClass *FoundRC = 0;
3871 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3872 E = TRI->regclass_end(); RCI != E; ++RCI) {
3873 MVT ThisVT = MVT::Other;
3875 const TargetRegisterClass *RC = *RCI;
3876 // If none of the the value types for this register class are valid, we
3877 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3878 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3880 if (TLI.isTypeLegal(*I)) {
3881 // If we have already found this register in a different register class,
3882 // choose the one with the largest VT specified. For example, on
3883 // PowerPC, we favor f64 register classes over f32.
3884 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3891 if (ThisVT == MVT::Other) continue;
3893 // NOTE: This isn't ideal. In particular, this might allocate the
3894 // frame pointer in functions that need it (due to them not being taken
3895 // out of allocation, because a variable sized allocation hasn't been seen
3896 // yet). This is a slight code pessimization, but should still work.
3897 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3898 E = RC->allocation_order_end(MF); I != E; ++I)
3900 // We found a matching register class. Keep looking at others in case
3901 // we find one with larger registers that this physreg is also in.
3912 /// AsmOperandInfo - This contains information for each constraint that we are
3914 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3915 /// CallOperand - If this is the result output operand or a clobber
3916 /// this is null, otherwise it is the incoming operand to the CallInst.
3917 /// This gets modified as the asm is processed.
3918 SDValue CallOperand;
3920 /// AssignedRegs - If this is a register or register class operand, this
3921 /// contains the set of register corresponding to the operand.
3922 RegsForValue AssignedRegs;
3924 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3925 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3928 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3929 /// busy in OutputRegs/InputRegs.
3930 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3931 std::set<unsigned> &OutputRegs,
3932 std::set<unsigned> &InputRegs,
3933 const TargetRegisterInfo &TRI) const {
3935 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3936 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3939 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3940 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3945 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3947 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3948 const TargetRegisterInfo &TRI) {
3949 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3951 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3952 for (; *Aliases; ++Aliases)
3953 Regs.insert(*Aliases);
3956 } // end anon namespace.
3959 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3960 /// specified operand. We prefer to assign virtual registers, to allow the
3961 /// register allocator handle the assignment process. However, if the asm uses
3962 /// features that we can't model on machineinstrs, we have SDISel do the
3963 /// allocation. This produces generally horrible, but correct, code.
3965 /// OpInfo describes the operand.
3966 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3967 /// or any explicitly clobbered registers.
3968 /// Input and OutputRegs are the set of already allocated physical registers.
3970 void SelectionDAGLowering::
3971 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3972 std::set<unsigned> &OutputRegs,
3973 std::set<unsigned> &InputRegs) {
3974 // Compute whether this value requires an input register, an output register,
3976 bool isOutReg = false;
3977 bool isInReg = false;
3978 switch (OpInfo.Type) {
3979 case InlineAsm::isOutput:
3982 // If this is an early-clobber output, or if there is an input
3983 // constraint that matches this, we need to reserve the input register
3984 // so no other inputs allocate to it.
3985 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3987 case InlineAsm::isInput:
3991 case InlineAsm::isClobber:
3998 MachineFunction &MF = DAG.getMachineFunction();
3999 SmallVector<unsigned, 4> Regs;
4001 // If this is a constraint for a single physreg, or a constraint for a
4002 // register class, find it.
4003 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4004 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4005 OpInfo.ConstraintVT);
4007 unsigned NumRegs = 1;
4008 if (OpInfo.ConstraintVT != MVT::Other)
4009 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4011 MVT ValueVT = OpInfo.ConstraintVT;
4014 // If this is a constraint for a specific physical register, like {r17},
4016 if (PhysReg.first) {
4017 if (OpInfo.ConstraintVT == MVT::Other)
4018 ValueVT = *PhysReg.second->vt_begin();
4020 // Get the actual register value type. This is important, because the user
4021 // may have asked for (e.g.) the AX register in i32 type. We need to
4022 // remember that AX is actually i16 to get the right extension.
4023 RegVT = *PhysReg.second->vt_begin();
4025 // This is a explicit reference to a physical register.
4026 Regs.push_back(PhysReg.first);
4028 // If this is an expanded reference, add the rest of the regs to Regs.
4030 TargetRegisterClass::iterator I = PhysReg.second->begin();
4031 for (; *I != PhysReg.first; ++I)
4032 assert(I != PhysReg.second->end() && "Didn't find reg!");
4034 // Already added the first reg.
4036 for (; NumRegs; --NumRegs, ++I) {
4037 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4041 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4042 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4043 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4047 // Otherwise, if this was a reference to an LLVM register class, create vregs
4048 // for this reference.
4049 std::vector<unsigned> RegClassRegs;
4050 const TargetRegisterClass *RC = PhysReg.second;
4052 // If this is an early clobber or tied register, our regalloc doesn't know
4053 // how to maintain the constraint. If it isn't, go ahead and create vreg
4054 // and let the regalloc do the right thing.
4055 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4056 // If there is some other early clobber and this is an input register,
4057 // then we are forced to pre-allocate the input reg so it doesn't
4058 // conflict with the earlyclobber.
4059 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4060 RegVT = *PhysReg.second->vt_begin();
4062 if (OpInfo.ConstraintVT == MVT::Other)
4065 // Create the appropriate number of virtual registers.
4066 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4067 for (; NumRegs; --NumRegs)
4068 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4070 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4074 // Otherwise, we can't allocate it. Let the code below figure out how to
4075 // maintain these constraints.
4076 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4079 // This is a reference to a register class that doesn't directly correspond
4080 // to an LLVM register class. Allocate NumRegs consecutive, available,
4081 // registers from the class.
4082 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4083 OpInfo.ConstraintVT);
4086 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4087 unsigned NumAllocated = 0;
4088 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4089 unsigned Reg = RegClassRegs[i];
4090 // See if this register is available.
4091 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4092 (isInReg && InputRegs.count(Reg))) { // Already used.
4093 // Make sure we find consecutive registers.
4098 // Check to see if this register is allocatable (i.e. don't give out the
4101 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4102 if (!RC) { // Couldn't allocate this register.
4103 // Reset NumAllocated to make sure we return consecutive registers.
4109 // Okay, this register is good, we can use it.
4112 // If we allocated enough consecutive registers, succeed.
4113 if (NumAllocated == NumRegs) {
4114 unsigned RegStart = (i-NumAllocated)+1;
4115 unsigned RegEnd = i+1;
4116 // Mark all of the allocated registers used.
4117 for (unsigned i = RegStart; i != RegEnd; ++i)
4118 Regs.push_back(RegClassRegs[i]);
4120 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4121 OpInfo.ConstraintVT);
4122 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4127 // Otherwise, we couldn't allocate enough registers for this.
4131 /// visitInlineAsm - Handle a call to an InlineAsm object.
4133 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4134 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4136 /// ConstraintOperands - Information about all of the constraints.
4137 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4139 SDValue Chain = getRoot();
4142 std::set<unsigned> OutputRegs, InputRegs;
4144 // Do a prepass over the constraints, canonicalizing them, and building up the
4145 // ConstraintOperands list.
4146 std::vector<InlineAsm::ConstraintInfo>
4147 ConstraintInfos = IA->ParseConstraints();
4149 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4150 // constraint. If so, we can't let the register allocator allocate any input
4151 // registers, because it will not know to avoid the earlyclobbered output reg.
4152 bool SawEarlyClobber = false;
4154 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4155 unsigned ResNo = 0; // ResNo - The result number of the next output.
4156 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4157 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4158 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4160 MVT OpVT = MVT::Other;
4162 // Compute the value type for each operand.
4163 switch (OpInfo.Type) {
4164 case InlineAsm::isOutput:
4165 // Indirect outputs just consume an argument.
4166 if (OpInfo.isIndirect) {
4167 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4170 // The return value of the call is this value. As such, there is no
4171 // corresponding argument.
4172 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4173 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4174 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4176 assert(ResNo == 0 && "Asm only has one result!");
4177 OpVT = TLI.getValueType(CS.getType());
4181 case InlineAsm::isInput:
4182 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4184 case InlineAsm::isClobber:
4189 // If this is an input or an indirect output, process the call argument.
4190 // BasicBlocks are labels, currently appearing only in asm's.
4191 if (OpInfo.CallOperandVal) {
4192 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4193 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4195 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4196 const Type *OpTy = OpInfo.CallOperandVal->getType();
4197 // If this is an indirect operand, the operand is a pointer to the
4199 if (OpInfo.isIndirect)
4200 OpTy = cast<PointerType>(OpTy)->getElementType();
4202 // If OpTy is not a single value, it may be a struct/union that we
4203 // can tile with integers.
4204 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4205 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4213 OpTy = IntegerType::get(BitSize);
4218 OpVT = TLI.getValueType(OpTy, true);
4222 OpInfo.ConstraintVT = OpVT;
4224 // Compute the constraint code and ConstraintType to use.
4225 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4227 // Keep track of whether we see an earlyclobber.
4228 SawEarlyClobber |= OpInfo.isEarlyClobber;
4230 // If we see a clobber of a register, it is an early clobber.
4231 if (!SawEarlyClobber &&
4232 OpInfo.Type == InlineAsm::isClobber &&
4233 OpInfo.ConstraintType == TargetLowering::C_Register) {
4234 // Note that we want to ignore things that we don't trick here, like
4235 // dirflag, fpsr, flags, etc.
4236 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4237 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4238 OpInfo.ConstraintVT);
4239 if (PhysReg.first || PhysReg.second) {
4240 // This is a register we know of.
4241 SawEarlyClobber = true;
4245 // If this is a memory input, and if the operand is not indirect, do what we
4246 // need to to provide an address for the memory input.
4247 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4248 !OpInfo.isIndirect) {
4249 assert(OpInfo.Type == InlineAsm::isInput &&
4250 "Can only indirectify direct input operands!");
4252 // Memory operands really want the address of the value. If we don't have
4253 // an indirect input, put it in the constpool if we can, otherwise spill
4254 // it to a stack slot.
4256 // If the operand is a float, integer, or vector constant, spill to a
4257 // constant pool entry to get its address.
4258 Value *OpVal = OpInfo.CallOperandVal;
4259 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4260 isa<ConstantVector>(OpVal)) {
4261 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4262 TLI.getPointerTy());
4264 // Otherwise, create a stack slot and emit a store to it before the
4266 const Type *Ty = OpVal->getType();
4267 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4268 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4269 MachineFunction &MF = DAG.getMachineFunction();
4270 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4271 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4272 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4273 OpInfo.CallOperand = StackSlot;
4276 // There is no longer a Value* corresponding to this operand.
4277 OpInfo.CallOperandVal = 0;
4278 // It is now an indirect operand.
4279 OpInfo.isIndirect = true;
4282 // If this constraint is for a specific register, allocate it before
4284 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4285 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4287 ConstraintInfos.clear();
4290 // Second pass - Loop over all of the operands, assigning virtual or physregs
4291 // to registerclass operands.
4292 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4293 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4295 // C_Register operands have already been allocated, Other/Memory don't need
4297 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4298 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4301 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4302 std::vector<SDValue> AsmNodeOperands;
4303 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
4304 AsmNodeOperands.push_back(
4305 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4308 // Loop over all of the inputs, copying the operand values into the
4309 // appropriate registers and processing the output regs.
4310 RegsForValue RetValRegs;
4312 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4313 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4315 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4316 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4318 switch (OpInfo.Type) {
4319 case InlineAsm::isOutput: {
4320 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4321 OpInfo.ConstraintType != TargetLowering::C_Register) {
4322 // Memory output, or 'other' output (e.g. 'X' constraint).
4323 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4325 // Add information to the INLINEASM node to know about this output.
4326 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4327 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4328 TLI.getPointerTy()));
4329 AsmNodeOperands.push_back(OpInfo.CallOperand);
4333 // Otherwise, this is a register or register class output.
4335 // Copy the output from the appropriate register. Find a register that
4337 if (OpInfo.AssignedRegs.Regs.empty()) {
4338 cerr << "Couldn't allocate output reg for constraint '"
4339 << OpInfo.ConstraintCode << "'!\n";
4343 // If this is an indirect operand, store through the pointer after the
4345 if (OpInfo.isIndirect) {
4346 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4347 OpInfo.CallOperandVal));
4349 // This is the result value of the call.
4350 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4351 // Concatenate this output onto the outputs list.
4352 RetValRegs.append(OpInfo.AssignedRegs);
4355 // Add information to the INLINEASM node to know that this register is
4357 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4361 case InlineAsm::isInput: {
4362 SDValue InOperandVal = OpInfo.CallOperand;
4364 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4365 // If this is required to match an output register we have already set,
4366 // just use its register.
4367 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4369 // Scan until we find the definition we already emitted of this operand.
4370 // When we find it, create a RegsForValue operand.
4371 unsigned CurOp = 2; // The first operand.
4372 for (; OperandNo; --OperandNo) {
4373 // Advance to the next operand.
4375 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4376 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4377 (NumOps & 7) == 4 /*MEM*/) &&
4378 "Skipped past definitions?");
4379 CurOp += (NumOps>>3)+1;
4383 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4384 if ((NumOps & 7) == 2 /*REGDEF*/) {
4385 // Add NumOps>>3 registers to MatchedRegs.
4386 RegsForValue MatchedRegs;
4387 MatchedRegs.TLI = &TLI;
4388 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4389 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4390 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4392 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4393 MatchedRegs.Regs.push_back(Reg);
4396 // Use the produced MatchedRegs object to
4397 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4398 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4401 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4402 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4403 // Add information to the INLINEASM node to know about this input.
4404 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4405 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4406 TLI.getPointerTy()));
4407 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4412 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4413 assert(!OpInfo.isIndirect &&
4414 "Don't know how to handle indirect other inputs yet!");
4416 std::vector<SDValue> Ops;
4417 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4420 cerr << "Invalid operand for inline asm constraint '"
4421 << OpInfo.ConstraintCode << "'!\n";
4425 // Add information to the INLINEASM node to know about this input.
4426 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4427 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4428 TLI.getPointerTy()));
4429 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4431 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4432 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4433 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4434 "Memory operands expect pointer values");
4436 // Add information to the INLINEASM node to know about this input.
4437 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4438 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4439 TLI.getPointerTy()));
4440 AsmNodeOperands.push_back(InOperandVal);
4444 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4445 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4446 "Unknown constraint type!");
4447 assert(!OpInfo.isIndirect &&
4448 "Don't know how to handle indirect register inputs yet!");
4450 // Copy the input into the appropriate registers.
4451 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4452 "Couldn't allocate input reg!");
4454 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4456 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4460 case InlineAsm::isClobber: {
4461 // Add the clobbered value to the operand list, so that the register
4462 // allocator is aware that the physreg got clobbered.
4463 if (!OpInfo.AssignedRegs.Regs.empty())
4464 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4471 // Finish up input operands.
4472 AsmNodeOperands[0] = Chain;
4473 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4475 Chain = DAG.getNode(ISD::INLINEASM,
4476 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4477 &AsmNodeOperands[0], AsmNodeOperands.size());
4478 Flag = Chain.getValue(1);
4480 // If this asm returns a register value, copy the result from that register
4481 // and set it as the value of the call.
4482 if (!RetValRegs.Regs.empty()) {
4483 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4485 // If any of the results of the inline asm is a vector, it may have the
4486 // wrong width/num elts. This can happen for register classes that can
4487 // contain multiple different value types. The preg or vreg allocated may
4488 // not have the same VT as was expected. Convert it to the right type with
4490 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4491 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4492 if (Val.Val->getValueType(i).isVector())
4493 Val = DAG.getNode(ISD::BIT_CONVERT,
4494 TLI.getValueType(ResSTy->getElementType(i)), Val);
4497 if (Val.getValueType().isVector())
4498 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4502 setValue(CS.getInstruction(), Val);
4505 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
4507 // Process indirect outputs, first output all of the flagged copies out of
4509 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4510 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4511 Value *Ptr = IndirectStoresToEmit[i].second;
4512 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4513 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4516 // Emit the non-flagged stores from the physregs.
4517 SmallVector<SDValue, 8> OutChains;
4518 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4519 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4520 getValue(StoresToEmit[i].second),
4521 StoresToEmit[i].second, 0));
4522 if (!OutChains.empty())
4523 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4524 &OutChains[0], OutChains.size());
4529 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4530 SDValue Src = getValue(I.getOperand(0));
4532 MVT IntPtr = TLI.getPointerTy();
4534 if (IntPtr.bitsLT(Src.getValueType()))
4535 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4536 else if (IntPtr.bitsGT(Src.getValueType()))
4537 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4539 // Scale the source by the type size.
4540 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4541 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4542 Src, DAG.getIntPtrConstant(ElementSize));
4544 TargetLowering::ArgListTy Args;
4545 TargetLowering::ArgListEntry Entry;
4547 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4548 Args.push_back(Entry);
4550 std::pair<SDValue,SDValue> Result =
4551 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4552 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4553 setValue(&I, Result.first); // Pointers always fit in registers
4554 DAG.setRoot(Result.second);
4557 void SelectionDAGLowering::visitFree(FreeInst &I) {
4558 TargetLowering::ArgListTy Args;
4559 TargetLowering::ArgListEntry Entry;
4560 Entry.Node = getValue(I.getOperand(0));
4561 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4562 Args.push_back(Entry);
4563 MVT IntPtr = TLI.getPointerTy();
4564 std::pair<SDValue,SDValue> Result =
4565 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4566 CallingConv::C, true,
4567 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4568 DAG.setRoot(Result.second);
4571 // EmitInstrWithCustomInserter - This method should be implemented by targets
4572 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4573 // instructions are special in various ways, which require special support to
4574 // insert. The specified MachineInstr is created but not inserted into any
4575 // basic blocks, and the scheduler passes ownership of it to this method.
4576 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4577 MachineBasicBlock *MBB) {
4578 cerr << "If a target marks an instruction with "
4579 << "'usesCustomDAGSchedInserter', it must implement "
4580 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4585 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4586 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4587 getValue(I.getOperand(1)),
4588 DAG.getSrcValue(I.getOperand(1))));
4591 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4592 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4593 getValue(I.getOperand(0)),
4594 DAG.getSrcValue(I.getOperand(0)));
4596 DAG.setRoot(V.getValue(1));
4599 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4600 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4601 getValue(I.getOperand(1)),
4602 DAG.getSrcValue(I.getOperand(1))));
4605 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4606 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4607 getValue(I.getOperand(1)),
4608 getValue(I.getOperand(2)),
4609 DAG.getSrcValue(I.getOperand(1)),
4610 DAG.getSrcValue(I.getOperand(2))));
4613 /// TargetLowering::LowerArguments - This is the default LowerArguments
4614 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4615 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4616 /// integrated into SDISel.
4617 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4618 SmallVectorImpl<SDValue> &ArgValues) {
4619 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4620 SmallVector<SDValue, 3+16> Ops;
4621 Ops.push_back(DAG.getRoot());
4622 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4623 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4625 // Add one result value for each formal argument.
4626 SmallVector<MVT, 16> RetVals;
4628 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4630 SmallVector<MVT, 4> ValueVTs;
4631 ComputeValueVTs(*this, I->getType(), ValueVTs);
4632 for (unsigned Value = 0, NumValues = ValueVTs.size();
4633 Value != NumValues; ++Value) {
4634 MVT VT = ValueVTs[Value];
4635 const Type *ArgTy = VT.getTypeForMVT();
4636 ISD::ArgFlagsTy Flags;
4637 unsigned OriginalAlignment =
4638 getTargetData()->getABITypeAlignment(ArgTy);
4640 if (F.paramHasAttr(j, ParamAttr::ZExt))
4642 if (F.paramHasAttr(j, ParamAttr::SExt))
4644 if (F.paramHasAttr(j, ParamAttr::InReg))
4646 if (F.paramHasAttr(j, ParamAttr::StructRet))
4648 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4650 const PointerType *Ty = cast<PointerType>(I->getType());
4651 const Type *ElementTy = Ty->getElementType();
4652 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4653 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4654 // For ByVal, alignment should be passed from FE. BE will guess if
4655 // this info is not there but there are cases it cannot get right.
4656 if (F.getParamAlignment(j))
4657 FrameAlign = F.getParamAlignment(j);
4658 Flags.setByValAlign(FrameAlign);
4659 Flags.setByValSize(FrameSize);
4661 if (F.paramHasAttr(j, ParamAttr::Nest))
4663 Flags.setOrigAlign(OriginalAlignment);
4665 MVT RegisterVT = getRegisterType(VT);
4666 unsigned NumRegs = getNumRegisters(VT);
4667 for (unsigned i = 0; i != NumRegs; ++i) {
4668 RetVals.push_back(RegisterVT);
4669 ISD::ArgFlagsTy MyFlags = Flags;
4670 if (NumRegs > 1 && i == 0)
4672 // if it isn't first piece, alignment must be 1
4674 MyFlags.setOrigAlign(1);
4675 Ops.push_back(DAG.getArgFlags(MyFlags));
4680 RetVals.push_back(MVT::Other);
4683 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4684 DAG.getVTList(&RetVals[0], RetVals.size()),
4685 &Ops[0], Ops.size()).Val;
4687 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4688 // allows exposing the loads that may be part of the argument access to the
4689 // first DAGCombiner pass.
4690 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
4692 // The number of results should match up, except that the lowered one may have
4693 // an extra flag result.
4694 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4695 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4696 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4697 && "Lowering produced unexpected number of results!");
4699 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
4700 if (Result != TmpRes.Val && Result->use_empty()) {
4701 HandleSDNode Dummy(DAG.getRoot());
4702 DAG.RemoveDeadNode(Result);
4705 Result = TmpRes.Val;
4707 unsigned NumArgRegs = Result->getNumValues() - 1;
4708 DAG.setRoot(SDValue(Result, NumArgRegs));
4710 // Set up the return result vector.
4713 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4715 SmallVector<MVT, 4> ValueVTs;
4716 ComputeValueVTs(*this, I->getType(), ValueVTs);
4717 for (unsigned Value = 0, NumValues = ValueVTs.size();
4718 Value != NumValues; ++Value) {
4719 MVT VT = ValueVTs[Value];
4720 MVT PartVT = getRegisterType(VT);
4722 unsigned NumParts = getNumRegisters(VT);
4723 SmallVector<SDValue, 4> Parts(NumParts);
4724 for (unsigned j = 0; j != NumParts; ++j)
4725 Parts[j] = SDValue(Result, i++);
4727 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4728 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4729 AssertOp = ISD::AssertSext;
4730 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4731 AssertOp = ISD::AssertZext;
4733 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4737 assert(i == NumArgRegs && "Argument register count mismatch!");
4741 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4742 /// implementation, which just inserts an ISD::CALL node, which is later custom
4743 /// lowered by the target to something concrete. FIXME: When all targets are
4744 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4745 std::pair<SDValue, SDValue>
4746 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
4747 bool RetSExt, bool RetZExt, bool isVarArg,
4748 unsigned CallingConv, bool isTailCall,
4750 ArgListTy &Args, SelectionDAG &DAG) {
4751 SmallVector<SDValue, 32> Ops;
4752 Ops.push_back(Chain); // Op#0 - Chain
4753 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4754 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4755 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4756 Ops.push_back(Callee);
4758 // Handle all of the outgoing arguments.
4759 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4760 SmallVector<MVT, 4> ValueVTs;
4761 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4762 for (unsigned Value = 0, NumValues = ValueVTs.size();
4763 Value != NumValues; ++Value) {
4764 MVT VT = ValueVTs[Value];
4765 const Type *ArgTy = VT.getTypeForMVT();
4766 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4767 ISD::ArgFlagsTy Flags;
4768 unsigned OriginalAlignment =
4769 getTargetData()->getABITypeAlignment(ArgTy);
4775 if (Args[i].isInReg)
4779 if (Args[i].isByVal) {
4781 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4782 const Type *ElementTy = Ty->getElementType();
4783 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4784 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4785 // For ByVal, alignment should come from FE. BE will guess if this
4786 // info is not there but there are cases it cannot get right.
4787 if (Args[i].Alignment)
4788 FrameAlign = Args[i].Alignment;
4789 Flags.setByValAlign(FrameAlign);
4790 Flags.setByValSize(FrameSize);
4794 Flags.setOrigAlign(OriginalAlignment);
4796 MVT PartVT = getRegisterType(VT);
4797 unsigned NumParts = getNumRegisters(VT);
4798 SmallVector<SDValue, 4> Parts(NumParts);
4799 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4802 ExtendKind = ISD::SIGN_EXTEND;
4803 else if (Args[i].isZExt)
4804 ExtendKind = ISD::ZERO_EXTEND;
4806 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4808 for (unsigned i = 0; i != NumParts; ++i) {
4809 // if it isn't first piece, alignment must be 1
4810 ISD::ArgFlagsTy MyFlags = Flags;
4811 if (NumParts > 1 && i == 0)
4814 MyFlags.setOrigAlign(1);
4816 Ops.push_back(Parts[i]);
4817 Ops.push_back(DAG.getArgFlags(MyFlags));
4822 // Figure out the result value types. We start by making a list of
4823 // the potentially illegal return value types.
4824 SmallVector<MVT, 4> LoweredRetTys;
4825 SmallVector<MVT, 4> RetTys;
4826 ComputeValueVTs(*this, RetTy, RetTys);
4828 // Then we translate that to a list of legal types.
4829 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4831 MVT RegisterVT = getRegisterType(VT);
4832 unsigned NumRegs = getNumRegisters(VT);
4833 for (unsigned i = 0; i != NumRegs; ++i)
4834 LoweredRetTys.push_back(RegisterVT);
4837 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4839 // Create the CALL node.
4840 SDValue Res = DAG.getNode(ISD::CALL,
4841 DAG.getVTList(&LoweredRetTys[0],
4842 LoweredRetTys.size()),
4843 &Ops[0], Ops.size());
4844 Chain = Res.getValue(LoweredRetTys.size() - 1);
4846 // Gather up the call result into a single value.
4847 if (RetTy != Type::VoidTy) {
4848 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4851 AssertOp = ISD::AssertSext;
4853 AssertOp = ISD::AssertZext;
4855 SmallVector<SDValue, 4> ReturnValues;
4857 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4859 MVT RegisterVT = getRegisterType(VT);
4860 unsigned NumRegs = getNumRegisters(VT);
4861 unsigned RegNoEnd = NumRegs + RegNo;
4862 SmallVector<SDValue, 4> Results;
4863 for (; RegNo != RegNoEnd; ++RegNo)
4864 Results.push_back(Res.getValue(RegNo));
4865 SDValue ReturnValue =
4866 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4868 ReturnValues.push_back(ReturnValue);
4870 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4871 &ReturnValues[0], ReturnValues.size());
4874 return std::make_pair(Res, Chain);
4877 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4878 assert(0 && "LowerOperation not implemented for this target!");
4884 //===----------------------------------------------------------------------===//
4885 // SelectionDAGISel code
4886 //===----------------------------------------------------------------------===//
4888 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4889 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4892 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4893 AU.addRequired<AliasAnalysis>();
4894 AU.addRequired<GCModuleInfo>();
4895 AU.setPreservesAll();
4898 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4899 // Get alias analysis for load/store combining.
4900 AA = &getAnalysis<AliasAnalysis>();
4902 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4903 if (MF.getFunction()->hasGC())
4904 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
4907 RegInfo = &MF.getRegInfo();
4908 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4910 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4912 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4913 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4914 // Mark landing pad.
4915 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4917 SelectAllBasicBlocks(Fn, MF, FuncInfo);
4919 // Add function live-ins to entry block live-in set.
4920 BasicBlock *EntryBB = &Fn.getEntryBlock();
4921 BB = FuncInfo.MBBMap[EntryBB];
4922 if (!RegInfo->livein_empty())
4923 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4924 E = RegInfo->livein_end(); I != E; ++I)
4925 BB->addLiveIn(I->first);
4928 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4929 "Not all catch info was assigned to a landing pad!");
4935 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4936 SDValue Op = getValue(V);
4937 assert((Op.getOpcode() != ISD::CopyFromReg ||
4938 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4939 "Copy from a reg to the same reg!");
4940 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4942 RegsForValue RFV(TLI, Reg, V->getType());
4943 SDValue Chain = DAG.getEntryNode();
4944 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4945 PendingExports.push_back(Chain);
4948 void SelectionDAGISel::
4949 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4950 // If this is the entry block, emit arguments.
4951 Function &F = *LLVMBB->getParent();
4952 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4953 SDValue OldRoot = SDL.DAG.getRoot();
4954 SmallVector<SDValue, 16> Args;
4955 TLI.LowerArguments(F, SDL.DAG, Args);
4958 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4960 SmallVector<MVT, 4> ValueVTs;
4961 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4962 unsigned NumValues = ValueVTs.size();
4963 if (!AI->use_empty()) {
4964 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
4965 // If this argument is live outside of the entry block, insert a copy from
4966 // whereever we got it to the vreg that other BB's will reference it as.
4967 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4968 if (VMI != FuncInfo.ValueMap.end()) {
4969 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4975 // Finally, if the target has anything special to do, allow it to do so.
4976 // FIXME: this should insert code into the DAG!
4977 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4980 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4981 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4982 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4983 if (isSelector(I)) {
4984 // Apply the catch info to DestBB.
4985 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4987 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4988 FLI.CatchInfoFound.insert(I);
4993 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4994 /// whether object offset >= 0.
4996 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
4997 if (!isa<FrameIndexSDNode>(Op)) return false;
4999 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
5000 int FrameIdx = FrameIdxNode->getIndex();
5001 return MFI->isFixedObjectIndex(FrameIdx) &&
5002 MFI->getObjectOffset(FrameIdx) >= 0;
5005 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
5006 /// possibly be overwritten when lowering the outgoing arguments in a tail
5007 /// call. Currently the implementation of this call is very conservative and
5008 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
5009 /// virtual registers would be overwritten by direct lowering.
5010 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
5011 MachineFrameInfo * MFI) {
5012 RegisterSDNode * OpReg = NULL;
5013 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
5014 (Op.getOpcode()== ISD::CopyFromReg &&
5015 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
5016 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
5017 (Op.getOpcode() == ISD::LOAD &&
5018 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
5019 (Op.getOpcode() == ISD::MERGE_VALUES &&
5020 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
5021 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
5027 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
5028 /// DAG and fixes their tailcall attribute operand.
5029 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
5030 TargetLowering& TLI) {
5031 SDNode * Ret = NULL;
5032 SDValue Terminator = DAG.getRoot();
5035 if (Terminator.getOpcode() == ISD::RET) {
5036 Ret = Terminator.Val;
5039 // Fix tail call attribute of CALL nodes.
5040 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5041 BI = DAG.allnodes_end(); BI != BE; ) {
5043 if (BI->getOpcode() == ISD::CALL) {
5044 SDValue OpRet(Ret, 0);
5045 SDValue OpCall(BI, 0);
5046 bool isMarkedTailCall =
5047 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5048 // If CALL node has tail call attribute set to true and the call is not
5049 // eligible (no RET or the target rejects) the attribute is fixed to
5050 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5051 // must correctly identify tail call optimizable calls.
5052 if (!isMarkedTailCall) continue;
5054 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5055 // Not eligible. Mark CALL node as non tail call.
5056 SmallVector<SDValue, 32> Ops;
5058 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5059 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5063 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5065 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5067 // Look for tail call clobbered arguments. Emit a series of
5068 // copyto/copyfrom virtual register nodes to protect them.
5069 SmallVector<SDValue, 32> Ops;
5070 SDValue Chain = OpCall.getOperand(0), InFlag;
5072 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5073 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5075 if (idx > 4 && (idx % 2)) {
5076 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5077 getArgFlags().isByVal();
5078 MachineFunction &MF = DAG.getMachineFunction();
5079 MachineFrameInfo *MFI = MF.getFrameInfo();
5081 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5082 MVT VT = Arg.getValueType();
5083 unsigned VReg = MF.getRegInfo().
5084 createVirtualRegister(TLI.getRegClassFor(VT));
5085 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5086 InFlag = Chain.getValue(1);
5087 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5088 Chain = Arg.getValue(1);
5089 InFlag = Arg.getValue(2);
5094 // Link in chain of CopyTo/CopyFromReg.
5096 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5102 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5103 /// ensure constants are generated when needed. Remember the virtual registers
5104 /// that need to be added to the Machine PHI nodes as input. We cannot just
5105 /// directly add them, because expansion might result in multiple MBB's for one
5106 /// BB. As such, the start of the BB might correspond to a different MBB than
5110 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB,
5111 FunctionLoweringInfo &FuncInfo,
5112 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5113 SelectionDAGLowering &SDL) {
5114 TerminatorInst *TI = LLVMBB->getTerminator();
5116 // Emit constants only once even if used by multiple PHI nodes.
5117 std::map<Constant*, unsigned> ConstantsOut;
5119 BitVector SuccsHandled;
5120 if (TI->getNumSuccessors())
5121 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5123 // Check successor nodes' PHI nodes that expect a constant to be available
5125 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5126 BasicBlock *SuccBB = TI->getSuccessor(succ);
5127 if (!isa<PHINode>(SuccBB->begin())) continue;
5128 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5130 // If this terminator has multiple identical successors (common for
5131 // switches), only handle each succ once.
5132 unsigned SuccMBBNo = SuccMBB->getNumber();
5133 if (SuccsHandled[SuccMBBNo]) continue;
5134 SuccsHandled[SuccMBBNo] = true;
5136 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5139 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5140 // nodes and Machine PHI nodes, but the incoming operands have not been
5142 for (BasicBlock::iterator I = SuccBB->begin();
5143 (PN = dyn_cast<PHINode>(I)); ++I) {
5144 // Ignore dead phi's.
5145 if (PN->use_empty()) continue;
5148 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5150 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5151 unsigned &RegOut = ConstantsOut[C];
5153 RegOut = FuncInfo.CreateRegForValue(C);
5154 SDL.CopyValueToVirtualRegister(C, RegOut);
5158 Reg = FuncInfo.ValueMap[PHIOp];
5160 assert(isa<AllocaInst>(PHIOp) &&
5161 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5162 "Didn't codegen value into a register!??");
5163 Reg = FuncInfo.CreateRegForValue(PHIOp);
5164 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5168 // Remember that this register needs to added to the machine PHI node as
5169 // the input for this MBB.
5170 SmallVector<MVT, 4> ValueVTs;
5171 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5172 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5173 MVT VT = ValueVTs[vti];
5174 unsigned NumRegisters = TLI.getNumRegisters(VT);
5175 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5176 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5177 Reg += NumRegisters;
5181 ConstantsOut.clear();
5183 // Lower the terminator after the copies are emitted.
5184 SDL.visit(*LLVMBB->getTerminator());
5186 // Copy over any CaseBlock records that may now exist due to SwitchInst
5187 // lowering, as well as any jump table information.
5188 SwitchCases.clear();
5189 SwitchCases = SDL.SwitchCases;
5191 JTCases = SDL.JTCases;
5192 BitTestCases.clear();
5193 BitTestCases = SDL.BitTestCases;
5196 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
5197 BasicBlock::iterator Begin,
5198 BasicBlock::iterator End,
5200 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5201 FunctionLoweringInfo &FuncInfo) {
5202 SelectionDAGLowering SDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
5204 // Lower any arguments needed in this block if this is the entry block.
5206 LowerArguments(LLVMBB, SDL);
5208 SDL.setCurrentBasicBlock(BB);
5210 MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo();
5212 if (MMI && BB->isLandingPad()) {
5213 // Add a label to mark the beginning of the landing pad. Deletion of the
5214 // landing pad can thus be detected via the MachineModuleInfo.
5215 unsigned LabelID = MMI->addLandingPad(BB);
5216 CurDAG->setRoot(CurDAG->getLabel(ISD::EH_LABEL,
5217 CurDAG->getEntryNode(), LabelID));
5219 // Mark exception register as live in.
5220 unsigned Reg = TLI.getExceptionAddressRegister();
5221 if (Reg) BB->addLiveIn(Reg);
5223 // Mark exception selector register as live in.
5224 Reg = TLI.getExceptionSelectorRegister();
5225 if (Reg) BB->addLiveIn(Reg);
5227 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5228 // function and list of typeids logically belong to the invoke (or, if you
5229 // like, the basic block containing the invoke), and need to be associated
5230 // with it in the dwarf exception handling tables. Currently however the
5231 // information is provided by an intrinsic (eh.selector) that can be moved
5232 // to unexpected places by the optimizers: if the unwind edge is critical,
5233 // then breaking it can result in the intrinsics being in the successor of
5234 // the landing pad, not the landing pad itself. This results in exceptions
5235 // not being caught because no typeids are associated with the invoke.
5236 // This may not be the only way things can go wrong, but it is the only way
5237 // we try to work around for the moment.
5238 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5240 if (Br && Br->isUnconditional()) { // Critical edge?
5241 BasicBlock::iterator I, E;
5242 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5247 // No catch info found - try to extract some from the successor.
5248 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5252 // Lower all of the non-terminator instructions.
5253 for (BasicBlock::iterator I = Begin; I != End; ++I)
5254 if (!isa<TerminatorInst>(I))
5257 // Ensure that all instructions which are used outside of their defining
5258 // blocks are available as virtual registers. Invoke is handled elsewhere.
5259 for (BasicBlock::iterator I = Begin; I != End; ++I)
5260 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5261 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5262 if (VMI != FuncInfo.ValueMap.end())
5263 SDL.CopyValueToVirtualRegister(I, VMI->second);
5266 // Handle PHI nodes in successor blocks.
5267 if (Begin != End && End == LLVMBB->end())
5268 HandlePHINodesInSuccessorBlocks(LLVMBB, FuncInfo, PHINodesToUpdate, SDL);
5270 // Make sure the root of the DAG is up-to-date.
5271 CurDAG->setRoot(SDL.getControlRoot());
5273 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5274 // with correct tailcall attribute so that the target can rely on the tailcall
5275 // attribute indicating whether the call is really eligible for tail call
5277 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
5279 // Final step, emit the lowered DAG as machine code.
5280 CodeGenAndEmitDAG();
5284 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
5285 SmallPtrSet<SDNode*, 128> VisitedNodes;
5286 SmallVector<SDNode*, 128> Worklist;
5288 Worklist.push_back(CurDAG->getRoot().Val);
5294 while (!Worklist.empty()) {
5295 SDNode *N = Worklist.back();
5296 Worklist.pop_back();
5298 // If we've already seen this node, ignore it.
5299 if (!VisitedNodes.insert(N))
5302 // Otherwise, add all chain operands to the worklist.
5303 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5304 if (N->getOperand(i).getValueType() == MVT::Other)
5305 Worklist.push_back(N->getOperand(i).Val);
5307 // If this is a CopyToReg with a vreg dest, process it.
5308 if (N->getOpcode() != ISD::CopyToReg)
5311 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5312 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5315 // Ignore non-scalar or non-integer values.
5316 SDValue Src = N->getOperand(2);
5317 MVT SrcVT = Src.getValueType();
5318 if (!SrcVT.isInteger() || SrcVT.isVector())
5321 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
5322 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5323 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5325 // Only install this information if it tells us something.
5326 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5327 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5328 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
5329 if (DestReg >= FLI.LiveOutRegInfo.size())
5330 FLI.LiveOutRegInfo.resize(DestReg+1);
5331 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5332 LOI.NumSignBits = NumSignBits;
5333 LOI.KnownOne = NumSignBits;
5334 LOI.KnownZero = NumSignBits;
5339 void SelectionDAGISel::CodeGenAndEmitDAG() {
5340 std::string GroupName;
5341 if (TimePassesIsEnabled)
5342 GroupName = "Instruction Selection and Scheduling";
5343 std::string BlockName;
5344 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
5345 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
5346 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' +
5347 BB->getBasicBlock()->getName();
5349 DOUT << "Initial selection DAG:\n";
5350 DEBUG(CurDAG->dump());
5352 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
5354 // Run the DAG combiner in pre-legalize mode.
5355 if (TimePassesIsEnabled) {
5356 NamedRegionTimer T("DAG Combining 1", GroupName);
5357 CurDAG->Combine(false, *AA, Fast);
5359 CurDAG->Combine(false, *AA, Fast);
5362 DOUT << "Optimized lowered selection DAG:\n";
5363 DEBUG(CurDAG->dump());
5365 // Second step, hack on the DAG until it only uses operations and types that
5366 // the target supports.
5367 if (EnableLegalizeTypes) {// Enable this some day.
5368 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
5371 if (TimePassesIsEnabled) {
5372 NamedRegionTimer T("Type Legalization", GroupName);
5373 CurDAG->LegalizeTypes();
5375 CurDAG->LegalizeTypes();
5378 DOUT << "Type-legalized selection DAG:\n";
5379 DEBUG(CurDAG->dump());
5381 // TODO: enable a dag combine pass here.
5384 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
5386 if (TimePassesIsEnabled) {
5387 NamedRegionTimer T("DAG Legalization", GroupName);
5393 DOUT << "Legalized selection DAG:\n";
5394 DEBUG(CurDAG->dump());
5396 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
5398 // Run the DAG combiner in post-legalize mode.
5399 if (TimePassesIsEnabled) {
5400 NamedRegionTimer T("DAG Combining 2", GroupName);
5401 CurDAG->Combine(true, *AA, Fast);
5403 CurDAG->Combine(true, *AA, Fast);
5406 DOUT << "Optimized legalized selection DAG:\n";
5407 DEBUG(CurDAG->dump());
5409 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
5411 if (!Fast && EnableValueProp)
5412 ComputeLiveOutVRegInfo();
5414 // Third, instruction select all of the operations to machine code, adding the
5415 // code to the MachineBasicBlock.
5416 if (TimePassesIsEnabled) {
5417 NamedRegionTimer T("Instruction Selection", GroupName);
5418 InstructionSelect();
5420 InstructionSelect();
5423 DOUT << "Selected selection DAG:\n";
5424 DEBUG(CurDAG->dump());
5426 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
5428 // Schedule machine code.
5429 ScheduleDAG *Scheduler;
5430 if (TimePassesIsEnabled) {
5431 NamedRegionTimer T("Instruction Scheduling", GroupName);
5432 Scheduler = Schedule();
5434 Scheduler = Schedule();
5437 if (ViewSUnitDAGs) Scheduler->viewGraph();
5439 // Emit machine code to BB. This can change 'BB' to the last block being
5441 if (TimePassesIsEnabled) {
5442 NamedRegionTimer T("Instruction Creation", GroupName);
5443 BB = Scheduler->EmitSchedule();
5445 BB = Scheduler->EmitSchedule();
5448 // Free the scheduler state.
5449 if (TimePassesIsEnabled) {
5450 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
5456 DOUT << "Selected machine code:\n";
5460 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
5461 FunctionLoweringInfo &FuncInfo) {
5462 // Define the SelectionDAG here so that memory allocation is reused for
5463 // each basic block.
5464 SelectionDAG DAG(TLI, MF, FuncInfo,
5465 getAnalysisToUpdate<MachineModuleInfo>());
5468 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5469 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
5470 BasicBlock *LLVMBB = &*I;
5471 BB = FuncInfo.MBBMap[LLVMBB];
5473 BasicBlock::iterator Begin = LLVMBB->begin();
5474 BasicBlock::iterator End = LLVMBB->end();
5475 bool DoArgs = LLVMBB == &Fn.getEntryBlock();
5477 // Before doing SelectionDAG ISel, see if FastISel has been requested.
5478 // FastISel doesn't support EH landing pads, which require special handling.
5479 if (EnableFastISel && !BB->isLandingPad()) {
5480 if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
5481 while (Begin != End) {
5482 Begin = F->SelectInstructions(Begin, End, FuncInfo.ValueMap,
5483 FuncInfo.MBBMap, BB);
5486 // The "fast" selector selected the entire block, so we're done.
5489 // Handle certain instructions as single-LLVM-Instruction blocks.
5490 if (isa<CallInst>(Begin) || isa<LoadInst>(Begin) ||
5491 isa<StoreInst>(Begin)) {
5492 if (Begin->getType() != Type::VoidTy) {
5493 unsigned &R = FuncInfo.ValueMap[Begin];
5495 R = FuncInfo.CreateRegForValue(Begin);
5498 SelectBasicBlock(LLVMBB, Begin, next(Begin), DoArgs,
5499 PHINodesToUpdate, FuncInfo);
5506 if (!DisableFastISelAbort &&
5507 // For now, don't abort on non-conditional-branch terminators.
5508 (!isa<TerminatorInst>(Begin) ||
5509 (isa<BranchInst>(Begin) &&
5510 cast<BranchInst>(Begin)->isUnconditional()))) {
5511 // The "fast" selector couldn't handle something and bailed.
5512 // For the purpose of debugging, just abort.
5516 assert(0 && "FastISel didn't select the entire block");
5524 if (Begin != End || DoArgs)
5525 SelectBasicBlock(LLVMBB, Begin, End, DoArgs, PHINodesToUpdate, FuncInfo);
5527 FinishBasicBlock(FuncInfo, PHINodesToUpdate);
5528 PHINodesToUpdate.clear();
5535 SelectionDAGISel::FinishBasicBlock(FunctionLoweringInfo &FuncInfo,
5536 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate) {
5538 // Perform target specific isel post processing.
5539 InstructionSelectPostProcessing();
5541 DOUT << "Target-post-processed machine code:\n";
5544 DOUT << "Total amount of phi nodes to update: "
5545 << PHINodesToUpdate.size() << "\n";
5546 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5547 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5548 << ", " << PHINodesToUpdate[i].second << ")\n";);
5550 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5551 // PHI nodes in successors.
5552 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5553 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5554 MachineInstr *PHI = PHINodesToUpdate[i].first;
5555 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5556 "This is not a machine PHI node that we are updating!");
5557 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5559 PHI->addOperand(MachineOperand::CreateMBB(BB));
5564 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5565 // Lower header first, if it wasn't already lowered
5566 if (!BitTestCases[i].Emitted) {
5567 SelectionDAGLowering HSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
5568 // Set the current basic block to the mbb we wish to insert the code into
5569 BB = BitTestCases[i].Parent;
5570 HSDL.setCurrentBasicBlock(BB);
5572 HSDL.visitBitTestHeader(BitTestCases[i]);
5573 CurDAG->setRoot(HSDL.getRoot());
5574 CodeGenAndEmitDAG();
5578 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5579 SelectionDAGLowering BSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
5580 // Set the current basic block to the mbb we wish to insert the code into
5581 BB = BitTestCases[i].Cases[j].ThisBB;
5582 BSDL.setCurrentBasicBlock(BB);
5585 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5586 BitTestCases[i].Reg,
5587 BitTestCases[i].Cases[j]);
5589 BSDL.visitBitTestCase(BitTestCases[i].Default,
5590 BitTestCases[i].Reg,
5591 BitTestCases[i].Cases[j]);
5594 CurDAG->setRoot(BSDL.getRoot());
5595 CodeGenAndEmitDAG();
5600 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5601 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5602 MachineBasicBlock *PHIBB = PHI->getParent();
5603 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5604 "This is not a machine PHI node that we are updating!");
5605 // This is "default" BB. We have two jumps to it. From "header" BB and
5606 // from last "case" BB.
5607 if (PHIBB == BitTestCases[i].Default) {
5608 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5610 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5611 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5613 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5616 // One of "cases" BB.
5617 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5618 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5619 if (cBB->succ_end() !=
5620 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5621 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5623 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5629 // If the JumpTable record is filled in, then we need to emit a jump table.
5630 // Updating the PHI nodes is tricky in this case, since we need to determine
5631 // whether the PHI is a successor of the range check MBB or the jump table MBB
5632 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5633 // Lower header first, if it wasn't already lowered
5634 if (!JTCases[i].first.Emitted) {
5635 SelectionDAGLowering HSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
5636 // Set the current basic block to the mbb we wish to insert the code into
5637 BB = JTCases[i].first.HeaderBB;
5638 HSDL.setCurrentBasicBlock(BB);
5640 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5641 CurDAG->setRoot(HSDL.getRoot());
5642 CodeGenAndEmitDAG();
5646 SelectionDAGLowering JSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
5647 // Set the current basic block to the mbb we wish to insert the code into
5648 BB = JTCases[i].second.MBB;
5649 JSDL.setCurrentBasicBlock(BB);
5651 JSDL.visitJumpTable(JTCases[i].second);
5652 CurDAG->setRoot(JSDL.getRoot());
5653 CodeGenAndEmitDAG();
5657 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5658 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5659 MachineBasicBlock *PHIBB = PHI->getParent();
5660 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5661 "This is not a machine PHI node that we are updating!");
5662 // "default" BB. We can go there only from header BB.
5663 if (PHIBB == JTCases[i].second.Default) {
5664 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5666 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5668 // JT BB. Just iterate over successors here
5669 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5670 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5672 PHI->addOperand(MachineOperand::CreateMBB(BB));
5677 // If the switch block involved a branch to one of the actual successors, we
5678 // need to update PHI nodes in that block.
5679 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5680 MachineInstr *PHI = PHINodesToUpdate[i].first;
5681 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5682 "This is not a machine PHI node that we are updating!");
5683 if (BB->isSuccessor(PHI->getParent())) {
5684 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5686 PHI->addOperand(MachineOperand::CreateMBB(BB));
5690 // If we generated any switch lowering information, build and codegen any
5691 // additional DAGs necessary.
5692 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5693 SelectionDAGLowering SDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
5695 // Set the current basic block to the mbb we wish to insert the code into
5696 BB = SwitchCases[i].ThisBB;
5697 SDL.setCurrentBasicBlock(BB);
5700 SDL.visitSwitchCase(SwitchCases[i]);
5701 CurDAG->setRoot(SDL.getRoot());
5702 CodeGenAndEmitDAG();
5705 // Handle any PHI nodes in successors of this chunk, as if we were coming
5706 // from the original BB before switch expansion. Note that PHI nodes can
5707 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5708 // handle them the right number of times.
5709 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5710 for (MachineBasicBlock::iterator Phi = BB->begin();
5711 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5712 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5713 for (unsigned pn = 0; ; ++pn) {
5714 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5715 if (PHINodesToUpdate[pn].first == Phi) {
5716 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5718 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5724 // Don't process RHS if same block as LHS.
5725 if (BB == SwitchCases[i].FalseBB)
5726 SwitchCases[i].FalseBB = 0;
5728 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5729 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5730 SwitchCases[i].FalseBB = 0;
5732 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5737 /// Schedule - Pick a safe ordering for instructions for each
5738 /// target node in the graph.
5740 ScheduleDAG *SelectionDAGISel::Schedule() {
5741 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5745 RegisterScheduler::setDefault(Ctor);
5748 ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast);
5755 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5756 return new HazardRecognizer();
5759 //===----------------------------------------------------------------------===//
5760 // Helper functions used by the generated instruction selector.
5761 //===----------------------------------------------------------------------===//
5762 // Calls to these methods are generated by tblgen.
5764 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5765 /// the dag combiner simplified the 255, we still want to match. RHS is the
5766 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5767 /// specified in the .td file (e.g. 255).
5768 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
5769 int64_t DesiredMaskS) const {
5770 const APInt &ActualMask = RHS->getAPIntValue();
5771 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5773 // If the actual mask exactly matches, success!
5774 if (ActualMask == DesiredMask)
5777 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5778 if (ActualMask.intersects(~DesiredMask))
5781 // Otherwise, the DAG Combiner may have proven that the value coming in is
5782 // either already zero or is not demanded. Check for known zero input bits.
5783 APInt NeededMask = DesiredMask & ~ActualMask;
5784 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5787 // TODO: check to see if missing bits are just not demanded.
5789 // Otherwise, this pattern doesn't match.
5793 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5794 /// the dag combiner simplified the 255, we still want to match. RHS is the
5795 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5796 /// specified in the .td file (e.g. 255).
5797 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
5798 int64_t DesiredMaskS) const {
5799 const APInt &ActualMask = RHS->getAPIntValue();
5800 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5802 // If the actual mask exactly matches, success!
5803 if (ActualMask == DesiredMask)
5806 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5807 if (ActualMask.intersects(~DesiredMask))
5810 // Otherwise, the DAG Combiner may have proven that the value coming in is
5811 // either already zero or is not demanded. Check for known zero input bits.
5812 APInt NeededMask = DesiredMask & ~ActualMask;
5814 APInt KnownZero, KnownOne;
5815 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5817 // If all the missing bits in the or are already known to be set, match!
5818 if ((NeededMask & KnownOne) == NeededMask)
5821 // TODO: check to see if missing bits are just not demanded.
5823 // Otherwise, this pattern doesn't match.
5828 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5829 /// by tblgen. Others should not call it.
5830 void SelectionDAGISel::
5831 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
5832 std::vector<SDValue> InOps;
5833 std::swap(InOps, Ops);
5835 Ops.push_back(InOps[0]); // input chain.
5836 Ops.push_back(InOps[1]); // input asm string.
5838 unsigned i = 2, e = InOps.size();
5839 if (InOps[e-1].getValueType() == MVT::Flag)
5840 --e; // Don't process a flag operand if it is here.
5843 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5844 if ((Flags & 7) != 4 /*MEM*/) {
5845 // Just skip over this operand, copying the operands verbatim.
5846 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5847 i += (Flags >> 3) + 1;
5849 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5850 // Otherwise, this is a memory operand. Ask the target to select it.
5851 std::vector<SDValue> SelOps;
5852 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
5853 cerr << "Could not match memory address. Inline asm failure!\n";
5857 // Add this to the output node.
5858 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
5859 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5861 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5866 // Add the flag input back if present.
5867 if (e != InOps.size())
5868 Ops.push_back(InOps.back());
5871 char SelectionDAGISel::ID = 0;