1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Target/MRegisterInfo.h"
35 #include "llvm/Target/TargetData.h"
36 #include "llvm/Target/TargetFrameInfo.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/MathExtras.h"
43 #include "llvm/Support/Debug.h"
52 ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
55 ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
61 // Scheduling heuristics
62 enum SchedHeuristics {
63 defaultScheduling, // Let the target specify its preference.
64 noScheduling, // No scheduling, emit breadth first sequence.
65 simpleScheduling, // Two pass, min. critical path, max. utilization.
66 simpleNoItinScheduling, // Same as above exact using generic latency.
67 listSchedulingBURR, // Bottom up reg reduction list scheduling.
68 listSchedulingTD // Top-down list scheduler.
72 cl::opt<SchedHeuristics>
75 cl::desc("Choose scheduling style"),
76 cl::init(defaultScheduling),
78 clEnumValN(defaultScheduling, "default",
79 "Target preferred scheduling style"),
80 clEnumValN(noScheduling, "none",
81 "No scheduling: breadth first sequencing"),
82 clEnumValN(simpleScheduling, "simple",
83 "Simple two pass scheduling: minimize critical path "
84 "and maximize processor utilization"),
85 clEnumValN(simpleNoItinScheduling, "simple-noitin",
86 "Simple two pass scheduling: Same as simple "
87 "except using generic latency"),
88 clEnumValN(listSchedulingBURR, "list-burr",
89 "Bottom up register reduction list scheduling"),
90 clEnumValN(listSchedulingTD, "list-td",
91 "Top-down list scheduler"),
96 /// RegsForValue - This struct represents the physical registers that a
97 /// particular value is assigned and the type information about the value.
98 /// This is needed because values can be promoted into larger registers and
99 /// expanded into multiple smaller registers than the value.
100 struct RegsForValue {
101 /// Regs - This list hold the register (for legal and promoted values)
102 /// or register set (for expanded values) that the value should be assigned
104 std::vector<unsigned> Regs;
106 /// RegVT - The value type of each register.
108 MVT::ValueType RegVT;
110 /// ValueVT - The value type of the LLVM value, which may be promoted from
111 /// RegVT or made from merging the two expanded parts.
112 MVT::ValueType ValueVT;
114 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
116 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
117 : RegVT(regvt), ValueVT(valuevt) {
120 RegsForValue(const std::vector<unsigned> ®s,
121 MVT::ValueType regvt, MVT::ValueType valuevt)
122 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
125 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
126 /// this value and returns the result as a ValueVT value. This uses
127 /// Chain/Flag as the input and updates them for the output Chain/Flag.
128 SDOperand getCopyFromRegs(SelectionDAG &DAG,
129 SDOperand &Chain, SDOperand &Flag) const;
131 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
132 /// specified value into the registers specified by this object. This uses
133 /// Chain/Flag as the input and updates them for the output Chain/Flag.
134 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
135 SDOperand &Chain, SDOperand &Flag) const;
137 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
138 /// operand list. This adds the code marker and includes the number of
139 /// values added into it.
140 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
141 std::vector<SDOperand> &Ops) const;
146 //===--------------------------------------------------------------------===//
147 /// FunctionLoweringInfo - This contains information that is global to a
148 /// function that is used when lowering a region of the function.
149 class FunctionLoweringInfo {
156 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
158 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
159 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
161 /// ValueMap - Since we emit code for the function a basic block at a time,
162 /// we must remember which virtual registers hold the values for
163 /// cross-basic-block values.
164 std::map<const Value*, unsigned> ValueMap;
166 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
167 /// the entry block. This allows the allocas to be efficiently referenced
168 /// anywhere in the function.
169 std::map<const AllocaInst*, int> StaticAllocaMap;
171 unsigned MakeReg(MVT::ValueType VT) {
172 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
175 unsigned CreateRegForValue(const Value *V);
177 unsigned InitializeRegForValue(const Value *V) {
178 unsigned &R = ValueMap[V];
179 assert(R == 0 && "Already initialized this value register!");
180 return R = CreateRegForValue(V);
185 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
186 /// PHI nodes or outside of the basic block that defines it, or used by a
187 /// switch instruction, which may expand to multiple basic blocks.
188 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
189 if (isa<PHINode>(I)) return true;
190 BasicBlock *BB = I->getParent();
191 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
192 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
193 isa<SwitchInst>(*UI))
198 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
199 /// entry block, return true. This includes arguments used by switches, since
200 /// the switch may expand into multiple basic blocks.
201 static bool isOnlyUsedInEntryBlock(Argument *A) {
202 BasicBlock *Entry = A->getParent()->begin();
203 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
204 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
205 return false; // Use not in entry block.
209 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
210 Function &fn, MachineFunction &mf)
211 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
213 // Create a vreg for each argument register that is not dead and is used
214 // outside of the entry block for the function.
215 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
217 if (!isOnlyUsedInEntryBlock(AI))
218 InitializeRegForValue(AI);
220 // Initialize the mapping of values to registers. This is only set up for
221 // instruction values that are used outside of the block that defines
223 Function::iterator BB = Fn.begin(), EB = Fn.end();
224 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
225 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
226 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
227 const Type *Ty = AI->getAllocatedType();
228 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
230 std::max((unsigned)TLI.getTargetData().getTypeAlignment(Ty),
233 // If the alignment of the value is smaller than the size of the value,
234 // and if the size of the value is particularly small (<= 8 bytes),
235 // round up to the size of the value for potentially better performance.
237 // FIXME: This could be made better with a preferred alignment hook in
238 // TargetData. It serves primarily to 8-byte align doubles for X86.
239 if (Align < TySize && TySize <= 8) Align = TySize;
240 TySize *= CUI->getValue(); // Get total allocated size.
241 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
242 StaticAllocaMap[AI] =
243 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
246 for (; BB != EB; ++BB)
247 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
248 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
249 if (!isa<AllocaInst>(I) ||
250 !StaticAllocaMap.count(cast<AllocaInst>(I)))
251 InitializeRegForValue(I);
253 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
254 // also creates the initial PHI MachineInstrs, though none of the input
255 // operands are populated.
256 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
257 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
259 MF.getBasicBlockList().push_back(MBB);
261 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
264 for (BasicBlock::iterator I = BB->begin();
265 (PN = dyn_cast<PHINode>(I)); ++I)
266 if (!PN->use_empty()) {
267 MVT::ValueType VT = TLI.getValueType(PN->getType());
268 unsigned NumElements;
269 if (VT != MVT::Vector)
270 NumElements = TLI.getNumElements(VT);
272 MVT::ValueType VT1,VT2;
274 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
277 unsigned PHIReg = ValueMap[PN];
278 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
279 for (unsigned i = 0; i != NumElements; ++i)
280 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
285 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
286 /// the correctly promoted or expanded types. Assign these registers
287 /// consecutive vreg numbers and return the first assigned number.
288 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
289 MVT::ValueType VT = TLI.getValueType(V->getType());
291 // The number of multiples of registers that we need, to, e.g., split up
292 // a <2 x int64> -> 4 x i32 registers.
293 unsigned NumVectorRegs = 1;
295 // If this is a packed type, figure out what type it will decompose into
296 // and how many of the elements it will use.
297 if (VT == MVT::Vector) {
298 const PackedType *PTy = cast<PackedType>(V->getType());
299 unsigned NumElts = PTy->getNumElements();
300 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
302 // Divide the input until we get to a supported size. This will always
303 // end with a scalar if the target doesn't support vectors.
304 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
311 VT = getVectorType(EltTy, NumElts);
314 // The common case is that we will only create one register for this
315 // value. If we have that case, create and return the virtual register.
316 unsigned NV = TLI.getNumElements(VT);
318 // If we are promoting this value, pick the next largest supported type.
319 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
320 unsigned Reg = MakeReg(PromotedType);
321 // If this is a vector of supported or promoted types (e.g. 4 x i16),
322 // create all of the registers.
323 for (unsigned i = 1; i != NumVectorRegs; ++i)
324 MakeReg(PromotedType);
328 // If this value is represented with multiple target registers, make sure
329 // to create enough consecutive registers of the right (smaller) type.
330 unsigned NT = VT-1; // Find the type to use.
331 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
334 unsigned R = MakeReg((MVT::ValueType)NT);
335 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
336 MakeReg((MVT::ValueType)NT);
340 //===----------------------------------------------------------------------===//
341 /// SelectionDAGLowering - This is the common target-independent lowering
342 /// implementation that is parameterized by a TargetLowering object.
343 /// Also, targets can overload any lowering method.
346 class SelectionDAGLowering {
347 MachineBasicBlock *CurMBB;
349 std::map<const Value*, SDOperand> NodeMap;
351 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
352 /// them up and then emit token factor nodes when possible. This allows us to
353 /// get simple disambiguation between loads without worrying about alias
355 std::vector<SDOperand> PendingLoads;
357 /// Case - A pair of values to record the Value for a switch case, and the
358 /// case's target basic block.
359 typedef std::pair<Constant*, MachineBasicBlock*> Case;
360 typedef std::vector<Case>::iterator CaseItr;
361 typedef std::pair<CaseItr, CaseItr> CaseRange;
363 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
364 /// of conditional branches.
366 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
367 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
369 /// CaseBB - The MBB in which to emit the compare and branch
370 MachineBasicBlock *CaseBB;
371 /// LT, GE - If nonzero, we know the current case value must be less-than or
372 /// greater-than-or-equal-to these Constants.
375 /// Range - A pair of iterators representing the range of case values to be
376 /// processed at this point in the binary search tree.
380 /// The comparison function for sorting Case values.
382 bool operator () (const Case& C1, const Case& C2) {
383 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
384 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
386 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
387 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
392 // TLI - This is information that describes the available target features we
393 // need for lowering. This indicates when operations are unavailable,
394 // implemented with a libcall, etc.
397 const TargetData &TD;
399 /// SwitchCases - Vector of CaseBlock structures used to communicate
400 /// SwitchInst code generation information.
401 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
402 SelectionDAGISel::JumpTable JT;
404 /// FuncInfo - Information about the function as a whole.
406 FunctionLoweringInfo &FuncInfo;
408 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
409 FunctionLoweringInfo &funcinfo)
410 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
411 JT(0,0,0,0), FuncInfo(funcinfo) {
414 /// getRoot - Return the current virtual root of the Selection DAG.
416 SDOperand getRoot() {
417 if (PendingLoads.empty())
418 return DAG.getRoot();
420 if (PendingLoads.size() == 1) {
421 SDOperand Root = PendingLoads[0];
423 PendingLoads.clear();
427 // Otherwise, we have to make a token factor node.
428 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
429 PendingLoads.clear();
434 void visit(Instruction &I) { visit(I.getOpcode(), I); }
436 void visit(unsigned Opcode, User &I) {
438 default: assert(0 && "Unknown instruction type encountered!");
440 // Build the switch statement using the Instruction.def file.
441 #define HANDLE_INST(NUM, OPCODE, CLASS) \
442 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
443 #include "llvm/Instruction.def"
447 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
449 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
450 SDOperand SrcValue, SDOperand Root,
453 SDOperand getIntPtrConstant(uint64_t Val) {
454 return DAG.getConstant(Val, TLI.getPointerTy());
457 SDOperand getValue(const Value *V);
459 const SDOperand &setValue(const Value *V, SDOperand NewN) {
460 SDOperand &N = NodeMap[V];
461 assert(N.Val == 0 && "Already set a value for this node!");
465 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
467 bool OutReg, bool InReg,
468 std::set<unsigned> &OutputRegs,
469 std::set<unsigned> &InputRegs);
471 // Terminator instructions.
472 void visitRet(ReturnInst &I);
473 void visitBr(BranchInst &I);
474 void visitSwitch(SwitchInst &I);
475 void visitUnreachable(UnreachableInst &I) { /* noop */ }
477 // Helper for visitSwitch
478 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
479 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
481 // These all get lowered before this pass.
482 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
483 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
485 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
486 void visitShift(User &I, unsigned Opcode);
487 void visitAdd(User &I) {
488 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
490 void visitSub(User &I);
491 void visitMul(User &I) {
492 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
494 void visitDiv(User &I) {
495 const Type *Ty = I.getType();
497 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
498 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
500 void visitRem(User &I) {
501 const Type *Ty = I.getType();
502 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
504 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
505 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
506 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
507 void visitShl(User &I) { visitShift(I, ISD::SHL); }
508 void visitShr(User &I) {
509 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
512 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
513 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ); }
514 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE); }
515 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE); }
516 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE); }
517 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
518 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
520 void visitExtractElement(User &I);
521 void visitInsertElement(User &I);
522 void visitShuffleVector(User &I);
524 void visitGetElementPtr(User &I);
525 void visitCast(User &I);
526 void visitSelect(User &I);
528 void visitMalloc(MallocInst &I);
529 void visitFree(FreeInst &I);
530 void visitAlloca(AllocaInst &I);
531 void visitLoad(LoadInst &I);
532 void visitStore(StoreInst &I);
533 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
534 void visitCall(CallInst &I);
535 void visitInlineAsm(CallInst &I);
536 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
537 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
539 void visitVAStart(CallInst &I);
540 void visitVAArg(VAArgInst &I);
541 void visitVAEnd(CallInst &I);
542 void visitVACopy(CallInst &I);
543 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
545 void visitMemIntrinsic(CallInst &I, unsigned Op);
547 void visitUserOp1(Instruction &I) {
548 assert(0 && "UserOp1 should not exist at instruction selection time!");
551 void visitUserOp2(Instruction &I) {
552 assert(0 && "UserOp2 should not exist at instruction selection time!");
556 } // end namespace llvm
558 SDOperand SelectionDAGLowering::getValue(const Value *V) {
559 SDOperand &N = NodeMap[V];
562 const Type *VTy = V->getType();
563 MVT::ValueType VT = TLI.getValueType(VTy);
564 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
565 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
566 visit(CE->getOpcode(), *CE);
567 assert(N.Val && "visit didn't populate the ValueMap!");
569 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
570 return N = DAG.getGlobalAddress(GV, VT);
571 } else if (isa<ConstantPointerNull>(C)) {
572 return N = DAG.getConstant(0, TLI.getPointerTy());
573 } else if (isa<UndefValue>(C)) {
574 if (!isa<PackedType>(VTy))
575 return N = DAG.getNode(ISD::UNDEF, VT);
577 // Create a VBUILD_VECTOR of undef nodes.
578 const PackedType *PTy = cast<PackedType>(VTy);
579 unsigned NumElements = PTy->getNumElements();
580 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
582 std::vector<SDOperand> Ops;
583 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
585 // Create a VConstant node with generic Vector type.
586 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
587 Ops.push_back(DAG.getValueType(PVT));
588 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
589 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
590 return N = DAG.getConstantFP(CFP->getValue(), VT);
591 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
592 unsigned NumElements = PTy->getNumElements();
593 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
595 // Now that we know the number and type of the elements, push a
596 // Constant or ConstantFP node onto the ops list for each element of
597 // the packed constant.
598 std::vector<SDOperand> Ops;
599 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
600 for (unsigned i = 0; i != NumElements; ++i)
601 Ops.push_back(getValue(CP->getOperand(i)));
603 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
605 if (MVT::isFloatingPoint(PVT))
606 Op = DAG.getConstantFP(0, PVT);
608 Op = DAG.getConstant(0, PVT);
609 Ops.assign(NumElements, Op);
612 // Create a VBUILD_VECTOR node with generic Vector type.
613 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
614 Ops.push_back(DAG.getValueType(PVT));
615 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
617 // Canonicalize all constant ints to be unsigned.
618 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
622 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
623 std::map<const AllocaInst*, int>::iterator SI =
624 FuncInfo.StaticAllocaMap.find(AI);
625 if (SI != FuncInfo.StaticAllocaMap.end())
626 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
629 std::map<const Value*, unsigned>::const_iterator VMI =
630 FuncInfo.ValueMap.find(V);
631 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
633 unsigned InReg = VMI->second;
635 // If this type is not legal, make it so now.
636 if (VT != MVT::Vector) {
637 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
639 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
641 // Source must be expanded. This input value is actually coming from the
642 // register pair VMI->second and VMI->second+1.
643 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
644 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
645 } else if (DestVT > VT) { // Promotion case
646 if (MVT::isFloatingPoint(VT))
647 N = DAG.getNode(ISD::FP_ROUND, VT, N);
649 N = DAG.getNode(ISD::TRUNCATE, VT, N);
652 // Otherwise, if this is a vector, make it available as a generic vector
654 MVT::ValueType PTyElementVT, PTyLegalElementVT;
655 const PackedType *PTy = cast<PackedType>(VTy);
656 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
659 // Build a VBUILD_VECTOR with the input registers.
660 std::vector<SDOperand> Ops;
661 if (PTyElementVT == PTyLegalElementVT) {
662 // If the value types are legal, just VBUILD the CopyFromReg nodes.
663 for (unsigned i = 0; i != NE; ++i)
664 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
666 } else if (PTyElementVT < PTyLegalElementVT) {
667 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
668 for (unsigned i = 0; i != NE; ++i) {
669 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
671 if (MVT::isFloatingPoint(PTyElementVT))
672 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
674 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
678 // If the register was expanded, use BUILD_PAIR.
679 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
680 for (unsigned i = 0; i != NE/2; ++i) {
681 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
683 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
685 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
689 Ops.push_back(DAG.getConstant(NE, MVT::i32));
690 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
691 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
693 // Finally, use a VBIT_CONVERT to make this available as the appropriate
695 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
696 DAG.getConstant(PTy->getNumElements(),
698 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
705 void SelectionDAGLowering::visitRet(ReturnInst &I) {
706 if (I.getNumOperands() == 0) {
707 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
710 std::vector<SDOperand> NewValues;
711 NewValues.push_back(getRoot());
712 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
713 SDOperand RetOp = getValue(I.getOperand(i));
715 // If this is an integer return value, we need to promote it ourselves to
716 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
718 if (MVT::isInteger(RetOp.getValueType()) &&
719 RetOp.getValueType() < MVT::i64) {
720 MVT::ValueType TmpVT;
721 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
722 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
726 if (I.getOperand(i)->getType()->isSigned())
727 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
729 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
731 NewValues.push_back(RetOp);
733 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
736 void SelectionDAGLowering::visitBr(BranchInst &I) {
737 // Update machine-CFG edges.
738 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
739 CurMBB->addSuccessor(Succ0MBB);
741 // Figure out which block is immediately after the current one.
742 MachineBasicBlock *NextBlock = 0;
743 MachineFunction::iterator BBI = CurMBB;
744 if (++BBI != CurMBB->getParent()->end())
747 if (I.isUnconditional()) {
748 // If this is not a fall-through branch, emit the branch.
749 if (Succ0MBB != NextBlock)
750 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
751 DAG.getBasicBlock(Succ0MBB)));
753 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
754 CurMBB->addSuccessor(Succ1MBB);
756 SDOperand Cond = getValue(I.getCondition());
757 if (Succ1MBB == NextBlock) {
758 // If the condition is false, fall through. This means we should branch
759 // if the condition is true to Succ #0.
760 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
761 Cond, DAG.getBasicBlock(Succ0MBB)));
762 } else if (Succ0MBB == NextBlock) {
763 // If the condition is true, fall through. This means we should branch if
764 // the condition is false to Succ #1. Invert the condition first.
765 SDOperand True = DAG.getConstant(1, Cond.getValueType());
766 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
767 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
768 Cond, DAG.getBasicBlock(Succ1MBB)));
770 std::vector<SDOperand> Ops;
771 Ops.push_back(getRoot());
772 // If the false case is the current basic block, then this is a self
773 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
774 // adds an extra instruction in the loop. Instead, invert the
775 // condition and emit "Loop: ... br!cond Loop; br Out.
776 if (CurMBB == Succ1MBB) {
777 std::swap(Succ0MBB, Succ1MBB);
778 SDOperand True = DAG.getConstant(1, Cond.getValueType());
779 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
781 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
782 DAG.getBasicBlock(Succ0MBB));
783 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
784 DAG.getBasicBlock(Succ1MBB)));
789 /// visitSwitchCase - Emits the necessary code to represent a single node in
790 /// the binary search tree resulting from lowering a switch instruction.
791 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
792 SDOperand SwitchOp = getValue(CB.SwitchV);
793 SDOperand CaseOp = getValue(CB.CaseC);
794 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
796 // Set NextBlock to be the MBB immediately after the current one, if any.
797 // This is used to avoid emitting unnecessary branches to the next block.
798 MachineBasicBlock *NextBlock = 0;
799 MachineFunction::iterator BBI = CurMBB;
800 if (++BBI != CurMBB->getParent()->end())
803 // If the lhs block is the next block, invert the condition so that we can
804 // fall through to the lhs instead of the rhs block.
805 if (CB.LHSBB == NextBlock) {
806 std::swap(CB.LHSBB, CB.RHSBB);
807 SDOperand True = DAG.getConstant(1, Cond.getValueType());
808 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
810 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
811 DAG.getBasicBlock(CB.LHSBB));
812 if (CB.RHSBB == NextBlock)
815 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
816 DAG.getBasicBlock(CB.RHSBB)));
817 // Update successor info
818 CurMBB->addSuccessor(CB.LHSBB);
819 CurMBB->addSuccessor(CB.RHSBB);
822 /// visitSwitchCase - Emits the necessary code to represent a single node in
823 /// the binary search tree resulting from lowering a switch instruction.
824 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
825 // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
826 // we need to add the address of the jump table to the value loaded, since
827 // the entries in the jump table will be differences rather than absolute
830 // Emit the code for the jump table
831 MVT::ValueType PTy = TLI.getPointerTy();
832 unsigned PTyBytes = MVT::getSizeInBits(PTy)/8;
833 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
834 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
835 DAG.getConstant(PTyBytes, PTy));
836 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, DAG.getJumpTable(JT.JTI,PTy));
837 SDOperand LD = DAG.getLoad(PTy, Copy.getValue(1), ADD, DAG.getSrcValue(0));
838 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
840 // Update successor info
841 for (std::set<MachineBasicBlock*>::iterator ii = JT.SuccMBBs.begin(),
842 ee = JT.SuccMBBs.end(); ii != ee; ++ii)
843 JT.MBB->addSuccessor(*ii);
846 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
847 // Figure out which block is immediately after the current one.
848 MachineBasicBlock *NextBlock = 0;
849 MachineFunction::iterator BBI = CurMBB;
850 if (++BBI != CurMBB->getParent()->end())
853 // If there is only the default destination, branch to it if it is not the
854 // next basic block. Otherwise, just fall through.
855 if (I.getNumOperands() == 2) {
856 // Update machine-CFG edges.
857 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
858 // If this is not a fall-through branch, emit the branch.
859 if (DefaultMBB != NextBlock)
860 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
861 DAG.getBasicBlock(DefaultMBB)));
865 // If there are any non-default case statements, create a vector of Cases
866 // representing each one, and sort the vector so that we can efficiently
867 // create a binary search tree from them.
868 std::vector<Case> Cases;
869 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
870 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
871 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
873 std::sort(Cases.begin(), Cases.end(), CaseCmp());
875 // Get the Value to be switched on and default basic blocks, which will be
876 // inserted into CaseBlock records, representing basic blocks in the binary
878 Value *SV = I.getOperand(0);
879 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
881 // Get the MachineFunction which holds the current MBB. This is used during
882 // emission of jump tables, and when inserting any additional MBBs necessary
883 // to represent the switch.
884 MachineFunction *CurMF = CurMBB->getParent();
885 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
886 Reloc::Model Relocs = TLI.getTargetMachine().getRelocationModel();
888 // If the switch has more than 3 blocks, and is 100% dense, then emit a jump
889 // table rather than lowering the switch to a binary tree of conditional
891 // FIXME: Make this work with 64 bit targets someday, possibly by always
892 // doing differences there so that entries stay 32 bits.
893 // FIXME: Make this work with PIC code
894 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
895 TLI.getPointerTy() == MVT::i32 &&
896 (Relocs == Reloc::Static || Relocs == Reloc::DynamicNoPIC) &&
898 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
899 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
902 // FIXME: support sub-100% density
903 if (((Last - First) + 1ULL) == (uint64_t)Cases.size()) {
904 // Create a new basic block to hold the code for loading the address
905 // of the jump table, and jumping to it. Update successor information;
906 // we will either branch to the default case for the switch, or the jump
908 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
909 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
910 CurMBB->addSuccessor(Default);
911 CurMBB->addSuccessor(JumpTableBB);
913 // Subtract the lowest switch case value from the value being switched on
914 // and conditional branch to default mbb if the result is greater than the
915 // difference between smallest and largest cases.
916 SDOperand SwitchOp = getValue(SV);
917 MVT::ValueType VT = SwitchOp.getValueType();
918 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
919 DAG.getConstant(First, VT));
921 // The SDNode we just created, which holds the value being switched on
922 // minus the the smallest case value, needs to be copied to a virtual
923 // register so it can be used as an index into the jump table in a
924 // subsequent basic block. This value may be smaller or larger than the
925 // target's pointer type, and therefore require extension or truncating.
926 if (VT > TLI.getPointerTy())
927 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
929 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
930 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
931 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
933 // Emit the range check for the jump table, and branch to the default
934 // block for the switch statement if the value being switched on exceeds
935 // the largest case in the switch.
936 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
937 DAG.getConstant(Last-First,VT), ISD::SETUGT);
938 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
939 DAG.getBasicBlock(Default)));
941 // Build a sorted vector of destination BBs, corresponding to each target
943 // FIXME: need to insert DefaultMBB for each "hole" in the jump table,
944 // when we support jump tables with < 100% density.
945 std::set<MachineBasicBlock*> UniqueBBs;
946 std::vector<MachineBasicBlock*> DestBBs;
947 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++ii) {
948 DestBBs.push_back(ii->second);
949 UniqueBBs.insert(ii->second);
951 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
953 // Set the jump table information so that we can codegen it as a second
955 JT.Reg = JumpTableReg;
957 JT.MBB = JumpTableBB;
958 JT.Default = Default;
959 JT.SuccMBBs = UniqueBBs;
964 // Push the initial CaseRec onto the worklist
965 std::vector<CaseRec> CaseVec;
966 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
968 while (!CaseVec.empty()) {
969 // Grab a record representing a case range to process off the worklist
970 CaseRec CR = CaseVec.back();
973 // Size is the number of Cases represented by this range. If Size is 1,
974 // then we are processing a leaf of the binary search tree. Otherwise,
975 // we need to pick a pivot, and push left and right ranges onto the
977 unsigned Size = CR.Range.second - CR.Range.first;
980 // Create a CaseBlock record representing a conditional branch to
981 // the Case's target mbb if the value being switched on SV is equal
982 // to C. Otherwise, branch to default.
983 Constant *C = CR.Range.first->first;
984 MachineBasicBlock *Target = CR.Range.first->second;
985 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
987 // If the MBB representing the leaf node is the current MBB, then just
988 // call visitSwitchCase to emit the code into the current block.
989 // Otherwise, push the CaseBlock onto the vector to be later processed
990 // by SDISel, and insert the node's MBB before the next MBB.
991 if (CR.CaseBB == CurMBB)
994 SwitchCases.push_back(CB);
995 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
998 // split case range at pivot
999 CaseItr Pivot = CR.Range.first + (Size / 2);
1000 CaseRange LHSR(CR.Range.first, Pivot);
1001 CaseRange RHSR(Pivot, CR.Range.second);
1002 Constant *C = Pivot->first;
1003 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1004 // We know that we branch to the LHS if the Value being switched on is
1005 // less than the Pivot value, C. We use this to optimize our binary
1006 // tree a bit, by recognizing that if SV is greater than or equal to the
1007 // LHS's Case Value, and that Case Value is exactly one less than the
1008 // Pivot's Value, then we can branch directly to the LHS's Target,
1009 // rather than creating a leaf node for it.
1010 if ((LHSR.second - LHSR.first) == 1 &&
1011 LHSR.first->first == CR.GE &&
1012 cast<ConstantIntegral>(C)->getRawValue() ==
1013 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1014 LHSBB = LHSR.first->second;
1016 LHSBB = new MachineBasicBlock(LLVMBB);
1017 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1019 // Similar to the optimization above, if the Value being switched on is
1020 // known to be less than the Constant CR.LT, and the current Case Value
1021 // is CR.LT - 1, then we can branch directly to the target block for
1022 // the current Case Value, rather than emitting a RHS leaf node for it.
1023 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1024 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1025 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1026 RHSBB = RHSR.first->second;
1028 RHSBB = new MachineBasicBlock(LLVMBB);
1029 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1031 // Create a CaseBlock record representing a conditional branch to
1032 // the LHS node if the value being switched on SV is less than C.
1033 // Otherwise, branch to LHS.
1034 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1035 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1036 if (CR.CaseBB == CurMBB)
1037 visitSwitchCase(CB);
1039 SwitchCases.push_back(CB);
1040 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1046 void SelectionDAGLowering::visitSub(User &I) {
1047 // -0.0 - X --> fneg
1048 if (I.getType()->isFloatingPoint()) {
1049 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1050 if (CFP->isExactlyValue(-0.0)) {
1051 SDOperand Op2 = getValue(I.getOperand(1));
1052 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1056 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
1059 void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1061 const Type *Ty = I.getType();
1062 SDOperand Op1 = getValue(I.getOperand(0));
1063 SDOperand Op2 = getValue(I.getOperand(1));
1065 if (Ty->isIntegral()) {
1066 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1067 } else if (Ty->isFloatingPoint()) {
1068 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1070 const PackedType *PTy = cast<PackedType>(Ty);
1071 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1072 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1073 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1077 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1078 SDOperand Op1 = getValue(I.getOperand(0));
1079 SDOperand Op2 = getValue(I.getOperand(1));
1081 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1083 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1086 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1087 ISD::CondCode UnsignedOpcode) {
1088 SDOperand Op1 = getValue(I.getOperand(0));
1089 SDOperand Op2 = getValue(I.getOperand(1));
1090 ISD::CondCode Opcode = SignedOpcode;
1091 if (I.getOperand(0)->getType()->isUnsigned())
1092 Opcode = UnsignedOpcode;
1093 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1096 void SelectionDAGLowering::visitSelect(User &I) {
1097 SDOperand Cond = getValue(I.getOperand(0));
1098 SDOperand TrueVal = getValue(I.getOperand(1));
1099 SDOperand FalseVal = getValue(I.getOperand(2));
1100 if (!isa<PackedType>(I.getType())) {
1101 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1102 TrueVal, FalseVal));
1104 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1105 *(TrueVal.Val->op_end()-2),
1106 *(TrueVal.Val->op_end()-1)));
1110 void SelectionDAGLowering::visitCast(User &I) {
1111 SDOperand N = getValue(I.getOperand(0));
1112 MVT::ValueType SrcVT = N.getValueType();
1113 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1115 if (DestVT == MVT::Vector) {
1116 // This is a cast to a vector from something else. This is always a bit
1117 // convert. Get information about the input vector.
1118 const PackedType *DestTy = cast<PackedType>(I.getType());
1119 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1120 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1121 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1122 DAG.getValueType(EltVT)));
1123 } else if (SrcVT == DestVT) {
1124 setValue(&I, N); // noop cast.
1125 } else if (DestVT == MVT::i1) {
1126 // Cast to bool is a comparison against zero, not truncation to zero.
1127 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1128 DAG.getConstantFP(0.0, N.getValueType());
1129 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1130 } else if (isInteger(SrcVT)) {
1131 if (isInteger(DestVT)) { // Int -> Int cast
1132 if (DestVT < SrcVT) // Truncating cast?
1133 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1134 else if (I.getOperand(0)->getType()->isSigned())
1135 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1137 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1138 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1139 if (I.getOperand(0)->getType()->isSigned())
1140 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1142 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1144 assert(0 && "Unknown cast!");
1146 } else if (isFloatingPoint(SrcVT)) {
1147 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1148 if (DestVT < SrcVT) // Rounding cast?
1149 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1151 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1152 } else if (isInteger(DestVT)) { // FP -> Int cast.
1153 if (I.getType()->isSigned())
1154 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1156 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1158 assert(0 && "Unknown cast!");
1161 assert(SrcVT == MVT::Vector && "Unknown cast!");
1162 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1163 // This is a cast from a vector to something else. This is always a bit
1164 // convert. Get information about the input vector.
1165 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1169 void SelectionDAGLowering::visitInsertElement(User &I) {
1170 SDOperand InVec = getValue(I.getOperand(0));
1171 SDOperand InVal = getValue(I.getOperand(1));
1172 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1173 getValue(I.getOperand(2)));
1175 SDOperand Num = *(InVec.Val->op_end()-2);
1176 SDOperand Typ = *(InVec.Val->op_end()-1);
1177 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1178 InVec, InVal, InIdx, Num, Typ));
1181 void SelectionDAGLowering::visitExtractElement(User &I) {
1182 SDOperand InVec = getValue(I.getOperand(0));
1183 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1184 getValue(I.getOperand(1)));
1185 SDOperand Typ = *(InVec.Val->op_end()-1);
1186 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1187 TLI.getValueType(I.getType()), InVec, InIdx));
1190 void SelectionDAGLowering::visitShuffleVector(User &I) {
1191 SDOperand V1 = getValue(I.getOperand(0));
1192 SDOperand V2 = getValue(I.getOperand(1));
1193 SDOperand Mask = getValue(I.getOperand(2));
1195 SDOperand Num = *(V1.Val->op_end()-2);
1196 SDOperand Typ = *(V2.Val->op_end()-1);
1197 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1198 V1, V2, Mask, Num, Typ));
1202 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1203 SDOperand N = getValue(I.getOperand(0));
1204 const Type *Ty = I.getOperand(0)->getType();
1205 const Type *UIntPtrTy = TD.getIntPtrType();
1207 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1210 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1211 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1214 uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field];
1215 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1216 getIntPtrConstant(Offset));
1218 Ty = StTy->getElementType(Field);
1220 Ty = cast<SequentialType>(Ty)->getElementType();
1222 // If this is a constant subscript, handle it quickly.
1223 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1224 if (CI->getRawValue() == 0) continue;
1227 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1228 Offs = (int64_t)TD.getTypeSize(Ty)*CSI->getValue();
1230 Offs = TD.getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1231 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1235 // N = N + Idx * ElementSize;
1236 uint64_t ElementSize = TD.getTypeSize(Ty);
1237 SDOperand IdxN = getValue(Idx);
1239 // If the index is smaller or larger than intptr_t, truncate or extend
1241 if (IdxN.getValueType() < N.getValueType()) {
1242 if (Idx->getType()->isSigned())
1243 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1245 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1246 } else if (IdxN.getValueType() > N.getValueType())
1247 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1249 // If this is a multiply by a power of two, turn it into a shl
1250 // immediately. This is a very common case.
1251 if (isPowerOf2_64(ElementSize)) {
1252 unsigned Amt = Log2_64(ElementSize);
1253 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1254 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1255 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1259 SDOperand Scale = getIntPtrConstant(ElementSize);
1260 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1261 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1267 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1268 // If this is a fixed sized alloca in the entry block of the function,
1269 // allocate it statically on the stack.
1270 if (FuncInfo.StaticAllocaMap.count(&I))
1271 return; // getValue will auto-populate this.
1273 const Type *Ty = I.getAllocatedType();
1274 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
1275 unsigned Align = std::max((unsigned)TLI.getTargetData().getTypeAlignment(Ty),
1278 SDOperand AllocSize = getValue(I.getArraySize());
1279 MVT::ValueType IntPtr = TLI.getPointerTy();
1280 if (IntPtr < AllocSize.getValueType())
1281 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1282 else if (IntPtr > AllocSize.getValueType())
1283 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1285 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1286 getIntPtrConstant(TySize));
1288 // Handle alignment. If the requested alignment is less than or equal to the
1289 // stack alignment, ignore it and round the size of the allocation up to the
1290 // stack alignment size. If the size is greater than the stack alignment, we
1291 // note this in the DYNAMIC_STACKALLOC node.
1292 unsigned StackAlign =
1293 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1294 if (Align <= StackAlign) {
1296 // Add SA-1 to the size.
1297 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1298 getIntPtrConstant(StackAlign-1));
1299 // Mask out the low bits for alignment purposes.
1300 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1301 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1304 std::vector<MVT::ValueType> VTs;
1305 VTs.push_back(AllocSize.getValueType());
1306 VTs.push_back(MVT::Other);
1307 std::vector<SDOperand> Ops;
1308 Ops.push_back(getRoot());
1309 Ops.push_back(AllocSize);
1310 Ops.push_back(getIntPtrConstant(Align));
1311 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
1312 DAG.setRoot(setValue(&I, DSA).getValue(1));
1314 // Inform the Frame Information that we have just allocated a variable-sized
1316 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1319 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1320 SDOperand Ptr = getValue(I.getOperand(0));
1326 // Do not serialize non-volatile loads against each other.
1327 Root = DAG.getRoot();
1330 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
1331 Root, I.isVolatile()));
1334 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1335 SDOperand SrcValue, SDOperand Root,
1338 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1339 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1340 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
1342 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
1346 DAG.setRoot(L.getValue(1));
1348 PendingLoads.push_back(L.getValue(1));
1354 void SelectionDAGLowering::visitStore(StoreInst &I) {
1355 Value *SrcV = I.getOperand(0);
1356 SDOperand Src = getValue(SrcV);
1357 SDOperand Ptr = getValue(I.getOperand(1));
1358 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
1359 DAG.getSrcValue(I.getOperand(1))));
1362 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1363 /// access memory and has no other side effects at all.
1364 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1365 #define GET_NO_MEMORY_INTRINSICS
1366 #include "llvm/Intrinsics.gen"
1367 #undef GET_NO_MEMORY_INTRINSICS
1371 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1372 // have any side-effects or if it only reads memory.
1373 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1374 #define GET_SIDE_EFFECT_INFO
1375 #include "llvm/Intrinsics.gen"
1376 #undef GET_SIDE_EFFECT_INFO
1380 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1382 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1383 unsigned Intrinsic) {
1384 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1385 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1387 // Build the operand list.
1388 std::vector<SDOperand> Ops;
1389 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1391 // We don't need to serialize loads against other loads.
1392 Ops.push_back(DAG.getRoot());
1394 Ops.push_back(getRoot());
1398 // Add the intrinsic ID as an integer operand.
1399 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1401 // Add all operands of the call to the operand list.
1402 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1403 SDOperand Op = getValue(I.getOperand(i));
1405 // If this is a vector type, force it to the right packed type.
1406 if (Op.getValueType() == MVT::Vector) {
1407 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1408 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1410 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1411 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1412 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1415 assert(TLI.isTypeLegal(Op.getValueType()) &&
1416 "Intrinsic uses a non-legal type?");
1420 std::vector<MVT::ValueType> VTs;
1421 if (I.getType() != Type::VoidTy) {
1422 MVT::ValueType VT = TLI.getValueType(I.getType());
1423 if (VT == MVT::Vector) {
1424 const PackedType *DestTy = cast<PackedType>(I.getType());
1425 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1427 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1428 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1431 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1435 VTs.push_back(MVT::Other);
1440 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
1441 else if (I.getType() != Type::VoidTy)
1442 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
1444 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
1447 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1449 PendingLoads.push_back(Chain);
1453 if (I.getType() != Type::VoidTy) {
1454 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1455 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1456 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1457 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1458 DAG.getValueType(EVT));
1460 setValue(&I, Result);
1464 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1465 /// we want to emit this as a call to a named external function, return the name
1466 /// otherwise lower it and return null.
1468 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1469 switch (Intrinsic) {
1471 // By default, turn this into a target intrinsic node.
1472 visitTargetIntrinsic(I, Intrinsic);
1474 case Intrinsic::vastart: visitVAStart(I); return 0;
1475 case Intrinsic::vaend: visitVAEnd(I); return 0;
1476 case Intrinsic::vacopy: visitVACopy(I); return 0;
1477 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1478 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1479 case Intrinsic::setjmp:
1480 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1482 case Intrinsic::longjmp:
1483 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1485 case Intrinsic::memcpy_i32:
1486 case Intrinsic::memcpy_i64:
1487 visitMemIntrinsic(I, ISD::MEMCPY);
1489 case Intrinsic::memset_i32:
1490 case Intrinsic::memset_i64:
1491 visitMemIntrinsic(I, ISD::MEMSET);
1493 case Intrinsic::memmove_i32:
1494 case Intrinsic::memmove_i64:
1495 visitMemIntrinsic(I, ISD::MEMMOVE);
1498 case Intrinsic::dbg_stoppoint: {
1499 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1500 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1501 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1502 std::vector<SDOperand> Ops;
1504 Ops.push_back(getRoot());
1505 Ops.push_back(getValue(SPI.getLineValue()));
1506 Ops.push_back(getValue(SPI.getColumnValue()));
1508 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1509 assert(DD && "Not a debug information descriptor");
1510 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1512 Ops.push_back(DAG.getString(CompileUnit->getFileName()));
1513 Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
1515 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
1520 case Intrinsic::dbg_region_start: {
1521 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1522 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1523 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1524 std::vector<SDOperand> Ops;
1526 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1528 Ops.push_back(getRoot());
1529 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1531 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1536 case Intrinsic::dbg_region_end: {
1537 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1538 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1539 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1540 std::vector<SDOperand> Ops;
1542 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1544 Ops.push_back(getRoot());
1545 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1547 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1552 case Intrinsic::dbg_func_start: {
1553 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1554 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1555 if (DebugInfo && FSI.getSubprogram() &&
1556 DebugInfo->Verify(FSI.getSubprogram())) {
1557 std::vector<SDOperand> Ops;
1559 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1561 Ops.push_back(getRoot());
1562 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1564 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1569 case Intrinsic::dbg_declare: {
1570 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1571 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1572 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1573 std::vector<SDOperand> Ops;
1575 SDOperand AddressOp = getValue(DI.getAddress());
1576 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
1577 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1584 case Intrinsic::isunordered_f32:
1585 case Intrinsic::isunordered_f64:
1586 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1587 getValue(I.getOperand(2)), ISD::SETUO));
1590 case Intrinsic::sqrt_f32:
1591 case Intrinsic::sqrt_f64:
1592 setValue(&I, DAG.getNode(ISD::FSQRT,
1593 getValue(I.getOperand(1)).getValueType(),
1594 getValue(I.getOperand(1))));
1596 case Intrinsic::pcmarker: {
1597 SDOperand Tmp = getValue(I.getOperand(1));
1598 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1601 case Intrinsic::readcyclecounter: {
1602 std::vector<MVT::ValueType> VTs;
1603 VTs.push_back(MVT::i64);
1604 VTs.push_back(MVT::Other);
1605 std::vector<SDOperand> Ops;
1606 Ops.push_back(getRoot());
1607 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
1609 DAG.setRoot(Tmp.getValue(1));
1612 case Intrinsic::bswap_i16:
1613 case Intrinsic::bswap_i32:
1614 case Intrinsic::bswap_i64:
1615 setValue(&I, DAG.getNode(ISD::BSWAP,
1616 getValue(I.getOperand(1)).getValueType(),
1617 getValue(I.getOperand(1))));
1619 case Intrinsic::cttz_i8:
1620 case Intrinsic::cttz_i16:
1621 case Intrinsic::cttz_i32:
1622 case Intrinsic::cttz_i64:
1623 setValue(&I, DAG.getNode(ISD::CTTZ,
1624 getValue(I.getOperand(1)).getValueType(),
1625 getValue(I.getOperand(1))));
1627 case Intrinsic::ctlz_i8:
1628 case Intrinsic::ctlz_i16:
1629 case Intrinsic::ctlz_i32:
1630 case Intrinsic::ctlz_i64:
1631 setValue(&I, DAG.getNode(ISD::CTLZ,
1632 getValue(I.getOperand(1)).getValueType(),
1633 getValue(I.getOperand(1))));
1635 case Intrinsic::ctpop_i8:
1636 case Intrinsic::ctpop_i16:
1637 case Intrinsic::ctpop_i32:
1638 case Intrinsic::ctpop_i64:
1639 setValue(&I, DAG.getNode(ISD::CTPOP,
1640 getValue(I.getOperand(1)).getValueType(),
1641 getValue(I.getOperand(1))));
1643 case Intrinsic::stacksave: {
1644 std::vector<MVT::ValueType> VTs;
1645 VTs.push_back(TLI.getPointerTy());
1646 VTs.push_back(MVT::Other);
1647 std::vector<SDOperand> Ops;
1648 Ops.push_back(getRoot());
1649 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
1651 DAG.setRoot(Tmp.getValue(1));
1654 case Intrinsic::stackrestore: {
1655 SDOperand Tmp = getValue(I.getOperand(1));
1656 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1659 case Intrinsic::prefetch:
1660 // FIXME: Currently discarding prefetches.
1666 void SelectionDAGLowering::visitCall(CallInst &I) {
1667 const char *RenameFn = 0;
1668 if (Function *F = I.getCalledFunction()) {
1669 if (F->isExternal())
1670 if (unsigned IID = F->getIntrinsicID()) {
1671 RenameFn = visitIntrinsicCall(I, IID);
1674 } else { // Not an LLVM intrinsic.
1675 const std::string &Name = F->getName();
1676 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1677 if (I.getNumOperands() == 3 && // Basic sanity checks.
1678 I.getOperand(1)->getType()->isFloatingPoint() &&
1679 I.getType() == I.getOperand(1)->getType() &&
1680 I.getType() == I.getOperand(2)->getType()) {
1681 SDOperand LHS = getValue(I.getOperand(1));
1682 SDOperand RHS = getValue(I.getOperand(2));
1683 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1687 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1688 if (I.getNumOperands() == 2 && // Basic sanity checks.
1689 I.getOperand(1)->getType()->isFloatingPoint() &&
1690 I.getType() == I.getOperand(1)->getType()) {
1691 SDOperand Tmp = getValue(I.getOperand(1));
1692 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1695 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1696 if (I.getNumOperands() == 2 && // Basic sanity checks.
1697 I.getOperand(1)->getType()->isFloatingPoint() &&
1698 I.getType() == I.getOperand(1)->getType()) {
1699 SDOperand Tmp = getValue(I.getOperand(1));
1700 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1703 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1704 if (I.getNumOperands() == 2 && // Basic sanity checks.
1705 I.getOperand(1)->getType()->isFloatingPoint() &&
1706 I.getType() == I.getOperand(1)->getType()) {
1707 SDOperand Tmp = getValue(I.getOperand(1));
1708 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1713 } else if (isa<InlineAsm>(I.getOperand(0))) {
1720 Callee = getValue(I.getOperand(0));
1722 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1723 std::vector<std::pair<SDOperand, const Type*> > Args;
1724 Args.reserve(I.getNumOperands());
1725 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1726 Value *Arg = I.getOperand(i);
1727 SDOperand ArgNode = getValue(Arg);
1728 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1731 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1732 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1734 std::pair<SDOperand,SDOperand> Result =
1735 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1736 I.isTailCall(), Callee, Args, DAG);
1737 if (I.getType() != Type::VoidTy)
1738 setValue(&I, Result.first);
1739 DAG.setRoot(Result.second);
1742 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1743 SDOperand &Chain, SDOperand &Flag)const{
1744 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1745 Chain = Val.getValue(1);
1746 Flag = Val.getValue(2);
1748 // If the result was expanded, copy from the top part.
1749 if (Regs.size() > 1) {
1750 assert(Regs.size() == 2 &&
1751 "Cannot expand to more than 2 elts yet!");
1752 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1753 Chain = Val.getValue(1);
1754 Flag = Val.getValue(2);
1755 if (DAG.getTargetLoweringInfo().isLittleEndian())
1756 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1758 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1761 // Otherwise, if the return value was promoted, truncate it to the
1762 // appropriate type.
1763 if (RegVT == ValueVT)
1766 if (MVT::isInteger(RegVT))
1767 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1769 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1772 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1773 /// specified value into the registers specified by this object. This uses
1774 /// Chain/Flag as the input and updates them for the output Chain/Flag.
1775 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1776 SDOperand &Chain, SDOperand &Flag) const {
1777 if (Regs.size() == 1) {
1778 // If there is a single register and the types differ, this must be
1780 if (RegVT != ValueVT) {
1781 if (MVT::isInteger(RegVT))
1782 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1784 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1786 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1787 Flag = Chain.getValue(1);
1789 std::vector<unsigned> R(Regs);
1790 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1791 std::reverse(R.begin(), R.end());
1793 for (unsigned i = 0, e = R.size(); i != e; ++i) {
1794 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1795 DAG.getConstant(i, MVT::i32));
1796 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1797 Flag = Chain.getValue(1);
1802 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1803 /// operand list. This adds the code marker and includes the number of
1804 /// values added into it.
1805 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1806 std::vector<SDOperand> &Ops) const {
1807 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1808 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1809 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1812 /// isAllocatableRegister - If the specified register is safe to allocate,
1813 /// i.e. it isn't a stack pointer or some other special register, return the
1814 /// register class for the register. Otherwise, return null.
1815 static const TargetRegisterClass *
1816 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1817 const TargetLowering &TLI, const MRegisterInfo *MRI) {
1818 MVT::ValueType FoundVT = MVT::Other;
1819 const TargetRegisterClass *FoundRC = 0;
1820 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1821 E = MRI->regclass_end(); RCI != E; ++RCI) {
1822 MVT::ValueType ThisVT = MVT::Other;
1824 const TargetRegisterClass *RC = *RCI;
1825 // If none of the the value types for this register class are valid, we
1826 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1827 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1829 if (TLI.isTypeLegal(*I)) {
1830 // If we have already found this register in a different register class,
1831 // choose the one with the largest VT specified. For example, on
1832 // PowerPC, we favor f64 register classes over f32.
1833 if (FoundVT == MVT::Other ||
1834 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1841 if (ThisVT == MVT::Other) continue;
1843 // NOTE: This isn't ideal. In particular, this might allocate the
1844 // frame pointer in functions that need it (due to them not being taken
1845 // out of allocation, because a variable sized allocation hasn't been seen
1846 // yet). This is a slight code pessimization, but should still work.
1847 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1848 E = RC->allocation_order_end(MF); I != E; ++I)
1850 // We found a matching register class. Keep looking at others in case
1851 // we find one with larger registers that this physreg is also in.
1860 RegsForValue SelectionDAGLowering::
1861 GetRegistersForValue(const std::string &ConstrCode,
1862 MVT::ValueType VT, bool isOutReg, bool isInReg,
1863 std::set<unsigned> &OutputRegs,
1864 std::set<unsigned> &InputRegs) {
1865 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1866 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1867 std::vector<unsigned> Regs;
1869 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1870 MVT::ValueType RegVT;
1871 MVT::ValueType ValueVT = VT;
1873 if (PhysReg.first) {
1874 if (VT == MVT::Other)
1875 ValueVT = *PhysReg.second->vt_begin();
1878 // This is a explicit reference to a physical register.
1879 Regs.push_back(PhysReg.first);
1881 // If this is an expanded reference, add the rest of the regs to Regs.
1883 RegVT = *PhysReg.second->vt_begin();
1884 TargetRegisterClass::iterator I = PhysReg.second->begin();
1885 TargetRegisterClass::iterator E = PhysReg.second->end();
1886 for (; *I != PhysReg.first; ++I)
1887 assert(I != E && "Didn't find reg!");
1889 // Already added the first reg.
1891 for (; NumRegs; --NumRegs, ++I) {
1892 assert(I != E && "Ran out of registers to allocate!");
1896 return RegsForValue(Regs, RegVT, ValueVT);
1899 // This is a reference to a register class. Allocate NumRegs consecutive,
1900 // available, registers from the class.
1901 std::vector<unsigned> RegClassRegs =
1902 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1904 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1905 MachineFunction &MF = *CurMBB->getParent();
1906 unsigned NumAllocated = 0;
1907 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1908 unsigned Reg = RegClassRegs[i];
1909 // See if this register is available.
1910 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1911 (isInReg && InputRegs.count(Reg))) { // Already used.
1912 // Make sure we find consecutive registers.
1917 // Check to see if this register is allocatable (i.e. don't give out the
1919 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1921 // Make sure we find consecutive registers.
1926 // Okay, this register is good, we can use it.
1929 // If we allocated enough consecutive
1930 if (NumAllocated == NumRegs) {
1931 unsigned RegStart = (i-NumAllocated)+1;
1932 unsigned RegEnd = i+1;
1933 // Mark all of the allocated registers used.
1934 for (unsigned i = RegStart; i != RegEnd; ++i) {
1935 unsigned Reg = RegClassRegs[i];
1936 Regs.push_back(Reg);
1937 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1938 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1941 return RegsForValue(Regs, *RC->vt_begin(), VT);
1945 // Otherwise, we couldn't allocate enough registers for this.
1946 return RegsForValue();
1950 /// visitInlineAsm - Handle a call to an InlineAsm object.
1952 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1953 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1955 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1958 // Note, we treat inline asms both with and without side-effects as the same.
1959 // If an inline asm doesn't have side effects and doesn't access memory, we
1960 // could not choose to not chain it.
1961 bool hasSideEffects = IA->hasSideEffects();
1963 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
1964 std::vector<MVT::ValueType> ConstraintVTs;
1966 /// AsmNodeOperands - A list of pairs. The first element is a register, the
1967 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
1968 /// if it is a def of that register.
1969 std::vector<SDOperand> AsmNodeOperands;
1970 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
1971 AsmNodeOperands.push_back(AsmStr);
1973 SDOperand Chain = getRoot();
1976 // We fully assign registers here at isel time. This is not optimal, but
1977 // should work. For register classes that correspond to LLVM classes, we
1978 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
1979 // over the constraints, collecting fixed registers that we know we can't use.
1980 std::set<unsigned> OutputRegs, InputRegs;
1982 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
1983 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
1984 std::string &ConstraintCode = Constraints[i].Codes[0];
1986 MVT::ValueType OpVT;
1988 // Compute the value type for each operand and add it to ConstraintVTs.
1989 switch (Constraints[i].Type) {
1990 case InlineAsm::isOutput:
1991 if (!Constraints[i].isIndirectOutput) {
1992 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
1993 OpVT = TLI.getValueType(I.getType());
1995 const Type *OpTy = I.getOperand(OpNum)->getType();
1996 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
1997 OpNum++; // Consumes a call operand.
2000 case InlineAsm::isInput:
2001 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2002 OpNum++; // Consumes a call operand.
2004 case InlineAsm::isClobber:
2009 ConstraintVTs.push_back(OpVT);
2011 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2012 continue; // Not assigned a fixed reg.
2014 // Build a list of regs that this operand uses. This always has a single
2015 // element for promoted/expanded operands.
2016 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2018 OutputRegs, InputRegs);
2020 switch (Constraints[i].Type) {
2021 case InlineAsm::isOutput:
2022 // We can't assign any other output to this register.
2023 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2024 // If this is an early-clobber output, it cannot be assigned to the same
2025 // value as the input reg.
2026 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2027 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2029 case InlineAsm::isInput:
2030 // We can't assign any other input to this register.
2031 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2033 case InlineAsm::isClobber:
2034 // Clobbered regs cannot be used as inputs or outputs.
2035 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2036 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2041 // Loop over all of the inputs, copying the operand values into the
2042 // appropriate registers and processing the output regs.
2043 RegsForValue RetValRegs;
2044 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2047 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2048 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2049 std::string &ConstraintCode = Constraints[i].Codes[0];
2051 switch (Constraints[i].Type) {
2052 case InlineAsm::isOutput: {
2053 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2054 if (ConstraintCode.size() == 1) // not a physreg name.
2055 CTy = TLI.getConstraintType(ConstraintCode[0]);
2057 if (CTy == TargetLowering::C_Memory) {
2059 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2061 // Check that the operand (the address to store to) isn't a float.
2062 if (!MVT::isInteger(InOperandVal.getValueType()))
2063 assert(0 && "MATCH FAIL!");
2065 if (!Constraints[i].isIndirectOutput)
2066 assert(0 && "MATCH FAIL!");
2068 OpNum++; // Consumes a call operand.
2070 // Extend/truncate to the right pointer type if needed.
2071 MVT::ValueType PtrType = TLI.getPointerTy();
2072 if (InOperandVal.getValueType() < PtrType)
2073 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2074 else if (InOperandVal.getValueType() > PtrType)
2075 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2077 // Add information to the INLINEASM node to know about this output.
2078 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2079 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2080 AsmNodeOperands.push_back(InOperandVal);
2084 // Otherwise, this is a register output.
2085 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2087 // If this is an early-clobber output, or if there is an input
2088 // constraint that matches this, we need to reserve the input register
2089 // so no other inputs allocate to it.
2090 bool UsesInputRegister = false;
2091 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2092 UsesInputRegister = true;
2094 // Copy the output from the appropriate register. Find a register that
2097 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2098 true, UsesInputRegister,
2099 OutputRegs, InputRegs);
2100 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2102 if (!Constraints[i].isIndirectOutput) {
2103 assert(RetValRegs.Regs.empty() &&
2104 "Cannot have multiple output constraints yet!");
2105 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2108 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2109 I.getOperand(OpNum)));
2110 OpNum++; // Consumes a call operand.
2113 // Add information to the INLINEASM node to know that this register is
2115 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2118 case InlineAsm::isInput: {
2119 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2120 OpNum++; // Consumes a call operand.
2122 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2123 // If this is required to match an output register we have already set,
2124 // just use its register.
2125 unsigned OperandNo = atoi(ConstraintCode.c_str());
2127 // Scan until we find the definition we already emitted of this operand.
2128 // When we find it, create a RegsForValue operand.
2129 unsigned CurOp = 2; // The first operand.
2130 for (; OperandNo; --OperandNo) {
2131 // Advance to the next operand.
2133 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2134 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2135 "Skipped past definitions?");
2136 CurOp += (NumOps>>3)+1;
2140 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2141 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2142 "Skipped past definitions?");
2144 // Add NumOps>>3 registers to MatchedRegs.
2145 RegsForValue MatchedRegs;
2146 MatchedRegs.ValueVT = InOperandVal.getValueType();
2147 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2148 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2149 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2150 MatchedRegs.Regs.push_back(Reg);
2153 // Use the produced MatchedRegs object to
2154 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2155 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2159 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2160 if (ConstraintCode.size() == 1) // not a physreg name.
2161 CTy = TLI.getConstraintType(ConstraintCode[0]);
2163 if (CTy == TargetLowering::C_Other) {
2164 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2165 assert(0 && "MATCH FAIL!");
2167 // Add information to the INLINEASM node to know about this input.
2168 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2169 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2170 AsmNodeOperands.push_back(InOperandVal);
2172 } else if (CTy == TargetLowering::C_Memory) {
2175 // Check that the operand isn't a float.
2176 if (!MVT::isInteger(InOperandVal.getValueType()))
2177 assert(0 && "MATCH FAIL!");
2179 // Extend/truncate to the right pointer type if needed.
2180 MVT::ValueType PtrType = TLI.getPointerTy();
2181 if (InOperandVal.getValueType() < PtrType)
2182 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2183 else if (InOperandVal.getValueType() > PtrType)
2184 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2186 // Add information to the INLINEASM node to know about this input.
2187 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2188 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2189 AsmNodeOperands.push_back(InOperandVal);
2193 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2195 // Copy the input into the appropriate registers.
2196 RegsForValue InRegs =
2197 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2198 false, true, OutputRegs, InputRegs);
2199 // FIXME: should be match fail.
2200 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2202 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2204 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2207 case InlineAsm::isClobber: {
2208 RegsForValue ClobberedRegs =
2209 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2210 OutputRegs, InputRegs);
2211 // Add the clobbered value to the operand list, so that the register
2212 // allocator is aware that the physreg got clobbered.
2213 if (!ClobberedRegs.Regs.empty())
2214 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2220 // Finish up input operands.
2221 AsmNodeOperands[0] = Chain;
2222 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2224 std::vector<MVT::ValueType> VTs;
2225 VTs.push_back(MVT::Other);
2226 VTs.push_back(MVT::Flag);
2227 Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
2228 Flag = Chain.getValue(1);
2230 // If this asm returns a register value, copy the result from that register
2231 // and set it as the value of the call.
2232 if (!RetValRegs.Regs.empty())
2233 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2235 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2237 // Process indirect outputs, first output all of the flagged copies out of
2239 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2240 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2241 Value *Ptr = IndirectStoresToEmit[i].second;
2242 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2243 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2246 // Emit the non-flagged stores from the physregs.
2247 std::vector<SDOperand> OutChains;
2248 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2249 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2250 StoresToEmit[i].first,
2251 getValue(StoresToEmit[i].second),
2252 DAG.getSrcValue(StoresToEmit[i].second)));
2253 if (!OutChains.empty())
2254 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
2259 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2260 SDOperand Src = getValue(I.getOperand(0));
2262 MVT::ValueType IntPtr = TLI.getPointerTy();
2264 if (IntPtr < Src.getValueType())
2265 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2266 else if (IntPtr > Src.getValueType())
2267 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2269 // Scale the source by the type size.
2270 uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType());
2271 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2272 Src, getIntPtrConstant(ElementSize));
2274 std::vector<std::pair<SDOperand, const Type*> > Args;
2275 Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
2277 std::pair<SDOperand,SDOperand> Result =
2278 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2279 DAG.getExternalSymbol("malloc", IntPtr),
2281 setValue(&I, Result.first); // Pointers always fit in registers
2282 DAG.setRoot(Result.second);
2285 void SelectionDAGLowering::visitFree(FreeInst &I) {
2286 std::vector<std::pair<SDOperand, const Type*> > Args;
2287 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2288 TLI.getTargetData().getIntPtrType()));
2289 MVT::ValueType IntPtr = TLI.getPointerTy();
2290 std::pair<SDOperand,SDOperand> Result =
2291 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2292 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2293 DAG.setRoot(Result.second);
2296 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2297 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2298 // instructions are special in various ways, which require special support to
2299 // insert. The specified MachineInstr is created but not inserted into any
2300 // basic blocks, and the scheduler passes ownership of it to this method.
2301 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2302 MachineBasicBlock *MBB) {
2303 std::cerr << "If a target marks an instruction with "
2304 "'usesCustomDAGSchedInserter', it must implement "
2305 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2310 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2311 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2312 getValue(I.getOperand(1)),
2313 DAG.getSrcValue(I.getOperand(1))));
2316 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2317 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2318 getValue(I.getOperand(0)),
2319 DAG.getSrcValue(I.getOperand(0)));
2321 DAG.setRoot(V.getValue(1));
2324 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2325 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2326 getValue(I.getOperand(1)),
2327 DAG.getSrcValue(I.getOperand(1))));
2330 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2331 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2332 getValue(I.getOperand(1)),
2333 getValue(I.getOperand(2)),
2334 DAG.getSrcValue(I.getOperand(1)),
2335 DAG.getSrcValue(I.getOperand(2))));
2338 /// TargetLowering::LowerArguments - This is the default LowerArguments
2339 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2340 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be removed.
2341 std::vector<SDOperand>
2342 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2343 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2344 std::vector<SDOperand> Ops;
2345 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2346 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2348 // Add one result value for each formal argument.
2349 std::vector<MVT::ValueType> RetVals;
2350 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2351 MVT::ValueType VT = getValueType(I->getType());
2353 switch (getTypeAction(VT)) {
2354 default: assert(0 && "Unknown type action!");
2356 RetVals.push_back(VT);
2359 RetVals.push_back(getTypeToTransformTo(VT));
2362 if (VT != MVT::Vector) {
2363 // If this is a large integer, it needs to be broken up into small
2364 // integers. Figure out what the destination type is and how many small
2365 // integers it turns into.
2366 MVT::ValueType NVT = getTypeToTransformTo(VT);
2367 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2368 for (unsigned i = 0; i != NumVals; ++i)
2369 RetVals.push_back(NVT);
2371 // Otherwise, this is a vector type. We only support legal vectors
2373 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2374 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2376 // Figure out if there is a Packed type corresponding to this Vector
2377 // type. If so, convert to the packed type.
2378 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2379 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2380 RetVals.push_back(TVT);
2382 assert(0 && "Don't support illegal by-val vector arguments yet!");
2389 if (RetVals.size() == 0)
2390 RetVals.push_back(MVT::isVoid);
2393 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
2395 // Set up the return result vector.
2398 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2399 MVT::ValueType VT = getValueType(I->getType());
2401 switch (getTypeAction(VT)) {
2402 default: assert(0 && "Unknown type action!");
2404 Ops.push_back(SDOperand(Result, i++));
2407 SDOperand Op(Result, i++);
2408 if (MVT::isInteger(VT)) {
2409 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2411 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2412 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2414 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2415 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2421 if (VT != MVT::Vector) {
2422 // If this is a large integer, it needs to be reassembled from small
2423 // integers. Figure out what the source elt type is and how many small
2425 MVT::ValueType NVT = getTypeToTransformTo(VT);
2426 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2428 SDOperand Lo = SDOperand(Result, i++);
2429 SDOperand Hi = SDOperand(Result, i++);
2431 if (!isLittleEndian())
2434 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2436 // Value scalarized into many values. Unimp for now.
2437 assert(0 && "Cannot expand i64 -> i16 yet!");
2440 // Otherwise, this is a vector type. We only support legal vectors
2442 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2443 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2445 // Figure out if there is a Packed type corresponding to this Vector
2446 // type. If so, convert to the packed type.
2447 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2448 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2449 Ops.push_back(SDOperand(Result, i++));
2451 assert(0 && "Don't support illegal by-val vector arguments yet!");
2460 // It is always conservatively correct for llvm.returnaddress and
2461 // llvm.frameaddress to return 0.
2462 std::pair<SDOperand, SDOperand>
2463 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2464 unsigned Depth, SelectionDAG &DAG) {
2465 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2468 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2469 assert(0 && "LowerOperation not implemented for this target!");
2474 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2475 SelectionDAG &DAG) {
2476 assert(0 && "CustomPromoteOperation not implemented for this target!");
2481 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2482 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2483 std::pair<SDOperand,SDOperand> Result =
2484 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2485 setValue(&I, Result.first);
2486 DAG.setRoot(Result.second);
2489 /// getMemsetValue - Vectorized representation of the memset value
2491 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2492 SelectionDAG &DAG) {
2493 MVT::ValueType CurVT = VT;
2494 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2495 uint64_t Val = C->getValue() & 255;
2497 while (CurVT != MVT::i8) {
2498 Val = (Val << Shift) | Val;
2500 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2502 return DAG.getConstant(Val, VT);
2504 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2506 while (CurVT != MVT::i8) {
2508 DAG.getNode(ISD::OR, VT,
2509 DAG.getNode(ISD::SHL, VT, Value,
2510 DAG.getConstant(Shift, MVT::i8)), Value);
2512 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2519 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2520 /// used when a memcpy is turned into a memset when the source is a constant
2522 static SDOperand getMemsetStringVal(MVT::ValueType VT,
2523 SelectionDAG &DAG, TargetLowering &TLI,
2524 std::string &Str, unsigned Offset) {
2525 MVT::ValueType CurVT = VT;
2527 unsigned MSB = getSizeInBits(VT) / 8;
2528 if (TLI.isLittleEndian())
2529 Offset = Offset + MSB - 1;
2530 for (unsigned i = 0; i != MSB; ++i) {
2531 Val = (Val << 8) | Str[Offset];
2532 Offset += TLI.isLittleEndian() ? -1 : 1;
2534 return DAG.getConstant(Val, VT);
2537 /// getMemBasePlusOffset - Returns base and offset node for the
2538 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2539 SelectionDAG &DAG, TargetLowering &TLI) {
2540 MVT::ValueType VT = Base.getValueType();
2541 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2544 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2545 /// to replace the memset / memcpy is below the threshold. It also returns the
2546 /// types of the sequence of memory ops to perform memset / memcpy.
2547 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2548 unsigned Limit, uint64_t Size,
2549 unsigned Align, TargetLowering &TLI) {
2552 if (TLI.allowsUnalignedMemoryAccesses()) {
2555 switch (Align & 7) {
2571 MVT::ValueType LVT = MVT::i64;
2572 while (!TLI.isTypeLegal(LVT))
2573 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2574 assert(MVT::isInteger(LVT));
2579 unsigned NumMemOps = 0;
2581 unsigned VTSize = getSizeInBits(VT) / 8;
2582 while (VTSize > Size) {
2583 VT = (MVT::ValueType)((unsigned)VT - 1);
2586 assert(MVT::isInteger(VT));
2588 if (++NumMemOps > Limit)
2590 MemOps.push_back(VT);
2597 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2598 SDOperand Op1 = getValue(I.getOperand(1));
2599 SDOperand Op2 = getValue(I.getOperand(2));
2600 SDOperand Op3 = getValue(I.getOperand(3));
2601 SDOperand Op4 = getValue(I.getOperand(4));
2602 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2603 if (Align == 0) Align = 1;
2605 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2606 std::vector<MVT::ValueType> MemOps;
2608 // Expand memset / memcpy to a series of load / store ops
2609 // if the size operand falls below a certain threshold.
2610 std::vector<SDOperand> OutChains;
2612 default: break; // Do nothing for now.
2614 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2615 Size->getValue(), Align, TLI)) {
2616 unsigned NumMemOps = MemOps.size();
2617 unsigned Offset = 0;
2618 for (unsigned i = 0; i < NumMemOps; i++) {
2619 MVT::ValueType VT = MemOps[i];
2620 unsigned VTSize = getSizeInBits(VT) / 8;
2621 SDOperand Value = getMemsetValue(Op2, VT, DAG);
2622 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
2624 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2625 DAG.getSrcValue(I.getOperand(1), Offset));
2626 OutChains.push_back(Store);
2633 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2634 Size->getValue(), Align, TLI)) {
2635 unsigned NumMemOps = MemOps.size();
2636 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2637 GlobalAddressSDNode *G = NULL;
2639 bool CopyFromStr = false;
2641 if (Op2.getOpcode() == ISD::GlobalAddress)
2642 G = cast<GlobalAddressSDNode>(Op2);
2643 else if (Op2.getOpcode() == ISD::ADD &&
2644 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2645 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2646 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2647 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2650 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2652 Str = GV->getStringValue(false);
2660 for (unsigned i = 0; i < NumMemOps; i++) {
2661 MVT::ValueType VT = MemOps[i];
2662 unsigned VTSize = getSizeInBits(VT) / 8;
2663 SDOperand Value, Chain, Store;
2666 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2669 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2670 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2671 DAG.getSrcValue(I.getOperand(1), DstOff));
2673 Value = DAG.getLoad(VT, getRoot(),
2674 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2675 DAG.getSrcValue(I.getOperand(2), SrcOff));
2676 Chain = Value.getValue(1);
2678 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2679 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2680 DAG.getSrcValue(I.getOperand(1), DstOff));
2682 OutChains.push_back(Store);
2691 if (!OutChains.empty()) {
2692 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
2697 std::vector<SDOperand> Ops;
2698 Ops.push_back(getRoot());
2703 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
2706 //===----------------------------------------------------------------------===//
2707 // SelectionDAGISel code
2708 //===----------------------------------------------------------------------===//
2710 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2711 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2714 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2715 // FIXME: we only modify the CFG to split critical edges. This
2716 // updates dom and loop info.
2720 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
2721 /// casting to the type of GEPI.
2722 static Value *InsertGEPComputeCode(Value *&V, BasicBlock *BB, Instruction *GEPI,
2723 Value *Ptr, Value *PtrOffset) {
2724 if (V) return V; // Already computed.
2726 BasicBlock::iterator InsertPt;
2727 if (BB == GEPI->getParent()) {
2728 // If insert into the GEP's block, insert right after the GEP.
2732 // Otherwise, insert at the top of BB, after any PHI nodes
2733 InsertPt = BB->begin();
2734 while (isa<PHINode>(InsertPt)) ++InsertPt;
2737 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
2738 // BB so that there is only one value live across basic blocks (the cast
2740 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
2741 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
2742 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
2744 // Add the offset, cast it to the right type.
2745 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
2746 Ptr = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
2751 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
2752 /// selection, we want to be a bit careful about some things. In particular, if
2753 /// we have a GEP instruction that is used in a different block than it is
2754 /// defined, the addressing expression of the GEP cannot be folded into loads or
2755 /// stores that use it. In this case, decompose the GEP and move constant
2756 /// indices into blocks that use it.
2757 static void OptimizeGEPExpression(GetElementPtrInst *GEPI,
2758 const TargetData &TD) {
2759 // If this GEP is only used inside the block it is defined in, there is no
2760 // need to rewrite it.
2761 bool isUsedOutsideDefBB = false;
2762 BasicBlock *DefBB = GEPI->getParent();
2763 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
2765 if (cast<Instruction>(*UI)->getParent() != DefBB) {
2766 isUsedOutsideDefBB = true;
2770 if (!isUsedOutsideDefBB) return;
2772 // If this GEP has no non-zero constant indices, there is nothing we can do,
2774 bool hasConstantIndex = false;
2775 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
2776 E = GEPI->op_end(); OI != E; ++OI) {
2777 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI))
2778 if (CI->getRawValue()) {
2779 hasConstantIndex = true;
2783 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
2784 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0))) return;
2786 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
2787 // constant offset (which we now know is non-zero) and deal with it later.
2788 uint64_t ConstantOffset = 0;
2789 const Type *UIntPtrTy = TD.getIntPtrType();
2790 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
2791 const Type *Ty = GEPI->getOperand(0)->getType();
2793 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
2794 E = GEPI->op_end(); OI != E; ++OI) {
2796 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2797 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
2799 ConstantOffset += TD.getStructLayout(StTy)->MemberOffsets[Field];
2800 Ty = StTy->getElementType(Field);
2802 Ty = cast<SequentialType>(Ty)->getElementType();
2804 // Handle constant subscripts.
2805 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2806 if (CI->getRawValue() == 0) continue;
2808 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
2809 ConstantOffset += (int64_t)TD.getTypeSize(Ty)*CSI->getValue();
2811 ConstantOffset+=TD.getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
2815 // Ptr = Ptr + Idx * ElementSize;
2817 // Cast Idx to UIntPtrTy if needed.
2818 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
2820 uint64_t ElementSize = TD.getTypeSize(Ty);
2821 // Mask off bits that should not be set.
2822 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
2823 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
2825 // Multiply by the element size and add to the base.
2826 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
2827 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
2831 // Make sure that the offset fits in uintptr_t.
2832 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
2833 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
2835 // Okay, we have now emitted all of the variable index parts to the BB that
2836 // the GEP is defined in. Loop over all of the using instructions, inserting
2837 // an "add Ptr, ConstantOffset" into each block that uses it and update the
2838 // instruction to use the newly computed value, making GEPI dead. When the
2839 // user is a load or store instruction address, we emit the add into the user
2840 // block, otherwise we use a canonical version right next to the gep (these
2841 // won't be foldable as addresses, so we might as well share the computation).
2843 std::map<BasicBlock*,Value*> InsertedExprs;
2844 while (!GEPI->use_empty()) {
2845 Instruction *User = cast<Instruction>(GEPI->use_back());
2847 // If this use is not foldable into the addressing mode, use a version
2848 // emitted in the GEP block.
2850 if (!isa<LoadInst>(User) &&
2851 (!isa<StoreInst>(User) || User->getOperand(0) == GEPI)) {
2852 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
2855 // Otherwise, insert the code in the User's block so it can be folded into
2856 // any users in that block.
2857 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
2858 User->getParent(), GEPI,
2861 User->replaceUsesOfWith(GEPI, NewVal);
2864 // Finally, the GEP is dead, remove it.
2865 GEPI->eraseFromParent();
2868 bool SelectionDAGISel::runOnFunction(Function &Fn) {
2869 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
2870 RegMap = MF.getSSARegMap();
2871 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
2873 // First, split all critical edges for PHI nodes with incoming values that are
2874 // constants, this way the load of the constant into a vreg will not be placed
2875 // into MBBs that are used some other way.
2877 // In this pass we also look for GEP instructions that are used across basic
2878 // blocks and rewrites them to improve basic-block-at-a-time selection.
2880 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
2882 BasicBlock::iterator BBI;
2883 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
2884 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
2885 if (isa<Constant>(PN->getIncomingValue(i)))
2886 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
2888 for (BasicBlock::iterator E = BB->end(); BBI != E; )
2889 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(BBI++))
2890 OptimizeGEPExpression(GEPI, TLI.getTargetData());
2893 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
2895 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
2896 SelectBasicBlock(I, MF, FuncInfo);
2902 SDOperand SelectionDAGISel::
2903 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
2904 SDOperand Op = SDL.getValue(V);
2905 assert((Op.getOpcode() != ISD::CopyFromReg ||
2906 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
2907 "Copy from a reg to the same reg!");
2909 // If this type is not legal, we must make sure to not create an invalid
2911 MVT::ValueType SrcVT = Op.getValueType();
2912 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
2913 SelectionDAG &DAG = SDL.DAG;
2914 if (SrcVT == DestVT) {
2915 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
2916 } else if (SrcVT == MVT::Vector) {
2917 // Handle copies from generic vectors to registers.
2918 MVT::ValueType PTyElementVT, PTyLegalElementVT;
2919 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
2920 PTyElementVT, PTyLegalElementVT);
2922 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
2923 // MVT::Vector type.
2924 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
2925 DAG.getConstant(NE, MVT::i32),
2926 DAG.getValueType(PTyElementVT));
2928 // Loop over all of the elements of the resultant vector,
2929 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
2930 // copying them into output registers.
2931 std::vector<SDOperand> OutChains;
2932 SDOperand Root = SDL.getRoot();
2933 for (unsigned i = 0; i != NE; ++i) {
2934 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
2935 Op, DAG.getConstant(i, MVT::i32));
2936 if (PTyElementVT == PTyLegalElementVT) {
2937 // Elements are legal.
2938 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
2939 } else if (PTyLegalElementVT > PTyElementVT) {
2940 // Elements are promoted.
2941 if (MVT::isFloatingPoint(PTyLegalElementVT))
2942 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
2944 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
2945 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
2947 // Elements are expanded.
2948 // The src value is expanded into multiple registers.
2949 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
2950 Elt, DAG.getConstant(0, MVT::i32));
2951 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
2952 Elt, DAG.getConstant(1, MVT::i32));
2953 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
2954 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
2957 return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
2958 } else if (SrcVT < DestVT) {
2959 // The src value is promoted to the register.
2960 if (MVT::isFloatingPoint(SrcVT))
2961 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
2963 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
2964 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
2966 // The src value is expanded into multiple registers.
2967 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
2968 Op, DAG.getConstant(0, MVT::i32));
2969 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
2970 Op, DAG.getConstant(1, MVT::i32));
2971 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
2972 return DAG.getCopyToReg(Op, Reg+1, Hi);
2976 void SelectionDAGISel::
2977 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
2978 std::vector<SDOperand> &UnorderedChains) {
2979 // If this is the entry block, emit arguments.
2980 Function &F = *BB->getParent();
2981 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
2982 SDOperand OldRoot = SDL.DAG.getRoot();
2983 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
2986 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
2988 if (!AI->use_empty()) {
2989 SDL.setValue(AI, Args[a]);
2991 MVT::ValueType VT = TLI.getValueType(AI->getType());
2992 if (VT == MVT::Vector) {
2993 // Insert a VBIT_CONVERT between the FORMAL_ARGUMENT node and its uses.
2994 // Or else legalizer will balk.
2995 BasicBlock::iterator InsertPt = BB->begin();
2996 Value *NewVal = new CastInst(AI, AI->getType(), AI->getName(), InsertPt);
2997 for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end();
2999 Instruction *User = cast<Instruction>(*UI);
3001 User->replaceUsesOfWith(AI, NewVal);
3004 // If this argument is live outside of the entry block, insert a copy from
3005 // whereever we got it to the vreg that other BB's will reference it as.
3006 if (FuncInfo.ValueMap.count(AI)) {
3008 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3009 UnorderedChains.push_back(Copy);
3013 // Next, if the function has live ins that need to be copied into vregs,
3014 // emit the copies now, into the top of the block.
3015 MachineFunction &MF = SDL.DAG.getMachineFunction();
3016 if (MF.livein_begin() != MF.livein_end()) {
3017 SSARegMap *RegMap = MF.getSSARegMap();
3018 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
3019 for (MachineFunction::livein_iterator LI = MF.livein_begin(),
3020 E = MF.livein_end(); LI != E; ++LI)
3022 MRI.copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
3023 LI->first, RegMap->getRegClass(LI->second));
3026 // Finally, if the target has anything special to do, allow it to do so.
3027 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3031 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3032 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3033 FunctionLoweringInfo &FuncInfo) {
3034 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3036 std::vector<SDOperand> UnorderedChains;
3038 // Lower any arguments needed in this block if this is the entry block.
3039 if (LLVMBB == &LLVMBB->getParent()->front())
3040 LowerArguments(LLVMBB, SDL, UnorderedChains);
3042 BB = FuncInfo.MBBMap[LLVMBB];
3043 SDL.setCurrentBasicBlock(BB);
3045 // Lower all of the non-terminator instructions.
3046 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3050 // Ensure that all instructions which are used outside of their defining
3051 // blocks are available as virtual registers.
3052 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3053 if (!I->use_empty() && !isa<PHINode>(I)) {
3054 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3055 if (VMI != FuncInfo.ValueMap.end())
3056 UnorderedChains.push_back(
3057 CopyValueToVirtualRegister(SDL, I, VMI->second));
3060 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3061 // ensure constants are generated when needed. Remember the virtual registers
3062 // that need to be added to the Machine PHI nodes as input. We cannot just
3063 // directly add them, because expansion might result in multiple MBB's for one
3064 // BB. As such, the start of the BB might correspond to a different MBB than
3068 // Emit constants only once even if used by multiple PHI nodes.
3069 std::map<Constant*, unsigned> ConstantsOut;
3071 // Check successor nodes PHI nodes that expect a constant to be available from
3073 TerminatorInst *TI = LLVMBB->getTerminator();
3074 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3075 BasicBlock *SuccBB = TI->getSuccessor(succ);
3076 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3079 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3080 // nodes and Machine PHI nodes, but the incoming operands have not been
3082 for (BasicBlock::iterator I = SuccBB->begin();
3083 (PN = dyn_cast<PHINode>(I)); ++I)
3084 if (!PN->use_empty()) {
3086 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3087 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3088 unsigned &RegOut = ConstantsOut[C];
3090 RegOut = FuncInfo.CreateRegForValue(C);
3091 UnorderedChains.push_back(
3092 CopyValueToVirtualRegister(SDL, C, RegOut));
3096 Reg = FuncInfo.ValueMap[PHIOp];
3098 assert(isa<AllocaInst>(PHIOp) &&
3099 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3100 "Didn't codegen value into a register!??");
3101 Reg = FuncInfo.CreateRegForValue(PHIOp);
3102 UnorderedChains.push_back(
3103 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
3107 // Remember that this register needs to added to the machine PHI node as
3108 // the input for this MBB.
3109 MVT::ValueType VT = TLI.getValueType(PN->getType());
3110 unsigned NumElements;
3111 if (VT != MVT::Vector)
3112 NumElements = TLI.getNumElements(VT);
3114 MVT::ValueType VT1,VT2;
3116 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3119 for (unsigned i = 0, e = NumElements; i != e; ++i)
3120 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3123 ConstantsOut.clear();
3125 // Turn all of the unordered chains into one factored node.
3126 if (!UnorderedChains.empty()) {
3127 SDOperand Root = SDL.getRoot();
3128 if (Root.getOpcode() != ISD::EntryToken) {
3129 unsigned i = 0, e = UnorderedChains.size();
3130 for (; i != e; ++i) {
3131 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3132 if (UnorderedChains[i].Val->getOperand(0) == Root)
3133 break; // Don't add the root if we already indirectly depend on it.
3137 UnorderedChains.push_back(Root);
3139 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
3142 // Lower the terminator after the copies are emitted.
3143 SDL.visit(*LLVMBB->getTerminator());
3145 // Copy over any CaseBlock records that may now exist due to SwitchInst
3146 // lowering, as well as any jump table information.
3147 SwitchCases.clear();
3148 SwitchCases = SDL.SwitchCases;
3151 // Make sure the root of the DAG is up-to-date.
3152 DAG.setRoot(SDL.getRoot());
3155 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3156 // Run the DAG combiner in pre-legalize mode.
3159 DEBUG(std::cerr << "Lowered selection DAG:\n");
3162 // Second step, hack on the DAG until it only uses operations and types that
3163 // the target supports.
3166 DEBUG(std::cerr << "Legalized selection DAG:\n");
3169 // Run the DAG combiner in post-legalize mode.
3172 if (ViewISelDAGs) DAG.viewGraph();
3174 // Third, instruction select all of the operations to machine code, adding the
3175 // code to the MachineBasicBlock.
3176 InstructionSelectBasicBlock(DAG);
3178 DEBUG(std::cerr << "Selected machine code:\n");
3182 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3183 FunctionLoweringInfo &FuncInfo) {
3184 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3186 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3189 // First step, lower LLVM code to some DAG. This DAG may use operations and
3190 // types that are not supported by the target.
3191 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3193 // Second step, emit the lowered DAG as machine code.
3194 CodeGenAndEmitDAG(DAG);
3197 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3198 // PHI nodes in successors.
3199 if (SwitchCases.empty() && JT.Reg == 0) {
3200 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3201 MachineInstr *PHI = PHINodesToUpdate[i].first;
3202 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3203 "This is not a machine PHI node that we are updating!");
3204 PHI->addRegOperand(PHINodesToUpdate[i].second);
3205 PHI->addMachineBasicBlockOperand(BB);
3210 // If the JumpTable record is filled in, then we need to emit a jump table.
3211 // Updating the PHI nodes is tricky in this case, since we need to determine
3212 // whether the PHI is a successor of the range check MBB or the jump table MBB
3214 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3215 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3217 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3218 MachineBasicBlock *RangeBB = BB;
3219 // Set the current basic block to the mbb we wish to insert the code into
3221 SDL.setCurrentBasicBlock(BB);
3223 SDL.visitJumpTable(JT);
3224 SDAG.setRoot(SDL.getRoot());
3225 CodeGenAndEmitDAG(SDAG);
3227 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3228 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3229 MachineBasicBlock *PHIBB = PHI->getParent();
3230 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3231 "This is not a machine PHI node that we are updating!");
3232 if (PHIBB == JT.Default || JT.SuccMBBs.find(PHIBB) != JT.SuccMBBs.end()) {
3233 PHIBB = (PHIBB == JT.Default) ? RangeBB : BB;
3234 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3235 PHI->addMachineBasicBlockOperand(PHIBB);
3241 // If we generated any switch lowering information, build and codegen any
3242 // additional DAGs necessary.
3243 for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3244 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3246 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3247 // Set the current basic block to the mbb we wish to insert the code into
3248 BB = SwitchCases[i].ThisBB;
3249 SDL.setCurrentBasicBlock(BB);
3251 SDL.visitSwitchCase(SwitchCases[i]);
3252 SDAG.setRoot(SDL.getRoot());
3253 CodeGenAndEmitDAG(SDAG);
3254 // Iterate over the phi nodes, if there is a phi node in a successor of this
3255 // block (for instance, the default block), then add a pair of operands to
3256 // the phi node for this block, as if we were coming from the original
3257 // BB before switch expansion.
3258 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3259 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3260 MachineBasicBlock *PHIBB = PHI->getParent();
3261 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3262 "This is not a machine PHI node that we are updating!");
3263 if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
3264 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3265 PHI->addMachineBasicBlockOperand(BB);
3271 //===----------------------------------------------------------------------===//
3272 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3273 /// target node in the graph.
3274 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3275 if (ViewSchedDAGs) DAG.viewGraph();
3276 ScheduleDAG *SL = NULL;
3278 switch (ISHeuristic) {
3279 default: assert(0 && "Unrecognized scheduling heuristic");
3280 case defaultScheduling:
3281 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
3282 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3284 assert(TLI.getSchedulingPreference() ==
3285 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
3286 SL = createBURRListDAGScheduler(DAG, BB);
3290 SL = createBFS_DAGScheduler(DAG, BB);
3292 case simpleScheduling:
3293 SL = createSimpleDAGScheduler(false, DAG, BB);
3295 case simpleNoItinScheduling:
3296 SL = createSimpleDAGScheduler(true, DAG, BB);
3298 case listSchedulingBURR:
3299 SL = createBURRListDAGScheduler(DAG, BB);
3301 case listSchedulingTD:
3302 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3309 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3310 return new HazardRecognizer();
3313 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3314 /// by tblgen. Others should not call it.
3315 void SelectionDAGISel::
3316 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3317 std::vector<SDOperand> InOps;
3318 std::swap(InOps, Ops);
3320 Ops.push_back(InOps[0]); // input chain.
3321 Ops.push_back(InOps[1]); // input asm string.
3323 const char *AsmStr = cast<ExternalSymbolSDNode>(InOps[1])->getSymbol();
3324 unsigned i = 2, e = InOps.size();
3325 if (InOps[e-1].getValueType() == MVT::Flag)
3326 --e; // Don't process a flag operand if it is here.
3329 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3330 if ((Flags & 7) != 4 /*MEM*/) {
3331 // Just skip over this operand, copying the operands verbatim.
3332 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3333 i += (Flags >> 3) + 1;
3335 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3336 // Otherwise, this is a memory operand. Ask the target to select it.
3337 std::vector<SDOperand> SelOps;
3338 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3339 std::cerr << "Could not match memory address. Inline asm failure!\n";
3343 // Add this to the output node.
3344 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3345 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3350 // Add the flag input back if present.
3351 if (e != InOps.size())
3352 Ops.push_back(InOps.back());