1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetData.h"
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/Support/MathExtras.h"
24 TargetLowering::TargetLowering(TargetMachine &tm)
25 : TM(tm), TD(TM.getTargetData()) {
26 assert(ISD::BUILTIN_OP_END <= 156 &&
27 "Fixed size array in TargetLowering is not large enough!");
28 // All operations default to being supported.
29 memset(OpActions, 0, sizeof(OpActions));
30 memset(LoadXActions, 0, sizeof(LoadXActions));
31 memset(&StoreXActions, 0, sizeof(StoreXActions));
33 IsLittleEndian = TD->isLittleEndian();
34 UsesGlobalOffsetTable = false;
35 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
36 ShiftAmtHandling = Undefined;
37 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
38 memset(TargetDAGCombineArray, 0,
39 sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0]));
40 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
41 allowUnalignedMemoryAccesses = false;
42 UseUnderscoreSetJmpLongJmp = false;
43 IntDivIsCheap = false;
44 Pow2DivIsCheap = false;
45 StackPointerRegisterToSaveRestore = 0;
46 SchedPreferenceInfo = SchedulingForLatency;
51 TargetLowering::~TargetLowering() {}
53 /// setValueTypeAction - Set the action for a particular value type. This
54 /// assumes an action has not already been set for this value type.
55 static void SetValueTypeAction(MVT::ValueType VT,
56 TargetLowering::LegalizeAction Action,
58 MVT::ValueType *TransformToType,
59 TargetLowering::ValueTypeActionImpl &ValueTypeActions) {
60 ValueTypeActions.setTypeAction(VT, Action);
61 if (Action == TargetLowering::Promote) {
62 MVT::ValueType PromoteTo;
66 unsigned LargerReg = VT+1;
67 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) {
69 assert(MVT::isInteger((MVT::ValueType)LargerReg) &&
70 "Nothing to promote to??");
72 PromoteTo = (MVT::ValueType)LargerReg;
75 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) &&
76 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) &&
77 "Can only promote from int->int or fp->fp!");
78 assert(VT < PromoteTo && "Must promote to a larger type!");
79 TransformToType[VT] = PromoteTo;
80 } else if (Action == TargetLowering::Expand) {
81 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
82 "Cannot expand this type: target must support SOME integer reg!");
83 // Expand to the next smaller integer type!
84 TransformToType[VT] = (MVT::ValueType)(VT-1);
89 /// computeRegisterProperties - Once all of the register classes are added,
90 /// this allows us to compute derived properties we expose.
91 void TargetLowering::computeRegisterProperties() {
92 assert(MVT::LAST_VALUETYPE <= 32 &&
93 "Too many value types for ValueTypeActions to hold!");
95 // Everything defaults to one.
96 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
97 NumElementsForVT[i] = 1;
99 // Find the largest integer register class.
100 unsigned LargestIntReg = MVT::i128;
101 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
102 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
104 // Every integer value type larger than this largest register takes twice as
105 // many registers to represent as the previous ValueType.
106 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
107 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
108 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
110 // Inspect all of the ValueType's possible, deciding how to process them.
111 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
112 // If we are expanding this type, expand it!
113 if (getNumElements((MVT::ValueType)IntReg) != 1)
114 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
116 else if (!isTypeLegal((MVT::ValueType)IntReg))
117 // Otherwise, if we don't have native support, we must promote to a
119 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this,
120 TransformToType, ValueTypeActions);
122 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
124 // If the target does not have native support for F32, promote it to F64.
125 if (!isTypeLegal(MVT::f32))
126 SetValueTypeAction(MVT::f32, Promote, *this,
127 TransformToType, ValueTypeActions);
129 TransformToType[MVT::f32] = MVT::f32;
131 // Set MVT::Vector to always be Expanded
132 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
135 // Loop over all of the legal vector value types, specifying an identity type
137 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
138 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
139 if (isTypeLegal((MVT::ValueType)i))
140 TransformToType[i] = (MVT::ValueType)i;
143 assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
144 TransformToType[MVT::f64] = MVT::f64;
147 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
151 /// getPackedTypeBreakdown - Packed types are broken down into some number of
152 /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32
153 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
155 /// This method returns the number and type of the resultant breakdown.
157 unsigned TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
158 MVT::ValueType &PTyElementVT,
159 MVT::ValueType &PTyLegalElementVT) const {
160 // Figure out the right, legal destination reg to copy into.
161 unsigned NumElts = PTy->getNumElements();
162 MVT::ValueType EltTy = getValueType(PTy->getElementType());
164 unsigned NumVectorRegs = 1;
166 // Divide the input until we get to a supported size. This will always
167 // end with a scalar if the target doesn't support vectors.
168 while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) {
177 VT = getVectorType(EltTy, NumElts);
181 MVT::ValueType DestVT = getTypeToTransformTo(VT);
182 PTyLegalElementVT = DestVT;
184 // Value is expanded, e.g. i64 -> i16.
185 return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
187 // Otherwise, promotion or legal types use the same number of registers as
188 // the vector decimated to the appropriate level.
189 return NumVectorRegs;
195 //===----------------------------------------------------------------------===//
196 // Optimization Methods
197 //===----------------------------------------------------------------------===//
199 /// ShrinkDemandedConstant - Check to see if the specified operand of the
200 /// specified instruction is a constant integer. If so, check to see if there
201 /// are any bits set in the constant that are not demanded. If so, shrink the
202 /// constant and return true.
203 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
205 // FIXME: ISD::SELECT, ISD::SELECT_CC
206 switch(Op.getOpcode()) {
211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
212 if ((~Demanded & C->getValue()) != 0) {
213 MVT::ValueType VT = Op.getValueType();
214 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
215 DAG.getConstant(Demanded & C->getValue(),
217 return CombineTo(Op, New);
224 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
225 /// DemandedMask bits of the result of Op are ever used downstream. If we can
226 /// use this information to simplify Op, create a new simplified DAG node and
227 /// return true, returning the original and new nodes in Old and New. Otherwise,
228 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
229 /// the expression (used to simplify the caller). The KnownZero/One bits may
230 /// only be accurate for those bits in the DemandedMask.
231 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
234 TargetLoweringOpt &TLO,
235 unsigned Depth) const {
236 KnownZero = KnownOne = 0; // Don't know anything.
237 // Other users may use these bits.
238 if (!Op.Val->hasOneUse()) {
240 // If not at the root, Just compute the KnownZero/KnownOne bits to
241 // simplify things downstream.
242 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
245 // If this is the root being simplified, allow it to have multiple uses,
246 // just set the DemandedMask to all bits.
247 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
248 } else if (DemandedMask == 0) {
249 // Not demanding any bits from Op.
250 if (Op.getOpcode() != ISD::UNDEF)
251 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
253 } else if (Depth == 6) { // Limit search depth.
257 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
258 switch (Op.getOpcode()) {
260 // We know all of the bits for a constant!
261 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
262 KnownZero = ~KnownOne & DemandedMask;
263 return false; // Don't fall through, will infinitely loop.
265 // If the RHS is a constant, check to see if the LHS would be zero without
266 // using the bits from the RHS. Below, we use knowledge about the RHS to
267 // simplify the LHS, here we're using information from the LHS to simplify
269 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
270 uint64_t LHSZero, LHSOne;
271 ComputeMaskedBits(Op.getOperand(0), DemandedMask,
272 LHSZero, LHSOne, Depth+1);
273 // If the LHS already has zeros where RHSC does, this and is dead.
274 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
275 return TLO.CombineTo(Op, Op.getOperand(0));
276 // If any of the set bits in the RHS are known zero on the LHS, shrink
278 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
282 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
283 KnownOne, TLO, Depth+1))
285 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
286 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
287 KnownZero2, KnownOne2, TLO, Depth+1))
289 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
291 // If all of the demanded bits are known one on one side, return the other.
292 // These bits cannot contribute to the result of the 'and'.
293 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
294 return TLO.CombineTo(Op, Op.getOperand(0));
295 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
296 return TLO.CombineTo(Op, Op.getOperand(1));
297 // If all of the demanded bits in the inputs are known zeros, return zero.
298 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
299 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
300 // If the RHS is a constant, see if we can simplify it.
301 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
304 // Output known-1 bits are only known if set in both the LHS & RHS.
305 KnownOne &= KnownOne2;
306 // Output known-0 are known to be clear if zero in either the LHS | RHS.
307 KnownZero |= KnownZero2;
310 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
311 KnownOne, TLO, Depth+1))
313 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
314 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
315 KnownZero2, KnownOne2, TLO, Depth+1))
317 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
319 // If all of the demanded bits are known zero on one side, return the other.
320 // These bits cannot contribute to the result of the 'or'.
321 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
322 return TLO.CombineTo(Op, Op.getOperand(0));
323 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
324 return TLO.CombineTo(Op, Op.getOperand(1));
325 // If all of the potentially set bits on one side are known to be set on
326 // the other side, just use the 'other' side.
327 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
328 (DemandedMask & (~KnownZero)))
329 return TLO.CombineTo(Op, Op.getOperand(0));
330 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
331 (DemandedMask & (~KnownZero2)))
332 return TLO.CombineTo(Op, Op.getOperand(1));
333 // If the RHS is a constant, see if we can simplify it.
334 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
337 // Output known-0 bits are only known if clear in both the LHS & RHS.
338 KnownZero &= KnownZero2;
339 // Output known-1 are known to be set if set in either the LHS | RHS.
340 KnownOne |= KnownOne2;
343 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
344 KnownOne, TLO, Depth+1))
346 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
347 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
348 KnownOne2, TLO, Depth+1))
350 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
352 // If all of the demanded bits are known zero on one side, return the other.
353 // These bits cannot contribute to the result of the 'xor'.
354 if ((DemandedMask & KnownZero) == DemandedMask)
355 return TLO.CombineTo(Op, Op.getOperand(0));
356 if ((DemandedMask & KnownZero2) == DemandedMask)
357 return TLO.CombineTo(Op, Op.getOperand(1));
359 // Output known-0 bits are known if clear or set in both the LHS & RHS.
360 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
361 // Output known-1 are known to be set if set in only one of the LHS, RHS.
362 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
364 // If all of the unknown bits are known to be zero on one side or the other
365 // (but not both) turn this into an *inclusive* or.
366 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
367 if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut))
368 if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits)
369 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
372 // If all of the demanded bits on one side are known, and all of the set
373 // bits on that side are also known to be set on the other side, turn this
374 // into an AND, as we know the bits will be cleared.
375 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
376 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
377 if ((KnownOne & KnownOne2) == KnownOne) {
378 MVT::ValueType VT = Op.getValueType();
379 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
380 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
385 // If the RHS is a constant, see if we can simplify it.
386 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
387 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
390 KnownZero = KnownZeroOut;
391 KnownOne = KnownOneOut;
394 // If we know the result of a setcc has the top bits zero, use this info.
395 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
396 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
399 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
400 KnownOne, TLO, Depth+1))
402 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
403 KnownOne2, TLO, Depth+1))
405 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
406 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
408 // If the operands are constants, see if we can simplify them.
409 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
412 // Only known if known in both the LHS and RHS.
413 KnownOne &= KnownOne2;
414 KnownZero &= KnownZero2;
417 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
418 KnownOne, TLO, Depth+1))
420 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
421 KnownOne2, TLO, Depth+1))
423 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
424 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
426 // If the operands are constants, see if we can simplify them.
427 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
430 // Only known if known in both the LHS and RHS.
431 KnownOne &= KnownOne2;
432 KnownZero &= KnownZero2;
435 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
436 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(),
437 KnownZero, KnownOne, TLO, Depth+1))
439 KnownZero <<= SA->getValue();
440 KnownOne <<= SA->getValue();
441 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
445 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
446 MVT::ValueType VT = Op.getValueType();
447 unsigned ShAmt = SA->getValue();
449 // Compute the new bits that are at the top now.
450 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
451 if (SimplifyDemandedBits(Op.getOperand(0),
452 (DemandedMask << ShAmt) & TypeMask,
453 KnownZero, KnownOne, TLO, Depth+1))
455 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
456 KnownZero &= TypeMask;
457 KnownOne &= TypeMask;
461 uint64_t HighBits = (1ULL << ShAmt)-1;
462 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
463 KnownZero |= HighBits; // High bits known zero.
467 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
468 MVT::ValueType VT = Op.getValueType();
469 unsigned ShAmt = SA->getValue();
471 // Compute the new bits that are at the top now.
472 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
474 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
476 // If any of the demanded bits are produced by the sign extension, we also
477 // demand the input sign bit.
478 uint64_t HighBits = (1ULL << ShAmt)-1;
479 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
480 if (HighBits & DemandedMask)
481 InDemandedMask |= MVT::getIntVTSignBit(VT);
483 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
484 KnownZero, KnownOne, TLO, Depth+1))
486 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
487 KnownZero &= TypeMask;
488 KnownOne &= TypeMask;
492 // Handle the sign bits.
493 uint64_t SignBit = MVT::getIntVTSignBit(VT);
494 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
496 // If the input sign bit is known to be zero, or if none of the top bits
497 // are demanded, turn this into an unsigned shift right.
498 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
499 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
501 } else if (KnownOne & SignBit) { // New bits are known one.
502 KnownOne |= HighBits;
506 case ISD::SIGN_EXTEND_INREG: {
507 MVT::ValueType VT = Op.getValueType();
508 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
510 // Sign extension. Compute the demanded bits in the result that are not
511 // present in the input.
512 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
514 // If none of the extended bits are demanded, eliminate the sextinreg.
516 return TLO.CombineTo(Op, Op.getOperand(0));
518 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
519 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
521 // Since the sign extended bits are demanded, we know that the sign
523 InputDemandedBits |= InSignBit;
525 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
526 KnownZero, KnownOne, TLO, Depth+1))
528 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
530 // If the sign bit of the input is known set or clear, then we know the
531 // top bits of the result.
533 // If the input sign bit is known zero, convert this into a zero extension.
534 if (KnownZero & InSignBit)
535 return TLO.CombineTo(Op,
536 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
538 if (KnownOne & InSignBit) { // Input sign bit known set
540 KnownZero &= ~NewBits;
541 } else { // Input sign bit unknown
542 KnownZero &= ~NewBits;
543 KnownOne &= ~NewBits;
550 MVT::ValueType VT = Op.getValueType();
551 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
552 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
557 if (ISD::isZEXTLoad(Op.Val)) {
558 LoadSDNode *LD = cast<LoadSDNode>(Op);
559 MVT::ValueType VT = LD->getLoadedVT();
560 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
564 case ISD::ZERO_EXTEND: {
565 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
567 // If none of the top bits are demanded, convert this into an any_extend.
568 uint64_t NewBits = (~InMask) & DemandedMask;
570 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
574 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
575 KnownZero, KnownOne, TLO, Depth+1))
577 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
578 KnownZero |= NewBits;
581 case ISD::SIGN_EXTEND: {
582 MVT::ValueType InVT = Op.getOperand(0).getValueType();
583 uint64_t InMask = MVT::getIntVTBitMask(InVT);
584 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
585 uint64_t NewBits = (~InMask) & DemandedMask;
587 // If none of the top bits are demanded, convert this into an any_extend.
589 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
592 // Since some of the sign extended bits are demanded, we know that the sign
594 uint64_t InDemandedBits = DemandedMask & InMask;
595 InDemandedBits |= InSignBit;
597 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
598 KnownOne, TLO, Depth+1))
601 // If the sign bit is known zero, convert this to a zero extend.
602 if (KnownZero & InSignBit)
603 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
607 // If the sign bit is known one, the top bits match.
608 if (KnownOne & InSignBit) {
610 KnownZero &= ~NewBits;
611 } else { // Otherwise, top bits aren't known.
612 KnownOne &= ~NewBits;
613 KnownZero &= ~NewBits;
617 case ISD::ANY_EXTEND: {
618 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
619 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
620 KnownZero, KnownOne, TLO, Depth+1))
622 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
625 case ISD::TRUNCATE: {
626 // Simplify the input, using demanded bit information, and compute the known
627 // zero/one bits live out.
628 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
629 KnownZero, KnownOne, TLO, Depth+1))
632 // If the input is only used by this truncate, see if we can shrink it based
633 // on the known demanded bits.
634 if (Op.getOperand(0).Val->hasOneUse()) {
635 SDOperand In = Op.getOperand(0);
636 switch (In.getOpcode()) {
639 // Shrink SRL by a constant if none of the high bits shifted in are
641 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
642 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
643 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType());
644 HighBits >>= ShAmt->getValue();
646 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) &&
647 (DemandedMask & HighBits) == 0) {
648 // None of the shifted in bits are needed. Add a truncate of the
649 // shift input, then shift it.
650 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
653 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
654 NewTrunc, In.getOperand(1)));
661 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
662 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
663 KnownZero &= OutMask;
667 case ISD::AssertZext: {
668 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
669 uint64_t InMask = MVT::getIntVTBitMask(VT);
670 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
671 KnownZero, KnownOne, TLO, Depth+1))
673 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
674 KnownZero |= ~InMask & DemandedMask;
679 case ISD::INTRINSIC_WO_CHAIN:
680 case ISD::INTRINSIC_W_CHAIN:
681 case ISD::INTRINSIC_VOID:
682 // Just use ComputeMaskedBits to compute output bits.
683 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
687 // If we know the value of all of the demanded bits, return this as a
689 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
690 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
695 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
696 /// this predicate to simplify operations downstream. Mask is known to be zero
697 /// for bits that V cannot have.
698 bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask,
699 unsigned Depth) const {
700 uint64_t KnownZero, KnownOne;
701 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
702 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
703 return (KnownZero & Mask) == Mask;
706 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
707 /// known to be either zero or one and return them in the KnownZero/KnownOne
708 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
710 void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
711 uint64_t &KnownZero, uint64_t &KnownOne,
712 unsigned Depth) const {
713 KnownZero = KnownOne = 0; // Don't know anything.
714 if (Depth == 6 || Mask == 0)
715 return; // Limit search depth.
717 uint64_t KnownZero2, KnownOne2;
719 switch (Op.getOpcode()) {
721 // We know all of the bits for a constant!
722 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask;
723 KnownZero = ~KnownOne & Mask;
726 // If either the LHS or the RHS are Zero, the result is zero.
727 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
729 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
730 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
731 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
733 // Output known-1 bits are only known if set in both the LHS & RHS.
734 KnownOne &= KnownOne2;
735 // Output known-0 are known to be clear if zero in either the LHS | RHS.
736 KnownZero |= KnownZero2;
739 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
741 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
742 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
743 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
745 // Output known-0 bits are only known if clear in both the LHS & RHS.
746 KnownZero &= KnownZero2;
747 // Output known-1 are known to be set if set in either the LHS | RHS.
748 KnownOne |= KnownOne2;
751 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
752 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
753 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
754 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
756 // Output known-0 bits are known if clear or set in both the LHS & RHS.
757 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
758 // Output known-1 are known to be set if set in only one of the LHS, RHS.
759 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
760 KnownZero = KnownZeroOut;
764 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
765 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
766 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
767 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
769 // Only known if known in both the LHS and RHS.
770 KnownOne &= KnownOne2;
771 KnownZero &= KnownZero2;
774 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
775 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
776 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
777 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
779 // Only known if known in both the LHS and RHS.
780 KnownOne &= KnownOne2;
781 KnownZero &= KnownZero2;
784 // If we know the result of a setcc has the top bits zero, use this info.
785 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
786 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
789 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
790 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
791 ComputeMaskedBits(Op.getOperand(0), Mask >> SA->getValue(),
792 KnownZero, KnownOne, Depth+1);
793 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
794 KnownZero <<= SA->getValue();
795 KnownOne <<= SA->getValue();
796 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
800 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
801 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
802 MVT::ValueType VT = Op.getValueType();
803 unsigned ShAmt = SA->getValue();
805 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
806 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt) & TypeMask,
807 KnownZero, KnownOne, Depth+1);
808 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
809 KnownZero &= TypeMask;
810 KnownOne &= TypeMask;
814 uint64_t HighBits = (1ULL << ShAmt)-1;
815 HighBits <<= MVT::getSizeInBits(VT)-ShAmt;
816 KnownZero |= HighBits; // High bits known zero.
820 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
821 MVT::ValueType VT = Op.getValueType();
822 unsigned ShAmt = SA->getValue();
824 // Compute the new bits that are at the top now.
825 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
827 uint64_t InDemandedMask = (Mask << ShAmt) & TypeMask;
828 // If any of the demanded bits are produced by the sign extension, we also
829 // demand the input sign bit.
830 uint64_t HighBits = (1ULL << ShAmt)-1;
831 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
833 InDemandedMask |= MVT::getIntVTSignBit(VT);
835 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
837 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
838 KnownZero &= TypeMask;
839 KnownOne &= TypeMask;
843 // Handle the sign bits.
844 uint64_t SignBit = MVT::getIntVTSignBit(VT);
845 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
847 if (KnownZero & SignBit) {
848 KnownZero |= HighBits; // New bits are known zero.
849 } else if (KnownOne & SignBit) {
850 KnownOne |= HighBits; // New bits are known one.
854 case ISD::SIGN_EXTEND_INREG: {
855 MVT::ValueType VT = Op.getValueType();
856 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
858 // Sign extension. Compute the demanded bits in the result that are not
859 // present in the input.
860 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask;
862 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
863 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT);
865 // If the sign extended bits are demanded, we know that the sign
868 InputDemandedBits |= InSignBit;
870 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
871 KnownZero, KnownOne, Depth+1);
872 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
874 // If the sign bit of the input is known set or clear, then we know the
875 // top bits of the result.
876 if (KnownZero & InSignBit) { // Input sign bit known clear
877 KnownZero |= NewBits;
878 KnownOne &= ~NewBits;
879 } else if (KnownOne & InSignBit) { // Input sign bit known set
881 KnownZero &= ~NewBits;
882 } else { // Input sign bit unknown
883 KnownZero &= ~NewBits;
884 KnownOne &= ~NewBits;
891 MVT::ValueType VT = Op.getValueType();
892 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
893 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
898 if (ISD::isZEXTLoad(Op.Val)) {
899 LoadSDNode *LD = cast<LoadSDNode>(Op);
900 MVT::ValueType VT = LD->getLoadedVT();
901 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
905 case ISD::ZERO_EXTEND: {
906 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
907 uint64_t NewBits = (~InMask) & Mask;
908 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
910 KnownZero |= NewBits & Mask;
911 KnownOne &= ~NewBits;
914 case ISD::SIGN_EXTEND: {
915 MVT::ValueType InVT = Op.getOperand(0).getValueType();
916 unsigned InBits = MVT::getSizeInBits(InVT);
917 uint64_t InMask = MVT::getIntVTBitMask(InVT);
918 uint64_t InSignBit = 1ULL << (InBits-1);
919 uint64_t NewBits = (~InMask) & Mask;
920 uint64_t InDemandedBits = Mask & InMask;
922 // If any of the sign extended bits are demanded, we know that the sign
925 InDemandedBits |= InSignBit;
927 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero,
929 // If the sign bit is known zero or one, the top bits match.
930 if (KnownZero & InSignBit) {
931 KnownZero |= NewBits;
932 KnownOne &= ~NewBits;
933 } else if (KnownOne & InSignBit) {
935 KnownZero &= ~NewBits;
936 } else { // Otherwise, top bits aren't known.
937 KnownOne &= ~NewBits;
938 KnownZero &= ~NewBits;
942 case ISD::ANY_EXTEND: {
943 MVT::ValueType VT = Op.getOperand(0).getValueType();
944 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT),
945 KnownZero, KnownOne, Depth+1);
948 case ISD::TRUNCATE: {
949 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
950 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
951 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
952 KnownZero &= OutMask;
956 case ISD::AssertZext: {
957 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
958 uint64_t InMask = MVT::getIntVTBitMask(VT);
959 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
961 KnownZero |= (~InMask) & Mask;
965 // If either the LHS or the RHS are Zero, the result is zero.
966 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
967 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
968 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
969 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
971 // Output known-0 bits are known if clear or set in both the low clear bits
972 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
974 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
975 CountTrailingZeros_64(~KnownZero2));
977 KnownZero = (1ULL << KnownZeroOut) - 1;
982 ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0));
985 // We know that the top bits of C-X are clear if X contains less bits
986 // than C (i.e. no wrap-around can happen). For example, 20-X is
987 // positive if we can prove that X is >= 0 and < 16.
988 MVT::ValueType VT = CLHS->getValueType(0);
989 if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear
990 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
991 uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit
992 MaskV = ~MaskV & MVT::getIntVTBitMask(VT);
993 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1);
995 // If all of the MaskV bits are known to be zero, then we know the output
996 // top bits are zero, because we now know that the output is from [0-C].
997 if ((KnownZero & MaskV) == MaskV) {
998 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
999 KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero.
1000 KnownOne = 0; // No one bits known.
1002 KnownZero = KnownOne = 0; // Otherwise, nothing known.
1008 // Allow the target to implement this method for its nodes.
1009 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1010 case ISD::INTRINSIC_WO_CHAIN:
1011 case ISD::INTRINSIC_W_CHAIN:
1012 case ISD::INTRINSIC_VOID:
1013 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
1019 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1020 /// in Mask are known to be either zero or one and return them in the
1021 /// KnownZero/KnownOne bitsets.
1022 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1024 uint64_t &KnownZero,
1026 unsigned Depth) const {
1027 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1028 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1029 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1030 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1031 "Should use MaskedValueIsZero if you don't know whether Op"
1032 " is a target node!");
1037 /// ComputeNumSignBits - Return the number of times the sign bit of the
1038 /// register is replicated into the other bits. We know that at least 1 bit
1039 /// is always equal to the sign bit (itself), but other cases can give us
1040 /// information. For example, immediately after an "SRA X, 2", we know that
1041 /// the top 3 bits are all equal to each other, so we return 3.
1042 unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
1043 MVT::ValueType VT = Op.getValueType();
1044 assert(MVT::isInteger(VT) && "Invalid VT!");
1045 unsigned VTBits = MVT::getSizeInBits(VT);
1049 return 1; // Limit search depth.
1051 switch (Op.getOpcode()) {
1053 case ISD::AssertSext:
1054 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1055 return VTBits-Tmp+1;
1056 case ISD::AssertZext:
1057 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1060 case ISD::Constant: {
1061 uint64_t Val = cast<ConstantSDNode>(Op)->getValue();
1062 // If negative, invert the bits, then look at it.
1063 if (Val & MVT::getIntVTSignBit(VT))
1066 // Shift the bits so they are the leading bits in the int64_t.
1069 // Return # leading zeros. We use 'min' here in case Val was zero before
1070 // shifting. We don't want to return '64' as for an i32 "0".
1071 return std::min(VTBits, CountLeadingZeros_64(Val));
1074 case ISD::SIGN_EXTEND:
1075 Tmp = VTBits-MVT::getSizeInBits(Op.getOperand(0).getValueType());
1076 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
1078 case ISD::SIGN_EXTEND_INREG:
1079 // Max of the input and what this extends.
1080 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1083 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1084 return std::max(Tmp, Tmp2);
1087 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1088 // SRA X, C -> adds C sign bits.
1089 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1090 Tmp += C->getValue();
1091 if (Tmp > VTBits) Tmp = VTBits;
1095 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1096 // shl destroys sign bits.
1097 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1098 if (C->getValue() >= VTBits || // Bad shift.
1099 C->getValue() >= Tmp) break; // Shifted all sign bits out.
1100 return Tmp - C->getValue();
1105 case ISD::XOR: // NOT is handled here.
1106 // Logical binary ops preserve the number of sign bits.
1107 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1108 if (Tmp == 1) return 1; // Early out.
1109 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1110 return std::min(Tmp, Tmp2);
1113 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1114 if (Tmp == 1) return 1; // Early out.
1115 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1116 return std::min(Tmp, Tmp2);
1119 // If setcc returns 0/-1, all bits are sign bits.
1120 if (getSetCCResultContents() == ZeroOrNegativeOneSetCCResult)
1125 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1126 unsigned RotAmt = C->getValue() & (VTBits-1);
1128 // Handle rotate right by N like a rotate left by 32-N.
1129 if (Op.getOpcode() == ISD::ROTR)
1130 RotAmt = (VTBits-RotAmt) & (VTBits-1);
1132 // If we aren't rotating out all of the known-in sign bits, return the
1133 // number that are left. This handles rotl(sext(x), 1) for example.
1134 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1135 if (Tmp > RotAmt+1) return Tmp-RotAmt;
1139 // Add can have at most one carry bit. Thus we know that the output
1140 // is, at worst, one more bit than the inputs.
1141 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1142 if (Tmp == 1) return 1; // Early out.
1144 // Special case decrementing a value (ADD X, -1):
1145 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
1146 if (CRHS->isAllOnesValue()) {
1147 uint64_t KnownZero, KnownOne;
1148 uint64_t Mask = MVT::getIntVTBitMask(VT);
1149 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1151 // If the input is known to be 0 or 1, the output is 0/-1, which is all
1153 if ((KnownZero|1) == Mask)
1156 // If we are subtracting one from a positive number, there is no carry
1157 // out of the result.
1158 if (KnownZero & MVT::getIntVTSignBit(VT))
1162 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1163 if (Tmp2 == 1) return 1;
1164 return std::min(Tmp, Tmp2)-1;
1168 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1169 if (Tmp2 == 1) return 1;
1172 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
1173 if (CLHS->getValue() == 0) {
1174 uint64_t KnownZero, KnownOne;
1175 uint64_t Mask = MVT::getIntVTBitMask(VT);
1176 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1177 // If the input is known to be 0 or 1, the output is 0/-1, which is all
1179 if ((KnownZero|1) == Mask)
1182 // If the input is known to be positive (the sign bit is known clear),
1183 // the output of the NEG has the same number of sign bits as the input.
1184 if (KnownZero & MVT::getIntVTSignBit(VT))
1187 // Otherwise, we treat this like a SUB.
1190 // Sub can have at most one carry bit. Thus we know that the output
1191 // is, at worst, one more bit than the inputs.
1192 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1193 if (Tmp == 1) return 1; // Early out.
1194 return std::min(Tmp, Tmp2)-1;
1197 // FIXME: it's tricky to do anything useful for this, but it is an important
1198 // case for targets like X86.
1202 // Handle LOADX separately here. EXTLOAD case will fallthrough.
1203 if (Op.getOpcode() == ISD::LOAD) {
1204 LoadSDNode *LD = cast<LoadSDNode>(Op);
1205 unsigned ExtType = LD->getExtensionType();
1208 case ISD::SEXTLOAD: // '17' bits known
1209 Tmp = MVT::getSizeInBits(LD->getLoadedVT());
1210 return VTBits-Tmp+1;
1211 case ISD::ZEXTLOAD: // '16' bits known
1212 Tmp = MVT::getSizeInBits(LD->getLoadedVT());
1217 // Allow the target to implement this method for its nodes.
1218 if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1219 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1220 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1221 Op.getOpcode() == ISD::INTRINSIC_VOID) {
1222 unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth);
1223 if (NumBits > 1) return NumBits;
1226 // Finally, if we can prove that the top bits of the result are 0's or 1's,
1227 // use this information.
1228 uint64_t KnownZero, KnownOne;
1229 uint64_t Mask = MVT::getIntVTBitMask(VT);
1230 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
1232 uint64_t SignBit = MVT::getIntVTSignBit(VT);
1233 if (KnownZero & SignBit) { // SignBit is 0
1235 } else if (KnownOne & SignBit) { // SignBit is 1;
1242 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine
1243 // the number of identical bits in the top of the input value.
1246 // Return # leading zeros. We use 'min' here in case Val was zero before
1247 // shifting. We don't want to return '64' as for an i32 "0".
1248 return std::min(VTBits, CountLeadingZeros_64(Mask));
1253 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1254 /// targets that want to expose additional information about sign bits to the
1256 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
1257 unsigned Depth) const {
1258 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1259 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1260 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1261 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1262 "Should use ComputeNumSignBits if you don't know whether Op"
1263 " is a target node!");
1268 SDOperand TargetLowering::
1269 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1270 // Default implementation: no optimization.
1274 //===----------------------------------------------------------------------===//
1275 // Inline Assembler Implementation Methods
1276 //===----------------------------------------------------------------------===//
1278 TargetLowering::ConstraintType
1279 TargetLowering::getConstraintType(char ConstraintLetter) const {
1280 // FIXME: lots more standard ones to handle.
1281 switch (ConstraintLetter) {
1282 default: return C_Unknown;
1283 case 'r': return C_RegisterClass;
1285 case 'o': // offsetable
1286 case 'V': // not offsetable
1288 case 'i': // Simple Integer or Relocatable Constant
1289 case 'n': // Simple Integer
1290 case 's': // Relocatable Constant
1291 case 'I': // Target registers.
1303 /// isOperandValidForConstraint - Return the specified operand (possibly
1304 /// modified) if the specified SDOperand is valid for the specified target
1305 /// constraint letter, otherwise return null.
1306 SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op,
1307 char ConstraintLetter,
1308 SelectionDAG &DAG) {
1309 switch (ConstraintLetter) {
1310 default: return SDOperand(0,0);
1311 case 'i': // Simple Integer or Relocatable Constant
1312 case 'n': // Simple Integer
1313 case 's': // Relocatable Constant
1314 return Op; // FIXME: not right.
1318 std::vector<unsigned> TargetLowering::
1319 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1320 MVT::ValueType VT) const {
1321 return std::vector<unsigned>();
1325 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1326 getRegForInlineAsmConstraint(const std::string &Constraint,
1327 MVT::ValueType VT) const {
1328 if (Constraint[0] != '{')
1329 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1330 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1332 // Remove the braces from around the name.
1333 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1335 // Figure out which register class contains this reg.
1336 const MRegisterInfo *RI = TM.getRegisterInfo();
1337 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1338 E = RI->regclass_end(); RCI != E; ++RCI) {
1339 const TargetRegisterClass *RC = *RCI;
1341 // If none of the the value types for this register class are valid, we
1342 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1343 bool isLegal = false;
1344 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1346 if (isTypeLegal(*I)) {
1352 if (!isLegal) continue;
1354 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1356 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
1357 return std::make_pair(*I, RC);
1361 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1364 //===----------------------------------------------------------------------===//
1365 // Loop Strength Reduction hooks
1366 //===----------------------------------------------------------------------===//
1368 /// isLegalAddressImmediate - Return true if the integer value or
1369 /// GlobalValue can be used as the offset of the target addressing mode.
1370 bool TargetLowering::isLegalAddressImmediate(int64_t V) const {
1373 bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
1378 // Magic for divide replacement
1381 int64_t m; // magic number
1382 int64_t s; // shift amount
1386 uint64_t m; // magic number
1387 int64_t a; // add indicator
1388 int64_t s; // shift amount
1391 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1392 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1394 static ms magic32(int32_t d) {
1396 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
1397 const uint32_t two31 = 0x80000000U;
1401 t = two31 + ((uint32_t)d >> 31);
1402 anc = t - 1 - t%ad; // absolute value of nc
1403 p = 31; // initialize p
1404 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
1405 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1406 q2 = two31/ad; // initialize q2 = 2p/abs(d)
1407 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
1410 q1 = 2*q1; // update q1 = 2p/abs(nc)
1411 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1412 if (r1 >= anc) { // must be unsigned comparison
1416 q2 = 2*q2; // update q2 = 2p/abs(d)
1417 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1418 if (r2 >= ad) { // must be unsigned comparison
1423 } while (q1 < delta || (q1 == delta && r1 == 0));
1425 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
1426 if (d < 0) mag.m = -mag.m; // resulting magic number
1427 mag.s = p - 32; // resulting shift
1431 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1432 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1433 static mu magicu32(uint32_t d) {
1435 uint32_t nc, delta, q1, r1, q2, r2;
1437 magu.a = 0; // initialize "add" indicator
1439 p = 31; // initialize p
1440 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
1441 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
1442 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
1443 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
1446 if (r1 >= nc - r1 ) {
1447 q1 = 2*q1 + 1; // update q1
1448 r1 = 2*r1 - nc; // update r1
1451 q1 = 2*q1; // update q1
1452 r1 = 2*r1; // update r1
1454 if (r2 + 1 >= d - r2) {
1455 if (q2 >= 0x7FFFFFFF) magu.a = 1;
1456 q2 = 2*q2 + 1; // update q2
1457 r2 = 2*r2 + 1 - d; // update r2
1460 if (q2 >= 0x80000000) magu.a = 1;
1461 q2 = 2*q2; // update q2
1462 r2 = 2*r2 + 1; // update r2
1465 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
1466 magu.m = q2 + 1; // resulting magic number
1467 magu.s = p - 32; // resulting shift
1471 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1472 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1474 static ms magic64(int64_t d) {
1476 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
1477 const uint64_t two63 = 9223372036854775808ULL; // 2^63
1480 ad = d >= 0 ? d : -d;
1481 t = two63 + ((uint64_t)d >> 63);
1482 anc = t - 1 - t%ad; // absolute value of nc
1483 p = 63; // initialize p
1484 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
1485 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1486 q2 = two63/ad; // initialize q2 = 2p/abs(d)
1487 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
1490 q1 = 2*q1; // update q1 = 2p/abs(nc)
1491 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1492 if (r1 >= anc) { // must be unsigned comparison
1496 q2 = 2*q2; // update q2 = 2p/abs(d)
1497 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1498 if (r2 >= ad) { // must be unsigned comparison
1503 } while (q1 < delta || (q1 == delta && r1 == 0));
1506 if (d < 0) mag.m = -mag.m; // resulting magic number
1507 mag.s = p - 64; // resulting shift
1511 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1512 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1513 static mu magicu64(uint64_t d)
1516 uint64_t nc, delta, q1, r1, q2, r2;
1518 magu.a = 0; // initialize "add" indicator
1520 p = 63; // initialize p
1521 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
1522 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
1523 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
1524 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
1527 if (r1 >= nc - r1 ) {
1528 q1 = 2*q1 + 1; // update q1
1529 r1 = 2*r1 - nc; // update r1
1532 q1 = 2*q1; // update q1
1533 r1 = 2*r1; // update r1
1535 if (r2 + 1 >= d - r2) {
1536 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
1537 q2 = 2*q2 + 1; // update q2
1538 r2 = 2*r2 + 1 - d; // update r2
1541 if (q2 >= 0x8000000000000000ull) magu.a = 1;
1542 q2 = 2*q2; // update q2
1543 r2 = 2*r2 + 1; // update r2
1546 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
1547 magu.m = q2 + 1; // resulting magic number
1548 magu.s = p - 64; // resulting shift
1552 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
1553 /// return a DAG expression to select that will generate the same value by
1554 /// multiplying by a magic number. See:
1555 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1556 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
1557 std::vector<SDNode*>* Created) const {
1558 MVT::ValueType VT = N->getValueType(0);
1560 // Check to see if we can do this.
1561 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1562 return SDOperand(); // BuildSDIV only operates on i32 or i64
1563 if (!isOperationLegal(ISD::MULHS, VT))
1564 return SDOperand(); // Make sure the target supports MULHS.
1566 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
1567 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
1569 // Multiply the numerator (operand 0) by the magic value
1570 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
1571 DAG.getConstant(magics.m, VT));
1572 // If d > 0 and m < 0, add the numerator
1573 if (d > 0 && magics.m < 0) {
1574 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
1576 Created->push_back(Q.Val);
1578 // If d < 0 and m > 0, subtract the numerator.
1579 if (d < 0 && magics.m > 0) {
1580 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
1582 Created->push_back(Q.Val);
1584 // Shift right algebraic if shift value is nonzero
1586 Q = DAG.getNode(ISD::SRA, VT, Q,
1587 DAG.getConstant(magics.s, getShiftAmountTy()));
1589 Created->push_back(Q.Val);
1591 // Extract the sign bit and add it to the quotient
1593 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
1594 getShiftAmountTy()));
1596 Created->push_back(T.Val);
1597 return DAG.getNode(ISD::ADD, VT, Q, T);
1600 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
1601 /// return a DAG expression to select that will generate the same value by
1602 /// multiplying by a magic number. See:
1603 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1604 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
1605 std::vector<SDNode*>* Created) const {
1606 MVT::ValueType VT = N->getValueType(0);
1608 // Check to see if we can do this.
1609 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1610 return SDOperand(); // BuildUDIV only operates on i32 or i64
1611 if (!isOperationLegal(ISD::MULHU, VT))
1612 return SDOperand(); // Make sure the target supports MULHU.
1614 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1615 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
1617 // Multiply the numerator (operand 0) by the magic value
1618 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
1619 DAG.getConstant(magics.m, VT));
1621 Created->push_back(Q.Val);
1623 if (magics.a == 0) {
1624 return DAG.getNode(ISD::SRL, VT, Q,
1625 DAG.getConstant(magics.s, getShiftAmountTy()));
1627 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
1629 Created->push_back(NPQ.Val);
1630 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
1631 DAG.getConstant(1, getShiftAmountTy()));
1633 Created->push_back(NPQ.Val);
1634 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
1636 Created->push_back(NPQ.Val);
1637 return DAG.getNode(ISD::SRL, VT, NPQ,
1638 DAG.getConstant(magics.s-1, getShiftAmountTy()));