1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtarget.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineJumpTableInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
34 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
35 bool isLocal = GV->hasLocalLinkage();
36 bool isDeclaration = GV->isDeclaration();
37 // FIXME: what should we do for protected and internal visibility?
38 // For variables, is internal different from hidden?
39 bool isHidden = GV->hasHiddenVisibility();
41 if (reloc == Reloc::PIC_) {
42 if (isLocal || isHidden)
43 return TLSModel::LocalDynamic;
45 return TLSModel::GeneralDynamic;
47 if (!isDeclaration || isHidden)
48 return TLSModel::LocalExec;
50 return TLSModel::InitialExec;
55 /// InitLibcallNames - Set default libcall names.
57 static void InitLibcallNames(const char **Names) {
58 Names[RTLIB::SHL_I16] = "__ashlhi3";
59 Names[RTLIB::SHL_I32] = "__ashlsi3";
60 Names[RTLIB::SHL_I64] = "__ashldi3";
61 Names[RTLIB::SHL_I128] = "__ashlti3";
62 Names[RTLIB::SRL_I16] = "__lshrhi3";
63 Names[RTLIB::SRL_I32] = "__lshrsi3";
64 Names[RTLIB::SRL_I64] = "__lshrdi3";
65 Names[RTLIB::SRL_I128] = "__lshrti3";
66 Names[RTLIB::SRA_I16] = "__ashrhi3";
67 Names[RTLIB::SRA_I32] = "__ashrsi3";
68 Names[RTLIB::SRA_I64] = "__ashrdi3";
69 Names[RTLIB::SRA_I128] = "__ashrti3";
70 Names[RTLIB::MUL_I8] = "__mulqi3";
71 Names[RTLIB::MUL_I16] = "__mulhi3";
72 Names[RTLIB::MUL_I32] = "__mulsi3";
73 Names[RTLIB::MUL_I64] = "__muldi3";
74 Names[RTLIB::MUL_I128] = "__multi3";
75 Names[RTLIB::SDIV_I8] = "__divqi3";
76 Names[RTLIB::SDIV_I16] = "__divhi3";
77 Names[RTLIB::SDIV_I32] = "__divsi3";
78 Names[RTLIB::SDIV_I64] = "__divdi3";
79 Names[RTLIB::SDIV_I128] = "__divti3";
80 Names[RTLIB::UDIV_I8] = "__udivqi3";
81 Names[RTLIB::UDIV_I16] = "__udivhi3";
82 Names[RTLIB::UDIV_I32] = "__udivsi3";
83 Names[RTLIB::UDIV_I64] = "__udivdi3";
84 Names[RTLIB::UDIV_I128] = "__udivti3";
85 Names[RTLIB::SREM_I8] = "__modqi3";
86 Names[RTLIB::SREM_I16] = "__modhi3";
87 Names[RTLIB::SREM_I32] = "__modsi3";
88 Names[RTLIB::SREM_I64] = "__moddi3";
89 Names[RTLIB::SREM_I128] = "__modti3";
90 Names[RTLIB::UREM_I8] = "__umodqi3";
91 Names[RTLIB::UREM_I16] = "__umodhi3";
92 Names[RTLIB::UREM_I32] = "__umodsi3";
93 Names[RTLIB::UREM_I64] = "__umoddi3";
94 Names[RTLIB::UREM_I128] = "__umodti3";
95 Names[RTLIB::NEG_I32] = "__negsi2";
96 Names[RTLIB::NEG_I64] = "__negdi2";
97 Names[RTLIB::ADD_F32] = "__addsf3";
98 Names[RTLIB::ADD_F64] = "__adddf3";
99 Names[RTLIB::ADD_F80] = "__addxf3";
100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
101 Names[RTLIB::SUB_F32] = "__subsf3";
102 Names[RTLIB::SUB_F64] = "__subdf3";
103 Names[RTLIB::SUB_F80] = "__subxf3";
104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
105 Names[RTLIB::MUL_F32] = "__mulsf3";
106 Names[RTLIB::MUL_F64] = "__muldf3";
107 Names[RTLIB::MUL_F80] = "__mulxf3";
108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
111 Names[RTLIB::DIV_F80] = "__divxf3";
112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
113 Names[RTLIB::REM_F32] = "fmodf";
114 Names[RTLIB::REM_F64] = "fmod";
115 Names[RTLIB::REM_F80] = "fmodl";
116 Names[RTLIB::REM_PPCF128] = "fmodl";
117 Names[RTLIB::POWI_F32] = "__powisf2";
118 Names[RTLIB::POWI_F64] = "__powidf2";
119 Names[RTLIB::POWI_F80] = "__powixf2";
120 Names[RTLIB::POWI_PPCF128] = "__powitf2";
121 Names[RTLIB::SQRT_F32] = "sqrtf";
122 Names[RTLIB::SQRT_F64] = "sqrt";
123 Names[RTLIB::SQRT_F80] = "sqrtl";
124 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
125 Names[RTLIB::LOG_F32] = "logf";
126 Names[RTLIB::LOG_F64] = "log";
127 Names[RTLIB::LOG_F80] = "logl";
128 Names[RTLIB::LOG_PPCF128] = "logl";
129 Names[RTLIB::LOG2_F32] = "log2f";
130 Names[RTLIB::LOG2_F64] = "log2";
131 Names[RTLIB::LOG2_F80] = "log2l";
132 Names[RTLIB::LOG2_PPCF128] = "log2l";
133 Names[RTLIB::LOG10_F32] = "log10f";
134 Names[RTLIB::LOG10_F64] = "log10";
135 Names[RTLIB::LOG10_F80] = "log10l";
136 Names[RTLIB::LOG10_PPCF128] = "log10l";
137 Names[RTLIB::EXP_F32] = "expf";
138 Names[RTLIB::EXP_F64] = "exp";
139 Names[RTLIB::EXP_F80] = "expl";
140 Names[RTLIB::EXP_PPCF128] = "expl";
141 Names[RTLIB::EXP2_F32] = "exp2f";
142 Names[RTLIB::EXP2_F64] = "exp2";
143 Names[RTLIB::EXP2_F80] = "exp2l";
144 Names[RTLIB::EXP2_PPCF128] = "exp2l";
145 Names[RTLIB::SIN_F32] = "sinf";
146 Names[RTLIB::SIN_F64] = "sin";
147 Names[RTLIB::SIN_F80] = "sinl";
148 Names[RTLIB::SIN_PPCF128] = "sinl";
149 Names[RTLIB::COS_F32] = "cosf";
150 Names[RTLIB::COS_F64] = "cos";
151 Names[RTLIB::COS_F80] = "cosl";
152 Names[RTLIB::COS_PPCF128] = "cosl";
153 Names[RTLIB::POW_F32] = "powf";
154 Names[RTLIB::POW_F64] = "pow";
155 Names[RTLIB::POW_F80] = "powl";
156 Names[RTLIB::POW_PPCF128] = "powl";
157 Names[RTLIB::CEIL_F32] = "ceilf";
158 Names[RTLIB::CEIL_F64] = "ceil";
159 Names[RTLIB::CEIL_F80] = "ceill";
160 Names[RTLIB::CEIL_PPCF128] = "ceill";
161 Names[RTLIB::TRUNC_F32] = "truncf";
162 Names[RTLIB::TRUNC_F64] = "trunc";
163 Names[RTLIB::TRUNC_F80] = "truncl";
164 Names[RTLIB::TRUNC_PPCF128] = "truncl";
165 Names[RTLIB::RINT_F32] = "rintf";
166 Names[RTLIB::RINT_F64] = "rint";
167 Names[RTLIB::RINT_F80] = "rintl";
168 Names[RTLIB::RINT_PPCF128] = "rintl";
169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
170 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
173 Names[RTLIB::FLOOR_F32] = "floorf";
174 Names[RTLIB::FLOOR_F64] = "floor";
175 Names[RTLIB::FLOOR_F80] = "floorl";
176 Names[RTLIB::FLOOR_PPCF128] = "floorl";
177 Names[RTLIB::COPYSIGN_F32] = "copysignf";
178 Names[RTLIB::COPYSIGN_F64] = "copysign";
179 Names[RTLIB::COPYSIGN_F80] = "copysignl";
180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
245 Names[RTLIB::OEQ_F32] = "__eqsf2";
246 Names[RTLIB::OEQ_F64] = "__eqdf2";
247 Names[RTLIB::UNE_F32] = "__nesf2";
248 Names[RTLIB::UNE_F64] = "__nedf2";
249 Names[RTLIB::OGE_F32] = "__gesf2";
250 Names[RTLIB::OGE_F64] = "__gedf2";
251 Names[RTLIB::OLT_F32] = "__ltsf2";
252 Names[RTLIB::OLT_F64] = "__ltdf2";
253 Names[RTLIB::OLE_F32] = "__lesf2";
254 Names[RTLIB::OLE_F64] = "__ledf2";
255 Names[RTLIB::OGT_F32] = "__gtsf2";
256 Names[RTLIB::OGT_F64] = "__gtdf2";
257 Names[RTLIB::UO_F32] = "__unordsf2";
258 Names[RTLIB::UO_F64] = "__unorddf2";
259 Names[RTLIB::O_F32] = "__unordsf2";
260 Names[RTLIB::O_F64] = "__unorddf2";
261 Names[RTLIB::MEMCPY] = "memcpy";
262 Names[RTLIB::MEMMOVE] = "memmove";
263 Names[RTLIB::MEMSET] = "memset";
264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
267 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
269 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
270 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
271 CCs[i] = CallingConv::C;
275 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
276 /// UNKNOWN_LIBCALL if there is none.
277 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
278 if (OpVT == MVT::f32) {
279 if (RetVT == MVT::f64)
280 return FPEXT_F32_F64;
283 return UNKNOWN_LIBCALL;
286 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
287 /// UNKNOWN_LIBCALL if there is none.
288 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
289 if (RetVT == MVT::f32) {
290 if (OpVT == MVT::f64)
291 return FPROUND_F64_F32;
292 if (OpVT == MVT::f80)
293 return FPROUND_F80_F32;
294 if (OpVT == MVT::ppcf128)
295 return FPROUND_PPCF128_F32;
296 } else if (RetVT == MVT::f64) {
297 if (OpVT == MVT::f80)
298 return FPROUND_F80_F64;
299 if (OpVT == MVT::ppcf128)
300 return FPROUND_PPCF128_F64;
303 return UNKNOWN_LIBCALL;
306 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
307 /// UNKNOWN_LIBCALL if there is none.
308 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
309 if (OpVT == MVT::f32) {
310 if (RetVT == MVT::i8)
311 return FPTOSINT_F32_I8;
312 if (RetVT == MVT::i16)
313 return FPTOSINT_F32_I16;
314 if (RetVT == MVT::i32)
315 return FPTOSINT_F32_I32;
316 if (RetVT == MVT::i64)
317 return FPTOSINT_F32_I64;
318 if (RetVT == MVT::i128)
319 return FPTOSINT_F32_I128;
320 } else if (OpVT == MVT::f64) {
321 if (RetVT == MVT::i8)
322 return FPTOSINT_F64_I8;
323 if (RetVT == MVT::i16)
324 return FPTOSINT_F64_I16;
325 if (RetVT == MVT::i32)
326 return FPTOSINT_F64_I32;
327 if (RetVT == MVT::i64)
328 return FPTOSINT_F64_I64;
329 if (RetVT == MVT::i128)
330 return FPTOSINT_F64_I128;
331 } else if (OpVT == MVT::f80) {
332 if (RetVT == MVT::i32)
333 return FPTOSINT_F80_I32;
334 if (RetVT == MVT::i64)
335 return FPTOSINT_F80_I64;
336 if (RetVT == MVT::i128)
337 return FPTOSINT_F80_I128;
338 } else if (OpVT == MVT::ppcf128) {
339 if (RetVT == MVT::i32)
340 return FPTOSINT_PPCF128_I32;
341 if (RetVT == MVT::i64)
342 return FPTOSINT_PPCF128_I64;
343 if (RetVT == MVT::i128)
344 return FPTOSINT_PPCF128_I128;
346 return UNKNOWN_LIBCALL;
349 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
350 /// UNKNOWN_LIBCALL if there is none.
351 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
352 if (OpVT == MVT::f32) {
353 if (RetVT == MVT::i8)
354 return FPTOUINT_F32_I8;
355 if (RetVT == MVT::i16)
356 return FPTOUINT_F32_I16;
357 if (RetVT == MVT::i32)
358 return FPTOUINT_F32_I32;
359 if (RetVT == MVT::i64)
360 return FPTOUINT_F32_I64;
361 if (RetVT == MVT::i128)
362 return FPTOUINT_F32_I128;
363 } else if (OpVT == MVT::f64) {
364 if (RetVT == MVT::i8)
365 return FPTOUINT_F64_I8;
366 if (RetVT == MVT::i16)
367 return FPTOUINT_F64_I16;
368 if (RetVT == MVT::i32)
369 return FPTOUINT_F64_I32;
370 if (RetVT == MVT::i64)
371 return FPTOUINT_F64_I64;
372 if (RetVT == MVT::i128)
373 return FPTOUINT_F64_I128;
374 } else if (OpVT == MVT::f80) {
375 if (RetVT == MVT::i32)
376 return FPTOUINT_F80_I32;
377 if (RetVT == MVT::i64)
378 return FPTOUINT_F80_I64;
379 if (RetVT == MVT::i128)
380 return FPTOUINT_F80_I128;
381 } else if (OpVT == MVT::ppcf128) {
382 if (RetVT == MVT::i32)
383 return FPTOUINT_PPCF128_I32;
384 if (RetVT == MVT::i64)
385 return FPTOUINT_PPCF128_I64;
386 if (RetVT == MVT::i128)
387 return FPTOUINT_PPCF128_I128;
389 return UNKNOWN_LIBCALL;
392 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
393 /// UNKNOWN_LIBCALL if there is none.
394 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
395 if (OpVT == MVT::i32) {
396 if (RetVT == MVT::f32)
397 return SINTTOFP_I32_F32;
398 else if (RetVT == MVT::f64)
399 return SINTTOFP_I32_F64;
400 else if (RetVT == MVT::f80)
401 return SINTTOFP_I32_F80;
402 else if (RetVT == MVT::ppcf128)
403 return SINTTOFP_I32_PPCF128;
404 } else if (OpVT == MVT::i64) {
405 if (RetVT == MVT::f32)
406 return SINTTOFP_I64_F32;
407 else if (RetVT == MVT::f64)
408 return SINTTOFP_I64_F64;
409 else if (RetVT == MVT::f80)
410 return SINTTOFP_I64_F80;
411 else if (RetVT == MVT::ppcf128)
412 return SINTTOFP_I64_PPCF128;
413 } else if (OpVT == MVT::i128) {
414 if (RetVT == MVT::f32)
415 return SINTTOFP_I128_F32;
416 else if (RetVT == MVT::f64)
417 return SINTTOFP_I128_F64;
418 else if (RetVT == MVT::f80)
419 return SINTTOFP_I128_F80;
420 else if (RetVT == MVT::ppcf128)
421 return SINTTOFP_I128_PPCF128;
423 return UNKNOWN_LIBCALL;
426 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
427 /// UNKNOWN_LIBCALL if there is none.
428 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
429 if (OpVT == MVT::i32) {
430 if (RetVT == MVT::f32)
431 return UINTTOFP_I32_F32;
432 else if (RetVT == MVT::f64)
433 return UINTTOFP_I32_F64;
434 else if (RetVT == MVT::f80)
435 return UINTTOFP_I32_F80;
436 else if (RetVT == MVT::ppcf128)
437 return UINTTOFP_I32_PPCF128;
438 } else if (OpVT == MVT::i64) {
439 if (RetVT == MVT::f32)
440 return UINTTOFP_I64_F32;
441 else if (RetVT == MVT::f64)
442 return UINTTOFP_I64_F64;
443 else if (RetVT == MVT::f80)
444 return UINTTOFP_I64_F80;
445 else if (RetVT == MVT::ppcf128)
446 return UINTTOFP_I64_PPCF128;
447 } else if (OpVT == MVT::i128) {
448 if (RetVT == MVT::f32)
449 return UINTTOFP_I128_F32;
450 else if (RetVT == MVT::f64)
451 return UINTTOFP_I128_F64;
452 else if (RetVT == MVT::f80)
453 return UINTTOFP_I128_F80;
454 else if (RetVT == MVT::ppcf128)
455 return UINTTOFP_I128_PPCF128;
457 return UNKNOWN_LIBCALL;
460 /// InitCmpLibcallCCs - Set default comparison libcall CC.
462 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
463 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
464 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
465 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
466 CCs[RTLIB::UNE_F32] = ISD::SETNE;
467 CCs[RTLIB::UNE_F64] = ISD::SETNE;
468 CCs[RTLIB::OGE_F32] = ISD::SETGE;
469 CCs[RTLIB::OGE_F64] = ISD::SETGE;
470 CCs[RTLIB::OLT_F32] = ISD::SETLT;
471 CCs[RTLIB::OLT_F64] = ISD::SETLT;
472 CCs[RTLIB::OLE_F32] = ISD::SETLE;
473 CCs[RTLIB::OLE_F64] = ISD::SETLE;
474 CCs[RTLIB::OGT_F32] = ISD::SETGT;
475 CCs[RTLIB::OGT_F64] = ISD::SETGT;
476 CCs[RTLIB::UO_F32] = ISD::SETNE;
477 CCs[RTLIB::UO_F64] = ISD::SETNE;
478 CCs[RTLIB::O_F32] = ISD::SETEQ;
479 CCs[RTLIB::O_F64] = ISD::SETEQ;
482 /// NOTE: The constructor takes ownership of TLOF.
483 TargetLowering::TargetLowering(const TargetMachine &tm,
484 const TargetLoweringObjectFile *tlof)
485 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
486 // All operations default to being supported.
487 memset(OpActions, 0, sizeof(OpActions));
488 memset(LoadExtActions, 0, sizeof(LoadExtActions));
489 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
490 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
491 memset(CondCodeActions, 0, sizeof(CondCodeActions));
493 // Set default actions for various operations.
494 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
495 // Default all indexed load / store to expand.
496 for (unsigned IM = (unsigned)ISD::PRE_INC;
497 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
498 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
499 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
502 // These operations default to expand.
503 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
504 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
507 // Most targets ignore the @llvm.prefetch intrinsic.
508 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
510 // ConstantFP nodes default to expand. Targets can either change this to
511 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
512 // to optimize expansions for certain constants.
513 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
514 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
515 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
517 // These library functions default to expand.
518 setOperationAction(ISD::FLOG , MVT::f64, Expand);
519 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
520 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
521 setOperationAction(ISD::FEXP , MVT::f64, Expand);
522 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
523 setOperationAction(ISD::FLOG , MVT::f32, Expand);
524 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
525 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
526 setOperationAction(ISD::FEXP , MVT::f32, Expand);
527 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
529 // Default ISD::TRAP to expand (which turns it into abort).
530 setOperationAction(ISD::TRAP, MVT::Other, Expand);
532 IsLittleEndian = TD->isLittleEndian();
533 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
534 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
535 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
536 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
537 benefitFromCodePlacementOpt = false;
538 UseUnderscoreSetJmp = false;
539 UseUnderscoreLongJmp = false;
540 SelectIsExpensive = false;
541 IntDivIsCheap = false;
542 Pow2DivIsCheap = false;
543 StackPointerRegisterToSaveRestore = 0;
544 ExceptionPointerRegister = 0;
545 ExceptionSelectorRegister = 0;
546 BooleanContents = UndefinedBooleanContent;
547 SchedPreferenceInfo = SchedulingForLatency;
549 JumpBufAlignment = 0;
550 IfCvtBlockSizeLimit = 2;
551 IfCvtDupBlockSizeLimit = 0;
552 PrefLoopAlignment = 0;
554 InitLibcallNames(LibcallRoutineNames);
555 InitCmpLibcallCCs(CmpLibcallCCs);
556 InitLibcallCallingConvs(LibcallCallingConvs);
559 TargetLowering::~TargetLowering() {
563 /// canOpTrap - Returns true if the operation can trap for the value type.
564 /// VT must be a legal type.
565 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
566 assert(isTypeLegal(VT));
581 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
582 unsigned &NumIntermediates,
584 TargetLowering* TLI) {
585 // Figure out the right, legal destination reg to copy into.
586 unsigned NumElts = VT.getVectorNumElements();
587 MVT EltTy = VT.getVectorElementType();
589 unsigned NumVectorRegs = 1;
591 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
592 // could break down into LHS/RHS like LegalizeDAG does.
593 if (!isPowerOf2_32(NumElts)) {
594 NumVectorRegs = NumElts;
598 // Divide the input until we get to a supported size. This will always
599 // end with a scalar if the target doesn't support vectors.
600 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
605 NumIntermediates = NumVectorRegs;
607 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
608 if (!TLI->isTypeLegal(NewVT))
610 IntermediateVT = NewVT;
612 EVT DestVT = TLI->getRegisterType(NewVT);
614 if (EVT(DestVT).bitsLT(NewVT)) {
615 // Value is expanded, e.g. i64 -> i16.
616 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
618 // Otherwise, promotion or legal types use the same number of registers as
619 // the vector decimated to the appropriate level.
620 return NumVectorRegs;
626 /// computeRegisterProperties - Once all of the register classes are added,
627 /// this allows us to compute derived properties we expose.
628 void TargetLowering::computeRegisterProperties() {
629 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
630 "Too many value types for ValueTypeActions to hold!");
632 // Everything defaults to needing one register.
633 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
634 NumRegistersForVT[i] = 1;
635 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
637 // ...except isVoid, which doesn't need any registers.
638 NumRegistersForVT[MVT::isVoid] = 0;
640 // Find the largest integer register class.
641 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
642 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
643 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
645 // Every integer value type larger than this largest register takes twice as
646 // many registers to represent as the previous ValueType.
647 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
648 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
649 if (!ExpandedVT.isInteger())
651 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
652 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
653 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
654 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
657 // Inspect all of the ValueType's smaller than the largest integer
658 // register to see which ones need promotion.
659 unsigned LegalIntReg = LargestIntReg;
660 for (unsigned IntReg = LargestIntReg - 1;
661 IntReg >= (unsigned)MVT::i1; --IntReg) {
662 EVT IVT = (MVT::SimpleValueType)IntReg;
663 if (isTypeLegal(IVT)) {
664 LegalIntReg = IntReg;
666 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
667 (MVT::SimpleValueType)LegalIntReg;
668 ValueTypeActions.setTypeAction(IVT, Promote);
672 // ppcf128 type is really two f64's.
673 if (!isTypeLegal(MVT::ppcf128)) {
674 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
675 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
676 TransformToType[MVT::ppcf128] = MVT::f64;
677 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
680 // Decide how to handle f64. If the target does not have native f64 support,
681 // expand it to i64 and we will be generating soft float library calls.
682 if (!isTypeLegal(MVT::f64)) {
683 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
684 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
685 TransformToType[MVT::f64] = MVT::i64;
686 ValueTypeActions.setTypeAction(MVT::f64, Expand);
689 // Decide how to handle f32. If the target does not have native support for
690 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
691 if (!isTypeLegal(MVT::f32)) {
692 if (isTypeLegal(MVT::f64)) {
693 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
694 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
695 TransformToType[MVT::f32] = MVT::f64;
696 ValueTypeActions.setTypeAction(MVT::f32, Promote);
698 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
699 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
700 TransformToType[MVT::f32] = MVT::i32;
701 ValueTypeActions.setTypeAction(MVT::f32, Expand);
705 // Loop over all of the vector value types to see which need transformations.
706 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
707 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
708 MVT VT = (MVT::SimpleValueType)i;
709 if (!isTypeLegal(VT)) {
712 unsigned NumIntermediates;
713 NumRegistersForVT[i] =
714 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
716 RegisterTypeForVT[i] = RegisterVT;
718 // Determine if there is a legal wider type.
719 bool IsLegalWiderType = false;
720 EVT EltVT = VT.getVectorElementType();
721 unsigned NElts = VT.getVectorNumElements();
722 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
723 EVT SVT = (MVT::SimpleValueType)nVT;
724 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
725 SVT.getVectorNumElements() > NElts && NElts != 1) {
726 TransformToType[i] = SVT;
727 ValueTypeActions.setTypeAction(VT, Promote);
728 IsLegalWiderType = true;
732 if (!IsLegalWiderType) {
733 EVT NVT = VT.getPow2VectorType();
735 // Type is already a power of 2. The default action is to split.
736 TransformToType[i] = MVT::Other;
737 ValueTypeActions.setTypeAction(VT, Expand);
739 TransformToType[i] = NVT;
740 ValueTypeActions.setTypeAction(VT, Promote);
747 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
752 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
753 return PointerTy.SimpleTy;
756 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
757 return MVT::i32; // return the default value
760 /// getVectorTypeBreakdown - Vector types are broken down into some number of
761 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
762 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
763 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
765 /// This method returns the number of registers needed, and the VT for each
766 /// register. It also returns the VT and quantity of the intermediate values
767 /// before they are promoted/expanded.
769 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
771 unsigned &NumIntermediates,
772 EVT &RegisterVT) const {
773 // Figure out the right, legal destination reg to copy into.
774 unsigned NumElts = VT.getVectorNumElements();
775 EVT EltTy = VT.getVectorElementType();
777 unsigned NumVectorRegs = 1;
779 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
780 // could break down into LHS/RHS like LegalizeDAG does.
781 if (!isPowerOf2_32(NumElts)) {
782 NumVectorRegs = NumElts;
786 // Divide the input until we get to a supported size. This will always
787 // end with a scalar if the target doesn't support vectors.
788 while (NumElts > 1 && !isTypeLegal(
789 EVT::getVectorVT(Context, EltTy, NumElts))) {
794 NumIntermediates = NumVectorRegs;
796 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
797 if (!isTypeLegal(NewVT))
799 IntermediateVT = NewVT;
801 EVT DestVT = getRegisterType(Context, NewVT);
803 if (DestVT.bitsLT(NewVT)) {
804 // Value is expanded, e.g. i64 -> i16.
805 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
807 // Otherwise, promotion or legal types use the same number of registers as
808 // the vector decimated to the appropriate level.
809 return NumVectorRegs;
815 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
816 /// function arguments in the caller parameter area. This is the actual
817 /// alignment, not its logarithm.
818 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
819 return TD->getCallFrameTypeAlignment(Ty);
822 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
823 /// current function. The returned value is a member of the
824 /// MachineJumpTableInfo::JTEntryKind enum.
825 unsigned TargetLowering::getJumpTableEncoding() const {
826 // In non-pic modes, just use the address of a block.
827 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
828 return MachineJumpTableInfo::EK_BlockAddress;
830 // In PIC mode, if the target supports a GPRel32 directive, use it.
831 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
832 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
834 // Otherwise, use a label difference.
835 return MachineJumpTableInfo::EK_LabelDifference32;
838 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
839 SelectionDAG &DAG) const {
840 // If our PIC model is GP relative, use the global offset table as the base.
841 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
842 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
846 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
847 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
850 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
851 unsigned JTI,MCContext &Ctx) const{
852 // The normal PIC reloc base is the label at the start of the jump table.
853 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
857 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
858 // Assume that everything is safe in static mode.
859 if (getTargetMachine().getRelocationModel() == Reloc::Static)
862 // In dynamic-no-pic mode, assume that known defined values are safe.
863 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
865 !GA->getGlobal()->isDeclaration() &&
866 !GA->getGlobal()->isWeakForLinker())
869 // Otherwise assume nothing is safe.
873 //===----------------------------------------------------------------------===//
874 // Optimization Methods
875 //===----------------------------------------------------------------------===//
877 /// ShrinkDemandedConstant - Check to see if the specified operand of the
878 /// specified instruction is a constant integer. If so, check to see if there
879 /// are any bits set in the constant that are not demanded. If so, shrink the
880 /// constant and return true.
881 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
882 const APInt &Demanded) {
883 DebugLoc dl = Op.getDebugLoc();
885 // FIXME: ISD::SELECT, ISD::SELECT_CC
886 switch (Op.getOpcode()) {
891 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
892 if (!C) return false;
894 if (Op.getOpcode() == ISD::XOR &&
895 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
898 // if we can expand it to have all bits set, do it
899 if (C->getAPIntValue().intersects(~Demanded)) {
900 EVT VT = Op.getValueType();
901 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
902 DAG.getConstant(Demanded &
905 return CombineTo(Op, New);
915 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
916 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
917 /// cast, but it could be generalized for targets with other types of
918 /// implicit widening casts.
920 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
922 const APInt &Demanded,
924 assert(Op.getNumOperands() == 2 &&
925 "ShrinkDemandedOp only supports binary operators!");
926 assert(Op.getNode()->getNumValues() == 1 &&
927 "ShrinkDemandedOp only supports nodes with one result!");
929 // Don't do this if the node has another user, which may require the
931 if (!Op.getNode()->hasOneUse())
934 // Search for the smallest integer type with free casts to and from
935 // Op's type. For expedience, just check power-of-2 integer types.
936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
937 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
938 if (!isPowerOf2_32(SmallVTBits))
939 SmallVTBits = NextPowerOf2(SmallVTBits);
940 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
941 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
942 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
943 TLI.isZExtFree(SmallVT, Op.getValueType())) {
944 // We found a type with free casts.
945 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
946 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
947 Op.getNode()->getOperand(0)),
948 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
949 Op.getNode()->getOperand(1)));
950 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
951 return CombineTo(Op, Z);
957 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
958 /// DemandedMask bits of the result of Op are ever used downstream. If we can
959 /// use this information to simplify Op, create a new simplified DAG node and
960 /// return true, returning the original and new nodes in Old and New. Otherwise,
961 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
962 /// the expression (used to simplify the caller). The KnownZero/One bits may
963 /// only be accurate for those bits in the DemandedMask.
964 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
965 const APInt &DemandedMask,
968 TargetLoweringOpt &TLO,
969 unsigned Depth) const {
970 unsigned BitWidth = DemandedMask.getBitWidth();
971 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
972 "Mask size mismatches value type size!");
973 APInt NewMask = DemandedMask;
974 DebugLoc dl = Op.getDebugLoc();
976 // Don't know anything.
977 KnownZero = KnownOne = APInt(BitWidth, 0);
979 // Other users may use these bits.
980 if (!Op.getNode()->hasOneUse()) {
982 // If not at the root, Just compute the KnownZero/KnownOne bits to
983 // simplify things downstream.
984 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
987 // If this is the root being simplified, allow it to have multiple uses,
988 // just set the NewMask to all bits.
989 NewMask = APInt::getAllOnesValue(BitWidth);
990 } else if (DemandedMask == 0) {
991 // Not demanding any bits from Op.
992 if (Op.getOpcode() != ISD::UNDEF)
993 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
995 } else if (Depth == 6) { // Limit search depth.
999 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1000 switch (Op.getOpcode()) {
1002 // We know all of the bits for a constant!
1003 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1004 KnownZero = ~KnownOne & NewMask;
1005 return false; // Don't fall through, will infinitely loop.
1007 // If the RHS is a constant, check to see if the LHS would be zero without
1008 // using the bits from the RHS. Below, we use knowledge about the RHS to
1009 // simplify the LHS, here we're using information from the LHS to simplify
1011 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1012 APInt LHSZero, LHSOne;
1013 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
1014 LHSZero, LHSOne, Depth+1);
1015 // If the LHS already has zeros where RHSC does, this and is dead.
1016 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1017 return TLO.CombineTo(Op, Op.getOperand(0));
1018 // If any of the set bits in the RHS are known zero on the LHS, shrink
1020 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1024 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1025 KnownOne, TLO, Depth+1))
1027 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1028 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1029 KnownZero2, KnownOne2, TLO, Depth+1))
1031 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1033 // If all of the demanded bits are known one on one side, return the other.
1034 // These bits cannot contribute to the result of the 'and'.
1035 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1036 return TLO.CombineTo(Op, Op.getOperand(0));
1037 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1038 return TLO.CombineTo(Op, Op.getOperand(1));
1039 // If all of the demanded bits in the inputs are known zeros, return zero.
1040 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1041 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1042 // If the RHS is a constant, see if we can simplify it.
1043 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1045 // If the operation can be done in a smaller type, do so.
1046 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1049 // Output known-1 bits are only known if set in both the LHS & RHS.
1050 KnownOne &= KnownOne2;
1051 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1052 KnownZero |= KnownZero2;
1055 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1056 KnownOne, TLO, Depth+1))
1058 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1059 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1060 KnownZero2, KnownOne2, TLO, Depth+1))
1062 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1064 // If all of the demanded bits are known zero on one side, return the other.
1065 // These bits cannot contribute to the result of the 'or'.
1066 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1067 return TLO.CombineTo(Op, Op.getOperand(0));
1068 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1069 return TLO.CombineTo(Op, Op.getOperand(1));
1070 // If all of the potentially set bits on one side are known to be set on
1071 // the other side, just use the 'other' side.
1072 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1073 return TLO.CombineTo(Op, Op.getOperand(0));
1074 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1075 return TLO.CombineTo(Op, Op.getOperand(1));
1076 // If the RHS is a constant, see if we can simplify it.
1077 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1079 // If the operation can be done in a smaller type, do so.
1080 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1083 // Output known-0 bits are only known if clear in both the LHS & RHS.
1084 KnownZero &= KnownZero2;
1085 // Output known-1 are known to be set if set in either the LHS | RHS.
1086 KnownOne |= KnownOne2;
1089 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1090 KnownOne, TLO, Depth+1))
1092 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1093 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1094 KnownOne2, TLO, Depth+1))
1096 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1098 // If all of the demanded bits are known zero on one side, return the other.
1099 // These bits cannot contribute to the result of the 'xor'.
1100 if ((KnownZero & NewMask) == NewMask)
1101 return TLO.CombineTo(Op, Op.getOperand(0));
1102 if ((KnownZero2 & NewMask) == NewMask)
1103 return TLO.CombineTo(Op, Op.getOperand(1));
1104 // If the operation can be done in a smaller type, do so.
1105 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1108 // If all of the unknown bits are known to be zero on one side or the other
1109 // (but not both) turn this into an *inclusive* or.
1110 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1111 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1112 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1116 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1117 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1118 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1119 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1121 // If all of the demanded bits on one side are known, and all of the set
1122 // bits on that side are also known to be set on the other side, turn this
1123 // into an AND, as we know the bits will be cleared.
1124 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1125 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1126 if ((KnownOne & KnownOne2) == KnownOne) {
1127 EVT VT = Op.getValueType();
1128 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1129 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1130 Op.getOperand(0), ANDC));
1134 // If the RHS is a constant, see if we can simplify it.
1135 // for XOR, we prefer to force bits to 1 if they will make a -1.
1136 // if we can't force bits, try to shrink constant
1137 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1138 APInt Expanded = C->getAPIntValue() | (~NewMask);
1139 // if we can expand it to have all bits set, do it
1140 if (Expanded.isAllOnesValue()) {
1141 if (Expanded != C->getAPIntValue()) {
1142 EVT VT = Op.getValueType();
1143 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1144 TLO.DAG.getConstant(Expanded, VT));
1145 return TLO.CombineTo(Op, New);
1147 // if it already has all the bits set, nothing to change
1148 // but don't shrink either!
1149 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1154 KnownZero = KnownZeroOut;
1155 KnownOne = KnownOneOut;
1158 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1159 KnownOne, TLO, Depth+1))
1161 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1162 KnownOne2, TLO, Depth+1))
1164 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1165 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1167 // If the operands are constants, see if we can simplify them.
1168 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1171 // Only known if known in both the LHS and RHS.
1172 KnownOne &= KnownOne2;
1173 KnownZero &= KnownZero2;
1175 case ISD::SELECT_CC:
1176 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1177 KnownOne, TLO, Depth+1))
1179 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1180 KnownOne2, TLO, Depth+1))
1182 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1183 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1185 // If the operands are constants, see if we can simplify them.
1186 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1189 // Only known if known in both the LHS and RHS.
1190 KnownOne &= KnownOne2;
1191 KnownZero &= KnownZero2;
1194 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1195 unsigned ShAmt = SA->getZExtValue();
1196 SDValue InOp = Op.getOperand(0);
1198 // If the shift count is an invalid immediate, don't do anything.
1199 if (ShAmt >= BitWidth)
1202 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1203 // single shift. We can do this if the bottom bits (which are shifted
1204 // out) are never demanded.
1205 if (InOp.getOpcode() == ISD::SRL &&
1206 isa<ConstantSDNode>(InOp.getOperand(1))) {
1207 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1208 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1209 unsigned Opc = ISD::SHL;
1210 int Diff = ShAmt-C1;
1217 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1218 EVT VT = Op.getValueType();
1219 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1220 InOp.getOperand(0), NewSA));
1224 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1225 KnownZero, KnownOne, TLO, Depth+1))
1227 KnownZero <<= SA->getZExtValue();
1228 KnownOne <<= SA->getZExtValue();
1229 // low bits known zero.
1230 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1234 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1235 EVT VT = Op.getValueType();
1236 unsigned ShAmt = SA->getZExtValue();
1237 unsigned VTSize = VT.getSizeInBits();
1238 SDValue InOp = Op.getOperand(0);
1240 // If the shift count is an invalid immediate, don't do anything.
1241 if (ShAmt >= BitWidth)
1244 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1245 // single shift. We can do this if the top bits (which are shifted out)
1246 // are never demanded.
1247 if (InOp.getOpcode() == ISD::SHL &&
1248 isa<ConstantSDNode>(InOp.getOperand(1))) {
1249 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1250 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1251 unsigned Opc = ISD::SRL;
1252 int Diff = ShAmt-C1;
1259 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1260 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1261 InOp.getOperand(0), NewSA));
1265 // Compute the new bits that are at the top now.
1266 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1267 KnownZero, KnownOne, TLO, Depth+1))
1269 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1270 KnownZero = KnownZero.lshr(ShAmt);
1271 KnownOne = KnownOne.lshr(ShAmt);
1273 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1274 KnownZero |= HighBits; // High bits known zero.
1278 // If this is an arithmetic shift right and only the low-bit is set, we can
1279 // always convert this into a logical shr, even if the shift amount is
1280 // variable. The low bit of the shift cannot be an input sign bit unless
1281 // the shift amount is >= the size of the datatype, which is undefined.
1282 if (DemandedMask == 1)
1283 return TLO.CombineTo(Op,
1284 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1285 Op.getOperand(0), Op.getOperand(1)));
1287 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1288 EVT VT = Op.getValueType();
1289 unsigned ShAmt = SA->getZExtValue();
1291 // If the shift count is an invalid immediate, don't do anything.
1292 if (ShAmt >= BitWidth)
1295 APInt InDemandedMask = (NewMask << ShAmt);
1297 // If any of the demanded bits are produced by the sign extension, we also
1298 // demand the input sign bit.
1299 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1300 if (HighBits.intersects(NewMask))
1301 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1303 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1304 KnownZero, KnownOne, TLO, Depth+1))
1306 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1307 KnownZero = KnownZero.lshr(ShAmt);
1308 KnownOne = KnownOne.lshr(ShAmt);
1310 // Handle the sign bit, adjusted to where it is now in the mask.
1311 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1313 // If the input sign bit is known to be zero, or if none of the top bits
1314 // are demanded, turn this into an unsigned shift right.
1315 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1316 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1319 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1320 KnownOne |= HighBits;
1324 case ISD::SIGN_EXTEND_INREG: {
1325 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1327 // Sign extension. Compute the demanded bits in the result that are not
1328 // present in the input.
1330 APInt::getHighBitsSet(BitWidth,
1331 BitWidth - EVT.getScalarType().getSizeInBits()) &
1334 // If none of the extended bits are demanded, eliminate the sextinreg.
1336 return TLO.CombineTo(Op, Op.getOperand(0));
1338 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
1339 InSignBit.zext(BitWidth);
1340 APInt InputDemandedBits =
1341 APInt::getLowBitsSet(BitWidth,
1342 EVT.getScalarType().getSizeInBits()) &
1345 // Since the sign extended bits are demanded, we know that the sign
1347 InputDemandedBits |= InSignBit;
1349 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1350 KnownZero, KnownOne, TLO, Depth+1))
1352 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1354 // If the sign bit of the input is known set or clear, then we know the
1355 // top bits of the result.
1357 // If the input sign bit is known zero, convert this into a zero extension.
1358 if (KnownZero.intersects(InSignBit))
1359 return TLO.CombineTo(Op,
1360 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1362 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1363 KnownOne |= NewBits;
1364 KnownZero &= ~NewBits;
1365 } else { // Input sign bit unknown
1366 KnownZero &= ~NewBits;
1367 KnownOne &= ~NewBits;
1371 case ISD::ZERO_EXTEND: {
1372 unsigned OperandBitWidth =
1373 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1374 APInt InMask = NewMask;
1375 InMask.trunc(OperandBitWidth);
1377 // If none of the top bits are demanded, convert this into an any_extend.
1379 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1380 if (!NewBits.intersects(NewMask))
1381 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1385 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1386 KnownZero, KnownOne, TLO, Depth+1))
1388 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1389 KnownZero.zext(BitWidth);
1390 KnownOne.zext(BitWidth);
1391 KnownZero |= NewBits;
1394 case ISD::SIGN_EXTEND: {
1395 EVT InVT = Op.getOperand(0).getValueType();
1396 unsigned InBits = InVT.getScalarType().getSizeInBits();
1397 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1398 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1399 APInt NewBits = ~InMask & NewMask;
1401 // If none of the top bits are demanded, convert this into an any_extend.
1403 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1407 // Since some of the sign extended bits are demanded, we know that the sign
1409 APInt InDemandedBits = InMask & NewMask;
1410 InDemandedBits |= InSignBit;
1411 InDemandedBits.trunc(InBits);
1413 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1414 KnownOne, TLO, Depth+1))
1416 KnownZero.zext(BitWidth);
1417 KnownOne.zext(BitWidth);
1419 // If the sign bit is known zero, convert this to a zero extend.
1420 if (KnownZero.intersects(InSignBit))
1421 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1425 // If the sign bit is known one, the top bits match.
1426 if (KnownOne.intersects(InSignBit)) {
1427 KnownOne |= NewBits;
1428 KnownZero &= ~NewBits;
1429 } else { // Otherwise, top bits aren't known.
1430 KnownOne &= ~NewBits;
1431 KnownZero &= ~NewBits;
1435 case ISD::ANY_EXTEND: {
1436 unsigned OperandBitWidth =
1437 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1438 APInt InMask = NewMask;
1439 InMask.trunc(OperandBitWidth);
1440 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1441 KnownZero, KnownOne, TLO, Depth+1))
1443 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1444 KnownZero.zext(BitWidth);
1445 KnownOne.zext(BitWidth);
1448 case ISD::TRUNCATE: {
1449 // Simplify the input, using demanded bit information, and compute the known
1450 // zero/one bits live out.
1451 unsigned OperandBitWidth =
1452 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1453 APInt TruncMask = NewMask;
1454 TruncMask.zext(OperandBitWidth);
1455 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1456 KnownZero, KnownOne, TLO, Depth+1))
1458 KnownZero.trunc(BitWidth);
1459 KnownOne.trunc(BitWidth);
1461 // If the input is only used by this truncate, see if we can shrink it based
1462 // on the known demanded bits.
1463 if (Op.getOperand(0).getNode()->hasOneUse()) {
1464 SDValue In = Op.getOperand(0);
1465 switch (In.getOpcode()) {
1468 // Shrink SRL by a constant if none of the high bits shifted in are
1470 if (TLO.LegalTypes() &&
1471 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1472 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1475 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1478 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1479 OperandBitWidth - BitWidth);
1480 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1481 HighBits.trunc(BitWidth);
1483 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1484 // None of the shifted in bits are needed. Add a truncate of the
1485 // shift input, then shift it.
1486 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1489 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1498 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1501 case ISD::AssertZext: {
1502 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1503 APInt InMask = APInt::getLowBitsSet(BitWidth,
1504 VT.getSizeInBits());
1505 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1506 KnownZero, KnownOne, TLO, Depth+1))
1508 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1509 KnownZero |= ~InMask & NewMask;
1512 case ISD::BIT_CONVERT:
1514 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1515 // is demanded, turn this into a FGETSIGN.
1516 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1517 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1518 !MVT::isVector(Op.getOperand(0).getValueType())) {
1519 // Only do this xform if FGETSIGN is valid or if before legalize.
1520 if (!TLO.AfterLegalize ||
1521 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1522 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1523 // place. We expect the SHL to be eliminated by other optimizations.
1524 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1526 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1527 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1528 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1537 // Add, Sub, and Mul don't demand any bits in positions beyond that
1538 // of the highest bit demanded of them.
1539 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1540 BitWidth - NewMask.countLeadingZeros());
1541 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1542 KnownOne2, TLO, Depth+1))
1544 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1545 KnownOne2, TLO, Depth+1))
1547 // See if the operation should be performed at a smaller bit width.
1548 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1553 // Just use ComputeMaskedBits to compute output bits.
1554 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1558 // If we know the value of all of the demanded bits, return this as a
1560 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1561 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1566 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1567 /// in Mask are known to be either zero or one and return them in the
1568 /// KnownZero/KnownOne bitsets.
1569 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1573 const SelectionDAG &DAG,
1574 unsigned Depth) const {
1575 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1576 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1577 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1578 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1579 "Should use MaskedValueIsZero if you don't know whether Op"
1580 " is a target node!");
1581 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1584 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1585 /// targets that want to expose additional information about sign bits to the
1587 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1588 unsigned Depth) const {
1589 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1590 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1591 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1592 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1593 "Should use ComputeNumSignBits if you don't know whether Op"
1594 " is a target node!");
1598 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1599 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1600 /// determine which bit is set.
1602 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1603 // A left-shift of a constant one will have exactly one bit set, because
1604 // shifting the bit off the end is undefined.
1605 if (Val.getOpcode() == ISD::SHL)
1606 if (ConstantSDNode *C =
1607 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1608 if (C->getAPIntValue() == 1)
1611 // Similarly, a right-shift of a constant sign-bit will have exactly
1613 if (Val.getOpcode() == ISD::SRL)
1614 if (ConstantSDNode *C =
1615 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1616 if (C->getAPIntValue().isSignBit())
1619 // More could be done here, though the above checks are enough
1620 // to handle some common cases.
1622 // Fall back to ComputeMaskedBits to catch other known cases.
1623 EVT OpVT = Val.getValueType();
1624 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1625 APInt Mask = APInt::getAllOnesValue(BitWidth);
1626 APInt KnownZero, KnownOne;
1627 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1628 return (KnownZero.countPopulation() == BitWidth - 1) &&
1629 (KnownOne.countPopulation() == 1);
1632 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1633 /// and cc. If it is unable to simplify it, return a null SDValue.
1635 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1636 ISD::CondCode Cond, bool foldBooleans,
1637 DAGCombinerInfo &DCI, DebugLoc dl) const {
1638 SelectionDAG &DAG = DCI.DAG;
1639 LLVMContext &Context = *DAG.getContext();
1641 // These setcc operations always fold.
1645 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1647 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1650 if (isa<ConstantSDNode>(N0.getNode())) {
1651 // Ensure that the constant occurs on the RHS, and fold constant
1653 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1656 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1657 const APInt &C1 = N1C->getAPIntValue();
1659 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1660 // equality comparison, then we're just comparing whether X itself is
1662 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1663 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1664 N0.getOperand(1).getOpcode() == ISD::Constant) {
1666 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1667 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1668 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1669 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1670 // (srl (ctlz x), 5) == 0 -> X != 0
1671 // (srl (ctlz x), 5) != 1 -> X != 0
1674 // (srl (ctlz x), 5) != 0 -> X == 0
1675 // (srl (ctlz x), 5) == 1 -> X == 0
1678 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1679 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1684 // If the LHS is '(and load, const)', the RHS is 0,
1685 // the test is for equality or unsigned, and all 1 bits of the const are
1686 // in the same partial word, see if we can shorten the load.
1687 if (DCI.isBeforeLegalize() &&
1688 N0.getOpcode() == ISD::AND && C1 == 0 &&
1689 N0.getNode()->hasOneUse() &&
1690 isa<LoadSDNode>(N0.getOperand(0)) &&
1691 N0.getOperand(0).getNode()->hasOneUse() &&
1692 isa<ConstantSDNode>(N0.getOperand(1))) {
1693 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1695 unsigned bestWidth = 0, bestOffset = 0;
1696 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1697 unsigned origWidth = N0.getValueType().getSizeInBits();
1698 unsigned maskWidth = origWidth;
1699 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1700 // 8 bits, but have to be careful...
1701 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1702 origWidth = Lod->getMemoryVT().getSizeInBits();
1704 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1705 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1706 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1707 for (unsigned offset=0; offset<origWidth/width; offset++) {
1708 if ((newMask & Mask) == Mask) {
1709 if (!TD->isLittleEndian())
1710 bestOffset = (origWidth/width - offset - 1) * (width/8);
1712 bestOffset = (uint64_t)offset * (width/8);
1713 bestMask = Mask.lshr(offset * (width/8) * 8);
1717 newMask = newMask << width;
1722 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1723 if (newVT.isRound()) {
1724 EVT PtrType = Lod->getOperand(1).getValueType();
1725 SDValue Ptr = Lod->getBasePtr();
1726 if (bestOffset != 0)
1727 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1728 DAG.getConstant(bestOffset, PtrType));
1729 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1730 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1732 Lod->getSrcValueOffset() + bestOffset,
1733 false, false, NewAlign);
1734 return DAG.getSetCC(dl, VT,
1735 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1736 DAG.getConstant(bestMask.trunc(bestWidth),
1738 DAG.getConstant(0LL, newVT), Cond);
1743 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1744 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1745 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1747 // If the comparison constant has bits in the upper part, the
1748 // zero-extended value could never match.
1749 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1750 C1.getBitWidth() - InSize))) {
1754 case ISD::SETEQ: return DAG.getConstant(0, VT);
1757 case ISD::SETNE: return DAG.getConstant(1, VT);
1760 // True if the sign bit of C1 is set.
1761 return DAG.getConstant(C1.isNegative(), VT);
1764 // True if the sign bit of C1 isn't set.
1765 return DAG.getConstant(C1.isNonNegative(), VT);
1771 // Otherwise, we can perform the comparison with the low bits.
1779 EVT newVT = N0.getOperand(0).getValueType();
1780 if (DCI.isBeforeLegalizeOps() ||
1781 (isOperationLegal(ISD::SETCC, newVT) &&
1782 getCondCodeAction(Cond, newVT)==Legal))
1783 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1784 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1789 break; // todo, be more careful with signed comparisons
1791 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1792 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1793 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1794 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1795 EVT ExtDstTy = N0.getValueType();
1796 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1798 // If the extended part has any inconsistent bits, it cannot ever
1799 // compare equal. In other words, they have to be all ones or all
1802 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1803 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1804 return DAG.getConstant(Cond == ISD::SETNE, VT);
1807 EVT Op0Ty = N0.getOperand(0).getValueType();
1808 if (Op0Ty == ExtSrcTy) {
1809 ZextOp = N0.getOperand(0);
1811 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1812 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1813 DAG.getConstant(Imm, Op0Ty));
1815 if (!DCI.isCalledByLegalizer())
1816 DCI.AddToWorklist(ZextOp.getNode());
1817 // Otherwise, make this a use of a zext.
1818 return DAG.getSetCC(dl, VT, ZextOp,
1819 DAG.getConstant(C1 & APInt::getLowBitsSet(
1824 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1825 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1826 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1827 if (N0.getOpcode() == ISD::SETCC &&
1828 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1829 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1831 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1832 // Invert the condition.
1833 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1834 CC = ISD::getSetCCInverse(CC,
1835 N0.getOperand(0).getValueType().isInteger());
1836 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1839 if ((N0.getOpcode() == ISD::XOR ||
1840 (N0.getOpcode() == ISD::AND &&
1841 N0.getOperand(0).getOpcode() == ISD::XOR &&
1842 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1843 isa<ConstantSDNode>(N0.getOperand(1)) &&
1844 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1845 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1846 // can only do this if the top bits are known zero.
1847 unsigned BitWidth = N0.getValueSizeInBits();
1848 if (DAG.MaskedValueIsZero(N0,
1849 APInt::getHighBitsSet(BitWidth,
1851 // Okay, get the un-inverted input value.
1853 if (N0.getOpcode() == ISD::XOR)
1854 Val = N0.getOperand(0);
1856 assert(N0.getOpcode() == ISD::AND &&
1857 N0.getOperand(0).getOpcode() == ISD::XOR);
1858 // ((X^1)&1)^1 -> X & 1
1859 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1860 N0.getOperand(0).getOperand(0),
1864 return DAG.getSetCC(dl, VT, Val, N1,
1865 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1867 } else if (N1C->getAPIntValue() == 1 &&
1869 getBooleanContents() == ZeroOrOneBooleanContent)) {
1871 if (Op0.getOpcode() == ISD::TRUNCATE)
1872 Op0 = Op0.getOperand(0);
1874 if ((Op0.getOpcode() == ISD::XOR) &&
1875 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1876 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1877 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1878 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1879 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1881 } else if (Op0.getOpcode() == ISD::AND &&
1882 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1883 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1884 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1885 if (Op0.getValueType() != VT)
1886 Op0 = DAG.getNode(ISD::AND, dl, VT,
1887 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1888 DAG.getConstant(1, VT));
1889 return DAG.getSetCC(dl, VT, Op0,
1890 DAG.getConstant(0, Op0.getValueType()),
1891 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1896 APInt MinVal, MaxVal;
1897 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1898 if (ISD::isSignedIntSetCC(Cond)) {
1899 MinVal = APInt::getSignedMinValue(OperandBitSize);
1900 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1902 MinVal = APInt::getMinValue(OperandBitSize);
1903 MaxVal = APInt::getMaxValue(OperandBitSize);
1906 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1907 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1908 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1909 // X >= C0 --> X > (C0-1)
1910 return DAG.getSetCC(dl, VT, N0,
1911 DAG.getConstant(C1-1, N1.getValueType()),
1912 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1915 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1916 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1917 // X <= C0 --> X < (C0+1)
1918 return DAG.getSetCC(dl, VT, N0,
1919 DAG.getConstant(C1+1, N1.getValueType()),
1920 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1923 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1924 return DAG.getConstant(0, VT); // X < MIN --> false
1925 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1926 return DAG.getConstant(1, VT); // X >= MIN --> true
1927 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1928 return DAG.getConstant(0, VT); // X > MAX --> false
1929 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1930 return DAG.getConstant(1, VT); // X <= MAX --> true
1932 // Canonicalize setgt X, Min --> setne X, Min
1933 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1934 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1935 // Canonicalize setlt X, Max --> setne X, Max
1936 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1937 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1939 // If we have setult X, 1, turn it into seteq X, 0
1940 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1941 return DAG.getSetCC(dl, VT, N0,
1942 DAG.getConstant(MinVal, N0.getValueType()),
1944 // If we have setugt X, Max-1, turn it into seteq X, Max
1945 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1946 return DAG.getSetCC(dl, VT, N0,
1947 DAG.getConstant(MaxVal, N0.getValueType()),
1950 // If we have "setcc X, C0", check to see if we can shrink the immediate
1953 // SETUGT X, SINTMAX -> SETLT X, 0
1954 if (Cond == ISD::SETUGT &&
1955 C1 == APInt::getSignedMaxValue(OperandBitSize))
1956 return DAG.getSetCC(dl, VT, N0,
1957 DAG.getConstant(0, N1.getValueType()),
1960 // SETULT X, SINTMIN -> SETGT X, -1
1961 if (Cond == ISD::SETULT &&
1962 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1963 SDValue ConstMinusOne =
1964 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1966 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1969 // Fold bit comparisons when we can.
1970 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1971 (VT == N0.getValueType() ||
1972 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1973 N0.getOpcode() == ISD::AND)
1974 if (ConstantSDNode *AndRHS =
1975 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1976 EVT ShiftTy = DCI.isBeforeLegalize() ?
1977 getPointerTy() : getShiftAmountTy();
1978 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1979 // Perform the xform if the AND RHS is a single bit.
1980 if (AndRHS->getAPIntValue().isPowerOf2()) {
1981 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1982 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1983 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1985 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1986 // (X & 8) == 8 --> (X & 8) >> 3
1987 // Perform the xform if C1 is a single bit.
1988 if (C1.isPowerOf2()) {
1989 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1990 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1991 DAG.getConstant(C1.logBase2(), ShiftTy)));
1997 if (isa<ConstantFPSDNode>(N0.getNode())) {
1998 // Constant fold or commute setcc.
1999 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2000 if (O.getNode()) return O;
2001 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2002 // If the RHS of an FP comparison is a constant, simplify it away in
2004 if (CFP->getValueAPF().isNaN()) {
2005 // If an operand is known to be a nan, we can fold it.
2006 switch (ISD::getUnorderedFlavor(Cond)) {
2007 default: llvm_unreachable("Unknown flavor!");
2008 case 0: // Known false.
2009 return DAG.getConstant(0, VT);
2010 case 1: // Known true.
2011 return DAG.getConstant(1, VT);
2012 case 2: // Undefined.
2013 return DAG.getUNDEF(VT);
2017 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2018 // constant if knowing that the operand is non-nan is enough. We prefer to
2019 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2021 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2022 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2024 // If the condition is not legal, see if we can find an equivalent one
2026 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2027 // If the comparison was an awkward floating-point == or != and one of
2028 // the comparison operands is infinity or negative infinity, convert the
2029 // condition to a less-awkward <= or >=.
2030 if (CFP->getValueAPF().isInfinity()) {
2031 if (CFP->getValueAPF().isNegative()) {
2032 if (Cond == ISD::SETOEQ &&
2033 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2034 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2035 if (Cond == ISD::SETUEQ &&
2036 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2037 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2038 if (Cond == ISD::SETUNE &&
2039 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2040 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2041 if (Cond == ISD::SETONE &&
2042 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2043 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2045 if (Cond == ISD::SETOEQ &&
2046 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2047 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2048 if (Cond == ISD::SETUEQ &&
2049 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2050 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2051 if (Cond == ISD::SETUNE &&
2052 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2053 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2054 if (Cond == ISD::SETONE &&
2055 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2056 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2063 // We can always fold X == X for integer setcc's.
2064 if (N0.getValueType().isInteger())
2065 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2066 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2067 if (UOF == 2) // FP operators that are undefined on NaNs.
2068 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2069 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2070 return DAG.getConstant(UOF, VT);
2071 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2072 // if it is not already.
2073 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2074 if (NewCond != Cond)
2075 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2078 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2079 N0.getValueType().isInteger()) {
2080 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2081 N0.getOpcode() == ISD::XOR) {
2082 // Simplify (X+Y) == (X+Z) --> Y == Z
2083 if (N0.getOpcode() == N1.getOpcode()) {
2084 if (N0.getOperand(0) == N1.getOperand(0))
2085 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2086 if (N0.getOperand(1) == N1.getOperand(1))
2087 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2088 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2089 // If X op Y == Y op X, try other combinations.
2090 if (N0.getOperand(0) == N1.getOperand(1))
2091 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2093 if (N0.getOperand(1) == N1.getOperand(0))
2094 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2099 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2100 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2101 // Turn (X+C1) == C2 --> X == C2-C1
2102 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2103 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2104 DAG.getConstant(RHSC->getAPIntValue()-
2105 LHSR->getAPIntValue(),
2106 N0.getValueType()), Cond);
2109 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2110 if (N0.getOpcode() == ISD::XOR)
2111 // If we know that all of the inverted bits are zero, don't bother
2112 // performing the inversion.
2113 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2115 DAG.getSetCC(dl, VT, N0.getOperand(0),
2116 DAG.getConstant(LHSR->getAPIntValue() ^
2117 RHSC->getAPIntValue(),
2122 // Turn (C1-X) == C2 --> X == C1-C2
2123 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2124 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2126 DAG.getSetCC(dl, VT, N0.getOperand(1),
2127 DAG.getConstant(SUBC->getAPIntValue() -
2128 RHSC->getAPIntValue(),
2135 // Simplify (X+Z) == X --> Z == 0
2136 if (N0.getOperand(0) == N1)
2137 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2138 DAG.getConstant(0, N0.getValueType()), Cond);
2139 if (N0.getOperand(1) == N1) {
2140 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2141 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2142 DAG.getConstant(0, N0.getValueType()), Cond);
2143 else if (N0.getNode()->hasOneUse()) {
2144 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2145 // (Z-X) == X --> Z == X<<1
2146 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2148 DAG.getConstant(1, getShiftAmountTy()));
2149 if (!DCI.isCalledByLegalizer())
2150 DCI.AddToWorklist(SH.getNode());
2151 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2156 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2157 N1.getOpcode() == ISD::XOR) {
2158 // Simplify X == (X+Z) --> Z == 0
2159 if (N1.getOperand(0) == N0) {
2160 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2161 DAG.getConstant(0, N1.getValueType()), Cond);
2162 } else if (N1.getOperand(1) == N0) {
2163 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2164 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2165 DAG.getConstant(0, N1.getValueType()), Cond);
2166 } else if (N1.getNode()->hasOneUse()) {
2167 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2168 // X == (Z-X) --> X<<1 == Z
2169 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2170 DAG.getConstant(1, getShiftAmountTy()));
2171 if (!DCI.isCalledByLegalizer())
2172 DCI.AddToWorklist(SH.getNode());
2173 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2178 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2179 // Note that where y is variable and is known to have at most
2180 // one bit set (for example, if it is z&1) we cannot do this;
2181 // the expressions are not equivalent when y==0.
2182 if (N0.getOpcode() == ISD::AND)
2183 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2184 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2185 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2186 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2187 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2190 if (N1.getOpcode() == ISD::AND)
2191 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2192 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2193 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2194 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2195 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2200 // Fold away ALL boolean setcc's.
2202 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2204 default: llvm_unreachable("Unknown integer setcc!");
2205 case ISD::SETEQ: // X == Y -> ~(X^Y)
2206 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2207 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2208 if (!DCI.isCalledByLegalizer())
2209 DCI.AddToWorklist(Temp.getNode());
2211 case ISD::SETNE: // X != Y --> (X^Y)
2212 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2214 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2215 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2216 Temp = DAG.getNOT(dl, N0, MVT::i1);
2217 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2218 if (!DCI.isCalledByLegalizer())
2219 DCI.AddToWorklist(Temp.getNode());
2221 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2222 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2223 Temp = DAG.getNOT(dl, N1, MVT::i1);
2224 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2225 if (!DCI.isCalledByLegalizer())
2226 DCI.AddToWorklist(Temp.getNode());
2228 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2229 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2230 Temp = DAG.getNOT(dl, N0, MVT::i1);
2231 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2232 if (!DCI.isCalledByLegalizer())
2233 DCI.AddToWorklist(Temp.getNode());
2235 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2236 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2237 Temp = DAG.getNOT(dl, N1, MVT::i1);
2238 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2241 if (VT != MVT::i1) {
2242 if (!DCI.isCalledByLegalizer())
2243 DCI.AddToWorklist(N0.getNode());
2244 // FIXME: If running after legalize, we probably can't do this.
2245 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2250 // Could not fold it.
2254 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2255 /// node is a GlobalAddress + offset.
2256 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
2257 int64_t &Offset) const {
2258 if (isa<GlobalAddressSDNode>(N)) {
2259 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2260 GA = GASD->getGlobal();
2261 Offset += GASD->getOffset();
2265 if (N->getOpcode() == ISD::ADD) {
2266 SDValue N1 = N->getOperand(0);
2267 SDValue N2 = N->getOperand(1);
2268 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2269 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2271 Offset += V->getSExtValue();
2274 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2275 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2277 Offset += V->getSExtValue();
2286 SDValue TargetLowering::
2287 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2288 // Default implementation: no optimization.
2292 //===----------------------------------------------------------------------===//
2293 // Inline Assembler Implementation Methods
2294 //===----------------------------------------------------------------------===//
2297 TargetLowering::ConstraintType
2298 TargetLowering::getConstraintType(const std::string &Constraint) const {
2299 // FIXME: lots more standard ones to handle.
2300 if (Constraint.size() == 1) {
2301 switch (Constraint[0]) {
2303 case 'r': return C_RegisterClass;
2305 case 'o': // offsetable
2306 case 'V': // not offsetable
2308 case 'i': // Simple Integer or Relocatable Constant
2309 case 'n': // Simple Integer
2310 case 's': // Relocatable Constant
2311 case 'X': // Allow ANY value.
2312 case 'I': // Target registers.
2324 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2325 Constraint[Constraint.size()-1] == '}')
2330 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2331 /// with another that has more specific requirements based on the type of the
2332 /// corresponding operand.
2333 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2334 if (ConstraintVT.isInteger())
2336 if (ConstraintVT.isFloatingPoint())
2337 return "f"; // works for many targets
2341 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2342 /// vector. If it is invalid, don't add anything to Ops.
2343 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2344 char ConstraintLetter,
2346 std::vector<SDValue> &Ops,
2347 SelectionDAG &DAG) const {
2348 switch (ConstraintLetter) {
2350 case 'X': // Allows any operand; labels (basic block) use this.
2351 if (Op.getOpcode() == ISD::BasicBlock) {
2356 case 'i': // Simple Integer or Relocatable Constant
2357 case 'n': // Simple Integer
2358 case 's': { // Relocatable Constant
2359 // These operands are interested in values of the form (GV+C), where C may
2360 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2361 // is possible and fine if either GV or C are missing.
2362 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2363 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2365 // If we have "(add GV, C)", pull out GV/C
2366 if (Op.getOpcode() == ISD::ADD) {
2367 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2368 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2369 if (C == 0 || GA == 0) {
2370 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2371 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2373 if (C == 0 || GA == 0)
2377 // If we find a valid operand, map to the TargetXXX version so that the
2378 // value itself doesn't get selected.
2379 if (GA) { // Either &GV or &GV+C
2380 if (ConstraintLetter != 'n') {
2381 int64_t Offs = GA->getOffset();
2382 if (C) Offs += C->getZExtValue();
2383 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2384 Op.getValueType(), Offs));
2388 if (C) { // just C, no GV.
2389 // Simple constants are not allowed for 's'.
2390 if (ConstraintLetter != 's') {
2391 // gcc prints these as sign extended. Sign extend value to 64 bits
2392 // now; without this it would get ZExt'd later in
2393 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2394 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2404 std::vector<unsigned> TargetLowering::
2405 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2407 return std::vector<unsigned>();
2411 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2412 getRegForInlineAsmConstraint(const std::string &Constraint,
2414 if (Constraint[0] != '{')
2415 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2416 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2418 // Remove the braces from around the name.
2419 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2421 // Figure out which register class contains this reg.
2422 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2423 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2424 E = RI->regclass_end(); RCI != E; ++RCI) {
2425 const TargetRegisterClass *RC = *RCI;
2427 // If none of the value types for this register class are valid, we
2428 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2429 bool isLegal = false;
2430 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2432 if (isTypeLegal(*I)) {
2438 if (!isLegal) continue;
2440 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2442 if (RegName.equals_lower(RI->getName(*I)))
2443 return std::make_pair(*I, RC);
2447 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2450 //===----------------------------------------------------------------------===//
2451 // Constraint Selection.
2453 /// isMatchingInputConstraint - Return true of this is an input operand that is
2454 /// a matching constraint like "4".
2455 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2456 assert(!ConstraintCode.empty() && "No known constraint!");
2457 return isdigit(ConstraintCode[0]);
2460 /// getMatchedOperand - If this is an input matching constraint, this method
2461 /// returns the output operand it matches.
2462 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2463 assert(!ConstraintCode.empty() && "No known constraint!");
2464 return atoi(ConstraintCode.c_str());
2468 /// getConstraintGenerality - Return an integer indicating how general CT
2470 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2472 default: llvm_unreachable("Unknown constraint type!");
2473 case TargetLowering::C_Other:
2474 case TargetLowering::C_Unknown:
2476 case TargetLowering::C_Register:
2478 case TargetLowering::C_RegisterClass:
2480 case TargetLowering::C_Memory:
2485 /// ChooseConstraint - If there are multiple different constraints that we
2486 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2487 /// This is somewhat tricky: constraints fall into four classes:
2488 /// Other -> immediates and magic values
2489 /// Register -> one specific register
2490 /// RegisterClass -> a group of regs
2491 /// Memory -> memory
2492 /// Ideally, we would pick the most specific constraint possible: if we have
2493 /// something that fits into a register, we would pick it. The problem here
2494 /// is that if we have something that could either be in a register or in
2495 /// memory that use of the register could cause selection of *other*
2496 /// operands to fail: they might only succeed if we pick memory. Because of
2497 /// this the heuristic we use is:
2499 /// 1) If there is an 'other' constraint, and if the operand is valid for
2500 /// that constraint, use it. This makes us take advantage of 'i'
2501 /// constraints when available.
2502 /// 2) Otherwise, pick the most general constraint present. This prefers
2503 /// 'm' over 'r', for example.
2505 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2506 bool hasMemory, const TargetLowering &TLI,
2507 SDValue Op, SelectionDAG *DAG) {
2508 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2509 unsigned BestIdx = 0;
2510 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2511 int BestGenerality = -1;
2513 // Loop over the options, keeping track of the most general one.
2514 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2515 TargetLowering::ConstraintType CType =
2516 TLI.getConstraintType(OpInfo.Codes[i]);
2518 // If this is an 'other' constraint, see if the operand is valid for it.
2519 // For example, on X86 we might have an 'rI' constraint. If the operand
2520 // is an integer in the range [0..31] we want to use I (saving a load
2521 // of a register), otherwise we must use 'r'.
2522 if (CType == TargetLowering::C_Other && Op.getNode()) {
2523 assert(OpInfo.Codes[i].size() == 1 &&
2524 "Unhandled multi-letter 'other' constraint");
2525 std::vector<SDValue> ResultOps;
2526 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2528 if (!ResultOps.empty()) {
2535 // This constraint letter is more general than the previous one, use it.
2536 int Generality = getConstraintGenerality(CType);
2537 if (Generality > BestGenerality) {
2540 BestGenerality = Generality;
2544 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2545 OpInfo.ConstraintType = BestType;
2548 /// ComputeConstraintToUse - Determines the constraint code and constraint
2549 /// type to use for the specific AsmOperandInfo, setting
2550 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2551 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2554 SelectionDAG *DAG) const {
2555 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2557 // Single-letter constraints ('r') are very common.
2558 if (OpInfo.Codes.size() == 1) {
2559 OpInfo.ConstraintCode = OpInfo.Codes[0];
2560 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2562 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2565 // 'X' matches anything.
2566 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2567 // Labels and constants are handled elsewhere ('X' is the only thing
2568 // that matches labels). For Functions, the type here is the type of
2569 // the result, which is not what we want to look at; leave them alone.
2570 Value *v = OpInfo.CallOperandVal;
2571 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2572 OpInfo.CallOperandVal = v;
2576 // Otherwise, try to resolve it to something we know about by looking at
2577 // the actual operand type.
2578 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2579 OpInfo.ConstraintCode = Repl;
2580 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2585 //===----------------------------------------------------------------------===//
2586 // Loop Strength Reduction hooks
2587 //===----------------------------------------------------------------------===//
2589 /// isLegalAddressingMode - Return true if the addressing mode represented
2590 /// by AM is legal for this target, for a load/store of the specified type.
2591 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2592 const Type *Ty) const {
2593 // The default implementation of this implements a conservative RISCy, r+r and
2596 // Allows a sign-extended 16-bit immediate field.
2597 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2600 // No global is ever allowed as a base.
2604 // Only support r+r,
2606 case 0: // "r+i" or just "i", depending on HasBaseReg.
2609 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2611 // Otherwise we have r+r or r+i.
2614 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2616 // Allow 2*r as r+r.
2623 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2624 /// return a DAG expression to select that will generate the same value by
2625 /// multiplying by a magic number. See:
2626 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2627 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2628 std::vector<SDNode*>* Created) const {
2629 EVT VT = N->getValueType(0);
2630 DebugLoc dl= N->getDebugLoc();
2632 // Check to see if we can do this.
2633 // FIXME: We should be more aggressive here.
2634 if (!isTypeLegal(VT))
2637 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2638 APInt::ms magics = d.magic();
2640 // Multiply the numerator (operand 0) by the magic value
2641 // FIXME: We should support doing a MUL in a wider type
2643 if (isOperationLegalOrCustom(ISD::MULHS, VT))
2644 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2645 DAG.getConstant(magics.m, VT));
2646 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2647 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2649 DAG.getConstant(magics.m, VT)).getNode(), 1);
2651 return SDValue(); // No mulhs or equvialent
2652 // If d > 0 and m < 0, add the numerator
2653 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2654 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2656 Created->push_back(Q.getNode());
2658 // If d < 0 and m > 0, subtract the numerator.
2659 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2660 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2662 Created->push_back(Q.getNode());
2664 // Shift right algebraic if shift value is nonzero
2666 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2667 DAG.getConstant(magics.s, getShiftAmountTy()));
2669 Created->push_back(Q.getNode());
2671 // Extract the sign bit and add it to the quotient
2673 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2674 getShiftAmountTy()));
2676 Created->push_back(T.getNode());
2677 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2680 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2681 /// return a DAG expression to select that will generate the same value by
2682 /// multiplying by a magic number. See:
2683 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2684 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2685 std::vector<SDNode*>* Created) const {
2686 EVT VT = N->getValueType(0);
2687 DebugLoc dl = N->getDebugLoc();
2689 // Check to see if we can do this.
2690 // FIXME: We should be more aggressive here.
2691 if (!isTypeLegal(VT))
2694 // FIXME: We should use a narrower constant when the upper
2695 // bits are known to be zero.
2696 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2697 APInt::mu magics = N1C->getAPIntValue().magicu();
2699 // Multiply the numerator (operand 0) by the magic value
2700 // FIXME: We should support doing a MUL in a wider type
2702 if (isOperationLegalOrCustom(ISD::MULHU, VT))
2703 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2704 DAG.getConstant(magics.m, VT));
2705 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2706 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2708 DAG.getConstant(magics.m, VT)).getNode(), 1);
2710 return SDValue(); // No mulhu or equvialent
2712 Created->push_back(Q.getNode());
2714 if (magics.a == 0) {
2715 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2716 "We shouldn't generate an undefined shift!");
2717 return DAG.getNode(ISD::SRL, dl, VT, Q,
2718 DAG.getConstant(magics.s, getShiftAmountTy()));
2720 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2722 Created->push_back(NPQ.getNode());
2723 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2724 DAG.getConstant(1, getShiftAmountTy()));
2726 Created->push_back(NPQ.getNode());
2727 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2729 Created->push_back(NPQ.getNode());
2730 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2731 DAG.getConstant(magics.s-1, getShiftAmountTy()));