1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Target/TargetLoweringObjectFile.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
36 /// InitLibcallNames - Set default libcall names.
38 static void InitLibcallNames(const char **Names) {
39 Names[RTLIB::SHL_I16] = "__ashlhi3";
40 Names[RTLIB::SHL_I32] = "__ashlsi3";
41 Names[RTLIB::SHL_I64] = "__ashldi3";
42 Names[RTLIB::SHL_I128] = "__ashlti3";
43 Names[RTLIB::SRL_I16] = "__lshrhi3";
44 Names[RTLIB::SRL_I32] = "__lshrsi3";
45 Names[RTLIB::SRL_I64] = "__lshrdi3";
46 Names[RTLIB::SRL_I128] = "__lshrti3";
47 Names[RTLIB::SRA_I16] = "__ashrhi3";
48 Names[RTLIB::SRA_I32] = "__ashrsi3";
49 Names[RTLIB::SRA_I64] = "__ashrdi3";
50 Names[RTLIB::SRA_I128] = "__ashrti3";
51 Names[RTLIB::MUL_I8] = "__mulqi3";
52 Names[RTLIB::MUL_I16] = "__mulhi3";
53 Names[RTLIB::MUL_I32] = "__mulsi3";
54 Names[RTLIB::MUL_I64] = "__muldi3";
55 Names[RTLIB::MUL_I128] = "__multi3";
56 Names[RTLIB::MULO_I32] = "__mulosi4";
57 Names[RTLIB::MULO_I64] = "__mulodi4";
58 Names[RTLIB::MULO_I128] = "__muloti4";
59 Names[RTLIB::SDIV_I8] = "__divqi3";
60 Names[RTLIB::SDIV_I16] = "__divhi3";
61 Names[RTLIB::SDIV_I32] = "__divsi3";
62 Names[RTLIB::SDIV_I64] = "__divdi3";
63 Names[RTLIB::SDIV_I128] = "__divti3";
64 Names[RTLIB::UDIV_I8] = "__udivqi3";
65 Names[RTLIB::UDIV_I16] = "__udivhi3";
66 Names[RTLIB::UDIV_I32] = "__udivsi3";
67 Names[RTLIB::UDIV_I64] = "__udivdi3";
68 Names[RTLIB::UDIV_I128] = "__udivti3";
69 Names[RTLIB::SREM_I8] = "__modqi3";
70 Names[RTLIB::SREM_I16] = "__modhi3";
71 Names[RTLIB::SREM_I32] = "__modsi3";
72 Names[RTLIB::SREM_I64] = "__moddi3";
73 Names[RTLIB::SREM_I128] = "__modti3";
74 Names[RTLIB::UREM_I8] = "__umodqi3";
75 Names[RTLIB::UREM_I16] = "__umodhi3";
76 Names[RTLIB::UREM_I32] = "__umodsi3";
77 Names[RTLIB::UREM_I64] = "__umoddi3";
78 Names[RTLIB::UREM_I128] = "__umodti3";
80 // These are generally not available.
81 Names[RTLIB::SDIVREM_I8] = 0;
82 Names[RTLIB::SDIVREM_I16] = 0;
83 Names[RTLIB::SDIVREM_I32] = 0;
84 Names[RTLIB::SDIVREM_I64] = 0;
85 Names[RTLIB::SDIVREM_I128] = 0;
86 Names[RTLIB::UDIVREM_I8] = 0;
87 Names[RTLIB::UDIVREM_I16] = 0;
88 Names[RTLIB::UDIVREM_I32] = 0;
89 Names[RTLIB::UDIVREM_I64] = 0;
90 Names[RTLIB::UDIVREM_I128] = 0;
92 Names[RTLIB::NEG_I32] = "__negsi2";
93 Names[RTLIB::NEG_I64] = "__negdi2";
94 Names[RTLIB::ADD_F32] = "__addsf3";
95 Names[RTLIB::ADD_F64] = "__adddf3";
96 Names[RTLIB::ADD_F80] = "__addxf3";
97 Names[RTLIB::ADD_F128] = "__addtf3";
98 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
99 Names[RTLIB::SUB_F32] = "__subsf3";
100 Names[RTLIB::SUB_F64] = "__subdf3";
101 Names[RTLIB::SUB_F80] = "__subxf3";
102 Names[RTLIB::SUB_F128] = "__subtf3";
103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
104 Names[RTLIB::MUL_F32] = "__mulsf3";
105 Names[RTLIB::MUL_F64] = "__muldf3";
106 Names[RTLIB::MUL_F80] = "__mulxf3";
107 Names[RTLIB::MUL_F128] = "__multf3";
108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
111 Names[RTLIB::DIV_F80] = "__divxf3";
112 Names[RTLIB::DIV_F128] = "__divtf3";
113 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
114 Names[RTLIB::REM_F32] = "fmodf";
115 Names[RTLIB::REM_F64] = "fmod";
116 Names[RTLIB::REM_F80] = "fmodl";
117 Names[RTLIB::REM_F128] = "fmodl";
118 Names[RTLIB::REM_PPCF128] = "fmodl";
119 Names[RTLIB::FMA_F32] = "fmaf";
120 Names[RTLIB::FMA_F64] = "fma";
121 Names[RTLIB::FMA_F80] = "fmal";
122 Names[RTLIB::FMA_F128] = "fmal";
123 Names[RTLIB::FMA_PPCF128] = "fmal";
124 Names[RTLIB::POWI_F32] = "__powisf2";
125 Names[RTLIB::POWI_F64] = "__powidf2";
126 Names[RTLIB::POWI_F80] = "__powixf2";
127 Names[RTLIB::POWI_F128] = "__powitf2";
128 Names[RTLIB::POWI_PPCF128] = "__powitf2";
129 Names[RTLIB::SQRT_F32] = "sqrtf";
130 Names[RTLIB::SQRT_F64] = "sqrt";
131 Names[RTLIB::SQRT_F80] = "sqrtl";
132 Names[RTLIB::SQRT_F128] = "sqrtl";
133 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
134 Names[RTLIB::LOG_F32] = "logf";
135 Names[RTLIB::LOG_F64] = "log";
136 Names[RTLIB::LOG_F80] = "logl";
137 Names[RTLIB::LOG_F128] = "logl";
138 Names[RTLIB::LOG_PPCF128] = "logl";
139 Names[RTLIB::LOG2_F32] = "log2f";
140 Names[RTLIB::LOG2_F64] = "log2";
141 Names[RTLIB::LOG2_F80] = "log2l";
142 Names[RTLIB::LOG2_F128] = "log2l";
143 Names[RTLIB::LOG2_PPCF128] = "log2l";
144 Names[RTLIB::LOG10_F32] = "log10f";
145 Names[RTLIB::LOG10_F64] = "log10";
146 Names[RTLIB::LOG10_F80] = "log10l";
147 Names[RTLIB::LOG10_F128] = "log10l";
148 Names[RTLIB::LOG10_PPCF128] = "log10l";
149 Names[RTLIB::EXP_F32] = "expf";
150 Names[RTLIB::EXP_F64] = "exp";
151 Names[RTLIB::EXP_F80] = "expl";
152 Names[RTLIB::EXP_F128] = "expl";
153 Names[RTLIB::EXP_PPCF128] = "expl";
154 Names[RTLIB::EXP2_F32] = "exp2f";
155 Names[RTLIB::EXP2_F64] = "exp2";
156 Names[RTLIB::EXP2_F80] = "exp2l";
157 Names[RTLIB::EXP2_F128] = "exp2l";
158 Names[RTLIB::EXP2_PPCF128] = "exp2l";
159 Names[RTLIB::SIN_F32] = "sinf";
160 Names[RTLIB::SIN_F64] = "sin";
161 Names[RTLIB::SIN_F80] = "sinl";
162 Names[RTLIB::SIN_F128] = "sinl";
163 Names[RTLIB::SIN_PPCF128] = "sinl";
164 Names[RTLIB::COS_F32] = "cosf";
165 Names[RTLIB::COS_F64] = "cos";
166 Names[RTLIB::COS_F80] = "cosl";
167 Names[RTLIB::COS_F128] = "cosl";
168 Names[RTLIB::COS_PPCF128] = "cosl";
169 Names[RTLIB::POW_F32] = "powf";
170 Names[RTLIB::POW_F64] = "pow";
171 Names[RTLIB::POW_F80] = "powl";
172 Names[RTLIB::POW_F128] = "powl";
173 Names[RTLIB::POW_PPCF128] = "powl";
174 Names[RTLIB::CEIL_F32] = "ceilf";
175 Names[RTLIB::CEIL_F64] = "ceil";
176 Names[RTLIB::CEIL_F80] = "ceill";
177 Names[RTLIB::CEIL_F128] = "ceill";
178 Names[RTLIB::CEIL_PPCF128] = "ceill";
179 Names[RTLIB::TRUNC_F32] = "truncf";
180 Names[RTLIB::TRUNC_F64] = "trunc";
181 Names[RTLIB::TRUNC_F80] = "truncl";
182 Names[RTLIB::TRUNC_F128] = "truncl";
183 Names[RTLIB::TRUNC_PPCF128] = "truncl";
184 Names[RTLIB::RINT_F32] = "rintf";
185 Names[RTLIB::RINT_F64] = "rint";
186 Names[RTLIB::RINT_F80] = "rintl";
187 Names[RTLIB::RINT_F128] = "rintl";
188 Names[RTLIB::RINT_PPCF128] = "rintl";
189 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
190 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
191 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
192 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
193 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
194 Names[RTLIB::FLOOR_F32] = "floorf";
195 Names[RTLIB::FLOOR_F64] = "floor";
196 Names[RTLIB::FLOOR_F80] = "floorl";
197 Names[RTLIB::FLOOR_F128] = "floorl";
198 Names[RTLIB::FLOOR_PPCF128] = "floorl";
199 Names[RTLIB::COPYSIGN_F32] = "copysignf";
200 Names[RTLIB::COPYSIGN_F64] = "copysign";
201 Names[RTLIB::COPYSIGN_F80] = "copysignl";
202 Names[RTLIB::COPYSIGN_F128] = "copysignl";
203 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
204 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
205 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
206 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
207 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
208 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
209 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
210 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
211 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
212 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
213 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
214 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
215 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
216 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
217 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
218 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
219 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
220 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
221 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
222 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
223 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
224 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
225 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
226 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
227 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
228 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
229 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
230 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
231 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
232 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
233 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
234 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
235 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
236 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
237 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
238 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
239 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
240 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
241 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
242 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
243 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
244 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
245 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
246 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
247 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
248 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
249 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
250 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
251 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
252 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
253 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
254 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
255 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
256 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
257 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
258 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
259 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
260 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
261 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
262 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
263 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
264 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
265 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
266 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
267 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
268 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
269 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
270 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
271 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
272 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
273 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
274 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
275 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
276 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
277 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
278 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
279 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
280 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
281 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
282 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
283 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
284 Names[RTLIB::OEQ_F32] = "__eqsf2";
285 Names[RTLIB::OEQ_F64] = "__eqdf2";
286 Names[RTLIB::OEQ_F128] = "__eqtf2";
287 Names[RTLIB::UNE_F32] = "__nesf2";
288 Names[RTLIB::UNE_F64] = "__nedf2";
289 Names[RTLIB::UNE_F128] = "__netf2";
290 Names[RTLIB::OGE_F32] = "__gesf2";
291 Names[RTLIB::OGE_F64] = "__gedf2";
292 Names[RTLIB::OGE_F128] = "__getf2";
293 Names[RTLIB::OLT_F32] = "__ltsf2";
294 Names[RTLIB::OLT_F64] = "__ltdf2";
295 Names[RTLIB::OLT_F128] = "__lttf2";
296 Names[RTLIB::OLE_F32] = "__lesf2";
297 Names[RTLIB::OLE_F64] = "__ledf2";
298 Names[RTLIB::OLE_F128] = "__letf2";
299 Names[RTLIB::OGT_F32] = "__gtsf2";
300 Names[RTLIB::OGT_F64] = "__gtdf2";
301 Names[RTLIB::OGT_F128] = "__gttf2";
302 Names[RTLIB::UO_F32] = "__unordsf2";
303 Names[RTLIB::UO_F64] = "__unorddf2";
304 Names[RTLIB::UO_F128] = "__unordtf2";
305 Names[RTLIB::O_F32] = "__unordsf2";
306 Names[RTLIB::O_F64] = "__unorddf2";
307 Names[RTLIB::O_F128] = "__unordtf2";
308 Names[RTLIB::MEMCPY] = "memcpy";
309 Names[RTLIB::MEMMOVE] = "memmove";
310 Names[RTLIB::MEMSET] = "memset";
311 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
312 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
313 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
314 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
315 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
316 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
317 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
318 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
319 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
320 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
321 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
322 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
323 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
324 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
325 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
326 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
327 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
328 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
329 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
330 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
331 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
332 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
333 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
334 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
335 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
336 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
337 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
338 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
339 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
340 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
341 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
342 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
343 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
346 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
348 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
349 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
350 CCs[i] = CallingConv::C;
354 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
355 /// UNKNOWN_LIBCALL if there is none.
356 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
357 if (OpVT == MVT::f32) {
358 if (RetVT == MVT::f64)
359 return FPEXT_F32_F64;
360 if (RetVT == MVT::f128)
361 return FPEXT_F32_F128;
362 } else if (OpVT == MVT::f64) {
363 if (RetVT == MVT::f128)
364 return FPEXT_F64_F128;
367 return UNKNOWN_LIBCALL;
370 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
371 /// UNKNOWN_LIBCALL if there is none.
372 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
373 if (RetVT == MVT::f32) {
374 if (OpVT == MVT::f64)
375 return FPROUND_F64_F32;
376 if (OpVT == MVT::f80)
377 return FPROUND_F80_F32;
378 if (OpVT == MVT::f128)
379 return FPROUND_F128_F32;
380 if (OpVT == MVT::ppcf128)
381 return FPROUND_PPCF128_F32;
382 } else if (RetVT == MVT::f64) {
383 if (OpVT == MVT::f80)
384 return FPROUND_F80_F64;
385 if (OpVT == MVT::f128)
386 return FPROUND_F128_F64;
387 if (OpVT == MVT::ppcf128)
388 return FPROUND_PPCF128_F64;
391 return UNKNOWN_LIBCALL;
394 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
395 /// UNKNOWN_LIBCALL if there is none.
396 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
397 if (OpVT == MVT::f32) {
398 if (RetVT == MVT::i8)
399 return FPTOSINT_F32_I8;
400 if (RetVT == MVT::i16)
401 return FPTOSINT_F32_I16;
402 if (RetVT == MVT::i32)
403 return FPTOSINT_F32_I32;
404 if (RetVT == MVT::i64)
405 return FPTOSINT_F32_I64;
406 if (RetVT == MVT::i128)
407 return FPTOSINT_F32_I128;
408 } else if (OpVT == MVT::f64) {
409 if (RetVT == MVT::i8)
410 return FPTOSINT_F64_I8;
411 if (RetVT == MVT::i16)
412 return FPTOSINT_F64_I16;
413 if (RetVT == MVT::i32)
414 return FPTOSINT_F64_I32;
415 if (RetVT == MVT::i64)
416 return FPTOSINT_F64_I64;
417 if (RetVT == MVT::i128)
418 return FPTOSINT_F64_I128;
419 } else if (OpVT == MVT::f80) {
420 if (RetVT == MVT::i32)
421 return FPTOSINT_F80_I32;
422 if (RetVT == MVT::i64)
423 return FPTOSINT_F80_I64;
424 if (RetVT == MVT::i128)
425 return FPTOSINT_F80_I128;
426 } else if (OpVT == MVT::f128) {
427 if (RetVT == MVT::i32)
428 return FPTOSINT_F128_I32;
429 if (RetVT == MVT::i64)
430 return FPTOSINT_F128_I64;
431 if (RetVT == MVT::i128)
432 return FPTOSINT_F128_I128;
433 } else if (OpVT == MVT::ppcf128) {
434 if (RetVT == MVT::i32)
435 return FPTOSINT_PPCF128_I32;
436 if (RetVT == MVT::i64)
437 return FPTOSINT_PPCF128_I64;
438 if (RetVT == MVT::i128)
439 return FPTOSINT_PPCF128_I128;
441 return UNKNOWN_LIBCALL;
444 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
445 /// UNKNOWN_LIBCALL if there is none.
446 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
447 if (OpVT == MVT::f32) {
448 if (RetVT == MVT::i8)
449 return FPTOUINT_F32_I8;
450 if (RetVT == MVT::i16)
451 return FPTOUINT_F32_I16;
452 if (RetVT == MVT::i32)
453 return FPTOUINT_F32_I32;
454 if (RetVT == MVT::i64)
455 return FPTOUINT_F32_I64;
456 if (RetVT == MVT::i128)
457 return FPTOUINT_F32_I128;
458 } else if (OpVT == MVT::f64) {
459 if (RetVT == MVT::i8)
460 return FPTOUINT_F64_I8;
461 if (RetVT == MVT::i16)
462 return FPTOUINT_F64_I16;
463 if (RetVT == MVT::i32)
464 return FPTOUINT_F64_I32;
465 if (RetVT == MVT::i64)
466 return FPTOUINT_F64_I64;
467 if (RetVT == MVT::i128)
468 return FPTOUINT_F64_I128;
469 } else if (OpVT == MVT::f80) {
470 if (RetVT == MVT::i32)
471 return FPTOUINT_F80_I32;
472 if (RetVT == MVT::i64)
473 return FPTOUINT_F80_I64;
474 if (RetVT == MVT::i128)
475 return FPTOUINT_F80_I128;
476 } else if (OpVT == MVT::f128) {
477 if (RetVT == MVT::i32)
478 return FPTOUINT_F128_I32;
479 if (RetVT == MVT::i64)
480 return FPTOUINT_F128_I64;
481 if (RetVT == MVT::i128)
482 return FPTOUINT_F128_I128;
483 } else if (OpVT == MVT::ppcf128) {
484 if (RetVT == MVT::i32)
485 return FPTOUINT_PPCF128_I32;
486 if (RetVT == MVT::i64)
487 return FPTOUINT_PPCF128_I64;
488 if (RetVT == MVT::i128)
489 return FPTOUINT_PPCF128_I128;
491 return UNKNOWN_LIBCALL;
494 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
495 /// UNKNOWN_LIBCALL if there is none.
496 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
497 if (OpVT == MVT::i32) {
498 if (RetVT == MVT::f32)
499 return SINTTOFP_I32_F32;
500 if (RetVT == MVT::f64)
501 return SINTTOFP_I32_F64;
502 if (RetVT == MVT::f80)
503 return SINTTOFP_I32_F80;
504 if (RetVT == MVT::f128)
505 return SINTTOFP_I32_F128;
506 if (RetVT == MVT::ppcf128)
507 return SINTTOFP_I32_PPCF128;
508 } else if (OpVT == MVT::i64) {
509 if (RetVT == MVT::f32)
510 return SINTTOFP_I64_F32;
511 if (RetVT == MVT::f64)
512 return SINTTOFP_I64_F64;
513 if (RetVT == MVT::f80)
514 return SINTTOFP_I64_F80;
515 if (RetVT == MVT::f128)
516 return SINTTOFP_I64_F128;
517 if (RetVT == MVT::ppcf128)
518 return SINTTOFP_I64_PPCF128;
519 } else if (OpVT == MVT::i128) {
520 if (RetVT == MVT::f32)
521 return SINTTOFP_I128_F32;
522 if (RetVT == MVT::f64)
523 return SINTTOFP_I128_F64;
524 if (RetVT == MVT::f80)
525 return SINTTOFP_I128_F80;
526 if (RetVT == MVT::f128)
527 return SINTTOFP_I128_F128;
528 if (RetVT == MVT::ppcf128)
529 return SINTTOFP_I128_PPCF128;
531 return UNKNOWN_LIBCALL;
534 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
535 /// UNKNOWN_LIBCALL if there is none.
536 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
537 if (OpVT == MVT::i32) {
538 if (RetVT == MVT::f32)
539 return UINTTOFP_I32_F32;
540 if (RetVT == MVT::f64)
541 return UINTTOFP_I32_F64;
542 if (RetVT == MVT::f80)
543 return UINTTOFP_I32_F80;
544 if (RetVT == MVT::f128)
545 return UINTTOFP_I32_F128;
546 if (RetVT == MVT::ppcf128)
547 return UINTTOFP_I32_PPCF128;
548 } else if (OpVT == MVT::i64) {
549 if (RetVT == MVT::f32)
550 return UINTTOFP_I64_F32;
551 if (RetVT == MVT::f64)
552 return UINTTOFP_I64_F64;
553 if (RetVT == MVT::f80)
554 return UINTTOFP_I64_F80;
555 if (RetVT == MVT::f128)
556 return UINTTOFP_I64_F128;
557 if (RetVT == MVT::ppcf128)
558 return UINTTOFP_I64_PPCF128;
559 } else if (OpVT == MVT::i128) {
560 if (RetVT == MVT::f32)
561 return UINTTOFP_I128_F32;
562 if (RetVT == MVT::f64)
563 return UINTTOFP_I128_F64;
564 if (RetVT == MVT::f80)
565 return UINTTOFP_I128_F80;
566 if (RetVT == MVT::f128)
567 return UINTTOFP_I128_F128;
568 if (RetVT == MVT::ppcf128)
569 return UINTTOFP_I128_PPCF128;
571 return UNKNOWN_LIBCALL;
574 /// InitCmpLibcallCCs - Set default comparison libcall CC.
576 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
577 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
578 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
579 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
580 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
581 CCs[RTLIB::UNE_F32] = ISD::SETNE;
582 CCs[RTLIB::UNE_F64] = ISD::SETNE;
583 CCs[RTLIB::UNE_F128] = ISD::SETNE;
584 CCs[RTLIB::OGE_F32] = ISD::SETGE;
585 CCs[RTLIB::OGE_F64] = ISD::SETGE;
586 CCs[RTLIB::OGE_F128] = ISD::SETGE;
587 CCs[RTLIB::OLT_F32] = ISD::SETLT;
588 CCs[RTLIB::OLT_F64] = ISD::SETLT;
589 CCs[RTLIB::OLT_F128] = ISD::SETLT;
590 CCs[RTLIB::OLE_F32] = ISD::SETLE;
591 CCs[RTLIB::OLE_F64] = ISD::SETLE;
592 CCs[RTLIB::OLE_F128] = ISD::SETLE;
593 CCs[RTLIB::OGT_F32] = ISD::SETGT;
594 CCs[RTLIB::OGT_F64] = ISD::SETGT;
595 CCs[RTLIB::OGT_F128] = ISD::SETGT;
596 CCs[RTLIB::UO_F32] = ISD::SETNE;
597 CCs[RTLIB::UO_F64] = ISD::SETNE;
598 CCs[RTLIB::UO_F128] = ISD::SETNE;
599 CCs[RTLIB::O_F32] = ISD::SETEQ;
600 CCs[RTLIB::O_F64] = ISD::SETEQ;
601 CCs[RTLIB::O_F128] = ISD::SETEQ;
604 /// NOTE: The constructor takes ownership of TLOF.
605 TargetLowering::TargetLowering(const TargetMachine &tm,
606 const TargetLoweringObjectFile *tlof)
607 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) {
608 // All operations default to being supported.
609 memset(OpActions, 0, sizeof(OpActions));
610 memset(LoadExtActions, 0, sizeof(LoadExtActions));
611 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
612 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
613 memset(CondCodeActions, 0, sizeof(CondCodeActions));
615 // Set default actions for various operations.
616 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
617 // Default all indexed load / store to expand.
618 for (unsigned IM = (unsigned)ISD::PRE_INC;
619 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
620 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
621 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
624 // These operations default to expand.
625 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
626 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
629 // Most targets ignore the @llvm.prefetch intrinsic.
630 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
632 // ConstantFP nodes default to expand. Targets can either change this to
633 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
634 // to optimize expansions for certain constants.
635 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
636 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
637 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
638 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
639 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
641 // These library functions default to expand.
642 setOperationAction(ISD::FLOG , MVT::f16, Expand);
643 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
644 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
645 setOperationAction(ISD::FEXP , MVT::f16, Expand);
646 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
650 setOperationAction(ISD::FRINT, MVT::f16, Expand);
651 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
652 setOperationAction(ISD::FLOG , MVT::f32, Expand);
653 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
654 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
655 setOperationAction(ISD::FEXP , MVT::f32, Expand);
656 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
657 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
658 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
659 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
660 setOperationAction(ISD::FRINT, MVT::f32, Expand);
661 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
662 setOperationAction(ISD::FLOG , MVT::f64, Expand);
663 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
664 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
665 setOperationAction(ISD::FEXP , MVT::f64, Expand);
666 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
667 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
668 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
669 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
670 setOperationAction(ISD::FRINT, MVT::f64, Expand);
671 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
672 setOperationAction(ISD::FLOG , MVT::f128, Expand);
673 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
674 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
675 setOperationAction(ISD::FEXP , MVT::f128, Expand);
676 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
677 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
678 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
679 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
680 setOperationAction(ISD::FRINT, MVT::f128, Expand);
681 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
683 // Default ISD::TRAP to expand (which turns it into abort).
684 setOperationAction(ISD::TRAP, MVT::Other, Expand);
686 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
687 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
689 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
691 IsLittleEndian = TD->isLittleEndian();
692 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0));
693 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
694 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
695 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
696 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
697 = maxStoresPerMemmoveOptSize = 4;
698 benefitFromCodePlacementOpt = false;
699 UseUnderscoreSetJmp = false;
700 UseUnderscoreLongJmp = false;
701 SelectIsExpensive = false;
702 IntDivIsCheap = false;
703 Pow2DivIsCheap = false;
704 JumpIsExpensive = false;
705 predictableSelectIsExpensive = false;
706 StackPointerRegisterToSaveRestore = 0;
707 ExceptionPointerRegister = 0;
708 ExceptionSelectorRegister = 0;
709 BooleanContents = UndefinedBooleanContent;
710 BooleanVectorContents = UndefinedBooleanContent;
711 SchedPreferenceInfo = Sched::ILP;
713 JumpBufAlignment = 0;
714 MinFunctionAlignment = 0;
715 PrefFunctionAlignment = 0;
716 PrefLoopAlignment = 0;
717 MinStackArgumentAlignment = 1;
718 ShouldFoldAtomicFences = false;
719 InsertFencesForAtomic = false;
720 SupportJumpTables = true;
721 MinimumJumpTableEntries = 4;
723 InitLibcallNames(LibcallRoutineNames);
724 InitCmpLibcallCCs(CmpLibcallCCs);
725 InitLibcallCallingConvs(LibcallCallingConvs);
728 TargetLowering::~TargetLowering() {
732 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
733 return MVT::getIntegerVT(8*TD->getPointerSize(0));
736 /// canOpTrap - Returns true if the operation can trap for the value type.
737 /// VT must be a legal type.
738 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
739 assert(isTypeLegal(VT));
754 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
755 unsigned &NumIntermediates,
757 TargetLowering *TLI) {
758 // Figure out the right, legal destination reg to copy into.
759 unsigned NumElts = VT.getVectorNumElements();
760 MVT EltTy = VT.getVectorElementType();
762 unsigned NumVectorRegs = 1;
764 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
765 // could break down into LHS/RHS like LegalizeDAG does.
766 if (!isPowerOf2_32(NumElts)) {
767 NumVectorRegs = NumElts;
771 // Divide the input until we get to a supported size. This will always
772 // end with a scalar if the target doesn't support vectors.
773 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
778 NumIntermediates = NumVectorRegs;
780 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
781 if (!TLI->isTypeLegal(NewVT))
783 IntermediateVT = NewVT;
785 unsigned NewVTSize = NewVT.getSizeInBits();
787 // Convert sizes such as i33 to i64.
788 if (!isPowerOf2_32(NewVTSize))
789 NewVTSize = NextPowerOf2(NewVTSize);
791 MVT DestVT = TLI->getRegisterType(NewVT);
793 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
794 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
796 // Otherwise, promotion or legal types use the same number of registers as
797 // the vector decimated to the appropriate level.
798 return NumVectorRegs;
801 /// isLegalRC - Return true if the value types that can be represented by the
802 /// specified register class are all legal.
803 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
804 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
812 /// findRepresentativeClass - Return the largest legal super-reg register class
813 /// of the register class for the specified type and its associated "cost".
814 std::pair<const TargetRegisterClass*, uint8_t>
815 TargetLowering::findRepresentativeClass(MVT VT) const {
816 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
817 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
819 return std::make_pair(RC, 0);
821 // Compute the set of all super-register classes.
822 BitVector SuperRegRC(TRI->getNumRegClasses());
823 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
824 SuperRegRC.setBitsInMask(RCI.getMask());
826 // Find the first legal register class with the largest spill size.
827 const TargetRegisterClass *BestRC = RC;
828 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
829 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
830 // We want the largest possible spill size.
831 if (SuperRC->getSize() <= BestRC->getSize())
833 if (!isLegalRC(SuperRC))
837 return std::make_pair(BestRC, 1);
840 /// computeRegisterProperties - Once all of the register classes are added,
841 /// this allows us to compute derived properties we expose.
842 void TargetLowering::computeRegisterProperties() {
843 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
844 "Too many value types for ValueTypeActions to hold!");
846 // Everything defaults to needing one register.
847 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
848 NumRegistersForVT[i] = 1;
849 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
851 // ...except isVoid, which doesn't need any registers.
852 NumRegistersForVT[MVT::isVoid] = 0;
854 // Find the largest integer register class.
855 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
856 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
857 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
859 // Every integer value type larger than this largest register takes twice as
860 // many registers to represent as the previous ValueType.
861 for (unsigned ExpandedReg = LargestIntReg + 1;
862 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
863 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
864 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
865 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
866 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
870 // Inspect all of the ValueType's smaller than the largest integer
871 // register to see which ones need promotion.
872 unsigned LegalIntReg = LargestIntReg;
873 for (unsigned IntReg = LargestIntReg - 1;
874 IntReg >= (unsigned)MVT::i1; --IntReg) {
875 MVT IVT = (MVT::SimpleValueType)IntReg;
876 if (isTypeLegal(IVT)) {
877 LegalIntReg = IntReg;
879 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
880 (const MVT::SimpleValueType)LegalIntReg;
881 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
885 // ppcf128 type is really two f64's.
886 if (!isTypeLegal(MVT::ppcf128)) {
887 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
888 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
889 TransformToType[MVT::ppcf128] = MVT::f64;
890 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
893 // Decide how to handle f64. If the target does not have native f64 support,
894 // expand it to i64 and we will be generating soft float library calls.
895 if (!isTypeLegal(MVT::f64)) {
896 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
897 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
898 TransformToType[MVT::f64] = MVT::i64;
899 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
902 // Decide how to handle f32. If the target does not have native support for
903 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
904 if (!isTypeLegal(MVT::f32)) {
905 if (isTypeLegal(MVT::f64)) {
906 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
907 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
908 TransformToType[MVT::f32] = MVT::f64;
909 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
911 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
912 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
913 TransformToType[MVT::f32] = MVT::i32;
914 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
918 // Loop over all of the vector value types to see which need transformations.
919 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
920 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
921 MVT VT = (MVT::SimpleValueType)i;
922 if (isTypeLegal(VT)) continue;
924 // Determine if there is a legal wider type. If so, we should promote to
925 // that wider vector type.
926 MVT EltVT = VT.getVectorElementType();
927 unsigned NElts = VT.getVectorNumElements();
928 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) {
929 bool IsLegalWiderType = false;
930 // First try to promote the elements of integer vectors. If no legal
931 // promotion was found, fallback to the widen-vector method.
932 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
933 MVT SVT = (MVT::SimpleValueType)nVT;
934 // Promote vectors of integers to vectors with the same number
935 // of elements, with a wider element type.
936 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
937 && SVT.getVectorNumElements() == NElts &&
938 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
939 TransformToType[i] = SVT;
940 RegisterTypeForVT[i] = SVT;
941 NumRegistersForVT[i] = 1;
942 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
943 IsLegalWiderType = true;
948 if (IsLegalWiderType) continue;
950 // Try to widen the vector.
951 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
952 MVT SVT = (MVT::SimpleValueType)nVT;
953 if (SVT.getVectorElementType() == EltVT &&
954 SVT.getVectorNumElements() > NElts &&
956 TransformToType[i] = SVT;
957 RegisterTypeForVT[i] = SVT;
958 NumRegistersForVT[i] = 1;
959 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
960 IsLegalWiderType = true;
964 if (IsLegalWiderType) continue;
969 unsigned NumIntermediates;
970 NumRegistersForVT[i] =
971 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
973 RegisterTypeForVT[i] = RegisterVT;
975 MVT NVT = VT.getPow2VectorType();
977 // Type is already a power of 2. The default action is to split.
978 TransformToType[i] = MVT::Other;
979 unsigned NumElts = VT.getVectorNumElements();
980 ValueTypeActions.setTypeAction(VT,
981 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
983 TransformToType[i] = NVT;
984 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
988 // Determine the 'representative' register class for each value type.
989 // An representative register class is the largest (meaning one which is
990 // not a sub-register class / subreg register class) legal register class for
991 // a group of value types. For example, on i386, i8, i16, and i32
992 // representative would be GR32; while on x86_64 it's GR64.
993 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
994 const TargetRegisterClass* RRC;
996 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
997 RepRegClassForVT[i] = RRC;
998 RepRegClassCostForVT[i] = Cost;
1002 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
1006 EVT TargetLowering::getSetCCResultType(EVT VT) const {
1007 assert(!VT.isVector() && "No default SetCC type for vectors!");
1008 return getPointerTy(0).SimpleTy;
1011 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
1012 return MVT::i32; // return the default value
1015 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1016 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1017 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1018 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1020 /// This method returns the number of registers needed, and the VT for each
1021 /// register. It also returns the VT and quantity of the intermediate values
1022 /// before they are promoted/expanded.
1024 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1025 EVT &IntermediateVT,
1026 unsigned &NumIntermediates,
1027 MVT &RegisterVT) const {
1028 unsigned NumElts = VT.getVectorNumElements();
1030 // If there is a wider vector type with the same element type as this one,
1031 // or a promoted vector type that has the same number of elements which
1032 // are wider, then we should convert to that legal vector type.
1033 // This handles things like <2 x float> -> <4 x float> and
1034 // <4 x i1> -> <4 x i32>.
1035 LegalizeTypeAction TA = getTypeAction(Context, VT);
1036 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1037 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1038 if (isTypeLegal(RegisterEVT)) {
1039 IntermediateVT = RegisterEVT;
1040 RegisterVT = RegisterEVT.getSimpleVT();
1041 NumIntermediates = 1;
1046 // Figure out the right, legal destination reg to copy into.
1047 EVT EltTy = VT.getVectorElementType();
1049 unsigned NumVectorRegs = 1;
1051 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1052 // could break down into LHS/RHS like LegalizeDAG does.
1053 if (!isPowerOf2_32(NumElts)) {
1054 NumVectorRegs = NumElts;
1058 // Divide the input until we get to a supported size. This will always
1059 // end with a scalar if the target doesn't support vectors.
1060 while (NumElts > 1 && !isTypeLegal(
1061 EVT::getVectorVT(Context, EltTy, NumElts))) {
1063 NumVectorRegs <<= 1;
1066 NumIntermediates = NumVectorRegs;
1068 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1069 if (!isTypeLegal(NewVT))
1071 IntermediateVT = NewVT;
1073 MVT DestVT = getRegisterType(Context, NewVT);
1074 RegisterVT = DestVT;
1075 unsigned NewVTSize = NewVT.getSizeInBits();
1077 // Convert sizes such as i33 to i64.
1078 if (!isPowerOf2_32(NewVTSize))
1079 NewVTSize = NextPowerOf2(NewVTSize);
1081 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1082 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1084 // Otherwise, promotion or legal types use the same number of registers as
1085 // the vector decimated to the appropriate level.
1086 return NumVectorRegs;
1089 /// Get the EVTs and ArgFlags collections that represent the legalized return
1090 /// type of the given function. This does not require a DAG or a return value,
1091 /// and is suitable for use before any DAGs for the function are constructed.
1092 /// TODO: Move this out of TargetLowering.cpp.
1093 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1094 SmallVectorImpl<ISD::OutputArg> &Outs,
1095 const TargetLowering &TLI) {
1096 SmallVector<EVT, 4> ValueVTs;
1097 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1098 unsigned NumValues = ValueVTs.size();
1099 if (NumValues == 0) return;
1101 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1102 EVT VT = ValueVTs[j];
1103 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1105 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1106 ExtendKind = ISD::SIGN_EXTEND;
1107 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1108 ExtendKind = ISD::ZERO_EXTEND;
1110 // FIXME: C calling convention requires the return type to be promoted to
1111 // at least 32-bit. But this is not necessary for non-C calling
1112 // conventions. The frontend should mark functions whose return values
1113 // require promoting with signext or zeroext attributes.
1114 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1115 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1116 if (VT.bitsLT(MinVT))
1120 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1121 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1123 // 'inreg' on function refers to return value
1124 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1125 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1128 // Propagate extension type if any
1129 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1131 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1134 for (unsigned i = 0; i < NumParts; ++i)
1135 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0));
1139 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1140 /// function arguments in the caller parameter area. This is the actual
1141 /// alignment, not its logarithm.
1142 unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
1143 return TD->getCallFrameTypeAlignment(Ty);
1146 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1147 /// current function. The returned value is a member of the
1148 /// MachineJumpTableInfo::JTEntryKind enum.
1149 unsigned TargetLowering::getJumpTableEncoding() const {
1150 // In non-pic modes, just use the address of a block.
1151 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1152 return MachineJumpTableInfo::EK_BlockAddress;
1154 // In PIC mode, if the target supports a GPRel32 directive, use it.
1155 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1156 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1158 // Otherwise, use a label difference.
1159 return MachineJumpTableInfo::EK_LabelDifference32;
1162 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1163 SelectionDAG &DAG) const {
1164 // If our PIC model is GP relative, use the global offset table as the base.
1165 unsigned JTEncoding = getJumpTableEncoding();
1167 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
1168 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
1169 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
1174 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1175 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1178 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1179 unsigned JTI,MCContext &Ctx) const{
1180 // The normal PIC reloc base is the label at the start of the jump table.
1181 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1185 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1186 // Assume that everything is safe in static mode.
1187 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1190 // In dynamic-no-pic mode, assume that known defined values are safe.
1191 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1193 !GA->getGlobal()->isDeclaration() &&
1194 !GA->getGlobal()->isWeakForLinker())
1197 // Otherwise assume nothing is safe.
1201 //===----------------------------------------------------------------------===//
1202 // TargetTransformInfo Helpers
1203 //===----------------------------------------------------------------------===//
1205 int TargetLowering::InstructionOpcodeToISD(unsigned Opcode) const {
1206 enum InstructionOpcodes {
1207 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1208 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1209 #include "llvm/IR/Instruction.def"
1211 switch (static_cast<InstructionOpcodes>(Opcode)) {
1214 case Switch: return 0;
1215 case IndirectBr: return 0;
1216 case Invoke: return 0;
1217 case Resume: return 0;
1218 case Unreachable: return 0;
1219 case Add: return ISD::ADD;
1220 case FAdd: return ISD::FADD;
1221 case Sub: return ISD::SUB;
1222 case FSub: return ISD::FSUB;
1223 case Mul: return ISD::MUL;
1224 case FMul: return ISD::FMUL;
1225 case UDiv: return ISD::UDIV;
1226 case SDiv: return ISD::UDIV;
1227 case FDiv: return ISD::FDIV;
1228 case URem: return ISD::UREM;
1229 case SRem: return ISD::SREM;
1230 case FRem: return ISD::FREM;
1231 case Shl: return ISD::SHL;
1232 case LShr: return ISD::SRL;
1233 case AShr: return ISD::SRA;
1234 case And: return ISD::AND;
1235 case Or: return ISD::OR;
1236 case Xor: return ISD::XOR;
1237 case Alloca: return 0;
1238 case Load: return ISD::LOAD;
1239 case Store: return ISD::STORE;
1240 case GetElementPtr: return 0;
1241 case Fence: return 0;
1242 case AtomicCmpXchg: return 0;
1243 case AtomicRMW: return 0;
1244 case Trunc: return ISD::TRUNCATE;
1245 case ZExt: return ISD::ZERO_EXTEND;
1246 case SExt: return ISD::SIGN_EXTEND;
1247 case FPToUI: return ISD::FP_TO_UINT;
1248 case FPToSI: return ISD::FP_TO_SINT;
1249 case UIToFP: return ISD::UINT_TO_FP;
1250 case SIToFP: return ISD::SINT_TO_FP;
1251 case FPTrunc: return ISD::FP_ROUND;
1252 case FPExt: return ISD::FP_EXTEND;
1253 case PtrToInt: return ISD::BITCAST;
1254 case IntToPtr: return ISD::BITCAST;
1255 case BitCast: return ISD::BITCAST;
1256 case ICmp: return ISD::SETCC;
1257 case FCmp: return ISD::SETCC;
1259 case Call: return 0;
1260 case Select: return ISD::SELECT;
1261 case UserOp1: return 0;
1262 case UserOp2: return 0;
1263 case VAArg: return 0;
1264 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1265 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1266 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1267 case ExtractValue: return ISD::MERGE_VALUES;
1268 case InsertValue: return ISD::MERGE_VALUES;
1269 case LandingPad: return 0;
1272 llvm_unreachable("Unknown instruction type encountered!");
1275 std::pair<unsigned, MVT>
1276 TargetLowering::getTypeLegalizationCost(Type *Ty) const {
1277 LLVMContext &C = Ty->getContext();
1278 EVT MTy = getValueType(Ty);
1281 // We keep legalizing the type until we find a legal kind. We assume that
1282 // the only operation that costs anything is the split. After splitting
1283 // we need to handle two types.
1285 LegalizeKind LK = getTypeConversion(C, MTy);
1287 if (LK.first == TypeLegal)
1288 return std::make_pair(Cost, MTy.getSimpleVT());
1290 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1293 // Keep legalizing the type.
1298 //===----------------------------------------------------------------------===//
1299 // Optimization Methods
1300 //===----------------------------------------------------------------------===//
1302 /// ShrinkDemandedConstant - Check to see if the specified operand of the
1303 /// specified instruction is a constant integer. If so, check to see if there
1304 /// are any bits set in the constant that are not demanded. If so, shrink the
1305 /// constant and return true.
1306 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1307 const APInt &Demanded) {
1308 DebugLoc dl = Op.getDebugLoc();
1310 // FIXME: ISD::SELECT, ISD::SELECT_CC
1311 switch (Op.getOpcode()) {
1316 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1317 if (!C) return false;
1319 if (Op.getOpcode() == ISD::XOR &&
1320 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1323 // if we can expand it to have all bits set, do it
1324 if (C->getAPIntValue().intersects(~Demanded)) {
1325 EVT VT = Op.getValueType();
1326 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1327 DAG.getConstant(Demanded &
1330 return CombineTo(Op, New);
1340 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1341 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1342 /// cast, but it could be generalized for targets with other types of
1343 /// implicit widening casts.
1345 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1347 const APInt &Demanded,
1349 assert(Op.getNumOperands() == 2 &&
1350 "ShrinkDemandedOp only supports binary operators!");
1351 assert(Op.getNode()->getNumValues() == 1 &&
1352 "ShrinkDemandedOp only supports nodes with one result!");
1354 // Don't do this if the node has another user, which may require the
1356 if (!Op.getNode()->hasOneUse())
1359 // Search for the smallest integer type with free casts to and from
1360 // Op's type. For expedience, just check power-of-2 integer types.
1361 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1362 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
1363 unsigned SmallVTBits = DemandedSize;
1364 if (!isPowerOf2_32(SmallVTBits))
1365 SmallVTBits = NextPowerOf2(SmallVTBits);
1366 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1367 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1368 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1369 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1370 // We found a type with free casts.
1371 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1372 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1373 Op.getNode()->getOperand(0)),
1374 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1375 Op.getNode()->getOperand(1)));
1376 bool NeedZext = DemandedSize > SmallVTBits;
1377 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
1378 dl, Op.getValueType(), X);
1379 return CombineTo(Op, Z);
1385 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1386 /// DemandedMask bits of the result of Op are ever used downstream. If we can
1387 /// use this information to simplify Op, create a new simplified DAG node and
1388 /// return true, returning the original and new nodes in Old and New. Otherwise,
1389 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
1390 /// the expression (used to simplify the caller). The KnownZero/One bits may
1391 /// only be accurate for those bits in the DemandedMask.
1392 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1393 const APInt &DemandedMask,
1396 TargetLoweringOpt &TLO,
1397 unsigned Depth) const {
1398 unsigned BitWidth = DemandedMask.getBitWidth();
1399 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1400 "Mask size mismatches value type size!");
1401 APInt NewMask = DemandedMask;
1402 DebugLoc dl = Op.getDebugLoc();
1404 // Don't know anything.
1405 KnownZero = KnownOne = APInt(BitWidth, 0);
1407 // Other users may use these bits.
1408 if (!Op.getNode()->hasOneUse()) {
1410 // If not at the root, Just compute the KnownZero/KnownOne bits to
1411 // simplify things downstream.
1412 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1415 // If this is the root being simplified, allow it to have multiple uses,
1416 // just set the NewMask to all bits.
1417 NewMask = APInt::getAllOnesValue(BitWidth);
1418 } else if (DemandedMask == 0) {
1419 // Not demanding any bits from Op.
1420 if (Op.getOpcode() != ISD::UNDEF)
1421 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1423 } else if (Depth == 6) { // Limit search depth.
1427 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1428 switch (Op.getOpcode()) {
1430 // We know all of the bits for a constant!
1431 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1432 KnownZero = ~KnownOne;
1433 return false; // Don't fall through, will infinitely loop.
1435 // If the RHS is a constant, check to see if the LHS would be zero without
1436 // using the bits from the RHS. Below, we use knowledge about the RHS to
1437 // simplify the LHS, here we're using information from the LHS to simplify
1439 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1440 APInt LHSZero, LHSOne;
1441 // Do not increment Depth here; that can cause an infinite loop.
1442 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
1443 // If the LHS already has zeros where RHSC does, this and is dead.
1444 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1445 return TLO.CombineTo(Op, Op.getOperand(0));
1446 // If any of the set bits in the RHS are known zero on the LHS, shrink
1448 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1452 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1453 KnownOne, TLO, Depth+1))
1455 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1456 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1457 KnownZero2, KnownOne2, TLO, Depth+1))
1459 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1461 // If all of the demanded bits are known one on one side, return the other.
1462 // These bits cannot contribute to the result of the 'and'.
1463 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1464 return TLO.CombineTo(Op, Op.getOperand(0));
1465 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1466 return TLO.CombineTo(Op, Op.getOperand(1));
1467 // If all of the demanded bits in the inputs are known zeros, return zero.
1468 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1469 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1470 // If the RHS is a constant, see if we can simplify it.
1471 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1473 // If the operation can be done in a smaller type, do so.
1474 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1477 // Output known-1 bits are only known if set in both the LHS & RHS.
1478 KnownOne &= KnownOne2;
1479 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1480 KnownZero |= KnownZero2;
1483 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1484 KnownOne, TLO, Depth+1))
1486 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1487 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1488 KnownZero2, KnownOne2, TLO, Depth+1))
1490 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1492 // If all of the demanded bits are known zero on one side, return the other.
1493 // These bits cannot contribute to the result of the 'or'.
1494 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1495 return TLO.CombineTo(Op, Op.getOperand(0));
1496 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1497 return TLO.CombineTo(Op, Op.getOperand(1));
1498 // If all of the potentially set bits on one side are known to be set on
1499 // the other side, just use the 'other' side.
1500 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1501 return TLO.CombineTo(Op, Op.getOperand(0));
1502 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1503 return TLO.CombineTo(Op, Op.getOperand(1));
1504 // If the RHS is a constant, see if we can simplify it.
1505 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1507 // If the operation can be done in a smaller type, do so.
1508 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1511 // Output known-0 bits are only known if clear in both the LHS & RHS.
1512 KnownZero &= KnownZero2;
1513 // Output known-1 are known to be set if set in either the LHS | RHS.
1514 KnownOne |= KnownOne2;
1517 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1518 KnownOne, TLO, Depth+1))
1520 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1521 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1522 KnownOne2, TLO, Depth+1))
1524 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1526 // If all of the demanded bits are known zero on one side, return the other.
1527 // These bits cannot contribute to the result of the 'xor'.
1528 if ((KnownZero & NewMask) == NewMask)
1529 return TLO.CombineTo(Op, Op.getOperand(0));
1530 if ((KnownZero2 & NewMask) == NewMask)
1531 return TLO.CombineTo(Op, Op.getOperand(1));
1532 // If the operation can be done in a smaller type, do so.
1533 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1536 // If all of the unknown bits are known to be zero on one side or the other
1537 // (but not both) turn this into an *inclusive* or.
1538 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1539 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1540 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1544 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1545 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1546 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1547 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1549 // If all of the demanded bits on one side are known, and all of the set
1550 // bits on that side are also known to be set on the other side, turn this
1551 // into an AND, as we know the bits will be cleared.
1552 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1553 // NB: it is okay if more bits are known than are requested
1554 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
1555 if (KnownOne == KnownOne2) { // set bits are the same on both sides
1556 EVT VT = Op.getValueType();
1557 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1558 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1559 Op.getOperand(0), ANDC));
1563 // If the RHS is a constant, see if we can simplify it.
1564 // for XOR, we prefer to force bits to 1 if they will make a -1.
1565 // if we can't force bits, try to shrink constant
1566 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1567 APInt Expanded = C->getAPIntValue() | (~NewMask);
1568 // if we can expand it to have all bits set, do it
1569 if (Expanded.isAllOnesValue()) {
1570 if (Expanded != C->getAPIntValue()) {
1571 EVT VT = Op.getValueType();
1572 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1573 TLO.DAG.getConstant(Expanded, VT));
1574 return TLO.CombineTo(Op, New);
1576 // if it already has all the bits set, nothing to change
1577 // but don't shrink either!
1578 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1583 KnownZero = KnownZeroOut;
1584 KnownOne = KnownOneOut;
1587 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1588 KnownOne, TLO, Depth+1))
1590 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1591 KnownOne2, TLO, Depth+1))
1593 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1594 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1596 // If the operands are constants, see if we can simplify them.
1597 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1600 // Only known if known in both the LHS and RHS.
1601 KnownOne &= KnownOne2;
1602 KnownZero &= KnownZero2;
1604 case ISD::SELECT_CC:
1605 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1606 KnownOne, TLO, Depth+1))
1608 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1609 KnownOne2, TLO, Depth+1))
1611 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1612 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1614 // If the operands are constants, see if we can simplify them.
1615 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1618 // Only known if known in both the LHS and RHS.
1619 KnownOne &= KnownOne2;
1620 KnownZero &= KnownZero2;
1623 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1624 unsigned ShAmt = SA->getZExtValue();
1625 SDValue InOp = Op.getOperand(0);
1627 // If the shift count is an invalid immediate, don't do anything.
1628 if (ShAmt >= BitWidth)
1631 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1632 // single shift. We can do this if the bottom bits (which are shifted
1633 // out) are never demanded.
1634 if (InOp.getOpcode() == ISD::SRL &&
1635 isa<ConstantSDNode>(InOp.getOperand(1))) {
1636 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1637 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1638 unsigned Opc = ISD::SHL;
1639 int Diff = ShAmt-C1;
1646 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1647 EVT VT = Op.getValueType();
1648 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1649 InOp.getOperand(0), NewSA));
1653 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1654 KnownZero, KnownOne, TLO, Depth+1))
1657 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1658 // are not demanded. This will likely allow the anyext to be folded away.
1659 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1660 SDValue InnerOp = InOp.getNode()->getOperand(0);
1661 EVT InnerVT = InnerOp.getValueType();
1662 unsigned InnerBits = InnerVT.getSizeInBits();
1663 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
1664 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1665 EVT ShTy = getShiftAmountTy(InnerVT);
1666 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1669 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1670 TLO.DAG.getConstant(ShAmt, ShTy));
1673 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1678 KnownZero <<= SA->getZExtValue();
1679 KnownOne <<= SA->getZExtValue();
1680 // low bits known zero.
1681 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1685 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1686 EVT VT = Op.getValueType();
1687 unsigned ShAmt = SA->getZExtValue();
1688 unsigned VTSize = VT.getSizeInBits();
1689 SDValue InOp = Op.getOperand(0);
1691 // If the shift count is an invalid immediate, don't do anything.
1692 if (ShAmt >= BitWidth)
1695 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1696 // single shift. We can do this if the top bits (which are shifted out)
1697 // are never demanded.
1698 if (InOp.getOpcode() == ISD::SHL &&
1699 isa<ConstantSDNode>(InOp.getOperand(1))) {
1700 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1701 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1702 unsigned Opc = ISD::SRL;
1703 int Diff = ShAmt-C1;
1710 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1711 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1712 InOp.getOperand(0), NewSA));
1716 // Compute the new bits that are at the top now.
1717 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1718 KnownZero, KnownOne, TLO, Depth+1))
1720 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1721 KnownZero = KnownZero.lshr(ShAmt);
1722 KnownOne = KnownOne.lshr(ShAmt);
1724 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1725 KnownZero |= HighBits; // High bits known zero.
1729 // If this is an arithmetic shift right and only the low-bit is set, we can
1730 // always convert this into a logical shr, even if the shift amount is
1731 // variable. The low bit of the shift cannot be an input sign bit unless
1732 // the shift amount is >= the size of the datatype, which is undefined.
1734 return TLO.CombineTo(Op,
1735 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1736 Op.getOperand(0), Op.getOperand(1)));
1738 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1739 EVT VT = Op.getValueType();
1740 unsigned ShAmt = SA->getZExtValue();
1742 // If the shift count is an invalid immediate, don't do anything.
1743 if (ShAmt >= BitWidth)
1746 APInt InDemandedMask = (NewMask << ShAmt);
1748 // If any of the demanded bits are produced by the sign extension, we also
1749 // demand the input sign bit.
1750 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1751 if (HighBits.intersects(NewMask))
1752 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1754 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1755 KnownZero, KnownOne, TLO, Depth+1))
1757 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1758 KnownZero = KnownZero.lshr(ShAmt);
1759 KnownOne = KnownOne.lshr(ShAmt);
1761 // Handle the sign bit, adjusted to where it is now in the mask.
1762 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1764 // If the input sign bit is known to be zero, or if none of the top bits
1765 // are demanded, turn this into an unsigned shift right.
1766 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1767 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1770 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1771 KnownOne |= HighBits;
1775 case ISD::SIGN_EXTEND_INREG: {
1776 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1778 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1779 // If we only care about the highest bit, don't bother shifting right.
1780 if (MsbMask == DemandedMask) {
1781 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1782 SDValue InOp = Op.getOperand(0);
1784 // Compute the correct shift amount type, which must be getShiftAmountTy
1785 // for scalar types after legalization.
1786 EVT ShiftAmtTy = Op.getValueType();
1787 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1788 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1790 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
1791 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1792 Op.getValueType(), InOp, ShiftAmt));
1795 // Sign extension. Compute the demanded bits in the result that are not
1796 // present in the input.
1798 APInt::getHighBitsSet(BitWidth,
1799 BitWidth - ExVT.getScalarType().getSizeInBits());
1801 // If none of the extended bits are demanded, eliminate the sextinreg.
1802 if ((NewBits & NewMask) == 0)
1803 return TLO.CombineTo(Op, Op.getOperand(0));
1806 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
1807 APInt InputDemandedBits =
1808 APInt::getLowBitsSet(BitWidth,
1809 ExVT.getScalarType().getSizeInBits()) &
1812 // Since the sign extended bits are demanded, we know that the sign
1814 InputDemandedBits |= InSignBit;
1816 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1817 KnownZero, KnownOne, TLO, Depth+1))
1819 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1821 // If the sign bit of the input is known set or clear, then we know the
1822 // top bits of the result.
1824 // If the input sign bit is known zero, convert this into a zero extension.
1825 if (KnownZero.intersects(InSignBit))
1826 return TLO.CombineTo(Op,
1827 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
1829 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1830 KnownOne |= NewBits;
1831 KnownZero &= ~NewBits;
1832 } else { // Input sign bit unknown
1833 KnownZero &= ~NewBits;
1834 KnownOne &= ~NewBits;
1838 case ISD::ZERO_EXTEND: {
1839 unsigned OperandBitWidth =
1840 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1841 APInt InMask = NewMask.trunc(OperandBitWidth);
1843 // If none of the top bits are demanded, convert this into an any_extend.
1845 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1846 if (!NewBits.intersects(NewMask))
1847 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1851 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1852 KnownZero, KnownOne, TLO, Depth+1))
1854 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1855 KnownZero = KnownZero.zext(BitWidth);
1856 KnownOne = KnownOne.zext(BitWidth);
1857 KnownZero |= NewBits;
1860 case ISD::SIGN_EXTEND: {
1861 EVT InVT = Op.getOperand(0).getValueType();
1862 unsigned InBits = InVT.getScalarType().getSizeInBits();
1863 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1864 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1865 APInt NewBits = ~InMask & NewMask;
1867 // If none of the top bits are demanded, convert this into an any_extend.
1869 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1873 // Since some of the sign extended bits are demanded, we know that the sign
1875 APInt InDemandedBits = InMask & NewMask;
1876 InDemandedBits |= InSignBit;
1877 InDemandedBits = InDemandedBits.trunc(InBits);
1879 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1880 KnownOne, TLO, Depth+1))
1882 KnownZero = KnownZero.zext(BitWidth);
1883 KnownOne = KnownOne.zext(BitWidth);
1885 // If the sign bit is known zero, convert this to a zero extend.
1886 if (KnownZero.intersects(InSignBit))
1887 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1891 // If the sign bit is known one, the top bits match.
1892 if (KnownOne.intersects(InSignBit)) {
1893 KnownOne |= NewBits;
1894 assert((KnownZero & NewBits) == 0);
1895 } else { // Otherwise, top bits aren't known.
1896 assert((KnownOne & NewBits) == 0);
1897 assert((KnownZero & NewBits) == 0);
1901 case ISD::ANY_EXTEND: {
1902 unsigned OperandBitWidth =
1903 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1904 APInt InMask = NewMask.trunc(OperandBitWidth);
1905 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1906 KnownZero, KnownOne, TLO, Depth+1))
1908 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1909 KnownZero = KnownZero.zext(BitWidth);
1910 KnownOne = KnownOne.zext(BitWidth);
1913 case ISD::TRUNCATE: {
1914 // Simplify the input, using demanded bit information, and compute the known
1915 // zero/one bits live out.
1916 unsigned OperandBitWidth =
1917 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1918 APInt TruncMask = NewMask.zext(OperandBitWidth);
1919 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1920 KnownZero, KnownOne, TLO, Depth+1))
1922 KnownZero = KnownZero.trunc(BitWidth);
1923 KnownOne = KnownOne.trunc(BitWidth);
1925 // If the input is only used by this truncate, see if we can shrink it based
1926 // on the known demanded bits.
1927 if (Op.getOperand(0).getNode()->hasOneUse()) {
1928 SDValue In = Op.getOperand(0);
1929 switch (In.getOpcode()) {
1932 // Shrink SRL by a constant if none of the high bits shifted in are
1934 if (TLO.LegalTypes() &&
1935 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1936 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1939 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1942 SDValue Shift = In.getOperand(1);
1943 if (TLO.LegalTypes()) {
1944 uint64_t ShVal = ShAmt->getZExtValue();
1946 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1949 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1950 OperandBitWidth - BitWidth);
1951 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1953 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1954 // None of the shifted in bits are needed. Add a truncate of the
1955 // shift input, then shift it.
1956 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1959 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1968 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1971 case ISD::AssertZext: {
1972 // AssertZext demands all of the high bits, plus any of the low bits
1973 // demanded by its users.
1974 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1975 APInt InMask = APInt::getLowBitsSet(BitWidth,
1976 VT.getSizeInBits());
1977 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1978 KnownZero, KnownOne, TLO, Depth+1))
1980 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1982 KnownZero |= ~InMask & NewMask;
1986 // If this is an FP->Int bitcast and if the sign bit is the only
1987 // thing demanded, turn this into a FGETSIGN.
1988 if (!TLO.LegalOperations() &&
1989 !Op.getValueType().isVector() &&
1990 !Op.getOperand(0).getValueType().isVector() &&
1991 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1992 Op.getOperand(0).getValueType().isFloatingPoint()) {
1993 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1994 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1995 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1996 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1997 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1998 // place. We expect the SHL to be eliminated by other optimizations.
1999 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
2000 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
2001 if (!OpVTLegal && OpVTSizeInBits > 32)
2002 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
2003 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
2004 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
2005 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
2014 // Add, Sub, and Mul don't demand any bits in positions beyond that
2015 // of the highest bit demanded of them.
2016 APInt LoMask = APInt::getLowBitsSet(BitWidth,
2017 BitWidth - NewMask.countLeadingZeros());
2018 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
2019 KnownOne2, TLO, Depth+1))
2021 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
2022 KnownOne2, TLO, Depth+1))
2024 // See if the operation should be performed at a smaller bit width.
2025 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
2030 // Just use ComputeMaskedBits to compute output bits.
2031 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
2035 // If we know the value of all of the demanded bits, return this as a
2037 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
2038 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
2043 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
2044 /// in Mask are known to be either zero or one and return them in the
2045 /// KnownZero/KnownOne bitsets.
2046 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
2049 const SelectionDAG &DAG,
2050 unsigned Depth) const {
2051 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2052 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2053 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2054 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2055 "Should use MaskedValueIsZero if you don't know whether Op"
2056 " is a target node!");
2057 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
2060 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
2061 /// targets that want to expose additional information about sign bits to the
2063 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
2064 unsigned Depth) const {
2065 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2066 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2067 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2068 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2069 "Should use ComputeNumSignBits if you don't know whether Op"
2070 " is a target node!");
2074 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
2075 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
2076 /// determine which bit is set.
2078 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
2079 // A left-shift of a constant one will have exactly one bit set, because
2080 // shifting the bit off the end is undefined.
2081 if (Val.getOpcode() == ISD::SHL)
2082 if (ConstantSDNode *C =
2083 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
2084 if (C->getAPIntValue() == 1)
2087 // Similarly, a right-shift of a constant sign-bit will have exactly
2089 if (Val.getOpcode() == ISD::SRL)
2090 if (ConstantSDNode *C =
2091 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
2092 if (C->getAPIntValue().isSignBit())
2095 // More could be done here, though the above checks are enough
2096 // to handle some common cases.
2098 // Fall back to ComputeMaskedBits to catch other known cases.
2099 EVT OpVT = Val.getValueType();
2100 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
2101 APInt KnownZero, KnownOne;
2102 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
2103 return (KnownZero.countPopulation() == BitWidth - 1) &&
2104 (KnownOne.countPopulation() == 1);
2107 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
2108 /// and cc. If it is unable to simplify it, return a null SDValue.
2110 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2111 ISD::CondCode Cond, bool foldBooleans,
2112 DAGCombinerInfo &DCI, DebugLoc dl) const {
2113 SelectionDAG &DAG = DCI.DAG;
2115 // These setcc operations always fold.
2119 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2121 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2124 // Ensure that the constant occurs on the RHS, and fold constant
2126 if (isa<ConstantSDNode>(N0.getNode()))
2127 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2129 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
2130 const APInt &C1 = N1C->getAPIntValue();
2132 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
2133 // equality comparison, then we're just comparing whether X itself is
2135 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
2136 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
2137 N0.getOperand(1).getOpcode() == ISD::Constant) {
2139 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2140 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2141 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
2142 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
2143 // (srl (ctlz x), 5) == 0 -> X != 0
2144 // (srl (ctlz x), 5) != 1 -> X != 0
2147 // (srl (ctlz x), 5) != 0 -> X == 0
2148 // (srl (ctlz x), 5) == 1 -> X == 0
2151 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2152 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
2158 // Look through truncs that don't change the value of a ctpop.
2159 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
2160 CTPOP = N0.getOperand(0);
2162 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
2163 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
2164 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
2165 EVT CTVT = CTPOP.getValueType();
2166 SDValue CTOp = CTPOP.getOperand(0);
2168 // (ctpop x) u< 2 -> (x & x-1) == 0
2169 // (ctpop x) u> 1 -> (x & x-1) != 0
2170 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
2171 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
2172 DAG.getConstant(1, CTVT));
2173 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
2174 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
2175 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
2178 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
2181 // (zext x) == C --> x == (trunc C)
2182 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
2183 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2184 unsigned MinBits = N0.getValueSizeInBits();
2186 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
2188 MinBits = N0->getOperand(0).getValueSizeInBits();
2189 PreZExt = N0->getOperand(0);
2190 } else if (N0->getOpcode() == ISD::AND) {
2191 // DAGCombine turns costly ZExts into ANDs
2192 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2193 if ((C->getAPIntValue()+1).isPowerOf2()) {
2194 MinBits = C->getAPIntValue().countTrailingOnes();
2195 PreZExt = N0->getOperand(0);
2197 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
2199 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2200 MinBits = LN0->getMemoryVT().getSizeInBits();
2205 // Make sure we're not losing bits from the constant.
2206 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2207 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2208 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2209 // Will get folded away.
2210 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2211 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2212 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2217 // If the LHS is '(and load, const)', the RHS is 0,
2218 // the test is for equality or unsigned, and all 1 bits of the const are
2219 // in the same partial word, see if we can shorten the load.
2220 if (DCI.isBeforeLegalize() &&
2221 N0.getOpcode() == ISD::AND && C1 == 0 &&
2222 N0.getNode()->hasOneUse() &&
2223 isa<LoadSDNode>(N0.getOperand(0)) &&
2224 N0.getOperand(0).getNode()->hasOneUse() &&
2225 isa<ConstantSDNode>(N0.getOperand(1))) {
2226 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2228 unsigned bestWidth = 0, bestOffset = 0;
2229 if (!Lod->isVolatile() && Lod->isUnindexed()) {
2230 unsigned origWidth = N0.getValueType().getSizeInBits();
2231 unsigned maskWidth = origWidth;
2232 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2233 // 8 bits, but have to be careful...
2234 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2235 origWidth = Lod->getMemoryVT().getSizeInBits();
2237 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2238 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2239 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2240 for (unsigned offset=0; offset<origWidth/width; offset++) {
2241 if ((newMask & Mask) == Mask) {
2242 if (!TD->isLittleEndian())
2243 bestOffset = (origWidth/width - offset - 1) * (width/8);
2245 bestOffset = (uint64_t)offset * (width/8);
2246 bestMask = Mask.lshr(offset * (width/8) * 8);
2250 newMask = newMask << width;
2255 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2256 if (newVT.isRound()) {
2257 EVT PtrType = Lod->getOperand(1).getValueType();
2258 SDValue Ptr = Lod->getBasePtr();
2259 if (bestOffset != 0)
2260 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2261 DAG.getConstant(bestOffset, PtrType));
2262 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2263 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2264 Lod->getPointerInfo().getWithOffset(bestOffset),
2265 false, false, false, NewAlign);
2266 return DAG.getSetCC(dl, VT,
2267 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2268 DAG.getConstant(bestMask.trunc(bestWidth),
2270 DAG.getConstant(0LL, newVT), Cond);
2275 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2276 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2277 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2279 // If the comparison constant has bits in the upper part, the
2280 // zero-extended value could never match.
2281 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2282 C1.getBitWidth() - InSize))) {
2286 case ISD::SETEQ: return DAG.getConstant(0, VT);
2289 case ISD::SETNE: return DAG.getConstant(1, VT);
2292 // True if the sign bit of C1 is set.
2293 return DAG.getConstant(C1.isNegative(), VT);
2296 // True if the sign bit of C1 isn't set.
2297 return DAG.getConstant(C1.isNonNegative(), VT);
2303 // Otherwise, we can perform the comparison with the low bits.
2311 EVT newVT = N0.getOperand(0).getValueType();
2312 if (DCI.isBeforeLegalizeOps() ||
2313 (isOperationLegal(ISD::SETCC, newVT) &&
2314 getCondCodeAction(Cond, newVT.getSimpleVT())==Legal))
2315 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2316 DAG.getConstant(C1.trunc(InSize), newVT),
2321 break; // todo, be more careful with signed comparisons
2323 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2324 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2325 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2326 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2327 EVT ExtDstTy = N0.getValueType();
2328 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2330 // If the constant doesn't fit into the number of bits for the source of
2331 // the sign extension, it is impossible for both sides to be equal.
2332 if (C1.getMinSignedBits() > ExtSrcTyBits)
2333 return DAG.getConstant(Cond == ISD::SETNE, VT);
2336 EVT Op0Ty = N0.getOperand(0).getValueType();
2337 if (Op0Ty == ExtSrcTy) {
2338 ZextOp = N0.getOperand(0);
2340 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2341 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2342 DAG.getConstant(Imm, Op0Ty));
2344 if (!DCI.isCalledByLegalizer())
2345 DCI.AddToWorklist(ZextOp.getNode());
2346 // Otherwise, make this a use of a zext.
2347 return DAG.getSetCC(dl, VT, ZextOp,
2348 DAG.getConstant(C1 & APInt::getLowBitsSet(
2353 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2354 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2355 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2356 if (N0.getOpcode() == ISD::SETCC &&
2357 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2358 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2360 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2361 // Invert the condition.
2362 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2363 CC = ISD::getSetCCInverse(CC,
2364 N0.getOperand(0).getValueType().isInteger());
2365 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2368 if ((N0.getOpcode() == ISD::XOR ||
2369 (N0.getOpcode() == ISD::AND &&
2370 N0.getOperand(0).getOpcode() == ISD::XOR &&
2371 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2372 isa<ConstantSDNode>(N0.getOperand(1)) &&
2373 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2374 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2375 // can only do this if the top bits are known zero.
2376 unsigned BitWidth = N0.getValueSizeInBits();
2377 if (DAG.MaskedValueIsZero(N0,
2378 APInt::getHighBitsSet(BitWidth,
2380 // Okay, get the un-inverted input value.
2382 if (N0.getOpcode() == ISD::XOR)
2383 Val = N0.getOperand(0);
2385 assert(N0.getOpcode() == ISD::AND &&
2386 N0.getOperand(0).getOpcode() == ISD::XOR);
2387 // ((X^1)&1)^1 -> X & 1
2388 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2389 N0.getOperand(0).getOperand(0),
2393 return DAG.getSetCC(dl, VT, Val, N1,
2394 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2396 } else if (N1C->getAPIntValue() == 1 &&
2398 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
2400 if (Op0.getOpcode() == ISD::TRUNCATE)
2401 Op0 = Op0.getOperand(0);
2403 if ((Op0.getOpcode() == ISD::XOR) &&
2404 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2405 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2406 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2407 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2408 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2411 if (Op0.getOpcode() == ISD::AND &&
2412 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2413 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2414 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2415 if (Op0.getValueType().bitsGT(VT))
2416 Op0 = DAG.getNode(ISD::AND, dl, VT,
2417 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2418 DAG.getConstant(1, VT));
2419 else if (Op0.getValueType().bitsLT(VT))
2420 Op0 = DAG.getNode(ISD::AND, dl, VT,
2421 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2422 DAG.getConstant(1, VT));
2424 return DAG.getSetCC(dl, VT, Op0,
2425 DAG.getConstant(0, Op0.getValueType()),
2426 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2428 if (Op0.getOpcode() == ISD::AssertZext &&
2429 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
2430 return DAG.getSetCC(dl, VT, Op0,
2431 DAG.getConstant(0, Op0.getValueType()),
2432 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2436 APInt MinVal, MaxVal;
2437 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2438 if (ISD::isSignedIntSetCC(Cond)) {
2439 MinVal = APInt::getSignedMinValue(OperandBitSize);
2440 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2442 MinVal = APInt::getMinValue(OperandBitSize);
2443 MaxVal = APInt::getMaxValue(OperandBitSize);
2446 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2447 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2448 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2449 // X >= C0 --> X > (C0-1)
2450 return DAG.getSetCC(dl, VT, N0,
2451 DAG.getConstant(C1-1, N1.getValueType()),
2452 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2455 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2456 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2457 // X <= C0 --> X < (C0+1)
2458 return DAG.getSetCC(dl, VT, N0,
2459 DAG.getConstant(C1+1, N1.getValueType()),
2460 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2463 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2464 return DAG.getConstant(0, VT); // X < MIN --> false
2465 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2466 return DAG.getConstant(1, VT); // X >= MIN --> true
2467 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2468 return DAG.getConstant(0, VT); // X > MAX --> false
2469 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2470 return DAG.getConstant(1, VT); // X <= MAX --> true
2472 // Canonicalize setgt X, Min --> setne X, Min
2473 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2474 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2475 // Canonicalize setlt X, Max --> setne X, Max
2476 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2477 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2479 // If we have setult X, 1, turn it into seteq X, 0
2480 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2481 return DAG.getSetCC(dl, VT, N0,
2482 DAG.getConstant(MinVal, N0.getValueType()),
2484 // If we have setugt X, Max-1, turn it into seteq X, Max
2485 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2486 return DAG.getSetCC(dl, VT, N0,
2487 DAG.getConstant(MaxVal, N0.getValueType()),
2490 // If we have "setcc X, C0", check to see if we can shrink the immediate
2493 // SETUGT X, SINTMAX -> SETLT X, 0
2494 if (Cond == ISD::SETUGT &&
2495 C1 == APInt::getSignedMaxValue(OperandBitSize))
2496 return DAG.getSetCC(dl, VT, N0,
2497 DAG.getConstant(0, N1.getValueType()),
2500 // SETULT X, SINTMIN -> SETGT X, -1
2501 if (Cond == ISD::SETULT &&
2502 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2503 SDValue ConstMinusOne =
2504 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2506 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2509 // Fold bit comparisons when we can.
2510 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2511 (VT == N0.getValueType() ||
2512 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2513 N0.getOpcode() == ISD::AND)
2514 if (ConstantSDNode *AndRHS =
2515 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2516 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2517 getPointerTy() : getShiftAmountTy(N0.getValueType());
2518 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2519 // Perform the xform if the AND RHS is a single bit.
2520 if (AndRHS->getAPIntValue().isPowerOf2()) {
2521 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2522 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2523 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2525 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2526 // (X & 8) == 8 --> (X & 8) >> 3
2527 // Perform the xform if C1 is a single bit.
2528 if (C1.isPowerOf2()) {
2529 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2530 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2531 DAG.getConstant(C1.logBase2(), ShiftTy)));
2536 if (C1.getMinSignedBits() <= 64 &&
2537 !isLegalICmpImmediate(C1.getSExtValue())) {
2538 // (X & -256) == 256 -> (X >> 8) == 1
2539 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2540 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
2541 if (ConstantSDNode *AndRHS =
2542 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2543 const APInt &AndRHSC = AndRHS->getAPIntValue();
2544 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
2545 unsigned ShiftBits = AndRHSC.countTrailingZeros();
2546 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2547 getPointerTy() : getShiftAmountTy(N0.getValueType());
2548 EVT CmpTy = N0.getValueType();
2549 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
2550 DAG.getConstant(ShiftBits, ShiftTy));
2551 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
2552 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
2555 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
2556 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
2557 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
2558 // X < 0x100000000 -> (X >> 32) < 1
2559 // X >= 0x100000000 -> (X >> 32) >= 1
2560 // X <= 0x0ffffffff -> (X >> 32) < 1
2561 // X > 0x0ffffffff -> (X >> 32) >= 1
2564 ISD::CondCode NewCond = Cond;
2566 ShiftBits = C1.countTrailingOnes();
2568 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2570 ShiftBits = C1.countTrailingZeros();
2572 NewC = NewC.lshr(ShiftBits);
2573 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
2574 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2575 getPointerTy() : getShiftAmountTy(N0.getValueType());
2576 EVT CmpTy = N0.getValueType();
2577 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
2578 DAG.getConstant(ShiftBits, ShiftTy));
2579 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
2580 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2586 if (isa<ConstantFPSDNode>(N0.getNode())) {
2587 // Constant fold or commute setcc.
2588 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2589 if (O.getNode()) return O;
2590 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2591 // If the RHS of an FP comparison is a constant, simplify it away in
2593 if (CFP->getValueAPF().isNaN()) {
2594 // If an operand is known to be a nan, we can fold it.
2595 switch (ISD::getUnorderedFlavor(Cond)) {
2596 default: llvm_unreachable("Unknown flavor!");
2597 case 0: // Known false.
2598 return DAG.getConstant(0, VT);
2599 case 1: // Known true.
2600 return DAG.getConstant(1, VT);
2601 case 2: // Undefined.
2602 return DAG.getUNDEF(VT);
2606 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2607 // constant if knowing that the operand is non-nan is enough. We prefer to
2608 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2610 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2611 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2613 // If the condition is not legal, see if we can find an equivalent one
2615 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
2616 // If the comparison was an awkward floating-point == or != and one of
2617 // the comparison operands is infinity or negative infinity, convert the
2618 // condition to a less-awkward <= or >=.
2619 if (CFP->getValueAPF().isInfinity()) {
2620 if (CFP->getValueAPF().isNegative()) {
2621 if (Cond == ISD::SETOEQ &&
2622 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
2623 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2624 if (Cond == ISD::SETUEQ &&
2625 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
2626 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2627 if (Cond == ISD::SETUNE &&
2628 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
2629 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2630 if (Cond == ISD::SETONE &&
2631 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
2632 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2634 if (Cond == ISD::SETOEQ &&
2635 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
2636 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2637 if (Cond == ISD::SETUEQ &&
2638 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
2639 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2640 if (Cond == ISD::SETUNE &&
2641 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
2642 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2643 if (Cond == ISD::SETONE &&
2644 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
2645 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2652 // The sext(setcc()) => setcc() optimization relies on the appropriate
2653 // constant being emitted.
2655 switch (getBooleanContents(N0.getValueType().isVector())) {
2656 case UndefinedBooleanContent:
2657 case ZeroOrOneBooleanContent:
2658 EqVal = ISD::isTrueWhenEqual(Cond);
2660 case ZeroOrNegativeOneBooleanContent:
2661 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
2665 // We can always fold X == X for integer setcc's.
2666 if (N0.getValueType().isInteger()) {
2667 return DAG.getConstant(EqVal, VT);
2669 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2670 if (UOF == 2) // FP operators that are undefined on NaNs.
2671 return DAG.getConstant(EqVal, VT);
2672 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2673 return DAG.getConstant(EqVal, VT);
2674 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2675 // if it is not already.
2676 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2677 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
2678 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
2679 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2682 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2683 N0.getValueType().isInteger()) {
2684 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2685 N0.getOpcode() == ISD::XOR) {
2686 // Simplify (X+Y) == (X+Z) --> Y == Z
2687 if (N0.getOpcode() == N1.getOpcode()) {
2688 if (N0.getOperand(0) == N1.getOperand(0))
2689 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2690 if (N0.getOperand(1) == N1.getOperand(1))
2691 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2692 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2693 // If X op Y == Y op X, try other combinations.
2694 if (N0.getOperand(0) == N1.getOperand(1))
2695 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2697 if (N0.getOperand(1) == N1.getOperand(0))
2698 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2703 // If RHS is a legal immediate value for a compare instruction, we need
2704 // to be careful about increasing register pressure needlessly.
2705 bool LegalRHSImm = false;
2707 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2708 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2709 // Turn (X+C1) == C2 --> X == C2-C1
2710 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2711 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2712 DAG.getConstant(RHSC->getAPIntValue()-
2713 LHSR->getAPIntValue(),
2714 N0.getValueType()), Cond);
2717 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2718 if (N0.getOpcode() == ISD::XOR)
2719 // If we know that all of the inverted bits are zero, don't bother
2720 // performing the inversion.
2721 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2723 DAG.getSetCC(dl, VT, N0.getOperand(0),
2724 DAG.getConstant(LHSR->getAPIntValue() ^
2725 RHSC->getAPIntValue(),
2730 // Turn (C1-X) == C2 --> X == C1-C2
2731 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2732 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2734 DAG.getSetCC(dl, VT, N0.getOperand(1),
2735 DAG.getConstant(SUBC->getAPIntValue() -
2736 RHSC->getAPIntValue(),
2742 // Could RHSC fold directly into a compare?
2743 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2744 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
2747 // Simplify (X+Z) == X --> Z == 0
2748 // Don't do this if X is an immediate that can fold into a cmp
2749 // instruction and X+Z has other uses. It could be an induction variable
2750 // chain, and the transform would increase register pressure.
2751 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2752 if (N0.getOperand(0) == N1)
2753 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2754 DAG.getConstant(0, N0.getValueType()), Cond);
2755 if (N0.getOperand(1) == N1) {
2756 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2757 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2758 DAG.getConstant(0, N0.getValueType()), Cond);
2759 if (N0.getNode()->hasOneUse()) {
2760 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2761 // (Z-X) == X --> Z == X<<1
2762 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
2763 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2764 if (!DCI.isCalledByLegalizer())
2765 DCI.AddToWorklist(SH.getNode());
2766 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2772 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2773 N1.getOpcode() == ISD::XOR) {
2774 // Simplify X == (X+Z) --> Z == 0
2775 if (N1.getOperand(0) == N0)
2776 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2777 DAG.getConstant(0, N1.getValueType()), Cond);
2778 if (N1.getOperand(1) == N0) {
2779 if (DAG.isCommutativeBinOp(N1.getOpcode()))
2780 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2781 DAG.getConstant(0, N1.getValueType()), Cond);
2782 if (N1.getNode()->hasOneUse()) {
2783 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2784 // X == (Z-X) --> X<<1 == Z
2785 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2786 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2787 if (!DCI.isCalledByLegalizer())
2788 DCI.AddToWorklist(SH.getNode());
2789 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2794 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2795 // Note that where y is variable and is known to have at most
2796 // one bit set (for example, if it is z&1) we cannot do this;
2797 // the expressions are not equivalent when y==0.
2798 if (N0.getOpcode() == ISD::AND)
2799 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2800 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2801 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2802 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2803 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2806 if (N1.getOpcode() == ISD::AND)
2807 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2808 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2809 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2810 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2811 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2816 // Fold away ALL boolean setcc's.
2818 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2820 default: llvm_unreachable("Unknown integer setcc!");
2821 case ISD::SETEQ: // X == Y -> ~(X^Y)
2822 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2823 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2824 if (!DCI.isCalledByLegalizer())
2825 DCI.AddToWorklist(Temp.getNode());
2827 case ISD::SETNE: // X != Y --> (X^Y)
2828 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2830 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2831 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2832 Temp = DAG.getNOT(dl, N0, MVT::i1);
2833 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2834 if (!DCI.isCalledByLegalizer())
2835 DCI.AddToWorklist(Temp.getNode());
2837 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2838 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2839 Temp = DAG.getNOT(dl, N1, MVT::i1);
2840 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2841 if (!DCI.isCalledByLegalizer())
2842 DCI.AddToWorklist(Temp.getNode());
2844 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2845 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2846 Temp = DAG.getNOT(dl, N0, MVT::i1);
2847 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2848 if (!DCI.isCalledByLegalizer())
2849 DCI.AddToWorklist(Temp.getNode());
2851 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2852 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2853 Temp = DAG.getNOT(dl, N1, MVT::i1);
2854 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2857 if (VT != MVT::i1) {
2858 if (!DCI.isCalledByLegalizer())
2859 DCI.AddToWorklist(N0.getNode());
2860 // FIXME: If running after legalize, we probably can't do this.
2861 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2866 // Could not fold it.
2870 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2871 /// node is a GlobalAddress + offset.
2872 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2873 int64_t &Offset) const {
2874 if (isa<GlobalAddressSDNode>(N)) {
2875 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2876 GA = GASD->getGlobal();
2877 Offset += GASD->getOffset();
2881 if (N->getOpcode() == ISD::ADD) {
2882 SDValue N1 = N->getOperand(0);
2883 SDValue N2 = N->getOperand(1);
2884 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2885 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2887 Offset += V->getSExtValue();
2890 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2891 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2893 Offset += V->getSExtValue();
2903 SDValue TargetLowering::
2904 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2905 // Default implementation: no optimization.
2909 //===----------------------------------------------------------------------===//
2910 // Inline Assembler Implementation Methods
2911 //===----------------------------------------------------------------------===//
2914 TargetLowering::ConstraintType
2915 TargetLowering::getConstraintType(const std::string &Constraint) const {
2916 if (Constraint.size() == 1) {
2917 switch (Constraint[0]) {
2919 case 'r': return C_RegisterClass;
2921 case 'o': // offsetable
2922 case 'V': // not offsetable
2924 case 'i': // Simple Integer or Relocatable Constant
2925 case 'n': // Simple Integer
2926 case 'E': // Floating Point Constant
2927 case 'F': // Floating Point Constant
2928 case 's': // Relocatable Constant
2929 case 'p': // Address.
2930 case 'X': // Allow ANY value.
2931 case 'I': // Target registers.
2945 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2946 Constraint[Constraint.size()-1] == '}')
2951 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2952 /// with another that has more specific requirements based on the type of the
2953 /// corresponding operand.
2954 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2955 if (ConstraintVT.isInteger())
2957 if (ConstraintVT.isFloatingPoint())
2958 return "f"; // works for many targets
2962 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2963 /// vector. If it is invalid, don't add anything to Ops.
2964 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2965 std::string &Constraint,
2966 std::vector<SDValue> &Ops,
2967 SelectionDAG &DAG) const {
2969 if (Constraint.length() > 1) return;
2971 char ConstraintLetter = Constraint[0];
2972 switch (ConstraintLetter) {
2974 case 'X': // Allows any operand; labels (basic block) use this.
2975 if (Op.getOpcode() == ISD::BasicBlock) {
2980 case 'i': // Simple Integer or Relocatable Constant
2981 case 'n': // Simple Integer
2982 case 's': { // Relocatable Constant
2983 // These operands are interested in values of the form (GV+C), where C may
2984 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2985 // is possible and fine if either GV or C are missing.
2986 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2987 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2989 // If we have "(add GV, C)", pull out GV/C
2990 if (Op.getOpcode() == ISD::ADD) {
2991 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2992 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2993 if (C == 0 || GA == 0) {
2994 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2995 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2997 if (C == 0 || GA == 0)
3001 // If we find a valid operand, map to the TargetXXX version so that the
3002 // value itself doesn't get selected.
3003 if (GA) { // Either &GV or &GV+C
3004 if (ConstraintLetter != 'n') {
3005 int64_t Offs = GA->getOffset();
3006 if (C) Offs += C->getZExtValue();
3007 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
3008 C ? C->getDebugLoc() : DebugLoc(),
3009 Op.getValueType(), Offs));
3013 if (C) { // just C, no GV.
3014 // Simple constants are not allowed for 's'.
3015 if (ConstraintLetter != 's') {
3016 // gcc prints these as sign extended. Sign extend value to 64 bits
3017 // now; without this it would get ZExt'd later in
3018 // ScheduleDAGSDNodes::EmitNode, which is very generic.
3019 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
3029 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
3030 getRegForInlineAsmConstraint(const std::string &Constraint,
3032 if (Constraint[0] != '{')
3033 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
3034 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
3036 // Remove the braces from around the name.
3037 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
3039 std::pair<unsigned, const TargetRegisterClass*> R =
3040 std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3042 // Figure out which register class contains this reg.
3043 const TargetRegisterInfo *RI = TM.getRegisterInfo();
3044 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
3045 E = RI->regclass_end(); RCI != E; ++RCI) {
3046 const TargetRegisterClass *RC = *RCI;
3048 // If none of the value types for this register class are valid, we
3049 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3053 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
3055 if (RegName.equals_lower(RI->getName(*I))) {
3056 std::pair<unsigned, const TargetRegisterClass*> S =
3057 std::make_pair(*I, RC);
3059 // If this register class has the requested value type, return it,
3060 // otherwise keep searching and return the first class found
3061 // if no other is found which explicitly has the requested type.
3062 if (RC->hasType(VT))
3073 //===----------------------------------------------------------------------===//
3074 // Constraint Selection.
3076 /// isMatchingInputConstraint - Return true of this is an input operand that is
3077 /// a matching constraint like "4".
3078 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
3079 assert(!ConstraintCode.empty() && "No known constraint!");
3080 return isdigit(ConstraintCode[0]);
3083 /// getMatchedOperand - If this is an input matching constraint, this method
3084 /// returns the output operand it matches.
3085 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
3086 assert(!ConstraintCode.empty() && "No known constraint!");
3087 return atoi(ConstraintCode.c_str());
3091 /// ParseConstraints - Split up the constraint string from the inline
3092 /// assembly value into the specific constraints and their prefixes,
3093 /// and also tie in the associated operand values.
3094 /// If this returns an empty vector, and if the constraint string itself
3095 /// isn't empty, there was an error parsing.
3096 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
3097 ImmutableCallSite CS) const {
3098 /// ConstraintOperands - Information about all of the constraints.
3099 AsmOperandInfoVector ConstraintOperands;
3100 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3101 unsigned maCount = 0; // Largest number of multiple alternative constraints.
3103 // Do a prepass over the constraints, canonicalizing them, and building up the
3104 // ConstraintOperands list.
3105 InlineAsm::ConstraintInfoVector
3106 ConstraintInfos = IA->ParseConstraints();
3108 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3109 unsigned ResNo = 0; // ResNo - The result number of the next output.
3111 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3112 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3113 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3115 // Update multiple alternative constraint count.
3116 if (OpInfo.multipleAlternatives.size() > maCount)
3117 maCount = OpInfo.multipleAlternatives.size();
3119 OpInfo.ConstraintVT = MVT::Other;
3121 // Compute the value type for each operand.
3122 switch (OpInfo.Type) {
3123 case InlineAsm::isOutput:
3124 // Indirect outputs just consume an argument.
3125 if (OpInfo.isIndirect) {
3126 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
3130 // The return value of the call is this value. As such, there is no
3131 // corresponding argument.
3132 assert(!CS.getType()->isVoidTy() &&
3134 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
3135 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
3137 assert(ResNo == 0 && "Asm only has one result!");
3138 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
3142 case InlineAsm::isInput:
3143 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
3145 case InlineAsm::isClobber:
3150 if (OpInfo.CallOperandVal) {
3151 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
3152 if (OpInfo.isIndirect) {
3153 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
3155 report_fatal_error("Indirect operand for inline asm not a pointer!");
3156 OpTy = PtrTy->getElementType();
3159 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
3160 if (StructType *STy = dyn_cast<StructType>(OpTy))
3161 if (STy->getNumElements() == 1)
3162 OpTy = STy->getElementType(0);
3164 // If OpTy is not a single value, it may be a struct/union that we
3165 // can tile with integers.
3166 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
3167 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3176 OpInfo.ConstraintVT =
3177 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
3180 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
3181 OpInfo.ConstraintVT = MVT::getIntegerVT(
3182 8*TD->getPointerSize(PT->getAddressSpace()));
3184 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
3189 // If we have multiple alternative constraints, select the best alternative.
3190 if (ConstraintInfos.size()) {
3192 unsigned bestMAIndex = 0;
3193 int bestWeight = -1;
3194 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
3197 // Compute the sums of the weights for each alternative, keeping track
3198 // of the best (highest weight) one so far.
3199 for (maIndex = 0; maIndex < maCount; ++maIndex) {
3201 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3202 cIndex != eIndex; ++cIndex) {
3203 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
3204 if (OpInfo.Type == InlineAsm::isClobber)
3207 // If this is an output operand with a matching input operand,
3208 // look up the matching input. If their types mismatch, e.g. one
3209 // is an integer, the other is floating point, or their sizes are
3210 // different, flag it as an maCantMatch.
3211 if (OpInfo.hasMatchingInput()) {
3212 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3213 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3214 if ((OpInfo.ConstraintVT.isInteger() !=
3215 Input.ConstraintVT.isInteger()) ||
3216 (OpInfo.ConstraintVT.getSizeInBits() !=
3217 Input.ConstraintVT.getSizeInBits())) {
3218 weightSum = -1; // Can't match.
3223 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
3228 weightSum += weight;
3231 if (weightSum > bestWeight) {
3232 bestWeight = weightSum;
3233 bestMAIndex = maIndex;
3237 // Now select chosen alternative in each constraint.
3238 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3239 cIndex != eIndex; ++cIndex) {
3240 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
3241 if (cInfo.Type == InlineAsm::isClobber)
3243 cInfo.selectAlternative(bestMAIndex);
3248 // Check and hook up tied operands, choose constraint code to use.
3249 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3250 cIndex != eIndex; ++cIndex) {
3251 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
3253 // If this is an output operand with a matching input operand, look up the
3254 // matching input. If their types mismatch, e.g. one is an integer, the
3255 // other is floating point, or their sizes are different, flag it as an
3257 if (OpInfo.hasMatchingInput()) {
3258 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3260 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3261 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
3262 getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3263 OpInfo.ConstraintVT);
3264 std::pair<unsigned, const TargetRegisterClass*> InputRC =
3265 getRegForInlineAsmConstraint(Input.ConstraintCode,
3266 Input.ConstraintVT);
3267 if ((OpInfo.ConstraintVT.isInteger() !=
3268 Input.ConstraintVT.isInteger()) ||
3269 (MatchRC.second != InputRC.second)) {
3270 report_fatal_error("Unsupported asm: input constraint"
3271 " with a matching output constraint of"
3272 " incompatible type!");
3279 return ConstraintOperands;
3283 /// getConstraintGenerality - Return an integer indicating how general CT
3285 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3287 case TargetLowering::C_Other:
3288 case TargetLowering::C_Unknown:
3290 case TargetLowering::C_Register:
3292 case TargetLowering::C_RegisterClass:
3294 case TargetLowering::C_Memory:
3297 llvm_unreachable("Invalid constraint type");
3300 /// Examine constraint type and operand type and determine a weight value.
3301 /// This object must already have been set up with the operand type
3302 /// and the current alternative constraint selected.
3303 TargetLowering::ConstraintWeight
3304 TargetLowering::getMultipleConstraintMatchWeight(
3305 AsmOperandInfo &info, int maIndex) const {
3306 InlineAsm::ConstraintCodeVector *rCodes;
3307 if (maIndex >= (int)info.multipleAlternatives.size())
3308 rCodes = &info.Codes;
3310 rCodes = &info.multipleAlternatives[maIndex].Codes;
3311 ConstraintWeight BestWeight = CW_Invalid;
3313 // Loop over the options, keeping track of the most general one.
3314 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3315 ConstraintWeight weight =
3316 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3317 if (weight > BestWeight)
3318 BestWeight = weight;
3324 /// Examine constraint type and operand type and determine a weight value.
3325 /// This object must already have been set up with the operand type
3326 /// and the current alternative constraint selected.
3327 TargetLowering::ConstraintWeight
3328 TargetLowering::getSingleConstraintMatchWeight(
3329 AsmOperandInfo &info, const char *constraint) const {
3330 ConstraintWeight weight = CW_Invalid;
3331 Value *CallOperandVal = info.CallOperandVal;
3332 // If we don't have a value, we can't do a match,
3333 // but allow it at the lowest weight.
3334 if (CallOperandVal == NULL)
3336 // Look at the constraint type.
3337 switch (*constraint) {
3338 case 'i': // immediate integer.
3339 case 'n': // immediate integer with a known value.
3340 if (isa<ConstantInt>(CallOperandVal))
3341 weight = CW_Constant;
3343 case 's': // non-explicit intregal immediate.
3344 if (isa<GlobalValue>(CallOperandVal))
3345 weight = CW_Constant;
3347 case 'E': // immediate float if host format.
3348 case 'F': // immediate float.
3349 if (isa<ConstantFP>(CallOperandVal))
3350 weight = CW_Constant;
3352 case '<': // memory operand with autodecrement.
3353 case '>': // memory operand with autoincrement.
3354 case 'm': // memory operand.
3355 case 'o': // offsettable memory operand
3356 case 'V': // non-offsettable memory operand
3359 case 'r': // general register.
3360 case 'g': // general register, memory operand or immediate integer.
3361 // note: Clang converts "g" to "imr".
3362 if (CallOperandVal->getType()->isIntegerTy())
3363 weight = CW_Register;
3365 case 'X': // any operand.
3367 weight = CW_Default;
3373 /// ChooseConstraint - If there are multiple different constraints that we
3374 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3375 /// This is somewhat tricky: constraints fall into four classes:
3376 /// Other -> immediates and magic values
3377 /// Register -> one specific register
3378 /// RegisterClass -> a group of regs
3379 /// Memory -> memory
3380 /// Ideally, we would pick the most specific constraint possible: if we have
3381 /// something that fits into a register, we would pick it. The problem here
3382 /// is that if we have something that could either be in a register or in
3383 /// memory that use of the register could cause selection of *other*
3384 /// operands to fail: they might only succeed if we pick memory. Because of
3385 /// this the heuristic we use is:
3387 /// 1) If there is an 'other' constraint, and if the operand is valid for
3388 /// that constraint, use it. This makes us take advantage of 'i'
3389 /// constraints when available.
3390 /// 2) Otherwise, pick the most general constraint present. This prefers
3391 /// 'm' over 'r', for example.
3393 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3394 const TargetLowering &TLI,
3395 SDValue Op, SelectionDAG *DAG) {
3396 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3397 unsigned BestIdx = 0;
3398 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3399 int BestGenerality = -1;
3401 // Loop over the options, keeping track of the most general one.
3402 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3403 TargetLowering::ConstraintType CType =
3404 TLI.getConstraintType(OpInfo.Codes[i]);
3406 // If this is an 'other' constraint, see if the operand is valid for it.
3407 // For example, on X86 we might have an 'rI' constraint. If the operand
3408 // is an integer in the range [0..31] we want to use I (saving a load
3409 // of a register), otherwise we must use 'r'.
3410 if (CType == TargetLowering::C_Other && Op.getNode()) {
3411 assert(OpInfo.Codes[i].size() == 1 &&
3412 "Unhandled multi-letter 'other' constraint");
3413 std::vector<SDValue> ResultOps;
3414 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3416 if (!ResultOps.empty()) {
3423 // Things with matching constraints can only be registers, per gcc
3424 // documentation. This mainly affects "g" constraints.
3425 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3428 // This constraint letter is more general than the previous one, use it.
3429 int Generality = getConstraintGenerality(CType);
3430 if (Generality > BestGenerality) {
3433 BestGenerality = Generality;
3437 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3438 OpInfo.ConstraintType = BestType;
3441 /// ComputeConstraintToUse - Determines the constraint code and constraint
3442 /// type to use for the specific AsmOperandInfo, setting
3443 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3444 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3446 SelectionDAG *DAG) const {
3447 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3449 // Single-letter constraints ('r') are very common.
3450 if (OpInfo.Codes.size() == 1) {
3451 OpInfo.ConstraintCode = OpInfo.Codes[0];
3452 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3454 ChooseConstraint(OpInfo, *this, Op, DAG);
3457 // 'X' matches anything.
3458 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3459 // Labels and constants are handled elsewhere ('X' is the only thing
3460 // that matches labels). For Functions, the type here is the type of
3461 // the result, which is not what we want to look at; leave them alone.
3462 Value *v = OpInfo.CallOperandVal;
3463 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3464 OpInfo.CallOperandVal = v;
3468 // Otherwise, try to resolve it to something we know about by looking at
3469 // the actual operand type.
3470 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3471 OpInfo.ConstraintCode = Repl;
3472 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3477 //===----------------------------------------------------------------------===//
3478 // Loop Strength Reduction hooks
3479 //===----------------------------------------------------------------------===//
3481 /// isLegalAddressingMode - Return true if the addressing mode represented
3482 /// by AM is legal for this target, for a load/store of the specified type.
3483 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3485 // The default implementation of this implements a conservative RISCy, r+r and
3488 // Allows a sign-extended 16-bit immediate field.
3489 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3492 // No global is ever allowed as a base.
3496 // Only support r+r,
3498 case 0: // "r+i" or just "i", depending on HasBaseReg.
3501 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3503 // Otherwise we have r+r or r+i.
3506 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3508 // Allow 2*r as r+r.
3515 /// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3516 /// with the multiplicative inverse of the constant.
3517 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3518 SelectionDAG &DAG) const {
3519 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3520 APInt d = C->getAPIntValue();
3521 assert(d != 0 && "Division by zero!");
3523 // Shift the value upfront if it is even, so the LSB is one.
3524 unsigned ShAmt = d.countTrailingZeros();
3526 // TODO: For UDIV use SRL instead of SRA.
3527 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3528 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3532 // Calculate the multiplicative inverse, using Newton's method.
3534 while ((t = d*xn) != 1)
3535 xn *= APInt(d.getBitWidth(), 2) - t;
3537 Op2 = DAG.getConstant(xn, Op1.getValueType());
3538 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3541 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3542 /// return a DAG expression to select that will generate the same value by
3543 /// multiplying by a magic number. See:
3544 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3545 SDValue TargetLowering::
3546 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3547 std::vector<SDNode*> *Created) const {
3548 EVT VT = N->getValueType(0);
3549 DebugLoc dl= N->getDebugLoc();
3551 // Check to see if we can do this.
3552 // FIXME: We should be more aggressive here.
3553 if (!isTypeLegal(VT))
3556 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3557 APInt::ms magics = d.magic();
3559 // Multiply the numerator (operand 0) by the magic value
3560 // FIXME: We should support doing a MUL in a wider type
3562 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3563 isOperationLegalOrCustom(ISD::MULHS, VT))
3564 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3565 DAG.getConstant(magics.m, VT));
3566 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3567 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3568 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3570 DAG.getConstant(magics.m, VT)).getNode(), 1);
3572 return SDValue(); // No mulhs or equvialent
3573 // If d > 0 and m < 0, add the numerator
3574 if (d.isStrictlyPositive() && magics.m.isNegative()) {
3575 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3577 Created->push_back(Q.getNode());
3579 // If d < 0 and m > 0, subtract the numerator.
3580 if (d.isNegative() && magics.m.isStrictlyPositive()) {
3581 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3583 Created->push_back(Q.getNode());
3585 // Shift right algebraic if shift value is nonzero
3587 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3588 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3590 Created->push_back(Q.getNode());
3592 // Extract the sign bit and add it to the quotient
3594 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3595 getShiftAmountTy(Q.getValueType())));
3597 Created->push_back(T.getNode());
3598 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3601 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3602 /// return a DAG expression to select that will generate the same value by
3603 /// multiplying by a magic number. See:
3604 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3605 SDValue TargetLowering::
3606 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3607 std::vector<SDNode*> *Created) const {
3608 EVT VT = N->getValueType(0);
3609 DebugLoc dl = N->getDebugLoc();
3611 // Check to see if we can do this.
3612 // FIXME: We should be more aggressive here.
3613 if (!isTypeLegal(VT))
3616 // FIXME: We should use a narrower constant when the upper
3617 // bits are known to be zero.
3618 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3619 APInt::mu magics = N1C.magicu();
3621 SDValue Q = N->getOperand(0);
3623 // If the divisor is even, we can avoid using the expensive fixup by shifting
3624 // the divided value upfront.
3625 if (magics.a != 0 && !N1C[0]) {
3626 unsigned Shift = N1C.countTrailingZeros();
3627 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3628 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3630 Created->push_back(Q.getNode());
3632 // Get magic number for the shifted divisor.
3633 magics = N1C.lshr(Shift).magicu(Shift);
3634 assert(magics.a == 0 && "Should use cheap fixup now");
3637 // Multiply the numerator (operand 0) by the magic value
3638 // FIXME: We should support doing a MUL in a wider type
3639 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3640 isOperationLegalOrCustom(ISD::MULHU, VT))
3641 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3642 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3643 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3644 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3645 DAG.getConstant(magics.m, VT)).getNode(), 1);
3647 return SDValue(); // No mulhu or equvialent
3649 Created->push_back(Q.getNode());
3651 if (magics.a == 0) {
3652 assert(magics.s < N1C.getBitWidth() &&
3653 "We shouldn't generate an undefined shift!");
3654 return DAG.getNode(ISD::SRL, dl, VT, Q,
3655 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3657 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3659 Created->push_back(NPQ.getNode());
3660 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3661 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3663 Created->push_back(NPQ.getNode());
3664 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3666 Created->push_back(NPQ.getNode());
3667 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3668 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));