1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetData.h"
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/Support/MathExtras.h"
24 /// InitLibcallNames - Set default libcall names.
26 static void InitLibcallNames(const char **Names) {
27 Names[RTLIB::SHL_I32] = "__ashlsi3";
28 Names[RTLIB::SHL_I64] = "__ashldi3";
29 Names[RTLIB::SRL_I32] = "__lshrsi3";
30 Names[RTLIB::SRL_I64] = "__lshrdi3";
31 Names[RTLIB::SRA_I32] = "__ashrsi3";
32 Names[RTLIB::SRA_I64] = "__ashrdi3";
33 Names[RTLIB::MUL_I32] = "__mulsi3";
34 Names[RTLIB::MUL_I64] = "__muldi3";
35 Names[RTLIB::SDIV_I32] = "__divsi3";
36 Names[RTLIB::SDIV_I64] = "__divdi3";
37 Names[RTLIB::UDIV_I32] = "__udivsi3";
38 Names[RTLIB::UDIV_I64] = "__udivdi3";
39 Names[RTLIB::SREM_I32] = "__modsi3";
40 Names[RTLIB::SREM_I64] = "__moddi3";
41 Names[RTLIB::UREM_I32] = "__umodsi3";
42 Names[RTLIB::UREM_I64] = "__umoddi3";
43 Names[RTLIB::NEG_I32] = "__negsi2";
44 Names[RTLIB::NEG_I64] = "__negdi2";
45 Names[RTLIB::ADD_F32] = "__addsf3";
46 Names[RTLIB::ADD_F64] = "__adddf3";
47 Names[RTLIB::SUB_F32] = "__subsf3";
48 Names[RTLIB::SUB_F64] = "__subdf3";
49 Names[RTLIB::MUL_F32] = "__mulsf3";
50 Names[RTLIB::MUL_F64] = "__muldf3";
51 Names[RTLIB::DIV_F32] = "__divsf3";
52 Names[RTLIB::DIV_F64] = "__divdf3";
53 Names[RTLIB::REM_F32] = "fmodf";
54 Names[RTLIB::REM_F64] = "fmod";
55 Names[RTLIB::NEG_F32] = "__negsf2";
56 Names[RTLIB::NEG_F64] = "__negdf2";
57 Names[RTLIB::POWI_F32] = "__powisf2";
58 Names[RTLIB::POWI_F64] = "__powidf2";
59 Names[RTLIB::SQRT_F32] = "sqrtf";
60 Names[RTLIB::SQRT_F64] = "sqrt";
61 Names[RTLIB::SIN_F32] = "sinf";
62 Names[RTLIB::SIN_F64] = "sin";
63 Names[RTLIB::COS_F32] = "cosf";
64 Names[RTLIB::COS_F64] = "cos";
65 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
66 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
67 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
68 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
69 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
70 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
71 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
72 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
73 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
74 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
75 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
76 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
77 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
78 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
79 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
80 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
81 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
82 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
83 Names[RTLIB::OEQ_F32] = "__eqsf2";
84 Names[RTLIB::OEQ_F64] = "__eqdf2";
85 Names[RTLIB::UNE_F32] = "__nesf2";
86 Names[RTLIB::UNE_F64] = "__nedf2";
87 Names[RTLIB::OGE_F32] = "__gesf2";
88 Names[RTLIB::OGE_F64] = "__gedf2";
89 Names[RTLIB::OLT_F32] = "__ltsf2";
90 Names[RTLIB::OLT_F64] = "__ltdf2";
91 Names[RTLIB::OLE_F32] = "__lesf2";
92 Names[RTLIB::OLE_F64] = "__ledf2";
93 Names[RTLIB::OGT_F32] = "__gtsf2";
94 Names[RTLIB::OGT_F64] = "__gtdf2";
95 Names[RTLIB::UO_F32] = "__unordsf2";
96 Names[RTLIB::UO_F64] = "__unorddf2";
97 Names[RTLIB::O_F32] = "__unordsf2";
98 Names[RTLIB::O_F64] = "__unorddf2";
101 /// InitCmpLibcallCCs - Set default comparison libcall CC.
103 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
104 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
105 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
106 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
107 CCs[RTLIB::UNE_F32] = ISD::SETNE;
108 CCs[RTLIB::UNE_F64] = ISD::SETNE;
109 CCs[RTLIB::OGE_F32] = ISD::SETGE;
110 CCs[RTLIB::OGE_F64] = ISD::SETGE;
111 CCs[RTLIB::OLT_F32] = ISD::SETLT;
112 CCs[RTLIB::OLT_F64] = ISD::SETLT;
113 CCs[RTLIB::OLE_F32] = ISD::SETLE;
114 CCs[RTLIB::OLE_F64] = ISD::SETLE;
115 CCs[RTLIB::OGT_F32] = ISD::SETGT;
116 CCs[RTLIB::OGT_F64] = ISD::SETGT;
117 CCs[RTLIB::UO_F32] = ISD::SETNE;
118 CCs[RTLIB::UO_F64] = ISD::SETNE;
119 CCs[RTLIB::O_F32] = ISD::SETEQ;
120 CCs[RTLIB::O_F64] = ISD::SETEQ;
123 TargetLowering::TargetLowering(TargetMachine &tm)
124 : TM(tm), TD(TM.getTargetData()) {
125 assert(ISD::BUILTIN_OP_END <= 156 &&
126 "Fixed size array in TargetLowering is not large enough!");
127 // All operations default to being supported.
128 memset(OpActions, 0, sizeof(OpActions));
129 memset(LoadXActions, 0, sizeof(LoadXActions));
130 memset(&StoreXActions, 0, sizeof(StoreXActions));
131 // Initialize all indexed load / store to expand.
132 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
133 for (unsigned IM = (unsigned)ISD::PRE_INC;
134 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
135 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
136 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
140 IsLittleEndian = TD->isLittleEndian();
141 UsesGlobalOffsetTable = false;
142 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
143 ShiftAmtHandling = Undefined;
144 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
145 memset(TargetDAGCombineArray, 0,
146 sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0]));
147 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
148 allowUnalignedMemoryAccesses = false;
149 UseUnderscoreSetJmp = false;
150 UseUnderscoreLongJmp = false;
151 SelectIsExpensive = false;
152 IntDivIsCheap = false;
153 Pow2DivIsCheap = false;
154 StackPointerRegisterToSaveRestore = 0;
155 ExceptionPointerRegister = 0;
156 ExceptionSelectorRegister = 0;
157 SchedPreferenceInfo = SchedulingForLatency;
159 JumpBufAlignment = 0;
160 IfCvtBlockSizeLimit = 2;
162 InitLibcallNames(LibcallRoutineNames);
163 InitCmpLibcallCCs(CmpLibcallCCs);
166 TargetLowering::~TargetLowering() {}
168 /// computeRegisterProperties - Once all of the register classes are added,
169 /// this allows us to compute derived properties we expose.
170 void TargetLowering::computeRegisterProperties() {
171 assert(MVT::LAST_VALUETYPE <= 32 &&
172 "Too many value types for ValueTypeActions to hold!");
174 // Everything defaults to needing one register.
175 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
176 NumRegistersForVT[i] = 1;
177 RegisterTypeForVT[i] = TransformToType[i] = i;
179 // ...except isVoid, which doesn't need any registers.
180 NumRegistersForVT[MVT::isVoid] = 0;
182 // Find the largest integer register class.
183 unsigned LargestIntReg = MVT::i128;
184 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
185 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
187 // Every integer value type larger than this largest register takes twice as
188 // many registers to represent as the previous ValueType.
189 for (MVT::ValueType ExpandedReg = LargestIntReg + 1;
190 MVT::isInteger(ExpandedReg); ++ExpandedReg) {
191 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
192 RegisterTypeForVT[ExpandedReg] = LargestIntReg;
193 TransformToType[ExpandedReg] = ExpandedReg - 1;
194 ValueTypeActions.setTypeAction(ExpandedReg, Expand);
197 // Inspect all of the ValueType's smaller than the largest integer
198 // register to see which ones need promotion.
199 MVT::ValueType LegalIntReg = LargestIntReg;
200 for (MVT::ValueType IntReg = LargestIntReg - 1;
201 IntReg >= MVT::i1; --IntReg) {
202 if (isTypeLegal(IntReg)) {
203 LegalIntReg = IntReg;
205 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg;
206 ValueTypeActions.setTypeAction(IntReg, Promote);
210 // Decide how to handle f64. If the target does not have native f64 support,
211 // expand it to i64 and we will be generating soft float library calls.
212 if (!isTypeLegal(MVT::f64)) {
213 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
214 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
215 TransformToType[MVT::f64] = MVT::i64;
216 ValueTypeActions.setTypeAction(MVT::f64, Expand);
219 // Decide how to handle f32. If the target does not have native support for
220 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
221 if (!isTypeLegal(MVT::f32)) {
222 if (isTypeLegal(MVT::f64)) {
223 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
224 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
225 TransformToType[MVT::f32] = MVT::f64;
226 ValueTypeActions.setTypeAction(MVT::f32, Promote);
228 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
229 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
230 TransformToType[MVT::f32] = MVT::i32;
231 ValueTypeActions.setTypeAction(MVT::f32, Expand);
235 // Loop over all of the vector value types to see which need transformations.
236 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE;
237 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
238 if (!isTypeLegal(i)) {
239 MVT::ValueType IntermediateVT, RegisterVT;
240 unsigned NumIntermediates;
241 NumRegistersForVT[i] =
242 getVectorTypeBreakdown(i,
243 IntermediateVT, NumIntermediates,
245 RegisterTypeForVT[i] = RegisterVT;
246 TransformToType[i] = MVT::Other; // this isn't actually used
247 ValueTypeActions.setTypeAction(i, Expand);
252 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
256 /// getVectorTypeBreakdown - Vector types are broken down into some number of
257 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
258 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
259 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
261 /// This method returns the number of registers needed, and the VT for each
262 /// register. It also returns the VT and quantity of the intermediate values
263 /// before they are promoted/expanded.
265 unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
266 MVT::ValueType &IntermediateVT,
267 unsigned &NumIntermediates,
268 MVT::ValueType &RegisterVT) const {
269 // Figure out the right, legal destination reg to copy into.
270 unsigned NumElts = MVT::getVectorNumElements(VT);
271 MVT::ValueType EltTy = MVT::getVectorElementType(VT);
273 unsigned NumVectorRegs = 1;
275 // Divide the input until we get to a supported size. This will always
276 // end with a scalar if the target doesn't support vectors.
277 while (NumElts > 1 &&
278 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
283 NumIntermediates = NumVectorRegs;
285 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts);
286 if (!isTypeLegal(NewVT))
288 IntermediateVT = NewVT;
290 MVT::ValueType DestVT = getTypeToTransformTo(NewVT);
292 if (DestVT < NewVT) {
293 // Value is expanded, e.g. i64 -> i16.
294 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT));
296 // Otherwise, promotion or legal types use the same number of registers as
297 // the vector decimated to the appropriate level.
298 return NumVectorRegs;
304 //===----------------------------------------------------------------------===//
305 // Optimization Methods
306 //===----------------------------------------------------------------------===//
308 /// ShrinkDemandedConstant - Check to see if the specified operand of the
309 /// specified instruction is a constant integer. If so, check to see if there
310 /// are any bits set in the constant that are not demanded. If so, shrink the
311 /// constant and return true.
312 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
314 // FIXME: ISD::SELECT, ISD::SELECT_CC
315 switch(Op.getOpcode()) {
320 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
321 if ((~Demanded & C->getValue()) != 0) {
322 MVT::ValueType VT = Op.getValueType();
323 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
324 DAG.getConstant(Demanded & C->getValue(),
326 return CombineTo(Op, New);
333 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
334 /// DemandedMask bits of the result of Op are ever used downstream. If we can
335 /// use this information to simplify Op, create a new simplified DAG node and
336 /// return true, returning the original and new nodes in Old and New. Otherwise,
337 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
338 /// the expression (used to simplify the caller). The KnownZero/One bits may
339 /// only be accurate for those bits in the DemandedMask.
340 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
343 TargetLoweringOpt &TLO,
344 unsigned Depth) const {
345 KnownZero = KnownOne = 0; // Don't know anything.
347 // The masks are not wide enough to represent this type! Should use APInt.
348 if (Op.getValueType() == MVT::i128)
351 // Other users may use these bits.
352 if (!Op.Val->hasOneUse()) {
354 // If not at the root, Just compute the KnownZero/KnownOne bits to
355 // simplify things downstream.
356 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
359 // If this is the root being simplified, allow it to have multiple uses,
360 // just set the DemandedMask to all bits.
361 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
362 } else if (DemandedMask == 0) {
363 // Not demanding any bits from Op.
364 if (Op.getOpcode() != ISD::UNDEF)
365 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
367 } else if (Depth == 6) { // Limit search depth.
371 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
372 switch (Op.getOpcode()) {
374 // We know all of the bits for a constant!
375 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
376 KnownZero = ~KnownOne & DemandedMask;
377 return false; // Don't fall through, will infinitely loop.
379 // If the RHS is a constant, check to see if the LHS would be zero without
380 // using the bits from the RHS. Below, we use knowledge about the RHS to
381 // simplify the LHS, here we're using information from the LHS to simplify
383 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
384 uint64_t LHSZero, LHSOne;
385 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask,
386 LHSZero, LHSOne, Depth+1);
387 // If the LHS already has zeros where RHSC does, this and is dead.
388 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
389 return TLO.CombineTo(Op, Op.getOperand(0));
390 // If any of the set bits in the RHS are known zero on the LHS, shrink
392 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
396 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
397 KnownOne, TLO, Depth+1))
399 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
400 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
401 KnownZero2, KnownOne2, TLO, Depth+1))
403 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
405 // If all of the demanded bits are known one on one side, return the other.
406 // These bits cannot contribute to the result of the 'and'.
407 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
408 return TLO.CombineTo(Op, Op.getOperand(0));
409 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
410 return TLO.CombineTo(Op, Op.getOperand(1));
411 // If all of the demanded bits in the inputs are known zeros, return zero.
412 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
413 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
414 // If the RHS is a constant, see if we can simplify it.
415 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
418 // Output known-1 bits are only known if set in both the LHS & RHS.
419 KnownOne &= KnownOne2;
420 // Output known-0 are known to be clear if zero in either the LHS | RHS.
421 KnownZero |= KnownZero2;
424 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
425 KnownOne, TLO, Depth+1))
427 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
428 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
429 KnownZero2, KnownOne2, TLO, Depth+1))
431 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
433 // If all of the demanded bits are known zero on one side, return the other.
434 // These bits cannot contribute to the result of the 'or'.
435 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
436 return TLO.CombineTo(Op, Op.getOperand(0));
437 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
438 return TLO.CombineTo(Op, Op.getOperand(1));
439 // If all of the potentially set bits on one side are known to be set on
440 // the other side, just use the 'other' side.
441 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
442 (DemandedMask & (~KnownZero)))
443 return TLO.CombineTo(Op, Op.getOperand(0));
444 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
445 (DemandedMask & (~KnownZero2)))
446 return TLO.CombineTo(Op, Op.getOperand(1));
447 // If the RHS is a constant, see if we can simplify it.
448 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
451 // Output known-0 bits are only known if clear in both the LHS & RHS.
452 KnownZero &= KnownZero2;
453 // Output known-1 are known to be set if set in either the LHS | RHS.
454 KnownOne |= KnownOne2;
457 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
458 KnownOne, TLO, Depth+1))
460 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
461 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
462 KnownOne2, TLO, Depth+1))
464 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
466 // If all of the demanded bits are known zero on one side, return the other.
467 // These bits cannot contribute to the result of the 'xor'.
468 if ((DemandedMask & KnownZero) == DemandedMask)
469 return TLO.CombineTo(Op, Op.getOperand(0));
470 if ((DemandedMask & KnownZero2) == DemandedMask)
471 return TLO.CombineTo(Op, Op.getOperand(1));
473 // If all of the unknown bits are known to be zero on one side or the other
474 // (but not both) turn this into an *inclusive* or.
475 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
476 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0)
477 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
481 // Output known-0 bits are known if clear or set in both the LHS & RHS.
482 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
483 // Output known-1 are known to be set if set in only one of the LHS, RHS.
484 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
486 // If all of the demanded bits on one side are known, and all of the set
487 // bits on that side are also known to be set on the other side, turn this
488 // into an AND, as we know the bits will be cleared.
489 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
490 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
491 if ((KnownOne & KnownOne2) == KnownOne) {
492 MVT::ValueType VT = Op.getValueType();
493 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
494 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
499 // If the RHS is a constant, see if we can simplify it.
500 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
501 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
504 KnownZero = KnownZeroOut;
505 KnownOne = KnownOneOut;
508 // If we know the result of a setcc has the top bits zero, use this info.
509 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
510 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
513 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
514 KnownOne, TLO, Depth+1))
516 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
517 KnownOne2, TLO, Depth+1))
519 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
520 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
522 // If the operands are constants, see if we can simplify them.
523 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
526 // Only known if known in both the LHS and RHS.
527 KnownOne &= KnownOne2;
528 KnownZero &= KnownZero2;
531 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
532 KnownOne, TLO, Depth+1))
534 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
535 KnownOne2, TLO, Depth+1))
537 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
538 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
540 // If the operands are constants, see if we can simplify them.
541 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
544 // Only known if known in both the LHS and RHS.
545 KnownOne &= KnownOne2;
546 KnownZero &= KnownZero2;
549 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
550 unsigned ShAmt = SA->getValue();
551 SDOperand InOp = Op.getOperand(0);
553 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
554 // single shift. We can do this if the bottom bits (which are shifted
555 // out) are never demanded.
556 if (InOp.getOpcode() == ISD::SRL &&
557 isa<ConstantSDNode>(InOp.getOperand(1))) {
558 if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) {
559 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
560 unsigned Opc = ISD::SHL;
568 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
569 MVT::ValueType VT = Op.getValueType();
570 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
571 InOp.getOperand(0), NewSA));
575 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt,
576 KnownZero, KnownOne, TLO, Depth+1))
578 KnownZero <<= SA->getValue();
579 KnownOne <<= SA->getValue();
580 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
584 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
585 MVT::ValueType VT = Op.getValueType();
586 unsigned ShAmt = SA->getValue();
587 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
588 unsigned VTSize = MVT::getSizeInBits(VT);
589 SDOperand InOp = Op.getOperand(0);
591 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
592 // single shift. We can do this if the top bits (which are shifted out)
593 // are never demanded.
594 if (InOp.getOpcode() == ISD::SHL &&
595 isa<ConstantSDNode>(InOp.getOperand(1))) {
596 if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) {
597 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
598 unsigned Opc = ISD::SRL;
606 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
607 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
608 InOp.getOperand(0), NewSA));
612 // Compute the new bits that are at the top now.
613 if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask,
614 KnownZero, KnownOne, TLO, Depth+1))
616 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
617 KnownZero &= TypeMask;
618 KnownOne &= TypeMask;
622 uint64_t HighBits = (1ULL << ShAmt)-1;
623 HighBits <<= VTSize - ShAmt;
624 KnownZero |= HighBits; // High bits known zero.
628 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
629 MVT::ValueType VT = Op.getValueType();
630 unsigned ShAmt = SA->getValue();
632 // Compute the new bits that are at the top now.
633 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
635 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
637 // If any of the demanded bits are produced by the sign extension, we also
638 // demand the input sign bit.
639 uint64_t HighBits = (1ULL << ShAmt)-1;
640 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
641 if (HighBits & DemandedMask)
642 InDemandedMask |= MVT::getIntVTSignBit(VT);
644 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
645 KnownZero, KnownOne, TLO, Depth+1))
647 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
648 KnownZero &= TypeMask;
649 KnownOne &= TypeMask;
653 // Handle the sign bits.
654 uint64_t SignBit = MVT::getIntVTSignBit(VT);
655 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
657 // If the input sign bit is known to be zero, or if none of the top bits
658 // are demanded, turn this into an unsigned shift right.
659 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
660 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
662 } else if (KnownOne & SignBit) { // New bits are known one.
663 KnownOne |= HighBits;
667 case ISD::SIGN_EXTEND_INREG: {
668 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
670 // Sign extension. Compute the demanded bits in the result that are not
671 // present in the input.
672 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
674 // If none of the extended bits are demanded, eliminate the sextinreg.
676 return TLO.CombineTo(Op, Op.getOperand(0));
678 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
679 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
681 // Since the sign extended bits are demanded, we know that the sign
683 InputDemandedBits |= InSignBit;
685 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
686 KnownZero, KnownOne, TLO, Depth+1))
688 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
690 // If the sign bit of the input is known set or clear, then we know the
691 // top bits of the result.
693 // If the input sign bit is known zero, convert this into a zero extension.
694 if (KnownZero & InSignBit)
695 return TLO.CombineTo(Op,
696 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
698 if (KnownOne & InSignBit) { // Input sign bit known set
700 KnownZero &= ~NewBits;
701 } else { // Input sign bit unknown
702 KnownZero &= ~NewBits;
703 KnownOne &= ~NewBits;
710 MVT::ValueType VT = Op.getValueType();
711 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
712 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
717 if (ISD::isZEXTLoad(Op.Val)) {
718 LoadSDNode *LD = cast<LoadSDNode>(Op);
719 MVT::ValueType VT = LD->getLoadedVT();
720 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
724 case ISD::ZERO_EXTEND: {
725 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
727 // If none of the top bits are demanded, convert this into an any_extend.
728 uint64_t NewBits = (~InMask) & DemandedMask;
730 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
734 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
735 KnownZero, KnownOne, TLO, Depth+1))
737 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
738 KnownZero |= NewBits;
741 case ISD::SIGN_EXTEND: {
742 MVT::ValueType InVT = Op.getOperand(0).getValueType();
743 uint64_t InMask = MVT::getIntVTBitMask(InVT);
744 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
745 uint64_t NewBits = (~InMask) & DemandedMask;
747 // If none of the top bits are demanded, convert this into an any_extend.
749 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
752 // Since some of the sign extended bits are demanded, we know that the sign
754 uint64_t InDemandedBits = DemandedMask & InMask;
755 InDemandedBits |= InSignBit;
757 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
758 KnownOne, TLO, Depth+1))
761 // If the sign bit is known zero, convert this to a zero extend.
762 if (KnownZero & InSignBit)
763 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
767 // If the sign bit is known one, the top bits match.
768 if (KnownOne & InSignBit) {
770 KnownZero &= ~NewBits;
771 } else { // Otherwise, top bits aren't known.
772 KnownOne &= ~NewBits;
773 KnownZero &= ~NewBits;
777 case ISD::ANY_EXTEND: {
778 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
779 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
780 KnownZero, KnownOne, TLO, Depth+1))
782 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
785 case ISD::TRUNCATE: {
786 // Simplify the input, using demanded bit information, and compute the known
787 // zero/one bits live out.
788 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
789 KnownZero, KnownOne, TLO, Depth+1))
792 // If the input is only used by this truncate, see if we can shrink it based
793 // on the known demanded bits.
794 if (Op.getOperand(0).Val->hasOneUse()) {
795 SDOperand In = Op.getOperand(0);
796 switch (In.getOpcode()) {
799 // Shrink SRL by a constant if none of the high bits shifted in are
801 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
802 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
803 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType());
804 HighBits >>= ShAmt->getValue();
806 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) &&
807 (DemandedMask & HighBits) == 0) {
808 // None of the shifted in bits are needed. Add a truncate of the
809 // shift input, then shift it.
810 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
813 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
814 NewTrunc, In.getOperand(1)));
821 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
822 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
823 KnownZero &= OutMask;
827 case ISD::AssertZext: {
828 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
829 uint64_t InMask = MVT::getIntVTBitMask(VT);
830 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
831 KnownZero, KnownOne, TLO, Depth+1))
833 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
834 KnownZero |= ~InMask & DemandedMask;
839 case ISD::INTRINSIC_WO_CHAIN:
840 case ISD::INTRINSIC_W_CHAIN:
841 case ISD::INTRINSIC_VOID:
842 // Just use ComputeMaskedBits to compute output bits.
843 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
847 // If we know the value of all of the demanded bits, return this as a
849 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
850 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
855 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
856 /// in Mask are known to be either zero or one and return them in the
857 /// KnownZero/KnownOne bitsets.
858 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
862 const SelectionDAG &DAG,
863 unsigned Depth) const {
864 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
865 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
866 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
867 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
868 "Should use MaskedValueIsZero if you don't know whether Op"
869 " is a target node!");
874 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
875 /// targets that want to expose additional information about sign bits to the
877 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
878 unsigned Depth) const {
879 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
880 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
881 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
882 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
883 "Should use ComputeNumSignBits if you don't know whether Op"
884 " is a target node!");
889 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
890 /// and cc. If it is unable to simplify it, return a null SDOperand.
892 TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
893 ISD::CondCode Cond, bool foldBooleans,
894 DAGCombinerInfo &DCI) const {
895 SelectionDAG &DAG = DCI.DAG;
897 // These setcc operations always fold.
901 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
903 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
906 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
907 uint64_t C1 = N1C->getValue();
908 if (isa<ConstantSDNode>(N0.Val)) {
909 return DAG.FoldSetCC(VT, N0, N1, Cond);
911 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
912 // equality comparison, then we're just comparing whether X itself is
914 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
915 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
916 N0.getOperand(1).getOpcode() == ISD::Constant) {
917 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
918 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
919 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
920 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
921 // (srl (ctlz x), 5) == 0 -> X != 0
922 // (srl (ctlz x), 5) != 1 -> X != 0
925 // (srl (ctlz x), 5) != 0 -> X == 0
926 // (srl (ctlz x), 5) == 1 -> X == 0
929 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
930 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
935 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
936 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
937 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
939 // If the comparison constant has bits in the upper part, the
940 // zero-extended value could never match.
941 if (C1 & (~0ULL << InSize)) {
942 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
946 case ISD::SETEQ: return DAG.getConstant(0, VT);
949 case ISD::SETNE: return DAG.getConstant(1, VT);
952 // True if the sign bit of C1 is set.
953 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT);
956 // True if the sign bit of C1 isn't set.
957 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT);
963 // Otherwise, we can perform the comparison with the low bits.
971 return DAG.getSetCC(VT, N0.getOperand(0),
972 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
975 break; // todo, be more careful with signed comparisons
977 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
978 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
979 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
980 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
981 MVT::ValueType ExtDstTy = N0.getValueType();
982 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
984 // If the extended part has any inconsistent bits, it cannot ever
985 // compare equal. In other words, they have to be all ones or all
988 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
989 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
990 return DAG.getConstant(Cond == ISD::SETNE, VT);
993 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
994 if (Op0Ty == ExtSrcTy) {
995 ZextOp = N0.getOperand(0);
997 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
998 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
999 DAG.getConstant(Imm, Op0Ty));
1001 if (!DCI.isCalledByLegalizer())
1002 DCI.AddToWorklist(ZextOp.Val);
1003 // Otherwise, make this a use of a zext.
1004 return DAG.getSetCC(VT, ZextOp,
1005 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1008 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
1009 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1011 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1012 if (N0.getOpcode() == ISD::SETCC) {
1013 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
1017 // Invert the condition.
1018 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1019 CC = ISD::getSetCCInverse(CC,
1020 MVT::isInteger(N0.getOperand(0).getValueType()));
1021 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
1024 if ((N0.getOpcode() == ISD::XOR ||
1025 (N0.getOpcode() == ISD::AND &&
1026 N0.getOperand(0).getOpcode() == ISD::XOR &&
1027 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1028 isa<ConstantSDNode>(N0.getOperand(1)) &&
1029 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
1030 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1031 // can only do this if the top bits are known zero.
1032 if (DAG.MaskedValueIsZero(N0,
1033 MVT::getIntVTBitMask(N0.getValueType())-1)){
1034 // Okay, get the un-inverted input value.
1036 if (N0.getOpcode() == ISD::XOR)
1037 Val = N0.getOperand(0);
1039 assert(N0.getOpcode() == ISD::AND &&
1040 N0.getOperand(0).getOpcode() == ISD::XOR);
1041 // ((X^1)&1)^1 -> X & 1
1042 Val = DAG.getNode(ISD::AND, N0.getValueType(),
1043 N0.getOperand(0).getOperand(0),
1046 return DAG.getSetCC(VT, Val, N1,
1047 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1052 uint64_t MinVal, MaxVal;
1053 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1054 if (ISD::isSignedIntSetCC(Cond)) {
1055 MinVal = 1ULL << (OperandBitSize-1);
1056 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
1057 MaxVal = ~0ULL >> (65-OperandBitSize);
1062 MaxVal = ~0ULL >> (64-OperandBitSize);
1065 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1066 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1067 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1068 --C1; // X >= C0 --> X > (C0-1)
1069 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1070 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1073 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1074 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1075 ++C1; // X <= C0 --> X < (C0+1)
1076 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1077 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1080 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1081 return DAG.getConstant(0, VT); // X < MIN --> false
1082 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1083 return DAG.getConstant(1, VT); // X >= MIN --> true
1084 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1085 return DAG.getConstant(0, VT); // X > MAX --> false
1086 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1087 return DAG.getConstant(1, VT); // X <= MAX --> true
1089 // Canonicalize setgt X, Min --> setne X, Min
1090 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1091 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1092 // Canonicalize setlt X, Max --> setne X, Max
1093 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1094 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1096 // If we have setult X, 1, turn it into seteq X, 0
1097 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1098 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1100 // If we have setugt X, Max-1, turn it into seteq X, Max
1101 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1102 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1105 // If we have "setcc X, C0", check to see if we can shrink the immediate
1108 // SETUGT X, SINTMAX -> SETLT X, 0
1109 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1110 C1 == (~0ULL >> (65-OperandBitSize)))
1111 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1114 // FIXME: Implement the rest of these.
1116 // Fold bit comparisons when we can.
1117 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1118 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1119 if (ConstantSDNode *AndRHS =
1120 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1121 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1122 // Perform the xform if the AND RHS is a single bit.
1123 if (isPowerOf2_64(AndRHS->getValue())) {
1124 return DAG.getNode(ISD::SRL, VT, N0,
1125 DAG.getConstant(Log2_64(AndRHS->getValue()),
1126 getShiftAmountTy()));
1128 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1129 // (X & 8) == 8 --> (X & 8) >> 3
1130 // Perform the xform if C1 is a single bit.
1131 if (isPowerOf2_64(C1)) {
1132 return DAG.getNode(ISD::SRL, VT, N0,
1133 DAG.getConstant(Log2_64(C1), getShiftAmountTy()));
1138 } else if (isa<ConstantSDNode>(N0.Val)) {
1139 // Ensure that the constant occurs on the RHS.
1140 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1143 if (isa<ConstantFPSDNode>(N0.Val)) {
1144 // Constant fold or commute setcc.
1145 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
1146 if (O.Val) return O;
1150 // We can always fold X == X for integer setcc's.
1151 if (MVT::isInteger(N0.getValueType()))
1152 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1153 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1154 if (UOF == 2) // FP operators that are undefined on NaNs.
1155 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1156 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1157 return DAG.getConstant(UOF, VT);
1158 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1159 // if it is not already.
1160 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1161 if (NewCond != Cond)
1162 return DAG.getSetCC(VT, N0, N1, NewCond);
1165 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1166 MVT::isInteger(N0.getValueType())) {
1167 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1168 N0.getOpcode() == ISD::XOR) {
1169 // Simplify (X+Y) == (X+Z) --> Y == Z
1170 if (N0.getOpcode() == N1.getOpcode()) {
1171 if (N0.getOperand(0) == N1.getOperand(0))
1172 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1173 if (N0.getOperand(1) == N1.getOperand(1))
1174 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1175 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1176 // If X op Y == Y op X, try other combinations.
1177 if (N0.getOperand(0) == N1.getOperand(1))
1178 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1179 if (N0.getOperand(1) == N1.getOperand(0))
1180 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
1184 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1185 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1186 // Turn (X+C1) == C2 --> X == C2-C1
1187 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
1188 return DAG.getSetCC(VT, N0.getOperand(0),
1189 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
1190 N0.getValueType()), Cond);
1193 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1194 if (N0.getOpcode() == ISD::XOR)
1195 // If we know that all of the inverted bits are zero, don't bother
1196 // performing the inversion.
1197 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
1198 return DAG.getSetCC(VT, N0.getOperand(0),
1199 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
1200 N0.getValueType()), Cond);
1203 // Turn (C1-X) == C2 --> X == C1-C2
1204 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1205 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
1206 return DAG.getSetCC(VT, N0.getOperand(1),
1207 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
1208 N0.getValueType()), Cond);
1213 // Simplify (X+Z) == X --> Z == 0
1214 if (N0.getOperand(0) == N1)
1215 return DAG.getSetCC(VT, N0.getOperand(1),
1216 DAG.getConstant(0, N0.getValueType()), Cond);
1217 if (N0.getOperand(1) == N1) {
1218 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1219 return DAG.getSetCC(VT, N0.getOperand(0),
1220 DAG.getConstant(0, N0.getValueType()), Cond);
1221 else if (N0.Val->hasOneUse()) {
1222 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1223 // (Z-X) == X --> Z == X<<1
1224 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1226 DAG.getConstant(1, getShiftAmountTy()));
1227 if (!DCI.isCalledByLegalizer())
1228 DCI.AddToWorklist(SH.Val);
1229 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1234 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1235 N1.getOpcode() == ISD::XOR) {
1236 // Simplify X == (X+Z) --> Z == 0
1237 if (N1.getOperand(0) == N0) {
1238 return DAG.getSetCC(VT, N1.getOperand(1),
1239 DAG.getConstant(0, N1.getValueType()), Cond);
1240 } else if (N1.getOperand(1) == N0) {
1241 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1242 return DAG.getSetCC(VT, N1.getOperand(0),
1243 DAG.getConstant(0, N1.getValueType()), Cond);
1244 } else if (N1.Val->hasOneUse()) {
1245 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1246 // X == (Z-X) --> X<<1 == Z
1247 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1248 DAG.getConstant(1, getShiftAmountTy()));
1249 if (!DCI.isCalledByLegalizer())
1250 DCI.AddToWorklist(SH.Val);
1251 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1257 // Fold away ALL boolean setcc's.
1259 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1261 default: assert(0 && "Unknown integer setcc!");
1262 case ISD::SETEQ: // X == Y -> (X^Y)^1
1263 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1264 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1265 if (!DCI.isCalledByLegalizer())
1266 DCI.AddToWorklist(Temp.Val);
1268 case ISD::SETNE: // X != Y --> (X^Y)
1269 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1271 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1272 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1273 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1274 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1275 if (!DCI.isCalledByLegalizer())
1276 DCI.AddToWorklist(Temp.Val);
1278 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1279 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1280 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1281 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1282 if (!DCI.isCalledByLegalizer())
1283 DCI.AddToWorklist(Temp.Val);
1285 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1286 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1287 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1288 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1289 if (!DCI.isCalledByLegalizer())
1290 DCI.AddToWorklist(Temp.Val);
1292 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1293 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1294 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1295 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1298 if (VT != MVT::i1) {
1299 if (!DCI.isCalledByLegalizer())
1300 DCI.AddToWorklist(N0.Val);
1301 // FIXME: If running after legalize, we probably can't do this.
1302 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1307 // Could not fold it.
1311 SDOperand TargetLowering::
1312 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1313 // Default implementation: no optimization.
1317 //===----------------------------------------------------------------------===//
1318 // Inline Assembler Implementation Methods
1319 //===----------------------------------------------------------------------===//
1321 TargetLowering::ConstraintType
1322 TargetLowering::getConstraintType(const std::string &Constraint) const {
1323 // FIXME: lots more standard ones to handle.
1324 if (Constraint.size() == 1) {
1325 switch (Constraint[0]) {
1327 case 'r': return C_RegisterClass;
1329 case 'o': // offsetable
1330 case 'V': // not offsetable
1332 case 'i': // Simple Integer or Relocatable Constant
1333 case 'n': // Simple Integer
1334 case 's': // Relocatable Constant
1335 case 'X': // Allow ANY value.
1336 case 'I': // Target registers.
1348 if (Constraint.size() > 1 && Constraint[0] == '{' &&
1349 Constraint[Constraint.size()-1] == '}')
1354 /// isOperandValidForConstraint - Return the specified operand (possibly
1355 /// modified) if the specified SDOperand is valid for the specified target
1356 /// constraint letter, otherwise return null.
1357 SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op,
1358 char ConstraintLetter,
1359 SelectionDAG &DAG) {
1360 switch (ConstraintLetter) {
1362 case 'i': // Simple Integer or Relocatable Constant
1363 case 'n': // Simple Integer
1364 case 's': // Relocatable Constant
1365 case 'X': { // Allows any operand.
1366 // These operands are interested in values of the form (GV+C), where C may
1367 // be folded in as an offset of GV, or it may be explicitly added. Also, it
1368 // is possible and fine if either GV or C are missing.
1369 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1370 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
1372 // If we have "(add GV, C)", pull out GV/C
1373 if (Op.getOpcode() == ISD::ADD) {
1374 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1375 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
1376 if (C == 0 || GA == 0) {
1377 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1378 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
1380 if (C == 0 || GA == 0)
1384 // If we find a valid operand, map to the TargetXXX version so that the
1385 // value itself doesn't get selected.
1386 if (GA) { // Either &GV or &GV+C
1387 if (ConstraintLetter != 'n') {
1388 int64_t Offs = GA->getOffset();
1389 if (C) Offs += C->getValue();
1390 return DAG.getTargetGlobalAddress(GA->getGlobal(), Op.getValueType(),
1394 if (C) { // just C, no GV.
1395 // Simple constants are not allowed for 's'.
1396 if (ConstraintLetter != 's')
1397 return DAG.getTargetConstant(C->getValue(), Op.getValueType());
1402 return SDOperand(0,0);
1405 std::vector<unsigned> TargetLowering::
1406 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1407 MVT::ValueType VT) const {
1408 return std::vector<unsigned>();
1412 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1413 getRegForInlineAsmConstraint(const std::string &Constraint,
1414 MVT::ValueType VT) const {
1415 if (Constraint[0] != '{')
1416 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1417 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1419 // Remove the braces from around the name.
1420 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1422 // Figure out which register class contains this reg.
1423 const MRegisterInfo *RI = TM.getRegisterInfo();
1424 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1425 E = RI->regclass_end(); RCI != E; ++RCI) {
1426 const TargetRegisterClass *RC = *RCI;
1428 // If none of the the value types for this register class are valid, we
1429 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1430 bool isLegal = false;
1431 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1433 if (isTypeLegal(*I)) {
1439 if (!isLegal) continue;
1441 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1443 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
1444 return std::make_pair(*I, RC);
1448 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1451 //===----------------------------------------------------------------------===//
1452 // Loop Strength Reduction hooks
1453 //===----------------------------------------------------------------------===//
1455 /// isLegalAddressingMode - Return true if the addressing mode represented
1456 /// by AM is legal for this target, for a load/store of the specified type.
1457 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
1458 const Type *Ty) const {
1459 // The default implementation of this implements a conservative RISCy, r+r and
1462 // Allows a sign-extended 16-bit immediate field.
1463 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1466 // No global is ever allowed as a base.
1470 // Only support r+r,
1472 case 0: // "r+i" or just "i", depending on HasBaseReg.
1475 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1477 // Otherwise we have r+r or r+i.
1480 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1482 // Allow 2*r as r+r.
1489 // Magic for divide replacement
1492 int64_t m; // magic number
1493 int64_t s; // shift amount
1497 uint64_t m; // magic number
1498 int64_t a; // add indicator
1499 int64_t s; // shift amount
1502 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1503 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1505 static ms magic32(int32_t d) {
1507 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
1508 const uint32_t two31 = 0x80000000U;
1512 t = two31 + ((uint32_t)d >> 31);
1513 anc = t - 1 - t%ad; // absolute value of nc
1514 p = 31; // initialize p
1515 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
1516 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1517 q2 = two31/ad; // initialize q2 = 2p/abs(d)
1518 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
1521 q1 = 2*q1; // update q1 = 2p/abs(nc)
1522 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1523 if (r1 >= anc) { // must be unsigned comparison
1527 q2 = 2*q2; // update q2 = 2p/abs(d)
1528 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1529 if (r2 >= ad) { // must be unsigned comparison
1534 } while (q1 < delta || (q1 == delta && r1 == 0));
1536 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
1537 if (d < 0) mag.m = -mag.m; // resulting magic number
1538 mag.s = p - 32; // resulting shift
1542 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1543 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1544 static mu magicu32(uint32_t d) {
1546 uint32_t nc, delta, q1, r1, q2, r2;
1548 magu.a = 0; // initialize "add" indicator
1550 p = 31; // initialize p
1551 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
1552 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
1553 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
1554 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
1557 if (r1 >= nc - r1 ) {
1558 q1 = 2*q1 + 1; // update q1
1559 r1 = 2*r1 - nc; // update r1
1562 q1 = 2*q1; // update q1
1563 r1 = 2*r1; // update r1
1565 if (r2 + 1 >= d - r2) {
1566 if (q2 >= 0x7FFFFFFF) magu.a = 1;
1567 q2 = 2*q2 + 1; // update q2
1568 r2 = 2*r2 + 1 - d; // update r2
1571 if (q2 >= 0x80000000) magu.a = 1;
1572 q2 = 2*q2; // update q2
1573 r2 = 2*r2 + 1; // update r2
1576 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
1577 magu.m = q2 + 1; // resulting magic number
1578 magu.s = p - 32; // resulting shift
1582 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1583 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1585 static ms magic64(int64_t d) {
1587 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
1588 const uint64_t two63 = 9223372036854775808ULL; // 2^63
1591 ad = d >= 0 ? d : -d;
1592 t = two63 + ((uint64_t)d >> 63);
1593 anc = t - 1 - t%ad; // absolute value of nc
1594 p = 63; // initialize p
1595 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
1596 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1597 q2 = two63/ad; // initialize q2 = 2p/abs(d)
1598 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
1601 q1 = 2*q1; // update q1 = 2p/abs(nc)
1602 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1603 if (r1 >= anc) { // must be unsigned comparison
1607 q2 = 2*q2; // update q2 = 2p/abs(d)
1608 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1609 if (r2 >= ad) { // must be unsigned comparison
1614 } while (q1 < delta || (q1 == delta && r1 == 0));
1617 if (d < 0) mag.m = -mag.m; // resulting magic number
1618 mag.s = p - 64; // resulting shift
1622 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1623 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1624 static mu magicu64(uint64_t d)
1627 uint64_t nc, delta, q1, r1, q2, r2;
1629 magu.a = 0; // initialize "add" indicator
1631 p = 63; // initialize p
1632 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
1633 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
1634 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
1635 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
1638 if (r1 >= nc - r1 ) {
1639 q1 = 2*q1 + 1; // update q1
1640 r1 = 2*r1 - nc; // update r1
1643 q1 = 2*q1; // update q1
1644 r1 = 2*r1; // update r1
1646 if (r2 + 1 >= d - r2) {
1647 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
1648 q2 = 2*q2 + 1; // update q2
1649 r2 = 2*r2 + 1 - d; // update r2
1652 if (q2 >= 0x8000000000000000ull) magu.a = 1;
1653 q2 = 2*q2; // update q2
1654 r2 = 2*r2 + 1; // update r2
1657 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
1658 magu.m = q2 + 1; // resulting magic number
1659 magu.s = p - 64; // resulting shift
1663 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
1664 /// return a DAG expression to select that will generate the same value by
1665 /// multiplying by a magic number. See:
1666 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1667 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
1668 std::vector<SDNode*>* Created) const {
1669 MVT::ValueType VT = N->getValueType(0);
1671 // Check to see if we can do this.
1672 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1673 return SDOperand(); // BuildSDIV only operates on i32 or i64
1674 if (!isOperationLegal(ISD::MULHS, VT))
1675 return SDOperand(); // Make sure the target supports MULHS.
1677 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
1678 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
1680 // Multiply the numerator (operand 0) by the magic value
1681 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
1682 DAG.getConstant(magics.m, VT));
1683 // If d > 0 and m < 0, add the numerator
1684 if (d > 0 && magics.m < 0) {
1685 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
1687 Created->push_back(Q.Val);
1689 // If d < 0 and m > 0, subtract the numerator.
1690 if (d < 0 && magics.m > 0) {
1691 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
1693 Created->push_back(Q.Val);
1695 // Shift right algebraic if shift value is nonzero
1697 Q = DAG.getNode(ISD::SRA, VT, Q,
1698 DAG.getConstant(magics.s, getShiftAmountTy()));
1700 Created->push_back(Q.Val);
1702 // Extract the sign bit and add it to the quotient
1704 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
1705 getShiftAmountTy()));
1707 Created->push_back(T.Val);
1708 return DAG.getNode(ISD::ADD, VT, Q, T);
1711 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
1712 /// return a DAG expression to select that will generate the same value by
1713 /// multiplying by a magic number. See:
1714 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1715 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
1716 std::vector<SDNode*>* Created) const {
1717 MVT::ValueType VT = N->getValueType(0);
1719 // Check to see if we can do this.
1720 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1721 return SDOperand(); // BuildUDIV only operates on i32 or i64
1722 if (!isOperationLegal(ISD::MULHU, VT))
1723 return SDOperand(); // Make sure the target supports MULHU.
1725 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1726 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
1728 // Multiply the numerator (operand 0) by the magic value
1729 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
1730 DAG.getConstant(magics.m, VT));
1732 Created->push_back(Q.Val);
1734 if (magics.a == 0) {
1735 return DAG.getNode(ISD::SRL, VT, Q,
1736 DAG.getConstant(magics.s, getShiftAmountTy()));
1738 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
1740 Created->push_back(NPQ.Val);
1741 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
1742 DAG.getConstant(1, getShiftAmountTy()));
1744 Created->push_back(NPQ.Val);
1745 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
1747 Created->push_back(NPQ.Val);
1748 return DAG.getNode(ISD::SRL, VT, NPQ,
1749 DAG.getConstant(magics.s-1, getShiftAmountTy()));