1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetAsmInfo.h"
15 #include "llvm/Target/TargetLowering.h"
16 #include "llvm/Target/TargetSubtarget.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
20 #include "llvm/GlobalVariable.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/Support/MathExtras.h"
29 /// InitLibcallNames - Set default libcall names.
31 static void InitLibcallNames(const char **Names) {
32 Names[RTLIB::SHL_I32] = "__ashlsi3";
33 Names[RTLIB::SHL_I64] = "__ashldi3";
34 Names[RTLIB::SHL_I128] = "__ashlti3";
35 Names[RTLIB::SRL_I32] = "__lshrsi3";
36 Names[RTLIB::SRL_I64] = "__lshrdi3";
37 Names[RTLIB::SRL_I128] = "__lshrti3";
38 Names[RTLIB::SRA_I32] = "__ashrsi3";
39 Names[RTLIB::SRA_I64] = "__ashrdi3";
40 Names[RTLIB::SRA_I128] = "__ashrti3";
41 Names[RTLIB::MUL_I32] = "__mulsi3";
42 Names[RTLIB::MUL_I64] = "__muldi3";
43 Names[RTLIB::MUL_I128] = "__multi3";
44 Names[RTLIB::SDIV_I32] = "__divsi3";
45 Names[RTLIB::SDIV_I64] = "__divdi3";
46 Names[RTLIB::SDIV_I128] = "__divti3";
47 Names[RTLIB::UDIV_I32] = "__udivsi3";
48 Names[RTLIB::UDIV_I64] = "__udivdi3";
49 Names[RTLIB::UDIV_I128] = "__udivti3";
50 Names[RTLIB::SREM_I32] = "__modsi3";
51 Names[RTLIB::SREM_I64] = "__moddi3";
52 Names[RTLIB::SREM_I128] = "__modti3";
53 Names[RTLIB::UREM_I32] = "__umodsi3";
54 Names[RTLIB::UREM_I64] = "__umoddi3";
55 Names[RTLIB::UREM_I128] = "__umodti3";
56 Names[RTLIB::NEG_I32] = "__negsi2";
57 Names[RTLIB::NEG_I64] = "__negdi2";
58 Names[RTLIB::ADD_F32] = "__addsf3";
59 Names[RTLIB::ADD_F64] = "__adddf3";
60 Names[RTLIB::ADD_F80] = "__addxf3";
61 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
62 Names[RTLIB::SUB_F32] = "__subsf3";
63 Names[RTLIB::SUB_F64] = "__subdf3";
64 Names[RTLIB::SUB_F80] = "__subxf3";
65 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
66 Names[RTLIB::MUL_F32] = "__mulsf3";
67 Names[RTLIB::MUL_F64] = "__muldf3";
68 Names[RTLIB::MUL_F80] = "__mulxf3";
69 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
70 Names[RTLIB::DIV_F32] = "__divsf3";
71 Names[RTLIB::DIV_F64] = "__divdf3";
72 Names[RTLIB::DIV_F80] = "__divxf3";
73 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
74 Names[RTLIB::REM_F32] = "fmodf";
75 Names[RTLIB::REM_F64] = "fmod";
76 Names[RTLIB::REM_F80] = "fmodl";
77 Names[RTLIB::REM_PPCF128] = "fmodl";
78 Names[RTLIB::POWI_F32] = "__powisf2";
79 Names[RTLIB::POWI_F64] = "__powidf2";
80 Names[RTLIB::POWI_F80] = "__powixf2";
81 Names[RTLIB::POWI_PPCF128] = "__powitf2";
82 Names[RTLIB::SQRT_F32] = "sqrtf";
83 Names[RTLIB::SQRT_F64] = "sqrt";
84 Names[RTLIB::SQRT_F80] = "sqrtl";
85 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
86 Names[RTLIB::LOG_F32] = "logf";
87 Names[RTLIB::LOG_F64] = "log";
88 Names[RTLIB::LOG_F80] = "logl";
89 Names[RTLIB::LOG_PPCF128] = "logl";
90 Names[RTLIB::LOG2_F32] = "log2f";
91 Names[RTLIB::LOG2_F64] = "log2";
92 Names[RTLIB::LOG2_F80] = "log2l";
93 Names[RTLIB::LOG2_PPCF128] = "log2l";
94 Names[RTLIB::LOG10_F32] = "log10f";
95 Names[RTLIB::LOG10_F64] = "log10";
96 Names[RTLIB::LOG10_F80] = "log10l";
97 Names[RTLIB::LOG10_PPCF128] = "log10l";
98 Names[RTLIB::EXP_F32] = "expf";
99 Names[RTLIB::EXP_F64] = "exp";
100 Names[RTLIB::EXP_F80] = "expl";
101 Names[RTLIB::EXP_PPCF128] = "expl";
102 Names[RTLIB::EXP2_F32] = "exp2f";
103 Names[RTLIB::EXP2_F64] = "exp2";
104 Names[RTLIB::EXP2_F80] = "exp2l";
105 Names[RTLIB::EXP2_PPCF128] = "exp2l";
106 Names[RTLIB::SIN_F32] = "sinf";
107 Names[RTLIB::SIN_F64] = "sin";
108 Names[RTLIB::SIN_F80] = "sinl";
109 Names[RTLIB::SIN_PPCF128] = "sinl";
110 Names[RTLIB::COS_F32] = "cosf";
111 Names[RTLIB::COS_F64] = "cos";
112 Names[RTLIB::COS_F80] = "cosl";
113 Names[RTLIB::COS_PPCF128] = "cosl";
114 Names[RTLIB::POW_F32] = "powf";
115 Names[RTLIB::POW_F64] = "pow";
116 Names[RTLIB::POW_F80] = "powl";
117 Names[RTLIB::POW_PPCF128] = "powl";
118 Names[RTLIB::CEIL_F32] = "ceilf";
119 Names[RTLIB::CEIL_F64] = "ceil";
120 Names[RTLIB::CEIL_F80] = "ceill";
121 Names[RTLIB::CEIL_PPCF128] = "ceill";
122 Names[RTLIB::TRUNC_F32] = "truncf";
123 Names[RTLIB::TRUNC_F64] = "trunc";
124 Names[RTLIB::TRUNC_F80] = "truncl";
125 Names[RTLIB::TRUNC_PPCF128] = "truncl";
126 Names[RTLIB::RINT_F32] = "rintf";
127 Names[RTLIB::RINT_F64] = "rint";
128 Names[RTLIB::RINT_F80] = "rintl";
129 Names[RTLIB::RINT_PPCF128] = "rintl";
130 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
131 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
132 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
133 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
134 Names[RTLIB::FLOOR_F32] = "floorf";
135 Names[RTLIB::FLOOR_F64] = "floor";
136 Names[RTLIB::FLOOR_F80] = "floorl";
137 Names[RTLIB::FLOOR_PPCF128] = "floorl";
138 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
139 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
140 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
141 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
142 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
143 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
144 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
145 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
146 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
147 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
148 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
149 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
150 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
151 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
152 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
153 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
154 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
155 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
156 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
157 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
158 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
159 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
160 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
161 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
162 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
163 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
164 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
165 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
166 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
167 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
168 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
169 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
170 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
171 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
172 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
173 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
174 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
175 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
176 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
177 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
178 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
179 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
180 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
181 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
182 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
183 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
184 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
185 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
186 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
187 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
188 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
189 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
190 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
191 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
192 Names[RTLIB::OEQ_F32] = "__eqsf2";
193 Names[RTLIB::OEQ_F64] = "__eqdf2";
194 Names[RTLIB::UNE_F32] = "__nesf2";
195 Names[RTLIB::UNE_F64] = "__nedf2";
196 Names[RTLIB::OGE_F32] = "__gesf2";
197 Names[RTLIB::OGE_F64] = "__gedf2";
198 Names[RTLIB::OLT_F32] = "__ltsf2";
199 Names[RTLIB::OLT_F64] = "__ltdf2";
200 Names[RTLIB::OLE_F32] = "__lesf2";
201 Names[RTLIB::OLE_F64] = "__ledf2";
202 Names[RTLIB::OGT_F32] = "__gtsf2";
203 Names[RTLIB::OGT_F64] = "__gtdf2";
204 Names[RTLIB::UO_F32] = "__unordsf2";
205 Names[RTLIB::UO_F64] = "__unorddf2";
206 Names[RTLIB::O_F32] = "__unordsf2";
207 Names[RTLIB::O_F64] = "__unorddf2";
210 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
211 /// UNKNOWN_LIBCALL if there is none.
212 RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) {
213 if (OpVT == MVT::f32) {
214 if (RetVT == MVT::f64)
215 return FPEXT_F32_F64;
217 return UNKNOWN_LIBCALL;
220 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
221 /// UNKNOWN_LIBCALL if there is none.
222 RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) {
223 if (RetVT == MVT::f32) {
224 if (OpVT == MVT::f64)
225 return FPROUND_F64_F32;
226 if (OpVT == MVT::f80)
227 return FPROUND_F80_F32;
228 if (OpVT == MVT::ppcf128)
229 return FPROUND_PPCF128_F32;
230 } else if (RetVT == MVT::f64) {
231 if (OpVT == MVT::f80)
232 return FPROUND_F80_F64;
233 if (OpVT == MVT::ppcf128)
234 return FPROUND_PPCF128_F64;
236 return UNKNOWN_LIBCALL;
239 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
240 /// UNKNOWN_LIBCALL if there is none.
241 RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) {
242 if (OpVT == MVT::f32) {
243 if (RetVT == MVT::i32)
244 return FPTOSINT_F32_I32;
245 if (RetVT == MVT::i64)
246 return FPTOSINT_F32_I64;
247 if (RetVT == MVT::i128)
248 return FPTOSINT_F32_I128;
249 } else if (OpVT == MVT::f64) {
250 if (RetVT == MVT::i32)
251 return FPTOSINT_F64_I32;
252 if (RetVT == MVT::i64)
253 return FPTOSINT_F64_I64;
254 if (RetVT == MVT::i128)
255 return FPTOSINT_F64_I128;
256 } else if (OpVT == MVT::f80) {
257 if (RetVT == MVT::i32)
258 return FPTOSINT_F80_I32;
259 if (RetVT == MVT::i64)
260 return FPTOSINT_F80_I64;
261 if (RetVT == MVT::i128)
262 return FPTOSINT_F80_I128;
263 } else if (OpVT == MVT::ppcf128) {
264 if (RetVT == MVT::i32)
265 return FPTOSINT_PPCF128_I32;
266 if (RetVT == MVT::i64)
267 return FPTOSINT_PPCF128_I64;
268 if (RetVT == MVT::i128)
269 return FPTOSINT_PPCF128_I128;
271 return UNKNOWN_LIBCALL;
274 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
275 /// UNKNOWN_LIBCALL if there is none.
276 RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) {
277 if (OpVT == MVT::f32) {
278 if (RetVT == MVT::i32)
279 return FPTOUINT_F32_I32;
280 if (RetVT == MVT::i64)
281 return FPTOUINT_F32_I64;
282 if (RetVT == MVT::i128)
283 return FPTOUINT_F32_I128;
284 } else if (OpVT == MVT::f64) {
285 if (RetVT == MVT::i32)
286 return FPTOUINT_F64_I32;
287 if (RetVT == MVT::i64)
288 return FPTOUINT_F64_I64;
289 if (RetVT == MVT::i128)
290 return FPTOUINT_F64_I128;
291 } else if (OpVT == MVT::f80) {
292 if (RetVT == MVT::i32)
293 return FPTOUINT_F80_I32;
294 if (RetVT == MVT::i64)
295 return FPTOUINT_F80_I64;
296 if (RetVT == MVT::i128)
297 return FPTOUINT_F80_I128;
298 } else if (OpVT == MVT::ppcf128) {
299 if (RetVT == MVT::i32)
300 return FPTOUINT_PPCF128_I32;
301 if (RetVT == MVT::i64)
302 return FPTOUINT_PPCF128_I64;
303 if (RetVT == MVT::i128)
304 return FPTOUINT_PPCF128_I128;
306 return UNKNOWN_LIBCALL;
309 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
310 /// UNKNOWN_LIBCALL if there is none.
311 RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) {
312 if (OpVT == MVT::i32) {
313 if (RetVT == MVT::f32)
314 return SINTTOFP_I32_F32;
315 else if (RetVT == MVT::f64)
316 return SINTTOFP_I32_F64;
317 else if (RetVT == MVT::f80)
318 return SINTTOFP_I32_F80;
319 else if (RetVT == MVT::ppcf128)
320 return SINTTOFP_I32_PPCF128;
321 } else if (OpVT == MVT::i64) {
322 if (RetVT == MVT::f32)
323 return SINTTOFP_I64_F32;
324 else if (RetVT == MVT::f64)
325 return SINTTOFP_I64_F64;
326 else if (RetVT == MVT::f80)
327 return SINTTOFP_I64_F80;
328 else if (RetVT == MVT::ppcf128)
329 return SINTTOFP_I64_PPCF128;
330 } else if (OpVT == MVT::i128) {
331 if (RetVT == MVT::f32)
332 return SINTTOFP_I128_F32;
333 else if (RetVT == MVT::f64)
334 return SINTTOFP_I128_F64;
335 else if (RetVT == MVT::f80)
336 return SINTTOFP_I128_F80;
337 else if (RetVT == MVT::ppcf128)
338 return SINTTOFP_I128_PPCF128;
340 return UNKNOWN_LIBCALL;
343 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
344 /// UNKNOWN_LIBCALL if there is none.
345 RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) {
346 if (OpVT == MVT::i32) {
347 if (RetVT == MVT::f32)
348 return UINTTOFP_I32_F32;
349 else if (RetVT == MVT::f64)
350 return UINTTOFP_I32_F64;
351 else if (RetVT == MVT::f80)
352 return UINTTOFP_I32_F80;
353 else if (RetVT == MVT::ppcf128)
354 return UINTTOFP_I32_PPCF128;
355 } else if (OpVT == MVT::i64) {
356 if (RetVT == MVT::f32)
357 return UINTTOFP_I64_F32;
358 else if (RetVT == MVT::f64)
359 return UINTTOFP_I64_F64;
360 else if (RetVT == MVT::f80)
361 return UINTTOFP_I64_F80;
362 else if (RetVT == MVT::ppcf128)
363 return UINTTOFP_I64_PPCF128;
364 } else if (OpVT == MVT::i128) {
365 if (RetVT == MVT::f32)
366 return UINTTOFP_I128_F32;
367 else if (RetVT == MVT::f64)
368 return UINTTOFP_I128_F64;
369 else if (RetVT == MVT::f80)
370 return UINTTOFP_I128_F80;
371 else if (RetVT == MVT::ppcf128)
372 return UINTTOFP_I128_PPCF128;
374 return UNKNOWN_LIBCALL;
377 /// InitCmpLibcallCCs - Set default comparison libcall CC.
379 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
380 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
381 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
382 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
383 CCs[RTLIB::UNE_F32] = ISD::SETNE;
384 CCs[RTLIB::UNE_F64] = ISD::SETNE;
385 CCs[RTLIB::OGE_F32] = ISD::SETGE;
386 CCs[RTLIB::OGE_F64] = ISD::SETGE;
387 CCs[RTLIB::OLT_F32] = ISD::SETLT;
388 CCs[RTLIB::OLT_F64] = ISD::SETLT;
389 CCs[RTLIB::OLE_F32] = ISD::SETLE;
390 CCs[RTLIB::OLE_F64] = ISD::SETLE;
391 CCs[RTLIB::OGT_F32] = ISD::SETGT;
392 CCs[RTLIB::OGT_F64] = ISD::SETGT;
393 CCs[RTLIB::UO_F32] = ISD::SETNE;
394 CCs[RTLIB::UO_F64] = ISD::SETNE;
395 CCs[RTLIB::O_F32] = ISD::SETEQ;
396 CCs[RTLIB::O_F64] = ISD::SETEQ;
399 TargetLowering::TargetLowering(TargetMachine &tm)
400 : TM(tm), TD(TM.getTargetData()) {
401 assert(ISD::BUILTIN_OP_END <= OpActionsCapacity &&
402 "Fixed size array in TargetLowering is not large enough!");
403 // All operations default to being supported.
404 memset(OpActions, 0, sizeof(OpActions));
405 memset(LoadXActions, 0, sizeof(LoadXActions));
406 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
407 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
408 memset(ConvertActions, 0, sizeof(ConvertActions));
410 // Set default actions for various operations.
411 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
412 // Default all indexed load / store to expand.
413 for (unsigned IM = (unsigned)ISD::PRE_INC;
414 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
415 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
416 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
419 // These operations default to expand.
420 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
423 // Most targets ignore the @llvm.prefetch intrinsic.
424 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
426 // ConstantFP nodes default to expand. Targets can either change this to
427 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate
428 // to optimize expansions for certain constants.
429 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
430 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
431 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
433 // These library functions default to expand.
434 setOperationAction(ISD::FLOG , MVT::f64, Expand);
435 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
436 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
437 setOperationAction(ISD::FEXP , MVT::f64, Expand);
438 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
439 setOperationAction(ISD::FLOG , MVT::f32, Expand);
440 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
441 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
442 setOperationAction(ISD::FEXP , MVT::f32, Expand);
443 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
445 // Default ISD::TRAP to expand (which turns it into abort).
446 setOperationAction(ISD::TRAP, MVT::Other, Expand);
448 IsLittleEndian = TD->isLittleEndian();
449 UsesGlobalOffsetTable = false;
450 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType());
451 ShiftAmtHandling = Undefined;
452 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
453 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
454 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
455 allowUnalignedMemoryAccesses = false;
456 UseUnderscoreSetJmp = false;
457 UseUnderscoreLongJmp = false;
458 SelectIsExpensive = false;
459 IntDivIsCheap = false;
460 Pow2DivIsCheap = false;
461 StackPointerRegisterToSaveRestore = 0;
462 ExceptionPointerRegister = 0;
463 ExceptionSelectorRegister = 0;
464 SetCCResultContents = UndefinedSetCCResult;
465 SchedPreferenceInfo = SchedulingForLatency;
467 JumpBufAlignment = 0;
468 IfCvtBlockSizeLimit = 2;
469 IfCvtDupBlockSizeLimit = 0;
470 PrefLoopAlignment = 0;
472 InitLibcallNames(LibcallRoutineNames);
473 InitCmpLibcallCCs(CmpLibcallCCs);
475 // Tell Legalize whether the assembler supports DEBUG_LOC.
476 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile())
477 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
480 TargetLowering::~TargetLowering() {}
482 /// computeRegisterProperties - Once all of the register classes are added,
483 /// this allows us to compute derived properties we expose.
484 void TargetLowering::computeRegisterProperties() {
485 assert(MVT::LAST_VALUETYPE <= 32 &&
486 "Too many value types for ValueTypeActions to hold!");
488 // Everything defaults to needing one register.
489 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
490 NumRegistersForVT[i] = 1;
491 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
493 // ...except isVoid, which doesn't need any registers.
494 NumRegistersForVT[MVT::isVoid] = 0;
496 // Find the largest integer register class.
497 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
498 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
499 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
501 // Every integer value type larger than this largest register takes twice as
502 // many registers to represent as the previous ValueType.
503 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
504 MVT EVT = (MVT::SimpleValueType)ExpandedReg;
505 if (!EVT.isInteger())
507 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
508 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
509 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
510 ValueTypeActions.setTypeAction(EVT, Expand);
513 // Inspect all of the ValueType's smaller than the largest integer
514 // register to see which ones need promotion.
515 unsigned LegalIntReg = LargestIntReg;
516 for (unsigned IntReg = LargestIntReg - 1;
517 IntReg >= (unsigned)MVT::i1; --IntReg) {
518 MVT IVT = (MVT::SimpleValueType)IntReg;
519 if (isTypeLegal(IVT)) {
520 LegalIntReg = IntReg;
522 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
523 (MVT::SimpleValueType)LegalIntReg;
524 ValueTypeActions.setTypeAction(IVT, Promote);
528 // ppcf128 type is really two f64's.
529 if (!isTypeLegal(MVT::ppcf128)) {
530 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
531 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
532 TransformToType[MVT::ppcf128] = MVT::f64;
533 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
536 // Decide how to handle f64. If the target does not have native f64 support,
537 // expand it to i64 and we will be generating soft float library calls.
538 if (!isTypeLegal(MVT::f64)) {
539 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
540 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
541 TransformToType[MVT::f64] = MVT::i64;
542 ValueTypeActions.setTypeAction(MVT::f64, Expand);
545 // Decide how to handle f32. If the target does not have native support for
546 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
547 if (!isTypeLegal(MVT::f32)) {
548 if (isTypeLegal(MVT::f64)) {
549 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
550 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
551 TransformToType[MVT::f32] = MVT::f64;
552 ValueTypeActions.setTypeAction(MVT::f32, Promote);
554 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
555 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
556 TransformToType[MVT::f32] = MVT::i32;
557 ValueTypeActions.setTypeAction(MVT::f32, Expand);
561 // Loop over all of the vector value types to see which need transformations.
562 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
563 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
564 MVT VT = (MVT::SimpleValueType)i;
565 if (!isTypeLegal(VT)) {
566 MVT IntermediateVT, RegisterVT;
567 unsigned NumIntermediates;
568 NumRegistersForVT[i] =
569 getVectorTypeBreakdown(VT,
570 IntermediateVT, NumIntermediates,
572 RegisterTypeForVT[i] = RegisterVT;
573 TransformToType[i] = MVT::Other; // this isn't actually used
574 ValueTypeActions.setTypeAction(VT, Expand);
579 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
584 MVT TargetLowering::getSetCCResultType(const SDValue &) const {
585 return getValueType(TD->getIntPtrType());
589 /// getVectorTypeBreakdown - Vector types are broken down into some number of
590 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
591 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
592 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
594 /// This method returns the number of registers needed, and the VT for each
595 /// register. It also returns the VT and quantity of the intermediate values
596 /// before they are promoted/expanded.
598 unsigned TargetLowering::getVectorTypeBreakdown(MVT VT,
600 unsigned &NumIntermediates,
601 MVT &RegisterVT) const {
602 // Figure out the right, legal destination reg to copy into.
603 unsigned NumElts = VT.getVectorNumElements();
604 MVT EltTy = VT.getVectorElementType();
606 unsigned NumVectorRegs = 1;
608 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
609 // could break down into LHS/RHS like LegalizeDAG does.
610 if (!isPowerOf2_32(NumElts)) {
611 NumVectorRegs = NumElts;
615 // Divide the input until we get to a supported size. This will always
616 // end with a scalar if the target doesn't support vectors.
617 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
622 NumIntermediates = NumVectorRegs;
624 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
625 if (!isTypeLegal(NewVT))
627 IntermediateVT = NewVT;
629 MVT DestVT = getTypeToTransformTo(NewVT);
631 if (DestVT.bitsLT(NewVT)) {
632 // Value is expanded, e.g. i64 -> i16.
633 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
635 // Otherwise, promotion or legal types use the same number of registers as
636 // the vector decimated to the appropriate level.
637 return NumVectorRegs;
643 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
644 /// function arguments in the caller parameter area. This is the actual
645 /// alignment, not its logarithm.
646 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
647 return TD->getCallFrameTypeAlignment(Ty);
650 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
651 SelectionDAG &DAG) const {
652 if (usesGlobalOffsetTable())
653 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
657 //===----------------------------------------------------------------------===//
658 // Optimization Methods
659 //===----------------------------------------------------------------------===//
661 /// ShrinkDemandedConstant - Check to see if the specified operand of the
662 /// specified instruction is a constant integer. If so, check to see if there
663 /// are any bits set in the constant that are not demanded. If so, shrink the
664 /// constant and return true.
665 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
666 const APInt &Demanded) {
667 // FIXME: ISD::SELECT, ISD::SELECT_CC
668 switch(Op.getOpcode()) {
673 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
674 if (C->getAPIntValue().intersects(~Demanded)) {
675 MVT VT = Op.getValueType();
676 SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
677 DAG.getConstant(Demanded &
680 return CombineTo(Op, New);
687 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
688 /// DemandedMask bits of the result of Op are ever used downstream. If we can
689 /// use this information to simplify Op, create a new simplified DAG node and
690 /// return true, returning the original and new nodes in Old and New. Otherwise,
691 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
692 /// the expression (used to simplify the caller). The KnownZero/One bits may
693 /// only be accurate for those bits in the DemandedMask.
694 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
695 const APInt &DemandedMask,
698 TargetLoweringOpt &TLO,
699 unsigned Depth) const {
700 unsigned BitWidth = DemandedMask.getBitWidth();
701 assert(Op.getValueSizeInBits() == BitWidth &&
702 "Mask size mismatches value type size!");
703 APInt NewMask = DemandedMask;
705 // Don't know anything.
706 KnownZero = KnownOne = APInt(BitWidth, 0);
708 // Other users may use these bits.
709 if (!Op.getNode()->hasOneUse()) {
711 // If not at the root, Just compute the KnownZero/KnownOne bits to
712 // simplify things downstream.
713 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
716 // If this is the root being simplified, allow it to have multiple uses,
717 // just set the NewMask to all bits.
718 NewMask = APInt::getAllOnesValue(BitWidth);
719 } else if (DemandedMask == 0) {
720 // Not demanding any bits from Op.
721 if (Op.getOpcode() != ISD::UNDEF)
722 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
724 } else if (Depth == 6) { // Limit search depth.
728 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
729 switch (Op.getOpcode()) {
731 // We know all of the bits for a constant!
732 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
733 KnownZero = ~KnownOne & NewMask;
734 return false; // Don't fall through, will infinitely loop.
736 // If the RHS is a constant, check to see if the LHS would be zero without
737 // using the bits from the RHS. Below, we use knowledge about the RHS to
738 // simplify the LHS, here we're using information from the LHS to simplify
740 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
741 APInt LHSZero, LHSOne;
742 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
743 LHSZero, LHSOne, Depth+1);
744 // If the LHS already has zeros where RHSC does, this and is dead.
745 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
746 return TLO.CombineTo(Op, Op.getOperand(0));
747 // If any of the set bits in the RHS are known zero on the LHS, shrink
749 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
753 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
754 KnownOne, TLO, Depth+1))
756 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
757 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
758 KnownZero2, KnownOne2, TLO, Depth+1))
760 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
762 // If all of the demanded bits are known one on one side, return the other.
763 // These bits cannot contribute to the result of the 'and'.
764 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
765 return TLO.CombineTo(Op, Op.getOperand(0));
766 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
767 return TLO.CombineTo(Op, Op.getOperand(1));
768 // If all of the demanded bits in the inputs are known zeros, return zero.
769 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
770 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
771 // If the RHS is a constant, see if we can simplify it.
772 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
775 // Output known-1 bits are only known if set in both the LHS & RHS.
776 KnownOne &= KnownOne2;
777 // Output known-0 are known to be clear if zero in either the LHS | RHS.
778 KnownZero |= KnownZero2;
781 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
782 KnownOne, TLO, Depth+1))
784 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
785 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
786 KnownZero2, KnownOne2, TLO, Depth+1))
788 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
790 // If all of the demanded bits are known zero on one side, return the other.
791 // These bits cannot contribute to the result of the 'or'.
792 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
793 return TLO.CombineTo(Op, Op.getOperand(0));
794 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
795 return TLO.CombineTo(Op, Op.getOperand(1));
796 // If all of the potentially set bits on one side are known to be set on
797 // the other side, just use the 'other' side.
798 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
799 return TLO.CombineTo(Op, Op.getOperand(0));
800 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
801 return TLO.CombineTo(Op, Op.getOperand(1));
802 // If the RHS is a constant, see if we can simplify it.
803 if (TLO.ShrinkDemandedConstant(Op, NewMask))
806 // Output known-0 bits are only known if clear in both the LHS & RHS.
807 KnownZero &= KnownZero2;
808 // Output known-1 are known to be set if set in either the LHS | RHS.
809 KnownOne |= KnownOne2;
812 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
813 KnownOne, TLO, Depth+1))
815 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
816 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
817 KnownOne2, TLO, Depth+1))
819 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
821 // If all of the demanded bits are known zero on one side, return the other.
822 // These bits cannot contribute to the result of the 'xor'.
823 if ((KnownZero & NewMask) == NewMask)
824 return TLO.CombineTo(Op, Op.getOperand(0));
825 if ((KnownZero2 & NewMask) == NewMask)
826 return TLO.CombineTo(Op, Op.getOperand(1));
828 // If all of the unknown bits are known to be zero on one side or the other
829 // (but not both) turn this into an *inclusive* or.
830 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
831 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
832 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
836 // Output known-0 bits are known if clear or set in both the LHS & RHS.
837 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
838 // Output known-1 are known to be set if set in only one of the LHS, RHS.
839 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
841 // If all of the demanded bits on one side are known, and all of the set
842 // bits on that side are also known to be set on the other side, turn this
843 // into an AND, as we know the bits will be cleared.
844 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
845 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
846 if ((KnownOne & KnownOne2) == KnownOne) {
847 MVT VT = Op.getValueType();
848 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
849 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
854 // If the RHS is a constant, see if we can simplify it.
855 // for XOR, we prefer to force bits to 1 if they will make a -1.
856 // if we can't force bits, try to shrink constant
857 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
858 APInt Expanded = C->getAPIntValue() | (~NewMask);
859 // if we can expand it to have all bits set, do it
860 if (Expanded.isAllOnesValue()) {
861 if (Expanded != C->getAPIntValue()) {
862 MVT VT = Op.getValueType();
863 SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
864 TLO.DAG.getConstant(Expanded, VT));
865 return TLO.CombineTo(Op, New);
867 // if it already has all the bits set, nothing to change
868 // but don't shrink either!
869 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
874 KnownZero = KnownZeroOut;
875 KnownOne = KnownOneOut;
878 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
879 KnownOne, TLO, Depth+1))
881 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
882 KnownOne2, TLO, Depth+1))
884 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
885 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
887 // If the operands are constants, see if we can simplify them.
888 if (TLO.ShrinkDemandedConstant(Op, NewMask))
891 // Only known if known in both the LHS and RHS.
892 KnownOne &= KnownOne2;
893 KnownZero &= KnownZero2;
896 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
897 KnownOne, TLO, Depth+1))
899 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
900 KnownOne2, TLO, Depth+1))
902 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
903 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
905 // If the operands are constants, see if we can simplify them.
906 if (TLO.ShrinkDemandedConstant(Op, NewMask))
909 // Only known if known in both the LHS and RHS.
910 KnownOne &= KnownOne2;
911 KnownZero &= KnownZero2;
914 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
915 unsigned ShAmt = SA->getZExtValue();
916 SDValue InOp = Op.getOperand(0);
918 // If the shift count is an invalid immediate, don't do anything.
919 if (ShAmt >= BitWidth)
922 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
923 // single shift. We can do this if the bottom bits (which are shifted
924 // out) are never demanded.
925 if (InOp.getOpcode() == ISD::SRL &&
926 isa<ConstantSDNode>(InOp.getOperand(1))) {
927 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
928 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
929 unsigned Opc = ISD::SHL;
937 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
938 MVT VT = Op.getValueType();
939 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
940 InOp.getOperand(0), NewSA));
944 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
945 KnownZero, KnownOne, TLO, Depth+1))
947 KnownZero <<= SA->getZExtValue();
948 KnownOne <<= SA->getZExtValue();
949 // low bits known zero.
950 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
954 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
955 MVT VT = Op.getValueType();
956 unsigned ShAmt = SA->getZExtValue();
957 unsigned VTSize = VT.getSizeInBits();
958 SDValue InOp = Op.getOperand(0);
960 // If the shift count is an invalid immediate, don't do anything.
961 if (ShAmt >= BitWidth)
964 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
965 // single shift. We can do this if the top bits (which are shifted out)
966 // are never demanded.
967 if (InOp.getOpcode() == ISD::SHL &&
968 isa<ConstantSDNode>(InOp.getOperand(1))) {
969 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
970 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
971 unsigned Opc = ISD::SRL;
979 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
980 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
981 InOp.getOperand(0), NewSA));
985 // Compute the new bits that are at the top now.
986 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
987 KnownZero, KnownOne, TLO, Depth+1))
989 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
990 KnownZero = KnownZero.lshr(ShAmt);
991 KnownOne = KnownOne.lshr(ShAmt);
993 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
994 KnownZero |= HighBits; // High bits known zero.
998 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
999 MVT VT = Op.getValueType();
1000 unsigned ShAmt = SA->getZExtValue();
1002 // If the shift count is an invalid immediate, don't do anything.
1003 if (ShAmt >= BitWidth)
1006 APInt InDemandedMask = (NewMask << ShAmt);
1008 // If any of the demanded bits are produced by the sign extension, we also
1009 // demand the input sign bit.
1010 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1011 if (HighBits.intersects(NewMask))
1012 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits());
1014 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1015 KnownZero, KnownOne, TLO, Depth+1))
1017 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1018 KnownZero = KnownZero.lshr(ShAmt);
1019 KnownOne = KnownOne.lshr(ShAmt);
1021 // Handle the sign bit, adjusted to where it is now in the mask.
1022 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1024 // If the input sign bit is known to be zero, or if none of the top bits
1025 // are demanded, turn this into an unsigned shift right.
1026 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1027 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
1029 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1030 KnownOne |= HighBits;
1034 case ISD::SIGN_EXTEND_INREG: {
1035 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1037 // Sign extension. Compute the demanded bits in the result that are not
1038 // present in the input.
1039 APInt NewBits = APInt::getHighBitsSet(BitWidth,
1040 BitWidth - EVT.getSizeInBits()) &
1043 // If none of the extended bits are demanded, eliminate the sextinreg.
1045 return TLO.CombineTo(Op, Op.getOperand(0));
1047 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits());
1048 InSignBit.zext(BitWidth);
1049 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
1050 EVT.getSizeInBits()) &
1053 // Since the sign extended bits are demanded, we know that the sign
1055 InputDemandedBits |= InSignBit;
1057 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1058 KnownZero, KnownOne, TLO, Depth+1))
1060 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1062 // If the sign bit of the input is known set or clear, then we know the
1063 // top bits of the result.
1065 // If the input sign bit is known zero, convert this into a zero extension.
1066 if (KnownZero.intersects(InSignBit))
1067 return TLO.CombineTo(Op,
1068 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
1070 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1071 KnownOne |= NewBits;
1072 KnownZero &= ~NewBits;
1073 } else { // Input sign bit unknown
1074 KnownZero &= ~NewBits;
1075 KnownOne &= ~NewBits;
1079 case ISD::ZERO_EXTEND: {
1080 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1081 APInt InMask = NewMask;
1082 InMask.trunc(OperandBitWidth);
1084 // If none of the top bits are demanded, convert this into an any_extend.
1086 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1087 if (!NewBits.intersects(NewMask))
1088 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
1092 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1093 KnownZero, KnownOne, TLO, Depth+1))
1095 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1096 KnownZero.zext(BitWidth);
1097 KnownOne.zext(BitWidth);
1098 KnownZero |= NewBits;
1101 case ISD::SIGN_EXTEND: {
1102 MVT InVT = Op.getOperand(0).getValueType();
1103 unsigned InBits = InVT.getSizeInBits();
1104 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1105 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1106 APInt NewBits = ~InMask & NewMask;
1108 // If none of the top bits are demanded, convert this into an any_extend.
1110 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
1113 // Since some of the sign extended bits are demanded, we know that the sign
1115 APInt InDemandedBits = InMask & NewMask;
1116 InDemandedBits |= InSignBit;
1117 InDemandedBits.trunc(InBits);
1119 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1120 KnownOne, TLO, Depth+1))
1122 KnownZero.zext(BitWidth);
1123 KnownOne.zext(BitWidth);
1125 // If the sign bit is known zero, convert this to a zero extend.
1126 if (KnownZero.intersects(InSignBit))
1127 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
1131 // If the sign bit is known one, the top bits match.
1132 if (KnownOne.intersects(InSignBit)) {
1133 KnownOne |= NewBits;
1134 KnownZero &= ~NewBits;
1135 } else { // Otherwise, top bits aren't known.
1136 KnownOne &= ~NewBits;
1137 KnownZero &= ~NewBits;
1141 case ISD::ANY_EXTEND: {
1142 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1143 APInt InMask = NewMask;
1144 InMask.trunc(OperandBitWidth);
1145 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1146 KnownZero, KnownOne, TLO, Depth+1))
1148 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1149 KnownZero.zext(BitWidth);
1150 KnownOne.zext(BitWidth);
1153 case ISD::TRUNCATE: {
1154 // Simplify the input, using demanded bit information, and compute the known
1155 // zero/one bits live out.
1156 APInt TruncMask = NewMask;
1157 TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
1158 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1159 KnownZero, KnownOne, TLO, Depth+1))
1161 KnownZero.trunc(BitWidth);
1162 KnownOne.trunc(BitWidth);
1164 // If the input is only used by this truncate, see if we can shrink it based
1165 // on the known demanded bits.
1166 if (Op.getOperand(0).getNode()->hasOneUse()) {
1167 SDValue In = Op.getOperand(0);
1168 unsigned InBitWidth = In.getValueSizeInBits();
1169 switch (In.getOpcode()) {
1172 // Shrink SRL by a constant if none of the high bits shifted in are
1174 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1175 APInt HighBits = APInt::getHighBitsSet(InBitWidth,
1176 InBitWidth - BitWidth);
1177 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1178 HighBits.trunc(BitWidth);
1180 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1181 // None of the shifted in bits are needed. Add a truncate of the
1182 // shift input, then shift it.
1183 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
1186 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
1187 NewTrunc, In.getOperand(1)));
1194 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1197 case ISD::AssertZext: {
1198 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1199 APInt InMask = APInt::getLowBitsSet(BitWidth,
1200 VT.getSizeInBits());
1201 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1202 KnownZero, KnownOne, TLO, Depth+1))
1204 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1205 KnownZero |= ~InMask & NewMask;
1208 case ISD::BIT_CONVERT:
1210 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1211 // is demanded, turn this into a FGETSIGN.
1212 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) &&
1213 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1214 !MVT::isVector(Op.getOperand(0).getValueType())) {
1215 // Only do this xform if FGETSIGN is valid or if before legalize.
1216 if (!TLO.AfterLegalize ||
1217 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1218 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1219 // place. We expect the SHL to be eliminated by other optimizations.
1220 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1222 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1223 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1224 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1231 // Just use ComputeMaskedBits to compute output bits.
1232 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1236 // If we know the value of all of the demanded bits, return this as a
1238 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1239 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1244 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1245 /// in Mask are known to be either zero or one and return them in the
1246 /// KnownZero/KnownOne bitsets.
1247 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1251 const SelectionDAG &DAG,
1252 unsigned Depth) const {
1253 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1254 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1255 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1256 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1257 "Should use MaskedValueIsZero if you don't know whether Op"
1258 " is a target node!");
1259 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1262 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1263 /// targets that want to expose additional information about sign bits to the
1265 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1266 unsigned Depth) const {
1267 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1268 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1269 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1270 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1271 "Should use ComputeNumSignBits if you don't know whether Op"
1272 " is a target node!");
1277 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1278 /// and cc. If it is unable to simplify it, return a null SDValue.
1280 TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
1281 ISD::CondCode Cond, bool foldBooleans,
1282 DAGCombinerInfo &DCI) const {
1283 SelectionDAG &DAG = DCI.DAG;
1285 // These setcc operations always fold.
1289 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1291 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1294 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1295 const APInt &C1 = N1C->getAPIntValue();
1296 if (isa<ConstantSDNode>(N0.getNode())) {
1297 return DAG.FoldSetCC(VT, N0, N1, Cond);
1299 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1300 // equality comparison, then we're just comparing whether X itself is
1302 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1303 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1304 N0.getOperand(1).getOpcode() == ISD::Constant) {
1305 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1306 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1307 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1308 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1309 // (srl (ctlz x), 5) == 0 -> X != 0
1310 // (srl (ctlz x), 5) != 1 -> X != 0
1313 // (srl (ctlz x), 5) != 0 -> X == 0
1314 // (srl (ctlz x), 5) == 1 -> X == 0
1317 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1318 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
1323 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1324 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1325 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1327 // If the comparison constant has bits in the upper part, the
1328 // zero-extended value could never match.
1329 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1330 C1.getBitWidth() - InSize))) {
1334 case ISD::SETEQ: return DAG.getConstant(0, VT);
1337 case ISD::SETNE: return DAG.getConstant(1, VT);
1340 // True if the sign bit of C1 is set.
1341 return DAG.getConstant(C1.isNegative(), VT);
1344 // True if the sign bit of C1 isn't set.
1345 return DAG.getConstant(C1.isNonNegative(), VT);
1351 // Otherwise, we can perform the comparison with the low bits.
1359 return DAG.getSetCC(VT, N0.getOperand(0),
1360 DAG.getConstant(APInt(C1).trunc(InSize),
1361 N0.getOperand(0).getValueType()),
1364 break; // todo, be more careful with signed comparisons
1366 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1367 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1368 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1369 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1370 MVT ExtDstTy = N0.getValueType();
1371 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1373 // If the extended part has any inconsistent bits, it cannot ever
1374 // compare equal. In other words, they have to be all ones or all
1377 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1378 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1379 return DAG.getConstant(Cond == ISD::SETNE, VT);
1382 MVT Op0Ty = N0.getOperand(0).getValueType();
1383 if (Op0Ty == ExtSrcTy) {
1384 ZextOp = N0.getOperand(0);
1386 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1387 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1388 DAG.getConstant(Imm, Op0Ty));
1390 if (!DCI.isCalledByLegalizer())
1391 DCI.AddToWorklist(ZextOp.getNode());
1392 // Otherwise, make this a use of a zext.
1393 return DAG.getSetCC(VT, ZextOp,
1394 DAG.getConstant(C1 & APInt::getLowBitsSet(
1399 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1400 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1402 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1403 if (N0.getOpcode() == ISD::SETCC) {
1404 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
1408 // Invert the condition.
1409 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1410 CC = ISD::getSetCCInverse(CC,
1411 N0.getOperand(0).getValueType().isInteger());
1412 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
1415 if ((N0.getOpcode() == ISD::XOR ||
1416 (N0.getOpcode() == ISD::AND &&
1417 N0.getOperand(0).getOpcode() == ISD::XOR &&
1418 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1419 isa<ConstantSDNode>(N0.getOperand(1)) &&
1420 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1421 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1422 // can only do this if the top bits are known zero.
1423 unsigned BitWidth = N0.getValueSizeInBits();
1424 if (DAG.MaskedValueIsZero(N0,
1425 APInt::getHighBitsSet(BitWidth,
1427 // Okay, get the un-inverted input value.
1429 if (N0.getOpcode() == ISD::XOR)
1430 Val = N0.getOperand(0);
1432 assert(N0.getOpcode() == ISD::AND &&
1433 N0.getOperand(0).getOpcode() == ISD::XOR);
1434 // ((X^1)&1)^1 -> X & 1
1435 Val = DAG.getNode(ISD::AND, N0.getValueType(),
1436 N0.getOperand(0).getOperand(0),
1439 return DAG.getSetCC(VT, Val, N1,
1440 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1445 APInt MinVal, MaxVal;
1446 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1447 if (ISD::isSignedIntSetCC(Cond)) {
1448 MinVal = APInt::getSignedMinValue(OperandBitSize);
1449 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1451 MinVal = APInt::getMinValue(OperandBitSize);
1452 MaxVal = APInt::getMaxValue(OperandBitSize);
1455 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1456 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1457 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1458 // X >= C0 --> X > (C0-1)
1459 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()),
1460 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1463 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1464 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1465 // X <= C0 --> X < (C0+1)
1466 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()),
1467 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1470 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1471 return DAG.getConstant(0, VT); // X < MIN --> false
1472 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1473 return DAG.getConstant(1, VT); // X >= MIN --> true
1474 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1475 return DAG.getConstant(0, VT); // X > MAX --> false
1476 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1477 return DAG.getConstant(1, VT); // X <= MAX --> true
1479 // Canonicalize setgt X, Min --> setne X, Min
1480 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1481 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1482 // Canonicalize setlt X, Max --> setne X, Max
1483 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1484 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1486 // If we have setult X, 1, turn it into seteq X, 0
1487 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1488 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1490 // If we have setugt X, Max-1, turn it into seteq X, Max
1491 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1492 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1495 // If we have "setcc X, C0", check to see if we can shrink the immediate
1498 // SETUGT X, SINTMAX -> SETLT X, 0
1499 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1500 C1 == (~0ULL >> (65-OperandBitSize)))
1501 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1504 // FIXME: Implement the rest of these.
1506 // Fold bit comparisons when we can.
1507 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1508 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1509 if (ConstantSDNode *AndRHS =
1510 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1511 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1512 // Perform the xform if the AND RHS is a single bit.
1513 if (isPowerOf2_64(AndRHS->getZExtValue())) {
1514 return DAG.getNode(ISD::SRL, VT, N0,
1515 DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
1516 getShiftAmountTy()));
1518 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
1519 // (X & 8) == 8 --> (X & 8) >> 3
1520 // Perform the xform if C1 is a single bit.
1521 if (C1.isPowerOf2()) {
1522 return DAG.getNode(ISD::SRL, VT, N0,
1523 DAG.getConstant(C1.logBase2(), getShiftAmountTy()));
1528 } else if (isa<ConstantSDNode>(N0.getNode())) {
1529 // Ensure that the constant occurs on the RHS.
1530 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1533 if (isa<ConstantFPSDNode>(N0.getNode())) {
1534 // Constant fold or commute setcc.
1535 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond);
1536 if (O.getNode()) return O;
1537 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1538 // If the RHS of an FP comparison is a constant, simplify it away in
1540 if (CFP->getValueAPF().isNaN()) {
1541 // If an operand is known to be a nan, we can fold it.
1542 switch (ISD::getUnorderedFlavor(Cond)) {
1543 default: assert(0 && "Unknown flavor!");
1544 case 0: // Known false.
1545 return DAG.getConstant(0, VT);
1546 case 1: // Known true.
1547 return DAG.getConstant(1, VT);
1548 case 2: // Undefined.
1549 return DAG.getNode(ISD::UNDEF, VT);
1553 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1554 // constant if knowing that the operand is non-nan is enough. We prefer to
1555 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1557 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1558 return DAG.getSetCC(VT, N0, N0, Cond);
1562 // We can always fold X == X for integer setcc's.
1563 if (N0.getValueType().isInteger())
1564 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1565 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1566 if (UOF == 2) // FP operators that are undefined on NaNs.
1567 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1568 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1569 return DAG.getConstant(UOF, VT);
1570 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1571 // if it is not already.
1572 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1573 if (NewCond != Cond)
1574 return DAG.getSetCC(VT, N0, N1, NewCond);
1577 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1578 N0.getValueType().isInteger()) {
1579 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1580 N0.getOpcode() == ISD::XOR) {
1581 // Simplify (X+Y) == (X+Z) --> Y == Z
1582 if (N0.getOpcode() == N1.getOpcode()) {
1583 if (N0.getOperand(0) == N1.getOperand(0))
1584 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1585 if (N0.getOperand(1) == N1.getOperand(1))
1586 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1587 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1588 // If X op Y == Y op X, try other combinations.
1589 if (N0.getOperand(0) == N1.getOperand(1))
1590 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1591 if (N0.getOperand(1) == N1.getOperand(0))
1592 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
1596 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1597 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1598 // Turn (X+C1) == C2 --> X == C2-C1
1599 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1600 return DAG.getSetCC(VT, N0.getOperand(0),
1601 DAG.getConstant(RHSC->getAPIntValue()-
1602 LHSR->getAPIntValue(),
1603 N0.getValueType()), Cond);
1606 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1607 if (N0.getOpcode() == ISD::XOR)
1608 // If we know that all of the inverted bits are zero, don't bother
1609 // performing the inversion.
1610 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1612 DAG.getSetCC(VT, N0.getOperand(0),
1613 DAG.getConstant(LHSR->getAPIntValue() ^
1614 RHSC->getAPIntValue(),
1619 // Turn (C1-X) == C2 --> X == C1-C2
1620 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1621 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1623 DAG.getSetCC(VT, N0.getOperand(1),
1624 DAG.getConstant(SUBC->getAPIntValue() -
1625 RHSC->getAPIntValue(),
1632 // Simplify (X+Z) == X --> Z == 0
1633 if (N0.getOperand(0) == N1)
1634 return DAG.getSetCC(VT, N0.getOperand(1),
1635 DAG.getConstant(0, N0.getValueType()), Cond);
1636 if (N0.getOperand(1) == N1) {
1637 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1638 return DAG.getSetCC(VT, N0.getOperand(0),
1639 DAG.getConstant(0, N0.getValueType()), Cond);
1640 else if (N0.getNode()->hasOneUse()) {
1641 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1642 // (Z-X) == X --> Z == X<<1
1643 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1645 DAG.getConstant(1, getShiftAmountTy()));
1646 if (!DCI.isCalledByLegalizer())
1647 DCI.AddToWorklist(SH.getNode());
1648 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1653 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1654 N1.getOpcode() == ISD::XOR) {
1655 // Simplify X == (X+Z) --> Z == 0
1656 if (N1.getOperand(0) == N0) {
1657 return DAG.getSetCC(VT, N1.getOperand(1),
1658 DAG.getConstant(0, N1.getValueType()), Cond);
1659 } else if (N1.getOperand(1) == N0) {
1660 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1661 return DAG.getSetCC(VT, N1.getOperand(0),
1662 DAG.getConstant(0, N1.getValueType()), Cond);
1663 } else if (N1.getNode()->hasOneUse()) {
1664 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1665 // X == (Z-X) --> X<<1 == Z
1666 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1667 DAG.getConstant(1, getShiftAmountTy()));
1668 if (!DCI.isCalledByLegalizer())
1669 DCI.AddToWorklist(SH.getNode());
1670 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1676 // Fold away ALL boolean setcc's.
1678 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1680 default: assert(0 && "Unknown integer setcc!");
1681 case ISD::SETEQ: // X == Y -> (X^Y)^1
1682 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1683 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1684 if (!DCI.isCalledByLegalizer())
1685 DCI.AddToWorklist(Temp.getNode());
1687 case ISD::SETNE: // X != Y --> (X^Y)
1688 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1690 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1691 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1692 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1693 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1694 if (!DCI.isCalledByLegalizer())
1695 DCI.AddToWorklist(Temp.getNode());
1697 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1698 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1699 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1700 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1701 if (!DCI.isCalledByLegalizer())
1702 DCI.AddToWorklist(Temp.getNode());
1704 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1705 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1706 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1707 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1708 if (!DCI.isCalledByLegalizer())
1709 DCI.AddToWorklist(Temp.getNode());
1711 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1712 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1713 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1714 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1717 if (VT != MVT::i1) {
1718 if (!DCI.isCalledByLegalizer())
1719 DCI.AddToWorklist(N0.getNode());
1720 // FIXME: If running after legalize, we probably can't do this.
1721 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1726 // Could not fold it.
1730 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1731 /// node is a GlobalAddress + offset.
1732 bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
1733 int64_t &Offset) const {
1734 if (isa<GlobalAddressSDNode>(N)) {
1735 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
1736 GA = GASD->getGlobal();
1737 Offset += GASD->getOffset();
1741 if (N->getOpcode() == ISD::ADD) {
1742 SDValue N1 = N->getOperand(0);
1743 SDValue N2 = N->getOperand(1);
1744 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
1745 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
1747 Offset += V->getSExtValue();
1750 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
1751 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
1753 Offset += V->getSExtValue();
1762 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
1763 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
1764 /// location that the 'Base' load is loading from.
1765 bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
1766 unsigned Bytes, int Dist,
1767 const MachineFrameInfo *MFI) const {
1768 if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode())
1770 MVT VT = LD->getValueType(0);
1771 if (VT.getSizeInBits() / 8 != Bytes)
1774 SDValue Loc = LD->getOperand(1);
1775 SDValue BaseLoc = Base->getOperand(1);
1776 if (Loc.getOpcode() == ISD::FrameIndex) {
1777 if (BaseLoc.getOpcode() != ISD::FrameIndex)
1779 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
1780 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
1781 int FS = MFI->getObjectSize(FI);
1782 int BFS = MFI->getObjectSize(BFI);
1783 if (FS != BFS || FS != (int)Bytes) return false;
1784 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
1787 GlobalValue *GV1 = NULL;
1788 GlobalValue *GV2 = NULL;
1789 int64_t Offset1 = 0;
1790 int64_t Offset2 = 0;
1791 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
1792 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
1793 if (isGA1 && isGA2 && GV1 == GV2)
1794 return Offset1 == (Offset2 + Dist*Bytes);
1799 SDValue TargetLowering::
1800 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1801 // Default implementation: no optimization.
1805 //===----------------------------------------------------------------------===//
1806 // Inline Assembler Implementation Methods
1807 //===----------------------------------------------------------------------===//
1810 TargetLowering::ConstraintType
1811 TargetLowering::getConstraintType(const std::string &Constraint) const {
1812 // FIXME: lots more standard ones to handle.
1813 if (Constraint.size() == 1) {
1814 switch (Constraint[0]) {
1816 case 'r': return C_RegisterClass;
1818 case 'o': // offsetable
1819 case 'V': // not offsetable
1821 case 'i': // Simple Integer or Relocatable Constant
1822 case 'n': // Simple Integer
1823 case 's': // Relocatable Constant
1824 case 'X': // Allow ANY value.
1825 case 'I': // Target registers.
1837 if (Constraint.size() > 1 && Constraint[0] == '{' &&
1838 Constraint[Constraint.size()-1] == '}')
1843 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1844 /// with another that has more specific requirements based on the type of the
1845 /// corresponding operand.
1846 const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{
1847 if (ConstraintVT.isInteger())
1849 if (ConstraintVT.isFloatingPoint())
1850 return "f"; // works for many targets
1854 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1855 /// vector. If it is invalid, don't add anything to Ops.
1856 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
1857 char ConstraintLetter,
1859 std::vector<SDValue> &Ops,
1860 SelectionDAG &DAG) const {
1861 switch (ConstraintLetter) {
1863 case 'X': // Allows any operand; labels (basic block) use this.
1864 if (Op.getOpcode() == ISD::BasicBlock) {
1869 case 'i': // Simple Integer or Relocatable Constant
1870 case 'n': // Simple Integer
1871 case 's': { // Relocatable Constant
1872 // These operands are interested in values of the form (GV+C), where C may
1873 // be folded in as an offset of GV, or it may be explicitly added. Also, it
1874 // is possible and fine if either GV or C are missing.
1875 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1876 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
1878 // If we have "(add GV, C)", pull out GV/C
1879 if (Op.getOpcode() == ISD::ADD) {
1880 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1881 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
1882 if (C == 0 || GA == 0) {
1883 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1884 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
1886 if (C == 0 || GA == 0)
1890 // If we find a valid operand, map to the TargetXXX version so that the
1891 // value itself doesn't get selected.
1892 if (GA) { // Either &GV or &GV+C
1893 if (ConstraintLetter != 'n') {
1894 int64_t Offs = GA->getOffset();
1895 if (C) Offs += C->getZExtValue();
1896 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
1897 Op.getValueType(), Offs));
1901 if (C) { // just C, no GV.
1902 // Simple constants are not allowed for 's'.
1903 if (ConstraintLetter != 's') {
1904 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue(),
1905 Op.getValueType()));
1914 std::vector<unsigned> TargetLowering::
1915 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1917 return std::vector<unsigned>();
1921 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1922 getRegForInlineAsmConstraint(const std::string &Constraint,
1924 if (Constraint[0] != '{')
1925 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1926 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1928 // Remove the braces from around the name.
1929 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1931 // Figure out which register class contains this reg.
1932 const TargetRegisterInfo *RI = TM.getRegisterInfo();
1933 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1934 E = RI->regclass_end(); RCI != E; ++RCI) {
1935 const TargetRegisterClass *RC = *RCI;
1937 // If none of the the value types for this register class are valid, we
1938 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1939 bool isLegal = false;
1940 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1942 if (isTypeLegal(*I)) {
1948 if (!isLegal) continue;
1950 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1952 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
1953 return std::make_pair(*I, RC);
1957 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1960 //===----------------------------------------------------------------------===//
1961 // Constraint Selection.
1963 /// getConstraintGenerality - Return an integer indicating how general CT
1965 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
1967 default: assert(0 && "Unknown constraint type!");
1968 case TargetLowering::C_Other:
1969 case TargetLowering::C_Unknown:
1971 case TargetLowering::C_Register:
1973 case TargetLowering::C_RegisterClass:
1975 case TargetLowering::C_Memory:
1980 /// ChooseConstraint - If there are multiple different constraints that we
1981 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
1982 /// This is somewhat tricky: constraints fall into four classes:
1983 /// Other -> immediates and magic values
1984 /// Register -> one specific register
1985 /// RegisterClass -> a group of regs
1986 /// Memory -> memory
1987 /// Ideally, we would pick the most specific constraint possible: if we have
1988 /// something that fits into a register, we would pick it. The problem here
1989 /// is that if we have something that could either be in a register or in
1990 /// memory that use of the register could cause selection of *other*
1991 /// operands to fail: they might only succeed if we pick memory. Because of
1992 /// this the heuristic we use is:
1994 /// 1) If there is an 'other' constraint, and if the operand is valid for
1995 /// that constraint, use it. This makes us take advantage of 'i'
1996 /// constraints when available.
1997 /// 2) Otherwise, pick the most general constraint present. This prefers
1998 /// 'm' over 'r', for example.
2000 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2001 bool hasMemory, const TargetLowering &TLI,
2002 SDValue Op, SelectionDAG *DAG) {
2003 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2004 unsigned BestIdx = 0;
2005 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2006 int BestGenerality = -1;
2008 // Loop over the options, keeping track of the most general one.
2009 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2010 TargetLowering::ConstraintType CType =
2011 TLI.getConstraintType(OpInfo.Codes[i]);
2013 // If this is an 'other' constraint, see if the operand is valid for it.
2014 // For example, on X86 we might have an 'rI' constraint. If the operand
2015 // is an integer in the range [0..31] we want to use I (saving a load
2016 // of a register), otherwise we must use 'r'.
2017 if (CType == TargetLowering::C_Other && Op.getNode()) {
2018 assert(OpInfo.Codes[i].size() == 1 &&
2019 "Unhandled multi-letter 'other' constraint");
2020 std::vector<SDValue> ResultOps;
2021 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2023 if (!ResultOps.empty()) {
2030 // This constraint letter is more general than the previous one, use it.
2031 int Generality = getConstraintGenerality(CType);
2032 if (Generality > BestGenerality) {
2035 BestGenerality = Generality;
2039 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2040 OpInfo.ConstraintType = BestType;
2043 /// ComputeConstraintToUse - Determines the constraint code and constraint
2044 /// type to use for the specific AsmOperandInfo, setting
2045 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2046 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2049 SelectionDAG *DAG) const {
2050 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2052 // Single-letter constraints ('r') are very common.
2053 if (OpInfo.Codes.size() == 1) {
2054 OpInfo.ConstraintCode = OpInfo.Codes[0];
2055 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2057 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2060 // 'X' matches anything.
2061 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2062 // Labels and constants are handled elsewhere ('X' is the only thing
2063 // that matches labels).
2064 if (isa<BasicBlock>(OpInfo.CallOperandVal) ||
2065 isa<ConstantInt>(OpInfo.CallOperandVal))
2068 // Otherwise, try to resolve it to something we know about by looking at
2069 // the actual operand type.
2070 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2071 OpInfo.ConstraintCode = Repl;
2072 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2077 //===----------------------------------------------------------------------===//
2078 // Loop Strength Reduction hooks
2079 //===----------------------------------------------------------------------===//
2081 /// isLegalAddressingMode - Return true if the addressing mode represented
2082 /// by AM is legal for this target, for a load/store of the specified type.
2083 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2084 const Type *Ty) const {
2085 // The default implementation of this implements a conservative RISCy, r+r and
2088 // Allows a sign-extended 16-bit immediate field.
2089 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2092 // No global is ever allowed as a base.
2096 // Only support r+r,
2098 case 0: // "r+i" or just "i", depending on HasBaseReg.
2101 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2103 // Otherwise we have r+r or r+i.
2106 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2108 // Allow 2*r as r+r.
2115 // Magic for divide replacement
2118 int64_t m; // magic number
2119 int64_t s; // shift amount
2123 uint64_t m; // magic number
2124 int64_t a; // add indicator
2125 int64_t s; // shift amount
2128 /// magic - calculate the magic numbers required to codegen an integer sdiv as
2129 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
2131 static ms magic32(int32_t d) {
2133 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
2134 const uint32_t two31 = 0x80000000U;
2138 t = two31 + ((uint32_t)d >> 31);
2139 anc = t - 1 - t%ad; // absolute value of nc
2140 p = 31; // initialize p
2141 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
2142 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
2143 q2 = two31/ad; // initialize q2 = 2p/abs(d)
2144 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
2147 q1 = 2*q1; // update q1 = 2p/abs(nc)
2148 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
2149 if (r1 >= anc) { // must be unsigned comparison
2153 q2 = 2*q2; // update q2 = 2p/abs(d)
2154 r2 = 2*r2; // update r2 = rem(2p/abs(d))
2155 if (r2 >= ad) { // must be unsigned comparison
2160 } while (q1 < delta || (q1 == delta && r1 == 0));
2162 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
2163 if (d < 0) mag.m = -mag.m; // resulting magic number
2164 mag.s = p - 32; // resulting shift
2168 /// magicu - calculate the magic numbers required to codegen an integer udiv as
2169 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
2170 static mu magicu32(uint32_t d) {
2172 uint32_t nc, delta, q1, r1, q2, r2;
2174 magu.a = 0; // initialize "add" indicator
2176 p = 31; // initialize p
2177 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
2178 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
2179 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
2180 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
2183 if (r1 >= nc - r1 ) {
2184 q1 = 2*q1 + 1; // update q1
2185 r1 = 2*r1 - nc; // update r1
2188 q1 = 2*q1; // update q1
2189 r1 = 2*r1; // update r1
2191 if (r2 + 1 >= d - r2) {
2192 if (q2 >= 0x7FFFFFFF) magu.a = 1;
2193 q2 = 2*q2 + 1; // update q2
2194 r2 = 2*r2 + 1 - d; // update r2
2197 if (q2 >= 0x80000000) magu.a = 1;
2198 q2 = 2*q2; // update q2
2199 r2 = 2*r2 + 1; // update r2
2202 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
2203 magu.m = q2 + 1; // resulting magic number
2204 magu.s = p - 32; // resulting shift
2208 /// magic - calculate the magic numbers required to codegen an integer sdiv as
2209 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
2211 static ms magic64(int64_t d) {
2213 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
2214 const uint64_t two63 = 9223372036854775808ULL; // 2^63
2217 ad = d >= 0 ? d : -d;
2218 t = two63 + ((uint64_t)d >> 63);
2219 anc = t - 1 - t%ad; // absolute value of nc
2220 p = 63; // initialize p
2221 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
2222 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
2223 q2 = two63/ad; // initialize q2 = 2p/abs(d)
2224 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
2227 q1 = 2*q1; // update q1 = 2p/abs(nc)
2228 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
2229 if (r1 >= anc) { // must be unsigned comparison
2233 q2 = 2*q2; // update q2 = 2p/abs(d)
2234 r2 = 2*r2; // update r2 = rem(2p/abs(d))
2235 if (r2 >= ad) { // must be unsigned comparison
2240 } while (q1 < delta || (q1 == delta && r1 == 0));
2243 if (d < 0) mag.m = -mag.m; // resulting magic number
2244 mag.s = p - 64; // resulting shift
2248 /// magicu - calculate the magic numbers required to codegen an integer udiv as
2249 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
2250 static mu magicu64(uint64_t d)
2253 uint64_t nc, delta, q1, r1, q2, r2;
2255 magu.a = 0; // initialize "add" indicator
2257 p = 63; // initialize p
2258 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
2259 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
2260 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
2261 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
2264 if (r1 >= nc - r1 ) {
2265 q1 = 2*q1 + 1; // update q1
2266 r1 = 2*r1 - nc; // update r1
2269 q1 = 2*q1; // update q1
2270 r1 = 2*r1; // update r1
2272 if (r2 + 1 >= d - r2) {
2273 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
2274 q2 = 2*q2 + 1; // update q2
2275 r2 = 2*r2 + 1 - d; // update r2
2278 if (q2 >= 0x8000000000000000ull) magu.a = 1;
2279 q2 = 2*q2; // update q2
2280 r2 = 2*r2 + 1; // update r2
2283 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
2284 magu.m = q2 + 1; // resulting magic number
2285 magu.s = p - 64; // resulting shift
2289 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2290 /// return a DAG expression to select that will generate the same value by
2291 /// multiplying by a magic number. See:
2292 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2293 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2294 std::vector<SDNode*>* Created) const {
2295 MVT VT = N->getValueType(0);
2297 // Check to see if we can do this.
2298 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2299 return SDValue(); // BuildSDIV only operates on i32 or i64
2301 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue();
2302 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2304 // Multiply the numerator (operand 0) by the magic value
2306 if (isOperationLegal(ISD::MULHS, VT))
2307 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2308 DAG.getConstant(magics.m, VT));
2309 else if (isOperationLegal(ISD::SMUL_LOHI, VT))
2310 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
2312 DAG.getConstant(magics.m, VT)).getNode(), 1);
2314 return SDValue(); // No mulhs or equvialent
2315 // If d > 0 and m < 0, add the numerator
2316 if (d > 0 && magics.m < 0) {
2317 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2319 Created->push_back(Q.getNode());
2321 // If d < 0 and m > 0, subtract the numerator.
2322 if (d < 0 && magics.m > 0) {
2323 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2325 Created->push_back(Q.getNode());
2327 // Shift right algebraic if shift value is nonzero
2329 Q = DAG.getNode(ISD::SRA, VT, Q,
2330 DAG.getConstant(magics.s, getShiftAmountTy()));
2332 Created->push_back(Q.getNode());
2334 // Extract the sign bit and add it to the quotient
2336 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2337 getShiftAmountTy()));
2339 Created->push_back(T.getNode());
2340 return DAG.getNode(ISD::ADD, VT, Q, T);
2343 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2344 /// return a DAG expression to select that will generate the same value by
2345 /// multiplying by a magic number. See:
2346 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2347 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2348 std::vector<SDNode*>* Created) const {
2349 MVT VT = N->getValueType(0);
2351 // Check to see if we can do this.
2352 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2353 return SDValue(); // BuildUDIV only operates on i32 or i64
2355 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2356 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2358 // Multiply the numerator (operand 0) by the magic value
2360 if (isOperationLegal(ISD::MULHU, VT))
2361 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2362 DAG.getConstant(magics.m, VT));
2363 else if (isOperationLegal(ISD::UMUL_LOHI, VT))
2364 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
2366 DAG.getConstant(magics.m, VT)).getNode(), 1);
2368 return SDValue(); // No mulhu or equvialent
2370 Created->push_back(Q.getNode());
2372 if (magics.a == 0) {
2373 return DAG.getNode(ISD::SRL, VT, Q,
2374 DAG.getConstant(magics.s, getShiftAmountTy()));
2376 SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2378 Created->push_back(NPQ.getNode());
2379 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2380 DAG.getConstant(1, getShiftAmountTy()));
2382 Created->push_back(NPQ.getNode());
2383 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2385 Created->push_back(NPQ.getNode());
2386 return DAG.getNode(ISD::SRL, VT, NPQ,
2387 DAG.getConstant(magics.s-1, getShiftAmountTy()));