1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetSubtarget.h"
16 #include "llvm/Target/TargetData.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/MRegisterInfo.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/CallingConv.h"
28 /// InitLibcallNames - Set default libcall names.
30 static void InitLibcallNames(const char **Names) {
31 Names[RTLIB::SHL_I32] = "__ashlsi3";
32 Names[RTLIB::SHL_I64] = "__ashldi3";
33 Names[RTLIB::SRL_I32] = "__lshrsi3";
34 Names[RTLIB::SRL_I64] = "__lshrdi3";
35 Names[RTLIB::SRA_I32] = "__ashrsi3";
36 Names[RTLIB::SRA_I64] = "__ashrdi3";
37 Names[RTLIB::MUL_I32] = "__mulsi3";
38 Names[RTLIB::MUL_I64] = "__muldi3";
39 Names[RTLIB::SDIV_I32] = "__divsi3";
40 Names[RTLIB::SDIV_I64] = "__divdi3";
41 Names[RTLIB::UDIV_I32] = "__udivsi3";
42 Names[RTLIB::UDIV_I64] = "__udivdi3";
43 Names[RTLIB::SREM_I32] = "__modsi3";
44 Names[RTLIB::SREM_I64] = "__moddi3";
45 Names[RTLIB::UREM_I32] = "__umodsi3";
46 Names[RTLIB::UREM_I64] = "__umoddi3";
47 Names[RTLIB::NEG_I32] = "__negsi2";
48 Names[RTLIB::NEG_I64] = "__negdi2";
49 Names[RTLIB::ADD_F32] = "__addsf3";
50 Names[RTLIB::ADD_F64] = "__adddf3";
51 Names[RTLIB::ADD_F80] = "__addxf3";
52 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
53 Names[RTLIB::SUB_F32] = "__subsf3";
54 Names[RTLIB::SUB_F64] = "__subdf3";
55 Names[RTLIB::SUB_F80] = "__subxf3";
56 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
57 Names[RTLIB::MUL_F32] = "__mulsf3";
58 Names[RTLIB::MUL_F64] = "__muldf3";
59 Names[RTLIB::MUL_F80] = "__mulxf3";
60 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
61 Names[RTLIB::DIV_F32] = "__divsf3";
62 Names[RTLIB::DIV_F64] = "__divdf3";
63 Names[RTLIB::DIV_F80] = "__divxf3";
64 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
65 Names[RTLIB::REM_F32] = "fmodf";
66 Names[RTLIB::REM_F64] = "fmod";
67 Names[RTLIB::REM_F80] = "fmodl";
68 Names[RTLIB::REM_PPCF128] = "fmodl";
69 Names[RTLIB::POWI_F32] = "__powisf2";
70 Names[RTLIB::POWI_F64] = "__powidf2";
71 Names[RTLIB::POWI_F80] = "__powixf2";
72 Names[RTLIB::POWI_PPCF128] = "__powitf2";
73 Names[RTLIB::SQRT_F32] = "sqrtf";
74 Names[RTLIB::SQRT_F64] = "sqrt";
75 Names[RTLIB::SQRT_F80] = "sqrtl";
76 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
77 Names[RTLIB::SIN_F32] = "sinf";
78 Names[RTLIB::SIN_F64] = "sin";
79 Names[RTLIB::SIN_F80] = "sinl";
80 Names[RTLIB::SIN_PPCF128] = "sinl";
81 Names[RTLIB::COS_F32] = "cosf";
82 Names[RTLIB::COS_F64] = "cos";
83 Names[RTLIB::COS_F80] = "cosl";
84 Names[RTLIB::COS_PPCF128] = "cosl";
85 Names[RTLIB::POW_F32] = "powf";
86 Names[RTLIB::POW_F64] = "pow";
87 Names[RTLIB::POW_F80] = "powl";
88 Names[RTLIB::POW_PPCF128] = "powl";
89 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
90 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
91 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
92 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
93 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
94 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
95 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
96 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
97 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
98 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
99 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
100 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
101 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
102 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
103 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
104 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
105 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
106 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
107 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
108 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
109 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
110 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
111 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
112 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
113 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
114 Names[RTLIB::OEQ_F32] = "__eqsf2";
115 Names[RTLIB::OEQ_F64] = "__eqdf2";
116 Names[RTLIB::UNE_F32] = "__nesf2";
117 Names[RTLIB::UNE_F64] = "__nedf2";
118 Names[RTLIB::OGE_F32] = "__gesf2";
119 Names[RTLIB::OGE_F64] = "__gedf2";
120 Names[RTLIB::OLT_F32] = "__ltsf2";
121 Names[RTLIB::OLT_F64] = "__ltdf2";
122 Names[RTLIB::OLE_F32] = "__lesf2";
123 Names[RTLIB::OLE_F64] = "__ledf2";
124 Names[RTLIB::OGT_F32] = "__gtsf2";
125 Names[RTLIB::OGT_F64] = "__gtdf2";
126 Names[RTLIB::UO_F32] = "__unordsf2";
127 Names[RTLIB::UO_F64] = "__unorddf2";
128 Names[RTLIB::O_F32] = "__unordsf2";
129 Names[RTLIB::O_F64] = "__unorddf2";
132 /// InitCmpLibcallCCs - Set default comparison libcall CC.
134 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
135 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
136 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
137 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
138 CCs[RTLIB::UNE_F32] = ISD::SETNE;
139 CCs[RTLIB::UNE_F64] = ISD::SETNE;
140 CCs[RTLIB::OGE_F32] = ISD::SETGE;
141 CCs[RTLIB::OGE_F64] = ISD::SETGE;
142 CCs[RTLIB::OLT_F32] = ISD::SETLT;
143 CCs[RTLIB::OLT_F64] = ISD::SETLT;
144 CCs[RTLIB::OLE_F32] = ISD::SETLE;
145 CCs[RTLIB::OLE_F64] = ISD::SETLE;
146 CCs[RTLIB::OGT_F32] = ISD::SETGT;
147 CCs[RTLIB::OGT_F64] = ISD::SETGT;
148 CCs[RTLIB::UO_F32] = ISD::SETNE;
149 CCs[RTLIB::UO_F64] = ISD::SETNE;
150 CCs[RTLIB::O_F32] = ISD::SETEQ;
151 CCs[RTLIB::O_F64] = ISD::SETEQ;
154 TargetLowering::TargetLowering(TargetMachine &tm)
155 : TM(tm), TD(TM.getTargetData()) {
156 assert(ISD::BUILTIN_OP_END <= 156 &&
157 "Fixed size array in TargetLowering is not large enough!");
158 // All operations default to being supported.
159 memset(OpActions, 0, sizeof(OpActions));
160 memset(LoadXActions, 0, sizeof(LoadXActions));
161 memset(&StoreXActions, 0, sizeof(StoreXActions));
162 memset(&IndexedModeActions, 0, sizeof(IndexedModeActions));
163 memset(&ConvertActions, 0, sizeof(ConvertActions));
165 // Set default actions for various operations.
166 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
167 // Default all indexed load / store to expand.
168 for (unsigned IM = (unsigned)ISD::PRE_INC;
169 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
170 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
171 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
174 // These operations default to expand.
175 setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand);
178 IsLittleEndian = TD->isLittleEndian();
179 UsesGlobalOffsetTable = false;
180 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
181 ShiftAmtHandling = Undefined;
182 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
183 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
184 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
185 allowUnalignedMemoryAccesses = false;
186 UseUnderscoreSetJmp = false;
187 UseUnderscoreLongJmp = false;
188 SelectIsExpensive = false;
189 IntDivIsCheap = false;
190 Pow2DivIsCheap = false;
191 StackPointerRegisterToSaveRestore = 0;
192 ExceptionPointerRegister = 0;
193 ExceptionSelectorRegister = 0;
194 SetCCResultContents = UndefinedSetCCResult;
195 SchedPreferenceInfo = SchedulingForLatency;
197 JumpBufAlignment = 0;
198 IfCvtBlockSizeLimit = 2;
200 InitLibcallNames(LibcallRoutineNames);
201 InitCmpLibcallCCs(CmpLibcallCCs);
203 // Tell Legalize whether the assembler supports DEBUG_LOC.
204 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile())
205 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
208 TargetLowering::~TargetLowering() {}
211 SDOperand TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
212 assert(getSubtarget() && "Subtarget not defined");
213 SDOperand ChainOp = Op.getOperand(0);
214 SDOperand DestOp = Op.getOperand(1);
215 SDOperand SourceOp = Op.getOperand(2);
216 SDOperand CountOp = Op.getOperand(3);
217 SDOperand AlignOp = Op.getOperand(4);
218 SDOperand AlwaysInlineOp = Op.getOperand(5);
220 bool AlwaysInline = (bool)cast<ConstantSDNode>(AlwaysInlineOp)->getValue();
221 unsigned Align = (unsigned)cast<ConstantSDNode>(AlignOp)->getValue();
222 if (Align == 0) Align = 1;
224 // If size is unknown, call memcpy.
225 ConstantSDNode *I = dyn_cast<ConstantSDNode>(CountOp);
227 assert(!AlwaysInline && "Cannot inline copy of unknown size");
228 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG);
231 // If not DWORD aligned or if size is more than threshold, then call memcpy.
232 // The libc version is likely to be faster for the following cases. It can
233 // use the address value and run time information about the CPU.
234 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster
235 unsigned Size = I->getValue();
237 (Size <= getSubtarget()->getMaxInlineSizeThreshold() &&
239 return LowerMEMCPYInline(ChainOp, DestOp, SourceOp, Size, Align, DAG);
240 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG);
244 SDOperand TargetLowering::LowerMEMCPYCall(SDOperand Chain,
249 MVT::ValueType IntPtr = getPointerTy();
250 TargetLowering::ArgListTy Args;
251 TargetLowering::ArgListEntry Entry;
252 Entry.Ty = getTargetData()->getIntPtrType();
253 Entry.Node = Dest; Args.push_back(Entry);
254 Entry.Node = Source; Args.push_back(Entry);
255 Entry.Node = Count; Args.push_back(Entry);
256 std::pair<SDOperand,SDOperand> CallResult =
257 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
258 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
259 return CallResult.second;
263 /// computeRegisterProperties - Once all of the register classes are added,
264 /// this allows us to compute derived properties we expose.
265 void TargetLowering::computeRegisterProperties() {
266 assert(MVT::LAST_VALUETYPE <= 32 &&
267 "Too many value types for ValueTypeActions to hold!");
269 // Everything defaults to needing one register.
270 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
271 NumRegistersForVT[i] = 1;
272 RegisterTypeForVT[i] = TransformToType[i] = i;
274 // ...except isVoid, which doesn't need any registers.
275 NumRegistersForVT[MVT::isVoid] = 0;
277 // Find the largest integer register class.
278 unsigned LargestIntReg = MVT::i128;
279 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
280 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
282 // Every integer value type larger than this largest register takes twice as
283 // many registers to represent as the previous ValueType.
284 for (MVT::ValueType ExpandedReg = LargestIntReg + 1;
285 MVT::isInteger(ExpandedReg); ++ExpandedReg) {
286 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
287 RegisterTypeForVT[ExpandedReg] = LargestIntReg;
288 TransformToType[ExpandedReg] = ExpandedReg - 1;
289 ValueTypeActions.setTypeAction(ExpandedReg, Expand);
292 // Inspect all of the ValueType's smaller than the largest integer
293 // register to see which ones need promotion.
294 MVT::ValueType LegalIntReg = LargestIntReg;
295 for (MVT::ValueType IntReg = LargestIntReg - 1;
296 IntReg >= MVT::i1; --IntReg) {
297 if (isTypeLegal(IntReg)) {
298 LegalIntReg = IntReg;
300 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg;
301 ValueTypeActions.setTypeAction(IntReg, Promote);
305 // ppcf128 type is really two f64's.
306 if (!isTypeLegal(MVT::ppcf128)) {
307 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
308 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
309 TransformToType[MVT::ppcf128] = MVT::f64;
310 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
313 // Decide how to handle f64. If the target does not have native f64 support,
314 // expand it to i64 and we will be generating soft float library calls.
315 if (!isTypeLegal(MVT::f64)) {
316 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
317 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
318 TransformToType[MVT::f64] = MVT::i64;
319 ValueTypeActions.setTypeAction(MVT::f64, Expand);
322 // Decide how to handle f32. If the target does not have native support for
323 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
324 if (!isTypeLegal(MVT::f32)) {
325 if (isTypeLegal(MVT::f64)) {
326 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
327 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
328 TransformToType[MVT::f32] = MVT::f64;
329 ValueTypeActions.setTypeAction(MVT::f32, Promote);
331 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
332 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
333 TransformToType[MVT::f32] = MVT::i32;
334 ValueTypeActions.setTypeAction(MVT::f32, Expand);
338 // Loop over all of the vector value types to see which need transformations.
339 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE;
340 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
341 if (!isTypeLegal(i)) {
342 MVT::ValueType IntermediateVT, RegisterVT;
343 unsigned NumIntermediates;
344 NumRegistersForVT[i] =
345 getVectorTypeBreakdown(i,
346 IntermediateVT, NumIntermediates,
348 RegisterTypeForVT[i] = RegisterVT;
349 TransformToType[i] = MVT::Other; // this isn't actually used
350 ValueTypeActions.setTypeAction(i, Expand);
355 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
359 /// getVectorTypeBreakdown - Vector types are broken down into some number of
360 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
361 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
362 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
364 /// This method returns the number of registers needed, and the VT for each
365 /// register. It also returns the VT and quantity of the intermediate values
366 /// before they are promoted/expanded.
368 unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
369 MVT::ValueType &IntermediateVT,
370 unsigned &NumIntermediates,
371 MVT::ValueType &RegisterVT) const {
372 // Figure out the right, legal destination reg to copy into.
373 unsigned NumElts = MVT::getVectorNumElements(VT);
374 MVT::ValueType EltTy = MVT::getVectorElementType(VT);
376 unsigned NumVectorRegs = 1;
378 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
379 // could break down into LHS/RHS like LegalizeDAG does.
380 if (!isPowerOf2_32(NumElts)) {
381 NumVectorRegs = NumElts;
385 // Divide the input until we get to a supported size. This will always
386 // end with a scalar if the target doesn't support vectors.
387 while (NumElts > 1 &&
388 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
393 NumIntermediates = NumVectorRegs;
395 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts);
396 if (!isTypeLegal(NewVT))
398 IntermediateVT = NewVT;
400 MVT::ValueType DestVT = getTypeToTransformTo(NewVT);
402 if (DestVT < NewVT) {
403 // Value is expanded, e.g. i64 -> i16.
404 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT));
406 // Otherwise, promotion or legal types use the same number of registers as
407 // the vector decimated to the appropriate level.
408 return NumVectorRegs;
414 SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
415 SelectionDAG &DAG) const {
416 if (usesGlobalOffsetTable())
417 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
421 //===----------------------------------------------------------------------===//
422 // Optimization Methods
423 //===----------------------------------------------------------------------===//
425 /// ShrinkDemandedConstant - Check to see if the specified operand of the
426 /// specified instruction is a constant integer. If so, check to see if there
427 /// are any bits set in the constant that are not demanded. If so, shrink the
428 /// constant and return true.
429 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
431 // FIXME: ISD::SELECT, ISD::SELECT_CC
432 switch(Op.getOpcode()) {
437 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
438 if ((~Demanded & C->getValue()) != 0) {
439 MVT::ValueType VT = Op.getValueType();
440 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
441 DAG.getConstant(Demanded & C->getValue(),
443 return CombineTo(Op, New);
450 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
451 /// DemandedMask bits of the result of Op are ever used downstream. If we can
452 /// use this information to simplify Op, create a new simplified DAG node and
453 /// return true, returning the original and new nodes in Old and New. Otherwise,
454 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
455 /// the expression (used to simplify the caller). The KnownZero/One bits may
456 /// only be accurate for those bits in the DemandedMask.
457 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
460 TargetLoweringOpt &TLO,
461 unsigned Depth) const {
462 KnownZero = KnownOne = 0; // Don't know anything.
464 // The masks are not wide enough to represent this type! Should use APInt.
465 if (Op.getValueType() == MVT::i128)
468 // Other users may use these bits.
469 if (!Op.Val->hasOneUse()) {
471 // If not at the root, Just compute the KnownZero/KnownOne bits to
472 // simplify things downstream.
473 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
476 // If this is the root being simplified, allow it to have multiple uses,
477 // just set the DemandedMask to all bits.
478 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
479 } else if (DemandedMask == 0) {
480 // Not demanding any bits from Op.
481 if (Op.getOpcode() != ISD::UNDEF)
482 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
484 } else if (Depth == 6) { // Limit search depth.
488 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
489 switch (Op.getOpcode()) {
491 // We know all of the bits for a constant!
492 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
493 KnownZero = ~KnownOne & DemandedMask;
494 return false; // Don't fall through, will infinitely loop.
496 // If the RHS is a constant, check to see if the LHS would be zero without
497 // using the bits from the RHS. Below, we use knowledge about the RHS to
498 // simplify the LHS, here we're using information from the LHS to simplify
500 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
501 uint64_t LHSZero, LHSOne;
502 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask,
503 LHSZero, LHSOne, Depth+1);
504 // If the LHS already has zeros where RHSC does, this and is dead.
505 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
506 return TLO.CombineTo(Op, Op.getOperand(0));
507 // If any of the set bits in the RHS are known zero on the LHS, shrink
509 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
513 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
514 KnownOne, TLO, Depth+1))
516 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
517 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
518 KnownZero2, KnownOne2, TLO, Depth+1))
520 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
522 // If all of the demanded bits are known one on one side, return the other.
523 // These bits cannot contribute to the result of the 'and'.
524 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
525 return TLO.CombineTo(Op, Op.getOperand(0));
526 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
527 return TLO.CombineTo(Op, Op.getOperand(1));
528 // If all of the demanded bits in the inputs are known zeros, return zero.
529 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
530 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
531 // If the RHS is a constant, see if we can simplify it.
532 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
535 // Output known-1 bits are only known if set in both the LHS & RHS.
536 KnownOne &= KnownOne2;
537 // Output known-0 are known to be clear if zero in either the LHS | RHS.
538 KnownZero |= KnownZero2;
541 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
542 KnownOne, TLO, Depth+1))
544 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
545 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
546 KnownZero2, KnownOne2, TLO, Depth+1))
548 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
550 // If all of the demanded bits are known zero on one side, return the other.
551 // These bits cannot contribute to the result of the 'or'.
552 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
553 return TLO.CombineTo(Op, Op.getOperand(0));
554 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
555 return TLO.CombineTo(Op, Op.getOperand(1));
556 // If all of the potentially set bits on one side are known to be set on
557 // the other side, just use the 'other' side.
558 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
559 (DemandedMask & (~KnownZero)))
560 return TLO.CombineTo(Op, Op.getOperand(0));
561 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
562 (DemandedMask & (~KnownZero2)))
563 return TLO.CombineTo(Op, Op.getOperand(1));
564 // If the RHS is a constant, see if we can simplify it.
565 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
568 // Output known-0 bits are only known if clear in both the LHS & RHS.
569 KnownZero &= KnownZero2;
570 // Output known-1 are known to be set if set in either the LHS | RHS.
571 KnownOne |= KnownOne2;
574 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
575 KnownOne, TLO, Depth+1))
577 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
578 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
579 KnownOne2, TLO, Depth+1))
581 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
583 // If all of the demanded bits are known zero on one side, return the other.
584 // These bits cannot contribute to the result of the 'xor'.
585 if ((DemandedMask & KnownZero) == DemandedMask)
586 return TLO.CombineTo(Op, Op.getOperand(0));
587 if ((DemandedMask & KnownZero2) == DemandedMask)
588 return TLO.CombineTo(Op, Op.getOperand(1));
590 // If all of the unknown bits are known to be zero on one side or the other
591 // (but not both) turn this into an *inclusive* or.
592 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
593 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0)
594 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
598 // Output known-0 bits are known if clear or set in both the LHS & RHS.
599 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
600 // Output known-1 are known to be set if set in only one of the LHS, RHS.
601 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
603 // If all of the demanded bits on one side are known, and all of the set
604 // bits on that side are also known to be set on the other side, turn this
605 // into an AND, as we know the bits will be cleared.
606 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
607 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
608 if ((KnownOne & KnownOne2) == KnownOne) {
609 MVT::ValueType VT = Op.getValueType();
610 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
611 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
616 // If the RHS is a constant, see if we can simplify it.
617 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
618 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
621 KnownZero = KnownZeroOut;
622 KnownOne = KnownOneOut;
625 // If we know the result of a setcc has the top bits zero, use this info.
626 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
627 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
630 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
631 KnownOne, TLO, Depth+1))
633 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
634 KnownOne2, TLO, Depth+1))
636 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
637 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
639 // If the operands are constants, see if we can simplify them.
640 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
643 // Only known if known in both the LHS and RHS.
644 KnownOne &= KnownOne2;
645 KnownZero &= KnownZero2;
648 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
649 KnownOne, TLO, Depth+1))
651 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
652 KnownOne2, TLO, Depth+1))
654 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
655 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
657 // If the operands are constants, see if we can simplify them.
658 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
661 // Only known if known in both the LHS and RHS.
662 KnownOne &= KnownOne2;
663 KnownZero &= KnownZero2;
666 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
667 unsigned ShAmt = SA->getValue();
668 SDOperand InOp = Op.getOperand(0);
670 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
671 // single shift. We can do this if the bottom bits (which are shifted
672 // out) are never demanded.
673 if (InOp.getOpcode() == ISD::SRL &&
674 isa<ConstantSDNode>(InOp.getOperand(1))) {
675 if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) {
676 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
677 unsigned Opc = ISD::SHL;
685 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
686 MVT::ValueType VT = Op.getValueType();
687 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
688 InOp.getOperand(0), NewSA));
692 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt,
693 KnownZero, KnownOne, TLO, Depth+1))
695 KnownZero <<= SA->getValue();
696 KnownOne <<= SA->getValue();
697 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
701 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
702 MVT::ValueType VT = Op.getValueType();
703 unsigned ShAmt = SA->getValue();
704 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
705 unsigned VTSize = MVT::getSizeInBits(VT);
706 SDOperand InOp = Op.getOperand(0);
708 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
709 // single shift. We can do this if the top bits (which are shifted out)
710 // are never demanded.
711 if (InOp.getOpcode() == ISD::SHL &&
712 isa<ConstantSDNode>(InOp.getOperand(1))) {
713 if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) {
714 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
715 unsigned Opc = ISD::SRL;
723 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
724 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
725 InOp.getOperand(0), NewSA));
729 // Compute the new bits that are at the top now.
730 if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask,
731 KnownZero, KnownOne, TLO, Depth+1))
733 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
734 KnownZero &= TypeMask;
735 KnownOne &= TypeMask;
739 uint64_t HighBits = (1ULL << ShAmt)-1;
740 HighBits <<= VTSize - ShAmt;
741 KnownZero |= HighBits; // High bits known zero.
745 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
746 MVT::ValueType VT = Op.getValueType();
747 unsigned ShAmt = SA->getValue();
749 // Compute the new bits that are at the top now.
750 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
752 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
754 // If any of the demanded bits are produced by the sign extension, we also
755 // demand the input sign bit.
756 uint64_t HighBits = (1ULL << ShAmt)-1;
757 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
758 if (HighBits & DemandedMask)
759 InDemandedMask |= MVT::getIntVTSignBit(VT);
761 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
762 KnownZero, KnownOne, TLO, Depth+1))
764 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
765 KnownZero &= TypeMask;
766 KnownOne &= TypeMask;
770 // Handle the sign bits.
771 uint64_t SignBit = MVT::getIntVTSignBit(VT);
772 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
774 // If the input sign bit is known to be zero, or if none of the top bits
775 // are demanded, turn this into an unsigned shift right.
776 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
777 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
779 } else if (KnownOne & SignBit) { // New bits are known one.
780 KnownOne |= HighBits;
784 case ISD::SIGN_EXTEND_INREG: {
785 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
787 // Sign extension. Compute the demanded bits in the result that are not
788 // present in the input.
789 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
791 // If none of the extended bits are demanded, eliminate the sextinreg.
793 return TLO.CombineTo(Op, Op.getOperand(0));
795 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
796 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
798 // Since the sign extended bits are demanded, we know that the sign
800 InputDemandedBits |= InSignBit;
802 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
803 KnownZero, KnownOne, TLO, Depth+1))
805 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
807 // If the sign bit of the input is known set or clear, then we know the
808 // top bits of the result.
810 // If the input sign bit is known zero, convert this into a zero extension.
811 if (KnownZero & InSignBit)
812 return TLO.CombineTo(Op,
813 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
815 if (KnownOne & InSignBit) { // Input sign bit known set
817 KnownZero &= ~NewBits;
818 } else { // Input sign bit unknown
819 KnownZero &= ~NewBits;
820 KnownOne &= ~NewBits;
827 MVT::ValueType VT = Op.getValueType();
828 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
829 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
834 if (ISD::isZEXTLoad(Op.Val)) {
835 LoadSDNode *LD = cast<LoadSDNode>(Op);
836 MVT::ValueType VT = LD->getLoadedVT();
837 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
841 case ISD::ZERO_EXTEND: {
842 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
844 // If none of the top bits are demanded, convert this into an any_extend.
845 uint64_t NewBits = (~InMask) & DemandedMask;
847 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
851 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
852 KnownZero, KnownOne, TLO, Depth+1))
854 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
855 KnownZero |= NewBits;
858 case ISD::SIGN_EXTEND: {
859 MVT::ValueType InVT = Op.getOperand(0).getValueType();
860 uint64_t InMask = MVT::getIntVTBitMask(InVT);
861 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
862 uint64_t NewBits = (~InMask) & DemandedMask;
864 // If none of the top bits are demanded, convert this into an any_extend.
866 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
869 // Since some of the sign extended bits are demanded, we know that the sign
871 uint64_t InDemandedBits = DemandedMask & InMask;
872 InDemandedBits |= InSignBit;
874 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
875 KnownOne, TLO, Depth+1))
878 // If the sign bit is known zero, convert this to a zero extend.
879 if (KnownZero & InSignBit)
880 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
884 // If the sign bit is known one, the top bits match.
885 if (KnownOne & InSignBit) {
887 KnownZero &= ~NewBits;
888 } else { // Otherwise, top bits aren't known.
889 KnownOne &= ~NewBits;
890 KnownZero &= ~NewBits;
894 case ISD::ANY_EXTEND: {
895 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
896 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
897 KnownZero, KnownOne, TLO, Depth+1))
899 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
902 case ISD::TRUNCATE: {
903 // Simplify the input, using demanded bit information, and compute the known
904 // zero/one bits live out.
905 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
906 KnownZero, KnownOne, TLO, Depth+1))
909 // If the input is only used by this truncate, see if we can shrink it based
910 // on the known demanded bits.
911 if (Op.getOperand(0).Val->hasOneUse()) {
912 SDOperand In = Op.getOperand(0);
913 switch (In.getOpcode()) {
916 // Shrink SRL by a constant if none of the high bits shifted in are
918 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
919 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
920 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType());
921 HighBits >>= ShAmt->getValue();
923 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) &&
924 (DemandedMask & HighBits) == 0) {
925 // None of the shifted in bits are needed. Add a truncate of the
926 // shift input, then shift it.
927 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
930 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
931 NewTrunc, In.getOperand(1)));
938 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
939 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
940 KnownZero &= OutMask;
944 case ISD::AssertZext: {
945 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
946 uint64_t InMask = MVT::getIntVTBitMask(VT);
947 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
948 KnownZero, KnownOne, TLO, Depth+1))
950 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
951 KnownZero |= ~InMask & DemandedMask;
955 // All bits are zero except the low bit.
956 KnownZero = MVT::getIntVTBitMask(Op.getValueType()) ^ 1;
958 case ISD::BIT_CONVERT:
960 // If this is an FP->Int bitcast and if the sign bit is the only thing that
961 // is demanded, turn this into a FGETSIGN.
962 if (DemandedMask == MVT::getIntVTSignBit(Op.getValueType()) &&
963 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
964 !MVT::isVector(Op.getOperand(0).getValueType())) {
965 // Only do this xform if FGETSIGN is valid or if before legalize.
966 if (!TLO.AfterLegalize ||
967 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
968 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
969 // place. We expect the SHL to be eliminated by other optimizations.
970 SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
972 unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1;
973 SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
974 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
982 case ISD::INTRINSIC_WO_CHAIN:
983 case ISD::INTRINSIC_W_CHAIN:
984 case ISD::INTRINSIC_VOID:
985 // Just use ComputeMaskedBits to compute output bits.
986 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
990 // If we know the value of all of the demanded bits, return this as a
992 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
993 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
998 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
999 /// in Mask are known to be either zero or one and return them in the
1000 /// KnownZero/KnownOne bitsets.
1001 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1003 uint64_t &KnownZero,
1005 const SelectionDAG &DAG,
1006 unsigned Depth) const {
1007 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1008 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1009 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1010 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1011 "Should use MaskedValueIsZero if you don't know whether Op"
1012 " is a target node!");
1017 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1018 /// targets that want to expose additional information about sign bits to the
1020 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
1021 unsigned Depth) const {
1022 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1023 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1024 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1025 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1026 "Should use ComputeNumSignBits if you don't know whether Op"
1027 " is a target node!");
1032 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1033 /// and cc. If it is unable to simplify it, return a null SDOperand.
1035 TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
1036 ISD::CondCode Cond, bool foldBooleans,
1037 DAGCombinerInfo &DCI) const {
1038 SelectionDAG &DAG = DCI.DAG;
1040 // These setcc operations always fold.
1044 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1046 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1049 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1050 uint64_t C1 = N1C->getValue();
1051 if (isa<ConstantSDNode>(N0.Val)) {
1052 return DAG.FoldSetCC(VT, N0, N1, Cond);
1054 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1055 // equality comparison, then we're just comparing whether X itself is
1057 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1058 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1059 N0.getOperand(1).getOpcode() == ISD::Constant) {
1060 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1061 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1062 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
1063 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1064 // (srl (ctlz x), 5) == 0 -> X != 0
1065 // (srl (ctlz x), 5) != 1 -> X != 0
1068 // (srl (ctlz x), 5) != 0 -> X == 0
1069 // (srl (ctlz x), 5) == 1 -> X == 0
1072 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
1073 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
1078 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1079 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1080 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1082 // If the comparison constant has bits in the upper part, the
1083 // zero-extended value could never match.
1084 if (C1 & (~0ULL << InSize)) {
1085 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
1089 case ISD::SETEQ: return DAG.getConstant(0, VT);
1092 case ISD::SETNE: return DAG.getConstant(1, VT);
1095 // True if the sign bit of C1 is set.
1096 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT);
1099 // True if the sign bit of C1 isn't set.
1100 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT);
1106 // Otherwise, we can perform the comparison with the low bits.
1114 return DAG.getSetCC(VT, N0.getOperand(0),
1115 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
1118 break; // todo, be more careful with signed comparisons
1120 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1121 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1122 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1123 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1124 MVT::ValueType ExtDstTy = N0.getValueType();
1125 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1127 // If the extended part has any inconsistent bits, it cannot ever
1128 // compare equal. In other words, they have to be all ones or all
1131 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
1132 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1133 return DAG.getConstant(Cond == ISD::SETNE, VT);
1136 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1137 if (Op0Ty == ExtSrcTy) {
1138 ZextOp = N0.getOperand(0);
1140 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
1141 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1142 DAG.getConstant(Imm, Op0Ty));
1144 if (!DCI.isCalledByLegalizer())
1145 DCI.AddToWorklist(ZextOp.Val);
1146 // Otherwise, make this a use of a zext.
1147 return DAG.getSetCC(VT, ZextOp,
1148 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1151 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
1152 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1154 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1155 if (N0.getOpcode() == ISD::SETCC) {
1156 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
1160 // Invert the condition.
1161 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1162 CC = ISD::getSetCCInverse(CC,
1163 MVT::isInteger(N0.getOperand(0).getValueType()));
1164 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
1167 if ((N0.getOpcode() == ISD::XOR ||
1168 (N0.getOpcode() == ISD::AND &&
1169 N0.getOperand(0).getOpcode() == ISD::XOR &&
1170 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1171 isa<ConstantSDNode>(N0.getOperand(1)) &&
1172 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
1173 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1174 // can only do this if the top bits are known zero.
1175 if (DAG.MaskedValueIsZero(N0,
1176 MVT::getIntVTBitMask(N0.getValueType())-1)){
1177 // Okay, get the un-inverted input value.
1179 if (N0.getOpcode() == ISD::XOR)
1180 Val = N0.getOperand(0);
1182 assert(N0.getOpcode() == ISD::AND &&
1183 N0.getOperand(0).getOpcode() == ISD::XOR);
1184 // ((X^1)&1)^1 -> X & 1
1185 Val = DAG.getNode(ISD::AND, N0.getValueType(),
1186 N0.getOperand(0).getOperand(0),
1189 return DAG.getSetCC(VT, Val, N1,
1190 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1195 uint64_t MinVal, MaxVal;
1196 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1197 if (ISD::isSignedIntSetCC(Cond)) {
1198 MinVal = 1ULL << (OperandBitSize-1);
1199 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
1200 MaxVal = ~0ULL >> (65-OperandBitSize);
1205 MaxVal = ~0ULL >> (64-OperandBitSize);
1208 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1209 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1210 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1211 --C1; // X >= C0 --> X > (C0-1)
1212 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1213 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1216 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1217 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1218 ++C1; // X <= C0 --> X < (C0+1)
1219 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1220 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1223 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1224 return DAG.getConstant(0, VT); // X < MIN --> false
1225 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1226 return DAG.getConstant(1, VT); // X >= MIN --> true
1227 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1228 return DAG.getConstant(0, VT); // X > MAX --> false
1229 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1230 return DAG.getConstant(1, VT); // X <= MAX --> true
1232 // Canonicalize setgt X, Min --> setne X, Min
1233 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1234 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1235 // Canonicalize setlt X, Max --> setne X, Max
1236 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1237 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1239 // If we have setult X, 1, turn it into seteq X, 0
1240 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1241 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1243 // If we have setugt X, Max-1, turn it into seteq X, Max
1244 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1245 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1248 // If we have "setcc X, C0", check to see if we can shrink the immediate
1251 // SETUGT X, SINTMAX -> SETLT X, 0
1252 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1253 C1 == (~0ULL >> (65-OperandBitSize)))
1254 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1257 // FIXME: Implement the rest of these.
1259 // Fold bit comparisons when we can.
1260 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1261 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1262 if (ConstantSDNode *AndRHS =
1263 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1264 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1265 // Perform the xform if the AND RHS is a single bit.
1266 if (isPowerOf2_64(AndRHS->getValue())) {
1267 return DAG.getNode(ISD::SRL, VT, N0,
1268 DAG.getConstant(Log2_64(AndRHS->getValue()),
1269 getShiftAmountTy()));
1271 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1272 // (X & 8) == 8 --> (X & 8) >> 3
1273 // Perform the xform if C1 is a single bit.
1274 if (isPowerOf2_64(C1)) {
1275 return DAG.getNode(ISD::SRL, VT, N0,
1276 DAG.getConstant(Log2_64(C1), getShiftAmountTy()));
1281 } else if (isa<ConstantSDNode>(N0.Val)) {
1282 // Ensure that the constant occurs on the RHS.
1283 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1286 if (isa<ConstantFPSDNode>(N0.Val)) {
1287 // Constant fold or commute setcc.
1288 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
1289 if (O.Val) return O;
1290 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) {
1291 // If the RHS of an FP comparison is a constant, simplify it away in
1293 if (CFP->getValueAPF().isNaN()) {
1294 // If an operand is known to be a nan, we can fold it.
1295 switch (ISD::getUnorderedFlavor(Cond)) {
1296 default: assert(0 && "Unknown flavor!");
1297 case 0: // Known false.
1298 return DAG.getConstant(0, VT);
1299 case 1: // Known true.
1300 return DAG.getConstant(1, VT);
1301 case 2: // Undefined.
1302 return DAG.getNode(ISD::UNDEF, VT);
1306 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1307 // constant if knowing that the operand is non-nan is enough. We prefer to
1308 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1310 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1311 return DAG.getSetCC(VT, N0, N0, Cond);
1315 // We can always fold X == X for integer setcc's.
1316 if (MVT::isInteger(N0.getValueType()))
1317 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1318 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1319 if (UOF == 2) // FP operators that are undefined on NaNs.
1320 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1321 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1322 return DAG.getConstant(UOF, VT);
1323 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1324 // if it is not already.
1325 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1326 if (NewCond != Cond)
1327 return DAG.getSetCC(VT, N0, N1, NewCond);
1330 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1331 MVT::isInteger(N0.getValueType())) {
1332 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1333 N0.getOpcode() == ISD::XOR) {
1334 // Simplify (X+Y) == (X+Z) --> Y == Z
1335 if (N0.getOpcode() == N1.getOpcode()) {
1336 if (N0.getOperand(0) == N1.getOperand(0))
1337 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1338 if (N0.getOperand(1) == N1.getOperand(1))
1339 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1340 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1341 // If X op Y == Y op X, try other combinations.
1342 if (N0.getOperand(0) == N1.getOperand(1))
1343 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1344 if (N0.getOperand(1) == N1.getOperand(0))
1345 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
1349 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1350 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1351 // Turn (X+C1) == C2 --> X == C2-C1
1352 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
1353 return DAG.getSetCC(VT, N0.getOperand(0),
1354 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
1355 N0.getValueType()), Cond);
1358 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1359 if (N0.getOpcode() == ISD::XOR)
1360 // If we know that all of the inverted bits are zero, don't bother
1361 // performing the inversion.
1362 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
1363 return DAG.getSetCC(VT, N0.getOperand(0),
1364 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
1365 N0.getValueType()), Cond);
1368 // Turn (C1-X) == C2 --> X == C1-C2
1369 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1370 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
1371 return DAG.getSetCC(VT, N0.getOperand(1),
1372 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
1373 N0.getValueType()), Cond);
1378 // Simplify (X+Z) == X --> Z == 0
1379 if (N0.getOperand(0) == N1)
1380 return DAG.getSetCC(VT, N0.getOperand(1),
1381 DAG.getConstant(0, N0.getValueType()), Cond);
1382 if (N0.getOperand(1) == N1) {
1383 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1384 return DAG.getSetCC(VT, N0.getOperand(0),
1385 DAG.getConstant(0, N0.getValueType()), Cond);
1386 else if (N0.Val->hasOneUse()) {
1387 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1388 // (Z-X) == X --> Z == X<<1
1389 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1391 DAG.getConstant(1, getShiftAmountTy()));
1392 if (!DCI.isCalledByLegalizer())
1393 DCI.AddToWorklist(SH.Val);
1394 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1399 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1400 N1.getOpcode() == ISD::XOR) {
1401 // Simplify X == (X+Z) --> Z == 0
1402 if (N1.getOperand(0) == N0) {
1403 return DAG.getSetCC(VT, N1.getOperand(1),
1404 DAG.getConstant(0, N1.getValueType()), Cond);
1405 } else if (N1.getOperand(1) == N0) {
1406 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1407 return DAG.getSetCC(VT, N1.getOperand(0),
1408 DAG.getConstant(0, N1.getValueType()), Cond);
1409 } else if (N1.Val->hasOneUse()) {
1410 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1411 // X == (Z-X) --> X<<1 == Z
1412 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1413 DAG.getConstant(1, getShiftAmountTy()));
1414 if (!DCI.isCalledByLegalizer())
1415 DCI.AddToWorklist(SH.Val);
1416 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1422 // Fold away ALL boolean setcc's.
1424 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1426 default: assert(0 && "Unknown integer setcc!");
1427 case ISD::SETEQ: // X == Y -> (X^Y)^1
1428 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1429 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1430 if (!DCI.isCalledByLegalizer())
1431 DCI.AddToWorklist(Temp.Val);
1433 case ISD::SETNE: // X != Y --> (X^Y)
1434 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1436 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1437 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1438 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1439 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1440 if (!DCI.isCalledByLegalizer())
1441 DCI.AddToWorklist(Temp.Val);
1443 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1444 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1445 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1446 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1447 if (!DCI.isCalledByLegalizer())
1448 DCI.AddToWorklist(Temp.Val);
1450 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1451 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1452 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1453 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1454 if (!DCI.isCalledByLegalizer())
1455 DCI.AddToWorklist(Temp.Val);
1457 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1458 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1459 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1460 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1463 if (VT != MVT::i1) {
1464 if (!DCI.isCalledByLegalizer())
1465 DCI.AddToWorklist(N0.Val);
1466 // FIXME: If running after legalize, we probably can't do this.
1467 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1472 // Could not fold it.
1476 SDOperand TargetLowering::
1477 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1478 // Default implementation: no optimization.
1482 //===----------------------------------------------------------------------===//
1483 // Inline Assembler Implementation Methods
1484 //===----------------------------------------------------------------------===//
1486 TargetLowering::ConstraintType
1487 TargetLowering::getConstraintType(const std::string &Constraint) const {
1488 // FIXME: lots more standard ones to handle.
1489 if (Constraint.size() == 1) {
1490 switch (Constraint[0]) {
1492 case 'r': return C_RegisterClass;
1494 case 'o': // offsetable
1495 case 'V': // not offsetable
1497 case 'i': // Simple Integer or Relocatable Constant
1498 case 'n': // Simple Integer
1499 case 's': // Relocatable Constant
1500 case 'X': // Allow ANY value.
1501 case 'I': // Target registers.
1513 if (Constraint.size() > 1 && Constraint[0] == '{' &&
1514 Constraint[Constraint.size()-1] == '}')
1519 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1520 /// vector. If it is invalid, don't add anything to Ops.
1521 void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
1522 char ConstraintLetter,
1523 std::vector<SDOperand> &Ops,
1524 SelectionDAG &DAG) {
1525 switch (ConstraintLetter) {
1527 case 'X': // Allows any operand; labels (basic block) use this.
1528 if (Op.getOpcode() == ISD::BasicBlock) {
1533 case 'i': // Simple Integer or Relocatable Constant
1534 case 'n': // Simple Integer
1535 case 's': { // Relocatable Constant
1536 // These operands are interested in values of the form (GV+C), where C may
1537 // be folded in as an offset of GV, or it may be explicitly added. Also, it
1538 // is possible and fine if either GV or C are missing.
1539 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1540 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
1542 // If we have "(add GV, C)", pull out GV/C
1543 if (Op.getOpcode() == ISD::ADD) {
1544 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1545 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
1546 if (C == 0 || GA == 0) {
1547 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1548 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
1550 if (C == 0 || GA == 0)
1554 // If we find a valid operand, map to the TargetXXX version so that the
1555 // value itself doesn't get selected.
1556 if (GA) { // Either &GV or &GV+C
1557 if (ConstraintLetter != 'n') {
1558 int64_t Offs = GA->getOffset();
1559 if (C) Offs += C->getValue();
1560 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
1561 Op.getValueType(), Offs));
1565 if (C) { // just C, no GV.
1566 // Simple constants are not allowed for 's'.
1567 if (ConstraintLetter != 's') {
1568 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType()));
1577 std::vector<unsigned> TargetLowering::
1578 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1579 MVT::ValueType VT) const {
1580 return std::vector<unsigned>();
1584 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1585 getRegForInlineAsmConstraint(const std::string &Constraint,
1586 MVT::ValueType VT) const {
1587 if (Constraint[0] != '{')
1588 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1589 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1591 // Remove the braces from around the name.
1592 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1594 // Figure out which register class contains this reg.
1595 const MRegisterInfo *RI = TM.getRegisterInfo();
1596 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1597 E = RI->regclass_end(); RCI != E; ++RCI) {
1598 const TargetRegisterClass *RC = *RCI;
1600 // If none of the the value types for this register class are valid, we
1601 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1602 bool isLegal = false;
1603 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1605 if (isTypeLegal(*I)) {
1611 if (!isLegal) continue;
1613 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1615 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
1616 return std::make_pair(*I, RC);
1620 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1623 //===----------------------------------------------------------------------===//
1624 // Loop Strength Reduction hooks
1625 //===----------------------------------------------------------------------===//
1627 /// isLegalAddressingMode - Return true if the addressing mode represented
1628 /// by AM is legal for this target, for a load/store of the specified type.
1629 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
1630 const Type *Ty) const {
1631 // The default implementation of this implements a conservative RISCy, r+r and
1634 // Allows a sign-extended 16-bit immediate field.
1635 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1638 // No global is ever allowed as a base.
1642 // Only support r+r,
1644 case 0: // "r+i" or just "i", depending on HasBaseReg.
1647 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1649 // Otherwise we have r+r or r+i.
1652 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1654 // Allow 2*r as r+r.
1661 // Magic for divide replacement
1664 int64_t m; // magic number
1665 int64_t s; // shift amount
1669 uint64_t m; // magic number
1670 int64_t a; // add indicator
1671 int64_t s; // shift amount
1674 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1675 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1677 static ms magic32(int32_t d) {
1679 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
1680 const uint32_t two31 = 0x80000000U;
1684 t = two31 + ((uint32_t)d >> 31);
1685 anc = t - 1 - t%ad; // absolute value of nc
1686 p = 31; // initialize p
1687 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
1688 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1689 q2 = two31/ad; // initialize q2 = 2p/abs(d)
1690 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
1693 q1 = 2*q1; // update q1 = 2p/abs(nc)
1694 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1695 if (r1 >= anc) { // must be unsigned comparison
1699 q2 = 2*q2; // update q2 = 2p/abs(d)
1700 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1701 if (r2 >= ad) { // must be unsigned comparison
1706 } while (q1 < delta || (q1 == delta && r1 == 0));
1708 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
1709 if (d < 0) mag.m = -mag.m; // resulting magic number
1710 mag.s = p - 32; // resulting shift
1714 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1715 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1716 static mu magicu32(uint32_t d) {
1718 uint32_t nc, delta, q1, r1, q2, r2;
1720 magu.a = 0; // initialize "add" indicator
1722 p = 31; // initialize p
1723 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
1724 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
1725 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
1726 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
1729 if (r1 >= nc - r1 ) {
1730 q1 = 2*q1 + 1; // update q1
1731 r1 = 2*r1 - nc; // update r1
1734 q1 = 2*q1; // update q1
1735 r1 = 2*r1; // update r1
1737 if (r2 + 1 >= d - r2) {
1738 if (q2 >= 0x7FFFFFFF) magu.a = 1;
1739 q2 = 2*q2 + 1; // update q2
1740 r2 = 2*r2 + 1 - d; // update r2
1743 if (q2 >= 0x80000000) magu.a = 1;
1744 q2 = 2*q2; // update q2
1745 r2 = 2*r2 + 1; // update r2
1748 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
1749 magu.m = q2 + 1; // resulting magic number
1750 magu.s = p - 32; // resulting shift
1754 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1755 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1757 static ms magic64(int64_t d) {
1759 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
1760 const uint64_t two63 = 9223372036854775808ULL; // 2^63
1763 ad = d >= 0 ? d : -d;
1764 t = two63 + ((uint64_t)d >> 63);
1765 anc = t - 1 - t%ad; // absolute value of nc
1766 p = 63; // initialize p
1767 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
1768 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1769 q2 = two63/ad; // initialize q2 = 2p/abs(d)
1770 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
1773 q1 = 2*q1; // update q1 = 2p/abs(nc)
1774 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1775 if (r1 >= anc) { // must be unsigned comparison
1779 q2 = 2*q2; // update q2 = 2p/abs(d)
1780 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1781 if (r2 >= ad) { // must be unsigned comparison
1786 } while (q1 < delta || (q1 == delta && r1 == 0));
1789 if (d < 0) mag.m = -mag.m; // resulting magic number
1790 mag.s = p - 64; // resulting shift
1794 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1795 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1796 static mu magicu64(uint64_t d)
1799 uint64_t nc, delta, q1, r1, q2, r2;
1801 magu.a = 0; // initialize "add" indicator
1803 p = 63; // initialize p
1804 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
1805 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
1806 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
1807 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
1810 if (r1 >= nc - r1 ) {
1811 q1 = 2*q1 + 1; // update q1
1812 r1 = 2*r1 - nc; // update r1
1815 q1 = 2*q1; // update q1
1816 r1 = 2*r1; // update r1
1818 if (r2 + 1 >= d - r2) {
1819 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
1820 q2 = 2*q2 + 1; // update q2
1821 r2 = 2*r2 + 1 - d; // update r2
1824 if (q2 >= 0x8000000000000000ull) magu.a = 1;
1825 q2 = 2*q2; // update q2
1826 r2 = 2*r2 + 1; // update r2
1829 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
1830 magu.m = q2 + 1; // resulting magic number
1831 magu.s = p - 64; // resulting shift
1835 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
1836 /// return a DAG expression to select that will generate the same value by
1837 /// multiplying by a magic number. See:
1838 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1839 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
1840 std::vector<SDNode*>* Created) const {
1841 MVT::ValueType VT = N->getValueType(0);
1843 // Check to see if we can do this.
1844 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1845 return SDOperand(); // BuildSDIV only operates on i32 or i64
1847 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
1848 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
1850 // Multiply the numerator (operand 0) by the magic value
1852 if (isOperationLegal(ISD::MULHS, VT))
1853 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
1854 DAG.getConstant(magics.m, VT));
1855 else if (isOperationLegal(ISD::SMUL_LOHI, VT))
1856 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
1858 DAG.getConstant(magics.m, VT)).Val, 1);
1860 return SDOperand(); // No mulhs or equvialent
1861 // If d > 0 and m < 0, add the numerator
1862 if (d > 0 && magics.m < 0) {
1863 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
1865 Created->push_back(Q.Val);
1867 // If d < 0 and m > 0, subtract the numerator.
1868 if (d < 0 && magics.m > 0) {
1869 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
1871 Created->push_back(Q.Val);
1873 // Shift right algebraic if shift value is nonzero
1875 Q = DAG.getNode(ISD::SRA, VT, Q,
1876 DAG.getConstant(magics.s, getShiftAmountTy()));
1878 Created->push_back(Q.Val);
1880 // Extract the sign bit and add it to the quotient
1882 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
1883 getShiftAmountTy()));
1885 Created->push_back(T.Val);
1886 return DAG.getNode(ISD::ADD, VT, Q, T);
1889 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
1890 /// return a DAG expression to select that will generate the same value by
1891 /// multiplying by a magic number. See:
1892 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1893 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
1894 std::vector<SDNode*>* Created) const {
1895 MVT::ValueType VT = N->getValueType(0);
1897 // Check to see if we can do this.
1898 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1899 return SDOperand(); // BuildUDIV only operates on i32 or i64
1901 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1902 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
1904 // Multiply the numerator (operand 0) by the magic value
1906 if (isOperationLegal(ISD::MULHU, VT))
1907 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
1908 DAG.getConstant(magics.m, VT));
1909 else if (isOperationLegal(ISD::UMUL_LOHI, VT))
1910 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
1912 DAG.getConstant(magics.m, VT)).Val, 1);
1914 return SDOperand(); // No mulhu or equvialent
1916 Created->push_back(Q.Val);
1918 if (magics.a == 0) {
1919 return DAG.getNode(ISD::SRL, VT, Q,
1920 DAG.getConstant(magics.s, getShiftAmountTy()));
1922 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
1924 Created->push_back(NPQ.Val);
1925 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
1926 DAG.getConstant(1, getShiftAmountTy()));
1928 Created->push_back(NPQ.Val);
1929 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
1931 Created->push_back(NPQ.Val);
1932 return DAG.getNode(ISD::SRL, VT, NPQ,
1933 DAG.getConstant(magics.s-1, getShiftAmountTy()));